diff --git a/driver/rfic/build.sh b/driver/rfic/build.sh new file mode 100644 index 0000000..11a0e20 --- /dev/null +++ b/driver/rfic/build.sh @@ -0,0 +1,12 @@ +set -e + +# git submodule init +# git submodule update --remote --merge --recursive + +# git clean -dxf +# git fetch +# git checkout DEV +# git pull + +make clr +make all \ No newline at end of file diff --git a/driver/rfic/doc/SL-UCP-000507-UCP4008 JESD Module User Guide V3.2.docx b/driver/rfic/doc/SL-UCP-000507-UCP4008 JESD Module User Guide V3.2.docx new file mode 100644 index 0000000..083f5aa Binary files /dev/null and b/driver/rfic/doc/SL-UCP-000507-UCP4008 JESD Module User Guide V3.2.docx differ diff --git a/driver/rfic/makefile b/driver/rfic/makefile new file mode 100644 index 0000000..a8d7296 --- /dev/null +++ b/driver/rfic/makefile @@ -0,0 +1,17 @@ +all: + rm -rf ./rf/ucp + rm -rf ./ucp/*.a + mkdir -p ./rf/ucp + mkdir -p ./rf/ucp/inc + make -C ./ucp + cp ./ucp/base/inc/ucp_param.h ./ucp/base/inc/ucp_jesd_gpio.h ./ucp/base/inc/ucp_reg_io.h ./rf/api/inc + cp ./ucp/api/inc/ucp_api_jesd.h ./rf/ucp/inc + cp ./ucp/libjesd.a ./rf/ucp/ + make -C ./rf + +clean: + make -C ./rf clean + +clr: + make -C ./rf clr + make -C ./ucp clean \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/LICENSE.pdf b/driver/rfic/rf/adrv9025/c_src/LICENSE.pdf new file mode 100644 index 0000000..90e370f Binary files /dev/null and b/driver/rfic/rf/adrv9025/c_src/LICENSE.pdf differ diff --git a/driver/rfic/rf/adrv9025/c_src/app/example/adi_ad9528Lib.c b/driver/rfic/rf/adrv9025/c_src/app/example/adi_ad9528Lib.c new file mode 100644 index 0000000..a59702a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/example/adi_ad9528Lib.c @@ -0,0 +1,165 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_api_clockGen.c +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-03-04 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#include +#include +#include +#include +#include "adi_ad9528.h" +#include "adi_ad9528_hal.h" +#include "adi_ad9528_utilities.h" +#include "adi_commonLib.h" +#include "ucp_jesd_gpio.h" +#include "ucp_rfic_gpio.h" + +#define AD9528_CHIP_ID 0x003 + +static adi_ad9528_Init_t ad9528InitInst; +static adi_ad9528_Device_t ad9528Device; +static int32_t recoveryAct = ADI_COMMON_ACT_ERR_RESET_FULL; + +static adi_ad9528_ClockFrequencySettings_t clockFrequencies = { + 122880000, //uint32_t vcxoFrequency_Hz; + 30720000, //uint32_t refAFrequency_Hz; + //uint32_t outputClock_Hz[ADI_AD9528_NUM_OUTPUT_CHANNELS]; + { + 122880000, // channels 0 ADRV9026 DEVCLK 122.88M + 960000, // channels 1 ADRV9026 SYSREF 7.68M + 960000, // channels 2 UCP_TX SYSREF 7.68M + 122880000, // channels 3 UCP_TX DEVCLK 122.88M + 0, // channels 4 + 960000, // channels 5 UCP_RX0 SYSREF 7.68M + 122880000, // channels 6 UCP_RX0 DEVCLK 122.88M + 122880000, // channels 7 UCP SYSDEV 122.88M + 960000, // channels 8 UCP_RX1 SYSREF 7.68M + 122880000, // channels 9 UCP_RX1 DEVCLK 122.88M + 0, // channels 10 + 0, // channels 11 + 0, // channels 12 + 0 // channels 13 + }, + //adi_ad9528_OutSourceSel_e outSource[ADI_AD9528_NUM_OUTPUT_CHANNELS]; + { + ADI_AD9528_CHANNEL_DIV, // channels 0 ADRV9026 DEVCLK 122.88M + ADI_AD9528_SYSREF, // channels 1 ADRV9026 SYSREF 7.68M + ADI_AD9528_SYSREF, // channels 2 UCP_TX SYSREF 7.68M + ADI_AD9528_CHANNEL_DIV, // channels 3 UCP_TX DEVCLK 122.88M + ADI_AD9528_CHANNEL_DIV, // channels 4 + ADI_AD9528_SYSREF, // channels 5 UCP_RX0 SYSREF 7.68M + ADI_AD9528_CHANNEL_DIV, // channels 6 UCP_RX0 DEVCLK 122.88M + ADI_AD9528_CHANNEL_DIV, // channels 7 UCP SYSDEV 122.88M + ADI_AD9528_SYSREF, // channels 8 UCP_RX1 SYSREF 7.68M + ADI_AD9528_CHANNEL_DIV, // channels 9 UCP_RX1 DEVCLK 122.88M + ADI_AD9528_CHANNEL_DIV, // channels 10 + ADI_AD9528_CHANNEL_DIV, // channels 11 + ADI_AD9528_CHANNEL_DIV, // channels 12 + ADI_AD9528_CHANNEL_DIV // channels 13 + } +}; + +void ucp_api_ad9528_Reset(void) +{ + ucp_jesd_gpioSet(GPIO_INDEX_9528RESET, 0); + sleep(1); + ucp_jesd_gpioSet(GPIO_INDEX_9528RESET, 1); + + memset(&ad9528Device, 0, sizeof(adi_ad9528_Device_t)); + memset(&ad9528InitInst, 0, sizeof(adi_ad9528_Init_t)); + + return; +} + +int32_t ucp_api_ad9528_Init(void) +{ + int32_t ret; + int32_t error = ADI_COMMON_HAL_OK; + uint8_t reg; + adi_ad9528_Device_t *ad9528Dev = NULL; + adi_ad9528_Init_t *ad9528Init = NULL; + adi_hal_Cfg_t *devCfg = NULL; + + /* Board Level */ + ad9528Dev = (adi_ad9528_Device_t*)&ad9528Device; + ad9528Init = (adi_ad9528_Init_t*)&ad9528InitInst; + + /* create hal layer for this motherboard daya: SPI_CHIP_SELECT_1 for ad9528*/ + ad9528Dev->common.devHalInfo = NULL; + ad9528Dev->common.devHalInfo = hal_DevHalCfgCreate((ADI_HAL_INTERFACE_SPI | \ + ADI_HAL_INTERFACE_LOG | \ + ADI_HAL_INTERFACE_HWRESET | \ + ADI_HAL_INTERFACE_TIMER), + SPI_CHIP_SELECT_1, "ad9528.txt"); + if (ad9528Dev->common.devHalInfo == NULL) + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + return ADI_HAL_SPI_FAIL; + } + + ad9528Dev->common.error.logEnable = ADI_ENABLE; + devCfg = (adi_hal_Cfg_t *)ad9528Dev->common.devHalInfo; + strcpy(devCfg->typeName, "ad9528Dev"); + error = adi_hal_PlatformSetup(ad9528Dev->common.devHalInfo, + (adi_hal_Platforms_e)ADI_UCP2_PLATFORM); + if (error != ADI_HAL_OK) + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + return ADI_HAL_SPI_FAIL; + } + + adi_ad9528_HwOpen(ad9528Dev); + adi_ad9528_SpiCfgSet(ad9528Dev, &ad9528Init->spiSettings); + + if ((recoveryAct = adi_ad9528_InitStructConfig(ad9528Dev, + &clockFrequencies, + ad9528Init)) < 0) + { + return recoveryAct; + } + + ret = adi_ad9528_Initialize(ad9528Dev, ad9528Init); + + adi_ad9528_SpiByteRead(ad9528Dev, AD9528_CHIP_ID, ®); + printf("AD9528 ID: 0x%02X\n", reg); + + reg = 0; + while (!(reg & 0x3)) { + adi_ad9528_PllLockStatusGet(ad9528Dev, ®); + sleep(1); + } + + printf("AD9528 LockStatus: 0x%02X\n", reg); + + return ret; +} + +uint8_t ucp_api_ad9528_LockStatus(void) +{ + uint8_t data; + + data = 0; + adi_ad9528_PllLockStatusGet((adi_ad9528_Device_t*)&ad9528Device, &data); + printf("status = %x\n", data); + + return data; +} + +void ucp_api_ad9528_OnePluse(uint8_t enable) +{ + adi_ad9528_SysrefRequest((adi_ad9528_Device_t*)&ad9528Device, enable); + return; +} + + diff --git a/driver/rfic/rf/adrv9025/c_src/app/example/adi_ad9528Lib.h b/driver/rfic/rf/adrv9025/c_src/app/example/adi_ad9528Lib.h new file mode 100644 index 0000000..47ed3f7 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/example/adi_ad9528Lib.h @@ -0,0 +1,34 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : adi_ad9528.h +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-09-08 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef ADI_AD9528_LIB_H_ +#define ADI_AD9528_LIB_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern void ucp_api_ad9528_Reset(void); +extern int32_t ucp_api_ad9528_Init(void); +extern uint8_t ucp_api_ad9528_LockStatus(void); +extern void ucp_api_ad9528_OnePluse(uint8_t enable); + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef ADI_JESD_H_ */ + diff --git a/driver/rfic/rf/adrv9025/c_src/app/example/adi_adrv9025Lib.c b/driver/rfic/rf/adrv9025/c_src/app/example/adi_adrv9025Lib.c new file mode 100644 index 0000000..22ce52f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/example/adi_adrv9025Lib.c @@ -0,0 +1,2371 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : adi_adrv9025Lib.c +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-09-08 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#include +#include +#include +#include +#include "string.h" +#include "adi_platform.h" +#include "adi_platform_types.h" +#include "adi_adrv9025_utilities.h" +#include "adi_adrv9025.h" +#include "adi_adrv9025_radioctrl.h" +#include "adi_adrv9025_tx.h" +#include "adi_common_error.h" +#include "adi_adrv9025_data_interface.h" +#include "adi_ad9528.h" +#include "adi_ad9528_utilities.h" +#include "initdata.h" +#include "platform_utils/adi_fmc_fru.h" +#include "platform_utils/adi_fmc_eeprom.h" +#include "adi_ad9528_utilities.h" +#include "adi_adrv9025_cals.h" +#include "adi_adrv9025_gpio.h" +#include "adi_adrv9025_rx.h" +#include "adi_ad9528Lib.h" + +#include "ucp_jesd_gpio.h" +#include "ucp_param.h" +#include "ucp_reg_io.h" +#include +#include +#include + +#include "adi_adrv9025Lib.h" + +#include "ucp_rfic_gpio.h" + +static int32_t recoveryAct = ADI_COMMON_ACT_ERR_RESET_FULL; + +static uint32_t mcsStatus = 0x00; +static uint32_t mcsStatusAnd = 0x17; + +static int8_t rxLinkSelect = 0x00; +static int8_t txLinkSelect = 0x00; +static int iterator = 0x00; +static bool programFlag = false; + +static adi_adrv9025_Device_t *adrv9025Device = NULL; +static adi_adrv9025_Device_t gAdrv9025Device; + +static adi_adrv9025_Init_t *adrv9025Init = NULL; +static adi_adrv9025_PinModeSettings_t *pinModeSettings = NULL; +static adi_adrv9025_PostMcsInit_t *adrv9025PostMcsInit = NULL; + +static adi_adrv9025_RxGainTableFile_t rxGainTableFileArr[] = { { { 0x00 } } }; +static adi_adrv9025_TxAttenTableFile_t txAttenTableFileArr[] = { { { 0x00 } } }; + +static adi_adrv9025_PinModeSettings_t pinModeSettingsLoad = { { { } } }; + +extern ucp_rfic_calPara_t ucp_GetRficCalParaInfo(void); +ucp_rfic_calPara_t gRficCalPara; + +/* Magic Numbers */ +const int8_t magicNumZero = 0x00; +const int8_t magicNumOne = 0x01; +const int8_t magicNumTwo = 0x02; +const int8_t magicNumThree = 0x03; +const int8_t magicNumFour = 0x04; +const int8_t magicNumFive = 0x05; +const int8_t magicNumSix = 0x06; +const int8_t magicNumSeven = 0x07; +const int8_t magicNumEight = 0x08; +const int8_t magicNumTwelve = 0x0C; +const int8_t magicNumThirteen = 0x0D; +const int8_t magicNumSixteen = 0x10; +const int8_t magicNumFifty = 0x32; +const int8_t magicNumNineSix = 0x60; +const int8_t magicNumHundred = 0x64; +const uint8_t magicNumTwoFiveFive = 0xFF; +const uint16_t magicNumOneThousand = 0x3E8; +const uint32_t magicNumOneTwentyThousand = 0x1D4C0; + +// config +static adi_hal_Cfg_t adiHal[3]; +const static int8_t failureReturn = -0x01; +static const uint8_t multichipSyncEnable = 0x01; +static const uint8_t multichipSyncDisable = 0x00; +static const uint8_t rxGainTableSize = 0x01; +static const uint8_t txAttenTableSize = 0x01; +static const uint8_t enableSync = 0x01; +static const uint8_t rxChannelMask = 0xFF; + +static const uint8_t loadConfigFileEnable = 0x00; +static uint8_t loadCalMgcGainIndex = 245; // 183 ~ 255 +static uint8_t localTxAtt = 0; + +const char adiProfileFilePath[] = "/lib/firmware/resources/adrv9025/profiles/daya2_4.9152G.profile"; +static adi_adrv9025_PlatformFiles_t platformFiles = { {"/lib/firmware/resources/adrv9025/arm_firmware/ADRV9025_FW.bin;/lib/firmware/resources/adrv9025/arm_firmware/ADRV9025_DPDCORE_FW.bin"}, + {"/lib/firmware/resources/adrv9025/arm_firmware/stream_image_357E871D1928C2A67823336885ACA3E3.bin"}, + { {{"/lib/firmware/resources/adrv9025/gain_tables/RxGainTable.csv"}, 0xFF} }, + 1, + { {{"/lib/firmware/resources/adrv9025/gain_tables/TxAttenTable.csv"}, 0x0F} }, + 1}; + + +/** +* \brief This is a helper function that will invoke the API : adi_adrv9025_ConfigFileLoad +* will initialize an ADRV9025 init struct +* +* \param adrv9025_Device Pointer to data structure that contains ADRV9025 device instance settings +* \param adrv9025_Init Pointer to ADRV9025 init settings structure +* +* Function will exit on failure +*/ +static void configFileLoad(adi_adrv9025_Device_t *adrv9025_Device, + adi_adrv9025_Init_t *adrv9025_Init) +{ + recoveryAct = ADI_COMMON_ACT_ERR_RESET_FULL; + /* Load ADRV9010 Init structure */ + /* adiProfileFilePath is defined as const global at top of this file */ + recoveryAct = adi_adrv9025_ConfigFileLoad(adrv9025_Device, adiProfileFilePath, adrv9025_Init); + if (recoveryAct != ADI_COMMON_ACT_NO_ACTION) + { + printf("ERROR: : %s:%u has failed.\n", __func__, __LINE__); + exit(EXIT_FAILURE); + } +} + +/** + * \brief This function is a helper function to fill out the members of the + * devHalCfg structure with driver names for common platform. + * + * This function allows keeping the platform specific knowledge of driver names + * in this layer of code. Higher layers of code can call this to fill out the + * devHalCfg structure correctly for the common platform. + * + * Each device gets a unique instance of the devHalCfg structure describing the + * device resources for that device, such as the SPI chip select, etc. + * + * \param interfaceMask A mask that represents which platform interfaces are required by a particular device (SPI, Logging, etc) + * \param spiChipSelect The chip select index describing the particular device + * \param logFilename The filename of the logfile for this device. + */ + void* hal_DevHalCfgCreate(uint32_t interfaceMask, + uint8_t spiChipSelect, + const char* logFilename) + { + uint8_t boardType; + char SPI_CHIP_DEV_PATH_0[30], SPI_CHIP_DEV_PATH_1[30], SPI_CHIP_DEV_PATH_2[30]; + + boardType = UCP_API_RFIC_GetBoardInfo(); + if (HW_EVMY == boardType) + { + strcpy(SPI_CHIP_DEV_PATH_0, "/dev/spidev3.0\0"); + strcpy(SPI_CHIP_DEV_PATH_1, "/dev/spidev1.1\0"); + strcpy(SPI_CHIP_DEV_PATH_2, "/dev/spidev1.0\0"); + } + else if ((HW_EVMF == boardType) || (HW_EVMT == boardType) || (HW_EVB == boardType)) + { + strcpy(SPI_CHIP_DEV_PATH_0, "/dev/spidev1.0\0"); + strcpy(SPI_CHIP_DEV_PATH_1, "/dev/spidev1.0\0"); + strcpy(SPI_CHIP_DEV_PATH_2, "/dev/spidev1.0\0"); + } + else + { + printf("error, unknow spi dev. @%s, %d\n", __FILE__, __LINE__); + } + + adi_hal_Cfg_t* halCfg = (adi_hal_Cfg_t*)&adiHal[spiChipSelect]; // (adi_hal_Cfg_t*)calloc(1, sizeof(adi_hal_Cfg_t)); // daya debug + if (halCfg == NULL) + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + return NULL; + } + + /* Disable all interfaces, and enable only if they are needed by the specific device */ + halCfg->spiCfg.interfaceEnabled = 0; + halCfg->logCfg.interfaceEnabled = 0; + halCfg->bbicCfg.interfaceEnabled = 0; + + /* If device requires SPI interface */ + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_SPI) > 0) + { + halCfg->spiCfg.interfaceEnabled = 1; + halCfg->spiCfg.chipSelectIndex = spiChipSelect; + + switch (spiChipSelect) + { + case SPI_CHIP_SELECT_0: + { + strncpy(halCfg->spiCfg.spidevName, + SPI_CHIP_DEV_PATH_0, + ADI_HAL_STRING_LENGTH); + break; + } + case SPI_CHIP_SELECT_1: + { + strncpy(halCfg->spiCfg.spidevName, + SPI_CHIP_DEV_PATH_1, + ADI_HAL_STRING_LENGTH); + break; + } + case SPI_CHIP_SELECT_2: + { + strncpy(halCfg->spiCfg.spidevName, + SPI_CHIP_DEV_PATH_2, + ADI_HAL_STRING_LENGTH); + break; + } + default: + { + // free(halCfg); // daya debug + return NULL; + } + } + + /* Default SPI settings */ + halCfg->spiCfg.autoIncAddrUp = 1; + halCfg->spiCfg.CPHA = 0; + halCfg->spiCfg.CPOL = 0; + halCfg->spiCfg.enSpiStreaming = 0; + halCfg->spiCfg.fourWireMode = 1; + halCfg->spiCfg.spiActionDisable = 0; + halCfg->spiCfg.spiClkFreq_Hz = 25000000; + } + + /* If device requires Logging interface */ + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_LOG) > 0) + { + halCfg->logCfg.interfaceEnabled = 1; + halCfg->logCfg.logLevel = ADI_HAL_LOG_ALL; + strncpy(halCfg->logCfg.logFileName, + logFilename, + ADI_HAL_STRING_LENGTH); + /* ensure null termination */ + halCfg->logCfg.logFileName[sizeof(halCfg->logCfg.logFileName) - 1] = '\0'; + } + +#if 0 // by daya + /* If device requires FPGA register interface */ + if (((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_BBICCTRL) > 0) || + ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_HWRESET) > 0)) /* ADS9 HWRESET interface requires BBICCTRL interface */ + { + halCfg->bbicCfg.interfaceEnabled = 1; + strncpy(halCfg->bbicCfg.coreRegsCfg.drvName, + BBIC_CORE_REG_PATH, + ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.coreRegsCfg.mapSize = MEM_SIZE_512MB; /* 512MB */ + strncpy(halCfg->bbicCfg.ramCfg.drvName, + BBIC_RAM_PATH, + ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.ramCfg.mapSize = MEM_SIZE_1GB; /* 1GB */ + strncpy(halCfg->bbicCfg.spiAdvRegsCfg.drvName, + BBIC_SPI_ADV_REG_PATH, + ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.spiAdvRegsCfg.mapSize = MEM_SIZE_16M; /* 16MB */ + } +#endif + + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_HWRESET) > 0) + { + halCfg->hwResetCfg.interfaceEnabled = 1; + + switch (spiChipSelect) + { + case SPI_CHIP_SELECT_0: + { + halCfg->hwResetCfg.resetPinIndex = 1; /* ADRV9025 reset pin bit position in FPGA register */ + break; + } + case SPI_CHIP_SELECT_1: + { + halCfg->hwResetCfg.resetPinIndex = 2; /* AD9528 reset pin bit position in FPGA register */ + break; + } + + default: + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + free(halCfg); + return NULL; + } + } + + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_I2C) > 0) + { + halCfg->i2cCfg.interfaceEnabled = 1; + strncpy(halCfg->i2cCfg.drvName, + I2C_EEPROM_PATH, + ADI_HAL_STRING_LENGTH); + } + + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_TIMER) > 0) + { + halCfg->timerCfg.interfaceEnabled = 1; + } + + return halCfg; +} + +extern uint32_t ucp_reg32_read(uint64_t reg); +void adrv9025_StatusMoniter (adi_adrv9025_Device_t *device, uint16_t monitMask) +{ + uint16_t i, j; + uint32_t pllLockStatus = 0; + uint8_t enable; + uint64_t gpIntStatus = 0, mask = 0; + adi_adrv9025_FramerStatus_t frameLinkStatus; + adi_adrv9025_DeframerStatus_t deframeLinkStatus; + char *framerStatusInf[] = { // expect 0x0A + "farameInf[3]: Current SYNCBIN level(1 = high, 0 = low)\n", + "farameInf[2]: SYSREF phase error - a new SYSREF had different timing than the first that set the LMFC timing\n", + "farameInf[1]: SYSREF phase established by framer\n", + "farameInf[0]: Flag indicating that configuration parameters are not supported when set(1)\n" + }; + char *deframerStatusInf[] = { // expect 0x87 + "defarameInf[7]: Valid checksum 1 if the checksum calculated by the ADRV9025 matched the one sent in the ILAS data\n", + "defarameInf[6]: EOF Event This bit captures the internal status of the framer End of Frame event. Value =1 if framing error during ILAS\n", + "defarameInf[5]: EOMF Event This bit captures the internal status of the framer End of Multi-Frame event. Value =1 if framing error during ILAS\n", + "defarameInf[4]: FS Lost This bit captures the internal status of the framer Frame Symbol event. Value =1 if framing error during ILAS or user data (invalid replacement characters)\n", + "defarameInf[3]: Reserved Reserved\n", + "defarameInf[2]: User Data Valid =1 when in user data (deframer link is up and sending valid DAC data)\n", + "defarameInf[1]: SYSREF Received Deframer has received the external SYSREF signal\n", + "defarameInf[0]: Syncb level Current level of Syncb signal internal to deframer (=1 means link is up)\n" + }; + +/*-------------------------------------—-------------------— +Status for JESD204B: +framerStatus->status +Description -------------------— + + [7] Reserved + [6] Reserved + [5] Reserved + [4] Reserved + [3] Current SYNCBIN level(1 = high, 0 = low) + [2] SYSREF phase error - a new SYSREF had different timing than the first that set the LMFC timing. + [1] SYSREF phase established by framer + [0] Flag indicating that configuration parameters are not supported when set(1) + +framerSynbcNeCount : 8 bit counter of negative edge Sync transitions +qbfStateStatus +Description --------------------— + + [7] Reserved + [6] Reserved + [5] Reserved + [4] Reserved + [3] Reserved + [2] QBF bit 2 + [1] QBF bit 1 + [0] QBF bit 0 + +syncNSel +Description --------------------— + + [7] Reserved + [6] Reserved + [5] Reserved + [4] Reserved + [3] Reserved + [2] Syncb crossbar select + [1] Syncb crossbar select + [0] Syncb crossbar select + +Status for JESD204C: +framerStatus->status +Description --------------------— + + [0] Sysref received bit +-------------------------------------—-------------------— */ + printf("--------------------------------------------------------------------\n"); + memset(&frameLinkStatus, 0, sizeof(adi_adrv9025_FramerStatus_t)); + adi_adrv9025_FramerStatusGet(device, ADI_ADRV9025_FRAMER_0, &frameLinkStatus); + printf("adiFramer 0 LinkStatus = %X SyncNeCount = %d qbfStateStatus = %X syncNSel = %X\n", + frameLinkStatus.status, + frameLinkStatus.framerSyncNeCount, + frameLinkStatus.qbfStateStatus, + frameLinkStatus.syncNSel); + mask = 1 << 3; + for (j = 0;j < 4;j++) { + if (mask & frameLinkStatus.status) { + printf(" #%s", framerStatusInf[j]); + } + mask >>= 1; + } + + printf("\n"); + memset(&frameLinkStatus, 0, sizeof(adi_adrv9025_FramerStatus_t)); + adi_adrv9025_FramerStatusGet(device, ADI_ADRV9025_FRAMER_1, &frameLinkStatus); + printf("adiFramer 1 LinkStatus = %X SyncNeCount = %d qbfStateStatus = %X syncNSel = %X\n", + frameLinkStatus.status, + frameLinkStatus.framerSyncNeCount, + frameLinkStatus.qbfStateStatus, + frameLinkStatus.syncNSel); + mask = 1 << 3; + for (j = 0;j < 4;j++) { + if (mask & frameLinkStatus.status) { + printf(" #%s", framerStatusInf[j]); + } + mask >>= 1; + } + + printf("\n"); + memset(&frameLinkStatus, 0, sizeof(adi_adrv9025_FramerStatus_t)); + adi_adrv9025_FramerStatusGet(device, ADI_ADRV9025_FRAMER_2, &frameLinkStatus); + printf("adiFramer 2 LinkStatus = %X SyncNeCount = %d qbfStateStatus = %X syncNSel = %X\n", + frameLinkStatus.status, + frameLinkStatus.framerSyncNeCount, + frameLinkStatus.qbfStateStatus, + frameLinkStatus.syncNSel); + mask = 1 << 3; + for (j = 0;j < 4;j++) { + if (mask & frameLinkStatus.status) { + printf(" #%s", framerStatusInf[j]); + } + mask >>= 1; + } + +/* +Status for JESD204B: +deframerStatus +Bit Name +Description -------------— + + [7] Valid checksum 1 if the checksum calculated by the ADRV9025 matched the one sent in the ILAS data. + [6] EOF Event This bit captures the internal status of the framer End of Frame event. Value =1 if framing error during ILAS + [5] EOMF Event This bit captures the internal status of the framer End of Multi-Frame event. Value =1 if framing error during ILAS + [4] FS Lost This bit captures the internal status of the framer Frame Symbol event. Value =1 if framing error during ILAS or user data (invalid replacement characters) + [3] Reserved Reserved + [2] User Data Valid =1 when in user data (deframer link is up and sending valid DAC data) + [1] SYSREF Received Deframer has received the external SYSREF signal + [0] Syncb level Current level of Syncb signal internal to deframer (=1 means link is up) + +Status for JESD204C: +deframerStatus +Bit Name +Description -------------— + + [2:0] Current lock state These 3 bits indicate state of JESD204C Lock + +An explanation of what each the value of the 3 bits relates to is below: +value +Description -------------— + + 0 Reset + 1 Unlocked + 2 Block(Blocks aligned) + 3 M_Block(Lanes aligned) + 4 E_M_Block(Multiblock aligned) + 5 FEC_BUF + 6 FEC_READY (Good State!) + 7 Reserved +*/ + printf("\n"); + memset(&deframeLinkStatus, 0, sizeof(adi_adrv9025_DeframerStatus_t)); + adi_adrv9025_DeframerStatusGet(device, ADI_ADRV9025_DEFRAMER_0, &deframeLinkStatus); + printf("adiDeframer 0 LinkStatus = %X reserved = %X\n", + deframeLinkStatus.status, + deframeLinkStatus.reserved); + mask = 1 << 7; + for (j = 0;j < 8;j++) { + if (mask & deframeLinkStatus.status) { + if (4 != j) { + printf(" #%s", deframerStatusInf[j]); + } + } + mask >>= 1; + } + + printf("\n"); + adi_adrv9025_DeframerStatusGet(device, ADI_ADRV9025_DEFRAMER_1, &deframeLinkStatus); + printf("adiDeframer 1 LinkStatus = %X reserved = %X\n", + deframeLinkStatus.status, + deframeLinkStatus.reserved); + mask = 1 << 7; + for (j = 0;j < 8;j++) { + if (mask & deframeLinkStatus.status) { + if (4 != j) { + printf(" #%s", deframerStatusInf[j]); + } + } + mask >>= 1; + } + + printf("\n"); + printf("RxCGS: %X\n", ucp_reg32_read(0x060013f4)); // cgs status + adi_adrv9025_FramerLinkStateGet(device, &enable); + printf("FramerLinkState = %d\n", enable); + adi_adrv9025_DfrmLinkStateGet(device, &enable); + printf("DeframerLinkState = %d\n", enable); + + /* + CLK_PLL_LOCK_STATUS bit0 + LO1_PLL_LOCK_STATUS bit1 + LO2_PLL_LOCK_STATUS bit2 + AUX_PLL_LOCK_STATUS bit3 + */ + adi_adrv9025_PllStatusGet(device, &pllLockStatus); + printf("pllLockStatus = %X\n", pllLockStatus); + +char *gpIntInf[] = { +//------------------------------------------------------------------------------- +//## Deframer + "D49 Deframer IRQ 11: Deframer1 JESD204C CRC error\n", + "D48 Deframer IRQ 10: Deframer1 JESD204C loss of sync\n", + +//------------------------------------------------------------------------------- +//## PLL + "D47 LO1 PLL unlock\n", + "D46 LO2 PLL unlock\n", + "D45 Auxiliary PLL unlock\n", + "D44 Clock PLL unlock\n", + "D43 LO1 PLL charge pump overrange\n", + "D42 LO2 PLL charge pump overrange\n", + "D41 Auxiliary PLL charge pump overrange\n", + "D40 Clock PLL charge pump overrange\n", + "D39 SERDES PLL unlock\n", + +//------------------------------------------------------------------------------- +//## Deframer + "D38 Deframer IRQ 9: Deframer1 JESD204B quad byte deframer (QBD) IRQ\n", + "D37 Deframer IRQ 8: Deframer1 SYSREF out of phase\n", + "D36 Deframer IRQ 7: Deframer1 elastic buffer error\n", + "D35 Deframer IRQ 6: Deframer1 lane FIFO pointer error\n", + "D34 Deframer IRQ 5: Deframer0 JESD204C CRC error\n", + "D33 Deframer IRQ 4: Deframer0 JESD204C loss of sync\n", + "D32 Deframer IRQ 3: Deframer0 JESD204B QBD IRQ\n", + "D31 Deframer IRQ 2: Deframer0 SYSREF out of phase\n", + "D30 Deframer IRQ 1: Deframer0 elastic buffer error\n", + "D29 Deframer IRQ 0: Deframer0 lane FIFO pointer error\n", + +//------------------------------------------------------------------------------- +//## Framer + "D28 Framer IRQ 8: Framer2 transport not sending data\n", + "D27 Framer IRQ 7: Framer2 SYSREF out of phase\n", + "D26 Framer IRQ 6: Framer2 lane FIFO pointer error\n", + "D25 Framer IRQ 5: Framer1 transport layer not sending data\n", + "D24 Framer IRQ 4: Framer1 SYSREF out of phase\n", + "D23 Framer IRQ 3: Framer1 lane FIFO pointer error\n", + "D22 Framer IRQ 2: Framer0 Transport layer not sending data\n", + "D21 Framer IRQ 1: Framer0 SYSREF out of phase\n", + "D20 Framer IRQ 0: Framer0 lane FIFO pointer error\n", + +//------------------------------------------------------------------------------- +//## Transmitter ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR + "D19 Power Amplifier Protection Error Tx4 (threshold exceeded)\n", + "D18 Power Amplifier Protection Error Tx3 (threshold exceeded)\n", + "D17 Power Amplifier Protection Error Tx2 (threshold exceeded)\n", + "D16 Power Amplifier Protection Error Tx1 (threshold exceeded)\n", + +//------------------------------------------------------------------------------- +//## ARM ADI_COMMON_ACT_ERROR_RESET_FULL + "D15 ARM has forced interrupt\n", + "D14 ARM watchdog timer timeout \n", + "D13 Slew rate limiter IRQ\n", + "D12 ARM system error\n", + +//------------------------------------------------------------------------------- +//## Stream processor + "D11 ORx3 or ORx4 stream processor error\n", + "D10 ORx1 or ORx2 stream processor error\n", + "D9 Tx4 stream processor error\n", + "D8 Tx3 stream processor error\n", + "D7 Tx2 stream processor error\n", + "D6 Tx1 stream processor error\n", + "D5 Rx4 stream processor error\n", + "D4 Rx3 stream processor error\n", + "D3 Rx2 stream processor error\n", + "D2 Rx1 stream processor error\n", + "D1 Core stream processor error\n", + +//------------------------------------------------------------------------------- +//## ARM + "D0 Memory ECC error\n" +}; + + gpIntStatus = 0; + adi_adrv9025_GpIntStatusGet(device, & gpIntStatus); + printf("gpIntStatus = %08X %08X\n", (uint32_t)((gpIntStatus >> 32) & 0xFFFFFFFF), (uint32_t)(gpIntStatus & 0xFFFFFFFF)); + mask = 1; + for (j = 0;j < 50;j++) { + if (mask & gpIntStatus) { + printf(" #%s", gpIntInf[49-j]); + } + mask <<= 1; + } + adi_adrv9025_GPIntClearStatusRegister(device); + + // printf("PCS_BIT_REV_CTRL: %X\n", ucp_reg32_read(JS_PMA0_PCS_BIT_REV_CTRL)); + + adi_adrv9025_DfrmCompareData_t dfrData; + adi_adrv9025_DfrmIlasMismatchGet(device, ADI_ADRV9025_DEFRAMER_0, &dfrData); + printf("\nchkFlag: %X, MismatchDfrm: %X\n\n", + dfrData.zeroCheckFlag, + dfrData.ilasMismatchDfrm); + printf("ilas: DID %d, BID %d, LID0 %d, L %d, SRC %d, F %d, K %d, M %d, N %d, CS %d, NP %d, S %d, CF %d, HD %X, FCHK0 %X\n", + dfrData.dfrmIlasData.dfrmDID, + dfrData.dfrmIlasData.dfrmBID, + dfrData.dfrmIlasData.dfrmLID0, + dfrData.dfrmIlasData.dfrmL, + dfrData.dfrmIlasData.dfrmSCR, + dfrData.dfrmIlasData.dfrmF, + dfrData.dfrmIlasData.dfrmK, + dfrData.dfrmIlasData.dfrmM, + dfrData.dfrmIlasData.dfrmN, + dfrData.dfrmIlasData.dfrmCS, + dfrData.dfrmIlasData.dfrmNP, + dfrData.dfrmIlasData.dfrmS, + dfrData.dfrmIlasData.dfrmCF, + dfrData.dfrmIlasData.dfrmHD, + dfrData.dfrmIlasData.dfrmFCHK0); + printf("cfig: DID %d, BID %d, LID0 %d, L %d, SRC %d, F %d, K %d, M %d, N %d, CS %d, NP %d, S %d, CF %d, HD %X, FCHK0 %X\n\n", + dfrData.dfrmCfgData.dfrmDID, + dfrData.dfrmCfgData.dfrmBID, + dfrData.dfrmCfgData.dfrmLID0, + dfrData.dfrmCfgData.dfrmL, + dfrData.dfrmCfgData.dfrmSCR, + dfrData.dfrmCfgData.dfrmF, + dfrData.dfrmCfgData.dfrmK, + dfrData.dfrmCfgData.dfrmM, + dfrData.dfrmCfgData.dfrmN, + dfrData.dfrmCfgData.dfrmCS, + dfrData.dfrmCfgData.dfrmNP, + dfrData.dfrmCfgData.dfrmS, + dfrData.dfrmCfgData.dfrmCF, + dfrData.dfrmCfgData.dfrmHD, + dfrData.dfrmCfgData.dfrmFCHK0); + +/* + laneStatus deframer status bits + bdCntValue Bad-Disparity error counter current value + uekCntValue UnExpected-K error counter current value + nitCntValue Not-In-Table error counter current value + +UnExpected + K-charactoer (UEK), + Not-In-Table (NIT), + Initial Lane Synchronization (ILS), + Inter-Lane De-skew (ILD), + Frame Sync (FS), + Computed CheckSum (CCS), + Code Group Sync (CGS), + Bad Disparity (BD). + +Lane Status Bit +Description ------— + [7] UEK Error, 0 = No Error, 1 = Error + [6] NIT Error, 0 = No Error, 1 = Error + [5] ILS Status, 0 = Not Completed, 1 = Completed Successfully + [4] ILD Status, 0 = Not Completed, 1 = Completed Successfully + [3] FS Status, 0 = Not Completed, 1 = Completed Successfully + [2] CCS Status, 0 = Not Completed, 1 = Completed Successfully + [1] CGS Status, 0 = Not Completed, 1 = Completed Successfully + [0] BD Error, 0 = No Error, 1 = Error +*/ + + adi_adrv9025_DfrmErrCounterStatus_t errCounterStatus; + for (i = 0;i < 4;i++) + { + // memset(&errCounterStatus, 0, sizeof(adi_adrv9025_DfrmErrCounterStatus_t)); + adi_adrv9025_DfrmErrCounterStatusGet(device, + ADI_ADRV9025_DEFRAMER_0, + i, + &errCounterStatus); + printf(" #deframe_%d lane%d: laneStatus %X, bdCntValue %d, nitCntValue %d, uekCntValue %d\n", + ADI_ADRV9025_DEFRAMER_0, + i, + errCounterStatus.laneStatus, + errCounterStatus.bdCntValue, + errCounterStatus.nitCntValue, + errCounterStatus.uekCntValue); + } + + printf("\n"); + for (i = 0;i < 4;i++) + { + // memset(&errCounterStatus, 0, sizeof(adi_adrv9025_DfrmErrCounterStatus_t)); + adi_adrv9025_DfrmErrCounterStatusGet(device, + ADI_ADRV9025_DEFRAMER_1, + i, + &errCounterStatus); + printf(" #deframe_%d lane%d: laneStatus %X, bdCntValue %d, nitCntValue %d, uekCntValue %d\n", + ADI_ADRV9025_DEFRAMER_1, + i, + errCounterStatus.laneStatus, + errCounterStatus.bdCntValue, + errCounterStatus.nitCntValue, + errCounterStatus.uekCntValue); + } + + printf("--------------------------------------------------------------------\n"); +} + +static int32_t adi_board_adrv9025_JesdTxBringup(adi_adrv9025_Device_t* adrv9025Device, + uint32_t link) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if 0 + /* Unmask incoming sysref in FPGA framers (leave rx links untouched) */ + recoveryAction = adi_fpga9025_SysRefEnableSet(fpga9025Device, + (uint8_t)link, + 0, + ADI_ENABLE); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + /* Enable/reset FPGA Framer(s) */ + recoveryAction = adi_fpga9025_FramerReset(fpga9025Device, + (uint8_t)link); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); +#endif + /* Request sysref to start fpga framers sending data */ + ucp_api_ad9528_OnePluse(1); + +#if 0 + /* Mask the sysref for the fpga framers as a precaution for the next sysref (leave rx links untouched) */ + recoveryAction = adi_fpga9025_SysRefEnableSet(fpga9025Device, + (uint8_t)link, + 0, + ADI_DISABLE); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); +#endif + /* Reset/Enable Adrv9025 Deframer(s) */ + recoveryAction = adi_adrv9025_DfrmLinkStateSet(adrv9025Device, + (uint8_t)link, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_common_hal_Wait_ms(&adrv9025Device->common, + 50); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_DfrmLinkStateSet(adrv9025Device, + (uint8_t)link, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + sleep(1); +#if 0 + /* Notify ARM to run SERDES Calbriation if necessary */ + serdesCal.calMask = ADI_ADRV9025_SERDES_INIT; + serdesCal.channelMask = CAL_ALL_CHANNELS; + serdesCal.warmBoot = 0; + recoveryAction = adi_adrv9025_InitCalsRun(adrv9025Device, + &serdesCal); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Wait up to 60 seconds for ARM */ + recoveryAction = adi_adrv9025_InitCalsWait(adrv9025Device, + 60000, + &errFlags); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); +#endif + /* Adrv9025 Unmask Sysref in Deframer(s) */ + recoveryAction = adi_adrv9025_DeframerSysrefCtrlSet(adrv9025Device, + (adi_adrv9025_DeframerSel_e)link, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Request sysref for adrv9025 deframers only */ + ucp_api_ad9528_OnePluse(1); + + /* Adrv9025 mask Sysref in Deframer(s) as a precaution */ + recoveryAction = adi_adrv9025_DeframerSysrefCtrlSet(adrv9025Device, + (adi_adrv9025_DeframerSel_e)link, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + return recoveryAction; +} + +static int32_t adi_board_adrv9025_JesdRxBringup(adi_adrv9025_Device_t* adrv9025Device, + uint32_t link) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t sysrefEnabledForFramer2 = ADI_FALSE; + + if (adrv9025Device->devStateInfo.linkSharingEnabled == 1) + { + /* Start the AUX Sys Ref in JTX Link 1*/ + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + ADI_ADRV9025_FRAMER_1, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Adrv9025 Unmask incoming Sysref in Framer(s) */ + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_FRAMER_1, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + ucp_api_ad9528_OnePluse(1); + + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + ADI_ADRV9025_FRAMER_1, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_FRAMER_1, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + ADI_ADRV9025_FRAMER_0, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_FRAMER_0, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Check that if the profile uses Framer 2 */ + if ((link & (uint32_t)ADI_ADRV9025_FRAMER_2) == (uint32_t)ADI_ADRV9025_FRAMER_2) + { + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + ADI_ADRV9025_FRAMER_2, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_FRAMER_2, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + sysrefEnabledForFramer2 = ADI_TRUE; + } + } + else + { + /* Enable/reset Adrv9025 Framer(s) */ + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + link, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_common_hal_Wait_ms(&adrv9025Device->common, + 50); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + link, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Adrv9025 Unmask incoming Sysref in Framer(s) */ + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + (uint8_t)link, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + } + +#if 0 + /* Disable DFE LPM in PHY before after sys ref */ + adi_fpga9025_ChannelDfeLpmOverrideSet(fpga9025Device, + 0xFF, + 0); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); +#endif + + /* Wait 100ms for clock recovery on FPGA to lock */ + recoveryAction = adi_common_hal_Wait_ms(&adrv9025Device->common, + 100); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); +#if 0 + /* Enable/reset FPGA Deframer(s) */ + recoveryAction = adi_fpga9025_DeframerReset(fpga9025Device, + (uint8_t)link); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + /* Disable DFE LPM in PHY before after sys ref */ + recoveryAction = adi_fpga9025_ChannelDfeLpmOverrideSet(fpga9025Device, + 0xFF, + 0); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + /* Unmask incoming sysref in FPGA deframers (leave tx links untouched) */ + recoveryAction = adi_fpga9025_SysRefEnableSet(fpga9025Device, + 0, + (uint8_t)link, + ADI_ENABLE); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); +#endif + /* Request sysref to bring up Rx links */ + ucp_api_ad9528_OnePluse(1); + + if (adrv9025Device->devStateInfo.linkSharingEnabled == 0) + { + /* Adrv9025 mask sysref in Framers. Precaution against future sysref signals */ + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + (uint8_t)link, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + } + + if (sysrefEnabledForFramer2 == ADI_TRUE) + { + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_FRAMER_2, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + } +#if 0 + /* Mask sysref in fpga deframers. Precaution against future sysref signals */ + recoveryAction = adi_fpga9025_SysRefEnableSet(fpga9025Device, + 0, + (uint8_t)link, + ADI_DISABLE); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); +#endif + return recoveryAction; +} + +static int32_t adi_board_adrv9025_JesdBringup(adi_adrv9025_Device_t * adrv9025Device, + uint32_t txLinkSel, + uint32_t rxLinkSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t i = 0; + uint8_t adrv9025LinkStatus = 0; + uint8_t deframerLinkCondition = 0; + + /* Mask all sysrefs in Adrv9025 */ + recoveryAction = adi_adrv9025_DeframerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_DEFRAMER_0, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_ALL_FRAMERS, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); +#if 0 + /* Mask all sysrefs in fpga */ + recoveryAction = adi_fpga9025_SysRefEnableSet(fpga9025Device, + ADI_FPGA9025_FRAMER_ALL, + ADI_FPGA9025_DEFRAMER_ALL, + ADI_DISABLE); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + /* Disable all the FPGA framer & deframers */ + recoveryAction = adi_fpga9025_FramerDisable(fpga9025Device, + ADI_FPGA9025_FRAMER_ALL); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + recoveryAction = adi_fpga9025_DeframerDisable(fpga9025Device, + ADI_FPGA9025_DEFRAMER_ALL); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); +#endif + /* Disable all the ADRV9025 framer & deframers */ + recoveryAction = adi_adrv9025_DfrmLinkStateSet(adrv9025Device, + (uint8_t)ADI_ADRV9025_DEFRAMER_0, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + (uint8_t)ADI_ADRV9025_ALL_FRAMERS, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); +#if 0 + /* Override DFE LPM in PHY before sending sys ref */ + recoveryAction = adi_fpga9025_ChannelDfeLpmOverrideSet(fpga9025Device, + 0xFF, + 1); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); +#endif + if (rxLinkSel != 0) + { + /* Bring up the Rx links */ + recoveryAction = adi_board_adrv9025_JesdRxBringup(adrv9025Device, + rxLinkSel); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); +#if 0 + if (fpga9025Device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + recoveryAction = adi_fpga9025_Jesd204CDeframerCmdDataSet(fpga9025Device, + rxLinkSel, + ADI_ENABLE, + ADI_ENABLE); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + } +#endif + } + + if (txLinkSel != 0) + { + /* Bring up the Tx links */ + recoveryAction = adi_board_adrv9025_JesdTxBringup(adrv9025Device, + txLinkSel); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); +#if 0 + if (fpga9025Device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + recoveryAction = adi_fpga9025_Jesd204CFramerCmdDataSet(fpga9025Device, + txLinkSel, + ADI_ENABLE, + ADI_ENABLE); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + } +#endif + } + + /* Adrv9025 Deframer Status get*/ + for (i = 0; i < 2; i++) + { + if ((txLinkSel & (1 << i)) > 0) + { + deframerLinkCondition = 0; + recoveryAction = adi_adrv9025_DfrmLinkConditionGet(adrv9025Device, + (adi_adrv9025_DeframerSel_e)((uint8_t)(1 << i)), + &deframerLinkCondition); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + if (deframerLinkCondition & 0x01) + { + adrv9025LinkStatus |= (1 << i); + } + } + } +#if 0 + /* Fpga Reading User Data Ready bit*/ + recoveryAction = adi_fpga9025_DeframerStatusGet(fpga9025Device, + rxLinkSel, + &fpga9025LinkStatus); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + if (adrv9025LinkStatus != txLinkSel) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_INTERFACE; + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Not all Tx links have been established."); + + /* Disable all the FPGA deframers. Don't update the error though, this is just cleanup */ + adi_fpga9025_FramerDisable(fpga9025Device, + ADI_FPGA9025_FRAMER_ALL); + } + if (fpga9025LinkStatus != rxLinkSel) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_INTERFACE; + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Not all Rx links have been established."); + + /* Disable all the FPGA deframers. Don't update the error though, this is just cleanup */ + adi_fpga9025_DeframerDisable(fpga9025Device, + ADI_FPGA9025_DEFRAMER_ALL); + } +#endif + + /* Kick off SERDES tracking cal if lanes are up */ + recoveryAction = adi_adrv9025_TrackingCalsEnableSet(adrv9025Device, + 0x100FFFFFF, // ADI_ADRV9025_TRACK_DESERIALIZER, + ADI_ADRV9025_TRACKING_CAL_DISABLE); // ADI_ADRV9025_TRACKING_CAL_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_setAtt (uint8_t chanMask, uint16_t att) +{ + int32_t recoveryAction = 0; + adi_adrv9025_TxAtten_t txAtten = { 0 }; + + if (att > 41000) + { + printf("err: att out of range!\n"); + return ADI_COMMON_ACT_ERR_RESET_FULL; + } + + printf("txAtt: 0x%02X %d\n", chanMask, att); + txAtten.txChannelMask = chanMask; + txAtten.txAttenuation_mdB = att; /* Back off Tx output power by 30dB */ + recoveryAction = adi_adrv9025_TxAttenSet(adrv9025Device, &txAtten, 1); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + printf("Failed to set ADRV9025 Tx Attenuation\n"); + printf("ERROR: Error number %d, Recovery action %d. In file %s, in function %s, in line %d, variable name %s. Error message %s.\n", + adrv9025Device->common.error.errCode, + adrv9025Device->common.error.newAction, + adrv9025Device->common.error.errFile, + adrv9025Device->common.error.errFunc, + adrv9025Device->common.error.errLine, + adrv9025Device->common.error.varName, + adrv9025Device->common.error.errormessage); + /* Call action handler */ + return ADI_COMMON_ACT_ERR_RESET_FULL; + } + + return recoveryAction; +} + +int32_t adrv9025_spiRxTxEnableSet(uint32_t rxChannelMask, + uint32_t txChannelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + recoveryAction = adi_adrv9025_RxTxEnableSet(adrv9025Device, rxChannelMask, txChannelMask); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + printf("Failed to enable ADRV9025 Tx RF output\n"); + printf("ERROR: Error number %d, Recovery action %d. In file %s, in function %s, in line %d, variable name %s. Error message %s.\n", + adrv9025Device->common.error.errCode, + adrv9025Device->common.error.newAction, + adrv9025Device->common.error.errFile, + adrv9025Device->common.error.errFunc, + adrv9025Device->common.error.errLine, + adrv9025Device->common.error.varName, + adrv9025Device->common.error.errormessage); + + /* Call action handler */ + return ADI_COMMON_ACT_ERR_RESET_FULL; + } + + return recoveryAction; +} + +void adrv9025_setGainMode (uint8_t mgcEn) +{ + adi_adrv9025_RxAgcMode_t gainMode[2]; + adi_adrv9025_RxAgcMode_e mode; + + mode = mgcEn ? ADI_ADRV9025_MGC : ADI_ADRV9025_AGCFAST; + + gainMode[0].agcMode = mode; + gainMode[0].rxChannelMask = 0xFF; + gainMode[1].agcMode = mode; + gainMode[1].rxChannelMask = 0xFF; + gainMode[2].agcMode = mode; + gainMode[2].rxChannelMask = 0xFF; + gainMode[3].agcMode = mode; + gainMode[3].rxChannelMask = 0xFF; + adi_adrv9025_RxGainCtrlModeSet(adrv9025Device, gainMode, 4); +} + +int32_t adi_adrv9025_EnableTxExample (adi_adrv9025_Device_t *device) +{ + int32_t recoveryAction = 0; + + if (device == NULL) + { + printf("NULL ADRV9025 device pointer\n"); + return -1; + } + + /* Setup internal Tx test tone frequency */ + adi_adrv9025_TxTestToneCfg_t toneCfg = { 0 }; + toneCfg.txChannelMask = ADI_ADRV9025_TXALL; + toneCfg.txToneFreq_Hz = 2800000; + toneCfg.txToneGain = ADI_ADRV9025_TX_NCO_0_DB; + toneCfg.enable = 1; + recoveryAction = adi_adrv9025_TxTestToneSet(device, &toneCfg, 1); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + printf("Failed to setup ADRV9025 Tx Test Tone\n"); + printf("ERROR: Error number %d, Recovery action %d. In file %s, in function %s, in line %d, variable name %s. Error message %s.\n", + device->common.error.errCode, + device->common.error.newAction, + device->common.error.errFile, + device->common.error.errFunc, + device->common.error.errLine, + device->common.error.varName, + device->common.error.errormessage); + /* Call action handler */ + return ADI_COMMON_ACT_ERR_RESET_FULL; + } + +#if 0 + adi_adrv9025_TxAtten_t txAtten = { 0 }; + txAtten.txChannelMask = ADI_ADRV9025_TXALL; + txAtten.txAttenuation_mdB = 30000; // 15000; /* Back off Tx output power by 30dB */ + recoveryAction = adi_adrv9025_TxAttenSet(device, &txAtten, 1); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + printf("Failed to set ADRV9025 Tx Attenuation\n"); + printf("ERROR: Error number %d, Recovery action %d. In file %s, in function %s, in line %d, variable name %s. Error message %s.\n", + device->common.error.errCode, + device->common.error.newAction, + device->common.error.errFile, + device->common.error.errFunc, + device->common.error.errLine, + device->common.error.varName, + device->common.error.errormessage); + /* Call action handler */ + return ADI_COMMON_ACT_ERR_RESET_FULL; + } +#endif + return 0; +} + +int32_t adrv9025_tone (bool set) +{ + int32_t recoveryAction = 0; + + UCP_API_GPIO_Tx(); + recoveryAction = adi_adrv9025_EnableTxExample(adrv9025Device); + return recoveryAction; +} + +int32_t ad9025_MGC_Cfg(uint8_t en) +{ + adi_adrv9025_RxAgcMode_t gainMode[3]; + + if (en) + { + gainMode[0].agcMode = ADI_ADRV9025_MGC; + } + else + { + gainMode[0].agcMode = ADI_ADRV9025_AGCFAST; + } + + gainMode[0].rxChannelMask = 0xFF; + adi_adrv9025_RxGainCtrlModeSet(adrv9025Device, gainMode, 1); + + return 1; +} + +int32_t ad9025_Gain_Set(double gain_db) +{ + adi_adrv9025_RxGain_t gain[3]; + uint8_t gain_index = 0; + + gain_index = (uint8_t)(gain_db*2); + gain[0].rxChannelMask = 0xFF; + loadCalMgcGainIndex = ((gain_index + 183) > 255) ? 255 : (gain_index + 183); + gain[0].gainIndex = loadCalMgcGainIndex; + adi_adrv9025_RxGainSet(adrv9025Device, gain, 1); + + return 0; +} + +double ad9025_Gain_Get(void) +{ + return (double)((loadCalMgcGainIndex - 183)*0.5); +} + +int32_t ad9025_Att_Set(uint8_t att_db) +{ + localTxAtt = (att_db > 20) ? 20 : att_db; + printf("localTxAtt: %d db\n", localTxAtt); + + // HW_EVMT/HW_EVMF: 15000 14500 14500 16450 + // HW_EVMY: 10000 10000 10000 12450 + // HW_EVB: 0 0 0 0 + adrv9025_setAtt(0x1, localTxAtt*1000 + gRficCalPara.calChAttPara[0]); + + return 0; +} + +uint8_t ad9025_Att_Get(void) +{ + return localTxAtt; +} + +void ad9025_rssi(void) +{ + uint16_t rssi[8] = {0}; + adi_adrv9025_RxAgcMode_t gainMode[3]; + adi_adrv9025_RxGain_t gain[3]; + uint8_t gainIndex; + double para_calRxInstrument, para_calOrxInstrument, + para_calRx, para_calOrx; + + printf("start rssi test:\n"); + + adrv9025_spiRxTxEnableSet(0xFF, 0x0F); + + gainMode[0].agcMode = ADI_ADRV9025_MGC; + gainMode[0].rxChannelMask = 0xFF; + adi_adrv9025_RxGainCtrlModeSet(adrv9025Device, gainMode, 1); + + gain[0].rxChannelMask = 0xFF; + gain[0].gainIndex = loadCalMgcGainIndex; // 183~255 20.7225@183 18.3475@185 + adi_adrv9025_RxGainSet(adrv9025Device, gain, 1); + + // orx - rx = 14.1875db + // rxNoisy = -36.155dbm@183 orxNoisy = -21.9675@183 + // rxRawNosiy = -57.1875db@183 orxRawNosiy = -42.5db@183 + // rxNoisy = -36.155; + para_calRx = 20.7225; + para_calOrx = para_calRx; + gainIndex = (gain[0].gainIndex < 183) ? 255 : gain[0].gainIndex; + para_calRxInstrument = para_calRx - (gainIndex - 183)*0.5; + para_calOrxInstrument = para_calOrx - (gainIndex - 183)*0.5; + + while (1) + { + adi_adrv9025_RxDecPowerGet(adrv9025Device, ADI_ADRV9025_RX1, &rssi[0]); + adi_adrv9025_RxDecPowerGet(adrv9025Device, ADI_ADRV9025_RX2, &rssi[1]); + adi_adrv9025_RxDecPowerGet(adrv9025Device, ADI_ADRV9025_RX3, &rssi[2]); + adi_adrv9025_RxDecPowerGet(adrv9025Device, ADI_ADRV9025_RX4, &rssi[3]); + adi_adrv9025_RxDecPowerGet(adrv9025Device, ADI_ADRV9025_ORX1, &rssi[4]); + adi_adrv9025_RxDecPowerGet(adrv9025Device, ADI_ADRV9025_ORX2, &rssi[5]); + adi_adrv9025_RxDecPowerGet(adrv9025Device, ADI_ADRV9025_ORX3, &rssi[6]); + adi_adrv9025_RxDecPowerGet(adrv9025Device, ADI_ADRV9025_ORX4, &rssi[7]); + printf("rssiInst = %.2f | %.2f | %.2f | %.2f | %.2f | %.2f | %.2f | %.2f\r\n", + -(rssi[0]*1.0/1000.0) + para_calRxInstrument, + -(rssi[1]*1.0/1000.0) + para_calRxInstrument, + -(rssi[2]*1.0/1000.0) + para_calRxInstrument, + -(rssi[3]*1.0/1000.0) + para_calRxInstrument, + -(rssi[4]*1.0/1000.0) + para_calOrxInstrument, + -(rssi[5]*1.0/1000.0) + para_calOrxInstrument, + -(rssi[6]*1.0/1000.0) + para_calOrxInstrument, + -(rssi[7]*1.0/1000.0) + para_calOrxInstrument); + printf("rssiPad = %.2f | %.2f | %.2f | %.2f | %.2f | %.2f | %.2f | %.2f\r\n", + -(rssi[0]*1.0/1000.0) + para_calRx, + -(rssi[1]*1.0/1000.0) + para_calRx, + -(rssi[2]*1.0/1000.0) + para_calRx, + -(rssi[3]*1.0/1000.0) + para_calRx, + -(rssi[4]*1.0/1000.0) + para_calOrx, + -(rssi[5]*1.0/1000.0) + para_calOrx, + -(rssi[6]*1.0/1000.0) + para_calOrx, + -(rssi[7]*1.0/1000.0) + para_calOrx); + printf("rssi_db = %.2f | %.2f | %.2f | %.2f | %.2f | %.2f | %.2f | %.2f\r\n\n", + -(rssi[0]*1.0/1000.0), + -(rssi[1]*1.0/1000.0), + -(rssi[2]*1.0/1000.0), + -(rssi[3]*1.0/1000.0), + -(rssi[4]*1.0/1000.0), + -(rssi[5]*1.0/1000.0), + -(rssi[6]*1.0/1000.0), + -(rssi[7]*1.0/1000.0)); + sleep(3); + rssi[0] = 0; rssi[1] = 0; rssi[2] = 0; rssi[3] = 0; + rssi[4] = 0; rssi[5] = 0; rssi[6] = 0; rssi[7] = 0; + } + + UCP_API_GPIO_Off(); +} + +uint32_t adrv9026_getLockStatus (void) +{ + uint32_t mcsStatus = 0x00, pllLockStatus = 0x00; + + adi_adrv9025_MultichipSyncStatusGet(adrv9025Device, &mcsStatus); + printf("MCS Status 0x%X\n", mcsStatus); + + adi_adrv9025_PllStatusGet(adrv9025Device, &pllLockStatus); + printf("pllLockStatus = %X\n", pllLockStatus); + + return pllLockStatus; +} + +int16_t adrv9026_getTemperature (void) +{ + int16_t temperatureDegC; + + adi_adrv9025_TemperatureGet(adrv9025Device, &temperatureDegC); + printf("Temperature: %d\n", temperatureDegC); + + return temperatureDegC; +} +#if 0 +void adi_cofigPrbs_send(uint8_t prbsIndex) +{ + adi_adrv9025_FrmTestDataCfg_t testCfg; + testCfg.injectPoint = ADI_ADRV9025_FTD_FRAMERINPUT; // ADI_ADRV9025_FTD_SERIALIZER; // ADI_ADRV9025_FTD_POST_LANEMAP; // ; + testCfg.framerSelMask = ADI_ADRV9025_FRAMER_0; + if (0 == prbsIndex) + { + testCfg.testDataSource = ADI_ADRV9025_FTD_PRBS31; + printf("adiSend_PRBS31\n"); + } + else + { + testCfg.testDataSource = ADI_ADRV9025_FTD_PRBS7; + printf("adiSend_PRBS7\n"); + } + adi_adrv9025_FramerTestDataSet(adrv9025Device, &testCfg); + + adrv9025_DeserializerLaneEnable(adrv9025Device, 0xF, 1); +} + +void adi_cofigPrbsCheck(uint8_t prbsIndex) +{ + adi_adrv9025_DfrmPrbsCfg_t testCfg; + + if (0 == prbsIndex) + { + testCfg.polyOrder = ADI_ADRV9025_PRBS31; + printf("adiCheck_PRBS31\n"); + } + else + { + testCfg.polyOrder = ADI_ADRV9025_FTD_PRBS7; + printf("adiCheck_PRBS7\n"); + } + testCfg.deframerSel = ADI_ADRV9025_DEFRAMER_0; + testCfg.checkerLocation = ADI_ADRV9025_PRBSCHECK_SAMPLEDATA; // ADI_ADRV9025_PRBSCHECK_LANEDATA; // + adi_adrv9025_DfrmPrbsCheckerStateSet(adrv9025Device, &testCfg); +} + +void adi_resetPrbsCheckCount (void) +{ + adi_adrv9025_DfrmPrbsCountReset(adrv9025Device); +} + +uint32_t adi_prbsCheckCount(void) +{ + adi_adrv9025_DfrmPrbsErrCounters_t count; + + adi_adrv9025_DfrmPrbsErrCountGet(adrv9025Device, &count); + + printf("adiPrbs: %d %d %d %d. s %X status %X %X %X %X\n", + count.laneErrors[0], count.laneErrors[1], count.laneErrors[2], count.laneErrors[3], + count.sampleSource, + count.errorStatus[0],count.errorStatus[1],count.errorStatus[2],count.errorStatus[3]); +} + +void ucp_testCsuTx (void) +{ + ucp_csu_config_test(); + + rf_txSwitch(); + + while (1) + { + js_csu_ioctrl_tx(); + } +} + +void ucp_testCsuRx (void) +{ + int getData; + uint16_t rssi[8] = {0}, rfSwitch = 0; + + ucp_csu_config_test(); + + adi_adrv9025_RxAgcMode_t gainMode[2]; + printf("start cus data sample\n"); + + gainMode[0].agcMode = ADI_ADRV9025_MGC; + gainMode[0].rxChannelMask = 0xFF; + gainMode[1].agcMode = ADI_ADRV9025_MGC; + gainMode[1].rxChannelMask = 0xFF; + gainMode[2].agcMode = ADI_ADRV9025_MGC; + gainMode[2].rxChannelMask = 0xFF; + rf_rxSwitch(); + adi_adrv9025_RxGainCtrlModeSet(adrv9025Device, gainMode, 3); + + while (1) + { + getData = getchar(); + + if (('s' == getData) || ('S' == getData)) + { + js_csu_ioctrl_rx(); + printf("sample one block!\n"); + } + + if (('b' == getData) || ('B' == getData)) + { + js_csu_ioctrl_rx(); + printf("sample over!\n"); + break; + } + + getData = 0; + } +} + +enum { + PRBS_UCP2TRX, + PRBS_TRX2UCP, + PRBS_UCP2TRX_ERR, + PRBS_TRX2UCP_ERR, + PRBS_NEAREND_LOOPBACK, + PRBS_FAREND_LOOPBACK, + PRBS_NEAREND_LOOPBACK_ERR, + PRBS_FAREND_LOOPBACK_ERR +}; + +void adi_prbsTest (uint8_t testcase) +{ + adi_adrv9025_FramerStatus_t frameLinkStatus; + adi_adrv9025_DeframerStatus_t deframeLinkStatus; + + if ((PRBS_UCP2TRX == testcase) || (PRBS_NEAREND_LOOPBACK == testcase)) + { + ucp_cofigPrbsSend(0); + } + + if ((PRBS_UCP2TRX_ERR == testcase) || (PRBS_NEAREND_LOOPBACK_ERR == testcase)) + { + ucp_cofigPrbsSend(1); + } + + if ((PRBS_TRX2UCP == testcase) || (PRBS_FAREND_LOOPBACK == testcase)) + { + adi_cofigPrbs_send(0); + } + + if ((PRBS_TRX2UCP_ERR == testcase) || (PRBS_FAREND_LOOPBACK_ERR == testcase)) + { + adi_cofigPrbs_send(1); + } + + if ((PRBS_UCP2TRX == testcase) \ + || (PRBS_FAREND_LOOPBACK == testcase) \ + || (PRBS_UCP2TRX_ERR == testcase) \ + || (PRBS_FAREND_LOOPBACK_ERR == testcase)) + { + adi_cofigPrbsCheck(0); + adi_resetPrbsCheckCount(); + } + + if ((PRBS_TRX2UCP == testcase) \ + || (PRBS_NEAREND_LOOPBACK == testcase) \ + || (PRBS_TRX2UCP_ERR == testcase) \ + || (PRBS_NEAREND_LOOPBACK_ERR == testcase)) + { + ucp_cofigPrbsCheck(0); + } + + + if ((PRBS_NEAREND_LOOPBACK == testcase) + || (PRBS_NEAREND_LOOPBACK_ERR == testcase)) + { + ucp_cofigPrbsNearEndLoopBack(); + } + + if ((PRBS_FAREND_LOOPBACK == testcase) + || (PRBS_FAREND_LOOPBACK_ERR == testcase)) + { + ucp_cofigPrbsFarEndLoopBack(); + } + + while (1) { + if ((PRBS_UCP2TRX == testcase) \ + || (PRBS_FAREND_LOOPBACK == testcase) \ + || (PRBS_UCP2TRX_ERR == testcase) \ + || (PRBS_FAREND_LOOPBACK_ERR == testcase)) + { + adi_prbsCheckCount(); + adi_resetPrbsCheckCount(); + } + + if ((PRBS_TRX2UCP == testcase) \ + || (PRBS_NEAREND_LOOPBACK == testcase) \ + || (PRBS_TRX2UCP_ERR == testcase) \ + || (PRBS_NEAREND_LOOPBACK_ERR == testcase)) + { + ucp_prbsCheckCount(); + } + + sleep(1); + } +} +#endif + +void adrv9025_setup_platform(void *adiInit, void *adiPostMcsStru) +{ + int32_t error = ADI_COMMON_HAL_OK; + adi_hal_Cfg_t* devCfg = NULL; + + /* Board Level */ + adrv9025Device = (adi_adrv9025_Device_t*)&gAdrv9025Device; + adrv9025Init = (adi_adrv9025_Init_t*)adiInit; + adrv9025PostMcsInit = (adi_adrv9025_PostMcsInit_t *)adiPostMcsStru; + pinModeSettings = (adi_adrv9025_PinModeSettings_t *)&pinModeSettingsLoad; + + /* create hal layer for this motherboard daya: SPI_CHIP_SELECT_1 for adrv9025*/ + adrv9025Device->common.devHalInfo = NULL; + adrv9025Device->common.devHalInfo = hal_DevHalCfgCreate((ADI_HAL_INTERFACE_SPI | \ + ADI_HAL_INTERFACE_LOG | \ + ADI_HAL_INTERFACE_HWRESET | \ + ADI_HAL_INTERFACE_TIMER), + SPI_CHIP_SELECT_0, "adrv9025.txt"); + if (adrv9025Device->common.devHalInfo == NULL) + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + return; + } + + adrv9025Device->common.error.logEnable = ADI_ENABLE; + devCfg = (adi_hal_Cfg_t*)adrv9025Device->common.devHalInfo; + strcpy(devCfg->typeName, "adrv9025Dev"); + + error = adi_hal_PlatformSetup(adrv9025Device->common.devHalInfo, + (adi_hal_Platforms_e)ADI_UCP2_PLATFORM); + if (error != ADI_HAL_OK) + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + return; + } + + adi_adrv9025_SpiSettings_t spiSettings = { + .msbFirst = 1, + .enSpiStreaming = 0, + .autoIncAddrUp = 1, + .fourWireMode = 1, + .cmosPadDrvStrength = ADI_ADRV9025_CMOSPAD_DRV_STRONG, + }; + + adi_adrv9025_HwOpen(adrv9025Device, &spiSettings); + + printf("adrv9025Device init ok!\n"); + + return; +} + +void adrv9025_remove_platform(void) +{ + adi_adrv9025_HwClose(adrv9025Device); + + return; +} + +void ad9025_InitInstAdjust(uint64_t txLo, uint64_t rxLo, uint64_t auxLo, uint16_t enOrx) +{ + uint8_t boardType; + + boardType = UCP_API_RFIC_GetBoardInfo(); + + if (txLo == rxLo) + { + adrv9025Init->clocks.rx12LoSelect = ADI_ADRV9025_LOSEL_LO1; + adrv9025Init->clocks.rx34LoSelect = ADI_ADRV9025_LOSEL_LO1; + adrv9025Init->clocks.tx12LoSelect = ADI_ADRV9025_LOSEL_LO1; + adrv9025Init->clocks.tx34LoSelect = ADI_ADRV9025_LOSEL_LO1; + + adrv9025PostMcsInit->radioCtrlInit.lo1PllFreq_Hz = rxLo; + adrv9025PostMcsInit->radioCtrlInit.lo2PllFreq_Hz = 0u; + } + else + { + adrv9025Init->clocks.rx12LoSelect = ADI_ADRV9025_LOSEL_LO1; + adrv9025Init->clocks.rx34LoSelect = ADI_ADRV9025_LOSEL_LO1; + adrv9025Init->clocks.tx12LoSelect = ADI_ADRV9025_LOSEL_LO2; + adrv9025Init->clocks.tx34LoSelect = ADI_ADRV9025_LOSEL_LO2; + + adrv9025PostMcsInit->radioCtrlInit.lo1PllFreq_Hz = rxLo; + adrv9025PostMcsInit->radioCtrlInit.lo2PllFreq_Hz = txLo; + } + + switch (enOrx) + { + case CFG_TLO_ORX: + adrv9025Init->clocks.orx12LoSelect = ADI_ADRV9025_ORXLOSEL_TXLO; + adrv9025Init->clocks.orx34LoSelect = ADI_ADRV9025_ORXLOSEL_TXLO; + break; + + case CFG_ALO_ORX: + adrv9025Init->clocks.orx12LoSelect = ADI_ADRV9025_ORXLOSEL_AUXLO; + adrv9025Init->clocks.orx34LoSelect = ADI_ADRV9025_ORXLOSEL_AUXLO; + + adrv9025PostMcsInit->radioCtrlInit.auxPllFreq_Hz = auxLo; + break; + + case CFG_RLO_ORX: + printf("adrv9025 can't support CFG_RLO_ORX mode\n"); + break; + + default: + break; + } + + if (HW_EVMY == boardType) + { + adrv9025Init->dataInterface.framer[0].syncbInSelect = 1; + adrv9025Init->dataInterface.framer[1].syncbInSelect = 0; + } + + if (HW_EVB == boardType) + { + adrv9025PostMcsInit->radioCtrlInit.radioCtrlModeCfg.txRadioCtrlModeCfg.txEnableMode = ADI_ADRV9025_TX_EN_SPI_MODE; + adrv9025PostMcsInit->radioCtrlInit.radioCtrlModeCfg.rxRadioCtrlModeCfg.rxEnableMode = ADI_ADRV9025_RX_EN_SPI_MODE; + } + + if ((HW_EVMT == boardType) || (HW_EVMF == boardType) || (HW_EVMY == boardType)) + { + adrv9025Init->tx.txChannelCfg[0].dacFullScale = 1; + adrv9025Init->tx.txChannelCfg[0].txAttenCtrl.dacFullScale = 1; + adrv9025Init->tx.txChannelCfg[0].txAttenCtrl.txAttenInit_mdB = 10000; + + adrv9025Init->tx.txChannelCfg[1].dacFullScale = 1; + adrv9025Init->tx.txChannelCfg[1].txAttenCtrl.dacFullScale = 1; + adrv9025Init->tx.txChannelCfg[1].txAttenCtrl.txAttenInit_mdB = 10000; + + adrv9025Init->tx.txChannelCfg[2].dacFullScale = 1; + adrv9025Init->tx.txChannelCfg[2].txAttenCtrl.dacFullScale = 1; + adrv9025Init->tx.txChannelCfg[2].txAttenCtrl.txAttenInit_mdB = 10000; + + adrv9025Init->tx.txChannelCfg[3].dacFullScale = 1; + adrv9025Init->tx.txChannelCfg[3].txAttenCtrl.dacFullScale = 1; + adrv9025Init->tx.txChannelCfg[3].txAttenCtrl.txAttenInit_mdB = 10000; + } +} + +void ucp_api_adrv9025_Reset(void) +{ + ucp_jesd_gpioSet(GPIO_INDEX_9025RESET, 0); + sleep(1); + ucp_jesd_gpioSet(GPIO_INDEX_9025RESET, 1); + + memset(&gAdrv9025Device, 0, sizeof(adi_adrv9025_Device_t)); + + return; +} + +/**** +The initialization process + +The following steps are the pre-multichip synchronization (MCS) initialization sequence: +1. adi_adrv9025_Initialize + a. Set SPI controller settings + b. Set master bias + c. Enable pin pads + d. Set device clock hsdig divider + e. Load PFIRs per channel + f. Load gain tables + g. Load transmitter attenuation tables + h. Load stream binary + i. Load ARM binary + j. Write initialization structure/receiver/transmitter profile info into ARM memory + k. ARM run = 1 + l. Wait for ARM boot to complete + m. Verify ARM checksum +2. ARM configuration + a. Receiver/transmitter channel configuration (all half-band filter enables, clock dividers) + b. Clock PLL and SERDES PLL configuration + c. JESD204B and JESD204C configuration + d. ARM switches to clock PLL output after PLL locked +The following steps are the post MCS initialization sequence: +1. MCS: + a. Set ARM run = 0 + b. Enable MCS state machine to listen for new SYSREF pulses + c. Customer sends SYSREF pulses + d. When MCS state machine complete, ARM run = 1 +2. Run ARM init calibrations +3. Enable tracking cals + a. Enable radio control pin mode or not + b. Setup any GPIO for ARM/streams +The system is now ready +****/ +int32_t adrv9025_init(uint64_t txLo, uint64_t rxLo, uint16_t initAtt, uint16_t initGain, + uint64_t auxLo, uint16_t enOrx, + ucp_rfic_calPara_t calPara) +{ + uint8_t data = 0, boardType; + int32_t recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + + adi_adrv9025_RxAgcMode_t gainMode[3]; + adi_adrv9025_RxGain_t gain[3]; + uint8_t errFlags = 0; + adi_adrv9025_InitCals_t serdesCal = {0}; + + boardType = UCP_API_RFIC_GetBoardInfo(); + gRficCalPara = calPara; + + adi_adrv9025_HwReset(adrv9025Device); + UCP_API_GPIO_Off(); + UCP_API_GPIO_OrxOff(); + + // step 1 >>> set platform + // step 2 >>> load config + /* Clear the common errors */ + if (loadConfigFileEnable) + { + if ((recoveryAction = adi_adrv9025_ConfigFileLoad(adrv9025Device, adiProfileFilePath, adrv9025Init)) != ADI_COMMON_ACT_NO_ACTION) + { + printf("Error loading the requested profile to ADRV9025 init"); + printf("ERROR: Error number %d, Recovery action %d. In file %s, in function %s, in line %d, variable name %s. Error message %s.\n", + adrv9025Device->common.error.errCode, + adrv9025Device->common.error.newAction, + adrv9025Device->common.error.errFile, + adrv9025Device->common.error.errFunc, + adrv9025Device->common.error.errLine, + adrv9025Device->common.error.varName, + adrv9025Device->common.error.errormessage); + /* Call action handler */ + return ADI_COMMON_ACT_ERR_RESET_FULL; + } + } + else + { + /* ADRV9025 settings are used from initdata.c + * they are already loaded in deviceInitInst. + * Verify that the structure was generated for the same API */ + + adi_adrv9025_ApiVersion_t apiVersion; + recoveryAction = adi_adrv9025_ApiVersionGet(adrv9025Device, &apiVersion); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + printf("ERROR: adi_adrv9025_ApiVersionGet has failed.\n"); + return ADI_COMMON_ACT_ERR_RESET_FULL; + } + + if (initStructApiVersion.majorVer != apiVersion.majorVer || initStructApiVersion.minorVer != apiVersion.minorVer || initStructApiVersion.maintenanceVer != apiVersion.maintenanceVer || initStructApiVersion.buildVer != apiVersion.buildVer) + { + printf("ERROR: Device initialization structure in \"initdata.c\" was generated for API version %d.%d.%d.%d, but the detected version on the device is %d.%d.%d.%d.\n\n", + initStructApiVersion.majorVer, initStructApiVersion.minorVer, initStructApiVersion.maintenanceVer, initStructApiVersion.buildVer, + apiVersion.majorVer, apiVersion.minorVer, apiVersion.maintenanceVer, apiVersion.buildVer); + return ADI_COMMON_ACT_ERR_RESET_FULL; + } + } + ad9025_InitInstAdjust(txLo, rxLo, auxLo, enOrx); + + // step 3 >>> Pre-MCS + /*********************************************************************************************/ + /**************** Pre-MCS V2 init sequence ***************************************************/ + /*********************************************************************************************/ + strcpy(rxGainTableFileArr[0].rxGainTableCsvFileName, (char*)platformFiles.rxGainTableFileArr); + rxGainTableFileArr[0].rxChannelMask = rxChannelMask; + + strcpy(txAttenTableFileArr[0].txAttenTableCsvFileName, (char*)platformFiles.txAttenTableFileArr); + txAttenTableFileArr[0].txChannelMask = adrv9025PostMcsInit->radioCtrlInit.radioCtrlModeCfg.txRadioCtrlModeCfg.txChannelMask; + + /* Execute API */ + recoveryAct = adi_adrv9025_PreMcsInit_v2(adrv9025Device, + adrv9025Init, + (const char*)platformFiles.armImageFile, + (const char*)platformFiles.streamImageFile, + rxGainTableFileArr, + rxGainTableSize, + txAttenTableFileArr, + txAttenTableSize); + if (recoveryAct != ADI_COMMON_ACT_NO_ACTION) + { + printf("ERROR: : %s:%u has failed.\n", __func__, __LINE__); + return recoveryAct; + } + /**************** END: Pre-MCS init sequence *************************************************/ + // step 4 >>> non-broadcastable MCS + /*********************************************************************************************/ + /**************** Pre-MCS non-broadcastable init sequence ************************************/ + /*********************************************************************************************/ + /* Call PreMcsInit_NonBroadCast and Set the state to ARM Loaded */ + if (loadConfigFileEnable) + { + configFileLoad(adrv9025Device, adrv9025Init); + } + ad9025_InitInstAdjust(txLo, rxLo, auxLo, enOrx); + + recoveryAct = adi_adrv9025_PreMcsInit_NonBroadCast(adrv9025Device, adrv9025Init); + if (recoveryAct != ADI_COMMON_ACT_NO_ACTION) + { + printf("ERROR: : %s:%u has failed.\n", __func__, __LINE__); + return recoveryAct; + } + + /**************** END: Pre-MCS non-broadcastable init sequence *******************************/ + /**************** END: Programming Sequence Phase 1 ******************************************/ + + + /*********************************************************************************************/ + /**************** Programming Sequence Phase 2 ***********************************************/ + /*********************************************************************************************/ + /* MCS start sequence */ + + /*********************************************************************************************/ + /**************** Setup the transceiver to listen for incoming SYSREF ************************/ + /**************** pulses to synchronize the internal clock tree ******************************/ + /*********************************************************************************************/ + recoveryAct = adi_adrv9025_MultichipSyncSet(adrv9025Device, multichipSyncEnable); + if (recoveryAct != ADI_COMMON_ACT_NO_ACTION) + { + printf("ERROR: : %s:%u has failed.\n", __func__, __LINE__); + return recoveryAct; + } + /**************** END: Transceiver Setup *****************************************************/ + + /*********************************************************************************************/ + /**************** Send SPI messages to request a SYSREF pulse ********************************/ + /*********************************************************************************************/ + + /* Loop over SysrefRequest 255 times, unless MCS status is achived before the loop completes */ + for (iterator = 0; iterator < magicNumTwoFiveFive; iterator++) + { + ucp_api_ad9528_OnePluse(enableSync); + + /*********************************************************************************************/ + /**************** Reads back the multi-chip sync status **************************************/ + /*********************************************************************************************/ + /* + mcsStatus + bit Description --------— + + [0] MCS JESD SYSREF Status (1 = sync occurred) + [1] MCS Digital Clocks Sync Status (1 = sync occurred) + [2] MCS Clock Gen Sync Status (1 = sync occurred) + [3] MCS CLKPLL SDM Sync Status (1 = sync occurred) + [4] MCS Device Clock divider Sync Status (1 = sync occurred) + */ + recoveryAct = adi_adrv9025_MultichipSyncStatusGet(adrv9025Device, &mcsStatus); + if (recoveryAct != ADI_COMMON_ACT_NO_ACTION) + { + printf("ERROR: : %s:%u has failed.\n", __func__, __LINE__); + return recoveryAct; + } + + if ((mcsStatus & mcsStatusAnd) == mcsStatusAnd) + { + break; + } + } + + /* Confirm mcsStatus is correct value after iteration */ + if ((mcsStatus & mcsStatusAnd) != mcsStatusAnd) + { + printf("ERROR: : %s:%u has failed mcsStatus = %X\n.\n", __func__, __LINE__, mcsStatus); + return failureReturn; + } + else + { + printf("SUCESS: MCS Status 0x%X\n", mcsStatus); + } + + /**************** END: Reads back the multi-chip sync status *********************************/ + /**************** END: Send SPI messages to request a SYSREF pulse ***************************/ + + /*********************************************************************************************/ + /**************** Disable the transceiver to listen for incoming SYSREF **********************/ + /**************** pulses to synchronize the internal clock tree ******************************/ + /*********************************************************************************************/ + recoveryAct = adi_adrv9025_MultichipSyncSet(adrv9025Device, multichipSyncDisable); + if (recoveryAct != ADI_COMMON_ACT_NO_ACTION) + { + printf("ERROR: : %s:%u has failed.\n", __func__, __LINE__); + return recoveryAct; + } + /**************** END: Disable the transceiver ***********************************************/ + + /*********************************************************************************************/ + /**************** Post MCS Sequence **********************************************************/ + /*********************************************************************************************/ + recoveryAct = adi_adrv9025_PostMcsInit(adrv9025Device, adrv9025PostMcsInit); + if (recoveryAct != ADI_COMMON_ACT_NO_ACTION) + { + printf("ERROR: : %s:%u has failed.\n", __func__, __LINE__); + return recoveryAct; + } + + // add by daya debug + recoveryAct = adi_adrv9025_PostMcsInit(adrv9025Device, adrv9025PostMcsInit); + if (recoveryAct != ADI_COMMON_ACT_NO_ACTION) + { + printf("ERROR: : %s:%u has failed.\n", __func__, __LINE__); + return recoveryAct; + } + + /**************** END: Post MCS Sequence *****************************************************/ + + /*********************************************************************************************/ + /**************** Reset the serializer *******************************************************/ + /*********************************************************************************************/ + recoveryAct = adi_adrv9025_SerializerReset(adrv9025Device, adrv9025Init->clocks.serdesPllVcoFreq_kHz); // pllClkSource); + if (recoveryAct != ADI_COMMON_ACT_NO_ACTION) + { + printf("ERROR: : %s:%u has failed.\n", __func__, __LINE__); + return recoveryAct; + } + /**************** END: Reset the serializer **************************************************/ + + /*********************************************************************************************/ + /**************** Bring up the JESD204 data link *********************************************/ + /*********************************************************************************************/ + for (iterator = magicNumZero; iterator < magicNumThree; iterator++) + { + if (adrv9025Init->dataInterface.framer[iterator].serializerLanesEnabled > magicNumZero) + { + rxLinkSelect |= magicNumOne << iterator; + } + } + + for (iterator = magicNumZero; iterator < magicNumTwo; iterator++) + { + if (adrv9025Init->dataInterface.deframer[iterator].deserializerLanesEnabled > magicNumZero) + { + txLinkSelect |= magicNumOne << iterator; + } + } + + printf("txLink = %X, rxLink = %X\n", txLinkSelect, rxLinkSelect); + + /* JESD204 link bring up */ + recoveryAct = adi_board_adrv9025_JesdBringup(adrv9025Device, txLinkSelect, rxLinkSelect); + if (recoveryAct != ADI_COMMON_ACT_NO_ACTION) + { + printf("ERROR: : %s:%u has failed.\n", __func__, __LINE__); + return recoveryAct; + } + /**************** END: Bring up the JESD204 data link ****************************************/ + + /*********************************************************************************************/ + /**************** Clear Jesd Dfrm Irq's ******************************************************/ + /*********************************************************************************************/ + recoveryAct = adi_adrv9025_TxRampDownInit(adrv9025Device, adrv9025Init); + if (recoveryAct != ADI_COMMON_ACT_NO_ACTION) + { + printf("ERROR: : %s:%u has failed.\n", __func__, __LINE__); + return recoveryAct; + } + + /**************** END: Clear Jesd Dfrm Irq's *************************************************/ + + /*********************************************************************************************/ + /**************** Initialize GP interrupt masks for pin0 & pin1 ******************************/ + /*********************************************************************************************/ + recoveryAct = adi_adrv9025_GpIntInit(adrv9025Device, &adrv9025Init->gpInterrupts); + if (recoveryAct != ADI_COMMON_ACT_NO_ACTION) + { + printf("ERROR: : %s:%u has failed.\n", __func__, __LINE__); + return recoveryAct; + } + /**************** END: Initialize GP interrupt masks for pin0 & pin1 *************************/ + /**************** END: Programming Sequence Phase 2 ******************************************/ + /**************** END: The programming sequence **********************************************/ + printf("LO1: %lu LO2: %lu auxLO: %lu\n", + adrv9025PostMcsInit->radioCtrlInit.lo1PllFreq_Hz, + adrv9025PostMcsInit->radioCtrlInit.lo2PllFreq_Hz, + adrv9025PostMcsInit->radioCtrlInit.auxPllFreq_Hz); + adi_adrv9025_ProductIdGet(adrv9025Device, &data); + printf("ADRV9025 ID: 0x%X\n", data); + printf("\n*** Platform Programmed Successfully *** \n\n"); + + programFlag = true; + + adrv9025_StatusMoniter(adrv9025Device, 1); + +// ext LO cal ------------------------------------------------ + printf("start extLo cal\n"); + + // ext cal att + printf("extCal attSet\n"); + adrv9025_setAtt(0x1, 10000); + + gainMode[0].agcMode = ADI_ADRV9025_MGC; + gainMode[0].rxChannelMask = 0xFF; + adi_adrv9025_RxGainCtrlModeSet(adrv9025Device, gainMode, 1); + + gain[0].rxChannelMask = 0x10; + gain[0].gainIndex = 240; //gRficCalPara.calOrxGainIndex; + adi_adrv9025_RxGainSet(adrv9025Device, gain, 1); + // HW_EVMT: 240 other: 245 + printf("extCal gainIndex: %d\n", gRficCalPara.calOrxGainIndex); + + UCP_API_GPIO_OrxOn(); + UCP_API_GPIO_Tx(); + + serdesCal.calMask = (0x00000800U); + serdesCal.warmBoot = 0; + serdesCal.channelMask = 0x01; + adrv9025_spiRxTxEnableSet(ADI_ADRV9025_ORX1, ADI_ADRV9025_TX1); + adi_adrv9025_InitCalsRun(adrv9025Device, &serdesCal); + adi_adrv9025_InitCalsWait(adrv9025Device, 60000, &errFlags); + + UCP_API_GPIO_Off(); + +//------------------------------------------------ + printf("Init attSet\n"); + ad9025_Att_Set(initAtt); + + gain[0].rxChannelMask = 0x0F; + gain[0].gainIndex = initGain; + adi_adrv9025_RxGainSet(adrv9025Device, gain, 1); + printf("Init gainIndex: %d\n", initGain); + + if (HW_EVMF == boardType) + { + UCP_API_GPIO_On(); + printf("LNA & PA On\n"); + } + + printf("adrv9025 init over.\n"); + + return recoveryAct; + +} + + + + + + diff --git a/driver/rfic/rf/adrv9025/c_src/app/example/adi_adrv9025Lib.h b/driver/rfic/rf/adrv9025/c_src/app/example/adi_adrv9025Lib.h new file mode 100644 index 0000000..daa4600 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/example/adi_adrv9025Lib.h @@ -0,0 +1,45 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : adi_adrv9025.h +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-09-08 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef ADI_ADRV9025_LIB_H_ +#define ADI_ADRV9025_LIB_H_ + +#include +#include +#include +#include "../../api/inc/ucp_api_rfic.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern void adrv9025_setup_platform(void *adiInit, void *adiPostMcsStru); +extern void ucp_api_adrv9025_Reset(void); +extern int32_t adrv9025_init(uint64_t txLo, uint64_t rxLo, uint16_t initAtt, uint16_t initGain, + uint64_t auxLo, uint16_t enOrx, + ucp_rfic_calPara_t calPara); +extern int32_t ad9025_MGC_Cfg(uint8_t en); +extern int32_t ad9025_Gain_Set(double gain_db); +extern double ad9025_Gain_Get(void); +extern int32_t ad9025_Att_Set(uint8_t att_db); +extern uint8_t ad9025_Att_Get(void); + +extern int32_t adrv9025_tone (bool set); +extern uint32_t adrv9026_getLockStatus (void); +extern int16_t adrv9026_getTemperature (void); +extern void ad9025_rssi(void); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef ADI_ADRV9025_LIB_H */ diff --git a/driver/rfic/rf/adrv9025/c_src/app/example/adi_commonLib.h b/driver/rfic/rf/adrv9025/c_src/app/example/adi_commonLib.h new file mode 100644 index 0000000..2c717bb --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/example/adi_commonLib.h @@ -0,0 +1,32 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : adi_commonLib.h +// Author : boheng.lin@smartlogictech.com +// Date First Issued : 2023-07-18 17:52:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef ADI_COMMON_LIB_H_ +#define ADI_COMMON_LIB_H_ + +#include +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +extern void* hal_DevHalCfgCreate(uint32_t interfaceMask, uint8_t spiChipSelect, const char* logFilename); + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef ADI_COMMON_LIB_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/app/example/initdata.h b/driver/rfic/rf/adrv9025/c_src/app/example/initdata.h new file mode 100644 index 0000000..015f7bd --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/example/initdata.h @@ -0,0 +1,50 @@ +/** +* \file initdata.h +* \brief Contains extern declarations for adrv9025 data structures initializations +* +* ADRV9025 API Version: 6.4.0.14 +* +*/ + +/** +* Copyright 2015 - 2018 Analog Devices Inc. +* Released under the adrv9025 API license, for more information +* see the "LICENSE.txt" file in this zip file. +*/ +#ifndef INITDATA_H_ +#define INITDATA_H_ + +#include "adi_adrv9025.h" +#include "adi_adrv9025_utilities.h" + +#ifdef __cplusplus +extern "C" { +#endif + + extern adi_adrv9025_ApiVersion_t initStructApiVersion; + extern adi_adrv9025_ArmVersion_t initStructArmVersion; + extern adi_adrv9025_StreamVersion_t initStructStreamVersion; + extern adi_adrv9025_Init_t deviceInitInst_122_88M_4_9152G; + extern adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_122_88M_4_9152G; + extern adi_adrv9025_Init_t deviceInitInst_61_44M_4_9152G_FDD2ANT; + extern adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_61_44M_4_9152G_FDD2ANT; + extern adi_adrv9025_Init_t deviceInitInst_61_44M_4_9152G_FDD4ANT; + extern adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_61_44M_4_9152G_FDD4ANT; + extern adi_adrv9025_Init_t deviceInitInst_245_76M_9_8304G; + extern adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_245_76M_9_8304G; + extern adi_adrv9025_Init_t deviceInitInst_122_88M_9_8304G; + extern adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_122_88M_9_8304G; + extern adi_adrv9025_Init_t deviceInitInst_122_88M_9_8304G_ORX; + extern adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_122_88M_9_8304G_ORX; + extern adi_adrv9025_Init_t deviceInitInst_240M; + extern adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_240M; + extern adi_adrv9025_Init_t deviceInitInst_122_88M_8_11008G; + extern adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_122_88M_8_11008G; + extern adi_adrv9025_Init_t deviceInitInst_122_88M_4_9152G_FDD2ANT; + extern adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_122_88M_4_9152G_FDD2ANT; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef INITDATA_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_122.88M_4.9152G.c b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_122.88M_4.9152G.c new file mode 100644 index 0000000..079e1b6 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_122.88M_4.9152G.c @@ -0,0 +1,1360 @@ +#include "initdata.h" + +adi_adrv9025_ApiVersion_t initStructApiVersion = {6, 4, 0, 14}; + +adi_adrv9025_ArmVersion_t initStructArmVersion = {6, 4, 0, 6}; + +adi_adrv9025_StreamVersion_t initStructStreamVersion = {9, 4, 0, 1}; + +adi_adrv9025_Init_t deviceInitInst_122_88M_4_9152G = +{ + { // clocks + 122880, // deviceClock_kHz + 9830400, // clkPllVcoFreq_kHz + 0, // serdesPllVcoFreq_kHz + 0, // ldoSelect + 0, // extLoFreq1_kHz + 0, // extLoFreq2_kHz + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll1LoMode + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll2LoMode + 0, // rfPll1LoOutDivider + 0, // rfPll2LoOutDivider + ADI_ADRV9025_RFPLLMCS_NOSYNC, // rfPllPhaseSyncMode + ADI_ADRV9025_LOSEL_LO1, // rx12LoSelect + ADI_ADRV9025_LOSEL_LO1, // rx34LoSelect + ADI_ADRV9025_LOSEL_LO1, // tx12LoSelect + ADI_ADRV9025_LOSEL_LO1, // tx34LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO, // orx12LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO // orx34LoSelect + }, + { // gpInterrupts + 0x0, // gpIntMaskPin0 + 0x0 // gpIntMaskPin1 + }, + { // rx + 0x3FF, // rxInitChannelMask + { // rxChannelCfg (array) + { // rxChannelCfg[0] + { // profile + ADI_ADRV9025_RX1, // channelType + 2, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 122880, // rxOutputRate_kHz + 100000, // rfBandwidth_kHz + 100000, // rxBbf3dBCorner_kHz + 50000, // rxAdcBandWidth_kHz + { // rxFir + -6, // gain_dB + 48, // numFirCoefs + {4, 22, 23, -38, -76, 51, 174, -49, -335, 11, 579, 89, -928, -295, 1417, 672, -2107, -1354, 3153, 2693, -5046, -6187, 10155, 30139, 30139, 10155, -6187, -5046, 2693, 3153, -1354, -2107, 672, 1417, -295, -928, 89, 579, 11, -335, -49, 174, 51, -76, -38, 23, 22, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x01, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[1] + { // profile + ADI_ADRV9025_RX2, // channelType + 2, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 122880, // rxOutputRate_kHz + 100000, // rfBandwidth_kHz + 100000, // rxBbf3dBCorner_kHz + 50000, // rxAdcBandWidth_kHz + { // rxFir + -6, // gain_dB + 48, // numFirCoefs + {4, 22, 23, -38, -76, 51, 174, -49, -335, 11, 579, 89, -928, -295, 1417, 672, -2107, -1354, 3153, 2693, -5046, -6187, 10155, 30139, 30139, 10155, -6187, -5046, 2693, 3153, -1354, -2107, 672, 1417, -295, -928, 89, 579, 11, -335, -49, 174, 51, -76, -38, 23, 22, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x02, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[2] + { // profile + ADI_ADRV9025_RX3, // channelType + 2, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 122880, // rxOutputRate_kHz + 100000, // rfBandwidth_kHz + 100000, // rxBbf3dBCorner_kHz + 50000, // rxAdcBandWidth_kHz + { // rxFir + -6, // gain_dB + 48, // numFirCoefs + {4, 22, 23, -38, -76, 51, 174, -49, -335, 11, 579, 89, -928, -295, 1417, 672, -2107, -1354, 3153, 2693, -5046, -6187, 10155, 30139, 30139, 10155, -6187, -5046, 2693, 3153, -1354, -2107, 672, 1417, -295, -928, 89, 579, 11, -335, -49, 174, 51, -76, -38, 23, 22, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x04, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[3] + { // profile + ADI_ADRV9025_RX4, // channelType + 2, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 122880, // rxOutputRate_kHz + 100000, // rfBandwidth_kHz + 100000, // rxBbf3dBCorner_kHz + 50000, // rxAdcBandWidth_kHz + { // rxFir + -6, // gain_dB + 48, // numFirCoefs + {4, 22, 23, -38, -76, 51, 174, -49, -335, 11, 579, 89, -928, -295, 1417, 672, -2107, -1354, 3153, 2693, -5046, -6187, 10155, 30139, 30139, 10155, -6187, -5046, 2693, 3153, -1354, -2107, 672, 1417, -295, -928, 89, 579, 11, -335, -49, 174, 51, -76, -38, 23, 22, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x08, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[4] + { // profile + ADI_ADRV9025_ORX1, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x10, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[5] + { // profile + ADI_ADRV9025_ORX2, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x20, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[6] + { // profile + ADI_ADRV9025_ORX3, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x40, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[7] + { // profile + ADI_ADRV9025_ORX4, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x80, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[8] + { // profile + ADI_ADRV9025_LB12, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x100, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[9] + { // profile + ADI_ADRV9025_LB34, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x200, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + } + }, // rxChannelCfg (end of array) + }, + { // tx + 0x0F, // txInitChannelMask + { // txChannelCfg (array) + { // txChannelCfg[0] + { // profile + 122880, // txInputRate_kHz + 100000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {-28, 45, -82, 152, -262, 462, -893, 1945, -4588, 22882, -4588, 1945, -893, 462, -262, 152, -82, 45, -28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_3DB, // dacFullScale + 0 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_3DB // dacFullScale + }, + { // txChannelCfg[1] + { // profile + 122880, // txInputRate_kHz + 100000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {-28, 45, -82, 152, -262, 462, -893, 1945, -4588, 22882, -4588, 1945, -893, 462, -262, 152, -82, 45, -28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_3DB, // dacFullScale + 0 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_3DB // dacFullScale + }, + { // txChannelCfg[2] + { // profile + 122880, // txInputRate_kHz + 100000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {-28, 45, -82, 152, -262, 462, -893, 1945, -4588, 22882, -4588, 1945, -893, 462, -262, 152, -82, 45, -28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_3DB, // dacFullScale + 0 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_3DB // dacFullScale + }, + { // txChannelCfg[3] + { // profile + 122880, // txInputRate_kHz + 100000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {-28, 45, -82, 152, -262, 462, -893, 1945, -4588, 22882, -4588, 1945, -893, 462, -262, 152, -82, 45, -28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_3DB, // dacFullScale + 0 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_3DB // dacFullScale + } + }, // txChannelCfg (end of array) + }, + { // dataInterface + { // framer (array) + { // framer[0] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0, // lmfcOffset + 0, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 1, // lane1FramerOutSel + 2, // lane2FramerOutSel + 3 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_RX1_I, // conv0 + ADI_ADRV9025_ADC_RX1_Q, // conv1 + ADI_ADRV9025_ADC_RX2_I, // conv2 + ADI_ADRV9025_ADC_RX2_Q, // conv3 + ADI_ADRV9025_ADC_RX3_I, // conv4 + ADI_ADRV9025_ADC_RX3_Q, // conv5 + ADI_ADRV9025_ADC_RX4_I, // conv6 + ADI_ADRV9025_ADC_RX4_Q, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[1] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 0, // jesd204M + 32, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 1, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 1, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[2] + 0, // enableJesd204C + 0, // bankId + 2, // deviceId + 0, // lane0Id + 0, // jesd204M + 1, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 1, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 2, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // framer (end of array) + { // deframer (array) + { // deframer[0] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // deserializerLanesEnabled + 0, // lmfcOffset + 0, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 0, // deframerInput0LaneSel + 1, // deframerInput1LaneSel + 2, // deframerInput2LaneSel + 3 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT0, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT1, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT2, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT3, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT4, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT5, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT6, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT7 // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 1, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // deframer[1] + 0, // enableJesd204C + 0, // bankId + 0, // deviceId + 0, // lane0Id + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 0, // lmfcOffset + 1, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 8, // deframerInput0LaneSel + 8, // deframerInput1LaneSel + 8, // deframerInput2LaneSel + 8 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 1, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // deframer (end of array) + { // serCfg (array) + { // serCfg[0] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[1] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[2] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[3] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + } + }, // serCfg (end of array) + { // desCfg (array) + { // desCfg[0] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[1] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[2] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[3] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + } + }, // desCfg (end of array) + { // linkSharingCfg + 0, // linkSharingEnabled + 0, // linkSharingM + 0, // linkSharingS + 0, // linkSharingNp + { // linkSharingAdcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE // conv15 + }, + }, + { // dataCfg + 0, // enable + 0, // configOption1 + 0 // configOption2 + }, + 0, // channelSelect + 0 // channelMode + }, + { // adcProfiles + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0, // OrxChannel1Index + 0 // OrxChannel2Index + }, +}; + + +adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_122_88M_4_9152G = +{ + { // radioCtrlInit + { // radioCtrlModeCfg + { // txRadioCtrlModeCfg + ADI_ADRV9025_TX_EN_PIN_MODE, // txEnableMode + 0x0F // txChannelMask + }, + { // rxRadioCtrlModeCfg + ADI_ADRV9025_RX_EN_PIN_MODE, // rxEnableMode + 0xFF // rxChannelMask + }, + { // orxRadioCtrlModeCfg + ADI_ADRV9025_ORX_EN_SINGLE_CH_1PIN_MODE, // orxEnableMode + 0, // orxPinSelectSettlingDelay_armClkCycles + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel1PinModeOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel2PinModeLowOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel2PinModeHighOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE // dualChannel2PinModeOrxSel + }, + }, + { // txToOrxMapping + ADI_ADRV9025_MAP_TX1_ORX1, // orx1Map + ADI_ADRV9025_MAP_TX2_ORX2, // orx2Map + ADI_ADRV9025_MAP_TX3_ORX3, // orx3Map + ADI_ADRV9025_MAP_TX4_ORX4 // orx4Map + }, + { // streamGpioCfg + ADI_ADRV9025_GPIO_INVALID, // streamGpInput0 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput1 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput2 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput3 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput4 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput5 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput6 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput7 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput8 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput9 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput10 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput11 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput12 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput13 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput14 + ADI_ADRV9025_GPIO_INVALID // streamGpInput15 + }, + 2575770000U, // 2566890000U, // lo1PllFreq_Hz + 0U, // lo2PllFreq_Hz + 0U // auxPllFreq_Hz + }, + { // initCals + 0xD37FF, // calMask + 0x01, // channelMask + 0 // warmBoot + }, + { // calRsltsFile + }, + 0 // checkFwVer +}; diff --git a/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_122.88M_4.9152G_FDD2ANT.c b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_122.88M_4.9152G_FDD2ANT.c new file mode 100644 index 0000000..97bc2c2 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_122.88M_4.9152G_FDD2ANT.c @@ -0,0 +1,1354 @@ +#include "initdata.h" + +adi_adrv9025_Init_t deviceInitInst_122_88M_4_9152G_FDD2ANT = +{ + { // clocks + 122880, // deviceClock_kHz + 9830400, // clkPllVcoFreq_kHz + 0, // serdesPllVcoFreq_kHz + 0, // ldoSelect + 0, // extLoFreq1_kHz + 0, // extLoFreq2_kHz + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll1LoMode + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll2LoMode + 0, // rfPll1LoOutDivider + 0, // rfPll2LoOutDivider + ADI_ADRV9025_RFPLLMCS_NOSYNC, // rfPllPhaseSyncMode + ADI_ADRV9025_LOSEL_LO1, // rx12LoSelect + ADI_ADRV9025_LOSEL_LO1, // rx34LoSelect + ADI_ADRV9025_LOSEL_LO2, // tx12LoSelect + ADI_ADRV9025_LOSEL_LO2, // tx34LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO, // orx12LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO // orx34LoSelect + }, + { // gpInterrupts + 0x0, // gpIntMaskPin0 + 0x0 // gpIntMaskPin1 + }, + { // rx + 0x3FF, // rxInitChannelMask + { // rxChannelCfg (array) + { // rxChannelCfg[0] + { // profile + ADI_ADRV9025_RX1, // channelType + 2, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 122880, // rxOutputRate_kHz + 100000, // rfBandwidth_kHz + 100000, // rxBbf3dBCorner_kHz + 50000, // rxAdcBandWidth_kHz + { // rxFir + -6, // gain_dB + 48, // numFirCoefs + {4, 22, 23, -38, -76, 51, 174, -49, -335, 11, 579, 89, -928, -295, 1417, 672, -2107, -1354, 3153, 2693, -5046, -6187, 10155, 30139, 30139, 10155, -6187, -5046, 2693, 3153, -1354, -2107, 672, 1417, -295, -928, 89, 579, 11, -335, -49, 174, 51, -76, -38, 23, 22, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x01, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[1] + { // profile + ADI_ADRV9025_RX2, // channelType + 2, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 122880, // rxOutputRate_kHz + 100000, // rfBandwidth_kHz + 100000, // rxBbf3dBCorner_kHz + 50000, // rxAdcBandWidth_kHz + { // rxFir + -6, // gain_dB + 48, // numFirCoefs + {4, 22, 23, -38, -76, 51, 174, -49, -335, 11, 579, 89, -928, -295, 1417, 672, -2107, -1354, 3153, 2693, -5046, -6187, 10155, 30139, 30139, 10155, -6187, -5046, 2693, 3153, -1354, -2107, 672, 1417, -295, -928, 89, 579, 11, -335, -49, 174, 51, -76, -38, 23, 22, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x02, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[2] + { // profile + ADI_ADRV9025_RX3, // channelType + 2, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 122880, // rxOutputRate_kHz + 100000, // rfBandwidth_kHz + 100000, // rxBbf3dBCorner_kHz + 50000, // rxAdcBandWidth_kHz + { // rxFir + -6, // gain_dB + 48, // numFirCoefs + {4, 22, 23, -38, -76, 51, 174, -49, -335, 11, 579, 89, -928, -295, 1417, 672, -2107, -1354, 3153, 2693, -5046, -6187, 10155, 30139, 30139, 10155, -6187, -5046, 2693, 3153, -1354, -2107, 672, 1417, -295, -928, 89, 579, 11, -335, -49, 174, 51, -76, -38, 23, 22, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x04, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[3] + { // profile + ADI_ADRV9025_RX4, // channelType + 2, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 122880, // rxOutputRate_kHz + 100000, // rfBandwidth_kHz + 100000, // rxBbf3dBCorner_kHz + 50000, // rxAdcBandWidth_kHz + { // rxFir + -6, // gain_dB + 48, // numFirCoefs + {4, 22, 23, -38, -76, 51, 174, -49, -335, 11, 579, 89, -928, -295, 1417, 672, -2107, -1354, 3153, 2693, -5046, -6187, 10155, 30139, 30139, 10155, -6187, -5046, 2693, 3153, -1354, -2107, 672, 1417, -295, -928, 89, 579, 11, -335, -49, 174, 51, -76, -38, 23, 22, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x08, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[4] + { // profile + ADI_ADRV9025_ORX1, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x10, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[5] + { // profile + ADI_ADRV9025_ORX2, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x20, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[6] + { // profile + ADI_ADRV9025_ORX3, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x40, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[7] + { // profile + ADI_ADRV9025_ORX4, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x80, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[8] + { // profile + ADI_ADRV9025_LB12, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x100, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[9] + { // profile + ADI_ADRV9025_LB34, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x200, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + } + }, // rxChannelCfg (end of array) + }, + { // tx + 0x0F, // txInitChannelMask + { // txChannelCfg (array) + { // txChannelCfg[0] + { // profile + 122880, // txInputRate_kHz + 100000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {-28, 45, -82, 152, -262, 462, -893, 1945, -4588, 22882, -4588, 1945, -893, 462, -262, 152, -82, 45, -28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_3DB, // dacFullScale + 0 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_3DB // dacFullScale + }, + { // txChannelCfg[1] + { // profile + 122880, // txInputRate_kHz + 100000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {-28, 45, -82, 152, -262, 462, -893, 1945, -4588, 22882, -4588, 1945, -893, 462, -262, 152, -82, 45, -28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_3DB, // dacFullScale + 0 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_3DB // dacFullScale + }, + { // txChannelCfg[2] + { // profile + 122880, // txInputRate_kHz + 100000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {-28, 45, -82, 152, -262, 462, -893, 1945, -4588, 22882, -4588, 1945, -893, 462, -262, 152, -82, 45, -28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_3DB, // dacFullScale + 0 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_3DB // dacFullScale + }, + { // txChannelCfg[3] + { // profile + 122880, // txInputRate_kHz + 100000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {-28, 45, -82, 152, -262, 462, -893, 1945, -4588, 22882, -4588, 1945, -893, 462, -262, 152, -82, 45, -28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_3DB, // dacFullScale + 0 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_3DB // dacFullScale + } + }, // txChannelCfg (end of array) + }, + { // dataInterface + { // framer (array) + { // framer[0] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 4, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // serializerLanesEnabled + 0, // lmfcOffset + 0, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 1, // lane1FramerOutSel + 8, // lane2FramerOutSel + 8 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_RX1_I, // conv0 + ADI_ADRV9025_ADC_RX1_Q, // conv1 + ADI_ADRV9025_ADC_RX2_I, // conv2 + ADI_ADRV9025_ADC_RX2_Q, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[1] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 0, // jesd204M + 32, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 1, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 1, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[2] + 0, // enableJesd204C + 0, // bankId + 2, // deviceId + 0, // lane0Id + 0, // jesd204M + 1, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 1, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 2, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // framer (end of array) + { // deframer (array) + { // deframer[0] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 4, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // deserializerLanesEnabled + 0, // lmfcOffset + 0, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 0, // deframerInput0LaneSel + 1, // deframerInput1LaneSel + 8, // deframerInput2LaneSel + 8 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT0, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT1, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT2, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT3, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 1, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // deframer[1] + 0, // enableJesd204C + 0, // bankId + 0, // deviceId + 0, // lane0Id + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 0, // lmfcOffset + 1, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 8, // deframerInput0LaneSel + 8, // deframerInput1LaneSel + 8, // deframerInput2LaneSel + 8 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 1, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // deframer (end of array) + { // serCfg (array) + { // serCfg[0] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[1] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[2] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[3] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + } + }, // serCfg (end of array) + { // desCfg (array) + { // desCfg[0] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[1] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[2] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[3] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + } + }, // desCfg (end of array) + { // linkSharingCfg + 0, // linkSharingEnabled + 0, // linkSharingM + 0, // linkSharingS + 0, // linkSharingNp + { // linkSharingAdcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE // conv15 + }, + }, + { // dataCfg + 0, // enable + 0, // configOption1 + 0 // configOption2 + }, + 0, // channelSelect + 0 // channelMode + }, + { // adcProfiles + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0, // OrxChannel1Index + 0 // OrxChannel2Index + }, +}; + + +adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_122_88M_4_9152G_FDD2ANT = +{ + { // radioCtrlInit + { // radioCtrlModeCfg + { // txRadioCtrlModeCfg + ADI_ADRV9025_TX_EN_PIN_MODE, // txEnableMode + 0x0F // txChannelMask + }, + { // rxRadioCtrlModeCfg + ADI_ADRV9025_RX_EN_PIN_MODE, // rxEnableMode + 0xFF // rxChannelMask + }, + { // orxRadioCtrlModeCfg + ADI_ADRV9025_ORX_EN_SINGLE_CH_1PIN_MODE, // orxEnableMode + 0, // orxPinSelectSettlingDelay_armClkCycles + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel1PinModeOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel2PinModeLowOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel2PinModeHighOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE // dualChannel2PinModeOrxSel + }, + }, + { // txToOrxMapping + ADI_ADRV9025_MAP_TX1_ORX1, // orx1Map + ADI_ADRV9025_MAP_TX2_ORX2, // orx2Map + ADI_ADRV9025_MAP_TX3_ORX3, // orx3Map + ADI_ADRV9025_MAP_TX4_ORX4 // orx4Map + }, + { // streamGpioCfg + ADI_ADRV9025_GPIO_INVALID, // streamGpInput0 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput1 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput2 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput3 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput4 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput5 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput6 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput7 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput8 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput9 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput10 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput11 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput12 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput13 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput14 + ADI_ADRV9025_GPIO_INVALID // streamGpInput15 + }, + 2575770000U, // 2566890000U, // lo1PllFreq_Hz + 0U, // lo2PllFreq_Hz + 0U // auxPllFreq_Hz + }, + { // initCals + 0xD37FF, // calMask + 0x0F, // channelMask + 0 // warmBoot + }, + { // calRsltsFile + }, + 0 // checkFwVer +}; diff --git a/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_122.88M_9.8304G.c b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_122.88M_9.8304G.c new file mode 100644 index 0000000..424c001 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_122.88M_9.8304G.c @@ -0,0 +1,1354 @@ +#include "initdata.h" + +adi_adrv9025_Init_t deviceInitInst_122_88M_9_8304G = +{ + { // clocks + 122880, // deviceClock_kHz + 9830400, // clkPllVcoFreq_kHz + 0, // serdesPllVcoFreq_kHz + 0, // ldoSelect + 0, // extLoFreq1_kHz + 0, // extLoFreq2_kHz + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll1LoMode + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll2LoMode + 0, // rfPll1LoOutDivider + 0, // rfPll2LoOutDivider + ADI_ADRV9025_RFPLLMCS_NOSYNC, // rfPllPhaseSyncMode + ADI_ADRV9025_LOSEL_LO1, // rx12LoSelect + ADI_ADRV9025_LOSEL_LO1, // rx34LoSelect + ADI_ADRV9025_LOSEL_LO1, // tx12LoSelect + ADI_ADRV9025_LOSEL_LO1, // tx34LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO, // orx12LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO // orx34LoSelect + }, + { // gpInterrupts + 0x0, // gpIntMaskPin0 + 0x0 // gpIntMaskPin1 + }, + { // rx + 0x3FF, // rxInitChannelMask + { // rxChannelCfg (array) + { // rxChannelCfg[0] + { // profile + ADI_ADRV9025_RX1, // channelType + 2, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 122880, // rxOutputRate_kHz + 100000, // rfBandwidth_kHz + 100000, // rxBbf3dBCorner_kHz + 50000, // rxAdcBandWidth_kHz + { // rxFir + -6, // gain_dB + 48, // numFirCoefs + {4, 22, 23, -38, -76, 51, 174, -49, -335, 11, 579, 89, -928, -295, 1417, 672, -2107, -1354, 3153, 2693, -5046, -6187, 10155, 30139, 30139, 10155, -6187, -5046, 2693, 3153, -1354, -2107, 672, 1417, -295, -928, 89, 579, 11, -335, -49, 174, 51, -76, -38, 23, 22, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x01, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[1] + { // profile + ADI_ADRV9025_RX2, // channelType + 2, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 122880, // rxOutputRate_kHz + 100000, // rfBandwidth_kHz + 100000, // rxBbf3dBCorner_kHz + 50000, // rxAdcBandWidth_kHz + { // rxFir + -6, // gain_dB + 48, // numFirCoefs + {4, 22, 23, -38, -76, 51, 174, -49, -335, 11, 579, 89, -928, -295, 1417, 672, -2107, -1354, 3153, 2693, -5046, -6187, 10155, 30139, 30139, 10155, -6187, -5046, 2693, 3153, -1354, -2107, 672, 1417, -295, -928, 89, 579, 11, -335, -49, 174, 51, -76, -38, 23, 22, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x02, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[2] + { // profile + ADI_ADRV9025_RX3, // channelType + 2, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 122880, // rxOutputRate_kHz + 100000, // rfBandwidth_kHz + 100000, // rxBbf3dBCorner_kHz + 50000, // rxAdcBandWidth_kHz + { // rxFir + -6, // gain_dB + 48, // numFirCoefs + {4, 22, 23, -38, -76, 51, 174, -49, -335, 11, 579, 89, -928, -295, 1417, 672, -2107, -1354, 3153, 2693, -5046, -6187, 10155, 30139, 30139, 10155, -6187, -5046, 2693, 3153, -1354, -2107, 672, 1417, -295, -928, 89, 579, 11, -335, -49, 174, 51, -76, -38, 23, 22, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x04, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[3] + { // profile + ADI_ADRV9025_RX4, // channelType + 2, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 122880, // rxOutputRate_kHz + 100000, // rfBandwidth_kHz + 100000, // rxBbf3dBCorner_kHz + 50000, // rxAdcBandWidth_kHz + { // rxFir + -6, // gain_dB + 48, // numFirCoefs + {4, 22, 23, -38, -76, 51, 174, -49, -335, 11, 579, 89, -928, -295, 1417, 672, -2107, -1354, 3153, 2693, -5046, -6187, 10155, 30139, 30139, 10155, -6187, -5046, 2693, 3153, -1354, -2107, 672, 1417, -295, -928, 89, 579, 11, -335, -49, 174, 51, -76, -38, 23, 22, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x08, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[4] + { // profile + ADI_ADRV9025_ORX1, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x10, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[5] + { // profile + ADI_ADRV9025_ORX2, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x20, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[6] + { // profile + ADI_ADRV9025_ORX3, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x40, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[7] + { // profile + ADI_ADRV9025_ORX4, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x80, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[8] + { // profile + ADI_ADRV9025_LB12, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x100, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[9] + { // profile + ADI_ADRV9025_LB34, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x200, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + } + }, // rxChannelCfg (end of array) + }, + { // tx + 0x0F, // txInitChannelMask + { // txChannelCfg (array) + { // txChannelCfg[0] + { // profile + 122880, // txInputRate_kHz + 100000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {-28, 45, -82, 152, -262, 462, -893, 1945, -4588, 22882, -4588, 1945, -893, 462, -262, 152, -82, 45, -28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_3DB, // dacFullScale + 0 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_3DB // dacFullScale + }, + { // txChannelCfg[1] + { // profile + 122880, // txInputRate_kHz + 100000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {-28, 45, -82, 152, -262, 462, -893, 1945, -4588, 22882, -4588, 1945, -893, 462, -262, 152, -82, 45, -28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_3DB, // dacFullScale + 0 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_3DB // dacFullScale + }, + { // txChannelCfg[2] + { // profile + 122880, // txInputRate_kHz + 100000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {-28, 45, -82, 152, -262, 462, -893, 1945, -4588, 22882, -4588, 1945, -893, 462, -262, 152, -82, 45, -28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_3DB, // dacFullScale + 0 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_3DB // dacFullScale + }, + { // txChannelCfg[3] + { // profile + 122880, // txInputRate_kHz + 100000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {-28, 45, -82, 152, -262, 462, -893, 1945, -4588, 22882, -4588, 1945, -893, 462, -262, 152, -82, 45, -28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_3DB, // dacFullScale + 0 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_3DB // dacFullScale + } + }, // txChannelCfg (end of array) + }, + { // dataInterface + { // framer (array) + { // framer[0] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 8, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // 15, // serializerLanesEnabled + 0, // lmfcOffset + 0, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 1, // lane1FramerOutSel + 8, // lane2FramerOutSel + 8 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_RX1_I, // conv0 + ADI_ADRV9025_ADC_RX1_Q, // conv1 + ADI_ADRV9025_ADC_RX2_I, // conv2 + ADI_ADRV9025_ADC_RX2_Q, // conv3 + ADI_ADRV9025_ADC_RX3_I, // conv4 + ADI_ADRV9025_ADC_RX3_Q, // conv5 + ADI_ADRV9025_ADC_RX4_I, // conv6 + ADI_ADRV9025_ADC_RX4_Q, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[1] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 0, // jesd204M + 32, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 1, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 1, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[2] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 0, // jesd204M + 1, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 1, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 2, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // framer (end of array) + { // deframer (array) + { // deframer[0] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 8, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // 15, // deserializerLanesEnabled + 0, // lmfcOffset + 0, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 0, // deframerInput0LaneSel + 1, // deframerInput1LaneSel + 8, // deframerInput2LaneSel + 8 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT0, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT1, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT2, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT3, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT4, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT5, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT6, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT7 // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 1, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // deframer[1] + 0, // enableJesd204C + 0, // bankId + 0, // deviceId + 0, // lane0Id + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 0, // lmfcOffset + 0, // syncbOutSelect + 0, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 8, // deframerInput0LaneSel + 8, // deframerInput1LaneSel + 8, // deframerInput2LaneSel + 8 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 1, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // deframer (end of array) + { // serCfg (array) + { // serCfg[0] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[1] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[2] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[3] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + } + }, // serCfg (end of array) + { // desCfg (array) + { // desCfg[0] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[1] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[2] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[3] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + } + }, // desCfg (end of array) + { // linkSharingCfg + 0, // linkSharingEnabled + 0, // linkSharingM + 0, // linkSharingS + 0, // linkSharingNp + { // linkSharingAdcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE // conv15 + }, + }, + { // dataCfg + 0, // enable + 0, // configOption1 + 0 // configOption2 + }, + 0, // channelSelect + 0 // channelMode + }, + { // adcProfiles + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0, // OrxChannel1Index + 0 // OrxChannel2Index + }, +}; + + +adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_122_88M_9_8304G = +{ + { // radioCtrlInit + { // radioCtrlModeCfg + { // txRadioCtrlModeCfg + ADI_ADRV9025_TX_EN_PIN_MODE, // txEnableMode + 0x0F // txChannelMask + }, + { // rxRadioCtrlModeCfg + ADI_ADRV9025_RX_EN_PIN_MODE, // rxEnableMode + 0xFF // rxChannelMask + }, + { // orxRadioCtrlModeCfg + ADI_ADRV9025_ORX_EN_SINGLE_CH_1PIN_MODE, // orxEnableMode + 0, // orxPinSelectSettlingDelay_armClkCycles + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel1PinModeOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel2PinModeLowOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel2PinModeHighOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE // dualChannel2PinModeOrxSel + }, + }, + { // txToOrxMapping + ADI_ADRV9025_MAP_TX1_ORX1, // orx1Map + ADI_ADRV9025_MAP_TX2_ORX2, // orx2Map + ADI_ADRV9025_MAP_TX3_ORX3, // orx3Map + ADI_ADRV9025_MAP_TX4_ORX4 // orx4Map + }, + { // streamGpioCfg + ADI_ADRV9025_GPIO_INVALID, // streamGpInput0 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput1 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput2 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput3 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput4 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput5 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput6 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput7 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput8 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput9 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput10 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput11 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput12 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput13 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput14 + ADI_ADRV9025_GPIO_INVALID // streamGpInput15 + }, + 2575770000U, // lo1PllFreq_Hz + 0U, // lo2PllFreq_Hz + 0U // auxPllFreq_Hz + }, + { // initCals + 0x0, // 0xD37FF, // calMask + 0x0F, // channelMask + 0 // warmBoot + }, + { // calRsltsFile + }, + 0 // checkFwVer +}; diff --git a/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_122.88M_9.8304G_ORX.c b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_122.88M_9.8304G_ORX.c new file mode 100644 index 0000000..e5f41e2 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_122.88M_9.8304G_ORX.c @@ -0,0 +1,1354 @@ +#include "initdata.h" + +adi_adrv9025_Init_t deviceInitInst_122_88M_9_8304G_ORX = +{ + { // clocks + 122880, // deviceClock_kHz + 9830400, // clkPllVcoFreq_kHz + 0, // serdesPllVcoFreq_kHz + 0, // ldoSelect + 0, // extLoFreq1_kHz + 0, // extLoFreq2_kHz + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll1LoMode + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll2LoMode + 0, // rfPll1LoOutDivider + 0, // rfPll2LoOutDivider + ADI_ADRV9025_RFPLLMCS_NOSYNC, // rfPllPhaseSyncMode + ADI_ADRV9025_LOSEL_LO1, // rx12LoSelect + ADI_ADRV9025_LOSEL_LO1, // rx34LoSelect + ADI_ADRV9025_LOSEL_LO1, // tx12LoSelect + ADI_ADRV9025_LOSEL_LO1, // tx34LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO, // orx12LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO // orx34LoSelect + }, + { // gpInterrupts + 0x0, // gpIntMaskPin0 + 0x0 // gpIntMaskPin1 + }, + { // rx + 0x3FF, // rxInitChannelMask + { // rxChannelCfg (array) + { // rxChannelCfg[0] + { // profile + ADI_ADRV9025_RX1, // channelType + 2, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 122880, // rxOutputRate_kHz + 100000, // rfBandwidth_kHz + 100000, // rxBbf3dBCorner_kHz + 50000, // rxAdcBandWidth_kHz + { // rxFir + -6, // gain_dB + 48, // numFirCoefs + {4, 22, 23, -38, -76, 51, 174, -49, -335, 11, 579, 89, -928, -295, 1417, 672, -2107, -1354, 3153, 2693, -5046, -6187, 10155, 30139, 30139, 10155, -6187, -5046, 2693, 3153, -1354, -2107, 672, 1417, -295, -928, 89, 579, 11, -335, -49, 174, 51, -76, -38, 23, 22, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x01, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[1] + { // profile + ADI_ADRV9025_RX2, // channelType + 2, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 122880, // rxOutputRate_kHz + 100000, // rfBandwidth_kHz + 100000, // rxBbf3dBCorner_kHz + 50000, // rxAdcBandWidth_kHz + { // rxFir + -6, // gain_dB + 48, // numFirCoefs + {4, 22, 23, -38, -76, 51, 174, -49, -335, 11, 579, 89, -928, -295, 1417, 672, -2107, -1354, 3153, 2693, -5046, -6187, 10155, 30139, 30139, 10155, -6187, -5046, 2693, 3153, -1354, -2107, 672, 1417, -295, -928, 89, 579, 11, -335, -49, 174, 51, -76, -38, 23, 22, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x02, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[2] + { // profile + ADI_ADRV9025_RX3, // channelType + 2, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 122880, // rxOutputRate_kHz + 100000, // rfBandwidth_kHz + 100000, // rxBbf3dBCorner_kHz + 50000, // rxAdcBandWidth_kHz + { // rxFir + -6, // gain_dB + 48, // numFirCoefs + {4, 22, 23, -38, -76, 51, 174, -49, -335, 11, 579, 89, -928, -295, 1417, 672, -2107, -1354, 3153, 2693, -5046, -6187, 10155, 30139, 30139, 10155, -6187, -5046, 2693, 3153, -1354, -2107, 672, 1417, -295, -928, 89, 579, 11, -335, -49, 174, 51, -76, -38, 23, 22, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x04, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[3] + { // profile + ADI_ADRV9025_RX4, // channelType + 2, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 122880, // rxOutputRate_kHz + 100000, // rfBandwidth_kHz + 100000, // rxBbf3dBCorner_kHz + 50000, // rxAdcBandWidth_kHz + { // rxFir + -6, // gain_dB + 48, // numFirCoefs + {4, 22, 23, -38, -76, 51, 174, -49, -335, 11, 579, 89, -928, -295, 1417, 672, -2107, -1354, 3153, 2693, -5046, -6187, 10155, 30139, 30139, 10155, -6187, -5046, 2693, 3153, -1354, -2107, 672, 1417, -295, -928, 89, 579, 11, -335, -49, 174, 51, -76, -38, 23, 22, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x08, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[4] + { // profile + ADI_ADRV9025_ORX1, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x10, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[5] + { // profile + ADI_ADRV9025_ORX2, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x20, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[6] + { // profile + ADI_ADRV9025_ORX3, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x40, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[7] + { // profile + ADI_ADRV9025_ORX4, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x80, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[8] + { // profile + ADI_ADRV9025_LB12, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x100, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[9] + { // profile + ADI_ADRV9025_LB34, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x200, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + } + }, // rxChannelCfg (end of array) + }, + { // tx + 0x0F, // txInitChannelMask + { // txChannelCfg (array) + { // txChannelCfg[0] + { // profile + 122880, // txInputRate_kHz + 100000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {-28, 45, -82, 152, -262, 462, -893, 1945, -4588, 22882, -4588, 1945, -893, 462, -262, 152, -82, 45, -28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_3DB, // dacFullScale + 0 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_3DB // dacFullScale + }, + { // txChannelCfg[1] + { // profile + 122880, // txInputRate_kHz + 100000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {-28, 45, -82, 152, -262, 462, -893, 1945, -4588, 22882, -4588, 1945, -893, 462, -262, 152, -82, 45, -28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_3DB, // dacFullScale + 0 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_3DB // dacFullScale + }, + { // txChannelCfg[2] + { // profile + 122880, // txInputRate_kHz + 100000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {-28, 45, -82, 152, -262, 462, -893, 1945, -4588, 22882, -4588, 1945, -893, 462, -262, 152, -82, 45, -28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_3DB, // dacFullScale + 0 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_3DB // dacFullScale + }, + { // txChannelCfg[3] + { // profile + 122880, // txInputRate_kHz + 100000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {-28, 45, -82, 152, -262, 462, -893, 1945, -4588, 22882, -4588, 1945, -893, 462, -262, 152, -82, 45, -28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_3DB, // dacFullScale + 0 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_3DB // dacFullScale + } + }, // txChannelCfg (end of array) + }, + { // dataInterface + { // framer (array) + { // framer[0] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 8, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // serializerLanesEnabled + 0, // lmfcOffset + 0, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 1, // lane1FramerOutSel + 8, // lane2FramerOutSel + 8 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_RX1_I, // conv0 + ADI_ADRV9025_ADC_RX1_Q, // conv1 + ADI_ADRV9025_ADC_RX2_I, // conv2 + ADI_ADRV9025_ADC_RX2_Q, // conv3 + ADI_ADRV9025_ADC_RX3_I, // conv4 + ADI_ADRV9025_ADC_RX3_Q, // conv5 + ADI_ADRV9025_ADC_RX4_I, // conv6 + ADI_ADRV9025_ADC_RX4_Q, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[1] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 2, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 4, // serializerLanesEnabled + 0, // lmfcOffset + 1, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 8, // lane0FramerOutSel + 8, // lane1FramerOutSel + 0, // lane2FramerOutSel + 8 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_ORX1_I, // conv0 + ADI_ADRV9025_ADC_ORX1_Q, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[2] + 0, // enableJesd204C + 0, // bankId + 2, // deviceId + 0, // lane0Id + 0, // jesd204M + 1, // deviceId + 0, // lane0Id + 0, // jesd204Np + 0, // jesd204E + 1, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 2, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 8, // lane0FramerOutSel + 8, // lane1FramerOutSel + 8, // lane2FramerOutSel + 8 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // framer (end of array) + { // deframer (array) + { // deframer[0] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // 15, // deserializerLanesEnabled + 0, // lmfcOffset + 0, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 0, // deframerInput0LaneSel + 1, // deframerInput1LaneSel + 2, // deframerInput2LaneSel + 3 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT0, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT1, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT2, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT3, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT4, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT5, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT6, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT7 // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 1, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // deframer[1] + 0, // enableJesd204C + 0, // bankId + 0, // deviceId + 0, // lane0Id + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 0, // lmfcOffset + 1, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 8, // deframerInput0LaneSel + 8, // deframerInput1LaneSel + 8, // deframerInput2LaneSel + 8 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 1, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // deframer (end of array) + { // serCfg (array) + { // serCfg[0] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[1] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[2] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[3] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + } + }, // serCfg (end of array) + { // desCfg (array) + { // desCfg[0] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[1] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[2] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[3] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + } + }, // desCfg (end of array) + { // linkSharingCfg + 0, // linkSharingEnabled + 0, // linkSharingM + 0, // linkSharingS + 0, // linkSharingNp + { // linkSharingAdcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE // conv15 + }, + }, + { // dataCfg + 0, // enable + 0, // configOption1 + 0 // configOption2 + }, + 0, // channelSelect + 0 // channelMode + }, + { // adcProfiles + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0, // OrxChannel1Index + 0 // OrxChannel2Index + }, +}; + + +adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_122_88M_9_8304G_ORX = +{ + { // radioCtrlInit + { // radioCtrlModeCfg + { // txRadioCtrlModeCfg + ADI_ADRV9025_TX_EN_PIN_MODE, // txEnableMode + 0x0F // txChannelMask + }, + { // rxRadioCtrlModeCfg + ADI_ADRV9025_RX_EN_PIN_MODE, // rxEnableMode + 0xFF // rxChannelMask + }, + { // orxRadioCtrlModeCfg + ADI_ADRV9025_ORX_EN_SINGLE_CH_1PIN_MODE, // orxEnableMode + 0, // orxPinSelectSettlingDelay_armClkCycles + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel1PinModeOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX1_FE, // singleChannel2PinModeLowOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel2PinModeHighOrxSel + ADI_ADRV9025_DUAL_CH_PIN_MODE_ORX1_ORX3_SEL // dualChannel2PinModeOrxSel + }, + }, + { // txToOrxMapping + ADI_ADRV9025_MAP_TX1_ORX1, // orx1Map + ADI_ADRV9025_MAP_TX2_ORX2, // orx2Map + ADI_ADRV9025_MAP_TX3_ORX3, // orx3Map + ADI_ADRV9025_MAP_TX4_ORX4 // orx4Map + }, + { // streamGpioCfg + ADI_ADRV9025_GPIO_INVALID, // streamGpInput0 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput1 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput2 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput3 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput4 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput5 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput6 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput7 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput8 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput9 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput10 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput11 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput12 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput13 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput14 + ADI_ADRV9025_GPIO_INVALID // streamGpInput15 + }, + 2575770000U, // lo1PllFreq_Hz + 0U, // lo2PllFreq_Hz + 0U // auxPllFreq_Hz + }, + { // initCals + 0xD37FF, // calMask + 0x0F, // channelMask + 0 // warmBoot + }, + { // calRsltsFile + }, + 0 // checkFwVer +}; diff --git a/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_240M.c.bak b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_240M.c.bak new file mode 100644 index 0000000..c5a5ec8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_240M.c.bak @@ -0,0 +1,1354 @@ +#include "initdata.h" + +adi_adrv9025_Init_t deviceInitInst_240M = +{ + { // clocks + 122880, // deviceClock_kHz + 9830400, // clkPllVcoFreq_kHz + 0, // serdesPllVcoFreq_kHz + 0, // ldoSelect + 0, // extLoFreq1_kHz + 0, // extLoFreq2_kHz + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll1LoMode + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll2LoMode + 0, // rfPll1LoOutDivider + 0, // rfPll2LoOutDivider + ADI_ADRV9025_RFPLLMCS_NOSYNC, // rfPllPhaseSyncMode + ADI_ADRV9025_LOSEL_LO1, // rx12LoSelect + ADI_ADRV9025_LOSEL_LO1, // rx34LoSelect + ADI_ADRV9025_LOSEL_LO1, // tx12LoSelect + ADI_ADRV9025_LOSEL_LO1, // tx34LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO, // orx12LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO // orx34LoSelect + }, + { // gpInterrupts + 0x0, // gpIntMaskPin0 + 0x0 // gpIntMaskPin1 + }, + { // rx + 0x3FF, // rxInitChannelMask + { // rxChannelCfg (array) + { // rxChannelCfg[0] + { // profile + ADI_ADRV9025_RX1, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 300000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-20, 36, -8, 1, 4, 30, -51, 13, 100, -154, -888, 18538, -888, -154, 100, 13, -51, 30, 4, 1, -8, 36, -20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x01, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_12BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[1] + { // profile + ADI_ADRV9025_RX2, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 300000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-20, 36, -8, 1, 4, 30, -51, 13, 100, -154, -888, 18538, -888, -154, 100, 13, -51, 30, 4, 1, -8, 36, -20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x02, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_12BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[2] + { // profile + ADI_ADRV9025_RX3, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 300000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-20, 36, -8, 1, 4, 30, -51, 13, 100, -154, -888, 18538, -888, -154, 100, 13, -51, 30, 4, 1, -8, 36, -20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x04, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_12BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[3] + { // profile + ADI_ADRV9025_RX4, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 300000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-20, 36, -8, 1, 4, 30, -51, 13, 100, -154, -888, 18538, -888, -154, 100, 13, -51, 30, 4, 1, -8, 36, -20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x08, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_12BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[4] + { // profile + ADI_ADRV9025_ORX1, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x10, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[5] + { // profile + ADI_ADRV9025_ORX2, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x20, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[6] + { // profile + ADI_ADRV9025_ORX3, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x40, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[7] + { // profile + ADI_ADRV9025_ORX4, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x80, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[8] + { // profile + ADI_ADRV9025_LB12, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x100, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[9] + { // profile + ADI_ADRV9025_LB34, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x200, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + } + }, // rxChannelCfg (end of array) + }, + { // tx + 0x0F, // txInitChannelMask + { // txChannelCfg (array) + { // txChannelCfg[0] + { // profile + 245760, // txInputRate_kHz + 200000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // dpdHb2Interpolation + 1, // txFirInterpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 0, // gain_dB + 20, // numFirCoefs + {150, -1580, 4231, -4275, -1981, 8637, -2338, -13408, 10714, 32466, 10714, -13408, -2338, 8637, -1981, -4275, 4231, -1580, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[1] + { // profile + 245760, // txInputRate_kHz + 200000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // dpdHb2Interpolation + 1, // txFirInterpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 0, // gain_dB + 20, // numFirCoefs + {150, -1580, 4231, -4275, -1981, 8637, -2338, -13408, 10714, 32466, 10714, -13408, -2338, 8637, -1981, -4275, 4231, -1580, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[2] + { // profile + 245760, // txInputRate_kHz + 200000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // dpdHb2Interpolation + 1, // txFirInterpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 0, // gain_dB + 20, // numFirCoefs + {150, -1580, 4231, -4275, -1981, 8637, -2338, -13408, 10714, 32466, 10714, -13408, -2338, 8637, -1981, -4275, 4231, -1580, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[3] + { // profile + 245760, // txInputRate_kHz + 200000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // dpdHb2Interpolation + 1, // txFirInterpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 0, // gain_dB + 20, // numFirCoefs + {150, -1580, 4231, -4275, -1981, 8637, -2338, -13408, 10714, 32466, 10714, -13408, -2338, 8637, -1981, -4275, 4231, -1580, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + } + }, // txChannelCfg (end of array) + }, + { // dataInterface + { // framer (array) + { // framer[0] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0, // lmfcOffset + 0, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 1, // lane1FramerOutSel + 2, // lane2FramerOutSel + 3 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_RX1_I, // conv0 + ADI_ADRV9025_ADC_RX1_Q, // conv1 + ADI_ADRV9025_ADC_RX2_I, // conv2 + ADI_ADRV9025_ADC_RX2_Q, // conv3 + ADI_ADRV9025_ADC_RX3_I, // conv4 + ADI_ADRV9025_ADC_RX3_Q, // conv5 + ADI_ADRV9025_ADC_RX4_I, // conv6 + ADI_ADRV9025_ADC_RX4_Q, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[1] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 0, // jesd204M + 32, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 1, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 1, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[2] + 0, // enableJesd204C + 0, // bankId + 2, // deviceId + 0, // lane0Id + 0, // jesd204M + 1, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 1, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 2, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // framer (end of array) + { // deframer (array) + { // deframer[0] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // deserializerLanesEnabled + 0, // lmfcOffset + 0, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 0, // deframerInput0LaneSel + 1, // deframerInput1LaneSel + 2, // deframerInput2LaneSel + 3 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT0, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT1, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT2, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT3, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT4, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT5, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT6, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT7 // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 1, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // deframer[1] + 0, // enableJesd204C + 0, // bankId + 0, // deviceId + 0, // lane0Id + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 0, // lmfcOffset + 1, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 8, // deframerInput0LaneSel + 8, // deframerInput1LaneSel + 8, // deframerInput2LaneSel + 8 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 1, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // deframer (end of array) + { // serCfg (array) + { // serCfg[0] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[1] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[2] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[3] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + } + }, // serCfg (end of array) + { // desCfg (array) + { // desCfg[0] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[1] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[2] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[3] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + } + }, // desCfg (end of array) + { // linkSharingCfg + 0, // linkSharingEnabled + 0, // linkSharingM + 0, // linkSharingS + 0, // linkSharingNp + { // linkSharingAdcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE // conv15 + }, + }, + { // dataCfg + 0, // enable + 0, // configOption1 + 0 // configOption2 + }, + 0, // channelSelect + 0 // channelMode + }, + { // adcProfiles + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0, // OrxChannel1Index + 0 // OrxChannel2Index + }, +}; + + +adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_240M = +{ + { // radioCtrlInit + { // radioCtrlModeCfg + { // txRadioCtrlModeCfg + ADI_ADRV9025_TX_EN_PIN_MODE, // txEnableMode + 0x0F // txChannelMask + }, + { // rxRadioCtrlModeCfg + ADI_ADRV9025_RX_EN_PIN_MODE, // rxEnableMode + 0xFF // rxChannelMask + }, + { // orxRadioCtrlModeCfg + ADI_ADRV9025_ORX_EN_SINGLE_CH_1PIN_MODE, // orxEnableMode + 0, // orxPinSelectSettlingDelay_armClkCycles + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel1PinModeOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel2PinModeLowOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel2PinModeHighOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE // dualChannel2PinModeOrxSel + }, + }, + { // txToOrxMapping + ADI_ADRV9025_MAP_TX1_ORX1, // orx1Map + ADI_ADRV9025_MAP_TX2_ORX2, // orx2Map + ADI_ADRV9025_MAP_TX3_ORX3, // orx3Map + ADI_ADRV9025_MAP_TX4_ORX4 // orx4Map + }, + { // streamGpioCfg + ADI_ADRV9025_GPIO_INVALID, // streamGpInput0 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput1 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput2 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput3 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput4 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput5 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput6 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput7 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput8 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput9 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput10 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput11 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput12 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput13 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput14 + ADI_ADRV9025_GPIO_INVALID // streamGpInput15 + }, + 2575770000U, // lo1PllFreq_Hz + 0U, // lo2PllFreq_Hz + 0U // auxPllFreq_Hz + }, + { // initCals + 0xD27FF, // calMask + 0x0F, // channelMask + 0 // warmBoot + }, + { // calRsltsFile + }, + 0 // checkFwVer +}; diff --git a/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_245.76M_9.8304G.c b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_245.76M_9.8304G.c new file mode 100644 index 0000000..df6edfc --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_245.76M_9.8304G.c @@ -0,0 +1,1354 @@ +#include "initdata.h" + +adi_adrv9025_Init_t deviceInitInst_245_76M_9_8304G = +{ + { // clocks + 122880, // deviceClock_kHz + 9830400, // clkPllVcoFreq_kHz + 0, // serdesPllVcoFreq_kHz + 0, // ldoSelect + 0, // extLoFreq1_kHz + 0, // extLoFreq2_kHz + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll1LoMode + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll2LoMode + 0, // rfPll1LoOutDivider + 0, // rfPll2LoOutDivider + ADI_ADRV9025_RFPLLMCS_NOSYNC, // rfPllPhaseSyncMode + ADI_ADRV9025_LOSEL_LO1, // rx12LoSelect + ADI_ADRV9025_LOSEL_LO1, // rx34LoSelect + ADI_ADRV9025_LOSEL_LO1, // tx12LoSelect + ADI_ADRV9025_LOSEL_LO1, // tx34LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO, // orx12LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO // orx34LoSelect + }, + { // gpInterrupts + 0x0, // gpIntMaskPin0 + 0x0 // gpIntMaskPin1 + }, + { // rx + 0x3FF, // rxInitChannelMask + { // rxChannelCfg (array) + { // rxChannelCfg[0] + { // profile + ADI_ADRV9025_RX1, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 200000, // rfBandwidth_kHz + 200000, // rxBbf3dBCorner_kHz + 100000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-10, 4, -1, -2, 8, -15, 21, -21, 7, 59, -502, 17153, -502, 59, 7, -21, 21, -15, 8, -2, -1, 4, -10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x01, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[1] + { // profile + ADI_ADRV9025_RX2, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 200000, // rfBandwidth_kHz + 200000, // rxBbf3dBCorner_kHz + 100000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-10, 4, -1, -2, 8, -15, 21, -21, 7, 59, -502, 17153, -502, 59, 7, -21, 21, -15, 8, -2, -1, 4, -10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x02, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[2] + { // profile + ADI_ADRV9025_RX3, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 200000, // rfBandwidth_kHz + 200000, // rxBbf3dBCorner_kHz + 100000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-10, 4, -1, -2, 8, -15, 21, -21, 7, 59, -502, 17153, -502, 59, 7, -21, 21, -15, 8, -2, -1, 4, -10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x04, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[3] + { // profile + ADI_ADRV9025_RX4, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 200000, // rfBandwidth_kHz + 200000, // rxBbf3dBCorner_kHz + 100000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-10, 4, -1, -2, 8, -15, 21, -21, 7, 59, -502, 17153, -502, 59, 7, -21, 21, -15, 8, -2, -1, 4, -10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x08, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[4] + { // profile + ADI_ADRV9025_ORX1, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x10, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[5] + { // profile + ADI_ADRV9025_ORX2, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x20, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[6] + { // profile + ADI_ADRV9025_ORX3, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x40, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[7] + { // profile + ADI_ADRV9025_ORX4, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x80, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[8] + { // profile + ADI_ADRV9025_LB12, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x100, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[9] + { // profile + ADI_ADRV9025_LB34, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x200, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + } + }, // rxChannelCfg (end of array) + }, + { // tx + 0x0F, // txInitChannelMask + { // txChannelCfg (array) + { // txChannelCfg[0] + { // profile + 245760, // txInputRate_kHz + 200000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 1, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 0, // gain_dB + 20, // numFirCoefs + {150, -1580, 4231, -4275, -1981, 8637, -2338, -13408, 10714, 32466, 10714, -13408, -2338, 8637, -1981, -4275, 4231, -1580, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[1] + { // profile + 245760, // txInputRate_kHz + 200000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 1, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 0, // gain_dB + 20, // numFirCoefs + {150, -1580, 4231, -4275, -1981, 8637, -2338, -13408, 10714, 32466, 10714, -13408, -2338, 8637, -1981, -4275, 4231, -1580, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[2] + { // profile + 245760, // txInputRate_kHz + 200000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 1, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 0, // gain_dB + 20, // numFirCoefs + {150, -1580, 4231, -4275, -1981, 8637, -2338, -13408, 10714, 32466, 10714, -13408, -2338, 8637, -1981, -4275, 4231, -1580, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[3] + { // profile + 245760, // txInputRate_kHz + 200000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 1, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 0, // gain_dB + 20, // numFirCoefs + {150, -1580, 4231, -4275, -1981, 8637, -2338, -13408, 10714, 32466, 10714, -13408, -2338, 8637, -1981, -4275, 4231, -1580, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + } + }, // txChannelCfg (end of array) + }, + { // dataInterface + { // framer (array) + { // framer[0] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0, // lmfcOffset + 0, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 1, // lane1FramerOutSel + 2, // lane2FramerOutSel + 3 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_RX1_I, // conv0 + ADI_ADRV9025_ADC_RX1_Q, // conv1 + ADI_ADRV9025_ADC_RX2_I, // conv2 + ADI_ADRV9025_ADC_RX2_Q, // conv3 + ADI_ADRV9025_ADC_RX3_I, // conv4 + ADI_ADRV9025_ADC_RX3_Q, // conv5 + ADI_ADRV9025_ADC_RX4_I, // conv6 + ADI_ADRV9025_ADC_RX4_Q, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[1] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 0, // jesd204M + 32, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 1, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 1, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[2] + 0, // enableJesd204C + 0, // bankId + 2, // deviceId + 0, // lane0Id + 0, // jesd204M + 1, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 1, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 2, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // framer (end of array) + { // deframer (array) + { // deframer[0] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // deserializerLanesEnabled + 0, // lmfcOffset + 0, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 0, // deframerInput0LaneSel + 1, // deframerInput1LaneSel + 2, // deframerInput2LaneSel + 3 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT0, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT1, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT2, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT3, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT4, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT5, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT6, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT7 // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 1, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // deframer[1] + 0, // enableJesd204C + 0, // bankId + 0, // deviceId + 0, // lane0Id + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 0, // lmfcOffset + 1, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 8, // deframerInput0LaneSel + 8, // deframerInput1LaneSel + 8, // deframerInput2LaneSel + 8 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 1, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // deframer (end of array) + { // serCfg (array) + { // serCfg[0] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[1] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[2] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[3] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + } + }, // serCfg (end of array) + { // desCfg (array) + { // desCfg[0] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[1] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[2] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[3] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + } + }, // desCfg (end of array) + { // linkSharingCfg + 0, // linkSharingEnabled + 0, // linkSharingM + 0, // linkSharingS + 0, // linkSharingNp + { // linkSharingAdcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE // conv15 + }, + }, + { // dataCfg + 0, // enable + 0, // configOption1 + 0 // configOption2 + }, + 0, // channelSelect + 0 // channelMode + }, + { // adcProfiles + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0, // OrxChannel1Index + 0 // OrxChannel2Index + }, +}; + + +adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_245_76M_9_8304G = +{ + { // radioCtrlInit + { // radioCtrlModeCfg + { // txRadioCtrlModeCfg + ADI_ADRV9025_TX_EN_PIN_MODE, // txEnableMode + 0x0F // txChannelMask + }, + { // rxRadioCtrlModeCfg + ADI_ADRV9025_RX_EN_PIN_MODE, // rxEnableMode + 0xFF // rxChannelMask + }, + { // orxRadioCtrlModeCfg + ADI_ADRV9025_ORX_EN_SINGLE_CH_1PIN_MODE, // orxEnableMode + 0, // orxPinSelectSettlingDelay_armClkCycles + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel1PinModeOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel2PinModeLowOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel2PinModeHighOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE // dualChannel2PinModeOrxSel + }, + }, + { // txToOrxMapping + ADI_ADRV9025_MAP_TX1_ORX1, // orx1Map + ADI_ADRV9025_MAP_TX2_ORX2, // orx2Map + ADI_ADRV9025_MAP_TX3_ORX3, // orx3Map + ADI_ADRV9025_MAP_TX4_ORX4 // orx4Map + }, + { // streamGpioCfg + ADI_ADRV9025_GPIO_INVALID, // streamGpInput0 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput1 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput2 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput3 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput4 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput5 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput6 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput7 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput8 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput9 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput10 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput11 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput12 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput13 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput14 + ADI_ADRV9025_GPIO_INVALID // streamGpInput15 + }, + 2575770000U, // lo1PllFreq_Hz + 0U, // lo2PllFreq_Hz + 0U // auxPllFreq_Hz + }, + { // initCals + 0xD37FF, // calMask + 0x01, // channelMask + 0 // warmBoot + }, + { // calRsltsFile + }, + 0 // checkFwVer +}; diff --git a/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_61.44M_4.9152G_FDD2ANT.c b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_61.44M_4.9152G_FDD2ANT.c new file mode 100644 index 0000000..d84c2ba --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_61.44M_4.9152G_FDD2ANT.c @@ -0,0 +1,1354 @@ +#include "initdata.h" + +adi_adrv9025_Init_t deviceInitInst_61_44M_4_9152G_FDD2ANT = +{ + { // clocks + 122880, // deviceClock_kHz + 9830400, // clkPllVcoFreq_kHz + 0, // serdesPllVcoFreq_kHz + 0, // ldoSelect + 0, // extLoFreq1_kHz + 0, // extLoFreq2_kHz + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll1LoMode + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll2LoMode + 0, // rfPll1LoOutDivider + 0, // rfPll2LoOutDivider + ADI_ADRV9025_RFPLLMCS_NOSYNC, // rfPllPhaseSyncMode + ADI_ADRV9025_LOSEL_LO1, // rx12LoSelect + ADI_ADRV9025_LOSEL_LO1, // rx34LoSelect + ADI_ADRV9025_LOSEL_LO2, // tx12LoSelect + ADI_ADRV9025_LOSEL_LO2, // tx34LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO, // orx12LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO // orx34LoSelect + }, + { // gpInterrupts + 0x0, // gpIntMaskPin0 + 0x0 // gpIntMaskPin1 + }, + { // rx + 0x3FF, // rxInitChannelMask + { // rxChannelCfg (array) + { // rxChannelCfg[0] + { // profile + ADI_ADRV9025_RX1, // channelType + 1, // rxFirDecimation + 1, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 2, // rhb3Decimation + 2, // rxFir1Decimation + 2, // rxFir2Decimation + 61440, // rxOutputRate_kHz + 20000, // rfBandwidth_kHz + 20000, // rxBbf3dBCorner_kHz + 10000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {25, -46, 3, -29, 29, 20, 38, -44, -131, -282, -370, 17847, -370, -282, -131, -44, 38, 20, 29, -29, 3, -46, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x01, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[1] + { // profile + ADI_ADRV9025_RX2, // channelType + 1, // rxFirDecimation + 1, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 2, // rhb3Decimation + 2, // rxFir1Decimation + 2, // rxFir2Decimation + 61440, // rxOutputRate_kHz + 20000, // rfBandwidth_kHz + 20000, // rxBbf3dBCorner_kHz + 10000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {25, -46, 3, -29, 29, 20, 38, -44, -131, -282, -370, 17847, -370, -282, -131, -44, 38, 20, 29, -29, 3, -46, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x02, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[2] + { // profile + ADI_ADRV9025_RX3, // channelType + 1, // rxFirDecimation + 1, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 2, // rhb3Decimation + 2, // rxFir1Decimation + 2, // rxFir2Decimation + 61440, // rxOutputRate_kHz + 20000, // rfBandwidth_kHz + 20000, // rxBbf3dBCorner_kHz + 10000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {25, -46, 3, -29, 29, 20, 38, -44, -131, -282, -370, 17847, -370, -282, -131, -44, 38, 20, 29, -29, 3, -46, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x04, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[3] + { // profile + ADI_ADRV9025_RX4, // channelType + 1, // rxFirDecimation + 1, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 2, // rhb3Decimation + 2, // rxFir1Decimation + 2, // rxFir2Decimation + 61440, // rxOutputRate_kHz + 20000, // rfBandwidth_kHz + 20000, // rxBbf3dBCorner_kHz + 10000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {25, -46, 3, -29, 29, 20, 38, -44, -131, -282, -370, 17847, -370, -282, -131, -44, 38, 20, 29, -29, 3, -46, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x08, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[4] + { // profile + ADI_ADRV9025_ORX1, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 225000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 112500, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {6, 0, 2, -1, 1, 4, -8, 17, -36, 100, -446, 17182, -446, 100, -36, 17, -8, 4, 1, -1, 2, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x10, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[5] + { // profile + ADI_ADRV9025_ORX2, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 225000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 112500, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {6, 0, 2, -1, 1, 4, -8, 17, -36, 100, -446, 17182, -446, 100, -36, 17, -8, 4, 1, -1, 2, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x20, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[6] + { // profile + ADI_ADRV9025_ORX3, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 225000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 112500, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {6, 0, 2, -1, 1, 4, -8, 17, -36, 100, -446, 17182, -446, 100, -36, 17, -8, 4, 1, -1, 2, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x40, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[7] + { // profile + ADI_ADRV9025_ORX4, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 225000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 112500, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {6, 0, 2, -1, 1, 4, -8, 17, -36, 100, -446, 17182, -446, 100, -36, 17, -8, 4, 1, -1, 2, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x80, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[8] + { // profile + ADI_ADRV9025_LB12, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 225000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 112500, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {6, 0, 2, -1, 1, 4, -8, 17, -36, 100, -446, 17182, -446, 100, -36, 17, -8, 4, 1, -1, 2, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x100, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[9] + { // profile + ADI_ADRV9025_LB34, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 225000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 112500, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {6, 0, 2, -1, 1, 4, -8, 17, -36, 100, -446, 17182, -446, 100, -36, 17, -8, 4, 1, -1, 2, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x200, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + } + }, // rxChannelCfg (end of array) + }, + { // tx + 0x0F, // txInitChannelMask + { // txChannelCfg (array) + { // txChannelCfg[0] + { // profile + 61440, // txInputRate_kHz + 40000, // primarySigBandwidth_kHz + 225000, // rfBandwidth_kHz + 225000, // txDac3dBCorner_kHz + 112500, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 2, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 80, // numFirCoefs + {-11, -17, 29, 23, -45, -34, 63, 56, -94, -75, 126, 106, -167, -145, 220, 190, -277, -252, 351, 323, -435, -410, 545, 538, -668, -684, 820, 890, -1013, -1167, 1259, 1575, -1586, -2235, 2035, 3443, -2558, -5848, 3874, 17638, 17638, 3874, -5848, -2558, 3443, 2035, -2235, -1586, 1575, 1259, -1167, -1013, 890, 820, -684, -668, 538, 545, -410, -435, 323, 351, -252, -277, 190, 220, -145, -167, 106, 126, -75, -94, 56, 63, -34, -45, 23, 29, -17, -11}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[1] + { // profile + 61440, // txInputRate_kHz + 40000, // primarySigBandwidth_kHz + 225000, // rfBandwidth_kHz + 225000, // txDac3dBCorner_kHz + 112500, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 2, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 80, // numFirCoefs + {-11, -17, 29, 23, -45, -34, 63, 56, -94, -75, 126, 106, -167, -145, 220, 190, -277, -252, 351, 323, -435, -410, 545, 538, -668, -684, 820, 890, -1013, -1167, 1259, 1575, -1586, -2235, 2035, 3443, -2558, -5848, 3874, 17638, 17638, 3874, -5848, -2558, 3443, 2035, -2235, -1586, 1575, 1259, -1167, -1013, 890, 820, -684, -668, 538, 545, -410, -435, 323, 351, -252, -277, 190, 220, -145, -167, 106, 126, -75, -94, 56, 63, -34, -45, 23, 29, -17, -11}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[2] + { // profile + 61440, // txInputRate_kHz + 40000, // primarySigBandwidth_kHz + 225000, // rfBandwidth_kHz + 225000, // txDac3dBCorner_kHz + 112500, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 2, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 80, // numFirCoefs + {-11, -17, 29, 23, -45, -34, 63, 56, -94, -75, 126, 106, -167, -145, 220, 190, -277, -252, 351, 323, -435, -410, 545, 538, -668, -684, 820, 890, -1013, -1167, 1259, 1575, -1586, -2235, 2035, 3443, -2558, -5848, 3874, 17638, 17638, 3874, -5848, -2558, 3443, 2035, -2235, -1586, 1575, 1259, -1167, -1013, 890, 820, -684, -668, 538, 545, -410, -435, 323, 351, -252, -277, 190, 220, -145, -167, 106, 126, -75, -94, 56, 63, -34, -45, 23, 29, -17, -11}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[3] + { // profile + 61440, // txInputRate_kHz + 40000, // primarySigBandwidth_kHz + 225000, // rfBandwidth_kHz + 225000, // txDac3dBCorner_kHz + 112500, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 2, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 80, // numFirCoefs + {-11, -17, 29, 23, -45, -34, 63, 56, -94, -75, 126, 106, -167, -145, 220, 190, -277, -252, 351, 323, -435, -410, 545, 538, -668, -684, 820, 890, -1013, -1167, 1259, 1575, -1586, -2235, 2035, 3443, -2558, -5848, 3874, 17638, 17638, 3874, -5848, -2558, 3443, 2035, -2235, -1586, 1575, 1259, -1167, -1013, 890, 820, -684, -668, 538, 545, -410, -435, 323, 351, -252, -277, 190, 220, -145, -167, 106, 126, -75, -94, 56, 63, -34, -45, 23, 29, -17, -11}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + } + }, // txChannelCfg (end of array) + }, + { // dataInterface + { // framer (array) + { // framer[0] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 4, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 1, // 15, // serializerLanesEnabled + 0, // lmfcOffset + 0, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 8, // lane1FramerOutSel + 8, // lane2FramerOutSel + 8 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_RX1_I, // conv0 + ADI_ADRV9025_ADC_RX1_Q, // conv1 + ADI_ADRV9025_ADC_RX2_I, // conv2 + ADI_ADRV9025_ADC_RX2_Q, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[1] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 0, // jesd204M + 32, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 1, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 1, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[2] + 0, // enableJesd204C + 0, // bankId + 2, // deviceId + 0, // lane0Id + 0, // jesd204M + 1, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 1, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 2, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // framer (end of array) + { // deframer (array) + { // deframer[0] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 4, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 1, // 15, // deserializerLanesEnabled + 0, // lmfcOffset + 0, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 0, // deframerInput0LaneSel + 8, // deframerInput1LaneSel + 8, // deframerInput2LaneSel + 8 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT0, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT1, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT2, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT3, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 1, // sysrefForStartup + 1, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // deframer[1] + 0, // enableJesd204C + 0, // bankId + 0, // deviceId + 0, // lane0Id + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 0, // lmfcOffset + 1, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 8, // deframerInput0LaneSel + 8, // deframerInput1LaneSel + 8, // deframerInput2LaneSel + 8 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 1, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // deframer (end of array) + { // serCfg (array) + { // serCfg[0] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[1] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[2] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[3] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + } + }, // serCfg (end of array) + { // desCfg (array) + { // desCfg[0] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[1] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[2] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[3] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + } + }, // desCfg (end of array) + { // linkSharingCfg + 0, // linkSharingEnabled + 0, // linkSharingM + 0, // linkSharingS + 0, // linkSharingNp + { // linkSharingAdcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE // conv15 + }, + }, + { // dataCfg + 0, // enable + 0, // configOption1 + 0 // configOption2 + }, + 0, // channelSelect + 0 // channelMode + }, + { // adcProfiles + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0, // OrxChannel1Index + 0 // OrxChannel2Index + }, +}; + + +adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_61_44M_4_9152G_FDD2ANT = +{ + { // radioCtrlInit + { // radioCtrlModeCfg + { // txRadioCtrlModeCfg + ADI_ADRV9025_TX_EN_PIN_MODE, // txEnableMode + 0x0F // txChannelMask + }, + { // rxRadioCtrlModeCfg + ADI_ADRV9025_RX_EN_PIN_MODE, // rxEnableMode + 0xFF // rxChannelMask + }, + { // orxRadioCtrlModeCfg + ADI_ADRV9025_ORX_EN_SINGLE_CH_1PIN_MODE, // orxEnableMode + 0, // orxPinSelectSettlingDelay_armClkCycles + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel1PinModeOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel2PinModeLowOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel2PinModeHighOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE // dualChannel2PinModeOrxSel + }, + }, + { // txToOrxMapping + ADI_ADRV9025_MAP_TX1_ORX1, // orx1Map + ADI_ADRV9025_MAP_TX2_ORX2, // orx2Map + ADI_ADRV9025_MAP_TX3_ORX3, // orx3Map + ADI_ADRV9025_MAP_TX4_ORX4 // orx4Map + }, + { // streamGpioCfg + ADI_ADRV9025_GPIO_INVALID, // streamGpInput0 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput1 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput2 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput3 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput4 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput5 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput6 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput7 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput8 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput9 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput10 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput11 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput12 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput13 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput14 + ADI_ADRV9025_GPIO_INVALID // streamGpInput15 + }, + 2575770000U, // 2566890000U, // lo1PllFreq_Hz + 2566890000U, // lo2PllFreq_Hz + 0U // auxPllFreq_Hz + }, + { // initCals + 0xD37FF, // calMask + 0x0F, // channelMask + 0 // warmBoot + }, + { // calRsltsFile + }, + 0 // checkFwVer +}; diff --git a/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_61.44M_4.9152G_FDD4ANT.c b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_61.44M_4.9152G_FDD4ANT.c new file mode 100644 index 0000000..b098c50 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_61.44M_4.9152G_FDD4ANT.c @@ -0,0 +1,1354 @@ +#include "initdata.h" + +adi_adrv9025_Init_t deviceInitInst_61_44M_4_9152G_FDD4ANT = +{ + { // clocks + 122880, // deviceClock_kHz + 9830400, // clkPllVcoFreq_kHz + 0, // serdesPllVcoFreq_kHz + 0, // ldoSelect + 0, // extLoFreq1_kHz + 0, // extLoFreq2_kHz + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll1LoMode + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll2LoMode + 0, // rfPll1LoOutDivider + 0, // rfPll2LoOutDivider + ADI_ADRV9025_RFPLLMCS_NOSYNC, // rfPllPhaseSyncMode + ADI_ADRV9025_LOSEL_LO1, // rx12LoSelect + ADI_ADRV9025_LOSEL_LO1, // rx34LoSelect + ADI_ADRV9025_LOSEL_LO2, // tx12LoSelect + ADI_ADRV9025_LOSEL_LO2, // tx34LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO, // orx12LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO // orx34LoSelect + }, + { // gpInterrupts + 0x0, // gpIntMaskPin0 + 0x0 // gpIntMaskPin1 + }, + { // rx + 0x3FF, // rxInitChannelMask + { // rxChannelCfg (array) + { // rxChannelCfg[0] + { // profile + ADI_ADRV9025_RX1, // channelType + 1, // rxFirDecimation + 1, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 2, // rhb3Decimation + 2, // rxFir1Decimation + 2, // rxFir2Decimation + 61440, // rxOutputRate_kHz + 20000, // rfBandwidth_kHz + 20000, // rxBbf3dBCorner_kHz + 10000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {25, -46, 3, -29, 29, 20, 38, -44, -131, -282, -370, 17847, -370, -282, -131, -44, 38, 20, 29, -29, 3, -46, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x01, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[1] + { // profile + ADI_ADRV9025_RX2, // channelType + 1, // rxFirDecimation + 1, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 2, // rhb3Decimation + 2, // rxFir1Decimation + 2, // rxFir2Decimation + 61440, // rxOutputRate_kHz + 20000, // rfBandwidth_kHz + 20000, // rxBbf3dBCorner_kHz + 10000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {25, -46, 3, -29, 29, 20, 38, -44, -131, -282, -370, 17847, -370, -282, -131, -44, 38, 20, 29, -29, 3, -46, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x02, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[2] + { // profile + ADI_ADRV9025_RX3, // channelType + 1, // rxFirDecimation + 1, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 2, // rhb3Decimation + 2, // rxFir1Decimation + 2, // rxFir2Decimation + 61440, // rxOutputRate_kHz + 20000, // rfBandwidth_kHz + 20000, // rxBbf3dBCorner_kHz + 10000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {25, -46, 3, -29, 29, 20, 38, -44, -131, -282, -370, 17847, -370, -282, -131, -44, 38, 20, 29, -29, 3, -46, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x04, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[3] + { // profile + ADI_ADRV9025_RX4, // channelType + 1, // rxFirDecimation + 1, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 2, // rhb3Decimation + 2, // rxFir1Decimation + 2, // rxFir2Decimation + 61440, // rxOutputRate_kHz + 20000, // rfBandwidth_kHz + 20000, // rxBbf3dBCorner_kHz + 10000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {25, -46, 3, -29, 29, 20, 38, -44, -131, -282, -370, 17847, -370, -282, -131, -44, 38, 20, 29, -29, 3, -46, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x08, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[4] + { // profile + ADI_ADRV9025_ORX1, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 225000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 112500, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {6, 0, 2, -1, 1, 4, -8, 17, -36, 100, -446, 17182, -446, 100, -36, 17, -8, 4, 1, -1, 2, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x10, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[5] + { // profile + ADI_ADRV9025_ORX2, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 225000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 112500, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {6, 0, 2, -1, 1, 4, -8, 17, -36, 100, -446, 17182, -446, 100, -36, 17, -8, 4, 1, -1, 2, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x20, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[6] + { // profile + ADI_ADRV9025_ORX3, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 225000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 112500, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {6, 0, 2, -1, 1, 4, -8, 17, -36, 100, -446, 17182, -446, 100, -36, 17, -8, 4, 1, -1, 2, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x40, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[7] + { // profile + ADI_ADRV9025_ORX4, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 225000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 112500, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {6, 0, 2, -1, 1, 4, -8, 17, -36, 100, -446, 17182, -446, 100, -36, 17, -8, 4, 1, -1, 2, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x80, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[8] + { // profile + ADI_ADRV9025_LB12, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 225000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 112500, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {6, 0, 2, -1, 1, 4, -8, 17, -36, 100, -446, 17182, -446, 100, -36, 17, -8, 4, 1, -1, 2, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x100, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[9] + { // profile + ADI_ADRV9025_LB34, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 225000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 112500, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {6, 0, 2, -1, 1, 4, -8, 17, -36, 100, -446, 17182, -446, 100, -36, 17, -8, 4, 1, -1, 2, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x200, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + } + }, // rxChannelCfg (end of array) + }, + { // tx + 0x0F, // txInitChannelMask + { // txChannelCfg (array) + { // txChannelCfg[0] + { // profile + 61440, // txInputRate_kHz + 40000, // primarySigBandwidth_kHz + 225000, // rfBandwidth_kHz + 225000, // txDac3dBCorner_kHz + 112500, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 2, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 80, // numFirCoefs + {-11, -17, 29, 23, -45, -34, 63, 56, -94, -75, 126, 106, -167, -145, 220, 190, -277, -252, 351, 323, -435, -410, 545, 538, -668, -684, 820, 890, -1013, -1167, 1259, 1575, -1586, -2235, 2035, 3443, -2558, -5848, 3874, 17638, 17638, 3874, -5848, -2558, 3443, 2035, -2235, -1586, 1575, 1259, -1167, -1013, 890, 820, -684, -668, 538, 545, -410, -435, 323, 351, -252, -277, 190, 220, -145, -167, 106, 126, -75, -94, 56, 63, -34, -45, 23, 29, -17, -11}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[1] + { // profile + 61440, // txInputRate_kHz + 40000, // primarySigBandwidth_kHz + 225000, // rfBandwidth_kHz + 225000, // txDac3dBCorner_kHz + 112500, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 2, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 80, // numFirCoefs + {-11, -17, 29, 23, -45, -34, 63, 56, -94, -75, 126, 106, -167, -145, 220, 190, -277, -252, 351, 323, -435, -410, 545, 538, -668, -684, 820, 890, -1013, -1167, 1259, 1575, -1586, -2235, 2035, 3443, -2558, -5848, 3874, 17638, 17638, 3874, -5848, -2558, 3443, 2035, -2235, -1586, 1575, 1259, -1167, -1013, 890, 820, -684, -668, 538, 545, -410, -435, 323, 351, -252, -277, 190, 220, -145, -167, 106, 126, -75, -94, 56, 63, -34, -45, 23, 29, -17, -11}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[2] + { // profile + 61440, // txInputRate_kHz + 40000, // primarySigBandwidth_kHz + 225000, // rfBandwidth_kHz + 225000, // txDac3dBCorner_kHz + 112500, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 2, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 80, // numFirCoefs + {-11, -17, 29, 23, -45, -34, 63, 56, -94, -75, 126, 106, -167, -145, 220, 190, -277, -252, 351, 323, -435, -410, 545, 538, -668, -684, 820, 890, -1013, -1167, 1259, 1575, -1586, -2235, 2035, 3443, -2558, -5848, 3874, 17638, 17638, 3874, -5848, -2558, 3443, 2035, -2235, -1586, 1575, 1259, -1167, -1013, 890, 820, -684, -668, 538, 545, -410, -435, 323, 351, -252, -277, 190, 220, -145, -167, 106, 126, -75, -94, 56, 63, -34, -45, 23, 29, -17, -11}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[3] + { // profile + 61440, // txInputRate_kHz + 40000, // primarySigBandwidth_kHz + 225000, // rfBandwidth_kHz + 225000, // txDac3dBCorner_kHz + 112500, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 2, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 80, // numFirCoefs + {-11, -17, 29, 23, -45, -34, 63, 56, -94, -75, 126, 106, -167, -145, 220, 190, -277, -252, 351, 323, -435, -410, 545, 538, -668, -684, 820, 890, -1013, -1167, 1259, 1575, -1586, -2235, 2035, 3443, -2558, -5848, 3874, 17638, 17638, 3874, -5848, -2558, 3443, 2035, -2235, -1586, 1575, 1259, -1167, -1013, 890, 820, -684, -668, 538, 545, -410, -435, 323, 351, -252, -277, 190, 220, -145, -167, 106, 126, -75, -94, 56, 63, -34, -45, 23, 29, -17, -11}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + } + }, // txChannelCfg (end of array) + }, + { // dataInterface + { // framer (array) + { // framer[0] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 8, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // 15, // serializerLanesEnabled + 0, // lmfcOffset + 0, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 1, // lane1FramerOutSel + 8, // lane2FramerOutSel + 8 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_RX1_I, // conv0 + ADI_ADRV9025_ADC_RX1_Q, // conv1 + ADI_ADRV9025_ADC_RX2_I, // conv2 + ADI_ADRV9025_ADC_RX2_Q, // conv3 + ADI_ADRV9025_ADC_RX3_I, // conv4 + ADI_ADRV9025_ADC_RX3_Q, // conv5 + ADI_ADRV9025_ADC_RX4_I, // conv6 + ADI_ADRV9025_ADC_RX4_Q, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[1] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 0, // jesd204M + 32, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 1, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 1, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[2] + 0, // enableJesd204C + 0, // bankId + 2, // deviceId + 0, // lane0Id + 0, // jesd204M + 1, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 1, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 2, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // framer (end of array) + { // deframer (array) + { // deframer[0] + 0, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 8, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // 15, // deserializerLanesEnabled + 0, // lmfcOffset + 0, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 0, // deframerInput0LaneSel + 1, // deframerInput1LaneSel + 8, // deframerInput2LaneSel + 8 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT0, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT1, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT2, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT3, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT4, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT5, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT6, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT7, // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 1, // sysrefForStartup + 1, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // deframer[1] + 0, // enableJesd204C + 0, // bankId + 0, // deviceId + 0, // lane0Id + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 0, // lmfcOffset + 1, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 8, // deframerInput0LaneSel + 8, // deframerInput1LaneSel + 8, // deframerInput2LaneSel + 8 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 1, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // deframer (end of array) + { // serCfg (array) + { // serCfg[0] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[1] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[2] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[3] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + } + }, // serCfg (end of array) + { // desCfg (array) + { // desCfg[0] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[1] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[2] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[3] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + } + }, // desCfg (end of array) + { // linkSharingCfg + 0, // linkSharingEnabled + 0, // linkSharingM + 0, // linkSharingS + 0, // linkSharingNp + { // linkSharingAdcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE // conv15 + }, + }, + { // dataCfg + 0, // enable + 0, // configOption1 + 0 // configOption2 + }, + 0, // channelSelect + 0 // channelMode + }, + { // adcProfiles + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0, // OrxChannel1Index + 0 // OrxChannel2Index + }, +}; + + +adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_61_44M_4_9152G_FDD4ANT = +{ + { // radioCtrlInit + { // radioCtrlModeCfg + { // txRadioCtrlModeCfg + ADI_ADRV9025_TX_EN_PIN_MODE, // txEnableMode + 0x0F // txChannelMask + }, + { // rxRadioCtrlModeCfg + ADI_ADRV9025_RX_EN_PIN_MODE, // rxEnableMode + 0xFF // rxChannelMask + }, + { // orxRadioCtrlModeCfg + ADI_ADRV9025_ORX_EN_SINGLE_CH_1PIN_MODE, // orxEnableMode + 0, // orxPinSelectSettlingDelay_armClkCycles + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel1PinModeOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel2PinModeLowOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, // singleChannel2PinModeHighOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE // dualChannel2PinModeOrxSel + }, + }, + { // txToOrxMapping + ADI_ADRV9025_MAP_TX1_ORX1, // orx1Map + ADI_ADRV9025_MAP_TX2_ORX2, // orx2Map + ADI_ADRV9025_MAP_TX3_ORX3, // orx3Map + ADI_ADRV9025_MAP_TX4_ORX4 // orx4Map + }, + { // streamGpioCfg + ADI_ADRV9025_GPIO_INVALID, // streamGpInput0 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput1 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput2 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput3 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput4 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput5 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput6 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput7 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput8 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput9 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput10 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput11 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput12 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput13 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput14 + ADI_ADRV9025_GPIO_INVALID // streamGpInput15 + }, + 2575770000U, // 2566890000U, // lo1PllFreq_Hz + 2566890000U, // lo2PllFreq_Hz + 0U // auxPllFreq_Hz + }, + { // initCals + 0xD37FF, // calMask + 0x0F, // channelMask + 0 // warmBoot + }, + { // calRsltsFile + }, + 0 // checkFwVer +}; diff --git a/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_sat.c b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_sat.c new file mode 100644 index 0000000..885637f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204B_sat.c @@ -0,0 +1,1354 @@ +#include "initdata.h" + +adi_adrv9025_Init_t deviceInitInst_240M = +{ + { // clocks + 122880, // deviceClock_kHz + 9830400, // clkPllVcoFreq_kHz + 0, // serdesPllVcoFreq_kHz + 0, // ldoSelect + 0, // extLoFreq1_kHz + 0, // extLoFreq2_kHz + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll1LoMode + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll2LoMode + 0, // rfPll1LoOutDivider + 0, // rfPll2LoOutDivider + ADI_ADRV9025_RFPLLMCS_NOSYNC, // rfPllPhaseSyncMode + ADI_ADRV9025_LOSEL_LO1, // rx12LoSelect + ADI_ADRV9025_LOSEL_LO1, // rx34LoSelect + ADI_ADRV9025_LOSEL_LO2, // tx12LoSelect + ADI_ADRV9025_LOSEL_LO2, // tx34LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO, // orx12LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO // orx34LoSelect + }, + { // gpInterrupts + 0x00, // gpIntMaskPin0 + 0x00 // gpIntMaskPin1 + }, + { // rx + 0x3FF, // rxInitChannelMask + { // rxChannelCfg (array) + { // rxChannelCfg[0] + { // profile + ADI_ADRV9025_RX1, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 200000, // rfBandwidth_kHz + 200000, // rxBbf3dBCorner_kHz + 100000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-10, 4, -1, -2, 8, -15, 21, -21, 7, 59, -502, 17153, -502, 59, 7, -21, 21, -15, 8, -2, -1, 4, -10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x01, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[1] + { // profile + ADI_ADRV9025_RX2, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 200000, // rfBandwidth_kHz + 200000, // rxBbf3dBCorner_kHz + 100000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-10, 4, -1, -2, 8, -15, 21, -21, 7, 59, -502, 17153, -502, 59, 7, -21, 21, -15, 8, -2, -1, 4, -10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x02, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[2] + { // profile + ADI_ADRV9025_RX3, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 200000, // rfBandwidth_kHz + 200000, // rxBbf3dBCorner_kHz + 100000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-10, 4, -1, -2, 8, -15, 21, -21, 7, 59, -502, 17153, -502, 59, 7, -21, 21, -15, 8, -2, -1, 4, -10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x04, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[3] + { // profile + ADI_ADRV9025_RX4, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 200000, // rfBandwidth_kHz + 200000, // rxBbf3dBCorner_kHz + 100000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-10, 4, -1, -2, 8, -15, 21, -21, 7, 59, -502, 17153, -502, 59, 7, -21, 21, -15, 8, -2, -1, 4, -10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x08, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[4] + { // profile + ADI_ADRV9025_ORX1, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 491520, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-2, 4, -6, 10, -16, 27, -47, 81, -157, 348, -1623, 19145, -1623, 348, -157, 81, -47, 27, -16, 10, -6, 4, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x10, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[5] + { // profile + ADI_ADRV9025_ORX2, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 491520, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-2, 4, -6, 10, -16, 27, -47, 81, -157, 348, -1623, 19145, -1623, 348, -157, 81, -47, 27, -16, 10, -6, 4, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x20, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[6] + { // profile + ADI_ADRV9025_ORX3, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 491520, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-2, 4, -6, 10, -16, 27, -47, 81, -157, 348, -1623, 19145, -1623, 348, -157, 81, -47, 27, -16, 10, -6, 4, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x40, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[7] + { // profile + ADI_ADRV9025_ORX4, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 491520, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-2, 4, -6, 10, -16, 27, -47, 81, -157, 348, -1623, 19145, -1623, 348, -157, 81, -47, 27, -16, 10, -6, 4, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x80, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[8] + { // profile + ADI_ADRV9025_LB12, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 491520, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-2, 4, -6, 10, -16, 27, -47, 81, -157, 348, -1623, 19145, -1623, 348, -157, 81, -47, 27, -16, 10, -6, 4, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x100, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[9] + { // profile + ADI_ADRV9025_LB34, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 491520, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-2, 4, -6, 10, -16, 27, -47, 81, -157, 348, -1623, 19145, -1623, 348, -157, 81, -47, 27, -16, 10, -6, 4, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x200, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + } + }, // rxChannelCfg (end of array) + }, + { // tx + 0x0F, // txInitChannelMask + { // txChannelCfg (array) + { // txChannelCfg[0] + { // profile + 491520, // txInputRate_kHz + 200000, // primarySigBandwidth_kHz + 330000, // rfBandwidth_kHz + 330000, // txDac3dBCorner_kHz + 200000, // txBbf3dBCorner_kHz + 1, // dpdHb1Interpolation + 1, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {20, -155, 462, -1015, 1838, -2809, 3577, -3352, 725, 17246, 725, -3352, 3577, -2809, 1838, -1015, 462, -155, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[1] + { // profile + 491520, // txInputRate_kHz + 200000, // primarySigBandwidth_kHz + 330000, // rfBandwidth_kHz + 330000, // txDac3dBCorner_kHz + 200000, // txBbf3dBCorner_kHz + 1, // dpdHb1Interpolation + 1, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {20, -155, 462, -1015, 1838, -2809, 3577, -3352, 725, 17246, 725, -3352, 3577, -2809, 1838, -1015, 462, -155, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[2] + { // profile + 491520, // txInputRate_kHz + 200000, // primarySigBandwidth_kHz + 330000, // rfBandwidth_kHz + 330000, // txDac3dBCorner_kHz + 200000, // txBbf3dBCorner_kHz + 1, // dpdHb1Interpolation + 1, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {20, -155, 462, -1015, 1838, -2809, 3577, -3352, 725, 17246, 725, -3352, 3577, -2809, 1838, -1015, 462, -155, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[3] + { // profile + 491520, // txInputRate_kHz + 200000, // primarySigBandwidth_kHz + 330000, // rfBandwidth_kHz + 330000, // txDac3dBCorner_kHz + 200000, // txBbf3dBCorner_kHz + 1, // dpdHb1Interpolation + 1, // dpdHb2Interpolation + 1, // txFirInterpolation + 2, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 6, // gain_dB + 20, // numFirCoefs + {20, -155, 462, -1015, 1838, -2809, 3577, -3352, 725, 17246, 725, -3352, 3577, -2809, 1838, -1015, 462, -155, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + } + }, // txChannelCfg (end of array) + }, + { // dataInterface + { // framer (array) + { // framer[0] + 0, // enableJesd204C + 0, // bankId + 0, // deviceId + 0, // lane0Id + 4, // jesd204M + 32, // jesd204K + 2, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0, // lmfcOffset + 0, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 1, // lane1FramerOutSel + 2, // lane2FramerOutSel + 3 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_RX1_I, // conv0 + ADI_ADRV9025_ADC_RX1_Q, // conv1 + ADI_ADRV9025_ADC_RX2_I, // conv2 + ADI_ADRV9025_ADC_RX2_Q, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[1] + 0, // enableJesd204C + 0, // bankId + 0, // deviceId + 0, // lane0Id + 0, // jesd204M + 32, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 1, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 0, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[2] + 0, // enableJesd204C + 0, // bankId + 0, // deviceId + 0, // lane0Id + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 0, // syncbInSelect + 0, // overSample + 0, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // framer (end of array) + { // deframer (array) + { // deframer[0] + 0, // enableJesd204C + 0, // bankId + 0, // deviceId + 0, // lane0Id + 4, // jesd204M + 32, // jesd204K + 2, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // deserializerLanesEnabled + 0, // lmfcOffset + 0, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 0, // deframerInput0LaneSel + 1, // deframerInput1LaneSel + 2, // deframerInput2LaneSel + 3 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT0, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT1, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT2, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT3, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // deframer[1] + 0, // enableJesd204C + 0, // bankId + 0, // deviceId + 0, // lane0Id + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 0, // lmfcOffset + 0, // syncbOutSelect + 0, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 4, // deframerInput0LaneSel + 5, // deframerInput1LaneSel + 6, // deframerInput2LaneSel + 7 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // deframer (end of array) + { // serCfg (array) + { // serCfg[0] + 0, // serAmplitude + 0, // serPreEmphasis + 0, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[1] + 0, // serAmplitude + 0, // serPreEmphasis + 0, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[2] + 0, // serAmplitude + 0, // serPreEmphasis + 0, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[3] + 0, // serAmplitude + 0, // serPreEmphasis + 0, // serPostEmphasis + 0 // serInvertLanePolarity + } + }, // serCfg (end of array) + { // desCfg (array) + { // desCfg[0] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[1] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[2] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[3] + 0, // desInvertLanePolarity + 0, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + } + }, // desCfg (end of array) + { // linkSharingCfg + 0, // linkSharingEnabled + 0, // linkSharingM + 1, // linkSharingS + 16, // linkSharingNp + { // linkSharingAdcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE // conv15 + }, + }, + { // dataCfg + 0, // enable + 0, // configOption1 + 0 // configOption2 + }, + 0, // channelSelect + 0 // channelMode + }, + { // adcProfiles + {386, 273, 505, 512, 10, 294, 153, 96, 40, 148, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {386, 273, 505, 512, 10, 294, 153, 96, 40, 148, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {386, 273, 505, 512, 10, 294, 153, 96, 40, 148, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {386, 273, 505, 512, 10, 294, 153, 96, 40, 148, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {386, 273, 541, 507, 47, 291, 153, 99, 40, 150, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {386, 273, 541, 507, 47, 291, 153, 99, 40, 150, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {386, 273, 541, 507, 47, 291, 153, 99, 40, 150, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {386, 273, 541, 507, 47, 291, 153, 99, 40, 150, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {386, 273, 541, 507, 47, 291, 153, 99, 40, 150, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {386, 273, 541, 507, 47, 291, 153, 99, 40, 150, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {386, 273, 541, 507, 47, 291, 153, 99, 40, 150, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {386, 273, 541, 507, 47, 291, 153, 99, 40, 150, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0, // OrxChannel1Index + 0 // OrxChannel2Index + }, +}; + + +adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_240M = +{ + { // radioCtrlInit + { // radioCtrlModeCfg + { // txRadioCtrlModeCfg + ADI_ADRV9025_TX_EN_SPI_MODE, // txEnableMode + 0x0F // txChannelMask + }, + { // rxRadioCtrlModeCfg + ADI_ADRV9025_RX_EN_SPI_MODE, // rxEnableMode + 0xFF // rxChannelMask + }, + { // orxRadioCtrlModeCfg + ADI_ADRV9025_ORX_EN_SPI_MODE, // orxEnableMode + 0, // orxPinSelectSettlingDelay_armClkCycles + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX1_FE, // singleChannel1PinModeOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX1_FE, // singleChannel2PinModeLowOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX1_FE, // singleChannel2PinModeHighOrxSel + ADI_ADRV9025_DUAL_CH_PIN_MODE_ORX1_ORX3_SEL // dualChannel2PinModeOrxSel + }, + }, + { // txToOrxMapping + ADI_ADRV9025_MAP_TX1_ORX1, // orx1Map + ADI_ADRV9025_MAP_TX2_ORX2, // orx2Map + ADI_ADRV9025_MAP_TX3_ORX3, // orx3Map + ADI_ADRV9025_MAP_TX4_ORX4 // orx4Map + }, + { // streamGpioCfg + ADI_ADRV9025_GPIO_INVALID, // streamGpInput0 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput1 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput2 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput3 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput4 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput5 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput6 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput7 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput8 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput9 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput10 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput11 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput12 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput13 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput14 + ADI_ADRV9025_GPIO_INVALID // streamGpInput15 + }, + 3500000000U, // lo1PllFreq_Hz + 3550000000U, // lo2PllFreq_Hz + 0U // auxPllFreq_Hz + }, + { // initCals + 0xD27FF, // calMask + 0x0F, // channelMask + 0 // warmBoot + }, + { // calRsltsFile + }, + 0 // checkFwVer +}; diff --git a/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204C_122.88M_8_11008G.c b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204C_122.88M_8_11008G.c new file mode 100644 index 0000000..ae42d2b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/example/initdata_204C_122.88M_8_11008G.c @@ -0,0 +1,1354 @@ +#include "initdata.h" + +adi_adrv9025_Init_t deviceInitInst_122_88M_8_11008G = +{ + { // clocks + 122880, // deviceClock_kHz + 9830400, // clkPllVcoFreq_kHz + 8110080, // serdesPllVcoFreq_kHz + 0, // ldoSelect + 0, // extLoFreq1_kHz + 0, // extLoFreq2_kHz + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll1LoMode + ADI_ADRV9025_INTLO_NOOUTPUT, // rfPll2LoMode + 0, // rfPll1LoOutDivider + 0, // rfPll2LoOutDivider + ADI_ADRV9025_RFPLLMCS_NOSYNC, // rfPllPhaseSyncMode + ADI_ADRV9025_LOSEL_LO1, // rx12LoSelect + ADI_ADRV9025_LOSEL_LO1, // rx34LoSelect + ADI_ADRV9025_LOSEL_LO1, // tx12LoSelect + ADI_ADRV9025_LOSEL_LO1, // tx34LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO, // orx12LoSelect + ADI_ADRV9025_ORXLOSEL_TXLO // orx34LoSelect + }, + { // gpInterrupts + 0x0, // gpIntMaskPin0 + 0x0 // gpIntMaskPin1 + }, + { // rx + 0x3FF, // rxInitChannelMask + { // rxChannelCfg (array) + { // rxChannelCfg[0] + { // profile + ADI_ADRV9025_RX1, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 200000, // rfBandwidth_kHz + 200000, // rxBbf3dBCorner_kHz + 100000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-10, 4, -1, -2, 8, -15, 21, -21, 7, 59, -502, 17153, -502, 59, 7, -21, 21, -15, 8, -2, -1, 4, -10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x01, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[1] + { // profile + ADI_ADRV9025_RX2, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 200000, // rfBandwidth_kHz + 200000, // rxBbf3dBCorner_kHz + 100000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-10, 4, -1, -2, 8, -15, 21, -21, 7, 59, -502, 17153, -502, 59, 7, -21, 21, -15, 8, -2, -1, 4, -10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x02, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[2] + { // profile + ADI_ADRV9025_RX3, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 200000, // rfBandwidth_kHz + 200000, // rxBbf3dBCorner_kHz + 100000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-10, 4, -1, -2, 8, -15, 21, -21, 7, 59, -502, 17153, -502, 59, 7, -21, 21, -15, 8, -2, -1, 4, -10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x04, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[3] + { // profile + ADI_ADRV9025_RX4, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 1, // rhb1WideBandMode + 2, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 200000, // rfBandwidth_kHz + 200000, // rxBbf3dBCorner_kHz + 100000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {-10, 4, -1, -2, 8, -15, 21, -21, 7, 59, -502, 17153, -502, 59, 7, -21, 21, -15, 8, -2, -1, 4, -10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_BYPASS, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x08, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[4] + { // profile + ADI_ADRV9025_ORX1, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x10, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[5] + { // profile + ADI_ADRV9025_ORX2, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x20, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[6] + { // profile + ADI_ADRV9025_ORX3, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x40, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[7] + { // profile + ADI_ADRV9025_ORX4, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x80, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[8] + { // profile + ADI_ADRV9025_LB12, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x100, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + }, + { // rxChannelCfg[9] + { // profile + ADI_ADRV9025_LB34, // channelType + 1, // rxFirDecimation + 5, // rxDec5Decimation + 2, // rhb1Decimation + 0, // rhb1WideBandMode + 1, // rhb2Decimation + 1, // rhb3Decimation + 1, // rxFir1Decimation + 1, // rxFir2Decimation + 245760, // rxOutputRate_kHz + 450000, // rfBandwidth_kHz + 225000, // rxBbf3dBCorner_kHz + 225000, // rxAdcBandWidth_kHz + { // rxFir + 6, // gain_dB + 24, // numFirCoefs + {33, -7, 9, -7, 3, 9, -27, 62, -138, 349, -1663, 19282, -1663, 349, -138, 62, -27, 9, 3, -7, 9, -7, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + ADI_ADRV9025_RXDDC_DEC2, // rxDdcMode + { // rxNcoShifterCfg + 0, // bandAInputBandWidth_kHz + 0, // bandAInputCenterFreq_kHz + 0, // bandANco1Freq_kHz + 0, // bandANco2Freq_kHz + 0, // bandBInputBandWidth_kHz + 0, // bandBInputCenterFreq_kHz + 0, // bandBNco1Freq_kHz + 0, // bandBNco2Freq_kHz + 0 // bandAbCombinedEnable + }, + 4, // tiaPowerMode + { // rxDataFormat + 0x200, // rxChannelMask + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, // formatSelect + { // floatingPointConfig + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND, // fpDataFormat + ADI_ADRV9025_ROUND_TO_EVEN, // fpRoundMode + ADI_ADRV9025_2_EXPONENTBITS, // fpNumExpBits + ADI_ADRV9025_FPATTEN_0DB, // fpAttenSteps + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE, // fpHideLeadingOne + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE // fpEncodeNan + }, + { // integerConfigSettings + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, // intEmbeddedBits + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, // intSampleResolution + ADI_ADRV9025_NO_PARITY, // intParity + ADI_ADRV9025_LOWER_NIBBLE_ON_Q // intEmbeddedPos + }, + { // slicerConfigSettings + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB, // extSlicerStepSize + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB, // intSlicerStepSize + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx1ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx2ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE, // rx3ExtSlicerGpioSelect + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE // rx4ExtSlicerGpioSelect + }, + { // embOvldMonitorSettings + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbQ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneI + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED, // embeddedMonitorSrcLsbPlusOneQ + ADI_ADRV9025_HB2_LOW_SRC_INVALID, // embeddedMonitorHb2LowSrcSel + ADI_ADRV9025_HB2_HIGH_SRC_INVALID, // embeddedMonitorHb2HighSrcSel + ADI_ADRV9025_APD_LOW_SRC_INVALID, // embeddedMonitorApdLowSrcSel + ADI_ADRV9025_APD_HIGH_SRC_INVALID, // embeddedMonitorApdHighSrcSel + 0, // invertHb2Flag + 0 // invertApdFlag + }, + 0, // externalLnaGain + 0 // tempCompensationEnable + }, + }, + } + }, // rxChannelCfg (end of array) + }, + { // tx + 0x0F, // txInitChannelMask + { // txChannelCfg (array) + { // txChannelCfg[0] + { // profile + 245760, // txInputRate_kHz + 200000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 1, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 0, // gain_dB + 20, // numFirCoefs + {150, -1580, 4231, -4275, -1981, 8637, -2338, -13408, 10714, 32466, 10714, -13408, -2338, 8637, -1981, -4275, 4231, -1580, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[1] + { // profile + 245760, // txInputRate_kHz + 200000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 1, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 0, // gain_dB + 20, // numFirCoefs + {150, -1580, 4231, -4275, -1981, 8637, -2338, -13408, 10714, 32466, 10714, -13408, -2338, 8637, -1981, -4275, 4231, -1580, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[2] + { // profile + 245760, // txInputRate_kHz + 200000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 1, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 0, // gain_dB + 20, // numFirCoefs + {150, -1580, 4231, -4275, -1981, 8637, -2338, -13408, 10714, 32466, 10714, -13408, -2338, 8637, -1981, -4275, 4231, -1580, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + }, + { // txChannelCfg[3] + { // profile + 245760, // txInputRate_kHz + 200000, // primarySigBandwidth_kHz + 450000, // rfBandwidth_kHz + 450000, // txDac3dBCorner_kHz + 225000, // txBbf3dBCorner_kHz + 2, // dpdHb1Interpolation + 2, // dpdHb2Interpolation + 1, // txFirInterpolation + 1, // thb1Interpolation + 1, // thb2Interpolation + 2, // thb3Interpolation + 1, // txInt5Interpolation + { // txFir + 0, // gain_dB + 20, // numFirCoefs + {150, -1580, 4231, -4275, -1981, 8637, -2338, -13408, 10714, 32466, 10714, -13408, -2338, 8637, -1981, -4275, 4231, -1580, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + 8 // txBbfPowerMode + }, + { // txAttenCtrl + ADI_ADRV9025_TXATTEN_0P05_DB, // txAttenStepSize + 63, // txRampDownEvents + 0, // reserved + ADI_ADRV9025_TXATTEN_SPI_MODE, // attenMode + ADI_ADRV9025_TX_DACFS_0DB, // dacFullScale + 10000 // txAttenInit_mdB + }, + ADI_ADRV9025_TX_DACFS_0DB // dacFullScale + } + }, // txChannelCfg (end of array) + }, + { // dataInterface + { // framer (array) + { // framer[0] + 1, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 8, // jesd204M + 64, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 1, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0, // lmfcOffset + 0, // syncbInSelect + 0, // overSample + 1, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 1, // lane1FramerOutSel + 2, // lane2FramerOutSel + 3 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_RX1_I, // conv0 + ADI_ADRV9025_ADC_RX1_Q, // conv1 + ADI_ADRV9025_ADC_RX2_I, // conv2 + ADI_ADRV9025_ADC_RX2_Q, // conv3 + ADI_ADRV9025_ADC_DUALBAND_RX3_BAND_A_I, // conv4 + ADI_ADRV9025_ADC_RX3_Q, // conv5 + ADI_ADRV9025_ADC_DUALBAND_RX4_BAND_A_I, // conv6 + ADI_ADRV9025_ADC_RX4_Q, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[1] + 1, // enableJesd204C + 0, // bankId + 0, // deviceId + 0, // lane0Id + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 0, // syncbInSelect + 0, // overSample + 0, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // framer[2] + 1, // enableJesd204C + 0, // bankId + 0, // deviceId + 0, // lane0Id + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // serializerLanesEnabled + 0, // lmfcOffset + 0, // syncbInSelect + 0, // overSample + 0, // syncbInLvdsMode + 0, // syncbInLvdsPnInvert + { // serializerLaneCrossbar + 0, // lane0FramerOutSel + 0, // lane1FramerOutSel + 0, // lane2FramerOutSel + 0 // lane3FramerOutSel + }, + { // adcCrossbar + ADI_ADRV9025_ADC_DISABLE, // conv0 + ADI_ADRV9025_ADC_DISABLE, // conv1 + ADI_ADRV9025_ADC_DISABLE, // conv2 + ADI_ADRV9025_ADC_DISABLE, // conv3 + ADI_ADRV9025_ADC_DISABLE, // conv4 + ADI_ADRV9025_ADC_DISABLE, // conv5 + ADI_ADRV9025_ADC_DISABLE, // conv6 + ADI_ADRV9025_ADC_DISABLE, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE, // conv15 + ADI_ADRV9025_ADC_DISABLE, // conv16 + ADI_ADRV9025_ADC_DISABLE, // conv17 + ADI_ADRV9025_ADC_DISABLE, // conv18 + ADI_ADRV9025_ADC_DISABLE, // conv19 + ADI_ADRV9025_ADC_DISABLE, // conv20 + ADI_ADRV9025_ADC_DISABLE, // conv21 + ADI_ADRV9025_ADC_DISABLE, // conv22 + ADI_ADRV9025_ADC_DISABLE // conv23 + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // framer (end of array) + { // deframer (array) + { // deframer[0] + 1, // enableJesd204C + 0, // bankId + 1, // deviceId + 0, // lane0Id + 8, // jesd204M + 64, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 1, // jesd204E + 1, // scramble + 15, // deserializerLanesEnabled + 0, // lmfcOffset + 0, // syncbOutSelect + 1, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 0, // deframerInput0LaneSel + 1, // deframerInput1LaneSel + 2, // deframerInput2LaneSel + 3 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT0, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT1, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT2, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT3, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT4, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT5, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT6, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT7 // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + }, + { // deframer[1] + 1, // enableJesd204C + 0, // bankId + 0, // deviceId + 0, // lane0Id + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 0, // lmfcOffset + 0, // syncbOutSelect + 0, // syncbOutLvdsMode + 0, // syncbOutLvdsPnInvert + 0, // syncbOutCmosSlewRate + 0, // syncbOutCmosDriveLevel + { // deserializerLaneCrossbar + 8, // deframerInput0LaneSel + 8, // deframerInput1LaneSel + 8, // deframerInput2LaneSel + 8 // deframerInput3LaneSel + }, + { // dacCrossbar + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanQ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx4DacChanI + ADI_ADRV9025_DEFRAMER_OUT_DISABLE // tx4DacChanQ + }, + 0, // newSysrefOnRelink + 0, // sysrefForStartup + 0, // sysrefNShotEnable + 0, // sysrefNShotCount + 0 // sysrefIgnoreWhenLinked + } + }, // deframer (end of array) + { // serCfg (array) + { // serCfg[0] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[1] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[2] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + }, + { // serCfg[3] + 0, // serAmplitude + 1, // serPreEmphasis + 3, // serPostEmphasis + 0 // serInvertLanePolarity + } + }, // serCfg (end of array) + { // desCfg (array) + { // desCfg[0] + 0, // desInvertLanePolarity + 1, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[1] + 0, // desInvertLanePolarity + 1, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[2] + 0, // desInvertLanePolarity + 1, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + }, + { // desCfg[3] + 0, // desInvertLanePolarity + 1, // highBoost + 0, // configOption1 + 0, // configOption2 + 0, // configOption3 + 0, // configOption4 + 0, // configOption5 + 0, // configOption6 + 0, // configOption7 + 0, // configOption8 + 0, // configOption9 + 0 // configOption10 + } + }, // desCfg (end of array) + { // linkSharingCfg + 1, // linkSharingEnabled + 8, // linkSharingM + 1, // linkSharingS + 16, // linkSharingNp + { // linkSharingAdcCrossbar + ADI_ADRV9025_ADC_ORX1_I, // conv0 + ADI_ADRV9025_ADC_ORX1_Q, // conv1 + ADI_ADRV9025_ADC_ORX2_I, // conv2 + ADI_ADRV9025_ADC_ORX2_Q, // conv3 + ADI_ADRV9025_ADC_RX1_Q, // conv4 + ADI_ADRV9025_ADC_RX1_Q, // conv5 + ADI_ADRV9025_ADC_RX1_Q, // conv6 + ADI_ADRV9025_ADC_RX1_Q, // conv7 + ADI_ADRV9025_ADC_DISABLE, // conv8 + ADI_ADRV9025_ADC_DISABLE, // conv9 + ADI_ADRV9025_ADC_DISABLE, // conv10 + ADI_ADRV9025_ADC_DISABLE, // conv11 + ADI_ADRV9025_ADC_DISABLE, // conv12 + ADI_ADRV9025_ADC_DISABLE, // conv13 + ADI_ADRV9025_ADC_DISABLE, // conv14 + ADI_ADRV9025_ADC_DISABLE // conv15 + }, + }, + { // dataCfg + 0, // enable + 0, // configOption1 + 0 // configOption2 + }, + 0, // channelSelect + 0 // channelMode + }, + { // adcProfiles + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0, // OrxChannel1Index + 0 // OrxChannel2Index + }, +}; + + +adi_adrv9025_PostMcsInit_t devicePostMcsInitInst_122_88M_8_11008G = +{ + { // radioCtrlInit + { // radioCtrlModeCfg + { // txRadioCtrlModeCfg + ADI_ADRV9025_TX_EN_SPI_MODE, // txEnableMode + 0x0F // txChannelMask + }, + { // rxRadioCtrlModeCfg + ADI_ADRV9025_RX_EN_SPI_MODE, // rxEnableMode + 0xFF // rxChannelMask + }, + { // orxRadioCtrlModeCfg + ADI_ADRV9025_ORX_EN_SPI_MODE, // orxEnableMode + 0, // orxPinSelectSettlingDelay_armClkCycles + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX1_FE, // singleChannel1PinModeOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX1_FE, // singleChannel2PinModeLowOrxSel + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX1_FE, // singleChannel2PinModeHighOrxSel + ADI_ADRV9025_DUAL_CH_PIN_MODE_ORX1_ORX3_SEL // dualChannel2PinModeOrxSel + }, + }, + { // txToOrxMapping + ADI_ADRV9025_MAP_TX1_ORX1, // orx1Map + ADI_ADRV9025_MAP_TX2_ORX2, // orx2Map + ADI_ADRV9025_MAP_TX3_ORX3, // orx3Map + ADI_ADRV9025_MAP_TX4_ORX4 // orx4Map + }, + { // streamGpioCfg + ADI_ADRV9025_GPIO_INVALID, // streamGpInput0 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput1 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput2 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput3 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput4 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput5 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput6 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput7 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput8 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput9 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput10 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput11 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput12 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput13 + ADI_ADRV9025_GPIO_INVALID, // streamGpInput14 + ADI_ADRV9025_GPIO_INVALID // streamGpInput15 + }, + 3500000000U, // lo1PllFreq_Hz + 3550000000U, // lo2PllFreq_Hz + 0U // auxPllFreq_Hz + }, + { // initCals + 0xD27FF, // calMask + 0x0F, // channelMask + 0 // warmBoot + }, + { // calRsltsFile + }, + 0 // checkFwVer +}; diff --git a/driver/rfic/rf/adrv9025/c_src/app/makefile b/driver/rfic/rf/adrv9025/c_src/app/makefile new file mode 100644 index 0000000..2b35506 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/app/makefile @@ -0,0 +1,34 @@ +LIB_ADI_APP = libadi_app.a +CC = aarch64-linux-gnu-gcc +C_SRC_ROOT = .. + +ARFLAGS = -rv +CFLAGS = -Wall -shared \ + -I./example \ + -I$(C_SRC_ROOT)/devices/ad9528/public/include \ + -I$(C_SRC_ROOT)/devices/adrv9025/public/include \ + -I$(C_SRC_ROOT)/common \ + -I$(C_SRC_ROOT)/common/adi_error \ + -I$(C_SRC_ROOT)/common/adi_hal \ + -I$(C_SRC_ROOT)/common/adi_logging \ + -I$(C_SRC_ROOT)/platforms \ + -I$(C_SRC_ROOT)/platforms/ucp2 \ + -I../../../ucp/inc \ + -I../../../api/inc \ + -Werror + +EXT = c + +SRC = $(wildcard ./example/*.$(EXT)) +OBJS = $(SRC:.$(EXT)=.o) + +all: $(LIB_ADI_APP) +.$(EXT).o: + $(CC) $(CFLAGS) -o $@ -c $< + +$(LIB_ADI_APP): $(OBJS) + ar $(ARFLAGS) $(LIB_ADI_APP) $(OBJS) + +clean: + rm -rf ./example/*.o + rm -rf *.a \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/ad9528/include/adi_ad9528_daughter_board.h b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/ad9528/include/adi_ad9528_daughter_board.h new file mode 100644 index 0000000..9cbebc0 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/ad9528/include/adi_ad9528_daughter_board.h @@ -0,0 +1,50 @@ +/** + * \file adi_ad9528_daughter_board.h + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_AD9528_DAUGHTER_BOARD_H_ +#define _ADI_AD9528_DAUGHTER_BOARD_H_ + +#include "adi_ad9528.h" +#include "adi_motherboard_trx.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/**************************************************************************** +* Runtime functions +**************************************************************************** +*/ + + +/** +* \brief Performing selected task to initialize the daughterboard. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param trxDaughterboard a pointer to generic daughterboard structure. +* \param actionFlags a selected task of initialization. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_clock9528Board_Dispatch(adi_daughterboard_trx_t *trxDaughterboard, adrvtrx_board_action_e actionFlags); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/ad9528/src/adi_adr9528_daughter_board.c b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/ad9528/src/adi_adr9528_daughter_board.c new file mode 100644 index 0000000..091f718 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/ad9528/src/adi_adr9528_daughter_board.c @@ -0,0 +1,73 @@ +/** + * \file adi_ad9528_daughter_board.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include +#include +#include "adi_ad9528.h" +#include "adi_ad9528_utilities.h" +#include "adi_motherboard_trx.h" + + +/**************************************************************************** +* Local functions +****************************************************************************/ + +int32_t adi_clock9528Board_Dispatch(adi_daughterboard_trx_t *trxDaughterboard, adrvtrx_board_action_e actionFlags) +{ + int32_t recoveryAction = ADI_COMMON_HAL_OK; + adi_common_Device_t *commonDev = NULL; + + /* Clock 9528 device allocation */ + if (actionFlags == TRX_BOARD_ACTION_DEVICE_ALLOC) + { + trxDaughterboard->clockDevice = (uintptr_t) calloc(1, sizeof(adi_ad9528_Device_t)); + if (trxDaughterboard->clockDevice == 0) + { + return (ADI_COMMON_HAL_GEN_SW); + } + + /* Assigning Abstract pointers */ + trxDaughterboard->clockAbstractDev.commonAbstractDevice = (adi_common_Device_t *) trxDaughterboard->clockDevice; + trxDaughterboard->clockAbstractDev.clockAbstractDevice = trxDaughterboard->clockDevice; + + return (ADI_COMMON_HAL_OK); + } + + /* HW Open */ + if (actionFlags == TRX_BOARD_ACTION_DEVICE_HWOPEN) + { + commonDev = trxDaughterboard->clockAbstractDev.commonAbstractDevice; + if ((recoveryAction = adi_ad9528_HwOpen((adi_ad9528_Device_t *) trxDaughterboard->clockDevice)) != (int32_t)ADI_HAL_OK) + { + printf("Clock HwOpen failed. %s \n", commonDev->error.errormessage); + return recoveryAction; + } + commonDev->error.logEnable = ADI_ENABLE; + + return (ADI_COMMON_HAL_OK); + } + + /* HW Close */ + if (actionFlags == TRX_BOARD_ACTION_DEVICE_HWCLOSE) + { + commonDev = trxDaughterboard->clockAbstractDev.commonAbstractDevice; + if ((recoveryAction = adi_ad9528_HwClose((adi_ad9528_Device_t *) trxDaughterboard->clockDevice)) != (int32_t)ADI_HAL_OK) + { + return recoveryAction; + } + adi_hal_DevHalCfgFree(commonDev->devHalInfo); + + return (ADI_COMMON_HAL_OK); + } + + return (recoveryAction); +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adi_daughterboard_trx_dev.c b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adi_daughterboard_trx_dev.c new file mode 100644 index 0000000..0303f93 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adi_daughterboard_trx_dev.c @@ -0,0 +1,593 @@ +/** + * \file adi_board_trx_dev.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_daughterboard_trx_dev.h" +#include +#include + +extern int32_t adi_adrv9025Board_Dispatch(adi_daughterboard_trx_t* trxDaughterboard, + adrvtrx_board_action_e actionFlags); + +extern int32_t adi_adrv9010Board_Dispatch(adi_daughterboard_trx_t* trxDaughterboard, + adrvtrx_board_action_e actionFlags); + +extern int32_t adi_fpga9025Board_Dispatch(adi_daughterboard_trx_t* trxDaughterboard, + adrvtrx_board_action_e actionFlags); + +extern int32_t adi_fpga9010Board_Dispatch(adi_daughterboard_trx_t* trxDaughterboard, + adrvtrx_board_action_e actionFlags); + +extern int32_t adi_clock9528Board_Dispatch(adi_daughterboard_trx_t* trxDaughterboard, + adrvtrx_board_action_e actionFlags); + +int32_t adi_daughterboard_Create(adi_daughterboard_trx_t* trxDaughterboard) +{ + int32_t recoveryAction = ADI_COMMON_HAL_OK; + if (trxDaughterboard == NULL) + { + return (ADI_COMMON_HAL_GEN_SW); + } + + // Memory allocation for clock device. + trxDaughterboard->ClockDispatch = adi_clock9528Board_Dispatch; + recoveryAction = trxDaughterboard->ClockDispatch(trxDaughterboard, + TRX_BOARD_ACTION_DEVICE_ALLOC); + if (recoveryAction != ADI_COMMON_HAL_OK) + { + if (trxDaughterboard->clockDevice) + { + free((void *)trxDaughterboard->clockDevice); + } + return (ADI_COMMON_HAL_GEN_SW); + } + +#if !defined(ADRV9025) && !defined(ADRV9010) + if ((trxDaughterboard->daughterCardId >= ADI_BOARD_9025_MIN) && (trxDaughterboard->daughterCardId <= ADI_BOARD_9025_MAX)) + { + trxDaughterboard->BoardDispatch = adi_adrv9025Board_Dispatch; + } + else if ((trxDaughterboard->daughterCardId >= ADI_BOARD_9010_MIN) && (trxDaughterboard->daughterCardId <= ADI_BOARD_9010_MAX)) + { + trxDaughterboard->BoardDispatch = adi_adrv9010Board_Dispatch; + } + + /* Set up FPGA Device Dispatch pointer */ + if (trxDaughterboard->motherboardId == ADI_ADS9_PLATFORM) + { + trxDaughterboard->FpgaDispatch = adi_fpga9025Board_Dispatch; + } + else if (trxDaughterboard->motherboardId == ADI_ADS8_PLATFORM) + { + trxDaughterboard->FpgaDispatch = adi_fpga9010Board_Dispatch; + } + + else + { + return (ADI_COMMON_HAL_GEN_SW); + } +#elif defined(ADRV9025) + if ((trxDaughterboard->daughterCardId >= ADI_BOARD_9025_MIN) && (trxDaughterboard->daughterCardId <= ADI_BOARD_9025_MAX)) + { + trxDaughterboard->BoardDispatch = adi_adrv9025Board_Dispatch; + } + + /* Set up FPGA Device Dispatch pointer */ + if (trxDaughterboard->motherboardId == ADI_ADS9_PLATFORM) + { + trxDaughterboard->FpgaDispatch = adi_fpga9025Board_Dispatch; + } + else if (trxDaughterboard->motherboardId == ADI_ADS8_PLATFORM) + { + trxDaughterboard->FpgaDispatch = adi_fpga9010Board_Dispatch; + } + + else + { + return (ADI_COMMON_HAL_GEN_SW); + } +#elif defined(ADRV9010) + if ((trxDaughterboard->daughterCardId >= ADI_BOARD_9010_MIN) && (trxDaughterboard->daughterCardId <= ADI_BOARD_9010_MAX)) + { + trxDaughterboard->BoardDispatch = adi_adrv9010Board_Dispatch; + } + /* Set up FPGA Device Dispatch pointer */ + if (trxDaughterboard->motherboardId == ADI_ADS8_PLATFORM) + { + trxDaughterboard->FpgaDispatch = adi_fpga9010Board_Dispatch; + } + + else + { + return (ADI_COMMON_HAL_GEN_SW); + } +#endif + + // Memory allocation for board device. + recoveryAction = trxDaughterboard->BoardDispatch(trxDaughterboard, + TRX_BOARD_ACTION_DEVICE_ALLOC); + if (recoveryAction != ADI_COMMON_HAL_OK) + { + if (trxDaughterboard->clockDevice) + { + free((void *)trxDaughterboard->clockDevice); + } + + if (trxDaughterboard->trxDevice) + { + free((void *)trxDaughterboard->trxDevice); + } + return (ADI_COMMON_HAL_GEN_SW); + } + + /* Memory allocation for FPGA device. FPGA is platform dependent */ + recoveryAction = trxDaughterboard->FpgaDispatch(trxDaughterboard, + TRX_BOARD_ACTION_DEVICE_ALLOC); + if ((recoveryAction != ADI_COMMON_HAL_OK) || (trxDaughterboard->fpgaDevice == 0)) + { + if (trxDaughterboard->clockDevice) + { + free((void *)trxDaughterboard->clockDevice); + } + if (trxDaughterboard->trxDevice) + { + free((void *)trxDaughterboard->trxDevice); + } + if (trxDaughterboard->fpgaDevice) + { + free((void *)trxDaughterboard->fpgaDevice); + } + return (ADI_COMMON_HAL_GEN_SW); + } + + return (ADI_COMMON_HAL_OK); +} + +int32_t adi_daughterboard_Init(adi_daughterboard_trx_t* trxDaughterboard) +{ + int32_t recoveryAction = ADI_HAL_OK; + adi_common_Device_t* commonDev; + + /* Check if function pointer is populated */ + if (adi_hal_DevHalCfgCreate == NULL) + { + /* TODO: add an error structure to the board level*/ + printf("NULL Hal layer function pointer"); + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + /* Initializing Clock common structure */ + commonDev = trxDaughterboard->clockAbstractDev.commonAbstractDevice; + commonDev->devHalInfo = adi_hal_DevHalCfgCreate((ADI_HAL_INTERFACE_SPI | ADI_HAL_INTERFACE_LOG | ADI_HAL_INTERFACE_HWRESET | ADI_HAL_INTERFACE_TIMER), + 1, + "ad9528.txt"); + if (commonDev->devHalInfo == NULL) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + /* Initializing Board common structure */ + if (((trxDaughterboard->daughterCardId >= ADI_BOARD_9025_MIN) && (trxDaughterboard->daughterCardId <= ADI_BOARD_9025_MAX)) || + ((trxDaughterboard->daughterCardId >= ADI_BOARD_9010_MIN) && (trxDaughterboard->daughterCardId <= ADI_BOARD_9010_MAX))) + { + commonDev = trxDaughterboard->trxAbstractDev.commonAbstractDevice; + commonDev->devHalInfo = adi_hal_DevHalCfgCreate((ADI_HAL_INTERFACE_SPI | ADI_HAL_INTERFACE_LOG | ADI_HAL_INTERFACE_HWRESET | ADI_HAL_INTERFACE_TIMER), + 0, + "adrvTrxLog.txt"); + if (commonDev->devHalInfo == NULL) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + } + + /* Initializing FPGA common structure */ + commonDev = trxDaughterboard->fpgaAbstractDev.commonAbstractDevice; + commonDev->devHalInfo = adi_hal_DevHalCfgCreate((ADI_HAL_INTERFACE_BBICCTRL | ADI_HAL_INTERFACE_LOG | ADI_HAL_INTERFACE_I2C | ADI_HAL_INTERFACE_TIMER), + 0, + "fpgaLog.txt"); + if (commonDev->devHalInfo == NULL) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + + /***** Open hardware for the different devices *****/ + commonDev = trxDaughterboard->fpgaAbstractDev.commonAbstractDevice; + if ((recoveryAction = adi_hal_HwOpen(commonDev->devHalInfo)) != (int32_t)ADI_HAL_OK) + { + printf("Board FPGA HwOpen failed. %s \n", + commonDev->error.errormessage); + return recoveryAction; + } + commonDev->error.logEnable = ADI_ENABLE; + + /* Open Clock device */ + recoveryAction = trxDaughterboard->ClockDispatch(trxDaughterboard, + TRX_BOARD_ACTION_DEVICE_HWOPEN); + if (recoveryAction != (int32_t)ADI_COMMON_HAL_OK) + { + printf("Clock Device HwOpen failed.\n"); + return recoveryAction; + } + + /* Open Board device */ + recoveryAction = trxDaughterboard->BoardDispatch(trxDaughterboard, + TRX_BOARD_ACTION_DEVICE_HWOPEN); + if (recoveryAction != (int32_t)ADI_COMMON_HAL_OK) + { + printf("TRX HwOpen failed.\n"); + return recoveryAction; + } + + + return (recoveryAction); +} + +static int32_t trx_board_Clear(adi_daughterboard_trx_t* trxDaughterboard) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adi_common_Device_t* commonDev; + + ADI_NULL_DEVICE_PTR_RETURN(trxDaughterboard); + + /* Check if function pointer is populated */ + if (adi_hal_DevHalCfgFree == NULL) + { + /* TODO: add an error structure to the board level*/ + printf("NULL Hal layer function pointer"); + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + /* If HW devices have been allocated, clear & free. + * Otherwise, skip. */ + if ((void *)trxDaughterboard->fpgaDevice != NULL) + { + /* Close FPGA device */ + commonDev = trxDaughterboard->fpgaAbstractDev.commonAbstractDevice; + if ((recoveryAction = adi_hal_HwClose(commonDev->devHalInfo)) != (int32_t)ADI_HAL_OK) + { + return recoveryAction; + } + adi_hal_DevHalCfgFree(commonDev->devHalInfo); + } + + if ((void *)trxDaughterboard->clockDevice != NULL) + { + /* Close Clock device */ + recoveryAction = trxDaughterboard->ClockDispatch(trxDaughterboard, + TRX_BOARD_ACTION_DEVICE_HWCLOSE); + if (recoveryAction != (int32_t)ADI_COMMON_HAL_OK) + { + printf("Clock Device HwClose failed\n"); + return recoveryAction; + } + } + + if ((void *)trxDaughterboard->BoardDispatch != NULL) + { + recoveryAction = trxDaughterboard->BoardDispatch(trxDaughterboard, + TRX_BOARD_ACTION_DEVICE_HWCLOSE); + if (recoveryAction != (int32_t)ADI_COMMON_HAL_OK) + { + printf("TRX HwClose failed\n"); + return recoveryAction; + } + } + + return recoveryAction; +} + +int32_t adi_daughterboard_Destroy(adi_daughterboard_trx_t* trxDaughterboard) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + if (trxDaughterboard == NULL) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + /* Need to bring down devices and free the common devices contain insides device structures. */ + if ((recoveryAction = trx_board_Clear(trxDaughterboard)) != ADI_COMMON_ACT_NO_ACTION) + { + return recoveryAction; + } + + /* Now free the device structures */ + if ((void *)trxDaughterboard->trxDevice != NULL) + { + if ((trxDaughterboard->boardAttribute & TRX_DAUGHTERBOARD_ATTRIBUTE_PREALLOCATE_TRX_DEVICE) == 0) + { + free((void *)trxDaughterboard->trxDevice); + } + + trxDaughterboard->trxDevice = (uintptr_t)NULL; + } + + if ((void *)trxDaughterboard->fpgaDevice != NULL) + { + free((void *)trxDaughterboard->fpgaDevice); + trxDaughterboard->fpgaDevice = (uintptr_t)NULL; + } + + if ((void *)trxDaughterboard->clockDevice != NULL) + { + free((void *)trxDaughterboard->clockDevice); + trxDaughterboard->clockDevice = (uintptr_t)NULL; + } + + /* Now free the daughterboard common device */ + if (adi_hal_DevHalCfgFree) + { + adi_hal_DevHalCfgFree((void *)trxDaughterboard->common.devHalInfo); + } + + /* Clean up specific data */ + trxDaughterboard->boardAttribute = 0; + trxDaughterboard->initializedStatus = 0; + trxDaughterboard->daughterCardName[0] = '\0'; + trxDaughterboard->daughterCardStrId[0] = '\0'; + + return recoveryAction; +} + +int32_t adi_daughterboard_Program(adi_daughterboard_trx_t* trxDaughterboard) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + if (trxDaughterboard == NULL) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + /* Execute Program Phase 1 */ + recoveryAction = trxDaughterboard->BoardProgramPhase1(trxDaughterboard); + + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + return recoveryAction; + } + + /* Execute Program Phase 2 */ + recoveryAction = trxDaughterboard->BoardProgramPhase2(trxDaughterboard); + + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + return recoveryAction; + } + + return recoveryAction; +} + +int32_t adi_daughterboard_ClockConfig(adi_daughterboard_trx_t* trxDaughterboard, + uintptr_t clockInit, + uint32_t deviceClock_kHz, + uint32_t vcxoFreq_kHz, + uint32_t refAFreq_kHz, + uint32_t fpgaClock_kHz) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + if ((trxDaughterboard == NULL) || (trxDaughterboard->BoardDispatch == NULL)) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + if (clockInit == 0) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + if ((trxDaughterboard->daughterCardId <= ADI_BOARD_BLANK_EEPROM)) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + trxDaughterboard->parameterBucket[0] = deviceClock_kHz; + trxDaughterboard->parameterBucket[1] = vcxoFreq_kHz; + trxDaughterboard->parameterBucket[2] = refAFreq_kHz; + trxDaughterboard->parameterBucket[3] = fpgaClock_kHz; + + /* Replace Clock Init if differeent */ + if (trxDaughterboard->clockInit != clockInit) + { + trxDaughterboard->clockInit = clockInit; + } + + recoveryAction = trxDaughterboard->BoardDispatch(trxDaughterboard, + TRX_BOARD_ACTION_CLOCK_CONFIG); + if (recoveryAction != (int32_t)ADI_COMMON_HAL_OK) + { + printf("TRX Clock Config failed.\n"); + return recoveryAction; + } + + return recoveryAction; +} + +int32_t adi_daughterboard_JesdBringup(adi_daughterboard_trx_t* trxDaughterboard, + uint32_t txLinkSel, + uint32_t rxLinkSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + if ((trxDaughterboard == NULL) || (trxDaughterboard->BoardDispatch == NULL)) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + trxDaughterboard->parameterBucket[0] = txLinkSel; + trxDaughterboard->parameterBucket[1] = rxLinkSel; + + recoveryAction = trxDaughterboard->BoardDispatch(trxDaughterboard, + TRX_BOARD_ACTION_DEVICE_JESD_BRINGUP); + + if (recoveryAction != (int32_t)ADI_COMMON_HAL_OK) + { + printf("TRX Jesd Bringup failed.\n"); + return recoveryAction; + } + + return recoveryAction; +} + +int32_t adi_daughterboard_JesdTxBringup(adi_daughterboard_trx_t* trxDaughterboard, + uint32_t txLinkSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + if ((trxDaughterboard == NULL) || (trxDaughterboard->BoardDispatch == NULL)) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + trxDaughterboard->parameterBucket[0] = txLinkSel; + + recoveryAction = trxDaughterboard->BoardDispatch(trxDaughterboard, + TRX_BOARD_ACTION_DEVICE_JESD_TX_BRINGUP); + + if (recoveryAction != (int32_t)ADI_COMMON_HAL_OK) + { + printf("TRX Jesd Tx Bringup failed.\n"); + return recoveryAction; + } + + return recoveryAction; +} + +int32_t adi_daughterboard_JesdRxBringup(adi_daughterboard_trx_t* trxDaughterboard, + uint32_t rxLinkSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + if ((trxDaughterboard == NULL) || (trxDaughterboard->BoardDispatch == NULL)) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + trxDaughterboard->parameterBucket[0] = rxLinkSel; + + recoveryAction = trxDaughterboard->BoardDispatch(trxDaughterboard, + TRX_BOARD_ACTION_DEVICE_JESD_RX_BRINGUP); + + if (recoveryAction != (int32_t)ADI_COMMON_HAL_OK) + { + printf("TRX Jesd Rx Bringup failed.\n"); + return recoveryAction; + } + + return recoveryAction; +} + +int32_t adi_daughterboard_Ad9528Init(adi_daughterboard_trx_t* trxDaughterboard) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + if ((trxDaughterboard == NULL) || (trxDaughterboard->BoardDispatch == NULL)) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + recoveryAction = trxDaughterboard->BoardDispatch(trxDaughterboard, TRX_BOARD_ACTION_DEVICE_AD9528_INIT); + + if (recoveryAction != (int32_t)ADI_COMMON_HAL_OK) + { + printf("Ad9528 Init has failed.\n"); + } + + return recoveryAction; +} + +int32_t adi_daughterboard_FpgaInit(adi_daughterboard_trx_t* trxDaughterboard) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + if ((trxDaughterboard == NULL) || (trxDaughterboard->BoardDispatch == NULL)) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + recoveryAction = trxDaughterboard->BoardDispatch(trxDaughterboard, TRX_BOARD_ACTION__FPGA__INIT); + + if (recoveryAction != (int32_t)ADI_COMMON_HAL_OK) + { + printf("Ad9528Init has failed.\n"); + } + + return recoveryAction; +} + +int32_t adi_daughterboard_ProgramPhase1(adi_daughterboard_trx_t* trxDaughterboard) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + if ((trxDaughterboard == NULL) || (trxDaughterboard->BoardDispatch == NULL) || (trxDaughterboard->FpgaDispatch == NULL)) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + + + /* Execute Daughterboard Phase 1*/ + recoveryAction = trxDaughterboard->BoardDispatch(trxDaughterboard, + TRX_BOARD_ACTION_PHASE_1); + + if (recoveryAction != (int32_t)ADI_COMMON_HAL_OK) + { + printf("TRX Phase 1 failed.\n"); + return recoveryAction; + } + + + + return recoveryAction; +} + +int32_t adi_daughterboard_ProgramPhase2(adi_daughterboard_trx_t* trxDaughterboard) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + if ((trxDaughterboard == NULL) || (trxDaughterboard->BoardDispatch == NULL)) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + recoveryAction = trxDaughterboard->BoardDispatch(trxDaughterboard, + TRX_BOARD_ACTION_PHASE_2); + + if (recoveryAction != (int32_t)ADI_COMMON_HAL_OK) + { + printf("TRX Phase 2 failed.\n"); + return recoveryAction; + } + + return recoveryAction; +} + +int32_t adi_daughterboard_DataInterfaceReset(adi_daughterboard_trx_t* trxDaughterboard) +{ + int32_t recoveryAction = ADI_COMMON_HAL_OK; + + if ((trxDaughterboard == NULL) || (trxDaughterboard->BoardDispatch == NULL)) + { + return (ADI_COMMON_HAL_GEN_SW); + } + + recoveryAction = trxDaughterboard->BoardDispatch(trxDaughterboard, + TRX_BOARD_ACTION_DATA_INTF_RESET); + + if (recoveryAction != (int32_t)ADI_COMMON_HAL_OK) + { + printf("TRX Phase 1 failed.\n"); + return recoveryAction; + } + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adi_daughterboard_trx_dev.h b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adi_daughterboard_trx_dev.h new file mode 100644 index 0000000..7693545 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adi_daughterboard_trx_dev.h @@ -0,0 +1,275 @@ +#ifndef _ADI_DAUGHTERBOARD_TRX_DEV_H_ +#define _ADI_DAUGHTERBOARD_TRX_DEV_H_ + +#include "adi_daughterboard_trx_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************** +* Runtime functions +**************************************************************************** +*/ + +/** +* \brief This function implements the following +* Closes Device drivers in use by the requested board +* Deallocates memory consumed by device HAL instances +* Removes the daughter board instance from the list of daughter cards instantiated +* Deallocates memory for device instances in the board requested +* Updates the list of daughter boards active +* +* \dep_begin +* \dep{genericBoardHandle} +* \dep_end +* +* \param genericBoardHandle Pointer to the generic board instance +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_daughterboard_Destroy(adi_daughterboard_trx_t* genericBoardHandle); + +/** +* \brief This function creates a device board instance for daughter card +* This function will create the clock instance +* This function will also create the FPGA instance for motherboard +* +* \dep_begin +* \dep{trxDaughterboard} +* \dep_end +* +* \param trxDaughterboard Pointer to the generic board instance +* +* \retval ADI_COMMON_HAL_GEN_SW Recovery action returned in case of error (null pointer or unable to allocate structures) +* \retval ADI_COMMON_HAL_OK Function completed successfully + +*/ +int32_t adi_daughterboard_Create(adi_daughterboard_trx_t* trxDaughterboard); + +/** +* \brief Function to Initialize the devices +* This function will create the platform layer structures for the different devices +* This function will open the HW needed for the devices +* +* \dep_begin +* \dep{trxDaughterboard} +* \dep_end +* +* \param trxDaughterboard Pointer to the generic board instance +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_daughterboard_Init(adi_daughterboard_trx_t* trxDaughterboard); + +/** +* \brief Function to Program the daughter card board +* This function will program the devices that are contained in the daughter card board +* +* \pre This function is called after the devices are Create() +* Init() have been called +* +* \dep_begin +* \dep{trxDaughterboard} +* \dep_end +* +* \param trxDaughterboard Pointer to the generic board instance +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_daughterboard_Program(adi_daughterboard_trx_t* trxDaughterboard); + +/** +* \brief Function to execute Program Phase 1 the daughter card board +* This function will program the devices that are contained in the daughter card board +* +* \pre This function is called after the devices are Create() +* Init() have been called +* +* \dep_begin +* \dep{trxDaughterboard} +* \dep_end +* +* \param trxDaughterboard Pointer to the generic board instance +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_daughterboard_ProgramPhase1(adi_daughterboard_trx_t* trxDaughterboard); + +/** +* \brief Function to execute Program Phase 2 the daughter card board +* This function will program the devices that are contained in the daughter card board +* +* \pre This function is called after the devices are Create() +* Init() have been called +* +* \dep_begin +* \dep{trxDaughterboard} +* \dep_end +* +* \param trxDaughterboard Pointer to the generic board instance +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_daughterboard_ProgramPhase2(adi_daughterboard_trx_t* trxDaughterboard); + +/** +* \brief Function to Confgiure Board Clock Settings +* This function will configure the Clock settings for the board +* +* \dep_begin +* \dep{ad9528Init} +* \dep_end +* +* \param trxDaughterboard Pointer to the generic board instance +* \param clockInit Pointer to AD9528 clock device init structure. +* \param deviceClock_kHz Device clock frequency in kHz +* \param vcxoFreq_kHz VCXO clock frequency in kHz +* \param refAFreq_kHz RefA clock frequency in kHz +* \param fpgaClock_kHz FPGA clock frequency in kHz +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_daughterboard_ClockConfig(adi_daughterboard_trx_t* trxDaughterboard, + uintptr_t clockInit, + uint32_t deviceClock_kHz, + uint32_t vcxoFreq_kHz, + uint32_t refAFreq_kHz, + uint32_t fpgaClock_kHz); + +/** +* \brief Function to bring up the JESD204 data link for the motherboard eval board. +* +* \pre This function is normally called by the Program_v2 +* function and is not required by the end user. It would be called after +* post MCS init. +* +* \dep_begin +* \dep{trxDaughterboard} +* \dep_end +* +* \param trxDaughterboard Pointer to the generic board instance +* \param txLinkSel Bitmask representing which RF TX links to enable (Bit0=1: Enable Deframer 0, Bit1=1: Enable Deframer 1) +* \param rxLinkSel Bitmask representing which RF RX links to enable (Bit0=1: Enable Framer 0, Bit1=1: Enable Framer 1, Bit2=1: Enable Framer 2) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_daughterboard_JesdBringup(adi_daughterboard_trx_t* trxDaughterboard, + uint32_t txLinkSel, + uint32_t rxLinkSel); + +/** +* \brief Function to bring up the JESD204 TX data link for the motherboard eval board. +* +* \pre This function is normally called by the adi_daughterboard_JesdBringup +* function and is not required by the end user. It would be called after +* post MCS init. +* +* \dep_begin +* \dep{trxDaughterboard} +* \dep_end +* +* \param trxDaughterboard Pointer to the generic board instance +* \param txLinkSel Bitmask representing which RF TX links to enable (Bit0=1: Enable Deframer 0, Bit1=1: Enable Deframer 1) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_daughterboard_JesdTxBringup(adi_daughterboard_trx_t* trxDaughterboard, + uint32_t txLinkSel); + +/** +* \brief Function to bring up the JESD204 RX data link for the motherboard eval board. +* +* \pre This function is normally called by the adi_daughterboard_JesdBringup +* function and is not required by the end user. It would be called after +* post MCS init. +* +* \dep_begin +* \dep{trxDaughterboard} +* \dep_end +* +* \param trxDaughterboard Pointer to the generic board instance +* \param rxLinkSel Bitmask representing which RF RX links to enable (Bit0=1: Enable Framer 0, Bit1=1: Enable Framer 1, Bit2=1: Enable Framer 2) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_daughterboard_JesdRxBringup(adi_daughterboard_trx_t* trxDaughterboard, + uint32_t rxLinkSel); + +/** +* \brief Resets the Data Interface with the appropriate procedure based on the daughterboard +* type. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param trxDaughterboard Pointer to the generic board instance +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_daughterboard_DataInterfaceReset(adi_daughterboard_trx_t* trxDaughterboard); + +/** +* \brief Initializes the AD9528 by writing all SPI registers +* +* Initializes the AD9528 using the values passed in through the adi_daughterboard_trx_t structure. +* +* Dependencies +* - All parameters in init structure +* - device->common.devHalInfo +* +* \param trxDaughterboard Pointer to the generic board instance +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter +* check +*/ +int32_t adi_daughterboard_Ad9528Init(adi_daughterboard_trx_t* trxDaughterboard); + +/** +* \brief Initializes the FPGA device +* +* Initializes the FPGA using the values passed in through the adi_daughterboard_trx_t structure. +* +* \pre adi_fpga9010Board_Dispatch API invoked and completed successfully +* +* \param trxDaughterboard Pointer to the generic board instance +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +*/ +int32_t adi_daughterboard_FpgaInit(adi_daughterboard_trx_t* trxDaughterboard); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adi_daughterboard_trx_types.h b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adi_daughterboard_trx_types.h new file mode 100644 index 0000000..f49ff14 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adi_daughterboard_trx_types.h @@ -0,0 +1,164 @@ +#ifndef _ADI_DAUGHTERBOARD_TRX_TYPES_H_ +#define _ADI_DAUGHTERBOARD_TRX_TYPES_H_ + +#include +#include "adi_common.h" +#include "adi_fmc_fru.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifndef ADI_BOARD_NAME_SIZE +#define ADI_BOARD_NAME_SIZE 64 +#endif + +#define TRX_DAUGHTERBOARD_ATTRIBUTE_TYPE_EE 0x00000001 +#define TRX_DAUGHTERBOARD_ATTRIBUTE_PREALLOCATE_TRX_DEVICE 0x00000002 + +typedef enum adrvtrx_board_action +{ + TRX_BOARD_ACTION_NONE = 0, + TRX_BOARD_ACTION_DEVICE_ALLOC, + TRX_BOARD_ACTION_DEVICE_HWOPEN, + TRX_BOARD_ACTION_DEVICE_HWCLOSE, + TRX_BOARD_ACTION_CLOCK_CONFIG, + TRX_BOARD_ACTION_DEVICE_JESD_BRINGUP, + TRX_BOARD_ACTION_DEVICE_JESD_TX_BRINGUP, + TRX_BOARD_ACTION_DEVICE_JESD_RX_BRINGUP, + TRX_BOARD_ACTION_PHASE_1, + TRX_BOARD_ACTION_PHASE_2, + TRX_BOARD_ACTION_DATA_INTF_RESET, + + TRX_BOARD_ACTION_FPGA_INIT, + TRX_BOARD_ACTION_DEVICE_AD9528_INIT, + TRX_BOARD_ACTION__FPGA__INIT +} adrvtrx_board_action_e; + +typedef struct adi_daughterboard_trx adi_daughterboard_trx_t; + +/** +* \brief Data structure to hold SPI settings for all system device types +*/ +typedef struct adi_adrvtrx_SpiSettings +{ + uint8_t msbFirst; /*!< 1 = MSB First, 0 = LSB First Bit order for SPI transaction */ + uint8_t enSpiStreaming; /*!< Not Recommended - most registers in ADRV9010 API are not consecutive */ + uint8_t autoIncAddrUp; /*!< For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr = addr-1 */ + uint8_t fourWireMode; /*!< 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */ + uint32_t cmosPadDrvStrength; /*!< Drive strength of CMOS pads when used as outputs (SDIO, SDO, GP_INTERRUPT, GPIO 1, GPIO 0) */ +} adi_adrvtrx_SpiSettings_t; + +/* + * \brief This is a union structure to contain several structures. It is intended to either access the common pointer (which is the fist element of device structure) + * or the device structure itself. + */ +typedef union adi_trxAbstract_union +{ + adi_common_Device_t* commonAbstractDevice; + uintptr_t fpgaAbstractDevice; /*!< Abstract pointer to FPGA device */ + uintptr_t trxAbstractDevice; /*!< Abstract pointer to TRX device i.e. 9010, 9025 */ + uintptr_t clockAbstractDevice; /*!< Abstract pointer to Clock device */ +} adi_trxAbstract_union_t; + +/* + * \brief Saving some necessary information during initialization for later access. + */ +typedef struct adi_adrvtrx_MiscInfo +{ + uint8_t enable204cState; + uintptr_t spi2Device; +} adi_adrvtrx_MiscInfo_t; + +/** +* \brief Data structure to hold devices in an daughter card +*/ +typedef struct adi_daughterboard_trx +{ + /* Common device */ + adi_common_Device_t common; /*!< Pointer to common device */ + + /* Initialization status */ + uint32_t initializedStatus; /*!< initialization status */ + uint32_t boardAttribute; /*!< Board attributes */ + + /* Place holder for extra parameters */ + uint32_t parameterBucket[12]; /*!< place holder for extra scalar parameters */ + uintptr_t parameterPointers[12]; /*!< place holder for extra pointer parameters */ + + /* Platform and board information */ + uint32_t daughterCardId; /*!< Board (daughter card) ID */ + uint8_t daughterCardRev[4]; /*!< Board Revision */ + int8_t daughterCardStrId[6]; /*!< Board ID string i.e. "9010", "9025" */ + int8_t daughterCardName[ADI_BOARD_NAME_SIZE]; /*!< Board name string */ + uint32_t motherboardId; /*!< The motherboard type i.e ADS8, ADS9 etc. */ + int8_t motherboardName[ADI_BOARD_NAME_SIZE]; /*!< Platform name string */ + adi_adrvtrx_MiscInfo_t savedInfo; /*!< Saving some necessary information */ + + /* Device pointers */ + uintptr_t trxDevice; /*!< Pointer to transceiver device on board */ + uintptr_t fpgaDevice; /*!< Pointer to FPGA device on board */ + uintptr_t clockDevice; /*!< Pointer to clock device on board */ + + adi_trxAbstract_union_t trxAbstractDev; /*!< Abstract TRX device on board */ + adi_trxAbstract_union_t fpgaAbstractDev; /*!< Abstract FPGA device on board */ + adi_trxAbstract_union_t clockAbstractDev; /*!< Abstract CLOCK device on board */ + + uintptr_t motherboardDevice; /*!< Pointer back to the motherboard which contains this daughterboard */ + + /* Initialization pointers */ + uintptr_t daughterCardInit; /*!< Init data structure configured with the profile data*/ + uintptr_t postMcsInit; /*common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param adrv9025Init Pointer to the ADRV9025 init structure +* \param framerSel Select the framer to read +* \param iqRate_kHz Pointer to uint32_t where the iqRate_kHz will be written +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025Board_RxLinkSamplingRateFind(adi_fpga9025_Device_t* device, + adi_adrv9025_Init_t* adrv9025Init, + adi_adrv9025_FramerSel_e framerSel, + uint32_t* iqRate_kHz); + +/** +* \brief Returns the iqRate for the selected ADRV9025 Deframer. If the selected Deframer has an M equal to 0, +* the function will return 0 for iqRate. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param adrv9025Init Pointer to the ADRV9025 init structure +* \param deframerSel Select the deframer to read +* \param iqRate_kHz Pointer to uint32_t where the iqRate_kHz will be written +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025Board_TxLinkSamplingRateFind(adi_fpga9025_Device_t* device, + adi_adrv9025_Init_t* adrv9025Init, + adi_adrv9025_DeframerSel_e deframerSel, + uint32_t* iqRate_kHz); + +/** +* \brief Using the ADI daughter card EEPROM BOM REV (3rd custom FMC) field, this function will +* override the profile ldoSelect setting with the correct setting for the EEPROM contents. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param adrv9025Init Pointer to the ADRV9025 init structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025Board_LdoSelectOverRide(adi_adrv9025_Init_t* adrv9025Init); + +/** +* \brief Resets the Data Interface with the appropriate procedure based on the daughterboard +* type. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param adrv9025Board adi_board_GenericBoardType_t Pointer to the ADRV9025 daughter card instance +* to be programmed +* \param adrv9025BoardSel is the enum to select the daughter card (EE01 / CE01) +* \param adrv9025Init Pointer to the ADRV9025 init structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025Board_DataInterfaceReset(adi_board_GenericBoardType_t* adrv9025Board, + adi_board_adrv9025Sel_e adrv9025BoardSel, + adi_adrv9025_Init_t* adrv9025Init); + +/** +* \brief Function to configure the AD9528 init structure for the daughtercard based +* on the desired device clock. This function will NOT program the AD9528. +* +* \pre This function is called after the devices are Create() +* Init() have been called +* +* \dep_begin +* \dep{trxDaughterboard} +* \dep_end +* +* \param trxDaughterboard Pointer to the generic board instance +* \param deviceClock_kHz Desired device clock in kHz +* \param vcxoFreq_kHz Frequency of the AD9528 Vcxo input in kHz +* \param refAFreq_kHz Frequency of the AD9528 RefA input in kHz +* \param fpgaClock_kHz Desired fpga clock in kHz +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_board_adrv9025_Ad9528Configure(adi_daughterboard_trx_t* trxDaughterboard, + uint32_t deviceClock_kHz, + uint32_t vcxoFreq_kHz, + uint32_t refAFreq_kHz, + uint32_t fpgaClock_kHz); + +/** +* \brief Function to bring up the JESD204 data link for the ADRV9025 eval board. +* +* \pre This function is normally called by the adi_board_adrv9025_Program_Phase2 +* function and is not required by the end user. It would be called after +* post MCS init. +* +* \dep_begin +* \dep{trxDaughterboard} +* \dep_end +* +* \param trxDaughterboard Pointer to the generic board instance +* \param txLinkSel Bitmask representing which RF TX links to enable (Bit0=1: Enable Deframer 0, Bit1=1: Enable Deframer 1) +* \param rxLinkSel Bitmask representing which RF RX links to enable (Bit0=1: Enable Framer 0, Bit1=1: Enable Framer 1, Bit2=1: Enable Framer 2) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_board_adrv9025_JesdBringup(adi_daughterboard_trx_t* trxDaughterboard, + uint32_t txLinkSel, + uint32_t rxLinkSel); + +/** +* \brief Function to bring up the JESD204 TX data link for the ADRV9025CE01 eval board. +* +* \pre This function is normally called by the adi_board_adrv9025_JesdBringup +* function and is not required by the end user. It would be called after +* post MCS init. +* +* \dep_begin +* \dep{trxDaughterboard} +* \dep_end +* +* \param trxDaughterboard Pointer to the generic board instance +* \param link Bitmask representing which RF TX links to enable (Bit0=1: Enable Deframer 0, Bit1=1: Enable Deframer 1) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_board_adrv9025_JesdTxBringup(adi_daughterboard_trx_t* trxDaughterboard, + uint32_t link); + +/** +* \brief Function to bring up the JESD204 RX data link for the ADRV9025CE01 eval board. +* +* \pre This function is normally called by the adi_board_adrv9025CE01_JesdBringup +* function and is not required by the end user. It would be called after +* post MCS init. +* +* \dep_begin +* \dep{trxDaughterboard} +* \dep_end +* +* \param trxDaughterboard Pointer to the generic board instance +* \param link Bitmask representing which RF RX links to enable (Bit0=1: Enable Framer 0, Bit1=1: Enable Framer 1, Bit2=1: Enable Framer 2) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_board_adrv9025CE01_JesdRxBringup(adi_daughterboard_trx_t* trxDaughterboard, + uint32_t link); + +/** +* \brief Function to reset and bring JESD204 links up using parameters from the daughterboard structure +* +* \pre This function is called after the devices are Create() +* Init() have been called +* +* \dep_begin +* \dep{trxDaughterboard} +* \dep_end +* +* \param trxDaughterboard Pointer to the generic board instance +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_board_adrv9025CE01_Jesd204LinkReset(adi_daughterboard_trx_t* trxDaughterboard); + +/** +* \brief Function to initialize the clock device +* +* \pre This function is called during the daughtercard initialization. +* +* \dep_begin +* \dep{trxDaughterboard} +* \dep_end +* +* \param trxDaughterboard Pointer to the generic board instance +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_board_adrv9025_Ad9528Init(adi_daughterboard_trx_t* trxDaughterboard); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adrv9025/include/adi_adrv9025_daughter_board_types.h b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adrv9025/include/adi_adrv9025_daughter_board_types.h new file mode 100644 index 0000000..97bf635 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adrv9025/include/adi_adrv9025_daughter_board_types.h @@ -0,0 +1,46 @@ +/** + * \file adi_adrv9025_daughter_board_types.h + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_ADRV9025_DAUGHTER_BOARD_TYPES_H_ +#define _ADI_ADRV9025_DAUGHTER_BOARD_TYPES_H_ + +#include "adi_adrv9025_types.h" +#include "adi_ad9528_types.h" +//#include "adi_fpga9025_types.h" +#include "adi_adrv9025_utilities_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \brief Enum of possible daughter board types +*/ +typedef enum adi_board_adrv9025Sel +{ + ADI_BOARD_ADRV9025_EE01 = 0xEE01, /*!< Selects a daughter board of type EE01 */ + ADI_BOARD_ADRV9025_CE01 = 0xCE01, /*!< Selects a daughter board of type CE01 */ + ADI_BOARD_ADRV9026_CE01 = 0xCE01, /*!< Selects a daughter board of type CE01 */ + ADI_BOARD_ADRV9025_STSHAL01 = 0xFF00, /*!< Selects a daughter board of type stsHal for all non-init actions */ + ADI_BOARD_ADRV9025_ADS8 = 0xAD58, /*!< Selects a daughter board of type stsHal for all non-init actions */ + ADI_BOARD_ADRV9025_NULL = 0, /*!< Initial value for board selection */ + ADI_BOARD_ADRV9025_BLANK_EEPROM = 1 /*!< Selects for no daughter board present */ +} adi_board_adrv9025Sel_e; + +typedef uintptr_t adi_board_GenericBoardType_t; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adrv9025/include/adi_board_adrv9025ADS8.h b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adrv9025/include/adi_board_adrv9025ADS8.h new file mode 100644 index 0000000..3c89c2f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adrv9025/include/adi_board_adrv9025ADS8.h @@ -0,0 +1,169 @@ +/** + * \file adi_board_adrv9025ADS8.h + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_BOARD_ADRV9025ADS8_H_ +#define _ADI_BOARD_ADRV9025ADS8_H_ + +#include "adi_adrv9025_daughter_board_types.h" +#include "adi_board_adrv9025ADS8_types.h" +#include "adi_adrv9025_utilities_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Function to configure the AD9528 init structure for the CE daughtercard based +* on the desired device clock. This function will NOT program the AD9528. +* +* \pre This function is called after the devices are Create() +* Init() have been called +* +* \dep_begin +* \dep{ad9528Device, ad9528Init} +* \dep_end +* +* \param ad9528Device Pointer to AD9528 device data structure +* \param ad9528Init Pointer to AD9528 clock device init structure +* \param deviceClock_kHz Desired device clock in kHz +* \param vcxoFreq_kHz Frequency of the AD9528 Vcxo input in kHz +* \param refAFreq_kHz Frequency of the AD9528 RefA input in kHz +* \param fpgaClock_kHz Desired fpga clock in kHz +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_board_adrv9025ADS8_Ad9528Configure(adi_board_adrv9025Ads8_t* adrv9025ADS8, + adi_ad9528_Init_t* ad9528Init, + uint32_t deviceClock_kHz, + uint32_t vcxoFreq_kHz, + uint32_t refAFreq_kHz, + uint32_t fpgaClock_kHz); + +/** +* \brief Function to bring up the JESD204 data link for the adrv9025ADS8 eval board. +* +* \pre This function is normally called by the adi_board_adrv9025ADS8_Program_v2 +* function and is not required by the end user. It would be called after +* post MCS init. +* +* \dep_begin +* \dep{adrv9025Device, fpga9010Device, ad9528Device} +* \dep_end +* +* \param adrv9025Device Pointer to ADRV9025 device data structure +* \param fpga9010Device Pointer to FPGA device data structure +* \param ad9528Device Pointer to AD9528 device data structure +* \param txLinkSel Bitmask representing which RF TX links to enable (Bit0=1: Enable Deframer 0, Bit1=1: Enable Deframer 1) +* \param rxLinkSel Bitmask representing which RF RX links to enable (Bit0=1: Enable Framer 0, Bit1=1: Enable Framer 1, Bit2=1: Enable Framer 2) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_board_adrv9025ADS8_JesdBringup(adi_adrv9025_Device_t* adrv9025Device, + adi_fpga9010_Device_t* fpgaDevice, + adi_ad9528_Device_t* ad9528Device, + uint32_t txLinkSel, + uint32_t rxLinkSel); + +/** +* \brief Function to bring up the JESD204 TX data link for the adrv9025ADS8 eval board. +* +* \pre This function is normally called by the adi_board_adrv9025ADS8_JesdBringup +* function and is not required by the end user. It would be called after +* post MCS init. +* +* \dep_begin +* \dep{adrv9025Device, fpga9010Device, ad9528Device} +* \dep_end +* +* \param adrv9025Device Pointer to ADRV9025 device data structure +* \param fpga9010Device Pointer to FPGA device data structure +* \param ad9528Device Pointer to AD9528 device data structure +* \param link Bitmask representing which RF TX links to enable (Bit0=1: Enable Deframer 0, Bit1=1: Enable Deframer 1) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_board_adrv9025ADS8_JesdTxBringup(adi_adrv9025_Device_t* adrv9025Device, + adi_fpga9010_Device_t* fpga9010Device, + adi_ad9528_Device_t* ad9528Device, + uint32_t link); + +/** +* \brief Function to bring up the JESD204 RX data link for the adrv9025ADS8 eval board. +* +* \pre This function is normally called by the adi_board_adrv9025ADS8_JesdBringup +* function and is not required by the end user. It would be called after +* post MCS init. +* +* \dep_begin +* \dep{adrv9025Device, fpga9010Device, ad9528Device} +* \dep_end +* +* \param adrv9025Device Pointer to ADRV9025 device data structure +* \param fpga9010Device Pointer to FPGA device data structure +* \param ad9528Device Pointer to AD9528 device data structure +* \param link Bitmask representing which RF RX links to enable (Bit0=1: Enable Framer 0, Bit1=1: Enable Framer 1, Bit2=1: Enable Framer 2) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_board_adrv9025ADS8_JesdRxBringup(adi_adrv9025_Device_t* adrv9025Device, + adi_fpga9010_Device_t* fpga9010Device, + adi_ad9528_Device_t* ad9528Device, + uint32_t link); + +int32_t adi_board_adrv9025ADS8_Program_Phase1(adi_board_adrv9025Ads8_t* adrv9025Ce01, + adi_adrv9025_Init_t* adrv9025Init, + adi_ad9528_Init_t* ad9528Init, + adi_adrv9025_PlatformFiles_t* adrv9025PlatformFiles); + +int32_t adi_board_adrv9025ADS8_Program_Phase2(adi_board_adrv9025Ads8_t* adrv9025Ce01, + adi_adrv9025_Init_t* adrv9025Init, + adi_adrv9025_PostMcsInit_t* adrv9025PostMcsInit, + adi_ad9528_Init_t* ad9528Init); + +/** +* \brief Function to reset and bring JESD204 links up using parameters from the init structure +* +* \pre This function is called after the devices are Create() +* Init() have been called +* +* \dep_begin +* \dep{adrv9025Device, adrv9025Init} +* \dep_end +* +* \param adrv9025ADS8 Pointer to adrv9025ADS8 daughter card instance to be programmed +* \param adrv9025Init Pointer to ADRV9025 Init data structure configured with the profile data +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_board_adrv9025ADS8_Jesd204LinkReset(adi_board_adrv9025Ads8_t* adrv9025ADS8, + adi_adrv9025_Init_t* adrv9025Init); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adrv9025/include/adi_board_adrv9025ADS8_types.h b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adrv9025/include/adi_board_adrv9025ADS8_types.h new file mode 100644 index 0000000..3a40164 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adrv9025/include/adi_board_adrv9025ADS8_types.h @@ -0,0 +1,41 @@ +/** + * \file adi_board_adrv9025CE01_types.h + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_BOARD_ADRV9025ADS8_TYPES_H_ +#define _ADI_BOARD_ADRV9025ADS8_TYPES_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "adi_adrv9025_types.h" +#include "adi_ad9528_types.h" +#include "adi_fpga9010_types.h" + +/** +* \brief Data structure to hold devices in an adi_board_adrv9025Ads8 daughter card +*/ +typedef struct adi_board_adrv9025Ads8 +{ + adi_adrv9025_Device_t* adrv9025Device; /*!< Pointer to ADRV9025 device on CE01 board */ + adi_fpga9010_Device_t* fpgaDevice; /*!< Pointer to FPGA device on CE01 board */ + adi_ad9528_Device_t* ad9528Device; /*!< Pointer to AD9528 clock device on CE01 board */ + + /* TODO: Update this with final interface */ + char pcbName[32]; +} adi_board_adrv9025Ads8_t; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adrv9025/src/adi_adrv9025_daughter_board.c b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adrv9025/src/adi_adrv9025_daughter_board.c new file mode 100644 index 0000000..6a8059e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adrv9025/src/adi_adrv9025_daughter_board.c @@ -0,0 +1,2222 @@ +/** + * \file adi_adrv9025_daughter_board.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_adrv9025_daughter_board.h" + +#include "adi_board_adrv9025ADS8.h" + + + +#include "adi_ad9528.h" +#include "adi_ad9528_utilities.h" +#include "adi_fpga9025_utilities.h" +#include "adi_adrv9025_gpio.h" +#include "adi_adrv9025_utilities.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_data_interface.h" +#include "adi_fpga9025.h" +#include "adi_fpga9010.h" +#include "platform_utils/adi_fmc_fru.h" +#include "platform_utils/adi_fmc_eeprom.h" +#include +#include +#include "adi_platform_identify.h" +#include "adi_motherboard_trx.h" + +#include "adi_fpga9025_axi_adv_spi.h" +#include "adi_fpga9025_clk.h" +#include "adi_fpga9025_jesd.h" +#include "adi_adrv9025_cals.h" +#define LANESENABLEDBINTODEC(x) ( (x & 0b0001) + ((x & 0b0010)>>1) + ((x & 0b0100)>>2) + ((x & 0b1000)>>3)) +/**************************************************************************** +* Local functions +****************************************************************************/ +int32_t adi_board_adrv9025_Ad9528Init(adi_daughterboard_trx_t* trxDaughterboard) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adi_ad9528_Device_t* ad9528Device = NULL; + adi_ad9528_Init_t* ad9528Init = NULL; + + if (trxDaughterboard == NULL) + { + return (ADI_COMMON_ACT_ERR_RESET_FULL); + } + + ad9528Device = (adi_ad9528_Device_t *)trxDaughterboard->clockDevice; + ad9528Init = (adi_ad9528_Init_t *)trxDaughterboard->clockInit; + + if ((recoveryAction = adi_ad9528_HwReset(ad9528Device)) < 0) + { + return recoveryAction; + } + + + if ((recoveryAction = adi_ad9528_Initialize(ad9528Device, + ad9528Init)) < 0) + { + return recoveryAction; + } + + + return recoveryAction; +} + +int32_t adi_board_adrv9025_Ad9528Configure(adi_daughterboard_trx_t* trxDaughterboard, + uint32_t deviceClock_kHz, + uint32_t vcxoFreq_kHz, + uint32_t refAFreq_kHz, + uint32_t fpgaClock_kHz) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adi_ad9528_ClockFrequencySettings_t clockFrequencies = {0}; + adi_ad9528_Device_t* ad9528Device = NULL; + adi_ad9528_Init_t* ad9528Init = NULL; + + if (trxDaughterboard == NULL) + { + return (ADI_COMMON_ACT_ERR_RESET_FULL); + } + ad9528Device = (adi_ad9528_Device_t *)trxDaughterboard->clockDevice; + ad9528Init = (adi_ad9528_Init_t *)trxDaughterboard->clockInit; + + clockFrequencies.vcxoFrequency_Hz = vcxoFreq_kHz * 1000; + if ((trxDaughterboard->boardAttribute & TRX_DAUGHTERBOARD_ATTRIBUTE_TYPE_EE) == 0) + { + clockFrequencies.refAFrequency_Hz = refAFreq_kHz * 1000; + clockFrequencies.outputClock_Hz[1] = deviceClock_kHz * 1000; + } + + clockFrequencies.outputClock_Hz[0] = 120000; /* TODO: SYSREF should not be fixed, this will break future profiles */ + clockFrequencies.outputClock_Hz[3] = fpgaClock_kHz * 1000; + clockFrequencies.outputClock_Hz[12] = 120000; + clockFrequencies.outputClock_Hz[13] = fpgaClock_kHz * 1000; + clockFrequencies.outSource[0] = ADI_AD9528_SYSREF; + clockFrequencies.outSource[12] = ADI_AD9528_SYSREF; + + /* Clear out the init structure because InitStructConfig sets all appropriate members */ + memset(ad9528Init, + 0, + sizeof(adi_ad9528_Init_t)); + + if ((recoveryAction = adi_ad9528_InitStructConfig(ad9528Device, + &clockFrequencies, + ad9528Init)) < 0) + { + return recoveryAction; + } + + if ((trxDaughterboard->boardAttribute & TRX_DAUGHTERBOARD_ATTRIBUTE_TYPE_EE) == 0) + { + ad9528Init->pll1Settings.vcxoBufferCtrl = ADI_AD9528_SINGLE_ENDED; + } + + return recoveryAction; +} + +int32_t adi_adrv9025Board_RxLinkSamplingRateFind(adi_fpga9025_Device_t* device, + adi_adrv9025_Init_t* adrv9025Init, + adi_adrv9025_FramerSel_e framerSel, + uint32_t* iqRate_kHz) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adi_adrv9025_AdcSampleXbarSel_e conv = ADI_ADRV9025_ADC_RX1_Q; + uint32_t framerIndex = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_NULL_PTR_RETURN(&device->common, + iqRate_kHz); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + switch (framerSel) + { + case ADI_ADRV9025_FRAMER_0: + framerIndex = 0; + break; + case ADI_ADRV9025_FRAMER_1: + framerIndex = 1; + break; + case ADI_ADRV9025_FRAMER_2: + framerIndex = 2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Only one framer can be selected at a time."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + if (adrv9025Init->dataInterface.framer[framerIndex].jesd204M < 1) + { + *iqRate_kHz = 0; + return recoveryAction; + } + + conv = adrv9025Init->dataInterface.framer[framerIndex].adcCrossbar.conv0; + + switch (conv) + { + case ADI_ADRV9025_ADC_RX1_I: /* fall through */ + case ADI_ADRV9025_ADC_RX1_Q: /* fall through */ + case ADI_ADRV9025_ADC_DUALBAND_RX1_BAND_B_I: /* fall through */ + case ADI_ADRV9025_ADC_DUALBAND_RX1_BAND_B_Q: /* fall through */ + *iqRate_kHz = adrv9025Init->rx.rxChannelCfg[0].profile.rxOutputRate_kHz; + break; + + case ADI_ADRV9025_ADC_RX2_I: /* fall through */ + case ADI_ADRV9025_ADC_RX2_Q: /* fall through */ + case ADI_ADRV9025_ADC_DUALBAND_RX2_BAND_B_I: /* fall through */ + case ADI_ADRV9025_ADC_DUALBAND_RX2_BAND_B_Q: /* fall through */ + *iqRate_kHz = adrv9025Init->rx.rxChannelCfg[1].profile.rxOutputRate_kHz; + break; + + case ADI_ADRV9025_ADC_RX3_I: /* fall through */ + case ADI_ADRV9025_ADC_RX3_Q: /* fall through */ + case ADI_ADRV9025_ADC_DUALBAND_RX3_BAND_B_I: /* fall through */ + case ADI_ADRV9025_ADC_DUALBAND_RX3_BAND_B_Q: /* fall through */ + *iqRate_kHz = adrv9025Init->rx.rxChannelCfg[2].profile.rxOutputRate_kHz; + break; + + case ADI_ADRV9025_ADC_RX4_I: /* fall through */ + case ADI_ADRV9025_ADC_RX4_Q: /* fall through */ + case ADI_ADRV9025_ADC_DUALBAND_RX4_BAND_B_I: /* fall through */ + case ADI_ADRV9025_ADC_DUALBAND_RX4_BAND_B_Q: /* fall through */ + *iqRate_kHz = adrv9025Init->rx.rxChannelCfg[3].profile.rxOutputRate_kHz; + break; + + // NOTE: ORx2/4 profiles never referenced, ORx2IQ enum below refers to digital channel not RF input + // RF ORx1/2 share digital ORX1, and RF ORX3/4 share digital ORX2 + case ADI_ADRV9025_ADC_ORX1_I: /* fall through */ + case ADI_ADRV9025_ADC_ORX1_Q: /* fall through */ + *iqRate_kHz = adrv9025Init->rx.rxChannelCfg[4].profile.rxOutputRate_kHz; + break; + + // NOTE: ORx2/4 profiles never referenced, ORx2IQ enum below refers to digital channel not RF input + // RF ORx1/2 share digital ORX1, and RF ORX3/4 share digital ORX2 + case ADI_ADRV9025_ADC_ORX2_I: /* fall through */ + case ADI_ADRV9025_ADC_ORX2_Q: /* fall through */ + *iqRate_kHz = adrv9025Init->rx.rxChannelCfg[6].profile.rxOutputRate_kHz; + break; + + default: + *iqRate_kHz = 0; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + adcCrossbar.conv0, + "Invalid ADC crossbar used to read iqRate_kHz"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_adrv9025Board_TxLinkSamplingRateFind(adi_fpga9025_Device_t* device, + adi_adrv9025_Init_t* adrv9025Init, + adi_adrv9025_DeframerSel_e deframerSel, + uint32_t* iqRate_kHz) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t deframerIndex = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_NULL_PTR_RETURN(&device->common, + iqRate_kHz); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + switch (deframerSel) + { + case ADI_ADRV9025_DEFRAMER_0: + deframerIndex = 0; + break; + case ADI_ADRV9025_DEFRAMER_1: + deframerIndex = 1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSel, + "Only one deframer can be selected at a time."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + if (adrv9025Init->dataInterface.deframer[deframerIndex].jesd204M < 1) + { + *iqRate_kHz = 0; + return recoveryAction; + } + + //Use samplerate of DAC set to use deframer output 0. + if ((adrv9025Init->dataInterface.deframer[deframerIndex].dacCrossbar.tx1DacChanI == ADI_ADRV9025_DEFRAMER_OUT0) || + (adrv9025Init->dataInterface.deframer[deframerIndex].dacCrossbar.tx1DacChanQ == ADI_ADRV9025_DEFRAMER_OUT0)) + { + *iqRate_kHz = adrv9025Init->tx.txChannelCfg[0].profile.txInputRate_kHz; + } + else if ((adrv9025Init->dataInterface.deframer[deframerIndex].dacCrossbar.tx2DacChanI == ADI_ADRV9025_DEFRAMER_OUT0) || + (adrv9025Init->dataInterface.deframer[deframerIndex].dacCrossbar.tx2DacChanQ == ADI_ADRV9025_DEFRAMER_OUT0)) + { + *iqRate_kHz = adrv9025Init->tx.txChannelCfg[1].profile.txInputRate_kHz; + } + else if ((adrv9025Init->dataInterface.deframer[deframerIndex].dacCrossbar.tx3DacChanI == ADI_ADRV9025_DEFRAMER_OUT0) || + (adrv9025Init->dataInterface.deframer[deframerIndex].dacCrossbar.tx3DacChanQ == ADI_ADRV9025_DEFRAMER_OUT0)) + { + *iqRate_kHz = adrv9025Init->tx.txChannelCfg[2].profile.txInputRate_kHz; + } + else if ((adrv9025Init->dataInterface.deframer[deframerIndex].dacCrossbar.tx4DacChanI == ADI_ADRV9025_DEFRAMER_OUT0) || + (adrv9025Init->dataInterface.deframer[deframerIndex].dacCrossbar.tx4DacChanQ == ADI_ADRV9025_DEFRAMER_OUT0)) + { + *iqRate_kHz = adrv9025Init->tx.txChannelCfg[3].profile.txInputRate_kHz; + } + + return recoveryAction; +} + +int32_t adi_adrv9025Board_LdoSelectOverRide(adi_adrv9025_Init_t* adrv9025Init) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t halRetVal = 0; + + static const int32_t SIZE_BYTES = 1024; + static const int32_t FMCINDEX = 0; + static const uint8_t LDO_BYPASS = 1; + static const uint8_t LDO_NONBYPASS = 0; + + int index = 0; + int indx = 0; + char infoStr[1024] = {0}; + char bomStr[7] = {0}; + char* tmpStrPtr; + /* const char *ceBom = "047405"; */ + /* const char *eeBom = "045639"; */ + const char* bypassStr = "bypass"; + + /* Adrv9010 programming sequence */ + + /* Select all Tokelau devices available for broadcast write */ + /* TODO: Uncomment this call when fpga image support manual CS manipulation */ + //if ((recoveryAction = adi_fpga9010_AxiAdvSpiChipSelectAll(adrv9010Ce01->fpga9010Device, ADI_TRUE)) != 0) + //{ + //return recoveryAction; + //} + + /* Begin ADS8 LDO Select Feature */ + /* This code only supports the ADI Evaluation card */ + /* protecting against LDO Bypass Damage */ + + /* this function writes return string */ + halRetVal = adi_FmcEepromInfoGet(FMCINDEX, + &infoStr[0], + SIZE_BYTES); + if (halRetVal != ADI_HAL_OK) + { + /* Return error to caller */ + return (ADI_COMMON_ACT_ERR_RESET_FULL); + } + + if (strstr(infoStr, + "ERROR") != NULL) + { + adrv9025Init->clocks.ldoSelect = LDO_NONBYPASS; + printf("ERROR: Could not read EEPROM, defaulted to LDO Non Bypass case to stay safe."); + } + else + { + /* extract EEPROM fields */ + tmpStrPtr = strtok(infoStr, ";"); /* Manufacturer */ + tmpStrPtr = strtok(NULL, ";"); /* Product Name */ + tmpStrPtr = strtok(NULL, ";"); /* Serial Number */ + tmpStrPtr = strtok(NULL, ";"); /* Part Number */ + tmpStrPtr = strtok(NULL, ";"); /* PCB ID */ + tmpStrPtr = strtok(NULL, ";"); /* BOM Part Number */ + + if (tmpStrPtr == NULL) + { + /* Stay safe on boards that don't explicitly have bypass in EEPROM */ + adrv9025Init->clocks.ldoSelect = LDO_NONBYPASS; + } + else + { + /* get the CE BOM number */ + indx = 0; + for (index = 8; index < 14; index++) + { + bomStr[indx] = tmpStrPtr[index]; + indx++; + } + + /* Must match bypass string to fall into this case*/ + if (strncmp(bomStr, + bypassStr, + strlen(bypassStr)) == 0) + { + adrv9025Init->clocks.ldoSelect = LDO_BYPASS; + } + else + { + adrv9025Init->clocks.ldoSelect = LDO_NONBYPASS; + } + } + } + + return recoveryAction; +} + +int32_t adi_board_adrv9025_JesdTxBringup(adi_daughterboard_trx_t* trxDaughterboard, + uint32_t link) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adi_adrv9025_InitCals_t serdesCal = {0}; + uint8_t errFlags = 0; + static const uint8_t CAL_ALL_CHANNELS = 0x0F; + adi_fpga9025_Device_t* fpga9025Device = NULL; + adi_adrv9025_Device_t* adrv9025Device = NULL; + adi_ad9528_Device_t* ad9528Device = NULL; + + if (trxDaughterboard == NULL) + { + return (ADI_COMMON_ACT_ERR_RESET_FULL); + } + + fpga9025Device = (adi_fpga9025_Device_t *)trxDaughterboard->fpgaDevice; + adrv9025Device = (adi_adrv9025_Device_t *)trxDaughterboard->trxDevice; + ad9528Device = (adi_ad9528_Device_t *)trxDaughterboard->clockDevice; + + /* Unmask incoming sysref in FPGA framers (leave rx links untouched) */ + recoveryAction = adi_fpga9025_SysRefEnableSet(fpga9025Device, + (uint8_t)link, + 0, + ADI_ENABLE); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + /* Enable/reset FPGA Framer(s) */ + recoveryAction = adi_fpga9025_FramerReset(fpga9025Device, + (uint8_t)link); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + /* Request sysref to start fpga framers sending data */ + recoveryAction = adi_ad9528_SysrefRequest(ad9528Device, + 1); + ADI_ERROR_REPORT(&ad9528Device->common, + ADI_COMMON_ERRSRC_API, + ad9528Device->common.error.errCode, + recoveryAction, + NULL, + ad9528Device->common.error.errormessage); + ADI_ERROR_RETURN(ad9528Device->common.error.newAction); + + /* Mask the sysref for the fpga framers as a precaution for the next sysref (leave rx links untouched) */ + recoveryAction = adi_fpga9025_SysRefEnableSet(fpga9025Device, + (uint8_t)link, + 0, + ADI_DISABLE); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + /* Reset/Enable Adrv9025 Deframer(s) */ + recoveryAction = adi_adrv9025_DfrmLinkStateSet(adrv9025Device, + (uint8_t)link, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_common_hal_Wait_ms(&adrv9025Device->common, + 50); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_DfrmLinkStateSet(adrv9025Device, + (uint8_t)link, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Notify ARM to run SERDES Calbriation if necessary */ + serdesCal.calMask = ADI_ADRV9025_SERDES_INIT; + serdesCal.channelMask = CAL_ALL_CHANNELS; + serdesCal.warmBoot = 0; + recoveryAction = adi_adrv9025_InitCalsRun(adrv9025Device, + &serdesCal); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Wait up to 60 seconds for ARM */ + recoveryAction = adi_adrv9025_InitCalsWait(adrv9025Device, + 60000, + &errFlags); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Adrv9025 Unmask Sysref in Deframer(s) */ + recoveryAction = adi_adrv9025_DeframerSysrefCtrlSet(adrv9025Device, + (adi_adrv9025_DeframerSel_e)link, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Request sysref for adrv9025 deframers only */ + recoveryAction = adi_ad9528_SysrefRequest(ad9528Device, + 1); + ADI_ERROR_REPORT(&ad9528Device->common, + ADI_COMMON_ERRSRC_API, + ad9528Device->common.error.errCode, + recoveryAction, + NULL, + ad9528Device->common.error.errormessage); + ADI_ERROR_RETURN(ad9528Device->common.error.newAction); + + /* Adrv9025 mask Sysref in Deframer(s) as a precaution */ + recoveryAction = adi_adrv9025_DeframerSysrefCtrlSet(adrv9025Device, + (adi_adrv9025_DeframerSel_e)link, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_board_adrv9025_JesdRxBringup(adi_daughterboard_trx_t* trxDaughterboard, + uint32_t link) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t sysrefEnabledForFramer2 = ADI_FALSE; + adi_fpga9025_Device_t* fpga9025Device = NULL; + adi_adrv9025_Device_t* adrv9025Device = NULL; + adi_ad9528_Device_t* ad9528Device = NULL; + + if (trxDaughterboard == NULL) + { + return (ADI_COMMON_ACT_ERR_RESET_FULL); + } + + fpga9025Device = (adi_fpga9025_Device_t *)trxDaughterboard->fpgaDevice; + adrv9025Device = (adi_adrv9025_Device_t *)trxDaughterboard->trxDevice; + ad9528Device = (adi_ad9528_Device_t *)trxDaughterboard->clockDevice; + + if (adrv9025Device->devStateInfo.linkSharingEnabled == 1) + { + /* Start the AUX Sys Ref in JTX Link 1*/ + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + ADI_ADRV9025_FRAMER_1, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Adrv9025 Unmask incoming Sysref in Framer(s) */ + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_FRAMER_1, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_ad9528_SysrefRequest(ad9528Device, + 1); + ADI_ERROR_REPORT(&ad9528Device->common, + ADI_COMMON_ERRSRC_API, + ad9528Device->common.error.errCode, + recoveryAction, + NULL, + ad9528Device->common.error.errormessage); + ADI_ERROR_RETURN(ad9528Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + ADI_ADRV9025_FRAMER_1, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_FRAMER_1, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + ADI_ADRV9025_FRAMER_0, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_FRAMER_0, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Check that if the profile uses Framer 2 */ + if ((link & (uint32_t)ADI_ADRV9025_FRAMER_2) == (uint32_t)ADI_ADRV9025_FRAMER_2) + { + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + ADI_ADRV9025_FRAMER_2, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_FRAMER_2, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + sysrefEnabledForFramer2 = ADI_TRUE; + } + } + else + { + /* Enable/reset Adrv9025 Framer(s) */ + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + link, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_common_hal_Wait_ms(&adrv9025Device->common, + 50); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + link, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Adrv9025 Unmask incoming Sysref in Framer(s) */ + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + (uint8_t)link, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + } + + /* Disable DFE LPM in PHY before after sys ref */ + adi_fpga9025_ChannelDfeLpmOverrideSet(fpga9025Device, + 0xFF, + 0); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + /* Wait 100ms for clock recovery on FPGA to lock */ + recoveryAction = adi_common_hal_Wait_ms(&adrv9025Device->common, + 100); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Enable/reset FPGA Deframer(s) */ + recoveryAction = adi_fpga9025_DeframerReset(fpga9025Device, + (uint8_t)link); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + /* Disable DFE LPM in PHY before after sys ref */ + recoveryAction = adi_fpga9025_ChannelDfeLpmOverrideSet(fpga9025Device, + 0xFF, + 0); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + /* Unmask incoming sysref in FPGA deframers (leave tx links untouched) */ + recoveryAction = adi_fpga9025_SysRefEnableSet(fpga9025Device, + 0, + (uint8_t)link, + ADI_ENABLE); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + /* Request sysref to bring up Rx links */ + recoveryAction = adi_ad9528_SysrefRequest(ad9528Device, + 1); + ADI_ERROR_REPORT(&ad9528Device->common, + ADI_COMMON_ERRSRC_API, + ad9528Device->common.error.errCode, + recoveryAction, + NULL, + ad9528Device->common.error.errormessage); + ADI_ERROR_RETURN(ad9528Device->common.error.newAction); + + if (adrv9025Device->devStateInfo.linkSharingEnabled == 0) + { + /* Adrv9025 mask sysref in Framers. Precaution against future sysref signals */ + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + (uint8_t)link, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + } + + if (sysrefEnabledForFramer2 == ADI_TRUE) + { + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_FRAMER_2, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + } + + /* Mask sysref in fpga deframers. Precaution against future sysref signals */ + recoveryAction = adi_fpga9025_SysRefEnableSet(fpga9025Device, + 0, + (uint8_t)link, + ADI_DISABLE); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_board_adrv9025_JesdBringup(adi_daughterboard_trx_t* trxDaughterboard, + uint32_t txLinkSel, + uint32_t rxLinkSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t i = 0; + uint8_t adrv9025LinkStatus = 0; + uint8_t fpga9025LinkStatus = 0; + uint8_t deframerLinkCondition = 0; + adi_fpga9025_Device_t* fpga9025Device = NULL; + adi_adrv9025_Device_t* adrv9025Device = NULL; + + if (trxDaughterboard == NULL) + { + return (ADI_COMMON_ACT_ERR_RESET_FULL); + } + + fpga9025Device = (adi_fpga9025_Device_t *)trxDaughterboard->fpgaDevice; + adrv9025Device = (adi_adrv9025_Device_t *)trxDaughterboard->trxDevice; + + /* Mask all sysrefs in Adrv9025 */ + recoveryAction = adi_adrv9025_DeframerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_DEFRAMER_0, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_ALL_FRAMERS, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Mask all sysrefs in fpga */ + recoveryAction = adi_fpga9025_SysRefEnableSet(fpga9025Device, + ADI_FPGA9025_FRAMER_ALL, + ADI_FPGA9025_DEFRAMER_ALL, + ADI_DISABLE); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + /* Disable all the FPGA framer & deframers */ + recoveryAction = adi_fpga9025_FramerDisable(fpga9025Device, + ADI_FPGA9025_FRAMER_ALL); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + recoveryAction = adi_fpga9025_DeframerDisable(fpga9025Device, + ADI_FPGA9025_DEFRAMER_ALL); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + /* Disable all the ADRV9025 framer & deframers */ + recoveryAction = adi_adrv9025_DfrmLinkStateSet(adrv9025Device, + (uint8_t)ADI_ADRV9025_DEFRAMER_0, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + (uint8_t)ADI_ADRV9025_ALL_FRAMERS, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Override DFE LPM in PHY before sending sys ref */ + recoveryAction = adi_fpga9025_ChannelDfeLpmOverrideSet(fpga9025Device, + 0xFF, + 1); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + if (rxLinkSel != 0) + { + /* Bring up the Rx links */ + recoveryAction = adi_board_adrv9025_JesdRxBringup(trxDaughterboard, + rxLinkSel); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + if (fpga9025Device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + recoveryAction = adi_fpga9025_Jesd204CDeframerCmdDataSet(fpga9025Device, + rxLinkSel, + ADI_ENABLE, + ADI_ENABLE); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + } + } + + if (txLinkSel != 0) + { + /* Bring up the Tx links */ + recoveryAction = adi_board_adrv9025_JesdTxBringup(trxDaughterboard, + txLinkSel); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + if (fpga9025Device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + recoveryAction = adi_fpga9025_Jesd204CFramerCmdDataSet(fpga9025Device, + txLinkSel, + ADI_ENABLE, + ADI_ENABLE); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + } + } + + /* Adrv9025 Deframer Status get*/ + for (i = 0; i < 2; i++) + { + if ((txLinkSel & (1 << i)) > 0) + { + deframerLinkCondition = 0; + recoveryAction = adi_adrv9025_DfrmLinkConditionGet(adrv9025Device, + (adi_adrv9025_DeframerSel_e)((uint8_t)(1 << i)), + &deframerLinkCondition); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + if (deframerLinkCondition & 0x01) + { + adrv9025LinkStatus |= (1 << i); + } + } + } + + /* Fpga Reading User Data Ready bit*/ + recoveryAction = adi_fpga9025_DeframerStatusGet(fpga9025Device, + rxLinkSel, + &fpga9025LinkStatus); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + fpga9025Device->common.error.errCode, + recoveryAction, + NULL, + fpga9025Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + if (adrv9025LinkStatus != txLinkSel) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_INTERFACE; + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Not all Tx links have been established."); + + /* Disable all the FPGA deframers. Don't update the error though, this is just cleanup */ + adi_fpga9025_FramerDisable(fpga9025Device, + ADI_FPGA9025_FRAMER_ALL); + } + if (fpga9025LinkStatus != rxLinkSel) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_INTERFACE; + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Not all Rx links have been established."); + + /* Disable all the FPGA deframers. Don't update the error though, this is just cleanup */ + adi_fpga9025_DeframerDisable(fpga9025Device, + ADI_FPGA9025_DEFRAMER_ALL); + } + + /* Kick off SERDES tracking cal if lanes are up */ + if (recoveryAction == ADI_COMMON_ACT_NO_ACTION) + { + recoveryAction = adi_adrv9025_TrackingCalsEnableSet(adrv9025Device, + ADI_ADRV9025_TRACK_DESERIALIZER, + ADI_ADRV9025_TRACKING_CAL_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_board_adrv9025_Jesd204LinkReset(adi_daughterboard_trx_t* trxDaughterboard) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t i = 0; + uint32_t txLinkSel = 0; + uint32_t rxLinkSel = 0; + adi_adrv9025_Init_t* adrv9025Init = NULL; + + if (trxDaughterboard == NULL) + { + return (ADI_COMMON_ACT_ERR_RESET_FULL); + } + + adrv9025Init = (adi_adrv9025_Init_t *)trxDaughterboard->daughterCardInit; + + for (i = 0; i < ADI_ADRV9025_NUM_FRAMERS; i++) + { + if (adrv9025Init->dataInterface.framer[i].serializerLanesEnabled > 0) + { + rxLinkSel |= 1 << i; + } + } + + for (i = 0; i < ADI_ADRV9025_NUM_DEFRAMERS; i++) + { + if (adrv9025Init->dataInterface.deframer[i].deserializerLanesEnabled > 0) + { + txLinkSel |= 1 << i; + } + } + + /* JESD204 link bring up */ + if ((recoveryAction = adi_board_adrv9025_JesdBringup(trxDaughterboard, + txLinkSel, + rxLinkSel)) < 0) + { + return recoveryAction; + } + + return 0; +} + +static int32_t adi_board_adrv9025_Fpga9025Init(adi_daughterboard_trx_t* trxDaughterboard) +{ + adi_fpga9025_Device_t* fpga9025Device = NULL; + adi_adrv9025_Init_t* adrv9025Init = NULL; + adi_fpga9025_Init_t initSet = {{{0}}}; + /* TODO: If above 614.4MHz, divide clock to FPGA in 9528 */ + uint32_t refClk_kHz = 0; + int32_t testReturnVal = ADI_COMMON_ACT_NO_ACTION; + int i = 0; + int j = 0; + + if (trxDaughterboard == NULL) + { + return (ADI_COMMON_ACT_ERR_RESET_FULL); + } + + fpga9025Device = (adi_fpga9025_Device_t *)trxDaughterboard->fpgaDevice; + adrv9025Init = (adi_adrv9025_Init_t *)trxDaughterboard->daughterCardInit; + refClk_kHz = adrv9025Init->clocks.deviceClock_kHz; + + fpga9025Device->memoryPageSize = 0x40000000; + + adi_fpga9025_SetupFpgaCfg_t fpgaCfg = {0}; + fpgaCfg.deviceClk_kHz = refClk_kHz; + fpgaCfg.framerlink0.datamoversUsed = 0; /*not used - remove from structure*/ + + /*TODO, find first valid Rx based on rx channel mask*/ + adi_adrv9025Board_RxLinkSamplingRateFind(fpga9025Device, + adrv9025Init, + ADI_ADRV9025_FRAMER_0, + &fpgaCfg.deframerlink0.iqRate_kHz); + fpgaCfg.deframerlink0.jesd204K = adrv9025Init->dataInterface.framer[0].jesd204K; + fpgaCfg.deframerlink0.jesd204M = adrv9025Init->dataInterface.framer[0].jesd204M; + fpgaCfg.deframerlink0.jesd204Np = adrv9025Init->dataInterface.framer[0].jesd204Np; + fpgaCfg.deframerlink0.jesd204E = adrv9025Init->dataInterface.framer[0].jesd204E; + fpgaCfg.deframerlink0.jesd204S = adrv9025Init->dataInterface.framer[0].jesd204Np == 0 ? 0 : (adrv9025Init->dataInterface.framer[0].jesd204F * LANESENABLEDBINTODEC(adrv9025Init->dataInterface.framer[0].serializerLanesEnabled) * 8) / (adrv9025Init->dataInterface.framer[0].jesd204Np * adrv9025Init->dataInterface.framer[0].jesd204M); + fpgaCfg.deframerlink0.lanesEnabled = adrv9025Init->dataInterface.framer[0].serializerLanesEnabled; + fpgaCfg.deframerlink0.scramble = adrv9025Init->dataInterface.framer[0].scramble; + fpgaCfg.deframerlink0.serializerLaneCrossbar.lane0FramerOutSel = adrv9025Init->dataInterface.framer[0].serializerLaneCrossbar.lane0FramerOutSel; + fpgaCfg.deframerlink0.serializerLaneCrossbar.lane1FramerOutSel = adrv9025Init->dataInterface.framer[0].serializerLaneCrossbar.lane1FramerOutSel; + fpgaCfg.deframerlink0.serializerLaneCrossbar.lane2FramerOutSel = adrv9025Init->dataInterface.framer[0].serializerLaneCrossbar.lane2FramerOutSel; + fpgaCfg.deframerlink0.serializerLaneCrossbar.lane3FramerOutSel = adrv9025Init->dataInterface.framer[0].serializerLaneCrossbar.lane3FramerOutSel; + adi_adrv9025Board_RxLinkSamplingRateFind(fpga9025Device, + adrv9025Init, + ADI_ADRV9025_FRAMER_1, + &fpgaCfg.deframerlink1.iqRate_kHz); + fpgaCfg.deframerlink1.jesd204K = adrv9025Init->dataInterface.framer[1].jesd204K; + fpgaCfg.deframerlink1.jesd204M = adrv9025Init->dataInterface.framer[1].jesd204M; + fpgaCfg.deframerlink1.jesd204Np = adrv9025Init->dataInterface.framer[1].jesd204Np; + fpgaCfg.deframerlink1.jesd204E = adrv9025Init->dataInterface.framer[1].jesd204E; + fpgaCfg.deframerlink1.jesd204S = adrv9025Init->dataInterface.framer[1].jesd204Np == 0 ? 0 : (adrv9025Init->dataInterface.framer[1].jesd204F * LANESENABLEDBINTODEC(adrv9025Init->dataInterface.framer[1].serializerLanesEnabled) * 8) / (adrv9025Init->dataInterface.framer[1].jesd204Np * adrv9025Init->dataInterface.framer[1].jesd204M); + fpgaCfg.deframerlink1.lanesEnabled = adrv9025Init->dataInterface.framer[1].serializerLanesEnabled; + fpgaCfg.deframerlink1.scramble = adrv9025Init->dataInterface.framer[1].scramble; + fpgaCfg.deframerlink1.serializerLaneCrossbar.lane0FramerOutSel = adrv9025Init->dataInterface.framer[1].serializerLaneCrossbar.lane0FramerOutSel; + fpgaCfg.deframerlink1.serializerLaneCrossbar.lane1FramerOutSel = adrv9025Init->dataInterface.framer[1].serializerLaneCrossbar.lane1FramerOutSel; + fpgaCfg.deframerlink1.serializerLaneCrossbar.lane2FramerOutSel = adrv9025Init->dataInterface.framer[1].serializerLaneCrossbar.lane2FramerOutSel; + fpgaCfg.deframerlink1.serializerLaneCrossbar.lane3FramerOutSel = adrv9025Init->dataInterface.framer[1].serializerLaneCrossbar.lane3FramerOutSel; + + adi_adrv9025Board_RxLinkSamplingRateFind(fpga9025Device, + adrv9025Init, + ADI_ADRV9025_FRAMER_2, + &fpgaCfg.deframerlink2.iqRate_kHz); + fpgaCfg.deframerlink2.jesd204K = adrv9025Init->dataInterface.framer[2].jesd204K; + fpgaCfg.deframerlink2.jesd204M = adrv9025Init->dataInterface.framer[2].jesd204M; + fpgaCfg.deframerlink2.jesd204Np = adrv9025Init->dataInterface.framer[2].jesd204Np; + fpgaCfg.deframerlink2.jesd204E = adrv9025Init->dataInterface.framer[2].jesd204E; + fpgaCfg.deframerlink2.jesd204S = adrv9025Init->dataInterface.framer[2].jesd204Np == 0 ? 0 : (adrv9025Init->dataInterface.framer[2].jesd204F * LANESENABLEDBINTODEC(adrv9025Init->dataInterface.framer[2].serializerLanesEnabled) * 8) / (adrv9025Init->dataInterface.framer[2].jesd204Np * adrv9025Init->dataInterface.framer[2].jesd204M); + fpgaCfg.deframerlink2.lanesEnabled = adrv9025Init->dataInterface.framer[2].serializerLanesEnabled; + fpgaCfg.deframerlink2.scramble = adrv9025Init->dataInterface.framer[2].scramble; + fpgaCfg.deframerlink2.serializerLaneCrossbar.lane0FramerOutSel = adrv9025Init->dataInterface.framer[2].serializerLaneCrossbar.lane0FramerOutSel; + fpgaCfg.deframerlink2.serializerLaneCrossbar.lane1FramerOutSel = adrv9025Init->dataInterface.framer[2].serializerLaneCrossbar.lane1FramerOutSel; + fpgaCfg.deframerlink2.serializerLaneCrossbar.lane2FramerOutSel = adrv9025Init->dataInterface.framer[2].serializerLaneCrossbar.lane2FramerOutSel; + fpgaCfg.deframerlink2.serializerLaneCrossbar.lane3FramerOutSel = adrv9025Init->dataInterface.framer[2].serializerLaneCrossbar.lane3FramerOutSel; + + adi_adrv9025Board_TxLinkSamplingRateFind(fpga9025Device, + adrv9025Init, + ADI_ADRV9025_DEFRAMER_0, + &fpgaCfg.framerlink0.iqRate_kHz); + fpgaCfg.framerlink0.jesd204K = adrv9025Init->dataInterface.deframer[0].jesd204K; + fpgaCfg.framerlink0.jesd204M = adrv9025Init->dataInterface.deframer[0].jesd204M; + fpgaCfg.framerlink0.jesd204Np = adrv9025Init->dataInterface.deframer[0].jesd204Np; + fpgaCfg.framerlink0.jesd204E = adrv9025Init->dataInterface.deframer[0].jesd204E; + fpgaCfg.framerlink0.jesd204S = adrv9025Init->dataInterface.deframer[0].jesd204Np == 0 ? 0 : (adrv9025Init->dataInterface.deframer[0].jesd204F * LANESENABLEDBINTODEC(adrv9025Init->dataInterface.deframer[0].deserializerLanesEnabled) * 8) / (adrv9025Init->dataInterface.deframer[0].jesd204Np * adrv9025Init->dataInterface.deframer[0].jesd204M); + fpgaCfg.framerlink0.lanesEnabled = adrv9025Init->dataInterface.deframer[0].deserializerLanesEnabled; + fpgaCfg.framerlink0.scramble = adrv9025Init->dataInterface.deframer[0].scramble; + fpgaCfg.framerlink0.deviceId = adrv9025Init->dataInterface.deframer[0].deviceId; + + adi_adrv9025Board_TxLinkSamplingRateFind(fpga9025Device, + adrv9025Init, + ADI_ADRV9025_DEFRAMER_1, + &fpgaCfg.framerlink1.iqRate_kHz); + fpgaCfg.framerlink1.jesd204K = adrv9025Init->dataInterface.deframer[1].jesd204K; + fpgaCfg.framerlink1.jesd204M = adrv9025Init->dataInterface.deframer[1].jesd204M; + fpgaCfg.framerlink1.jesd204Np = adrv9025Init->dataInterface.deframer[1].jesd204Np; + fpgaCfg.framerlink1.jesd204E = adrv9025Init->dataInterface.deframer[1].jesd204E; + fpgaCfg.framerlink1.jesd204S = adrv9025Init->dataInterface.deframer[1].jesd204Np == 0 ? 0 : (adrv9025Init->dataInterface.deframer[1].jesd204F * LANESENABLEDBINTODEC(adrv9025Init->dataInterface.deframer[1].deserializerLanesEnabled) * 8) / (adrv9025Init->dataInterface.deframer[1].jesd204Np * adrv9025Init->dataInterface.deframer[1].jesd204M); + fpgaCfg.framerlink1.lanesEnabled = adrv9025Init->dataInterface.deframer[1].deserializerLanesEnabled; + fpgaCfg.framerlink1.scramble = adrv9025Init->dataInterface.deframer[1].scramble; + fpgaCfg.framerlink1.deviceId = adrv9025Init->dataInterface.deframer[1].deviceId; + + /* Based on schematic showing inverted signals going into these links */ + initSet.datapath.syncBPolarity = 0x7; + + /* Setup the serializer lane swaps for this board (index maps to DUT lane; value is corresponding FPGA lane) */ + initSet.datapath.pcbSerLaneSwap[0] = 3; + initSet.datapath.pcbSerLaneSwap[1] = 2; + initSet.datapath.pcbSerLaneSwap[2] = 1; + initSet.datapath.pcbSerLaneSwap[3] = 0; + initSet.datapath.pcbSerLaneSwap[4] = 7; + initSet.datapath.pcbSerLaneSwap[5] = 7; + initSet.datapath.pcbSerLaneSwap[6] = 7; + initSet.datapath.pcbSerLaneSwap[7] = 7; + + initSet.datapath.serLanePnInvert[0] = 0; + initSet.datapath.serLanePnInvert[1] = 1; + initSet.datapath.serLanePnInvert[2] = 0; + initSet.datapath.serLanePnInvert[3] = 1; + initSet.datapath.serLanePnInvert[4] = 0; + initSet.datapath.serLanePnInvert[5] = 0; + initSet.datapath.serLanePnInvert[6] = 0; + initSet.datapath.serLanePnInvert[7] = 0; + + /* Setup the deserializer lane swaps for this board */ + initSet.datapath.pcbDesLaneSwap[0] = 1; + initSet.datapath.pcbDesLaneSwap[1] = 0; + initSet.datapath.pcbDesLaneSwap[2] = 2; + initSet.datapath.pcbDesLaneSwap[3] = 3; + initSet.datapath.pcbDesLaneSwap[4] = 7; + initSet.datapath.pcbDesLaneSwap[5] = 7; + initSet.datapath.pcbDesLaneSwap[6] = 7; + initSet.datapath.pcbDesLaneSwap[7] = 7; + + initSet.datapath.desLanePnInvert[0] = 1; + initSet.datapath.desLanePnInvert[1] = 1; + initSet.datapath.desLanePnInvert[2] = 1; + initSet.datapath.desLanePnInvert[3] = 1; + initSet.datapath.desLanePnInvert[4] = 1; + initSet.datapath.desLanePnInvert[5] = 1; + initSet.datapath.desLanePnInvert[6] = 1; + initSet.datapath.desLanePnInvert[7] = 1; + + testReturnVal = adi_fpga9025_InitConfig(fpga9025Device, + &fpgaCfg, + &initSet); + if (testReturnVal != 0) + { + return testReturnVal; + } + + // setup the bank id's for framers based on config + for (i = 0; i < ADI_FPGA9025_NUM_OF_FRAMERS; i++) + { + initSet.datapath.framerCfg[i].bankId = adrv9025Init->dataInterface.deframer[i].bankId; + } + // setup the bank id's for deframers based on config + for (i = 0; i < ADI_FPGA9025_NUM_OF_DEFRAMERS; i++) + { + for (j = 0; j < ADI_FPGA9025_NUM_LANES; j++) + { + initSet.datapath.deframerCfg[i].bankId[j] = adrv9025Init->dataInterface.framer[i].bankId; + } + } + initSet.clocks.qpll.quadSelect = ADI_FPGA9025_QPLL_QUAD0; + + testReturnVal = adi_fpga9025_InitSet(fpga9025Device, + &initSet); + if (testReturnVal != 0) + { + return testReturnVal; + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adi_board_adrv9025_Program_Phase1(adi_daughterboard_trx_t* trxDaughterboard) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adi_fpga9025_AxiAdvSpiFeatConfig_t fpgaAdvSpiCfg = {0}; + adi_fpga9025_Device_t* fpga9025Device = NULL; + adi_adrv9025_Init_t* adrv9025Init = NULL; + adi_adrv9025_Device_t* adrv9025Device = NULL; + adi_adrv9025_PlatformFiles_t* adrv9025PlatformFiles = NULL; + + if (trxDaughterboard == NULL) + { + return (ADI_COMMON_ACT_ERR_RESET_FULL); + } + + fpgaAdvSpiCfg.enable = 1; + fpgaAdvSpiCfg.cpha = 0; + fpgaAdvSpiCfg.cpol = 0; + fpgaAdvSpiCfg.lsbFirst = 0; + fpgaAdvSpiCfg.fourWire = 1; + fpgaAdvSpiCfg.misoSampleSlip = 1; + fpgaAdvSpiCfg.threeWireTriPoint = 16; + fpgaAdvSpiCfg.clockDiv = 1; + + fpga9025Device = (adi_fpga9025_Device_t *)trxDaughterboard->fpgaDevice; + adrv9025Init = (adi_adrv9025_Init_t *)trxDaughterboard->daughterCardInit; + adrv9025Device = (adi_adrv9025_Device_t *)trxDaughterboard->trxDevice; + adrv9025PlatformFiles = (adi_adrv9025_PlatformFiles_t *)trxDaughterboard->platformFilesInit; + + /* AD9528: 25Mhz SPICLK, but with SPIDO clocked half clock cycle later for improved setup.hold */ + recoveryAction = adi_fpga9025_AxiAdvSpiCfgSet(fpga9025Device, + &fpgaAdvSpiCfg, + 0); + if (recoveryAction != 0) + { + return recoveryAction; + } + + /* ADRV9025: 25Mhz SPICLK, but with SPIDO clocked half clock cycle later for improved setup.hold */ + recoveryAction = adi_fpga9025_AxiAdvSpiCfgSet(fpga9025Device, + &fpgaAdvSpiCfg, + 1); + if (recoveryAction != 0) + { + return recoveryAction; + } + + /* Reset FPGA MMCM to prevent lock up issues when switching FPGA refClk values */ + recoveryAction = adi_fpga9025_MmcmResetSet(fpga9025Device, + ADI_FPGA9025_CORE_MMCM); + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error resetting clock wizard"); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + + /* Init Ad9528 */ + if ((recoveryAction = adi_board_adrv9025_Ad9528Init(trxDaughterboard)) != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&trxDaughterboard->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recoveryAction, NULL, "Init Ad9528"); + ADI_ERROR_RETURN(recoveryAction); + } + + + + // CE and EE board use the same adi_board_adrv9025_Fpga9025Init() + if ((recoveryAction = adi_board_adrv9025_Fpga9025Init(trxDaughterboard)) != 0) + { + ADI_ERROR_REPORT(&trxDaughterboard->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recoveryAction, NULL, "Init FPGA"); + ADI_ERROR_RETURN(recoveryAction); + } + + + + /* Reset Hardware */ + recoveryAction = adi_adrv9025_HwReset(adrv9025Device); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Reset Adrv9025 device"); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Custom Step for ADI eval card to read ADRV9025 internal LDO bypass setting from the eval boards EEPROM to make sure the + * silicon is not accidentally damaged. ADI stores this in a custom FMC EEPROM field used for the BOM revision of the PCB */ + if ((recoveryAction = adi_adrv9025Board_LdoSelectOverRide(adrv9025Init)) != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to perform Ldo Select override"); + ADI_ERROR_RETURN(recoveryAction); + } + + /* Pre MCS - Broadcastable */ + if ((recoveryAction = adi_adrv9025_PreMcsInit_v2(adrv9025Device, + adrv9025Init, + adrv9025PlatformFiles->armImageFile, + adrv9025PlatformFiles->streamImageFile, + adrv9025PlatformFiles->rxGainTableFileArr, + adrv9025PlatformFiles->rxGainTableFileArrSize, + adrv9025PlatformFiles->txAttenTableFileArr, + adrv9025PlatformFiles->txAttenTableFileArrSize)) != ADI_COMMON_ACT_NO_ACTION) + { + return recoveryAction; + } + + /* Pre MCS - Non-Broadcastable */ + if ((recoveryAction = adi_adrv9025_PreMcsInit_NonBroadCast(adrv9025Device, + adrv9025Init)) != ADI_COMMON_ACT_NO_ACTION) + { + return recoveryAction; + } + + return 0; +} + +int32_t adi_board_adrv9025_Program_Phase2(adi_daughterboard_trx_t* trxDaughterboard) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t mcsStatus = 0; + uint8_t i = 0; + uint32_t txLinkSel = 0; + uint32_t rxLinkSel = 0; + adi_adrv9025_Device_t* adrv9025Device = NULL; + adi_ad9528_Device_t* ad9528Device = NULL; + adi_adrv9025_PostMcsInit_t* adrv9025PostMcsInit = NULL; + adi_adrv9025_Init_t* adrv9025Init = NULL; + + if (trxDaughterboard == NULL) + { + return (ADI_COMMON_ACT_ERR_RESET_FULL); + } + + adrv9025Device = (adi_adrv9025_Device_t *)trxDaughterboard->trxDevice; + ad9528Device = (adi_ad9528_Device_t *)trxDaughterboard->clockDevice; + adrv9025PostMcsInit = (adi_adrv9025_PostMcsInit_t *)trxDaughterboard->postMcsInit; + adrv9025Init = (adi_adrv9025_Init_t *)trxDaughterboard->daughterCardInit; + + /* MCS start sequence*/ + if ((recoveryAction = adi_adrv9025_MultichipSyncSet(adrv9025Device, + ADI_ENABLE)) < 0) + { + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to perform MCS"); + ADI_ERROR_RETURN(recoveryAction); + } + + /* This loop will send SysRef pulses up to 255 times unless MCS status achieved before. */ + for (i = 0; i < 255; i++) + { + if ((recoveryAction = adi_ad9528_SysrefRequest(ad9528Device, + 1)) != 0) + { + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "SysRef Request Failed"); + ADI_ERROR_RETURN(recoveryAction); + } + else + { + if ((recoveryAction = adi_adrv9025_MultichipSyncStatusGet(adrv9025Device, + &mcsStatus)) != 0) + { + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Get MCS status"); + ADI_ERROR_RETURN(recoveryAction); + } + else + { + if ((mcsStatus & 0x17) == 0x17) + { + break; + } + } + } + } + + if (mcsStatus != 0x17) + { + /*perror("ADRV9025 CLKPLL MCS status not correct\n");*/ + /*TODO : Add error message once there is error reporting added at the board level*/ + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Unable to perform MCS"); + ADI_ERROR_RETURN(ADI_COMMON_ACT_ERR_RESET_FULL); + } + + /* MCS end sequence*/ + if ((recoveryAction = adi_adrv9025_MultichipSyncSet(adrv9025Device, + ADI_DISABLE)) < 0) + { + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to set MCS state"); + ADI_ERROR_RETURN(recoveryAction); + } + + /* Post MCS */ + if ((recoveryAction = adi_adrv9025_PostMcsInit(adrv9025Device, + adrv9025PostMcsInit)) < 0) + { + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Get MCS status"); + ADI_ERROR_RETURN(recoveryAction); + } + + if ((recoveryAction = adi_adrv9025_SerializerReset(adrv9025Device, + adrv9025Init->clocks.serdesPllVcoFreq_kHz)) < 0) + { + return recoveryAction; + } + + for (i = 0; i < ADI_ADRV9025_NUM_FRAMERS; i++) + { + if (adrv9025Init->dataInterface.framer[i].serializerLanesEnabled > 0) + { + rxLinkSel |= 1 << i; + } + } + + for (i = 0; i < ADI_ADRV9025_NUM_DEFRAMERS; i++) + { + if (adrv9025Init->dataInterface.deframer[i].deserializerLanesEnabled > 0) + { + txLinkSel |= 1 << i; + } + } + + /* JESD204 link bring up */ + if ((recoveryAction = adi_board_adrv9025_JesdBringup(trxDaughterboard, + txLinkSel, + rxLinkSel)) < 0) + { + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "JESD204 link bring up fail"); + ADI_ERROR_RETURN(recoveryAction); + } + + /* Initialize Tx Ramp down functionality */ + if ((recoveryAction = adi_adrv9025_TxRampDownInit(adrv9025Device, + adrv9025Init) < 0)) + { + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Initialize Tx Ramp down functionality fail"); + ADI_ERROR_RETURN(recoveryAction); + } + + /* Setup GP Interrupts from init structure */ + if ((recoveryAction = adi_adrv9025_GpIntInit(adrv9025Device, + &adrv9025Init->gpInterrupts) < 0)) + { + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Setup GP Interrupts from init structure fail"); + ADI_ERROR_RETURN(recoveryAction); + } + + return 0; +} + +int32_t adi_adrv9025Board_Dispatch(adi_daughterboard_trx_t* trxDaughterboard, + adrvtrx_board_action_e actionFlags) +{ + #define BOARD_LAYER_ERROR_SIZE_BYTES 1000u /* Match ARGB_SIZE_BYTES size*/ + int32_t recoveryAction = ADI_COMMON_HAL_OK; + adi_common_Device_t* commonDev = NULL; + adi_adrv9025_Device_t* adrv9025Device = NULL; + adi_fpga9010_Device_t* fpga9010Device = NULL; + adi_ad9528_Device_t* ad9528Device = NULL; + uint32_t txLinkSel = 0; + uint32_t rxLinkSel = 0; + char errorStr[BOARD_LAYER_ERROR_SIZE_BYTES] = { 0 }; + + if ((trxDaughterboard == NULL) || (actionFlags == 0)) + { + return ADI_COMMON_HAL_GEN_SW; + } + + ad9528Device = (adi_ad9528_Device_t *)trxDaughterboard->clockDevice; + adrv9025Device = (adi_adrv9025_Device_t *)trxDaughterboard->trxDevice; + fpga9010Device = (adi_fpga9010_Device_t *)trxDaughterboard->fpgaDevice; + + /* Device allocation */ + if (actionFlags == TRX_BOARD_ACTION_DEVICE_ALLOC) + { + /* Only allocate if it is not already there */ + if ((trxDaughterboard->boardAttribute & TRX_DAUGHTERBOARD_ATTRIBUTE_PREALLOCATE_TRX_DEVICE) > 0) + { + if (trxDaughterboard->trxDevice == 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "Device allocation fail"); + ADI_ERROR_RETURN(recoveryAction); + } + } + else + { + if (trxDaughterboard->trxDevice == 0) + { + trxDaughterboard->trxDevice = (uintptr_t)calloc(1, + sizeof(adi_adrv9025_Device_t)); + } + } + + /* Ensure daughterboard is allocated */ + if (trxDaughterboard->trxDevice == 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "Device allocation fail"); + ADI_ERROR_RETURN(recoveryAction); + } + + /* Assigning Abstract pointers */ + trxDaughterboard->trxAbstractDev.commonAbstractDevice = (adi_common_Device_t *)trxDaughterboard->trxDevice; + trxDaughterboard->trxAbstractDev.trxAbstractDevice = trxDaughterboard->trxDevice; + + return (ADI_COMMON_HAL_OK); + } + + /* HW Open */ + if (actionFlags == TRX_BOARD_ACTION_DEVICE_HWOPEN) + { + adi_adrv9025_SpiSettings_t spiSettings = { + .msbFirst = 1, + .enSpiStreaming = 0, + .autoIncAddrUp = 1, + .fourWireMode = 1, + .cmosPadDrvStrength = ADI_ADRV9025_CMOSPAD_DRV_STRONG, + }; + + commonDev = trxDaughterboard->trxAbstractDev.commonAbstractDevice; + if ((recoveryAction = adi_adrv9025_HwOpen((adi_adrv9025_Device_t *)trxDaughterboard->trxDevice, + &spiSettings)) != (int32_t)ADI_COMMON_HAL_OK) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "Device open fail"); + ADI_ERROR_RETURN(recoveryAction); + } + commonDev->error.logEnable = ADI_ENABLE; + + /* Clear any previous board Errors */ + if (commonDev != NULL) + { + if ((recoveryAction = adi_common_ErrorClear(commonDev)) != ADI_COMMON_ACT_NO_ACTION) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "Error Clear fail"); + ADI_ERROR_RETURN(recoveryAction); + } + } + + return (ADI_COMMON_HAL_OK); + } + + /* HW Close */ + if (actionFlags == TRX_BOARD_ACTION_DEVICE_HWCLOSE) + { + commonDev = trxDaughterboard->trxAbstractDev.commonAbstractDevice; + if ((recoveryAction = adi_adrv9025_HwClose((adi_adrv9025_Device_t *)trxDaughterboard->trxDevice)) != (int32_t)ADI_COMMON_HAL_OK) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "HW close fail"); + ADI_ERROR_RETURN(recoveryAction); + } + adi_hal_DevHalCfgFree(commonDev->devHalInfo); + + return (ADI_COMMON_HAL_OK); + } + + /*Clock Config */ + if (actionFlags == TRX_BOARD_ACTION_CLOCK_CONFIG) + { + uint32_t deviceClock_kHz = trxDaughterboard->parameterBucket[0]; + uint32_t vcxoFreq_kHz = trxDaughterboard->parameterBucket[1]; + uint32_t refAFreq_kHz = trxDaughterboard->parameterBucket[2]; + uint32_t fpgaClock_kHz = trxDaughterboard->parameterBucket[3]; + + if ((recoveryAction = adi_board_adrv9025_Ad9528Configure(trxDaughterboard, + deviceClock_kHz, + vcxoFreq_kHz, + refAFreq_kHz, + fpgaClock_kHz)) != ADI_COMMON_ACT_NO_ACTION) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "Clock config fail"); + ADI_ERROR_RETURN(recoveryAction); + } + + return (ADI_COMMON_HAL_OK); + } + + /* JESD Bringup */ + if (actionFlags == TRX_BOARD_ACTION_DEVICE_JESD_BRINGUP) + { + txLinkSel = trxDaughterboard->parameterBucket[0]; + rxLinkSel = trxDaughterboard->parameterBucket[1]; + + if (trxDaughterboard->motherboardId == ADI_ADS9_PLATFORM) + { + /* JESD204 link bring up */ + if ((recoveryAction = adi_board_adrv9025_JesdBringup(trxDaughterboard, + txLinkSel, + rxLinkSel)) < 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "JESD bring up fail"); + ADI_ERROR_RETURN(recoveryAction); + } + } + else if (trxDaughterboard->motherboardId == ADI_ADS8_PLATFORM) + { + /* JESD204 link bring up */ + if ((recoveryAction = adi_board_adrv9025ADS8_JesdBringup(adrv9025Device, + fpga9010Device, + ad9528Device, + txLinkSel, + rxLinkSel)) < 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "JESD bring up fail"); + ADI_ERROR_RETURN(recoveryAction); + } + } + + return (ADI_COMMON_HAL_OK); + } + + /* JESD204 tx link bring up */ + if (actionFlags == TRX_BOARD_ACTION_DEVICE_JESD_TX_BRINGUP) + { + txLinkSel = trxDaughterboard->parameterBucket[0]; + + if (trxDaughterboard->motherboardId == ADI_ADS9_PLATFORM) + { + /* JESD204 rx link bring up */ + if ((recoveryAction = adi_board_adrv9025_JesdTxBringup(trxDaughterboard, + txLinkSel)) < 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "JESD Tx bring up fail"); + ADI_ERROR_RETURN(recoveryAction); + } + } + else if (trxDaughterboard->motherboardId == ADI_ADS8_PLATFORM) + { + /* JESD204 rx link bring up */ + if ((recoveryAction = adi_board_adrv9025ADS8_JesdTxBringup(adrv9025Device, + fpga9010Device, + ad9528Device, + txLinkSel)) < 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "JESD Tx bring up fail"); + ADI_ERROR_RETURN(recoveryAction); + } + } + + return (ADI_COMMON_HAL_OK); + } + + /* JESD204 rx link bring up */ + if (actionFlags == TRX_BOARD_ACTION_DEVICE_JESD_RX_BRINGUP) + { + rxLinkSel = trxDaughterboard->parameterBucket[0]; + + if (trxDaughterboard->motherboardId == ADI_ADS9_PLATFORM) + { + /* JESD204 rx link bring up */ + if ((recoveryAction = adi_board_adrv9025_JesdRxBringup(trxDaughterboard, + rxLinkSel)) < 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "JESD Rx bring up fail"); + ADI_ERROR_RETURN(recoveryAction); + } + } + else if (trxDaughterboard->motherboardId == ADI_ADS8_PLATFORM) + { + /* JESD204 rx link bring up */ + if ((recoveryAction = adi_board_adrv9025ADS8_JesdRxBringup(adrv9025Device, + fpga9010Device, + ad9528Device, + rxLinkSel)) < 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "JESD Rx bring up fail"); + ADI_ERROR_RETURN(recoveryAction); + } + } + + return (ADI_COMMON_HAL_OK); + } + + if (actionFlags == TRX_BOARD_ACTION_DEVICE_AD9528_INIT) + { + if ((recoveryAction = adi_board_adrv9025_Ad9528Init(trxDaughterboard)) < 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", __func__, __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "Ad9528Init has failed"); + ADI_ERROR_RETURN(recoveryAction); + } + + return (ADI_COMMON_HAL_OK); + } + + if (actionFlags == TRX_BOARD_ACTION__FPGA__INIT) + { + if ((recoveryAction = adi_board_adrv9025_Fpga9025Init(trxDaughterboard)) < 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", __func__, __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "Fpga9025Init has failed"); + ADI_ERROR_RETURN(recoveryAction); + } + + return (ADI_COMMON_HAL_OK); + } + + /* Phase 1 */ + if (actionFlags == TRX_BOARD_ACTION_PHASE_1) + { + adi_adrv9025_Init_t* adrv9025Init = (adi_adrv9025_Init_t *)trxDaughterboard->daughterCardInit; + adi_adrv9025_PlatformFiles_t* adrv9025PlatformFiles = (adi_adrv9025_PlatformFiles_t *)trxDaughterboard->platformFilesInit; + adi_ad9528_Init_t* ad9528Init = (adi_ad9528_Init_t *)trxDaughterboard->clockInit; + trxDaughterboard->savedInfo.enable204cState = adrv9025Init->dataInterface.deframer[0].enableJesd204C; + + /* Initialize FGPGA */ + recoveryAction = trxDaughterboard->FpgaDispatch(trxDaughterboard, + TRX_BOARD_ACTION_FPGA_INIT); + if (recoveryAction != (int32_t)ADI_COMMON_HAL_OK) + { + printf("FPGA 9025 initialization failed.\n"); + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "FPGA Init fail"); + ADI_ERROR_RETURN(recoveryAction); + } + + if (trxDaughterboard->motherboardId == ADI_ADS9_PLATFORM) + { + if ((recoveryAction = adi_board_adrv9025_Program_Phase1(trxDaughterboard)) != ADI_COMMON_ACT_NO_ACTION) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + + if (trxDaughterboard->common.error.errCode != ADI_COMMON_ACT_NO_ACTION) + { + sprintf(errorStr, "ERROR-Phase1 fail: DaughterBoard Error - %d, %s\n", trxDaughterboard->common.error.errCode, trxDaughterboard->common.error.errormessage); + } + else + { + sprintf(errorStr, "ERROR-Phase1 fail: No DaughterBoard Error\n"); + } + + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + errorStr); + ADI_ERROR_RETURN(recoveryAction); + } + } + else if (trxDaughterboard->motherboardId == ADI_ADS8_PLATFORM) + { + if ((trxDaughterboard->daughterCardId >= ADI_BOARD_9025_MIN) && (trxDaughterboard->daughterCardId <= ADI_BOARD_9025_MAX)) + { + adi_board_adrv9025Ads8_t boardADS8 = + { + .adrv9025Device = adrv9025Device, + .fpgaDevice = fpga9010Device, + .ad9528Device = (adi_ad9528_Device_t *)trxDaughterboard->clockDevice + }; + if ((recoveryAction = adi_board_adrv9025ADS8_Program_Phase1(&boardADS8, + adrv9025Init, + ad9528Init, + adrv9025PlatformFiles)) != ADI_COMMON_ACT_NO_ACTION) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + + if (trxDaughterboard->common.error.errCode != ADI_COMMON_ACT_NO_ACTION) + { + sprintf(errorStr, "ERROR-Phase1 fail: DaughterBoard Error - %d, %s\n", trxDaughterboard->common.error.errCode, trxDaughterboard->common.error.errormessage); + } + else + { + sprintf(errorStr, "ERROR-Phase1 fail: No DaughterBoard Error\n"); + } + + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + errorStr); + ADI_ERROR_RETURN(recoveryAction); + } + } + } + else + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "Phase 1 fail"); + ADI_ERROR_RETURN(recoveryAction); + } + + return (ADI_COMMON_HAL_OK); + } + + /* Phase 2 */ + if (actionFlags == TRX_BOARD_ACTION_PHASE_2) + { + adi_adrv9025_Init_t* adrv9025Init = (adi_adrv9025_Init_t *)trxDaughterboard->daughterCardInit; + adi_adrv9025_PostMcsInit_t* adrv9025PostMcsInit = (adi_adrv9025_PostMcsInit_t *)trxDaughterboard->postMcsInit; + adi_ad9528_Init_t* ad9528Init = (adi_ad9528_Init_t *)trxDaughterboard->clockInit; + + /* Proceed to the next board specific phase */ + if (trxDaughterboard->motherboardId == ADI_ADS9_PLATFORM) + { + if ((recoveryAction = adi_board_adrv9025_Program_Phase2(trxDaughterboard)) != ADI_COMMON_ACT_NO_ACTION) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + + if (trxDaughterboard->common.error.errCode != ADI_COMMON_ACT_NO_ACTION) + { + sprintf(errorStr, "ERROR-Phase2 fail: DaughterBoard Error - %d, %s\n", trxDaughterboard->common.error.errCode, trxDaughterboard->common.error.errormessage); + } + else + { + sprintf(errorStr, "ERROR-Phase2 fail: No DaughterBoard Error\n"); + } + + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + errorStr); + ADI_ERROR_RETURN(recoveryAction); + } + } + else if (trxDaughterboard->motherboardId == ADI_ADS8_PLATFORM) + { + fpga9010Device = (adi_fpga9010_Device_t *)trxDaughterboard->fpgaDevice; + if ((trxDaughterboard->daughterCardId == ADI_BOARD_9025CE01) || (trxDaughterboard->daughterCardId == ADI_BOARD_9025EE01)) + { + adi_board_adrv9025Ads8_t boardADS8 = + { + .adrv9025Device = adrv9025Device, + .fpgaDevice = fpga9010Device, + .ad9528Device = (adi_ad9528_Device_t *)trxDaughterboard->clockDevice + }; + if ((recoveryAction = adi_board_adrv9025ADS8_Program_Phase2(&boardADS8, + adrv9025Init, + adrv9025PostMcsInit, + ad9528Init)) != ADI_COMMON_ACT_NO_ACTION) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + + if (trxDaughterboard->common.error.errCode != ADI_COMMON_ACT_NO_ACTION) + { + sprintf(errorStr, "ERROR-Phase2 fail: DaughterBoard Error - %d, %s\n", trxDaughterboard->common.error.errCode, trxDaughterboard->common.error.errormessage); + } + else + { + sprintf(errorStr, "ERROR-Phase2 fail: No DaughterBoard Error\n"); + } + + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + errorStr); + ADI_ERROR_RETURN(recoveryAction); + } + } + } + else + { + return ADI_COMMON_HAL_GEN_SW; + } + } + + /* JESD Data Interface Reset */ + if (actionFlags == TRX_BOARD_ACTION_DATA_INTF_RESET) + { + adi_adrv9025_Init_t* adrv9025Init = (adi_adrv9025_Init_t *)trxDaughterboard->daughterCardInit; + + if (trxDaughterboard->motherboardId == ADI_ADS9_PLATFORM) + { + if ((trxDaughterboard->daughterCardId == ADI_BOARD_9025CE01) || (trxDaughterboard->daughterCardId == ADI_BOARD_9025EE01)) + { + if ((recoveryAction = adi_board_adrv9025_Jesd204LinkReset(trxDaughterboard)) != ADI_COMMON_ACT_NO_ACTION) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "JESD Data Interface Reset"); + ADI_ERROR_RETURN(recoveryAction); + } + } + } + else if (trxDaughterboard->motherboardId == ADI_ADS8_PLATFORM) + { + adi_board_adrv9025Ads8_t board9025 = + { + .adrv9025Device = (adi_adrv9025_Device_t *)trxDaughterboard->trxDevice, + .fpgaDevice = (adi_fpga9010_Device_t *)trxDaughterboard->fpgaDevice, + .ad9528Device = (adi_ad9528_Device_t *)trxDaughterboard->clockDevice + }; + + if ((recoveryAction = adi_board_adrv9025ADS8_Jesd204LinkReset(&board9025, + adrv9025Init)) != ADI_COMMON_ACT_NO_ACTION) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + ADI_ERROR_REPORT(&trxDaughterboard->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_HAL_GEN_SW, + recoveryAction, + NULL, + "JESD Data Interface Reset"); + ADI_ERROR_RETURN(recoveryAction); + } + } + else + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + return (ADI_COMMON_HAL_OK); + } + + return (ADI_COMMON_HAL_OK); +} diff --git a/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adrv9025/src/adi_board_adrv9025ADS8.c b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adrv9025/src/adi_board_adrv9025ADS8.c new file mode 100644 index 0000000..ee62f0b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/adrv9025/src/adi_board_adrv9025ADS8.c @@ -0,0 +1,1351 @@ +/** + * \file adi_board_adrv9025ADS8.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_board_adrv9025ADS8.h" +#include "adi_adrv9025_daughter_board.h" +#include "adi_ad9528.h" +#include "adi_ad9528_utilities.h" +#include "adi_fpga9010_utilities.h" +#include "adi_fpga9010_jesd.h" +#include "adi_fpga9010_clk.h" +#include "adi_adrv9025_gpio.h" +#include "adi_adrv9025_utilities.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_data_interface.h" +#include "adi_adrv9025_cals.h" +#include "adi_fpga9010.h" +#include "adi_fpga9010_axi_adv_spi.h" +#include "adi_fmc_eeprom.h" +#include +#include + +static int32_t adi_board_RxLinkSamplingRateFind(adi_fpga9010_Device_t* device, + adi_adrv9025_Init_t* adrv9025Init, + adi_adrv9025_FramerSel_e framerSel, + uint32_t* iqRate_kHz) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adi_adrv9025_AdcSampleXbarSel_e conv = ADI_ADRV9025_ADC_RX1_Q; + uint32_t framerIndex = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_NULL_PTR_RETURN(&device->common, + iqRate_kHz); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + switch (framerSel) + { + case ADI_ADRV9025_FRAMER_0: + framerIndex = 0; + break; + case ADI_ADRV9025_FRAMER_1: + framerIndex = 1; + break; + case ADI_ADRV9025_FRAMER_2: + framerIndex = 2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Only one framer can be selected at a time."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + if (adrv9025Init->dataInterface.framer[framerIndex].jesd204M < 1) + { + *iqRate_kHz = 0; + return recoveryAction; + } + + conv = adrv9025Init->dataInterface.framer[framerIndex].adcCrossbar.conv0; + + switch (conv) + { + case ADI_ADRV9025_ADC_RX1_I: /* fall through */ + case ADI_ADRV9025_ADC_RX1_Q: /* fall through */ + case ADI_ADRV9025_ADC_DUALBAND_RX1_BAND_B_I: /* fall through */ + case ADI_ADRV9025_ADC_DUALBAND_RX1_BAND_B_Q: /* fall through */ + *iqRate_kHz = adrv9025Init->rx.rxChannelCfg[0].profile.rxOutputRate_kHz; + break; + + case ADI_ADRV9025_ADC_RX2_I: /* fall through */ + case ADI_ADRV9025_ADC_RX2_Q: /* fall through */ + case ADI_ADRV9025_ADC_DUALBAND_RX2_BAND_B_I: /* fall through */ + case ADI_ADRV9025_ADC_DUALBAND_RX2_BAND_B_Q: /* fall through */ + *iqRate_kHz = adrv9025Init->rx.rxChannelCfg[1].profile.rxOutputRate_kHz; + break; + + case ADI_ADRV9025_ADC_RX3_I: /* fall through */ + case ADI_ADRV9025_ADC_RX3_Q: /* fall through */ + case ADI_ADRV9025_ADC_DUALBAND_RX3_BAND_B_I: /* fall through */ + case ADI_ADRV9025_ADC_DUALBAND_RX3_BAND_B_Q: /* fall through */ + *iqRate_kHz = adrv9025Init->rx.rxChannelCfg[2].profile.rxOutputRate_kHz; + break; + + case ADI_ADRV9025_ADC_RX4_I: /* fall through */ + case ADI_ADRV9025_ADC_RX4_Q: /* fall through */ + case ADI_ADRV9025_ADC_DUALBAND_RX4_BAND_B_I: /* fall through */ + case ADI_ADRV9025_ADC_DUALBAND_RX4_BAND_B_Q: /* fall through */ + *iqRate_kHz = adrv9025Init->rx.rxChannelCfg[3].profile.rxOutputRate_kHz; + break; + + // NOTE: ORx2/4 profiles never referenced, ORx2IQ enum below refers to digital channel not RF input + // RF ORx1/2 share digital ORX1, and RF ORX3/4 share digital ORX2 + case ADI_ADRV9025_ADC_ORX1_I: /* fall through */ + case ADI_ADRV9025_ADC_ORX1_Q: /* fall through */ + *iqRate_kHz = adrv9025Init->rx.rxChannelCfg[4].profile.rxOutputRate_kHz; + break; + + // NOTE: ORx2/4 profiles never referenced, ORx2IQ enum below refers to digital channel not RF input + // RF ORx1/2 share digital ORX1, and RF ORX3/4 share digital ORX2 + case ADI_ADRV9025_ADC_ORX2_I: /* fall through */ + case ADI_ADRV9025_ADC_ORX2_Q: /* fall through */ + *iqRate_kHz = adrv9025Init->rx.rxChannelCfg[6].profile.rxOutputRate_kHz; + break; + + default: + *iqRate_kHz = 0; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + adcCrossbar.conv0, + "Invalid ADC crossbar used to read iqRate_kHz"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +static int32_t adi_board_TxLinkSamplingRateFind(adi_fpga9010_Device_t* device, + adi_adrv9025_Init_t* adrv9025Init, + adi_adrv9025_DeframerSel_e deframerSel, + uint32_t* iqRate_kHz) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t deframerIndex = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_NULL_PTR_RETURN(&device->common, + iqRate_kHz); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + switch (deframerSel) + { + case ADI_ADRV9025_DEFRAMER_0: + deframerIndex = 0; + break; + case ADI_ADRV9025_DEFRAMER_1: + deframerIndex = 1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSel, + "Only one deframer can be selected at a time."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + if (adrv9025Init->dataInterface.deframer[deframerIndex].jesd204M < 1) + { + *iqRate_kHz = 0; + return recoveryAction; + } + + //Use samplerate of DAC set to use deframer output 0. + if ((adrv9025Init->dataInterface.deframer[deframerIndex].dacCrossbar.tx1DacChanI == ADI_ADRV9025_DEFRAMER_OUT0) || + (adrv9025Init->dataInterface.deframer[deframerIndex].dacCrossbar.tx1DacChanQ == ADI_ADRV9025_DEFRAMER_OUT0)) + { + *iqRate_kHz = adrv9025Init->tx.txChannelCfg[0].profile.txInputRate_kHz; + } + else if ((adrv9025Init->dataInterface.deframer[deframerIndex].dacCrossbar.tx2DacChanI == ADI_ADRV9025_DEFRAMER_OUT0) || + (adrv9025Init->dataInterface.deframer[deframerIndex].dacCrossbar.tx2DacChanQ == ADI_ADRV9025_DEFRAMER_OUT0)) + { + *iqRate_kHz = adrv9025Init->tx.txChannelCfg[1].profile.txInputRate_kHz; + } + else if ((adrv9025Init->dataInterface.deframer[deframerIndex].dacCrossbar.tx3DacChanI == ADI_ADRV9025_DEFRAMER_OUT0) || + (adrv9025Init->dataInterface.deframer[deframerIndex].dacCrossbar.tx3DacChanQ == ADI_ADRV9025_DEFRAMER_OUT0)) + { + *iqRate_kHz = adrv9025Init->tx.txChannelCfg[2].profile.txInputRate_kHz; + } + else if ((adrv9025Init->dataInterface.deframer[deframerIndex].dacCrossbar.tx4DacChanI == ADI_ADRV9025_DEFRAMER_OUT0) || + (adrv9025Init->dataInterface.deframer[deframerIndex].dacCrossbar.tx4DacChanQ == ADI_ADRV9025_DEFRAMER_OUT0)) + { + *iqRate_kHz = adrv9025Init->tx.txChannelCfg[3].profile.txInputRate_kHz; + } + + return recoveryAction; +} + +static int32_t adi_board_adrv9025ADS8_Fpga9010Init(adi_fpga9010_Device_t* fpgaDevice, + adi_adrv9025_Init_t* adrv9025Init) +{ + adi_fpga9010_Init_t initSet = {{{0}}}; + /* TODO: If above 614.4MHz, divide clock to FPGA in 9528 */ + uint32_t refClk_kHz = adrv9025Init->clocks.deviceClock_kHz; + int32_t testReturnVal = ADI_COMMON_ACT_NO_ACTION; + + fpgaDevice->memoryPageSize = 0x10000000; + + adi_fpga9010_SetupFpgaCfg_t fpgaCfg = {0}; + fpgaCfg.deviceClk_kHz = refClk_kHz; + fpgaCfg.framerlink0.datamoversUsed = 0; /*not used - remove from structure*/ + + /*TODO, find first valid Rx based on rx channel mask*/ + adi_board_RxLinkSamplingRateFind(fpgaDevice, + adrv9025Init, + ADI_ADRV9025_FRAMER_0, + &fpgaCfg.deframerlink0.iqRate_kHz); + fpgaCfg.deframerlink0.jesd204K = adrv9025Init->dataInterface.framer[0].jesd204K; + fpgaCfg.deframerlink0.jesd204M = adrv9025Init->dataInterface.framer[0].jesd204M; + fpgaCfg.deframerlink0.jesd204Np = adrv9025Init->dataInterface.framer[0].jesd204Np; + fpgaCfg.deframerlink0.jesd204E = adrv9025Init->dataInterface.framer[0].jesd204E; + fpgaCfg.deframerlink0.jesd204S = 1; + fpgaCfg.deframerlink0.lanesEnabled = adrv9025Init->dataInterface.framer[0].serializerLanesEnabled; + fpgaCfg.deframerlink0.scramble = adrv9025Init->dataInterface.framer[0].scramble; + + adi_board_RxLinkSamplingRateFind(fpgaDevice, + adrv9025Init, + ADI_ADRV9025_FRAMER_1, + &fpgaCfg.deframerlink1.iqRate_kHz); + fpgaCfg.deframerlink1.jesd204K = adrv9025Init->dataInterface.framer[1].jesd204K; + fpgaCfg.deframerlink1.jesd204M = adrv9025Init->dataInterface.framer[1].jesd204M; + fpgaCfg.deframerlink1.jesd204Np = adrv9025Init->dataInterface.framer[1].jesd204Np; + fpgaCfg.deframerlink1.jesd204E = adrv9025Init->dataInterface.framer[1].jesd204E; + fpgaCfg.deframerlink1.jesd204S = 1; + fpgaCfg.deframerlink1.lanesEnabled = adrv9025Init->dataInterface.framer[1].serializerLanesEnabled; + fpgaCfg.deframerlink1.scramble = adrv9025Init->dataInterface.framer[1].scramble; + + adi_board_RxLinkSamplingRateFind(fpgaDevice, + adrv9025Init, + ADI_ADRV9025_FRAMER_2, + &fpgaCfg.deframerlink2.iqRate_kHz); + fpgaCfg.deframerlink2.jesd204K = adrv9025Init->dataInterface.framer[2].jesd204K; + fpgaCfg.deframerlink2.jesd204M = adrv9025Init->dataInterface.framer[2].jesd204M; + fpgaCfg.deframerlink2.jesd204Np = adrv9025Init->dataInterface.framer[2].jesd204Np; + fpgaCfg.deframerlink2.jesd204E = adrv9025Init->dataInterface.framer[2].jesd204E; + fpgaCfg.deframerlink2.jesd204S = 1; + fpgaCfg.deframerlink2.lanesEnabled = adrv9025Init->dataInterface.framer[2].serializerLanesEnabled; + fpgaCfg.deframerlink2.scramble = adrv9025Init->dataInterface.framer[2].scramble; + + adi_board_TxLinkSamplingRateFind(fpgaDevice, + adrv9025Init, + ADI_ADRV9025_DEFRAMER_0, + &fpgaCfg.framerlink0.iqRate_kHz); + fpgaCfg.framerlink0.jesd204K = adrv9025Init->dataInterface.deframer[0].jesd204K; + fpgaCfg.framerlink0.jesd204M = adrv9025Init->dataInterface.deframer[0].jesd204M; + fpgaCfg.framerlink0.jesd204Np = adrv9025Init->dataInterface.deframer[0].jesd204Np; + fpgaCfg.framerlink0.jesd204E = adrv9025Init->dataInterface.deframer[0].jesd204E; + fpgaCfg.framerlink0.jesd204S = 1; + fpgaCfg.framerlink0.lanesEnabled = adrv9025Init->dataInterface.deframer[0].deserializerLanesEnabled; + fpgaCfg.framerlink0.scramble = adrv9025Init->dataInterface.deframer[0].scramble; + fpgaCfg.framerlink0.deviceId = adrv9025Init->dataInterface.deframer[0].deviceId; + + adi_board_TxLinkSamplingRateFind(fpgaDevice, + adrv9025Init, + ADI_ADRV9025_DEFRAMER_1, + &fpgaCfg.framerlink1.iqRate_kHz); + fpgaCfg.framerlink1.jesd204K = adrv9025Init->dataInterface.deframer[1].jesd204K; + fpgaCfg.framerlink1.jesd204M = adrv9025Init->dataInterface.deframer[1].jesd204M; + fpgaCfg.framerlink1.jesd204Np = adrv9025Init->dataInterface.deframer[1].jesd204Np; + fpgaCfg.framerlink1.jesd204E = adrv9025Init->dataInterface.deframer[1].jesd204E; + fpgaCfg.framerlink1.jesd204S = 1; + fpgaCfg.framerlink1.lanesEnabled = adrv9025Init->dataInterface.deframer[1].deserializerLanesEnabled; + fpgaCfg.framerlink1.scramble = adrv9025Init->dataInterface.deframer[1].scramble; + fpgaCfg.framerlink1.deviceId = adrv9025Init->dataInterface.deframer[1].deviceId; + + /* Based on schematic showing inverted signals going into these links */ + initSet.datapath.syncBPolarity = 0x7; + + /* Setup the serializer lane swaps for this board */ + initSet.datapath.pcbSerLaneSwap[0] = 3; + initSet.datapath.pcbSerLaneSwap[1] = 2; + initSet.datapath.pcbSerLaneSwap[2] = 1; + initSet.datapath.pcbSerLaneSwap[3] = 0; + initSet.datapath.pcbSerLaneSwap[4] = 7; + initSet.datapath.pcbSerLaneSwap[5] = 7; + initSet.datapath.pcbSerLaneSwap[6] = 7; + initSet.datapath.pcbSerLaneSwap[7] = 7; + + /* Setup the deserializer lane swaps for this board */ + initSet.datapath.pcbDesLaneSwap[0] = 1; + initSet.datapath.pcbDesLaneSwap[1] = 0; + initSet.datapath.pcbDesLaneSwap[2] = 2; + initSet.datapath.pcbDesLaneSwap[3] = 3; + initSet.datapath.pcbDesLaneSwap[4] = 7; + initSet.datapath.pcbDesLaneSwap[5] = 7; + initSet.datapath.pcbDesLaneSwap[6] = 7; + initSet.datapath.pcbDesLaneSwap[7] = 7; + + testReturnVal = adi_fpga9010_InitConfig(fpgaDevice, + &fpgaCfg, + &initSet); + if (testReturnVal != 0) + { + return testReturnVal; + } + + /* Setup ADRV9025 + ADS8 specific settings */ + initSet.clocks.qpll.refClkSelect[0] = ADI_FPGA9010_QPLL_GTREFCLK0; + initSet.clocks.qpll.quadSelect = ADI_FPGA9010_QPLL_QUAD0; + initSet.datapath.serializerCfg[0].polarity = 0; + initSet.datapath.serializerCfg[1].polarity = 0; + initSet.datapath.serializerCfg[2].polarity = 0; + initSet.datapath.serializerCfg[3].polarity = 0; + initSet.datapath.deserializerCfg[0].polarity = 1; + initSet.datapath.deserializerCfg[1].polarity = 1; + initSet.datapath.deserializerCfg[2].polarity = 1; + initSet.datapath.deserializerCfg[3].polarity = 1; + + testReturnVal = adi_fpga9010_InitSet(fpgaDevice, + &initSet); + if (testReturnVal != 0) + { + return testReturnVal; + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +static int32_t adi_board_adrv9025ADS8_Ad9528Init(adi_ad9528_Device_t* ad9528Device, + adi_fpga9010_Device_t* fpga9010Device, + adi_ad9528_Init_t* ad9528Init, + adi_adrv9025_Init_t* adrv9025Init) +{ + UNUSED_PARA(fpga9010Device); + UNUSED_PARA(adrv9025Init); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + if ((recoveryAction = adi_ad9528_HwReset(ad9528Device)) < 0) + { + return recoveryAction; + } + + + if ((recoveryAction = adi_ad9528_Initialize(ad9528Device, + ad9528Init)) < 0) + { + return recoveryAction; + } + + + return recoveryAction; +} + +int32_t adi_board_adrv9025ADS8_JesdTxBringup(adi_adrv9025_Device_t* adrv9025Device, + adi_fpga9010_Device_t* fpga9010Device, + adi_ad9528_Device_t* ad9528Device, + uint32_t link) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adi_adrv9025_InitCals_t serdesCal = {0}; + uint8_t errFlags = 0; + static const uint8_t CAL_ALL_CHANNELS = 0x0F; + + /* Unmask incoming sysref in FPGA framers (leave rx links untouched) */ + recoveryAction = adi_fpga9010_SysRefEnableSet(fpga9010Device, + (uint8_t)link, + 0, + ADI_ENABLE); + ADI_ERROR_REPORT(&fpga9010Device->common, + ADI_COMMON_ERRSRC_API, + fpga9010Device->common.error.errCode, + recoveryAction, + NULL, + fpga9010Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9010Device->common.error.newAction); + + /* Enable/reset FPGA Framer(s) */ + recoveryAction = adi_fpga9010_FramerReset(fpga9010Device, + (uint8_t)link); + ADI_ERROR_REPORT(&fpga9010Device->common, + ADI_COMMON_ERRSRC_API, + fpga9010Device->common.error.errCode, + recoveryAction, + NULL, + fpga9010Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9010Device->common.error.newAction); + + /* Request sysref to start fpga framers sending data */ + recoveryAction = adi_ad9528_SysrefRequest(ad9528Device, + 1); + ADI_ERROR_REPORT(&ad9528Device->common, + ADI_COMMON_ERRSRC_API, + ad9528Device->common.error.errCode, + recoveryAction, + NULL, + ad9528Device->common.error.errormessage); + ADI_ERROR_RETURN(ad9528Device->common.error.newAction); + + /* Mask the sysref for the fpga framers as a precaution for the next sysref (leave rx links untouched) */ + recoveryAction = adi_fpga9010_SysRefEnableSet(fpga9010Device, + (uint8_t)link, + 0, + ADI_DISABLE); + ADI_ERROR_REPORT(&fpga9010Device->common, + ADI_COMMON_ERRSRC_API, + fpga9010Device->common.error.errCode, + recoveryAction, + NULL, + fpga9010Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9010Device->common.error.newAction); + + /* Reset/Enable Adrv9025 Deframer(s) */ + recoveryAction = adi_adrv9025_DfrmLinkStateSet(adrv9025Device, + (uint8_t)link, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + adi_common_hal_Wait_ms(&adrv9025Device->common, + 50); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_DfrmLinkStateSet(adrv9025Device, + (uint8_t)link, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Notify ARM to run SERDES Calbriation if necessary */ + serdesCal.calMask = ADI_ADRV9025_SERDES_INIT; + serdesCal.channelMask = CAL_ALL_CHANNELS; + serdesCal.warmBoot = 0; + recoveryAction = adi_adrv9025_InitCalsRun(adrv9025Device, + &serdesCal); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Wait up to 6000 milliseconds for ARM */ + recoveryAction = adi_adrv9025_InitCalsWait(adrv9025Device, + 6000, + &errFlags); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Adrv9025 Unmask Sysref in Deframer(s) */ + recoveryAction = adi_adrv9025_DeframerSysrefCtrlSet(adrv9025Device, + (adi_adrv9025_DeframerSel_e)link, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Request sysref for adrv9025 deframers only */ + recoveryAction = adi_ad9528_SysrefRequest(ad9528Device, + 1); + ADI_ERROR_REPORT(&ad9528Device->common, + ADI_COMMON_ERRSRC_API, + ad9528Device->common.error.errCode, + recoveryAction, + NULL, + ad9528Device->common.error.errormessage); + ADI_ERROR_RETURN(ad9528Device->common.error.newAction); + + /* Adrv9025 mask Sysref in Deframer(s) as a precaution */ + recoveryAction = adi_adrv9025_DeframerSysrefCtrlSet(adrv9025Device, + (adi_adrv9025_DeframerSel_e)link, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_board_adrv9025ADS8_JesdRxBringup(adi_adrv9025_Device_t* adrv9025Device, + adi_fpga9010_Device_t* fpga9010Device, + adi_ad9528_Device_t* ad9528Device, + uint32_t link) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t sysrefEnabledForFramer2 = ADI_FALSE; + + if (adrv9025Device->devStateInfo.linkSharingEnabled == 1) + { + /* Start the AUX Sys Ref in JTX Link 1*/ + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + ADI_ADRV9025_FRAMER_1, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Adrv9010 Unmask incoming Sysref in Framer(s) */ + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_FRAMER_1, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_ad9528_SysrefRequest(ad9528Device, + 1); + ADI_ERROR_REPORT(&ad9528Device->common, + ADI_COMMON_ERRSRC_API, + ad9528Device->common.error.errCode, + recoveryAction, + NULL, + ad9528Device->common.error.errormessage); + ADI_ERROR_RETURN(ad9528Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + ADI_ADRV9025_FRAMER_1, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_FRAMER_1, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + ADI_ADRV9025_FRAMER_0, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_FRAMER_0, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Check that if the profile uses Framer 2 */ + if ((link & (uint32_t)ADI_ADRV9025_FRAMER_2) == (uint32_t)ADI_ADRV9025_FRAMER_2) + { + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + ADI_ADRV9025_FRAMER_2, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_FRAMER_2, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + sysrefEnabledForFramer2 = ADI_TRUE; + } + } + else + { + /* Enable/reset Adrv9010 Framer(s) */ + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + link, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + adi_common_hal_Wait_ms(&adrv9025Device->common, + 50); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + link, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Adrv9010 Unmask incoming Sysref in Framer(s) */ + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + (uint8_t)link, + ADI_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + } + + /* Wait 100ms for clock recovery on FPGA to lock */ + adi_common_hal_Wait_ms(&adrv9025Device->common, + 100); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Enable/reset FPGA Deframer(s) */ + recoveryAction = adi_fpga9010_DeframerReset(fpga9010Device, + (uint8_t)link); + ADI_ERROR_REPORT(&fpga9010Device->common, + ADI_COMMON_ERRSRC_API, + fpga9010Device->common.error.errCode, + recoveryAction, + NULL, + fpga9010Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9010Device->common.error.newAction); + + /* Unmask incoming sysref in FPGA deframers (leave tx links untouched) */ + recoveryAction = adi_fpga9010_SysRefEnableSet(fpga9010Device, + 0, + (uint8_t)link, + ADI_ENABLE); + ADI_ERROR_REPORT(&fpga9010Device->common, + ADI_COMMON_ERRSRC_API, + fpga9010Device->common.error.errCode, + recoveryAction, + NULL, + fpga9010Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9010Device->common.error.newAction); + + /* Request sysref to bring up Rx links */ + recoveryAction = adi_ad9528_SysrefRequest(ad9528Device, + 1); + ADI_ERROR_REPORT(&ad9528Device->common, + ADI_COMMON_ERRSRC_API, + ad9528Device->common.error.errCode, + recoveryAction, + NULL, + ad9528Device->common.error.errormessage); + ADI_ERROR_RETURN(ad9528Device->common.error.newAction); + + if (adrv9025Device->devStateInfo.linkSharingEnabled == 0) + { + /* Adrv9010 mask sysref in Framers. Precaution against future sysref signals */ + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + (uint8_t)link, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + } + + if (sysrefEnabledForFramer2 == ADI_TRUE) + { + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_FRAMER_2, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + } + + /* Mask sysref in fpga deframers. Precaution against future sysref signals */ + recoveryAction = adi_fpga9010_SysRefEnableSet(fpga9010Device, + 0, + (uint8_t)link, + ADI_DISABLE); + ADI_ERROR_REPORT(&fpga9010Device->common, + ADI_COMMON_ERRSRC_API, + fpga9010Device->common.error.errCode, + recoveryAction, + NULL, + fpga9010Device->common.error.errormessage); + ADI_ERROR_RETURN(fpga9010Device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_board_adrv9025ADS8_JesdBringup(adi_adrv9025_Device_t* adrv9025Device, + adi_fpga9010_Device_t* fpgaDevice, + adi_ad9528_Device_t* ad9528Device, + uint32_t txLinkSel, + uint32_t rxLinkSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t i = 0; + uint8_t adrv9025LinkStatus = 0; + uint8_t fpga9010LinkStatus = 0; + uint8_t deframerLinkCondition = 0; + + /* Mask all sysrefs in Adrv9025 */ + recoveryAction = adi_adrv9025_DeframerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_DEFRAMER_0, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerSysrefCtrlSet(adrv9025Device, + ADI_ADRV9025_ALL_FRAMERS, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Mask all sysrefs in fpga */ + recoveryAction = adi_fpga9010_SysRefEnableSet(fpgaDevice, + ADI_FPGA9010_FRAMER_ALL, + ADI_FPGA9010_DEFRAMER_ALL, + ADI_DISABLE); + ADI_ERROR_REPORT(&fpgaDevice->common, + ADI_COMMON_ERRSRC_API, + fpgaDevice->common.error.errCode, + recoveryAction, + NULL, + fpgaDevice->common.error.errormessage); + ADI_ERROR_RETURN(fpgaDevice->common.error.newAction); + + /* Disable all the FPGA framer & deframers */ + recoveryAction = adi_fpga9010_FramerDisable(fpgaDevice, + ADI_FPGA9010_FRAMER_ALL); + ADI_ERROR_REPORT(&fpgaDevice->common, + ADI_COMMON_ERRSRC_API, + fpgaDevice->common.error.errCode, + recoveryAction, + NULL, + fpgaDevice->common.error.errormessage); + ADI_ERROR_RETURN(fpgaDevice->common.error.newAction); + + recoveryAction = adi_fpga9010_DeframerDisable(fpgaDevice, + ADI_FPGA9010_DEFRAMER_ALL); + ADI_ERROR_REPORT(&fpgaDevice->common, + ADI_COMMON_ERRSRC_API, + fpgaDevice->common.error.errCode, + recoveryAction, + NULL, + fpgaDevice->common.error.errormessage); + ADI_ERROR_RETURN(fpgaDevice->common.error.newAction); + + /* Disable all the ADRV9025 framer & deframers */ + recoveryAction = adi_adrv9025_DfrmLinkStateSet(adrv9025Device, + (uint8_t)ADI_ADRV9025_DEFRAMER_0, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + recoveryAction = adi_adrv9025_FramerLinkStateSet(adrv9025Device, + (uint8_t)ADI_ADRV9025_ALL_FRAMERS, + ADI_DISABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + /* Override DFE LPM in PHY before sending sys ref */ + adi_fpga9010_ChannelDfeLpmOverrideSet(fpgaDevice, + 0xFF, + 1); + ADI_ERROR_REPORT(&fpgaDevice->common, + ADI_COMMON_ERRSRC_API, + fpgaDevice->common.error.errCode, + recoveryAction, + NULL, + fpgaDevice->common.error.errormessage); + ADI_ERROR_RETURN(fpgaDevice->common.error.newAction); + + if (rxLinkSel != 0) + { + /* Bring up the Rx links */ + adi_board_adrv9025ADS8_JesdRxBringup(adrv9025Device, + fpgaDevice, + ad9528Device, + rxLinkSel); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + if (fpgaDevice->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + adi_fpga9010_Jesd204CDeframerCmdDataSet(fpgaDevice, + rxLinkSel, + ADI_ENABLE, + ADI_ENABLE); + ADI_ERROR_REPORT(&fpgaDevice->common, + ADI_COMMON_ERRSRC_API, + fpgaDevice->common.error.errCode, + recoveryAction, + NULL, + fpgaDevice->common.error.errormessage); + ADI_ERROR_RETURN(fpgaDevice->common.error.newAction); + } + } + + if (txLinkSel != 0) + { + /* Bring up the Tx links */ + adi_board_adrv9025ADS8_JesdTxBringup(adrv9025Device, + fpgaDevice, + ad9528Device, + txLinkSel); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + if (fpgaDevice->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + adi_fpga9010_Jesd204CFramerCmdDataSet(fpgaDevice, + txLinkSel, + ADI_ENABLE, + ADI_ENABLE); + ADI_ERROR_REPORT(&fpgaDevice->common, + ADI_COMMON_ERRSRC_API, + fpgaDevice->common.error.errCode, + recoveryAction, + NULL, + fpgaDevice->common.error.errormessage); + ADI_ERROR_RETURN(fpgaDevice->common.error.newAction); + } + } + + /* Disable DFE LPM in PHY before after sys ref */ + adi_fpga9010_ChannelDfeLpmOverrideSet(fpgaDevice, + 0xFF, + 0); + ADI_ERROR_REPORT(&fpgaDevice->common, + ADI_COMMON_ERRSRC_API, + fpgaDevice->common.error.errCode, + recoveryAction, + NULL, + fpgaDevice->common.error.errormessage); + ADI_ERROR_RETURN(fpgaDevice->common.error.newAction); + + /* Adrv9025 Deframer Status get*/ + for (i = 0; i < ADI_ADRV9025_NUM_DEFRAMERS; i++) + { + if ((txLinkSel & (1 << i)) > 0) + { + deframerLinkCondition = 0; + recoveryAction = adi_adrv9025_DfrmLinkConditionGet(adrv9025Device, + (adi_adrv9025_DeframerSel_e)((uint8_t)(1 << i)), + &deframerLinkCondition); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + + if (deframerLinkCondition & 0x01) + { + adrv9025LinkStatus |= (1 << i); + } + } + } + + /* Fpga Reading User Data Ready bit*/ + recoveryAction = adi_fpga9010_DeframerStatusGet(fpgaDevice, + rxLinkSel, + &fpga9010LinkStatus); + ADI_ERROR_REPORT(&fpgaDevice->common, + ADI_COMMON_ERRSRC_API, + fpgaDevice->common.error.errCode, + recoveryAction, + NULL, + fpgaDevice->common.error.errormessage); + ADI_ERROR_RETURN(fpgaDevice->common.error.newAction); + + if (adrv9025LinkStatus != txLinkSel) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_INTERFACE; + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Not all Tx links have been established."); + + /* Disable all the FPGA deframers. Don't update the error though, this is just cleanup */ + adi_fpga9010_FramerDisable(fpgaDevice, + ADI_FPGA9010_FRAMER_ALL); + } + if (fpga9010LinkStatus != rxLinkSel) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_INTERFACE; + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Not all Rx links have been established."); + + /* Disable all the FPGA deframers. Don't update the error though, this is just cleanup */ + adi_fpga9010_DeframerDisable(fpgaDevice, + ADI_FPGA9010_DEFRAMER_ALL); + } + + /* Kick off SERDES tracking cal if lanes are up */ + if (recoveryAction == ADI_COMMON_ACT_NO_ACTION) + { + recoveryAction = adi_adrv9025_TrackingCalsEnableSet(adrv9025Device, + ADI_ADRV9025_TRACK_DESERIALIZER, + ADI_ADRV9025_TRACKING_CAL_ENABLE); + ADI_ERROR_REPORT(&adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + adrv9025Device->common.error.errCode, + recoveryAction, + NULL, + adrv9025Device->common.error.errormessage); + ADI_ERROR_RETURN(adrv9025Device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_board_adrv9025ADS8_Program_Phase1(adi_board_adrv9025Ads8_t* adrv9025Ads801, + adi_adrv9025_Init_t* adrv9025Init, + adi_ad9528_Init_t* ad9528Init, + adi_adrv9025_PlatformFiles_t* adrv9025PlatformFiles) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adi_fpga9010_AxiAdvSpiFeatConfig_t fpgaAdvSpiCfg = {0}; + + fpgaAdvSpiCfg.enable = 1; + fpgaAdvSpiCfg.cpha = 0; + fpgaAdvSpiCfg.cpol = 0; + fpgaAdvSpiCfg.lsbFirst = 0; + fpgaAdvSpiCfg.fourWire = 1; + fpgaAdvSpiCfg.misoSampleSlip = 1; + fpgaAdvSpiCfg.threeWireTriPoint = 16; + fpgaAdvSpiCfg.clockDiv = 1; + + /* AD9528: 25Mhz SPICLK, but with SPIDO clocked half clock cycle later for improved setup.hold */ + recoveryAction = adi_fpga9010_AxiAdvSpiCfgSet(adrv9025Ads801->fpgaDevice, + &fpgaAdvSpiCfg, + 0); + if (recoveryAction != 0) + { + return recoveryAction; + } + /* ADRV9025: 25Mhz SPICLK, but with SPIDO clocked half clock cycle later for improved setup.hold */ + recoveryAction = adi_fpga9010_AxiAdvSpiCfgSet(adrv9025Ads801->fpgaDevice, + &fpgaAdvSpiCfg, + 1); + if (recoveryAction != 0) + { + return recoveryAction; + } + + /* Reset FPGA MMCM to prevent lock up issues when switching FPGA refClk values */ + recoveryAction = adi_fpga9010_MmcmResetSet(adrv9025Ads801->fpgaDevice, + ADI_FPGA9010_CORE_MMCM); + ADI_ERROR_REPORT(&adrv9025Ads801->fpgaDevice->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error resetting clock wizard"); + ADI_ERROR_RETURN(adrv9025Ads801->fpgaDevice->common.error.newAction); + + /* Init Ad9528 */ + if ((recoveryAction = adi_board_adrv9025ADS8_Ad9528Init(adrv9025Ads801->ad9528Device, + adrv9025Ads801->fpgaDevice, + ad9528Init, + adrv9025Init)) != ADI_COMMON_ACT_NO_ACTION) + { + return recoveryAction; + } + + + if ((recoveryAction = adi_board_adrv9025ADS8_Fpga9010Init(adrv9025Ads801->fpgaDevice, + adrv9025Init)) != 0) + { + return recoveryAction; + } + + + /* Reset Hardware */ + recoveryAction = adi_adrv9025_HwReset(adrv9025Ads801->adrv9025Device); + ADI_ERROR_REPORT(&adrv9025Ads801->adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Reset Adrv9025 device"); + ADI_ERROR_RETURN(adrv9025Ads801->adrv9025Device->common.error.newAction); + + /* Custom Step for ADI eval card to read ADRV9025 internal LDO bypass setting from the eval boards EEPROM to make sure the + * silicon is not accidentally damaged. ADI stores this in a custom FMC EEPROM field used for the BOM revision of the PCB */ + if ((recoveryAction = adi_adrv9025Board_LdoSelectOverRide(adrv9025Init)) != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&adrv9025Ads801->adrv9025Device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to perform Ldo Select override"); + ADI_ERROR_RETURN(recoveryAction); + } + + /* Pre MCS - Broadcastable */ + if ((recoveryAction = adi_adrv9025_PreMcsInit_v2(adrv9025Ads801->adrv9025Device, + adrv9025Init, + adrv9025PlatformFiles->armImageFile, + adrv9025PlatformFiles->streamImageFile, + adrv9025PlatformFiles->rxGainTableFileArr, + adrv9025PlatformFiles->rxGainTableFileArrSize, + adrv9025PlatformFiles->txAttenTableFileArr, + adrv9025PlatformFiles->txAttenTableFileArrSize)) != ADI_COMMON_ACT_NO_ACTION) + { + return recoveryAction; + } + + /* Pre MCS - Non-Broadcastable */ + if ((recoveryAction = adi_adrv9025_PreMcsInit_NonBroadCast(adrv9025Ads801->adrv9025Device, + adrv9025Init)) != ADI_COMMON_ACT_NO_ACTION) + { + return recoveryAction; + } + + return 0; +} + +int32_t adi_board_adrv9025ADS8_Program_Phase2(adi_board_adrv9025Ads8_t* adrv9025Ads801, + adi_adrv9025_Init_t* adrv9025Init, + adi_adrv9025_PostMcsInit_t* adrv9025PostMcsInit, + adi_ad9528_Init_t* ad9528Init) +{ + (void)(ad9528Init); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t mcsStatus = 0; + uint8_t i = 0; + uint32_t txLinkSel = 0; + uint32_t rxLinkSel = 0; + + /* MCS start sequence*/ + if ((recoveryAction = adi_adrv9025_MultichipSyncSet(adrv9025Ads801->adrv9025Device, + ADI_ENABLE)) < 0) + { + return recoveryAction; + } + + /* This loop will send SysRef pulses up to 255 times unless MCS status achieved before. */ + for (i = 0; i < 255; i++) + { + if ((recoveryAction = adi_ad9528_SysrefRequest(adrv9025Ads801->ad9528Device, + 1)) != 0) + { + return recoveryAction; + } + else + { + if ((recoveryAction = adi_adrv9025_MultichipSyncStatusGet(adrv9025Ads801->adrv9025Device, + &mcsStatus)) != 0) + { + return recoveryAction; + } + else + { + if ((mcsStatus & 0x17) == 0x17) + { + break; + } + } + } + } + + if ((mcsStatus & 0x17) != 0x17) + { + /*perror("ADRV9025 CLKPLL MCS status not correct\n");*/ + /*TODO : Add error message once there is error reporting added at the board level*/ + return ADI_COMMON_ACT_ERR_RESET_FULL; + } + + /* MCS end sequence*/ + if ((recoveryAction = adi_adrv9025_MultichipSyncSet(adrv9025Ads801->adrv9025Device, + ADI_DISABLE)) < 0) + { + return recoveryAction; + } + + /* Post MCS */ + if ((recoveryAction = adi_adrv9025_PostMcsInit(adrv9025Ads801->adrv9025Device, + adrv9025PostMcsInit)) < 0) + { + return recoveryAction; + } + + if ((recoveryAction = adi_adrv9025_SerializerReset(adrv9025Ads801->adrv9025Device, + adrv9025Init->clocks.serdesPllVcoFreq_kHz)) < 0) + { + return recoveryAction; + } + + for (i = 0; i < ADI_ADRV9025_NUM_FRAMERS; i++) + { + if (adrv9025Init->dataInterface.framer[i].serializerLanesEnabled > 0) + { + rxLinkSel |= 1 << i; + } + } + + for (i = 0; i < ADI_ADRV9025_NUM_DEFRAMERS; i++) + { + if (adrv9025Init->dataInterface.deframer[i].deserializerLanesEnabled > 0) + { + txLinkSel |= 1 << i; + } + } + + /* JESD204 link bring up */ + if ((recoveryAction = adi_board_adrv9025ADS8_JesdBringup(adrv9025Ads801->adrv9025Device, + adrv9025Ads801->fpgaDevice, + adrv9025Ads801->ad9528Device, + txLinkSel, + rxLinkSel)) < 0) + { + return recoveryAction; + } + + /* Initialize Tx Ramp down functionality */ + if ((recoveryAction = adi_adrv9025_TxRampDownInit(adrv9025Ads801->adrv9025Device, + adrv9025Init) < 0)) + { + return recoveryAction; + } + + /* Setup GP Interrupts from init structure */ + if ((recoveryAction = adi_adrv9025_GpIntInit(adrv9025Ads801->adrv9025Device, + &adrv9025Init->gpInterrupts) < 0)) + { + return recoveryAction; + } + + return 0; +} + +int32_t adi_board_adrv9025ADS8_Ad9528Configure(adi_board_adrv9025Ads8_t* adrv9025ADS8, + adi_ad9528_Init_t* ad9528Init, + uint32_t deviceClock_kHz, + uint32_t vcxoFreq_kHz, + uint32_t refAFreq_kHz, + uint32_t fpgaClock_kHz) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adi_ad9528_ClockFrequencySettings_t clockFrequencies = {0}; + + /* TODO: if 9025EE EVB, set different settings for 9528 setup */ + + if (strstr(&adrv9025ADS8->pcbName[0], + "9025EE") != NULL) + { + clockFrequencies.vcxoFrequency_Hz = vcxoFreq_kHz * 1000; + clockFrequencies.refAFrequency_Hz = 0; + clockFrequencies.outputClock_Hz[0] = 120000; /* TODO: SYSREF should not be fixed, this will break future profiles */ + clockFrequencies.outputClock_Hz[3] = fpgaClock_kHz * 1000; + clockFrequencies.outputClock_Hz[12] = 120000; + clockFrequencies.outputClock_Hz[13] = fpgaClock_kHz * 1000; + clockFrequencies.outSource[0] = ADI_AD9528_SYSREF; + clockFrequencies.outSource[12] = ADI_AD9528_SYSREF; + + /* Clear out the init structure because InitStructConfig sets all appropriate members */ + memset(ad9528Init, + 0, + sizeof(adi_ad9528_Init_t)); + + if ((recoveryAction = adi_ad9528_InitStructConfig(adrv9025ADS8->ad9528Device, + &clockFrequencies, + ad9528Init)) < 0) + { + return recoveryAction; + } + } + else + { + clockFrequencies.vcxoFrequency_Hz = vcxoFreq_kHz * 1000; + clockFrequencies.refAFrequency_Hz = refAFreq_kHz * 1000; + clockFrequencies.outputClock_Hz[0] = 120000; /* TODO: SYSREF should not be fixed, this will break future profiles */ + clockFrequencies.outputClock_Hz[1] = deviceClock_kHz * 1000; + clockFrequencies.outputClock_Hz[3] = fpgaClock_kHz * 1000; + clockFrequencies.outputClock_Hz[12] = 120000; + clockFrequencies.outputClock_Hz[13] = fpgaClock_kHz * 1000; + clockFrequencies.outSource[0] = ADI_AD9528_SYSREF; + clockFrequencies.outSource[12] = ADI_AD9528_SYSREF; + + /* Clear out the init structure because InitStructConfig sets all appropriate members */ + memset(ad9528Init, + 0, + sizeof(adi_ad9528_Init_t)); + + if ((recoveryAction = adi_ad9528_InitStructConfig(adrv9025ADS8->ad9528Device, + &clockFrequencies, + ad9528Init)) < 0) + { + return recoveryAction; + } + + ad9528Init->pll1Settings.vcxoBufferCtrl = ADI_AD9528_SINGLE_ENDED; + } + + return recoveryAction; +} + +int32_t adi_board_adrv9025ADS8_Jesd204LinkReset(adi_board_adrv9025Ads8_t* adrv9025ADS8, + adi_adrv9025_Init_t* adrv9025Init) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t i = 0; + uint32_t txLinkSel = 0; + uint32_t rxLinkSel = 0; + + for (i = 0; i < ADI_ADRV9025_NUM_FRAMERS; i++) + { + if (adrv9025Init->dataInterface.framer[i].serializerLanesEnabled > 0) + { + rxLinkSel |= 1 << i; + } + } + + for (i = 0; i < ADI_ADRV9025_NUM_DEFRAMERS; i++) + { + if (adrv9025Init->dataInterface.deframer[i].deserializerLanesEnabled > 0) + { + txLinkSel |= 1 << i; + } + } + + /* JESD204 link bring up */ + if ((recoveryAction = adi_board_adrv9025ADS8_JesdBringup(adrv9025ADS8->adrv9025Device, + adrv9025ADS8->fpgaDevice, + adrv9025ADS8->ad9528Device, + txLinkSel, + rxLinkSel)) < 0) + { + return recoveryAction; + } + + return 0; +} diff --git a/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/fpga9010/adi_fpga9010_daughter_board.c b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/fpga9010/adi_fpga9010_daughter_board.c new file mode 100644 index 0000000..2453bf0 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/fpga9010/adi_fpga9010_daughter_board.c @@ -0,0 +1,97 @@ +/** + * \file adi_fpga9010_daughter_board.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9010.h" +#include "adi_motherboard_trx.h" +#include +#include + +/**************************************************************************** +* Local functions +****************************************************************************/ + +int32_t adi_fpga9010Board_Dispatch(adi_daughterboard_trx_t *trxDaughterboard, adrvtrx_board_action_e actionFlags) +{ + int32_t recoveryAction = ADI_COMMON_HAL_OK; + uint32_t fpgaVersion = 0; + uint8_t enableJesd204C = ADI_FALSE; + adi_fpga9010_Device_t *fpga9010Device = NULL; + + /* FPGA allocation */ + if (actionFlags == TRX_BOARD_ACTION_DEVICE_ALLOC) + { + trxDaughterboard->fpgaDevice = (uintptr_t) calloc(1, sizeof(adi_fpga9010_Device_t)); + if (trxDaughterboard->fpgaDevice == 0) + { + return (ADI_COMMON_HAL_GEN_SW); + } + + trxDaughterboard->fpgaAbstractDev.commonAbstractDevice = (adi_common_Device_t *) trxDaughterboard->fpgaDevice; + trxDaughterboard->fpgaAbstractDev.fpgaAbstractDevice = trxDaughterboard->fpgaDevice; + ((adi_fpga9010_Device_t *) trxDaughterboard->fpgaDevice)->memoryPageSize = MEM_SIZE_256MB; + + return (ADI_COMMON_HAL_OK); + } + + /* FPGA Initialization */ + if (actionFlags == TRX_BOARD_ACTION_FPGA_INIT) + { + fpga9010Device = (adi_fpga9010_Device_t *)trxDaughterboard->fpgaDevice; + enableJesd204C = trxDaughterboard->savedInfo.enable204cState; + + /* Verify FPGA design Version number is for ADRV9025 & is recent enough for the current API */ + recoveryAction = adi_fpga9010_VersionRead(fpga9010Device); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + return (recoveryAction); + } + + fpgaVersion = (fpga9010Device->devStateInfo.versionMajor << 16) + fpga9010Device->devStateInfo.versionMinor; + + if (fpgaVersion < ADI_FPGA9010_MIN_VERSION) + { + ADI_ERROR_REPORT(&fpga9010Device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_INVALID_FPGA_IMAGE, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Incompatible FPGA."); + ADI_ERROR_RETURN(fpga9010Device->common.error.newAction); + } + + if (fpga9010Device->devStateInfo.designId == ADI_FPGA9010_JESD204B_DEVICEID) + { + fpga9010Device->devStateInfo.encodingHighValue = 10; + fpga9010Device->devStateInfo.encodingLowValue = 8; + fpga9010Device->devStateInfo.linkLayerDataWidth = 40; + fpga9010Device->devStateInfo.dmaDataWidth = 32; + + if (enableJesd204C != ADI_FALSE) + { + ADI_ERROR_REPORT(&fpga9010Device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Cannot use a 204C profile with a 204B FPGA."); + ADI_ERROR_RETURN(fpga9010Device->common.error.newAction); + } + } + else if (fpga9010Device->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + fpga9010Device->devStateInfo.encodingHighValue = 66; + fpga9010Device->devStateInfo.encodingLowValue = 64; + fpga9010Device->devStateInfo.linkLayerDataWidth = 66; + fpga9010Device->devStateInfo.dmaDataWidth = 64; + + if (enableJesd204C == ADI_FALSE) + { + ADI_ERROR_REPORT(&fpga9010Device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Cannot use a 204B profile with a 204C FPGA."); + ADI_ERROR_RETURN(fpga9010Device->common.error.newAction); + } + } + + return (ADI_COMMON_HAL_OK); + } + + return (ADI_COMMON_HAL_OK); +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/fpga9025/adi_fpga9025_daughter_board.c b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/fpga9025/adi_fpga9025_daughter_board.c new file mode 100644 index 0000000..d4a36fd --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/fpga9025/adi_fpga9025_daughter_board.c @@ -0,0 +1,127 @@ +/** + * \file adi_fpga9025_daughter_board.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9025.h" +#include +#include +#include "adi_platform_identify.h" +#include "adi_motherboard_trx.h" + +/**************************************************************************** +* Local functions +****************************************************************************/ + +int32_t adi_fpga9025Board_Dispatch(adi_daughterboard_trx_t* trxDaughterboard, + adrvtrx_board_action_e actionFlags) +{ + int32_t recoveryAction = ADI_COMMON_HAL_OK; + uint32_t fpgaVersion = 0; + adi_fpga9025_Device_t* fpga9025Device = NULL; + uint8_t enableJesd204C = ADI_FALSE; + + /* FPGA allocation */ + if (actionFlags == TRX_BOARD_ACTION_DEVICE_ALLOC) + { + trxDaughterboard->fpgaDevice = (uintptr_t)calloc(1, + sizeof(adi_fpga9025_Device_t)); + if (trxDaughterboard->fpgaDevice == 0) + { + return (ADI_COMMON_HAL_GEN_SW); + } + + /* Assigning Abstract pointers */ + trxDaughterboard->fpgaAbstractDev.commonAbstractDevice = (adi_common_Device_t *)trxDaughterboard->fpgaDevice; + trxDaughterboard->fpgaAbstractDev.fpgaAbstractDevice = trxDaughterboard->fpgaDevice; + ((adi_fpga9025_Device_t *)trxDaughterboard->fpgaDevice)->memoryPageSize = MEM_SIZE_1GB; + + return (ADI_COMMON_HAL_OK); + } + + /* FPGA Initialization */ + if (actionFlags == TRX_BOARD_ACTION_FPGA_INIT) + { + fpga9025Device = (adi_fpga9025_Device_t *)trxDaughterboard->fpgaDevice; + enableJesd204C = trxDaughterboard->savedInfo.enable204cState; + + /* Verify FPGA design Version number is for ADRV9025 & is recent enough for the current API */ + recoveryAction = adi_fpga9025_VersionRead(fpga9025Device); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + return (recoveryAction); + } + + /* Init FPGA */ + fpgaVersion = (fpga9025Device->devStateInfo.versionMajor << 16) + fpga9025Device->devStateInfo.versionMinor; + + if (fpgaVersion < ADI_FPGA9025_MIN_VERSION) + { + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_INVALID_FPGA_IMAGE, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Incompatible FPGA."); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + } + + if (fpga9025Device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID) + { + fpga9025Device->devStateInfo.encodingHighValue = 10; + fpga9025Device->devStateInfo.encodingLowValue = 8; + fpga9025Device->devStateInfo.linkLayerDataWidth = 40; + fpga9025Device->devStateInfo.dmaDataWidth = 32; + + if (enableJesd204C != ADI_FALSE) + { + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Cannot use a 204C profile with a 204B FPGA."); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + } + } + else if (fpga9025Device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + fpga9025Device->devStateInfo.encodingHighValue = 66; + fpga9025Device->devStateInfo.encodingLowValue = 64; + fpga9025Device->devStateInfo.linkLayerDataWidth = 66; + fpga9025Device->devStateInfo.dmaDataWidth = 64; + + if (enableJesd204C == ADI_FALSE) + { + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Cannot use a 204B profile with a 204C FPGA."); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + } + } + else + { + ADI_ERROR_REPORT(&fpga9025Device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_INVALID_FPGA_IMAGE, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Invalid FPGA image."); + ADI_ERROR_RETURN(fpga9025Device->common.error.newAction); + } + + return (ADI_COMMON_HAL_OK); + } + + return (ADI_COMMON_HAL_OK); +} diff --git a/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/makefile b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/makefile new file mode 100644 index 0000000..0cba5d1 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/makefile @@ -0,0 +1,30 @@ +LIBADI_DAUGHTERBOARD = libadi_daughterboard.a +CC = gcc +ADI_ADRV9025_DAUGHTERBOARD_SRC = ./adrv9025/src +ADI_AD9528_DAUGHTERBOARD_SRC = ./ad9528/src +ADI_FPGA9025_DAUGHTERBOARD_SRC = ./fpga9025 +ADI_FPGA9010_DAUGHTERBOARD_SRC = ./fpga9010 + +ARFLAGS = -rv +CFLAGS = -Wall -Werror -I ./adrv9025/include -I ../motherboards -I ../daughterboards -I ../../devices/adrv9025/public/include/ -I ../../devices/fpga9010/public/include/ -I ../../devices/fpga9025/public/include/ -I ../../devices/ad9528/public/include/ -I ../../platforms/ -I ../../platforms/platform_utils -I ../../common/ -I ../../common/adi_error -I ../../common/adi_logging -I../../common/adi_hal +EXT = c + +SRC = $(wildcard *.$(EXT)) \ + $(wildcard $(ADI_ADRV9025_DAUGHTERBOARD_SRC)/*.$(EXT) \ + $(ADI_AD9528_DAUGHTERBOARD_SRC)/*.$(EXT) \ + $(ADI_FPGA9025_DAUGHTERBOARD_SRC)/*.$(EXT) \ + $(ADI_FPGA9010_DAUGHTERBOARD_SRC)/*.$(EXT)) + +OBJS = $(SRC:.$(EXT)=.o) + +all: $(SRC) $(LIBADI_DAUGHTERBOARD) + +.$(EXT).o: + $(CC) $(CFLAGS) -DADRV9025 -o $@ -c $< + +$(LIBADI_DAUGHTERBOARD): $(OBJS) + ar $(ARFLAGS) $(LIBADI_DAUGHTERBOARD) $(OBJS) + +clean: + rm -rf *.o + rm -rf *.a diff --git a/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/share_boards/adi_board_STSHAL01_types.h b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/share_boards/adi_board_STSHAL01_types.h new file mode 100644 index 0000000..9170c6e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/daughterboards/share_boards/adi_board_STSHAL01_types.h @@ -0,0 +1,44 @@ +/** + * \file adi_board_STSHAL01_types.h + * + * API Version: $ADI_API_VERSION$ + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_BOARD_STSHAL01_TYPES_H_ +#define _ADI_BOARD_STSHAL01_TYPES_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Enum of possible Control Modes for STSHAL board type +* STS_PREMCS_INIT = 1000; +* STS_POSTMCS_INIT = 2000; +* STS_POSTMCS_INIT_InitCals = 2100; +* STS_SYSREF_REQUEST = 3000; +* STS_MULTICHIPSYNC = 4000; +* STS_LINK_BRINGUP = 5000; +*/ +typedef enum adi_board_stshal_modeSelect +{ + ADI_BOARD_STSHAL01_PREMCS_INIT = 1000, /*!< Selects a STSHAL PreMcsInit Function */ + ADI_BOARD_STSHAL01_POSTMCS_INIT = 2000, /*!< Selects a STSHAL PostMcsInit Function */ + ADI_BOARD_STSHAL01_POSTMCS_INIT_INITCALS = 2100, /*!< Selects a STSHAL PostMcsInit InitCals Function No Actions Taken */ + ADI_BOARD_STSHAL01_SYSREF_REQUEST = 3000, /*!< Selects a STSHAL SysRef Request Function */ + ADI_BOARD_STSHAL01_MCS_INIT = 4000, /*!< Selects a STSHAL MCS Init Function No Actions Taken*/ + ADI_BOARD_STSHAL01_JESDBRINGUP = 5000 /*!< Selects a STSHAL JESD BRINGUP of type ATE tester */ +} adi_board_stshal_modeSelect_e; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/boards/makefile b/driver/rfic/rf/adrv9025/c_src/boards/makefile new file mode 100644 index 0000000..547c111 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/makefile @@ -0,0 +1,64 @@ +LIB_ADI_BOARDS = libadi_boards.a + +ADI_MOTHERBOARD_SRC = ./daughterboards +ADI_DAUGHTERBOARD_SRC = ./motherboards +ADI_PLATFORM_SRC = ../platforms +ADI_COMMON_SRC = ../common +ADI_COMMON_ERROR_SRC = ../common/adi_error +ADI_COMMON_LOGGING_SRC = ../common/adi_logging +ADI_COMMON_HAL_SRC = ../common/adi_hal +ADI_FPGA9025_SRC = ../devices/fpga9025 +ADI_FPGA9010_SRC = ../devices/fpga9010 +ADI_AD9528_SRC = ../devices/ad9528 +ADI_ADRV9025_SRC = ../devices/adrv9025 + +ARFLAGS = -rv + +all: adi_platform_lib \ + adi_common_lib \ + adi_fpga9025_lib \ + adi_fpga9010_lib \ + adi_ad9528_lib \ + adi_adrv9025_lib \ + motherboard_lib \ + daughterboard_lib \ + $(LIB_ADI_BOARDS) + +$(LIB_ADI_BOARDS): $(OBJS) + ar $(ARFLAGS) $(LIB_ADI_BOARDS) + +motherboard_lib: + $(MAKE) -C $(ADI_MOTHERBOARD_SRC) + +daughterboard_lib: + $(MAKE) -C $(ADI_DAUGHTERBOARD_SRC) + +adi_platform_lib: + $(MAKE) -C $(ADI_PLATFORM_SRC) + +adi_common_lib: + $(MAKE) -C $(ADI_COMMON_SRC) + +adi_fpga9025_lib: + $(MAKE) -C $(ADI_FPGA9025_SRC) + +adi_fpga9010_lib: + $(MAKE) -C $(ADI_FPGA9010_SRC) + +adi_ad9528_lib: + $(MAKE) -C $(ADI_AD9528_SRC) + +adi_adrv9025_lib: + $(MAKE) -C $(ADI_ADRV9025_SRC) + +clean: + rm -rf *.o + rm -rf *.a + $(MAKE) -C $(ADI_MOTHERBOARD_SRC) clean + $(MAKE) -C $(ADI_DAUGHTERBOARD_SRC) clean + $(MAKE) -C $(ADI_PLATFORM_SRC) clean + $(MAKE) -C $(ADI_COMMON_SRC) clean + $(MAKE) -C $(ADI_FPGA9025_SRC) clean + $(MAKE) -C $(ADI_FPGA9010_SRC) clean + $(MAKE) -C $(ADI_AD9528_SRC) clean + $(MAKE) -C $(ADI_ADRV9025_SRC) clean diff --git a/driver/rfic/rf/adrv9025/c_src/boards/motherboards/adi_motherboard_trx.c b/driver/rfic/rf/adrv9025/c_src/boards/motherboards/adi_motherboard_trx.c new file mode 100644 index 0000000..1badf61 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/motherboards/adi_motherboard_trx.c @@ -0,0 +1,768 @@ +/** + * \file adi_board_trx.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_platform.h" +#include "adi_fmc_eeprom.h" +#include "adi_fmc_fru.h" +#include "adi_platform_identify.h" + +#include "adi_motherboard_trx.h" +#include "adi_daughterboard_trx_dev.h" + +#include +#include + +#ifdef _ADI_STS_PLATFORM +#define strncasecmp(_x,_y,_z) _strnicmp((_x),(_y),(_z)) +#endif + +/** + * Platform and board discovery functions + * This functions are called while in board discovery in order to assignate the correct HAL layer and FPGA drivers + */ + +/**************************************************************************** +* Local functions +****************************************************************************/ + +static int32_t adi_motherboard_Compare(adi_motherboard_trx_t* trxMotherboard1, + adi_motherboard_trx_t* trxMotherboard2) +{ + int32_t i = 0; + + if ((trxMotherboard1 == NULL) || (trxMotherboard2 == NULL)) + { + return ADI_FALSE; + } + + for (i = 0; i < ADI_MAX_DAUGHTERBOARDS; i++) + { + if ((trxMotherboard1->daughterboards[i] != NULL) && (trxMotherboard2->daughterboards[i] != NULL)) + { + if (trxMotherboard1->daughterboards[i]->daughterCardId != trxMotherboard2->daughterboards[i]->daughterCardId) + { + return ADI_FALSE; + } + } + else if ((trxMotherboard1->daughterboards[i] == NULL) && (trxMotherboard2->daughterboards[i] == NULL)) + { + continue; + } + else + { + return ADI_FALSE; + } + } + + return ADI_TRUE; +} + +/* + * This function is to read the EEPROM of the daughter card to learn its identity (i.e. 9010 or 9025 etc.) and fill up the FRU structure. + */ +static FRU_DATA_t* trx_BoardReadFru(void* devHalCfg) +{ + struct FRU_DATA* fru = NULL; + adi_hal_Cfg_t* halCfg = NULL; + uint8_t* raw_input_data = NULL; + + if (devHalCfg == NULL) + { + return (0); + } + + /* Cast void *devHalCfg structure to the specific structure for ADS9 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->i2cCfg.drvName[0] == '\0') + { + return 0; + } + + /* trx_read_file will allocate a chunk of memory to hold the FRU information */ + if ((raw_input_data = read_file(halCfg->i2cCfg.drvName)) != NULL) + { + fru = parse_FRU(raw_input_data); + /* free memory allocated by trx_read_file() */ + free(raw_input_data); + + /* The parse_FRU() will return a null pointer for fru if an error occurred during reading the EEPROM, so verify a non-NULL pointer */ + if (fru == NULL) + { + return 0; + } + + return fru; + } /* if EEPROM file was readable, will still read even if daughter is not plugged on. */ + else + { + printf_err("ERROR: Board daughter card EEPROM not found or blank.\n"); + return (NULL); + } + + return (0); +} + +/* + * Read the FRU data, parse the FRU data to identify the daughter card. + */ +static int32_t trx_BoardIdentify(adi_daughterboard_trx_t* trxdaughterboard) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + char productName[ADI_BOARD_NAME_SIZE] = {0}; + char* strPtr = NULL; + int i = 0; + FRU_DATA_t* fru = NULL; + + if (trxdaughterboard == NULL) + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + return (ADI_HAL_NULL_PTR); + } + +#ifdef _ADI_STS_PLATFORM + // 9025 is the default daughter board? add daughtercard name? + trxdaughterboard->daughterCardId = ADI_BOARD_9025STSHAL; + strncpy((char *) trxdaughterboard->daughterCardName, "Product Name:9025STSHAL; ; ; ; ; ", ADI_BOARD_NAME_SIZE); +#else + + /* Read the FRU information from EEPROM */ + fru = trx_BoardReadFru(trxdaughterboard->common.devHalInfo); + if (fru == NULL) + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + return (ADI_HAL_NULL_PTR); + } + + /* Copy board name from FRU */ + if (!strncasecmp((const char *)&fru->Board_Area->manufacturer[1], + ADI_MANUFACTURER, + strlen(ADI_MANUFACTURER))) + { + for (i = 0; i < CUSTOM_FIELDS; i++) + { + /* These are ADI custom fields */ + if (fru->Board_Area->custom[i] && (fru->Board_Area->custom[i][0] & 0x3F)) + { + switch (fru->Board_Area->custom[i][1]) + { + case 1: + snprintf(productName, + ADI_BOARD_NAME_SIZE, + "%s", + (fru->Board_Area->custom[i] + 2)); + break; + + // case 2: + // sprintf(tmp_str, "%s", fru->Board_Area->custom[i]); + // strncat(bomStr, ";BOM REV:", (infoStrSize - 1)); + // strncat(infoStr, &tmp_str1[2], (infoStrSize - 1)); + // break; + + default: + break; + } + } + } + } + + /* Save the product name string */ + if ((strPtr = strstr(productName, + "9010CE01")) != NULL) + { + trxdaughterboard->daughterCardId = ADI_BOARD_9010CE01; + trxdaughterboard->daughterCardRev[0] = *(strPtr + 8); + sprintf((char *)trxdaughterboard->daughterCardName, + "Product Name:9010CE01%c; : ; : ; : ; : ; ", + trxdaughterboard->daughterCardRev[0]); + strncpy((char *)trxdaughterboard->daughterCardStrId, + "9010", + 6); + } + else if ((strPtr = strstr(productName, + "9010EE01")) != NULL) + { + trxdaughterboard->boardAttribute |= TRX_DAUGHTERBOARD_ATTRIBUTE_TYPE_EE; + trxdaughterboard->daughterCardId = ADI_BOARD_9010EE01; + trxdaughterboard->daughterCardRev[0] = *(strPtr + 8); + sprintf((char *)trxdaughterboard->daughterCardName, + "Product Name:9010EE01%c; : ; : ; : ; : ; ", + trxdaughterboard->daughterCardRev[0]); + strncpy((char *)trxdaughterboard->daughterCardStrId, + "9010", + 6); + } + else if ((strPtr = strstr(productName, + "9025CE01")) != NULL) + { + trxdaughterboard->daughterCardId = ADI_BOARD_9025CE01; + trxdaughterboard->daughterCardRev[0] = *(strPtr + 8); + sprintf((char *)trxdaughterboard->daughterCardName, + "Product Name:9025CE01%c; : ; : ; : ; : ; ", + trxdaughterboard->daughterCardRev[0]); + strncpy((char *)trxdaughterboard->daughterCardStrId, + "9025", + 6); + } + else if ((strPtr = strstr(productName, + "9025EE01")) != NULL) + { + trxdaughterboard->boardAttribute |= TRX_DAUGHTERBOARD_ATTRIBUTE_TYPE_EE; + trxdaughterboard->daughterCardId = ADI_BOARD_9025EE01; + trxdaughterboard->daughterCardRev[0] = *(strPtr + 8); + sprintf((char *)trxdaughterboard->daughterCardName, + "Product Name:9025EE01%c; : ; : ; : ; : ; ", + trxdaughterboard->daughterCardRev[0]); + strncpy((char *)trxdaughterboard->daughterCardStrId, + "9025", + 6); + } + else if ((strPtr = strstr(productName, + "9026CE01")) != NULL) + { + trxdaughterboard->daughterCardId = ADI_BOARD_9026CE01; + trxdaughterboard->daughterCardRev[0] = *(strPtr + 8); + sprintf((char *)trxdaughterboard->daughterCardName, + "Product Name:9026CE01%c; : ; : ; : ; : ; ", + trxdaughterboard->daughterCardRev[0]); + strncpy((char *)trxdaughterboard->daughterCardStrId, + "9026", + 6); + } + else if ((strPtr = strstr(productName, + "9024CE01")) != NULL) + { + trxdaughterboard->daughterCardId = ADI_BOARD_9024CE01; + trxdaughterboard->daughterCardRev[0] = *(strPtr + 8); + sprintf((char *)trxdaughterboard->daughterCardName, + "Product Name:9024CE01%c; : ; : ; : ; : ; ", + trxdaughterboard->daughterCardRev[0]); + strncpy((char *)trxdaughterboard->daughterCardStrId, + "9024", + 6); + } + else if ((strPtr = strstr(productName, + "9029CE01")) != NULL) + { + trxdaughterboard->daughterCardId = ADI_BOARD_9029CE01; + trxdaughterboard->daughterCardRev[0] = *(strPtr + 8); + sprintf((char *)trxdaughterboard->daughterCardName, + "Product Name:9029CE01%c; : ; : ; : ; : ; ", + trxdaughterboard->daughterCardRev[0]); + strncpy((char *)trxdaughterboard->daughterCardStrId, + "9029", + 6); + } + else if ((strPtr = strstr(productName, + "9020CE01")) != NULL) + { + trxdaughterboard->daughterCardId = ADI_BOARD_9020CE01; + trxdaughterboard->daughterCardRev[0] = *(strPtr + 8); + sprintf((char *)trxdaughterboard->daughterCardName, + "Product Name:9020CE01%c; : ; : ; : ; : ; ", + trxdaughterboard->daughterCardRev[0]); + strncpy((char *)trxdaughterboard->daughterCardStrId, + "9020", + 6); + } + else + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + trxdaughterboard->daughterCardId = ADI_BOARD_UNKNOWN; + strncpy((char *)trxdaughterboard->daughterCardName, + "Product Name:UNKNOWN; : ; : ; : ; : ; ", + ADI_BOARD_NAME_SIZE); + halError = ADI_HAL_I2C_FAIL; + } + + free(fru); +#endif + return (halError); +} + +/** +* \brief This function is a helper function to fill out the members of the +* devHalCfg structure with driver names for common platform. +* +* This function allows keeping the platform specific knowledge of driver names +* in this layer of code. Higher layers of code can call this to fill out the +* devHalCfg structure correctly for the common platform. +* +* Each device gets a unique instance of the devHalCfg structure describing the +* device resources for that device, such as the SPI chip select, etc. +* +* \param interfaceMask A mask that represents which platform interfaces are required by a particular device (SPI, Logging, etc) +* \param spiChipSelect The chip select index describing the particular device +* \param logFilename The filename of the logfile for this device. +*/ +void* hal_DevHalCfgCreate(uint32_t interfaceMask, + uint8_t spiChipSelect, + const char* logFilename) +{ + adi_hal_Cfg_t* halCfg = (adi_hal_Cfg_t*)calloc(1, + sizeof(adi_hal_Cfg_t)); + + if (halCfg == NULL) + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + return NULL; + } + + /* Disable all interfaces, and enable only if they are needed by the specific device */ + halCfg->spiCfg.interfaceEnabled = 0; + halCfg->logCfg.interfaceEnabled = 0; + halCfg->bbicCfg.interfaceEnabled = 0; + + /* If device requires SPI interface */ + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_SPI) > 0) + { + halCfg->spiCfg.interfaceEnabled = 1; + halCfg->spiCfg.chipSelectIndex = spiChipSelect; + + switch (spiChipSelect) + { + case SPI_CHIP_SELECT_0: + { + strncpy(halCfg->spiCfg.spidevName, + SPI_CHIP_DEV_PATH_0, + ADI_HAL_STRING_LENGTH); + break; + } + case SPI_CHIP_SELECT_1: + { + strncpy(halCfg->spiCfg.spidevName, + SPI_CHIP_DEV_PATH_1, + ADI_HAL_STRING_LENGTH); + break; + } + case SPI_CHIP_SELECT_2: + { + strncpy(halCfg->spiCfg.spidevName, + SPI_CHIP_DEV_PATH_2, + ADI_HAL_STRING_LENGTH); + break; + } + default: + { + free(halCfg); + return NULL; + } + } + + /* Default SPI settings */ + halCfg->spiCfg.autoIncAddrUp = 1; + halCfg->spiCfg.CPHA = 0; + halCfg->spiCfg.CPOL = 0; + halCfg->spiCfg.enSpiStreaming = 0; + halCfg->spiCfg.fourWireMode = 1; + halCfg->spiCfg.spiActionDisable = 0; + halCfg->spiCfg.spiClkFreq_Hz = 25000000; + } + + /* If device requires Logging interface */ + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_LOG) > 0) + { + halCfg->logCfg.interfaceEnabled = 1; + halCfg->logCfg.logLevel = ADI_HAL_LOG_ALL; + strncpy(halCfg->logCfg.logFileName, + logFilename, + ADI_HAL_STRING_LENGTH); + /* ensure null termination */ + halCfg->logCfg.logFileName[sizeof(halCfg->logCfg.logFileName) - 1] = '\0'; + } + + /* If device requires FPGA register interface */ + if (((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_BBICCTRL) > 0) || + ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_HWRESET) > 0)) /* ADS9 HWRESET interface requires BBICCTRL interface */ + { + halCfg->bbicCfg.interfaceEnabled = 1; + strncpy(halCfg->bbicCfg.coreRegsCfg.drvName, + BBIC_CORE_REG_PATH, + ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.coreRegsCfg.mapSize = MEM_SIZE_512MB; /* 512MB */ + strncpy(halCfg->bbicCfg.ramCfg.drvName, + BBIC_RAM_PATH, + ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.ramCfg.mapSize = MEM_SIZE_1GB; /* 1GB */ + strncpy(halCfg->bbicCfg.spiAdvRegsCfg.drvName, + BBIC_SPI_ADV_REG_PATH, + ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.spiAdvRegsCfg.mapSize = MEM_SIZE_16M; /* 16MB */ + } + + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_HWRESET) > 0) + { + halCfg->hwResetCfg.interfaceEnabled = 1; + + switch (spiChipSelect) + { + case SPI_CHIP_SELECT_0: + { + halCfg->hwResetCfg.resetPinIndex = 1; /* ADRV9025 reset pin bit position in FPGA register */ + break; + } + case SPI_CHIP_SELECT_1: + { + halCfg->hwResetCfg.resetPinIndex = 2; /* AD9528 reset pin bit position in FPGA register */ + break; + } + + default: + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + free(halCfg); + return NULL; + } + } + + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_I2C) > 0) + { + halCfg->i2cCfg.interfaceEnabled = 1; + strncpy(halCfg->i2cCfg.drvName, + I2C_EEPROM_PATH, + ADI_HAL_STRING_LENGTH); + } + + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_TIMER) > 0) + { + halCfg->timerCfg.interfaceEnabled = 1; + } + + return halCfg; +} + +int32_t adi_daughterboard_Discover(adi_motherboard_trx_t* trxMotherboard) +{ + int32_t error = ADI_COMMON_HAL_OK; + + /* Daughterboard Level */ + + if (trxMotherboard == NULL) + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + return (ADI_COMMON_HAL_GEN_SW); + } + + /* create hal layer for this daughterboard */ + trxMotherboard->daughterboards[0]->common.devHalInfo = hal_DevHalCfgCreate((ADI_HAL_INTERFACE_I2C |ADI_HAL_INTERFACE_LOG | ADI_HAL_INTERFACE_TIMER), SPI_CHIP_SELECT_0, "daughterBoard.txt"); + if (trxMotherboard->daughterboards[0]->common.devHalInfo == NULL) + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + return (ADI_COMMON_HAL_GEN_SW); + } + + trxMotherboard->daughterboards[0]->motherboardId = trxMotherboard->motherboardId; + + /* Identify the daughterboard */ + error = trx_BoardIdentify(trxMotherboard->daughterboards[0]); + if (error != ADI_HAL_OK) + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + return (ADI_COMMON_HAL_GEN_SW); + } + + /* Initializing structure operation pointers */ + trxMotherboard->daughterboards[0]->DeviceCreate = adi_daughterboard_Create; /* Create devices for daughter card, clock, and fpga */ + trxMotherboard->daughterboards[0]->DeviceInit = adi_daughterboard_Init; /* Initialize the HAL layer and bring up devices */ + trxMotherboard->daughterboards[0]->DeviceDestroy = adi_daughterboard_Destroy; /* Bring down, Close devices and free memory */ + trxMotherboard->daughterboards[0]->BoardProgram = adi_daughterboard_Program; + /* Start programming multiple devices on daughtercard and motherboard */ + trxMotherboard->daughterboards[0]->ClockConfigure = adi_daughterboard_ClockConfig; /* Configuring and initialize the clock device */ + trxMotherboard->daughterboards[0]->BoardJesdBringup = NULL; /* Configuring and initialize the FPGA device */ + trxMotherboard->daughterboards[0]->BoardProgramPhase1 = adi_daughterboard_ProgramPhase1; + /* Programming phase 1 for multiple devices on daughtercard and motherboard */ + trxMotherboard->daughterboards[0]->BoardProgramPhase2 = adi_daughterboard_ProgramPhase2; + /* Programming phase 2 for multiple devices on daughtercard and motherboard */ + trxMotherboard->daughterboards[0]->BoardDataInterfaceReset = adi_daughterboard_DataInterfaceReset; /* Resetting the data interface */ + + /* Saving motherboard pointer */ + trxMotherboard->daughterboards[0]->motherboardDevice = (uintptr_t) trxMotherboard; + + /* Create log file for daughterboard */ + if (adi_hal_HwOpen(trxMotherboard->daughterboards[0]->common.devHalInfo) != ADI_HAL_OK) + { + printf("Warning: %s:%u file open has failed.\n", __func__, __LINE__); + } + trxMotherboard->daughterboards[0]->common.error.logEnable = 1; + + /* Create board and platform */ + error = trxMotherboard->daughterboards[0]->DeviceCreate(trxMotherboard->daughterboards[0]); + if (error != ADI_COMMON_HAL_OK) + { + printf("ERROR: BoardCreate has failed.\n"); + return (error); + } + + /* Initializing board and platforms */ + error = trxMotherboard->daughterboards[0]->DeviceInit(trxMotherboard->daughterboards[0]); + if (error != ADI_COMMON_HAL_OK) + { + printf("ERROR: BoardInit has failed.\n"); + return (error); + } + + return (ADI_HAL_OK); +} + +adi_motherboard_trx_t* adi_platform_Discover(void) +{ + int32_t error = ADI_COMMON_HAL_OK; + /* Board Level */ + + /* Generic board dummy */ + adi_motherboard_trx_t* trxMotherboard = (adi_motherboard_trx_t*)calloc(1, + sizeof(adi_motherboard_trx_t)); + + if (trxMotherboard == NULL) + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + return (NULL); + } + trxMotherboard->initializedStatus = 0; + + /* Allocate daughterboard structure */ + trxMotherboard->daughterboards[0] = (adi_daughterboard_trx_t*)calloc(1, + sizeof(adi_daughterboard_trx_t)); + + if (trxMotherboard->daughterboards[0] == NULL) + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + free(trxMotherboard); + return (NULL); + } + + /* create hal layer for this motherboard */ + trxMotherboard->common.devHalInfo = hal_DevHalCfgCreate((ADI_HAL_INTERFACE_LOG | ADI_HAL_INTERFACE_TIMER), SPI_CHIP_SELECT_0, "platformLog.txt"); + if (trxMotherboard->common.devHalInfo == NULL) + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + free(trxMotherboard->daughterboards[0]); + free(trxMotherboard); + return (NULL); + } + + trxMotherboard->initializedStatus |= ADI_DEV_CFG_CREATED; + + /* Identify the platform (motherboard) */ + error = adi_platform_Identify(&trxMotherboard->motherboardId); + if (error != ADI_HAL_OK) + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + free(trxMotherboard->common.devHalInfo); + free(trxMotherboard->daughterboards[0]); + free(trxMotherboard); + return (NULL); + } + + /* Copy motherboard name */ + if (trxMotherboard->motherboardId == ADI_ADS9_PLATFORM) + { + strcpy((char *)trxMotherboard->motherboardName, + SYM2STR(ADI_ADS9_PLATFORM)); + } + else if (trxMotherboard->motherboardId == ADI_ADS8_PLATFORM) + { + strcpy((char *)trxMotherboard->motherboardName, + SYM2STR(ADI_ADS8_PLATFORM)); + } + + else + { + strcpy((char *)trxMotherboard->motherboardName, + SYM2STR(ADI_UNKNOWN_PLATFORM)); + } + + /* Motherboard is now known, set up the platform */ + + + error = adi_hal_PlatformSetup(trxMotherboard->common.devHalInfo, + (adi_hal_Platforms_e)trxMotherboard->motherboardId); + if (error != ADI_HAL_OK) + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + free(trxMotherboard->common.devHalInfo); + free(trxMotherboard->daughterboards[0]); + free(trxMotherboard); + return (NULL); + } + trxMotherboard->initializedStatus |= ADI_PLATFORM_CREATED; + + + /*Creating log file for the platform*/ + if (adi_hal_HwOpen(trxMotherboard->common.devHalInfo) != ADI_HAL_OK) + { + printf("Warning: %s:%u file open has failed.\n", __func__, __LINE__); + } + + trxMotherboard->common.error.logEnable = 1; + + return trxMotherboard; +} + +int32_t adi_motherboard_SaveInfo(adi_motherboard_trx_t* trxMotherboard, + uintptr_t saveData, + adrvtrx_data_save_t saveType) +{ + int32_t error = ADI_COMMON_HAL_OK; + + if ((trxMotherboard == NULL) || (trxMotherboard->daughterboards[0] == NULL)) + { + printf("ERROR: Motherboard pointer is NULL. %s:%u\n", + __func__, + __LINE__); + return (ADI_HAL_GEN_SW); + } + + /* Save the data in the structure */ + switch (saveType) + { + case TRX_PLATFORM_DATA_SAVE_TRX_DEVICE: + trxMotherboard->daughterboards[0]->trxDevice = saveData; + trxMotherboard->daughterboards[0]->boardAttribute |= TRX_DAUGHTERBOARD_ATTRIBUTE_PREALLOCATE_TRX_DEVICE; + break; + + case TRX_PLATFORM_DATA_SAVE_TRX_SETTING_INIT: + trxMotherboard->daughterboards[0]->daughterCardInit = saveData; + break; + + case TRX_PLATFORM_DATA_SAVE_TRX_SETTING_POST_MCS: + trxMotherboard->daughterboards[0]->postMcsInit = saveData; + break; + + case TRX_PLATFORM_DATA_SAVE_TRX_SETTING_PLATFORM_FILES: + trxMotherboard->daughterboards[0]->platformFilesInit = saveData; + break; + + case TRX_PLATFORM_DATA_SAVE_TRX_SETTING_PIN_MODE: + trxMotherboard->daughterboards[0]->pinModeSettings = saveData; + break; + + case TRX_PLATFORM_DATA_SAVE_CLOCK_SETTING_INIT: + trxMotherboard->daughterboards[0]->clockInit = saveData; + break; + + case TRX_PLATFORM_DATA_SAVE_FPGA_SETTING_INIT: + trxMotherboard->daughterboards[0]->fpgaInit = saveData; + break; + + case TRX_PLATFORM_DATA_SAVE_STREAM_SETTING_INIT: + trxMotherboard->daughterboards[0]->streamSettings = saveData; + break; + + default: + printf("ERROR: Unknown saving data type. %s:%u \n", + __func__, + __LINE__); + return (ADI_HAL_GEN_SW); + } + + return (error); +} + +int32_t adi_motherboard_Discover(adi_motherboard_trx_t** genericBoard) +{ + int32_t error = ADI_COMMON_HAL_OK; + adi_motherboard_trx_t* trxMotherboard = NULL; + int32_t compareFlag = 0; + + /* Create a device board */ + trxMotherboard = adi_platform_Discover(); + if (trxMotherboard == NULL) + { + error = ADI_HAL_GEN_SW; + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + return (error); + } + + compareFlag = adi_motherboard_Compare(*genericBoard, + trxMotherboard); + if (*genericBoard != NULL && compareFlag == ADI_TRUE) + { + /* The genericBoard parameter is the same as the existing configuration. + * Delete the local board and return. */ + error = adi_motherboard_Destroy(trxMotherboard); + return (error); + } + else if (*genericBoard != NULL && compareFlag == ADI_FALSE) + { + /* The genericBoard parameter was initialized for a different configuration. + * Delete the previous configuration and proceed with initializing the current. */ + adi_motherboard_Destroy(*genericBoard); + } + /* The last remaining case when genericBoard == NULL signifies the first initialization and + * should proceed with initializing normally. */ + + *genericBoard = trxMotherboard; + + /* Function pointer */ + trxMotherboard->Destroy = adi_motherboard_Destroy; + + return (ADI_COMMON_HAL_OK); +} + +int32_t adi_motherboard_Destroy(adi_motherboard_trx_t* trxMotherboard) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + if (trxMotherboard == NULL) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + /* bring down and free daughterboard */ + if (trxMotherboard->daughterboards[0] != NULL) + { + /* Bring down and free devices associated with duaghterboard */ + recoveryAction = trxMotherboard->daughterboards[0]->DeviceDestroy(trxMotherboard->daughterboards[0]); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + /* Free the daughterboard */ + free(trxMotherboard->daughterboards[0]); + trxMotherboard->daughterboards[0] = NULL; + } + + /* Now free the motherboard common device and structure */ + adi_hal_DevHalCfgFree((void *)trxMotherboard->common.devHalInfo); + free((void *)trxMotherboard); + trxMotherboard = NULL; + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/boards/motherboards/adi_motherboard_trx.h b/driver/rfic/rf/adrv9025/c_src/boards/motherboards/adi_motherboard_trx.h new file mode 100644 index 0000000..4ac0f54 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/motherboards/adi_motherboard_trx.h @@ -0,0 +1,105 @@ +#ifndef _ADI_MOTHERBOARD_TRX_H_ +#define _ADI_MOTHERBOARD_TRX_H_ + +#include "adi_motherboard_trx_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************** +* Runtime functions +**************************************************************************** +*/ +/** +* \brief This function is a helper function to fill out the members of the +* devHalCfg structure with driver names for common platform. +* +* This function allows keeping the platform specific knowledge of driver names +* in this layer of code. Higher layers of code can call this to fill out the +* devHalCfg structure correctly for the common platform. +* +* Each device gets a unique instance of the devHalCfg structure describing the +* device resources for that device, such as the SPI chip select, etc. +* +* \param interfaceMask A mask that represents which platform interfaces are required by a particular device (SPI, Logging, etc) +* \param spiChipSelect The chip select index describing the particular device +* \param logFilename The filename of the logfile for this device. +*/ +void* hal_DevHalCfgCreate(uint32_t interfaceMask, + uint8_t spiChipSelect, + const char* logFilename); + +/** +* \brief This function creates a structure to hold all the necessary information for daughter card +* +* \dep_begin +* \dep_end +* +* \param trxMotherboard Pointer to the generic structure +* +* \retval a pointer to the generic structure, null pointer if error occurs +*/ +int32_t adi_daughterboard_Discover(adi_motherboard_trx_t* trxMotherboard); + +/** +* \brief This function creates a generic structure to hold all the necessary information +* +* \dep_begin +* \dep_end +* +* \param trxMotherboard Pointer to the generic structure +* +* \retval ADI_HAL_GEN_SW Function could not completed +* \retval ADI_HAL_OK Function completed successfully, no action required +*/ +int32_t adi_motherboard_Discover(adi_motherboard_trx_t** trxMotherboard); + +/** +* \brief This function creates a generic structure to hold all the necessary information +* +* \dep_begin +* \dep_end +* +* \param trxMotherboard Pointer to the generic structure +* +* \retval ADI_HAL_GEN_SW Function could not completed +* \retval ADI_HAL_OK Function completed successfully, no action required +*/ +int32_t adi_motherboard_Discover(adi_motherboard_trx_t** trxMotherboard); + +/** +* \brief This function creates a generic structure to hold all the necessary information +* +* \dep_begin +* \dep_end +* +* \param trxMotherboard Pointer to the generic structure +* \param saveData Pointer to data to be save +* \param saveType initcates the type of data +* +* \retval ADI_HAL_GEN_SW Function could not completed +* \retval ADI_HAL_OK Function completed successfully, no action required +*/ +int32_t adi_motherboard_SaveInfo(adi_motherboard_trx_t* trxMotherboard, + uintptr_t saveData, + adrvtrx_data_save_t saveType); + +/** +* \brief This function destroy and clean up the motherboard structure +* +* \dep_begin +* \dep_end +* +* \param trxMotherboard Pointer to the generic structure +* +* \retval ADI_HAL_GEN_SW Function could not completed +* \retval ADI_HAL_OK Function completed successfully, no action required +*/ +int32_t adi_motherboard_Destroy(adi_motherboard_trx_t* trxMotherboard); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/boards/motherboards/adi_motherboard_trx_types.h b/driver/rfic/rf/adrv9025/c_src/boards/motherboards/adi_motherboard_trx_types.h new file mode 100644 index 0000000..081855e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/motherboards/adi_motherboard_trx_types.h @@ -0,0 +1,71 @@ +#ifndef _ADI_MOTHERBOARD_TRX_TYPES_H_ +#define _ADI_MOTHERBOARD_TRX_TYPES_H_ + +#include +#include "adi_common.h" +#include "adi_fmc_fru.h" +#include "adi_daughterboard_trx_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define ADI_MAX_DAUGHTERBOARDS 2 +#define ADI_BOARD_NAME_SIZE 64 + +typedef enum adrvtrx_data_save +{ + TRX_PLATFORM_DATA_SAVE_TRX_DEVICE = 1, + TRX_PLATFORM_DATA_SAVE_TRX_SETTING_INIT, + TRX_PLATFORM_DATA_SAVE_TRX_SETTING_POST_MCS, + TRX_PLATFORM_DATA_SAVE_TRX_SETTING_PLATFORM_FILES, + TRX_PLATFORM_DATA_SAVE_TRX_SETTING_PIN_MODE, + TRX_PLATFORM_DATA_SAVE_CLOCK_SETTING_INIT, + TRX_PLATFORM_DATA_SAVE_FPGA_SETTING_INIT, + TRX_PLATFORM_DATA_SAVE_STREAM_SETTING_INIT +} adrvtrx_data_save_t; + +typedef struct adi_daughterboard_trx adi_daughterboard_trx_t; +typedef struct adi_motherboard_trx adi_motherboard_trx_t; + +/** +* \brief Data structure to hold devices in an daughter card +*/ +typedef struct adi_motherboard_trx +{ + /* Common device */ + adi_common_Device_t common; /*!< Pointer to common device */ + + /* Initialization status */ + uint32_t initializedStatus; /*!< initialization status */ + + uint32_t motherboardId; /*!< The motherboard type i.e ADS8, ADS9 etc. */ + int8_t motherboardName[ADI_BOARD_NAME_SIZE]; /*!< Platform name string */ + + /* Array of daughter boards pointers */ + adi_daughterboard_trx_t* daughterboards[ADI_MAX_DAUGHTERBOARDS]; + + /* function pointers */ + /* Constructors and destructors */ + int32_t (*Create)(adi_motherboard_trx_t*); + + int32_t (*Destroy)(adi_motherboard_trx_t*); + + /* Programming functions */ + int32_t (*BoardProgram)(adi_motherboard_trx_t*); + + int32_t (*BoardJesdBringup)(adi_motherboard_trx_t*, + uint32_t , + uint32_t ); + + int32_t (*BoardProgramPhase1)(adi_motherboard_trx_t*); + + int32_t (*BoardProgramPhase2)(adi_motherboard_trx_t*); +} adi_motherboard_trx_t; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/boards/motherboards/makefile b/driver/rfic/rf/adrv9025/c_src/boards/motherboards/makefile new file mode 100644 index 0000000..21793b6 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/boards/motherboards/makefile @@ -0,0 +1,21 @@ +LIBADI_MOTHERBOARD = libadi_motherboard.a +CC = gcc +ARFLAGS = -rv +CFLAGS = -Wall -Werror -I ../daughterboards -I ../../platforms -I ../../platforms/platform_utils -I ../../common/ -I ../../common/adi_error -I ../../common/adi_logging -I../../common/adi_hal +EXT = c + +SRC = $(wildcard *.$(EXT)) + +OBJS = $(SRC:.$(EXT)=.o) + +all: $(SRC) $(LIBADI_MOTHERBOARD) + +.$(EXT).o: + $(CC) $(CFLAGS) -o $@ -c $< + +$(LIBADI_MOTHERBOARD): $(OBJS) + ar $(ARFLAGS) $(LIBADI_MOTHERBOARD) $(OBJS) + +clean: + rm -rf *.o + rm -rf *.a diff --git a/driver/rfic/rf/adrv9025/c_src/common/adi_common.h b/driver/rfic/rf/adrv9025/c_src/common/adi_common.h new file mode 100644 index 0000000..9bdf89d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/common/adi_common.h @@ -0,0 +1,23 @@ +/** +* \file adi_common.h +* \brief Contains ADI common interface. +* +* ADI common lib Version: 0.0.1.1 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_COMMON_H_ +#define _ADI_COMMON_H_ + +#include "adi_common_error.h" +#include "adi_common_hal.h" +#include "adi_common_log.h" +#include "adi_common_types.h" +#include "adi_common_user.h" + +#endif /* _ADI_COMMON_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/common/adi_common_macros.h b/driver/rfic/rf/adrv9025/c_src/common/adi_common_macros.h new file mode 100644 index 0000000..114675e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/common/adi_common_macros.h @@ -0,0 +1,46 @@ +/** +* \file adi_common_macros.h +* \brief Contains ADI Transceiver general purpose macros. +* +* ADI common lib Version: 0.0.1.1 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_COMMON_MACROS_H_ +#define _ADI_COMMON_MACROS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADI_HARDRESET 1U +#define ADI_SOFTRESET 0U + +#define ADI_TRUE 1U +#define ADI_FALSE 0U + +#define ADI_ENABLE 1U +#define ADI_DISABLE 0U + +#define ADI_ON 1U +#define ADI_OFF 0U + +#define ADI_SUCCESS 1U +#define ADI_FAILURE 0U + +#define ADI_COMMON_VERBOSE 1 +#define ADI_COMMON_VARIABLE_USAGE 1 +#define ADI_MAX_PATH 100 +#define ADI_MAX_ERR_STR 150 +#define ADI_ITER_BEGIN 0 +#define ADI_ITER_END UINT32_MAX + +#ifdef __cplusplus +} +#endif +#endif /* _ADI_COMMON_MACROS_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/common/adi_common_types.h b/driver/rfic/rf/adrv9025/c_src/common/adi_common_types.h new file mode 100644 index 0000000..1454f3f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/common/adi_common_types.h @@ -0,0 +1,41 @@ +/** +* \file adi_common_types.h +* \brief Contains ADI common types. +* +* ADI common lib Version: 0.0.1.1 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_COMMON_TYPES_H_ +#define _ADI_COMMON_TYPES_H_ + +#include "adi_common_error_types.h" +#include "adi_common_hal_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief ADI common device structure +*/ +typedef struct adi_common_Device +{ + void *devHalInfo; /*!< ADI_HAL Hardware layer settings pointer specific to this ADRV9025 instance */ + adi_common_ErrStruct_t error; + adi_common_Cache_t cacheInfo; /*!< TODO: add description */ + /* function pointer for datapacking or device specific hal */ +} adi_common_Device_t; + +typedef uint32_t adi_iter_t; + +#ifdef __cplusplus +} +#endif +#endif /* _ADI_COMMON_TYPES_H_ */ + diff --git a/driver/rfic/rf/adrv9025/c_src/common/adi_common_user.h b/driver/rfic/rf/adrv9025/c_src/common/adi_common_user.h new file mode 100644 index 0000000..23101a8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/common/adi_common_user.h @@ -0,0 +1,39 @@ +/** +* \file adi_common_user.h +* +* User modifiable defines +* +* \brief Contains ADI Transceiver common hal types. +* +* ADI common lib Version: 0.0.1.1 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_COMMON_USER_H_ +#define _ADI_COMMON_USER_H_ + +/* Includes that user can modify with their own libraries as long as the function prototypes matches */ +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ADI_COMMON_HAL_SPIARRAYSIZE + #define ADI_COMMON_HAL_SPIARRAYSIZE 256 +#endif + +#ifdef __cplusplus +} +#endif +#endif /* _ADI_COMMON_USER_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/common/adi_error/adi_common_error.c b/driver/rfic/rf/adrv9025/c_src/common/adi_error/adi_common_error.c new file mode 100644 index 0000000..3f690c7 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/common/adi_error/adi_common_error.c @@ -0,0 +1,124 @@ +/** + * \file adi_common_error.c + * \brief Contains common API error handling functions implementations + * + * These functions are public to the customer for getting more details on + * errors and debugging. + * + * ADI common lib Version: 0.0.1.1 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_common_error.h" +#include "adi_common_log.h" +#include "adi_platform.h" +#include + +void adi_common_ErrorReport(adi_common_Device_t* commonDev, + adi_common_ErrSources_e errSrc, + int32_t detErr, + int32_t actionToRecover, + const char* fileName, + const char* funcName, + uint32_t lineNum, + const char* varName, + const char* customError) +{ + int32_t actionReport = actionToRecover; + int32_t lastAction = ADI_COMMON_ACT_NO_ACTION; + adi_common_ErrStruct_t localSave; + + /* Check errorPtr pointer is not null */ + if (commonDev != NULL) + { + /* Check if error is an actual error */ + if (detErr > ADI_COMMON_ERR_OK) + { + /* Check if the action to recover is a warning or action */ + if (actionReport != ADI_COMMON_ACT_NO_ACTION) + { + /* Check if the action to recover is of more importance than the current action + * Warnings are always of a lower importance than actions. + * if warning then the API is design not to termintate execution see + * IF_ERROR_RETURN macro + */ + if ((actionReport > commonDev->error.newAction) && (commonDev->error.newAction != ADI_COMMON_ACT_NO_ACTION)) + { + /* log the error that has called this function and keep previous error in the error structure */ + localSave.errormessage = customError; + localSave.errFile = fileName; + localSave.errFunc = funcName; + localSave.errLine = lineNum; + localSave.errCode = detErr; + localSave.errSource = errSrc; + localSave.varName = varName; + localSave.newAction = actionReport; + + if (commonDev->error.logEnable == ADI_ENABLE) + { + ADI_ERROR_LOG(commonDev, + localSave); + } + } + else + { + /* Assign detected action and error to the errors structure */ + commonDev->error.errSource = errSrc; + commonDev->error.errCode = detErr; + commonDev->error.errLine = lineNum; + commonDev->error.errFunc = funcName; + commonDev->error.errFile = fileName; + commonDev->error.varName = varName; + commonDev->error.errormessage = customError; + commonDev->error.lastAction = commonDev->error.newAction; + commonDev->error.newAction = actionToRecover; // daya debug abort + printf("commonDev abort \n"); // daya debug + + if (commonDev->error.logEnable == ADI_ENABLE) + { + ADI_ERROR_LOG(commonDev, + commonDev->error); + } + } + } + else /* actionReport == ADI_COMMON_ACT_NO_ACTION */ + { + /* Clear error and pass it to the previous action */ + if (commonDev->error.newAction != ADI_COMMON_ACT_NO_ACTION) + { + lastAction = commonDev->error.newAction; + adi_common_ErrorClear(commonDev); + commonDev->error.lastAction = lastAction; + } + } + } + } +} + +int32_t adi_common_ErrorClear(adi_common_Device_t* commonDev) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(commonDev); + + ADI_FUNCTION_ENTRY_LOG(commonDev, + ADI_COMMON_LOG_API); + + commonDev->error.errSource = 0; + commonDev->error.errCode = 0; + commonDev->error.errLine = 0; + commonDev->error.errFunc = ""; + commonDev->error.errFile = ""; + commonDev->error.varName = ""; + commonDev->error.errormessage = ""; + commonDev->error.lastAction = 0; + commonDev->error.newAction = 0; + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/common/adi_error/adi_common_error.h b/driver/rfic/rf/adrv9025/c_src/common/adi_error/adi_common_error.h new file mode 100644 index 0000000..3d3f108 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/common/adi_error/adi_common_error.h @@ -0,0 +1,191 @@ +/** + * \file adi_common_error.h + * \brief Contains Common API error handling function prototypes and macros + * that will be used by the API and will call functions in adi_common_error.c + * + * These functions are public to the customer for getting more details on + * errors and debugging. + * +* ADI common lib Version: 0.0.1.1 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_COMMON_ERROR_H_ +#define _ADI_COMMON_ERROR_H_ + +#include +#include "adi_common_error_types.h" +#include "adi_common_types.h" +#include "adi_common_macros.h" + +/* +* ******************************* +* ADI Common error macros +* ******************************* +*/ + +/** +* \brief Macro to check if device pointer is a valid pointer +* if null pointer detected return ADI_COMMON_ACT_ERR_CHECK_PARAM action +* +* \param ptr Pointer to be checked +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM +*/ +#define ADI_NULL_DEVICE_PTR_RETURN(ptr)\ +if(ptr == NULL)\ +{ \ + return ADI_COMMON_ACT_ERR_CHECK_PARAM; \ +} + +/** +* \brief Macro to check if a pointer is a valid pointer +* This macro upon detection of a null pointer will report the error and +* return ADI_COMMON_ACT_ERR_CHECK_PARAM action +* +* \param devHalInfo pointer to the hal layer to use logging +* \param errorPtr Pointer to the error data structure +* \param ptr Pointer to be checked +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM +*/ +#define ADI_NULL_PTR_RETURN(commonDev, ptr)\ +{ \ + if(ptr == NULL) \ + { \ + ADI_ERROR_REPORT(commonDev, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_NULL_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, ptr, "NULL Pointer passed"); \ + return ADI_COMMON_ACT_ERR_CHECK_PARAM; \ + } \ +} + +/** +* \brief Macro to check if return from AI function is needed +* +* \param a Action to be checked +* +* \retval Action passed +*/ +#define ADI_ERROR_RETURN(a) if(a < ADI_COMMON_ACT_NO_ACTION) { printf("ERR RETURN: %s %d %s\n", __FILE__, __LINE__, __func__); return a; } + +/** +* \brief Macro to close a file and return if an error is detected +* +* \param1 an Action to be checked +* \param2 the file to close +* +* \retval Action passed +*/ +#define ADI_ERROR_CLOSE_RETURN(action, fileToClose) if(action < ADI_COMMON_ACT_NO_ACTION) {(void)fclose(fileToClose); return action;} + +#if ADI_COMMON_VERBOSE > 0 +#if ADI_COMMON_VARIABLE_USAGE > 0 +/* +* Macro to print variable name as a string, used in Error reporting facility +*/ +#ifndef GET_VARIABLE_NAME +#define GET_VARIABLE_NAME(Variable) (#Variable) +#endif +#else +#ifndef GET_VARIABLE_NAME + #define GET_VARIABLE_NAME(Variable) ("") +#endif +#endif /* ADI_COMMON_VARIABLE_USAGE */ + +/** +* \brief Macro to perform error reporting +* This macro will call adi_common_ErrorReport and extract the +* necessary information from the API function using the preprocessors: +* __FILE__ will represent the full path of the current API function file where the error happened, +* __FUNCTION__ will expand to the name of the function in the API where the error was produced, +* __LINE__ theis preprocessor macro expands to the line number inside the API function where the error happened. +* +* +* \param devHalInfo pointer to the hal layer to use logging +* \param errorPtr Pointer to the error data structure +* \param errorSource Error source of error code of type enum adi_common_ErrSources_e +* \param error Detected error +* \param action Action to recover from +* \param fileName file name of the file where the error was detected +* \param funcName function name of the function where the error was detected +* \param lineNum line number of where the error was detected +* \param variable variable name that had the error,GET_VARIABLE_NAME(variable) will print the variable name that needs to be checked, this can be NULL and it will mean that there is an error not depending on a variable only +* \param customError error message to be written to the struct +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM +*/ +#define ADI_ERROR_REPORT(commonDev, errorSource, error, action, variable, customError) \ + adi_common_ErrorReport(commonDev, (adi_common_ErrSources_e)errorSource, (int32_t)error, (int32_t)action, __FILE__, __FUNCTION__, __LINE__, GET_VARIABLE_NAME(variable), customError) + +#else +#define ADI_ERROR_REPORT(commonDev, errorSource, error, action, variable, customError) \ + adi_common_ErrorReport(commonDev, (adi_common_ErrSources_e)errorSource, (int32_t)error, (int32_t)action, "", "", __LINE__, "", "") +#endif /* ADI_COMMON_VERBOSE */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* +* ******************************* +* ADI Common error functions +* ******************************* +*/ + +/** + * \brief Common API error reporting facility + * + * Error handling to assign actions: + * If actionToRecover is ADI_COMMON_ACT_NO_ACTION then nothing gets logged or reported, if the previous new action in the error structure + * is different to ADI_COMMON_ACT_NO_ACTION the error struct will be cleared and then the previous action will be stored in the lastAction + * member. + * + * If not ADI_COMMON_ACT_NO_ACTION then check latest action previously logged in the error structure and verify if the new found action + * is of a higher priority level than the last error in the structure, + * If it is then we need to demote the error.newAction and log the previous action again + * demoting is done by assign it to error.lastAction. + * If action is a warning then it gets logged and assigned to the error structure the same way as the error action, if an error + * action occurs after a warning the warning will be demoted and could be accessed through error.lastAction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param commonDev pointer to adi_common_Device_t + * \param errSrc Error source of error code of type enum adi_common_ErrSources_e + * \param detErr Detected error + * \param actionToRecover Action to recover from + * \param fileName file name of the file where the error was detected + * \param funcName function name of the function where the error was detected + * \param lineNum line number of where the error was detected + * \param varName variable name that had the error, this can be NULL and it will mean that there is an error not depending on a variable only + * \param customError error message to be written to the struct + */ +void adi_common_ErrorReport(adi_common_Device_t* commonDev, + adi_common_ErrSources_e errSrc, + int32_t detErr, + int32_t actionToRecover, + const char* fileName, + const char* funcName, + uint32_t lineNum, + const char* varName, + const char* customError); + +/** + * \brief Function to clear existing error + * + * \param commonDev pointer to adi_common_Device_t + * + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_common_ErrorClear(adi_common_Device_t* commonDev); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_COMMON_ERROR_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/common/adi_error/adi_common_error_types.h b/driver/rfic/rf/adrv9025/c_src/common/adi_error/adi_common_error_types.h new file mode 100644 index 0000000..e714175 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/common/adi_error/adi_common_error_types.h @@ -0,0 +1,113 @@ +/** +* \file adi_common_error_types.h +* \brief Contains common error data types for API Error messaging +* +* ADI common lib Version: 0.0.1.1 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_COMMON_ERROR_TYPES_H_ +#define _ADI_COMMON_ERROR_TYPES_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief ADI common error structure +*/ +typedef struct adi_common_ErrStruct +{ + int32_t errSource; /*!< Current source of error returned */ + int32_t errCode; /*!< Current error code returned */ + uint32_t errLine; /*!< Line of the source code where the error was returned */ + const char* errFunc; /*!< Function name where the error occurred */ + const char* errFile; /*!< File name where the error occurred */ + const char* varName; /*!< Variable name which has the error */ + const char* errormessage; /*!< Error message to describe the error */ + int32_t lastAction; /*!< Previous action detected */ + int32_t newAction; /*!< Current action detected */ + uint8_t logEnable; /*!< Log errors enable flag */ +} adi_common_ErrStruct_t; + +/** +* \brief Unique Common error sources for Common layer. +* +** Common error sources will be given the following range: 0x0000 - 0x0FFF +* Specific error sources for different devices/boards will be given the following range: +* Devices 0xd000 - 0xdFFF where d is the device number +* +* TODO: replace by unique error source +* Shall this become common layer: +* -HAL +* -COMMON +* -DEVICE +* -BF +* -API +*/ +typedef enum adi_common_ErrSources +{ + ADI_COMMON_ERRSRC_API, /*!< Error detected in API */ + ADI_COMMON_ERRSRC_ADI_HAL, /*!< ADI HAL Error Src: Error codes defined by adi_common_hal_Err_e */ + ADI_COMMON_ERRSRC_DEVICEBF, /*!< ADI BitField Error Src: Error codes defined by adrv9025_BF_Err_t */ + ADI_COMMON_ERRSRC_DEVICEHAL /*!< ADI Device HAL Error Src: Error codes defined in device error extension */ +} adi_common_ErrSources_e; + +/** +* \brief Unique Error source for common layer +* this needs to be extended by the device specific source code files +* +* Common error sources will be given the following range: 0x0000 - 0x0FFF +* Specific error sources for different devices/boards will be given the following range: +* Devices 0xd000 - 0xdFFF where d is the device number +*/ +#define ADI_COMMON_SRC_ERROR 0x0001 /*!< Error detected in adi_common_error.c */ +#define ADI_COMMON_SRC_LOG 0x0002 /*!< Error detected in adi_common_log.c */ +#define ADI_COMMON_SRC_HAL 0x0003 /*!< Error detected in adi_common_hal.c */ + +/** +* \brief Unique Common error codes for API. +* Each error condition in the library shall have its own value +* to ease debug of errors. +* +* Common error codes will be given the following range: 0x0000 - 0x0FFF +* Specific error codes for different devices/boards will be given the following range: +* Devices 0xd000 - 0xdFFF where d is the device number +*/ +#define ADI_COMMON_ERR_OK 0x0000 /*!< No error detected */ +#define ADI_COMMON_ERR_INV_PARAM 0x0001 /*!< Invalid parameter detected in function */ +#define ADI_COMMON_ERR_NULL_PARAM 0x0002 /*!< Null parameter detected in function */ +#define ADI_COMMON_ERR_API_FAIL 0x0003 /*!< Error detected in API function */ +#define ADI_COMMON_ERR_SPI_FAIL 0x0004 /*!< SPI interface error detected */ +#define ADI_COMMON_ERR_CPU_EXCEPTION 0x0008 /*!< CPU exception detected */ + +/** +* \brief list of Common Recovery Actions used as return values from APIs. +* More information about the action is given in the error structure at run time +* Actions are divided into: +* Errors are negative, they indicate that an action shall be taken in order to continue the normal operation of the device +* Warnings are positive, they done break the normal operation of the device, they indicate that at some stage an action should be taken +*/ +#define ADI_COMMON_ACT_WARN_CHECK_PARAM (3) /*!< API OK - Parameter exceeds the range of values allowed */ +#define ADI_COMMON_ACT_WARN_RERUN_FEATURE (2) /*!< API OK - Rerun feature */ +#define ADI_COMMON_ACT_WARN_RESET_LOG (1) /*!< API OK - LOG Not working */ +#define ADI_COMMON_ACT_NO_ACTION (0) /*!< API OK - NO ACTION REQUIRED */ +#define ADI_COMMON_ACT_ERR_CHECK_TIMER (-1) /*!< API OK - timer not working */ +#define ADI_COMMON_ACT_ERR_CHECK_PARAM (-2) /*!< API OK - INVALID PARAM */ +#define ADI_COMMON_ACT_ERR_RESET_INTERFACE (-3) /*!< API NG - Interface Not Working */ +#define ADI_COMMON_ACT_ERR_RESET_FEATURE (-4) /*!< API NG - Reset feature */ +#define ADI_COMMON_ACT_ERR_RESET_MODULE (-5) /*!< API NG - Module Not working */ +#define ADI_COMMON_ACT_ERR_RESET_FULL (-6) /*!< API NG - FULL RESET REQUIRED */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_COMMON_ERROR_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/common/adi_hal/adi_common_hal.c b/driver/rfic/rf/adrv9025/c_src/common/adi_hal/adi_common_hal.c new file mode 100644 index 0000000..a9f07c2 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/common/adi_hal/adi_common_hal.c @@ -0,0 +1,180 @@ +/** +* \file adi_common_hal.c +* \brief Contains ADI Transceiver Hardware Abstraction functions +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +* +* ADI common lib Version: 0.0.1.1 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +/* Common HAL layer maintained by Analog Devices */ +#include "adi_common_hal.h" +#include "adi_common_error_types.h" +#include "adi_platform.h" + +int32_t adi_common_hal_HwOpen(adi_common_Device_t *commonDev) +{ + int32_t halError = (int32_t)ADI_COMMON_HAL_OK; + + if (commonDev == NULL) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + else + { + halError = adi_hal_HwOpen(commonDev->devHalInfo); + } + + if (halError != (int32_t)ADI_COMMON_HAL_OK) + { + /* Report error in this layer */ + ADI_ERROR_REPORT(commonDev, + ADI_COMMON_SRC_HAL, + halError, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Hardware can not be opened"); + } + + return commonDev->error.newAction; +} + +int32_t adi_common_hal_HwClose(adi_common_Device_t *commonDev) +{ + int32_t halError = (int32_t)ADI_COMMON_HAL_OK; + + if (commonDev == NULL) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + else + { + halError = adi_hal_HwClose(commonDev->devHalInfo); + } + + if (halError != (int32_t)ADI_COMMON_HAL_OK) + { + /* Report error in this layer */ + ADI_ERROR_REPORT(commonDev, + ADI_COMMON_SRC_HAL, + halError, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Hardware can not be closed"); + } + + return commonDev->error.newAction; +} + +int32_t adi_common_hal_HwReset(adi_common_Device_t *commonDev, uint8_t pinLevel) +{ + int32_t halError = (int32_t)ADI_COMMON_HAL_OK; + + if (commonDev == NULL) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + else + { + halError = adi_hal_HwReset(commonDev->devHalInfo, pinLevel); + } + + if (halError != (int32_t)ADI_COMMON_HAL_OK) + { + /* Report error in this layer */ + ADI_ERROR_REPORT(commonDev, + ADI_COMMON_SRC_HAL, + halError, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Hardware can not be opened"); + } + + return commonDev->error.newAction; +} + +int32_t adi_common_hal_Wait_us(adi_common_Device_t *commonDev, uint32_t time_us) +{ + int32_t halError = (int32_t)ADI_COMMON_HAL_OK; + + if (commonDev == NULL) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + else + { + halError = adi_hal_Wait_us(commonDev->devHalInfo, time_us); + } + + if (halError != (int32_t)ADI_COMMON_HAL_OK) + { + /* Report error in this layer */ + ADI_ERROR_REPORT(commonDev, + ADI_COMMON_SRC_HAL, + halError, + ADI_COMMON_ACT_ERR_CHECK_TIMER, + NULL, + "Wait function failed"); + } + + return commonDev->error.newAction; +} + +int32_t adi_common_hal_Wait_ms(adi_common_Device_t *commonDev, uint32_t time_ms) +{ + int32_t halError = (int32_t)ADI_COMMON_HAL_OK; + + if (commonDev == NULL) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + else + { + halError = adi_hal_Wait_us(commonDev->devHalInfo, time_ms * 1000); + } + + if (halError != (int32_t)ADI_COMMON_HAL_OK) + { + /* Report error in this layer */ + ADI_ERROR_REPORT(commonDev, + ADI_COMMON_SRC_HAL, + halError, + ADI_COMMON_ACT_ERR_CHECK_TIMER, + NULL, + "Wait function failed"); + } + + return commonDev->error.newAction; +} + +int32_t adi_common_hal_HwVerify(adi_common_Device_t *commonDev) +{ + int32_t halError = (int32_t)ADI_COMMON_HAL_OK; + if (commonDev == NULL) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + else + { + halError = adi_hal_HwVerify(commonDev->devHalInfo); + } + + if (halError != (int32_t)ADI_COMMON_HAL_OK) + { + /* Report error in this layer */ + ADI_ERROR_REPORT(commonDev, + ADI_COMMON_SRC_HAL, + halError, + ADI_COMMON_HAL_LIBRARY_NOT_AVAILABLE, + NULL, + "ERROR hardware verify failed"); + } + + return commonDev->error.newAction; +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/common/adi_hal/adi_common_hal.h b/driver/rfic/rf/adrv9025/c_src/common/adi_hal/adi_common_hal.h new file mode 100644 index 0000000..108035b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/common/adi_hal/adi_common_hal.h @@ -0,0 +1,129 @@ +/** + * \file adi_common_hal.h + * \brief Contains ADI Hardware Abstraction layer function prototypes and type definitions for adi_common_hal.c + * + * ADI common lib Version: 0.0.1.1 + */ + + /** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_COMMON_HAL_H_ +#define _ADI_COMMON_HAL_H_ + +/* include standard types and definitions */ +#include +#include "adi_common_log.h" + + + +/*======================================== + * Prototypes + *=======================================*/ +#ifdef __cplusplus +extern "C" { +#endif + +/*============================================================================ + * ADI Device Hardware Control Functions +*===========================================================================*/ + +/** +* \brief Used to initialise the HAL hardware. +* +* \dep_begin +* \dep{device->common} +* \dep_end +* +* \param commonDev Pointer to the common structure of type adi_common_Device_t +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_common_hal_HwOpen(adi_common_Device_t *commonDev); + +/** +* \brief Used to close the HAL hardware. +* +* \dep_begin +* \dep{device->common} +* \dep_end +* +* \param commonDev Pointer to the common structure of type adi_common_Device_t +* +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_common_hal_HwClose(adi_common_Device_t *commonDev); + +/** +* \brief Used to reset the HAL hardware. +* +* \dep_begin +* \dep{device->common} +* \dep_end +* +* \param commonDev Pointer to the common structure of type adi_common_Device_t +* \param pinLevel Pin level to be set 1 will held the reset line high, 0 will held the reset line low +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_common_hal_HwReset(adi_common_Device_t *commonDev, uint8_t pinLevel); + +/** +* \brief Used to sleep for a given number of microSeconds. +* +* \dep_begin +* \dep{device->common} +* \dep_end +* +* \param commonDev Pointer to the common structure of type adi_common_Device_t +* \param time_us The number of micro seconds to sleep +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_common_hal_Wait_us(adi_common_Device_t *commonDev, uint32_t time_us); + +/** +* \brief Used to sleep for a given number of milliSeconds. +* +* \dep_begin +* \dep{device->common} +* \dep_end +* +* \param commonDev Pointer to the common structure of type adi_common_Device_t +* \param time_ms The number of milli seconds to sleep. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_common_hal_Wait_ms(adi_common_Device_t *commonDev, uint32_t time_ms); + +/** +* \brief A helper function used to check that hardware is available to read from or write to. +* +* \dep_begin +* \dep{device->common} +* \dep_end +* +* \param commonDev Pointer to the common structure of type adi_common_Device_t +* +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_common_hal_HwVerify(adi_common_Device_t *commonDev); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/common/adi_hal/adi_common_hal_types.h b/driver/rfic/rf/adrv9025/c_src/common/adi_hal/adi_common_hal_types.h new file mode 100644 index 0000000..3c9a1b7 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/common/adi_hal/adi_common_hal_types.h @@ -0,0 +1,66 @@ +/** +* \file adi_common_hal_types.h +* \brief Contains ADI Transceiver common hal types. +* +* ADI common lib Version: 0.0.1.1 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_COMMON_HAL_TYPES_H_ +#define _ADI_COMMON_HAL_TYPES_H_ + +#include +#include "adi_common_user.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Enum of possible Errors Detected by HAL layer to be communicated +* to ADI APIs. +*/ +typedef enum adi_common_hal_Err +{ + ADI_COMMON_HAL_OK = 0, /*!< HAL function successful. No error Detected */ + ADI_COMMON_HAL_SPI_FAIL, /*!< HAL SPI operation failure. SPI controller Down */ + ADI_COMMON_HAL_GPIO_FAIL, /*!< HAL GPIO function Failure */ + ADI_COMMON_HAL_TIMER_FAIL, /*!< HAL Timer function Failure */ + ADI_COMMON_HAL_LOGGING_FAIL, /*!< HAL Logging function Failure */ + ADI_COMMON_HAL_LOGGGING_LEVEL_FAIL, /*!< HAL Logging level Failure */ + ADI_COMMON_HAL_WAIT_TIMEOUT, /*!< HAL function Timeout */ + ADI_COMMON_HAL_GEN_SW, /*!< HAL function failed due to general invalid HAL data*/ + ADI_COMMON_HAL_FUNCTION_NOT_IMP, /*!< HAL function error, not implemented in HAL layer */ + ADI_COMMON_HAL_LIBRARY_NOT_AVAILABLE, /*!< HAL function error, HAL layer library not found or available in this build */ + ADI_COMMON_HAL_WARNING, /*!< HAL function warning that non critical error was detected*/ + ADI_COMMON_HAL_FPGA_FAIL /*!< FPGA hal function failure */ +} adi_common_hal_Err_e; + +/** +* \brief Data structure to hold cache device settings +*/ +typedef struct adi_common_Cache +{ + uint16_t wrCacheIdx; /*! + +void adi_common_LogWrite(adi_common_Device_t* commonDev, + adi_common_LogLevel_e logLevel, + const char* comment, + ...) +{ + int32_t halError = (int32_t)ADI_COMMON_HAL_OK; + uint8_t logStatus = commonDev->error.logEnable; + + if (commonDev->devHalInfo == NULL) + { + halError = ADI_COMMON_HAL_GEN_SW; + } + else + { + va_list argp; + va_start(argp, + comment); + halError = adi_hal_LogWrite(commonDev->devHalInfo, + (int32_t)logLevel, + comment, + argp); + va_end(argp); + } + + if (halError != (int32_t)ADI_COMMON_HAL_OK) + { + /* reentrant function call, ADI_ERROR_REPORT calls adi_common_LogWrite + * At this point we should disable logging as it is not available, but keep reporting errors/warnings + * + * Todo: + * LogLevel should be set to NONE + * LogLevel should be reset to the particular level once the HAL layer is reset or fixed + * + * Figure out when to re-enable commonDev->error.logEnable + * + * Read state of log enable and restore it + */ + commonDev->error.logEnable = ADI_DISABLE; + ADI_ERROR_REPORT(commonDev, + ADI_COMMON_SRC_LOG, + halError, + ADI_COMMON_ACT_WARN_RESET_LOG, + NULL, + "Logging failure"); + commonDev->error.logEnable = logStatus; + } +} + +void adi_common_LogLevelSet(adi_common_Device_t* commonDev, + int32_t halLogLevel) +{ + int32_t halError = (int32_t)ADI_COMMON_HAL_OK; + + if (commonDev->devHalInfo == NULL) + { + halError = (int32_t)ADI_COMMON_HAL_GEN_SW; + } + else + { + halError = adi_hal_LogLevelSet(commonDev->devHalInfo, + halLogLevel); + } + + if (halError != (int32_t)ADI_COMMON_HAL_OK) + { + ADI_ERROR_REPORT(commonDev, + ADI_COMMON_SRC_LOG, + halError, + ADI_COMMON_ACT_WARN_RESET_LOG, + NULL, + "Log level set error"); + } +} + +void adi_common_LogLevelGet(adi_common_Device_t* commonDev, + int32_t* halLogLevel) +{ + int32_t halError = (int32_t)ADI_COMMON_HAL_OK; + + if ((commonDev->devHalInfo == NULL) || (halLogLevel == NULL)) + { + halError = (int32_t)ADI_COMMON_HAL_GEN_SW; + } + else + { + halError = adi_hal_LogLevelGet(commonDev->devHalInfo, + halLogLevel); + } + + if (halError != (int32_t)ADI_COMMON_HAL_OK) + { + ADI_ERROR_REPORT(commonDev, + ADI_COMMON_SRC_LOG, + halError, + ADI_COMMON_ACT_WARN_RESET_LOG, + NULL, + "Log level get error"); + } +} + +int32_t adi_common_LogFileOpen(adi_common_Device_t* commonDev, + char* fileName) +{ + int32_t halError = (int32_t)ADI_COMMON_HAL_OK; + + if (commonDev->devHalInfo == NULL) + { + halError = (int32_t)ADI_COMMON_HAL_GEN_SW; + } + else + { + halError = adi_hal_LogFileOpen(commonDev->devHalInfo, + fileName); + } + + if (halError != (int32_t)ADI_COMMON_HAL_OK) + { + ADI_ERROR_REPORT(commonDev, + ADI_COMMON_SRC_LOG, + halError, + ADI_COMMON_ACT_WARN_RESET_LOG, + NULL, + "Log file Open error"); + } + + return commonDev->error.newAction; +} + +int32_t adi_common_LogFileClose(adi_common_Device_t* commonDev) +{ + int32_t halError = (int32_t)ADI_COMMON_HAL_OK; + + if (commonDev->devHalInfo == NULL) + { + halError = (int32_t)ADI_COMMON_HAL_GEN_SW; + } + else + { + halError = adi_hal_LogFileClose(commonDev->devHalInfo); + } + + if (halError != (int32_t)ADI_COMMON_HAL_OK) + { + ADI_ERROR_REPORT(commonDev, + ADI_COMMON_SRC_LOG, + halError, + ADI_COMMON_ACT_WARN_RESET_LOG, + NULL, + "Log file Close error"); + } + + return commonDev->error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/common/adi_logging/adi_common_log.h b/driver/rfic/rf/adrv9025/c_src/common/adi_logging/adi_common_log.h new file mode 100644 index 0000000..4e9f593 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/common/adi_logging/adi_common_log.h @@ -0,0 +1,173 @@ +/** +* \file adi_common_log.h +* \brief Contains ADI Hardware Abstraction layer function prototypes and type definitions for adi_common_log.c +* +* ADI common lib Version: 0.0.1.1 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADI API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_COMMON_LOG_H_ +#define _ADI_COMMON_LOG_H_ + +#include +#include "adi_common_log_types.h" +#include "adi_common_macros.h" +#include "adi_common_error.h" +#include "adi_platform.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* +* ******************************* +* ADI devices logging macros +* ******************************* +*/ +#if ADI_COMMON_VERBOSE > 0 +/** +* \brief Macro to log API function entry +* +* This macro will call adi_common_LogWrite function with the __FUNCTION__ preprocessor +* It will report any error discovered. +* +* \param commonDev pointer to adi_common_Device_t +* \param logLevel of type adi_common_LogLevel_e +*/ +#define ADI_FUNCTION_ENTRY_LOG(commonDev, logLevel) \ + adi_common_LogWrite(commonDev, logLevel, "%s(...)", __FUNCTION__) + +/** +* \brief Macro to log API function entry +* +* This macro will call adi_common_LogWrite function with the __FUNCTION__ preprocessor +* +* \param commonDev pointer to adi_common_Device_t +* \param logLevel of type adi_common_LogLevel_e +* \param message const char pointer that represents the message to be logged +* \param ... variable argument passed to adi_common_Logwrite +*/ +#define ADI_FUNCTION_ENTRY_VARIABLE_LOG(commonDev, logLevel, message, ...) \ + adi_common_LogWrite(commonDev, logLevel, message, __FUNCTION__, ##__VA_ARGS__) + +/** +* \brief Macro to log API function entry +* +* This macro will call adi_common_LogWrite function with the __FUNCTION__ preprocessor +* +* \param commonDev pointer to adi_common_Device_t +* \param message const char pointer that represents the message to be logged +*/ +#define ADI_MESSAGE_LOG(commonDev, message) \ + adi_common_LogWrite(commonDev, ADI_COMMON_LOG_MSG, message) + +#else /* ADI_COMMON_VERBOSE < 0 or not defined */ +#define ADI_FUNCTION_ENTRY_LOG(commonDev, logLevel) \ + adi_common_LogWrite(commonDev, logLevel, "%s(...)", __FUNCTION__) +#define ADI_FUNCTION_ENTRY_VARIABLE_LOG(commonDev, logLevel, message, ...) \ + adi_common_LogWrite(commonDev, logLevel, message, __FUNCTION__, ##__VA_ARGS__) +#define ADI_MESSAGE_LOG(commonDev, message) \ + adi_common_LogWrite(commonDev, ADI_COMMON_LOG_MSG, message) +#endif + +/** +* \brief Macro to log error structure +* +* This macro will call adi_common_LogWrite function with the required string for logging the error. +* +* \param commonDev pointer to adi_common_Device_t +* \param err pointer to the error structure +*/ +#define ADI_ERROR_LOG(commonDev, err) \ +{\ + adi_common_LogWrite(commonDev,\ + ADI_COMMON_LOG_ERR,\ + "Error number % d (0x%08x), Recovery action % d.In file % s, in function % s, in line % d, variable name % s.Error message % s.\n",\ + err.errCode,\ + err.errCode,\ + err.newAction,\ + err.errFile,\ + err.errFunc,\ + err.errLine,\ + err.varName,\ + err.errormessage); \ +} + +/* +* ******************************* +* ADI devices common logging functions +* ******************************* +*/ + +/** +* \brief Function to set the log level +* +* Used to set the log level mask of what types of messages to log +* +* \param commonDev pointer to adi_common_Device_t +* \param halLogLevel of type int32_t that follows adi_common_LogLevel_e +* sets the application log level to which all log statement levels will be commpared to. +*/ +void adi_common_LogLevelSet(adi_common_Device_t* commonDev, + int32_t halLogLevel); + +/** +* \brief Function to get the log level +* +* Used to read the log level mask of what types of messages are able to be logged. +* +* \param commonDev pointer to adi_common_Device_t +* \param halLogLevel Pointer of type int32_t that follows adi_common_LogLevel_e +* +*/ +void adi_common_LogLevelGet(adi_common_Device_t* commonDev, + int32_t* halLogLevel); + +/** +* \brief Function to write to log with a selected comment +* +* \param commonDev pointer to adi_common_Device_t +* \param logLevel of type adi_common_LogLevel_e +* \param comment const char pointer that represents the message to be logged +* \param ... variable argument passed to adi_common_Logwrite +*/ +void adi_common_LogWrite(adi_common_Device_t* commonDev, + adi_common_LogLevel_e logLevel, + const char* comment, + ...); + +/** +* \brief Function to open the log file associated to the log +* +* Used to open the log file that is stored in the platform +* +* \param commonDev pointer to adi_common_Device_t +* \param fileName file name to be open, if null default name in the devHalInfo structure will be used +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_common_LogFileOpen(adi_common_Device_t* commonDev, + char* fileName); + +/** +* \brief Function to close the log file associated to the log +* +* Used to close the log file that is stored in the platform +* +* \param commonDev pointer to adi_common_Device_t +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_common_LogFileClose(adi_common_Device_t* commonDev); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* _ADI_COMMON_LOG_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/common/adi_logging/adi_common_log_types.h b/driver/rfic/rf/adrv9025/c_src/common/adi_logging/adi_common_log_types.h new file mode 100644 index 0000000..e58389e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/common/adi_logging/adi_common_log_types.h @@ -0,0 +1,51 @@ +/** +* \file adi_common_log_types.h +* \brief Contains ADI common log types. +* +* ADI common lib Version: 0.0.1.1 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_COMMON_LOG_TYPES_H_ +#define _ADI_COMMON_LOG_TYPES_H_ + +#include"adi_common_error_types.h" +#include"adi_common_hal_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* +* ******************************* +* ADI devices common logging enums +* ******************************* +*/ + +/** +* \brief An enumerated type in bit mask format to list the log message +* categories or groups. +*/ +typedef enum adi_common_LogLevel +{ + ADI_COMMON_LOG_NONE = 0x0, /*!< Common Log enum to represent all types of log messages not selected */ + ADI_COMMON_LOG_MSG = 0x1, /*!< Common Log enum to represent a log message type */ + ADI_COMMON_LOG_WARN = 0x2, /*!< Common Log enum to represent a warning message type */ + ADI_COMMON_LOG_ERR = 0x4, /*!< Common Log enum to represent a error message type */ + ADI_COMMON_LOG_API = 0x8, /*!< Common Log enum to represent an API function entry for logging purposes */ + ADI_COMMON_LOG_API_PRIV = 0x10, /*!< Common Log enum to represent an Private API function entry for logging purposes */ + ADI_COMMON_LOG_BF = 0x20, /*!< Common Log enum to represent a BF function entry for logging purposes */ + ADI_COMMON_LOG_HAL = 0x40, /*!< Common Log enum to represent a ADI HAL function entry for logging purposes */ + ADI_COMMON_LOG_SPI = 0x80, /*!< Common Log enum to represent a spi transaction type */ + ADI_COMMON_LOG_ALL = 0xFF /*!< Common Log enum to represent all types of log messages selected */ +} adi_common_LogLevel_e; + +#ifdef __cplusplus +} +#endif +#endif /* _ADI_COMMON_LOG_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/common/makefile b/driver/rfic/rf/adrv9025/c_src/common/makefile new file mode 100644 index 0000000..a3af47c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/common/makefile @@ -0,0 +1,33 @@ +LIB_ADI_COMMON = libadi_common.a +#CC = aarch64-linux-gnu-gcc +ADI_COMMON_SRC = ./ +ADI_COMMON_ERROR_SRC = ./adi_error/ +ADI_COMMON_LOGGING_SRC = ./adi_logging/ +ADI_COMMON_HAL_SRC = ./adi_hal/ + +ARFLAGS = -rv +CFLAGS = -Wall -Werror -I../platforms/ -I./ -I./adi_error/ -I./adi_logging/ -I./adi_hal/ +EXT = c + +SRC = $(wildcard $(ADI_COMMON_SRC)/*.$(EXT)) \ + $(wildcard $(ADI_COMMON_ERROR_SRC)/*.$(EXT)) \ + $(wildcard $(ADI_COMMON_LOGGING_SRC)/*.$(EXT)) \ + $(wildcard $(ADI_COMMON_HAL_SRC)/*.$(EXT)) + +OBJS = $(SRC:.$(EXT)=.o) + +all: $(SRC) $(LIB_ADI_COMMON) + +.$(EXT).o: + $(CC) $(CFLAGS) -o $@ -c $< + +$(LIB_ADI_COMMON): $(OBJS) + ar $(ARFLAGS) $(LIB_ADI_COMMON) $(OBJS) + +clean: + rm -rf $(ADI_COMMON_SRC)*.o + rm -rf $(ADI_COMMON_ERROR_SRC)*.o + rm -rf $(ADI_COMMON_LOGGING_SRC)*.o + rm -rf $(ADI_COMMON_HAL_SRC)*.o + rm -rf *.a + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/ad9528/makefile b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/makefile new file mode 100644 index 0000000..322cd8c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/makefile @@ -0,0 +1,37 @@ +LIB_ADI_AD9528_DEVICE = libadi_ad9528.a +#CC = aarch64-linux-gnu-gcc +ADI_AD9528_SRC = ./public/src +ADI_AD9528_PRIVATE_SRC = ./private/src +ARFLAGS = -rv +CFLAGS = -Wall -I./public/include -I../../platforms/ -I../../common/ -I../../common/adi_error -I../../common/adi_logging -I../../common/adi_hal #-Werror +ADI_PLATFORM_SRC = ../../platforms +ADI_COMMON_SRC = ../../common +EXT = c + +SRC = $(wildcard $(ADI_AD9528_PRIVATE_SRC)/*.$(EXT)) \ + $(wildcard $(ADI_AD9528_SRC)/*.$(EXT)) + +OBJS = $(SRC:.$(EXT)=.o) + +all: adi_platform_lib \ + adi_common_lib \ + $(LIB_ADI_AD9528_DEVICE) + +.$(EXT).o: + $(CC) $(CFLAGS) -o $@ -c $< + +$(LIB_ADI_AD9528_DEVICE): $(OBJS) + ar $(ARFLAGS) $(LIB_ADI_AD9528_DEVICE) $(OBJS) + +adi_platform_lib: + $(MAKE) -C $(ADI_PLATFORM_SRC) + +adi_common_lib: + $(MAKE) -C $(ADI_COMMON_SRC) + +clean: + rm -rf $(ADI_AD9528_SRC)/*.o + rm -rf $(ADI_AD9528_PRIVATE_SRC)/*.o + rm -rf *.a + $(MAKE) -C $(ADI_PLATFORM_SRC) clean + $(MAKE) -C $(ADI_COMMON_SRC) clean \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/ad9528/private/include/adi_ad9528_registers.h b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/private/include/adi_ad9528_registers.h new file mode 100644 index 0000000..7e3932f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/private/include/adi_ad9528_registers.h @@ -0,0 +1,90 @@ +/** +* \file adi_ad9528_registers.h +* \brief Contains register map definition for the AD9528 clock chip +*/ +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ +#ifndef _ADI_AD9528_REGISTERS_H_ +#define _ADI_AD9528_REGISTERS_H_ + +#include "adi_common_error_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define AD9528_READ (1 << 15) +#define AD9528_WRITE (0 << 15) +#define AD9528_CNT(x) (((x) - 1) << 13) +#define AD9528_ADDR(x) ((x) & 0xFFF) + +#define AD9528_1B(x) ((1 << 16) | ((x) + 0)) +#define AD9528_2B(x) ((2 << 16) | ((x) + 1)) +#define AD9528_3B(x) ((3 << 16) | ((x) + 2)) +#define AD9528_4B(x) ((4 << 16) | ((x) + 3)) +#define AD9528_TRANSF_LEN(x) ((x) >> 16) + +/* AD9528 SPI Address defines */ +#define AD9528_ADDR_ADI_SPI_CONFIG_A 0x000 +#define AD9528_ADDR_ADI_SPI_CONFIG_B 0x001 +#define AD9528_CHIP_ID 0x003 +#define AD9528_ADDR_IO_UPDATE 0x00F + +#define AD9528_ADDR_REF_A_DIVIDER_LSB 0x100 +#define AD9528_ADDR_REF_A_DIVIDER_MSB 0x101 +#define AD9528_ADDR_REF_B_DIVIDER_LSB 0x102 +#define AD9528_ADDR_REF_B_DIVIDER_MSB 0x103 +#define AD9528_ADDR_PLL1_N_DIV_LSB 0x104 +#define AD9528_ADDR_PLL1_N_DIV_MSB 0x105 +#define AD9528_ADDR_PLL1_CHARGEPUMP 0x106 +#define AD9528_ADDR_PLL1_CP_CTRL2 0x107 +#define AD9528_ADDR_INPUT_RECEIVERS1 0x108 +#define AD9528_ADDR_INPUT_RECEIVERS2 0x109 +#define AD9528_ADDR_INPUT_RECEIVERS3 0x10A +#define AD9528_ADDR_PLL1_FASTLOCK 0x10B + +#define AD9528_ADDR_PLL2_CHARGEPUMP 0x200 +#define AD9528_ADDR_PLL2_N_DIV 0x201 +#define AD9528_ADDR_PLL2_CTRL 0x202 +#define AD9528_ADDR_PLL2_VCO_CTRL 0x203 +#define AD9528_ADDR_PLL2_VCO_DIV 0x204 +#define AD9528_ADDR_PLL2_LF_CTRL1 0x205 +#define AD9528_ADDR_PLL2_LF_CTRL2 0x206 +#define AD9528_ADDR_PLL2_RDIV 0x207 +#define AD9528_ADDR_PLL2_REPLICA_CHDIV 0x208 +#define AD9528_ADDR_PLL2_REPLICA_DIV_PHASE 0x209 + +#define AD9528_ADDR_CH_OUT0_CTRL1 0x300 +#define AD9528_ADDR_CH_OUT0_CTRL2 0x301 +#define AD9528_ADDR_CH_OUT0_CHDIV 0x302 +#define AD9528_ADDR_OUTPUT_SYNC 0x32A +#define AD9528_ADDR_MASK_SYNC1 0x32B +#define AD9528_ADDR_MASK_SYNC2 0x32C +#define AD9528_ADDR_EN_OUTPUT_PATH_SEL1 0x32D +#define AD9528_ADDR_EN_OUTPUT_PATH_SEL2 0x32E + +#define AD9528_ADDR_SYSERF_DIV_LSB 0x400 +#define AD9528_ADDR_SYSERF_DIV_MSB 0x401 +#define AD9528_ADDR_SYSREF_CTRL3 0x402 +#define AD9528_ADDR_SYSREF_CTRL4 0x403 +#define AD9528_ADDR_SYSREF_CTRL5 0x404 + +#define AD9528_ADDR_POWERDOWN_CTRL 0x500 +#define AD9528_ADDR_CH_POWERDOWN1 0x501 +#define AD9528_ADDR_CH_POWERDOWN2 0x502 +#define AD9528_ADDR_LDO_ENABLES1 0x503 +#define AD9528_ADDR_LDO_ENABLES2 0x504 +#define AD9528_ADDR_STATUS0_CTRL 0x505 +#define AD9528_ADDR_STATUS1_CTRL 0x506 +#define AD9528_ADDR_STATUS_OE 0x507 +#define AD9528_ADDR_STATUS_READBACK0 0x508 +#define AD9528_ADDR_STATUS_READBACK1 0x509 + +#ifdef __cplusplus +} +#endif + +#endif /*_ADI_AD9528_REGISTERS_H_*/ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/include/adi_ad9528.h b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/include/adi_ad9528.h new file mode 100644 index 0000000..027e16b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/include/adi_ad9528.h @@ -0,0 +1,235 @@ +/** + * \file adi_ad9528.h + * \brief Contains function declarations for AD9528 API + */ +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ +#ifndef _ADI_AD9528_H_ +#define _ADI_AD9528_H_ + +#include "adi_ad9528_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Performs a Hardware Initialization for AD9528 Device. +* +* \pre This function may be called after device->common.devHalInfo has been initialized with +* user values +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to AD9528 device data structure +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +*/ +int32_t adi_ad9528_HwOpen(adi_ad9528_Device_t *device); + +/** +* \brief Performs a hardware shutdown for AD9528 Device. +* +* \pre This function may be called after device->common.devHalInfo has been initialized with +* user values +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to AD9528 device data structure +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +*/ +int32_t adi_ad9528_HwClose(adi_ad9528_Device_t *device); + +/** +* \brief Performs a hard reset on the AD9528 DUT +* +* Dependencies +* - device->common.devHalInfo +* +* \param device is structure pointer to the AD9528 data structure containing +* devHalInfo +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +*/ +int32_t adi_ad9528_HwReset(adi_ad9528_Device_t *device); + +/** +* \brief Sets the AD9528 device SPI settings (3wire/4wire, msbFirst, etc). +* +* This function will use the settings in the adi_ad9528_SpiSettings_t structure +* to set SPI stream mode, address auto increment direction, msbFirst/lsbfirst, +* and 3wire/4wire mode. The AD9528 device always uses SPI MODE 0 (CPHA=0, +* CPOL=0), uses a 16bit instruction word, and defaults to SPI streaming (auto increment) +* +* Dependencies +* - device->common.devHalInfo +* - spi->msbFirst +* - spi->autoIncAddrUp +* - spi->fourWireMode +* +* \param device is structure pointer to the AD9528 data structure containing +* settings +* \param spi is a structure pointer to AD9528 SPI controller settings - not +* platform hardware SPI settings +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +*/ +int32_t adi_ad9528_SpiCfgSet(adi_ad9528_Device_t *device, adi_ad9528_SpiSettings_t *spi); + +/** +* \brief Gets the AD9528 device SPI settings (3wire/4wire, MSBFirst, etc). +* +* This function will read the current SPI settings and load them into the spi +* input +* parameter. This function only works after the adi_ad9528_SpiCfgSet has been +* called. +* +* Dependencies +* - device->common.devHalInfo +* - spi->msbFirst +* - spi->enSpiStreaming +* - spi->autoIncAddrUp +* - spi->fourWireMode +* +* \param device is structure pointer to the AD9528 data structure containing +* settings +* \param spi is a structure pointer to AD9528 SPI controller settings - not +* platform hardware SPI settings +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +*/ +int32_t adi_ad9528_SpiCfgGet(adi_ad9528_Device_t *device, adi_ad9528_SpiSettings_t *spi); + +/** +* \brief Initializes the AD9528 by writing all SPI registers +* +* Initializes the AD9528 using the values passed in through the +* adi_ad9528_Init_t structure. +* +* Dependencies +* - All parameters in init structure +* - device->common.devHalInfo +* +* \param device is structure pointer to AD9528 clock device structure +* \param init is a structure pointer to the AD9528 initialization settings +* structure +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter +* check +*/ +int32_t adi_ad9528_Initialize(adi_ad9528_Device_t *device, adi_ad9528_Init_t *init); + +/** +* \brief Send a SPI message to request a SYSREF pulse or continuous SYSREF from +* the AD9528 +* +* Requests a SYSREF from the AD9528. It will use whatever settings for SYSREF +* that are current configured in the AD9528. This could be a single pulse, +* multiple pulses, or continuous pulses. +* +* Dependencies +* - device->common.devHalInfo +* +* \param device is structure pointer to AD9528 clock device structure +* \param enableSYSREF If NSHOT SYSREF mode, this parameter is ignored. If +* PRBS/CONTINUOUS SYSREF mode, 1= enable SYSREF, 0= disable SYSREF. +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +*/ +int32_t adi_ad9528_SysrefRequest(adi_ad9528_Device_t *device, uint8_t enableSYSREF); + +/** +* \brief Update the Sysref settings for an AD9528 device by writing to the +* corresponding configuration registers +* +* Dependencies +* - device->common.devHalInfo +* +* \param device is structure pointer to AD9528 clock device structure +* \param sysrefSettings is structure pointer to a Sysref settings device +* structure containing updated settings +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +*/ +int32_t adi_ad9528_SysrefSetup(adi_ad9528_Device_t *device, adi_ad9528_SysrefSettings_t *sysrefSettings); + +/** +* \brief Update the AD9528 clock outputs that are enabled. The function probes +* the AD9528 chip to determine the sysref settings. +* +* Dependencies +* - device->common.devHalInfo +* +* \param device is structure pointer to AD9528 clock device structure +* \param clkEnable Sets which clock outputs are enabled. +* Bit per clock output. bit0 = out0, etc. +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +*/ +int32_t adi_ad9528_ClockOutputsEnable(adi_ad9528_Device_t *device, uint16_t clkEnable); + +/** +* \brief Waits for PLL1 and PLL2 to lock and the REFA and VCXO clocks to be +* present +* +* Waits until Reference A clock and VCXO clock input to be detected (present), +* and PLL1 and PLL2 to lock. Will timeout after 1 second and return +* AD9528_FAILED. +* If clock are detected and PLLs locked, returns ADI_COMMON_ACT_NO_ACTION. +* Will read the AD9528 status prior. +* +* Dependencies +* - device->common.devHalInfo +* +* \param device is structure pointer to AD9528 clock device structure +* \param timeout_ms the amount of time to wait for a successful lock before +* returning +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +* \retval ADI_AD9528_ACT_PLL_LOCK_FAILED Recover action for a failed PLL lock +*/ +int32_t adi_ad9528_PllLockDebounce(adi_ad9528_Device_t *device, uint32_t timeout_ms); + +/** +* \brief Reads the Lock Status register of the AD9528 +* +* This function will read register 0x508 and load that value into the address +* pointed to by status parameter. +* +* Dependencies +* - device->common.devHalInfo +* +* \param device is structure pointer to AD9528 clock device structure +* \param status a pointer to a uint8_t that will be loaded with the value of +* register address 0x508 +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +*/ +int32_t adi_ad9528_PllLockStatusGet(adi_ad9528_Device_t *device, uint8_t *status); + + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_AD9528_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/include/adi_ad9528_error.h b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/include/adi_ad9528_error.h new file mode 100644 index 0000000..2a70def --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/include/adi_ad9528_error.h @@ -0,0 +1,33 @@ +/** +* \file adi_ad9528_error.h +* \brief AD9528 ERROR header file +* +* Extension of adi_common_error +* +* API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADI API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_AD9528_ERROR_H_ +#define _ADI_AD9528_ERROR_H_ + +#include "adi_common_error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Extending Common error for AD9528 */ +#define ADI_AD9528_ERR_PLL_LOCK_FAILED 0x2001 +#define ADI_AD9528_ERR_NUMBER_OF_ERRORS 0x2002 + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_AD9528_ERROR_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/include/adi_ad9528_hal.h b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/include/adi_ad9528_hal.h new file mode 100644 index 0000000..d453bf9 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/include/adi_ad9528_hal.h @@ -0,0 +1,30 @@ +/** +* \file adi_ad9528_hal.h +* \brief Contains prototypes and macro definitions for Private ADI HAL wrapper +* functions implemented in adi_ad9528_hal.c +*/ +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ +#ifndef _ADI_AD9528_HAL_H_ +#define _ADI_AD9528_HAL_H_ + +#include +#include + +#include "adi_ad9528_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t adi_ad9528_SpiByteWrite(adi_ad9528_Device_t *device, uint16_t addr, uint8_t data); +int32_t adi_ad9528_SpiByteRead(adi_ad9528_Device_t *device, uint16_t addr, uint8_t *data); + +#ifdef __cplusplus +} +#endif + +#endif /* ADI_AD9528_HAL_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/include/adi_ad9528_types.h b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/include/adi_ad9528_types.h new file mode 100644 index 0000000..bde8bf9 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/include/adi_ad9528_types.h @@ -0,0 +1,250 @@ +/** + * \file adi_ad9528_types.h + * \brief Contains enum and structure data types for all AD9528 function calls + */ +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ +#ifndef _ADI_AD9528_TYPES_H_ +#define _ADI_AD9528_TYPES_H_ + +#include +#include "adi_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADI_AD9528_NUM_OUTPUT_CHANNELS 14 +#define ADI_AD9528_NUMBER_SPI_RETRY 200 +#define ADI_AD9528_PLL_DEBOUNCE_TIME_MS 50 +#define ADI_AD9528_PLL_DEBOUNCE_INT_MS 10 +#define ADI_AD9528_REG508_STATUS_MASK 0xEF /* Mask bit 4: Both REFA/REFB missing since this is not set in lockStatusExpectedValue */ + +/** + * \brief Enum to select what source outputs from each AD9528 output channel + */ +typedef enum adi_ad9528_OutSourceSel +{ + ADI_AD9528_CHANNEL_DIV = 0, /*!< Channel divisor output select */ + ADI_AD9528_PLL1_OUTPUT = 1, /*!< VCXO output select */ + ADI_AD9528_SYSREF = 2, /*!< SYSREF output select */ + ADI_AD9528_INV_PLL1_OUTPUT = 5 /*!< VCXO inverted output select */ + +} adi_ad9528_OutSourceSel_e; + +/** + * \brief Enum to select what output buffer standard is used for the clock + * outputs + */ +typedef enum adi_ad9528_OutBufferControl +{ + ADI_AD9528_LVDS, /*!< LVDS output buffer select */ + ADI_AD9528_LVDS_BOOST, /*!< LVDS boost output buffer select */ + ADI_AD9528_HSTL /*!< HSTL output buffer select */ + +} adi_ad9528_OutBufferControl_e; + +/** + * \brief Enum to select the clock input buffer mode + */ +typedef enum adi_ad9528_RefBuffer +{ + ADI_AD9528_DISABLED, /*!< Disabled input buffer select */ + ADI_AD9528_SINGLE_ENDED, /*!< Single-ended input buffer select */ + ADI_AD9528_NEG_SINGLE_ENDED, /*!< Negative single-ended input buffer select */ + ADI_AD9528_DIFFERENTIAL /*!< Differential input buffer select */ + +} adi_ad9528_RefBuffer_e; + +/** + * \brief Enum to select the SYSREF output source + */ +typedef enum adi_ad9528_SysrefSourceSelection +{ + ADI_AD9528_EXTERNAL, /*!< External SYSREF source select */ + ADI_AD9528_EXT_RESAMPLED, /*!< External resampled SYSREF source select */ + ADI_AD9528_INTERNAL /*!< Internal SYSREF source select */ + +} adi_ad9528_SysrefSourceSelection_e; + +/** + * \brief Enum to choose the SYSREF pattern mode + */ +typedef enum adi_ad9528_SysrefPatternMode +{ + ADI_AD9528_NSHOT, /*!< 'N' shot SYSREF pattern mode select */ + ADI_AD9528_CONTINUOUS, /*!< Continuous SYSREF pattern mode select */ + ADI_AD9528_PRBS, /*!< PRBS SYSREF pattern mode select */ + ADI_AD9528_STOP /*!< Stop select */ + +} adi_ad9528_SysrefPatternMode_e; + +/** + * \brief Enum to select the SYSREF input pin mode + */ +typedef enum adi_ad9528_SysrefPinEdgeMode +{ + ADI_AD9528_LEVEL_ACTIVE_HIGH, /*!< Active high level input mode select */ + ADI_AD9528_LEVEL_ACTIVE_LOW, /*!< Active low level input mode select */ + ADI_AD9528_RISING_EDGE, /*!< Rising edge input mode select */ + ADI_AD9528_FALLING_EDGE /*!< Falling edge input mode select */ + +} adi_ad9528_SysrefPinEdgeMode_e; + +/** + * \brief Enum to select the SYSREF output number of pulses for NSHOT mode + */ +typedef enum adi_ad9528_SysrefNshotMode +{ + ADI_AD9528_ONE_PULSE = 0, /*!< Single (1) pulse NSHOT mode select */ + ADI_AD9528_TWO_PULSES = 2, /*!< Two (2) pulse NSHOT mode select */ + ADI_AD9528_FOUR_PULSES = 3, /*!< Four (4) pulse NSHOT mode select */ + ADI_AD9528_SIX_PULSES = 4, /*!< Six (6) pulse NSHOT mode select */ + ADI_AD9528_EIGHT_PULSES = 5 /*!< Eight (8) pulse NSHOT mode select */ + +} adi_ad9528_SysrefNshotMode_e; + +/** + * \brief Enum to select how a SYSREF is requested + */ +typedef enum adi_ad9528_SysrefRequestMethod +{ + ADI_AD9528_SPI, /*!< SPI mode request for SYSREF */ + ADI_AD9528_PIN /*!< Pin mode request for SYSREF */ + +} adi_ad9528_SysrefRequestMethod_e; + +/** +* \brief Structure for use in adi_ad9528_InitStructConfig function +*/ +typedef struct adi_ad9528_ClockFrequencySettings +{ + uint32_t vcxoFrequency_Hz; + uint32_t refAFrequency_Hz; + uint32_t outputClock_Hz[ADI_AD9528_NUM_OUTPUT_CHANNELS]; + adi_ad9528_OutSourceSel_e outSource[ADI_AD9528_NUM_OUTPUT_CHANNELS]; + +} adi_ad9528_ClockFrequencySettings_t; + +/** + * \brief Structure to hold AD9528 PLL1 settings + */ +typedef struct adi_ad9528_Pll1Settings +{ + uint32_t refA_Frequency_Hz; + uint16_t refA_Divider; + adi_ad9528_RefBuffer_e refA_bufferCtrl; + + uint32_t refB_Frequency_Hz; + uint16_t refB_Divider; + adi_ad9528_RefBuffer_e refB_bufferCtrl; + + uint32_t vcxo_Frequency_Hz; + adi_ad9528_RefBuffer_e vcxoBufferCtrl; + + uint16_t nDividerPll1; + +} adi_ad9528_Pll1Settings_t; + +/** + * \brief Data structure to hold SPI settings for all system device types + */ +typedef struct adi_ad9528_SpiSettings +{ + uint8_t msbFirst; /*!< 1 = MSBFirst, 0 = LSBFirst */ + uint8_t autoIncAddrUp; /*!< Not implemented. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr = addr-1 */ + uint8_t fourWireMode; /*!< 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode. */ + +} adi_ad9528_SpiSettings_t; + +/** + * \brief Structure to hold AD9528 PLL2 settings + */ +typedef struct adi_ad9528_Pll2Settings +{ + uint8_t rfDivider; /*!< VCO divider: Valid range (3,4,5) */ + uint16_t n2Divider; /*!< PLL2 N2 Divider */ + uint8_t r1Divider; /*! PLL2 R1 Divider */ + uint8_t totalNdiv; /*!< NDiv = 4*Bdiv + Adiv //Bdiv valid range (3 to 63), Adiv valid range (0-3) */ + +} adi_ad9528_Pll2Settings_t; + +/** + * \brief Structure to hold AD9528 Output Clock settings + */ +typedef struct adi_ad9528_OutputSettings +{ + uint16_t outPowerDown; /*!< bit per output, if 1 power down that output */ + adi_ad9528_OutSourceSel_e outSource[ADI_AD9528_NUM_OUTPUT_CHANNELS]; /*!< CHANNEL_DIV, PLL1_OUTPUT, SYSREF, INV_PLL1_OUTPUT */ + adi_ad9528_OutBufferControl_e outBufferCtrl[ADI_AD9528_NUM_OUTPUT_CHANNELS]; /*!< LVDS, LVDS_BOOST, HSTL */ + uint8_t outAnalogDelay[ADI_AD9528_NUM_OUTPUT_CHANNELS]; /*!< bit[4] enables fine analog delay & adds 600ps delay. bits[3:0] are find delay steps, 31 ps each */ + uint8_t outDigitalDelay[ADI_AD9528_NUM_OUTPUT_CHANNELS]; /*!< 6 bits, 1/2 clock resolution @ channel div input frequency */ + uint16_t outChannelDiv[ADI_AD9528_NUM_OUTPUT_CHANNELS]; /*!< 8 bit channel divider. Valid values 1-256. Register written with (value - 1) */ + uint32_t outFrequency_Hz[ADI_AD9528_NUM_OUTPUT_CHANNELS]; /*!< output clock frequency per clock output */ + +} adi_ad9528_OutputSettings_t; + +/** +* \brief Structure to hold AD9528 SYSREF output settings +*/ +typedef struct adi_ad9528_SysrefSettings +{ + adi_ad9528_SysrefRequestMethod_e sysrefRequestMethod; + adi_ad9528_SysrefSourceSelection_e sysrefSource; + adi_ad9528_SysrefPinEdgeMode_e sysrefPinEdgeMode; + adi_ad9528_RefBuffer_e sysrefPinBufferMode; + adi_ad9528_SysrefPatternMode_e sysrefPatternMode; + adi_ad9528_SysrefNshotMode_e sysrefNshotMode; + uint16_t sysrefDivide; + +} adi_ad9528_SysrefSettings_t; + +/** + * \brief Structure to hold AD9528 run time state information + */ +typedef struct adi_ad9528_Info +{ + /* uint8_t pllLocked;*/ + /* uint8_t programmed;*/ + uint8_t initialized; + uint8_t swModeEnabled; + uint32_t deviceRevision; + uint32_t deviceId; + adi_ad9528_SysrefPatternMode_e sysrefPatternMode; + uint8_t sysrefCtrlReg403Init; /*!< Initialize sets this to value that SPI reg x403 was initialized to for SYSREF Control, later used by SysrefRequest() */ + +} adi_ad9528_Info_t; + +/** +* \brief Structure to hold AD9528 init settings +*/ +typedef struct adi_ad9528_Init +{ + adi_ad9528_SpiSettings_t spiSettings; + adi_ad9528_Pll1Settings_t pll1Settings; + adi_ad9528_Pll2Settings_t pll2Settings; + adi_ad9528_OutputSettings_t outputSettings; + adi_ad9528_SysrefSettings_t sysrefSettings; + uint32_t pllLockTimeout_ms; /*!", (int32Ptr));\ + if ((ret) == 1) {\ + x.n = (int32);\ + continue;\ + }} + +#define GET_TOKEN_CAST(x, n, ca, ret, line, int32Ptr, int32) \ + {(ret) = sscanf((line), " <" #n "=%u>", (int32Ptr));\ + if ((ret) == 1) {\ + x.n = (ca)(int32);\ + continue;\ + }} +#else +#define GET_TOKEN(x, n, ret, line, int32Ptr, int32) \ + {(ret) = sscanf_s((line), " <" #n "=%u>", (int32Ptr));\ + if ((ret) == 1) {\ + x.n = (int32);\ + continue;\ + }} + +#define GET_TOKEN_CAST(x, n, ca, ret, line, int32Ptr, int32) \ + {(ret) = sscanf_s((line), " <" #n "=%u>", (int32Ptr));\ + if ((ret) == 1) {\ + x.n = (ca)(int32);\ + continue;\ + }} +#endif + +#ifdef __GNUC__ +#define sscanf_s sscanf +#endif + +#define ADI_AD9528_MAX_BUFFER 250 + +/** +* \brief Utility function that will initialize an AD9528 using the +* Configuration Wizard +* +* This reads the configuration file to scan for AD9528 settings. It +* constructs an AD9528 init structure +* and calls the AD9528 API Initialize function +* +* Dependencies +* - None +* +* \param configFile The absolute filepath of the Configuration File +* \param init Pointer to the AD9528 init device structure to initialize +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no +* action required +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter +* check +*/ +int32_t adi_ad9528_ConfigFileLoad(const char *configFile, adi_ad9528_Init_t *init); + +/** +* \brief Helper function for ADI transceiver eval boards to init the AD9528 +* data structure +* +* This function inits the AD9528 device data structure with defaults that +* are known to work with the ADI AD9369 and AD9370 evaluation boards. +* NOTE: This function will modify the contents of the AD9528 device data +* structure. +* +* Dependencies +* - device->common.devHalInfo +* +* \param device Pointer to the AD9528 device data structure to initialize +* \param clockFrequencies The adi_ad9528_ClockFrequencySettings_t data structure. +* vcxoFrequency_Hz The VCXO frequency that is connected to the AD9528 +* refAFrequency_Hz The reference clock frequency being input into +* the AD9528 REFCLK A input +* outputDeviceClock_Hz Desired output clock frequency to the FPGA +* and transceiver device +* \param init Point to the adi_ad9528_Init_t data structure. +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no +* action required +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter +* check +*/ +int32_t adi_ad9528_InitStructConfig(adi_ad9528_Device_t *device, adi_ad9528_ClockFrequencySettings_t *clockFrequencies, adi_ad9528_Init_t *init); + +#ifdef __cplusplus +} +#endif + +#endif /* ADI_AD9528_UTILITIES_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/src/adi_ad9528.c b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/src/adi_ad9528.c new file mode 100644 index 0000000..07b2f55 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/src/adi_ad9528.c @@ -0,0 +1,880 @@ +/** + * \file adi_ad9528.c + * \brief Contains source code for configuring and initializing AD9528 clock device + */ +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ +#include "adi_ad9528_user.h" +#include +#include "adi_ad9528_hal.h" +#include "adi_ad9528.h" +#include "../../private/include/adi_ad9528_registers.h" +#include "adi_common.h" +#include "adi_ad9528_error.h" +#include "math.h" + +#if (0) +#define DEBUG_AD9025_REG(a, b) (printf("#reg%04X = 0x%02X @%03d\n", a, b, __LINE__)) +#else +#define DEBUG_AD9025_REG(a, b) +#endif + +int32_t adi_ad9528_HwOpen(adi_ad9528_Device_t *device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + adi_common_LogLevelSet(&device->common, ADI_AD9528_LOGGING); + if (device->common.error.errCode != ADI_COMMON_HAL_OK) + { + switch (device->common.error.errCode) + { + case ADI_COMMON_HAL_LOGGING_FAIL: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_WARN_RESET_LOG, + NULL, + "Logging error"); + ADI_ERROR_RETURN(device->common.error.newAction); + case ADI_COMMON_HAL_LOGGGING_LEVEL_FAIL: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_WARN_RESET_LOG, + NULL, + "Logging Level error"); + ADI_ERROR_RETURN(device->common.error.newAction); + case ADI_COMMON_HAL_GEN_SW: /* fall through */ + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Param error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + recoveryAction = adi_common_hal_HwOpen(&device->common); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + switch (device->common.error.errCode) + { + case ADI_COMMON_HAL_SPI_FAIL: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI error"); + ADI_ERROR_RETURN(device->common.error.newAction); + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Param error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_ad9528_HwClose(adi_ad9528_Device_t *device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + recoveryAction = adi_common_hal_HwClose(&device->common); + if (device->common.error.errCode != ADI_COMMON_HAL_OK) + { + switch (device->common.error.errCode) + { + case ADI_COMMON_HAL_SPI_FAIL: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + recoveryAction, + NULL, + "SPI error"); + ADI_ERROR_RETURN(device->common.error.newAction); + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Param error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_ad9528_ClockRatesRead(adi_ad9528_Device_t *device, uint32_t *outputClock_Hz) +{ + UNUSED_PARA(device); + UNUSED_PARA(outputClock_Hz); + return ADI_COMMON_ACT_NO_ACTION; +} //debug function to help verify data structure is setup correctly. + + +int32_t adi_ad9528_HwReset(adi_ad9528_Device_t *device) +{ + /* toggle RESETB on device */ + int32_t halError = (int32_t)ADI_COMMON_HAL_OK; + static const uint8_t RESETB_LEVEL_LOW = 0; + static const uint8_t RESETB_LEVEL_HIGH = 1; + static const uint8_t RESETB_WAIT_MS = 1; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + /* toggle RESETB on device with matching spi chip select index */ + halError = adi_common_hal_HwReset(&device->common, RESETB_LEVEL_LOW); + if (halError != ADI_COMMON_HAL_OK) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, + halError, /* TODO: fix to use a error code from ERRSRC_API */ + ADI_COMMON_ACT_ERR_RESET_MODULE, + NULL, + "HwReset GPIO error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + halError = adi_common_hal_Wait_ms(&device->common, RESETB_WAIT_MS); + if (halError != ADI_COMMON_HAL_OK) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, + halError, /* TODO: fix to use a error code from ERRSRC_API */ + ADI_COMMON_ACT_ERR_RESET_MODULE, + NULL, + "Timer error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + halError = adi_common_hal_HwReset(&device->common, RESETB_LEVEL_HIGH); + if (halError != ADI_COMMON_HAL_OK) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, + halError, /* TODO: fix to use a error code from ERRSRC_API */ + ADI_COMMON_ACT_ERR_RESET_MODULE, + NULL, + "HwReset GPIO error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + device->devStateInfo.initialized = 0; + + return (device->common.error.newAction); +} + +int32_t adi_ad9528_SpiCfgSet(adi_ad9528_Device_t *device, adi_ad9528_SpiSettings_t* spi) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + uint8_t spiReg = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + /* Check spi settings is not null */ + ADI_NULL_PTR_RETURN(&device->common, spi); + +#if ADI_AD9528_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + if (spi->msbFirst == 0) + { + spiReg |= 0x42; /* SPI bit is 1=LSB first */ + } + + if (spi->autoIncAddrUp > 0) + { + spiReg |= 0x24; + } + + if (spi->fourWireMode > 0) + { + spiReg |= 0x18; + } + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_ADI_SPI_CONFIG_A, spiReg); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_ADI_SPI_CONFIG_A"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_ad9528_SpiCfgGet(adi_ad9528_Device_t *device, adi_ad9528_SpiSettings_t* spi) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + uint8_t spiReg = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + /* Check spi settings is not null */ + ADI_NULL_PTR_RETURN(&device->common, spi); + +#if ADI_AD9528_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + recoveryAction = adi_ad9528_SpiByteRead(device, AD9528_ADDR_ADI_SPI_CONFIG_A, &spiReg); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not read register AD9528_ADDR_ADI_SPI_CONFIG_A"); + ADI_ERROR_RETURN(device->common.error.newAction); + + spi->fourWireMode = (spiReg & 0x10) >> 4; + spi->autoIncAddrUp = (spiReg & 0x20) >> 5; + spi->msbFirst = 0x0001 - ((spiReg & 0x40) >> 6); + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adi_ad9528_Initialize(adi_ad9528_Device_t *device, adi_ad9528_Init_t *init) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t pll2_Adiv = init->pll2Settings.totalNdiv % 4; + uint8_t pll2_Bdiv = init->pll2Settings.totalNdiv / 4; + uint8_t reg108 = 0; + uint8_t reg109 = 0; + uint8_t i = 0; + uint8_t j = 0; + + /* Range checks */ + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + /* Check spi settings is not null */ + ADI_NULL_PTR_RETURN(&device->common, init); + + /* refA_Divider is a 10-bit bitfield */ + if (init->pll1Settings.refA_Divider > 1023) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, init->pll1Settings.refA_Divider, "AD9528 refA_Divider out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* refB_Divider is a 10-bit bitfield */ + if (init->pll1Settings.refB_Divider > 1023) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, init->pll1Settings.refB_Divider, "AD9528 refB_Divider out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* nDividerPll1 is a 10-bit bitfield */ + if (init->pll1Settings.nDividerPll1 > 1023) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, init->pll1Settings.nDividerPll1, "AD9528 nDividerPll1 out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* cal value must equal (RF * N2) */ + if (init->pll2Settings.totalNdiv != (init->pll2Settings.n2Divider * init->pll2Settings.rfDivider)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "totalNDiv (VCO Cal Divider) value must match RF div * N2 div"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if(init->pll2Settings.totalNdiv == 18 || init->pll2Settings.totalNdiv == 27) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Illegal VCO Cal divider value (if B < 7 only specific A values are allowed)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* n2Divider valid range is 1-256 */ + if (init->pll2Settings.n2Divider > 256 || init->pll2Settings.n2Divider < 1) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, init->pll2Settings.n2Divider, "AD9528 n2Divider out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* r1Divider valid range is 1-31 */ + if (init->pll2Settings.r1Divider > 31 || init->pll2Settings.r1Divider < 1) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, init->pll2Settings.r1Divider, "AD9528 r1Divider out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (pll2_Adiv > 3) { //A div valid range (0 to 3) + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, init->pll2Settings.totalNdiv, "AD9528 PLL2 A Divider out of range (0 to 3)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (pll2_Bdiv < 4 || pll2_Bdiv > 63) { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, init->pll2Settings.totalNdiv, "AD9528 PLL2 B Divider out of range (3 to 63)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (init->pll2Settings.rfDivider < 3 || init->pll2Settings.rfDivider > 5) { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, init->pll2Settings.rfDivider, "AD9528 PLL2 RF Divider out of range (3,4, or 5)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < 14; i = i + 1) + { + /* outChannelDiv valid range is 1-256 */ + if (init->outputSettings.outChannelDiv[i] > 256 || init->outputSettings.outChannelDiv[i] < 1) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, init->outputSettings.outChannelDiv, "An AD9528 outChannelDiv is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* sanity check on Analog Delay. If a delay is requested the enable needs to be set */ + if (((init->outputSettings.outAnalogDelay[i] & 0x0F) > 0) && ((init->outputSettings.outAnalogDelay[i] & 0x10) != 0x10)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, init->outputSettings.outAnalogDelay, "An Analog Delay is requested but enable is not set"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + +#if ADI_AD9528_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + adi_ad9528_SpiCfgSet(device, &init->spiSettings); + ADI_ERROR_RETURN(device->common.error.newAction); + + /********************************************************************** + * Configure PLL1 + **********************************************************************/ + /*REF A div[7:0]*/ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_REF_A_DIVIDER_LSB, (init->pll1Settings.refA_Divider & 0xFF)); + DEBUG_AD9025_REG(AD9528_ADDR_REF_A_DIVIDER_LSB, (init->pll1Settings.refA_Divider & 0xFF)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_REF_A_DIVIDER_LSB"); + ADI_ERROR_RETURN(device->common.error.newAction); + /*REF A div[9:8]*/ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_REF_A_DIVIDER_MSB, ((init->pll1Settings.refA_Divider >> 8) & 0x03)); + DEBUG_AD9025_REG(AD9528_ADDR_REF_A_DIVIDER_MSB, ((init->pll1Settings.refA_Divider >> 8) & 0x03)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_REF_A_DIVIDER_MSB"); + ADI_ERROR_RETURN(device->common.error.newAction); + /*REF B div[7:0]*/ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_REF_B_DIVIDER_LSB, (init->pll1Settings.refB_Divider & 0xFF)); + DEBUG_AD9025_REG(AD9528_ADDR_REF_B_DIVIDER_LSB, (init->pll1Settings.refB_Divider & 0xFF)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_REF_B_DIVIDER_LSB"); + ADI_ERROR_RETURN(device->common.error.newAction); + /*REF B div[9:8]*/ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_REF_B_DIVIDER_MSB, ((init->pll1Settings.refB_Divider >> 8) & 0x03)); + DEBUG_AD9025_REG(AD9528_ADDR_REF_B_DIVIDER_MSB, ((init->pll1Settings.refB_Divider >> 8) & 0x03)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_REF_B_DIVIDER_MSB"); + ADI_ERROR_RETURN(device->common.error.newAction); + /*PLL1 N div[7:0]*/ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_PLL1_N_DIV_LSB, (init->pll1Settings.nDividerPll1 & 0xFF)); + DEBUG_AD9025_REG(AD9528_ADDR_PLL1_N_DIV_LSB, (init->pll1Settings.nDividerPll1 & 0xFF)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_PLL1_N_DIV_LSB"); + ADI_ERROR_RETURN(device->common.error.newAction); + /* PLL1 N div[9:8] */ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_PLL1_N_DIV_MSB, ((init->pll1Settings.nDividerPll1 >> 8) & 0x03)); + DEBUG_AD9025_REG(AD9528_ADDR_PLL1_N_DIV_MSB, ((init->pll1Settings.nDividerPll1 >> 8) & 0x03)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_PLL1_N_DIV_MSB"); + ADI_ERROR_RETURN(device->common.error.newAction); + /* PLL1 Charge Pump control 1*/ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_PLL1_CHARGEPUMP, 0x0C); // daya debug 0x0A); + DEBUG_AD9025_REG(AD9528_ADDR_PLL1_CHARGEPUMP, 0x0C); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_PLL1_CHARGEPUMP"); + ADI_ERROR_RETURN(device->common.error.newAction); + /* PLL1 Charge Pump control 2*/ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_PLL1_CP_CTRL2, 0x03); // daya debug 0x02); + DEBUG_AD9025_REG(AD9528_ADDR_PLL1_CP_CTRL2, 0x02); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_PLL1_CP_CTRL2"); + ADI_ERROR_RETURN(device->common.error.newAction); + + switch (init->pll1Settings.refA_bufferCtrl) + { + case ADI_AD9528_DISABLED: reg108 &= ~0x28; reg109 &= ~0x01; break; /*clear all REFA enable bits*/ + case ADI_AD9528_SINGLE_ENDED: reg108 |= 0x08; reg109 &= ~0x01; break; /*Set REFA receiver enable, clear REFA SE negative input enable*/ + case ADI_AD9528_NEG_SINGLE_ENDED: reg108 |= 0x08; reg108 &= ~0x10; reg109 |= 0x01; break; /*Disable REFA diff receiver, enable REFA receiver and use negative REFA input*/ + // case ADI_AD9528_DIFFERENTIAL: reg108 |= 0x28; reg109 &= ~0x01; break; // daya debug + case ADI_AD9528_DIFFERENTIAL: reg108 = 0x28; reg109 = 0x02; break; + default: reg108 |= 0x08; reg109 &= ~0x01; break; /*default to single ended case*/ + } + switch (init->pll1Settings.refB_bufferCtrl) { + case ADI_AD9528_DISABLED: reg108 &= ~0x50; reg109 &= ~0x02; break; /*clear all REFB enable bits*/ + case ADI_AD9528_SINGLE_ENDED: reg108 |= 0x10; reg109 &= ~0x02; break; /*Set REFB receiver enable, clear REFB SE negative input enable*/ + case ADI_AD9528_NEG_SINGLE_ENDED: reg108 |= 0x10; reg108 &= ~0x40; reg109 |= 0x02; break; /*Disable REFB diff receiver, enable REFB receiver and use negative REFB input*/ + case ADI_AD9528_DIFFERENTIAL: reg108 |= 0x50; reg109 &= ~0x02; break; + default: reg108 |= 0x10; reg109 &= ~0x02; break; /*default to single ended case*/ + } + switch (init->pll1Settings.vcxoBufferCtrl) { + case ADI_AD9528_DISABLED: reg108 &= ~0x03; reg108 |= 0x04; break; /*power down VCXO input*/ + case ADI_AD9528_SINGLE_ENDED: reg108 &= ~0x07; break; /*Clear VCXO receiver power down, defaults to Single ended mode*/ + case ADI_AD9528_NEG_SINGLE_ENDED: reg108 &= ~0x07; reg108 |= 0x02; break; /*Clear VCXO power down, enable Negative single ended mode[1]*/ + case ADI_AD9528_DIFFERENTIAL: reg108 &= ~0x07; reg108 |= 0x01; break; /*Clear VCXO power down, enable differential input buffer[0]*/ + default: reg108 &= ~0x07; break; /*default to positive single ended case*/ + } + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_INPUT_RECEIVERS1, reg108); + DEBUG_AD9025_REG(AD9528_ADDR_INPUT_RECEIVERS1, reg108); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_INPUT_RECEIVERS1"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_INPUT_RECEIVERS2, reg109); + DEBUG_AD9025_REG(AD9528_ADDR_INPUT_RECEIVERS2, reg109); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_INPUT_RECEIVERS2"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_INPUT_RECEIVERS3, 0x06); // daya debug 0x02); + DEBUG_AD9025_REG(AD9528_ADDR_INPUT_RECEIVERS3, 0x02); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_INPUT_RECEIVERS3"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_PLL1_FASTLOCK, 0x00); + DEBUG_AD9025_REG(AD9528_ADDR_PLL1_FASTLOCK, 0x00); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_PLL1_FASTLOCK"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /********************************************************************** + * Configure PLL2 + **********************************************************************/ + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_PLL2_CHARGEPUMP, 0xE6); /*PLL2 Charge Pump[7:0]*/ + DEBUG_AD9025_REG(AD9528_ADDR_PLL2_CHARGEPUMP, 0xE6); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_PLL2_CHARGEPUMP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_PLL2_N_DIV, ((pll2_Adiv & 0x3) << 6) | (pll2_Bdiv & 0x3F)); /*PLL2 A and B divider*/ + DEBUG_AD9025_REG(AD9528_ADDR_PLL2_N_DIV, ((pll2_Adiv & 0x3) << 6) | (pll2_Bdiv & 0x3F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_PLL2_N_DIV"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_PLL2_CTRL, 0x03); /*PLL2 control*/ + DEBUG_AD9025_REG(AD9528_ADDR_PLL2_CTRL, 0x03); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_PLL2_CTRL"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_PLL2_VCO_DIV, init->pll2Settings.rfDivider); /*VCO divider*/ + DEBUG_AD9025_REG(AD9528_ADDR_PLL2_VCO_DIV, init->pll2Settings.rfDivider); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_PLL2_VCO_DIV"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_PLL2_LF_CTRL1, 0x2A); /*PLL2 Loop filter [7:0]*/ + DEBUG_AD9025_REG( AD9528_ADDR_PLL2_LF_CTRL1, 0x2A); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_PLL2_LF_CTRL1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_PLL2_LF_CTRL2, 0x00); /*PLL2 Loop filter [8]*/ + DEBUG_AD9025_REG(AD9528_ADDR_PLL2_LF_CTRL2, 0x00); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_PLL2_LF_CTRL2"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_PLL2_REPLICA_CHDIV, init->pll2Settings.n2Divider - 1); /*N2 Divider*/ + DEBUG_AD9025_REG( AD9528_ADDR_PLL2_REPLICA_CHDIV, init->pll2Settings.n2Divider - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_PLL2_REPLICA_CHDIV"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_PLL2_REPLICA_DIV_PHASE, 0x00); /*Replica Channel Divider phase*/ + DEBUG_AD9025_REG(AD9528_ADDR_PLL2_REPLICA_DIV_PHASE, 0x00); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_PLL2_REPLICA_DIV_PHASE"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_PLL2_RDIV, init->pll2Settings.r1Divider); /*R1 Divider*/ + DEBUG_AD9025_REG(AD9528_ADDR_PLL2_RDIV, init->pll2Settings.r1Divider); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_PLL2_RDIV"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (init->pll2Settings.r1Divider > 1) + { + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_PLL2_VCO_CTRL, 0x11); /*Enable R1*/ + DEBUG_AD9025_REG(AD9528_ADDR_PLL2_VCO_CTRL, 0x11); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_PLL2_VCO_CTRL"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_PLL2_VCO_CTRL, 0x01); /*Manual VCO CAL*/ + DEBUG_AD9025_REG(AD9528_ADDR_PLL2_VCO_CTRL, 0x01); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_PLL2_VCO_CTRL"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /********************************************************************** + * Configure Output Distribution + **********************************************************************/ + for (i = 0; i<14; i = i + 1) { + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_CH_OUT0_CTRL1 + j, ((init->outputSettings.outSource[i] & 0x7) << 5) | (init->outputSettings.outAnalogDelay[i] & 0x1F)); + DEBUG_AD9025_REG(AD9528_ADDR_CH_OUT0_CTRL1 + j, ((init->outputSettings.outSource[i] & 0x7) << 5) | (init->outputSettings.outAnalogDelay[i] & 0x1F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write an AD9528_ADDR_CH_OUT0_CTRL1 register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_CH_OUT0_CTRL2 + j, ((init->outputSettings.outBufferCtrl[i] & 0x3) << 6) | (init->outputSettings.outDigitalDelay[i] & 0x3F)); + DEBUG_AD9025_REG(AD9528_ADDR_CH_OUT0_CTRL2 + j, ((init->outputSettings.outBufferCtrl[i] & 0x3) << 6) | (init->outputSettings.outDigitalDelay[i] & 0x3F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write an AD9528_ADDR_CH_OUT0_CTRL2 register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_CH_OUT0_CHDIV + j, init->outputSettings.outChannelDiv[i] - 1); + DEBUG_AD9025_REG(AD9528_ADDR_CH_OUT0_CHDIV + j, init->outputSettings.outChannelDiv[i] - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write an AD9528_ADDR_CH_OUT0_CHDIV register"); + ADI_ERROR_RETURN(device->common.error.newAction); + j = j + 3; + } + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_OUTPUT_SYNC, 0x00); /*Sync outputs*/ + DEBUG_AD9025_REG(AD9528_ADDR_OUTPUT_SYNC, 0x00); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_OUTPUT_SYNC"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_MASK_SYNC1, 0x00); /*Mask SYNC[7:0]*/ + DEBUG_AD9025_REG(AD9528_ADDR_MASK_SYNC1, 0x00); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_MASK_SYNC1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_MASK_SYNC2, 0x00); /*Mask SYNC[13:8]*/ + DEBUG_AD9025_REG(AD9528_ADDR_MASK_SYNC2, 0x00); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_MASK_SYNC2"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_EN_OUTPUT_PATH_SEL1, 0x00); /*Bypass SYSREF resample [6:0], bit0:Enable VCXO to feed output distribution*/ + DEBUG_AD9025_REG(AD9528_ADDR_EN_OUTPUT_PATH_SEL1, 0x00); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_EN_OUTPUT_PATH_SEL1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_EN_OUTPUT_PATH_SEL2, 0x00); /*Bypass SYSREF resample [13:7]*/ + DEBUG_AD9025_REG(AD9528_ADDR_EN_OUTPUT_PATH_SEL2, 0x00); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_EN_OUTPUT_PATH_SEL2"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /********************************************************************** + * Configure SYSREF operation + **********************************************************************/ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_SYSERF_DIV_LSB, init->sysrefSettings.sysrefDivide & 0xFF); /*SYSREF divider [7:0]*/ + DEBUG_AD9025_REG(AD9528_ADDR_SYSERF_DIV_LSB, init->sysrefSettings.sysrefDivide & 0xFF); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_SYSERF_DIV_LSB"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_SYSERF_DIV_MSB, (init->sysrefSettings.sysrefDivide >> 8) & 0xFF); /*SYSREF divider [7:0]*/ + DEBUG_AD9025_REG(AD9528_ADDR_SYSERF_DIV_MSB, (init->sysrefSettings.sysrefDivide >> 8) & 0xFF); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_SYSERF_DIV_MSB"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_SYSREF_CTRL3, ((init->sysrefSettings.sysrefRequestMethod & 0x1) << 7) | + ((init->sysrefSettings.sysrefPinEdgeMode & 0x3) << 5)); + DEBUG_AD9025_REG( AD9528_ADDR_SYSREF_CTRL3, ((init->sysrefSettings.sysrefRequestMethod & 0x1) << 7) | + ((init->sysrefSettings.sysrefPinEdgeMode & 0x3) << 5)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_SYSREF_CTRL3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + device->devStateInfo.sysrefCtrlReg403Init = ((init->sysrefSettings.sysrefSource & 0x03) << 6) | + ((init->sysrefSettings.sysrefPatternMode & 0x3) << 4) | + ((init->sysrefSettings.sysrefNshotMode & 0x7) << 1); + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_SYSREF_CTRL4, device->devStateInfo.sysrefCtrlReg403Init); + DEBUG_AD9025_REG(AD9528_ADDR_SYSREF_CTRL4, device->devStateInfo.sysrefCtrlReg403Init); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_SYSREF_CTRL4"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (init->sysrefSettings.sysrefPinBufferMode == ADI_AD9528_DISABLED) + { + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_SYSREF_CTRL5, 0x04); /*power down input buffer for external SYSREF*/ + } + else if (init->sysrefSettings.sysrefPinBufferMode == ADI_AD9528_SINGLE_ENDED) + { + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_SYSREF_CTRL5, 0x00); /*enable positive singled ended input*/ + } + else if (init->sysrefSettings.sysrefPinBufferMode == ADI_AD9528_NEG_SINGLE_ENDED) + { + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_SYSREF_CTRL5, 0x02); /*enable negative singled ended input*/ + } + else if (init->sysrefSettings.sysrefPinBufferMode == ADI_AD9528_DIFFERENTIAL) + { + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_SYSREF_CTRL5, 0x01); /*enable differential input buffer*/ + } + else + { + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_SYSREF_CTRL5, 0x04); /*power down input buffer for external SYSREF*/ + } + DEBUG_AD9025_REG(AD9528_ADDR_SYSREF_CTRL5, 0x04); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_SYSREF_CTRL5"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set the info variable */ + device->devStateInfo.sysrefPatternMode = init->sysrefSettings.sysrefPatternMode; + + /********************************************************************** + * Power down control + **********************************************************************/ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_POWERDOWN_CTRL, 0x10);/* power up PLL1, PLL2 and output distribution*/ + DEBUG_AD9025_REG(AD9528_ADDR_POWERDOWN_CTRL, 0x10); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_POWERDOWN_CTRL"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_CH_POWERDOWN1, init->outputSettings.outPowerDown & 0xFF); /*power down out[7:0]*/ + DEBUG_AD9025_REG(AD9528_ADDR_CH_POWERDOWN1, init->outputSettings.outPowerDown & 0xFF); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_CH_POWERDOWN1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_CH_POWERDOWN2, ((init->outputSettings.outPowerDown >> 8) & 0x3F)); /*power down out[13:8]*/ + DEBUG_AD9025_REG(AD9528_ADDR_CH_POWERDOWN2, ((init->outputSettings.outPowerDown >> 8) & 0x3F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_CH_POWERDOWN2"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_LDO_ENABLES1, 0xFF); /*LDO enable per output channel [7:0]*/ + DEBUG_AD9025_REG(AD9528_ADDR_LDO_ENABLES1, 0xFF); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_LDO_ENABLES1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_LDO_ENABLES2, 0xFF); /*LDO enable per output channel [15:8]*/ + DEBUG_AD9025_REG(AD9528_ADDR_LDO_ENABLES2, 0xFF); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_LDO_ENABLES2"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_STATUS0_CTRL, 0x01); /*STATUS 0 outputs REFA present*/ + DEBUG_AD9025_REG(AD9528_ADDR_STATUS0_CTRL, 0x01); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_STATUS0_CTRL"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_STATUS1_CTRL, 0x07); /*STATUS 1 outputs PLL1 and PLL2 locked*/ + DEBUG_AD9025_REG(AD9528_ADDR_STATUS1_CTRL, 0x07); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_STATUS1_CTRL"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_STATUS_OE, 0x0C);/* Make Status0 and Status1 outputs after reset.*/ + DEBUG_AD9025_REG(AD9528_ADDR_STATUS_OE, 0x0C); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_STATUS_OE"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_IO_UPDATE, 0x01); /*IO update to make all these settings valid in the 9528*/ + DEBUG_AD9025_REG(AD9528_ADDR_IO_UPDATE, 0x01); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_IO_UPDATE"); + ADI_ERROR_RETURN(device->common.error.newAction); + + device->lockStatusExpectedValue = 0; + + if (init->pll1Settings.refA_bufferCtrl != ADI_AD9528_DISABLED) + { + device->lockStatusExpectedValue |= 0x04; /* bit 2 is REFA detected status */ + } + + if (init->pll1Settings.refB_bufferCtrl != ADI_AD9528_DISABLED) + { + device->lockStatusExpectedValue |= 0x08; /* bit 3 is REFB detected status */ + } + + /* If PLL 1 is enabled */ + if (init->pll1Settings.nDividerPll1 != 0) + { + device->lockStatusExpectedValue |= 0x41; /* bit 6 is PLL1 feedback detected status, bit 0 is pll1 locked status */ + } + + /* PLL2 is always enabled */ + device->lockStatusExpectedValue |= 0x82; /* bit 7 is PLL2 feedback detected status, bit 1 is pll2 locked status */ + + /* VCXO should always be present */ + device->lockStatusExpectedValue |= 0x20; /* bit 5 is VCXO detected status*/ + + if (init->pllLockTimeout_ms != 0) + { + recoveryAction = adi_ad9528_PllLockDebounce(device, init->pllLockTimeout_ms); + } + + return recoveryAction; +} + +int32_t adi_ad9528_SysrefRequest(adi_ad9528_Device_t *device, uint8_t enableSYSREF) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t enableSysrefBit = 0; + uint8_t reg403 = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_AD9528_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + if (device->devStateInfo.sysrefPatternMode == ADI_AD9528_NSHOT || enableSYSREF > 0) + { + enableSysrefBit = 0x01; + } + else + { + enableSysrefBit = 0x00; + } + + reg403 = (device->devStateInfo.sysrefCtrlReg403Init | enableSysrefBit); + + /* Set SPI SYSREF request bit */ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_SYSREF_CTRL4, reg403); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_SYSREF_CTRL4"); + ADI_ERROR_RETURN(device->common.error.newAction); + + + /* IO update to make all these settings valid in the 9528 */ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_IO_UPDATE, 0x01); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_IO_UPDATE"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_ad9528_SysrefSetup(adi_ad9528_Device_t *device, adi_ad9528_SysrefSettings_t *sysrefSettings) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t reg403 = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + /* Check spi settings is not null */ + ADI_NULL_PTR_RETURN(&device->common, sysrefSettings); + +#if ADI_AD9528_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + device->devStateInfo.sysrefPatternMode = sysrefSettings->sysrefPatternMode; + + recoveryAction = adi_ad9528_SpiByteRead(device, AD9528_ADDR_SYSREF_CTRL4, ®403); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not read to register AD9528_ADDR_SYSREF_CTRL4"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* clear bit 0 to stop a continuous sysref if it is on. */ + reg403 = reg403 & ~0x01; + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_SYSREF_CTRL4, reg403); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_SYSREF_CTRL4"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* clear bits for pattern mode and Nshot mode bitfields */ + reg403 = reg403 & ~0x3E; + reg403 = reg403 | ((sysrefSettings->sysrefPatternMode & 0x3) << 4) | ((sysrefSettings->sysrefNshotMode & 0x7) << 1); + /* update internal sysref pattern mode and Nshot mode (number of pulses) */ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_SYSREF_CTRL4, reg403); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_SYSREF_CTRL4"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* SYSREF request bit x403[0] is left 0. The next call to AD9528_requestSysref will start the SYSREF */ + /* IO update to make all these settings valid in the 9528 */ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_IO_UPDATE, 0x01); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_IO_UPDATE"); + ADI_ERROR_RETURN(device->common.error.newAction); + + + return recoveryAction; +} + +int32_t adi_ad9528_ClockOutputsEnable(adi_ad9528_Device_t *device, uint16_t clkEnable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_AD9528_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + /* clkEnable: bit per clock output */ + /* power down out[7:0] */ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_CH_POWERDOWN1, ~clkEnable & 0xFF); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_CH_POWERDOWN1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* power down out[13:8] */ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_CH_POWERDOWN2, ((~clkEnable >> 8) & 0x3F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_CH_POWERDOWN2"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* IO update to make all these settings valid in the 9528 */ + recoveryAction = adi_ad9528_SpiByteWrite(device, AD9528_ADDR_IO_UPDATE, 0x01); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "AD9528 could not write to register AD9528_ADDR_IO_UPDATE"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_ad9528_PllLockDebounce(adi_ad9528_Device_t *device, uint32_t timeout_ms) +{ + uint8_t reg508 = 0; + uint8_t i = 0; + uint32_t numLoops = 0; + uint32_t lockCount = ADI_AD9528_PLL_DEBOUNCE_TIME_MS / ADI_AD9528_PLL_DEBOUNCE_INT_MS; + uint8_t lockFlag = 0; + int32_t recoveryAction = 0; + + if (timeout_ms < ADI_AD9528_PLL_DEBOUNCE_TIME_MS) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Timeout must be greater than ADI_AD9528_PLL_DEBOUNCE_TIME_MS"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Check lock status in 10ms intervals*/ + numLoops = (uint32_t)ceil(((double)timeout_ms) / ADI_AD9528_PLL_DEBOUNCE_INT_MS); + } + + /* read twice to refresh status bits */ + recoveryAction = adi_ad9528_SpiByteRead(device, AD9528_ADDR_STATUS_READBACK0, ®508); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_SPI_FAIL, recoveryAction, NULL, "Error reading SPI"); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < numLoops; i++) + { + adi_ad9528_SpiByteRead(device, AD9528_ADDR_STATUS_READBACK0, ®508); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((reg508 & device->lockStatusExpectedValue) != device->lockStatusExpectedValue) + { + lockCount = ADI_AD9528_PLL_DEBOUNCE_TIME_MS / ADI_AD9528_PLL_DEBOUNCE_INT_MS; + } + else + { + lockCount--; + if (lockCount == 0) + { + lockFlag = 1; + break; + } + } + + adi_common_hal_Wait_ms(&device->common, ADI_AD9528_PLL_DEBOUNCE_INT_MS); + } + + if (lockFlag == 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_AD9528_ERR_PLL_LOCK_FAILED, ADI_COMMON_ACT_ERR_RESET_MODULE, NULL, "Ad9528 PLL Not locked"); + return ADI_COMMON_ACT_ERR_RESET_MODULE; + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adi_ad9528_PllLockStatusGet(adi_ad9528_Device_t *device, uint8_t *status) +{ + uint8_t reg508 = 0; + int32_t recoveryAction = 0; + + /* read twice to refresh status bits */ + recoveryAction = adi_ad9528_SpiByteRead(device, AD9528_ADDR_STATUS_READBACK0, ®508); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_SPI_FAIL, recoveryAction, NULL, "Error reading SPI"); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_ad9528_SpiByteRead(device, AD9528_ADDR_STATUS_READBACK0, ®508); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* if status is a valid pointer, return the PLL status */ + if (status != NULL) + { + *status = reg508; + } + + /* PLLs 1 and 2 are locked and VCXO and REFA detected if reg508 has bits 5,2,1 and 0 set */ + if ((reg508 & device->lockStatusExpectedValue) == device->lockStatusExpectedValue) + { + return ADI_COMMON_ACT_NO_ACTION; + } + else + { + return ADI_COMMON_ACT_ERR_RESET_MODULE; + } +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/src/adi_ad9528_hal.c b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/src/adi_ad9528_hal.c new file mode 100644 index 0000000..ac724ae --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/src/adi_ad9528_hal.c @@ -0,0 +1,89 @@ +/** +* \file adi_ad9528_hal.c +* \brief Contains ADI AD9528 Clock Generator Hardware Abstraction functions +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +*/ +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ +#include "adi_ad9528_user.h" +#include "adi_ad9528_hal.h" +#include "adi_common_error.h" +#include "adi_common_hal.h" + + +int32_t adi_ad9528_SpiByteWrite(adi_ad9528_Device_t *device, uint16_t addr, uint8_t data) +{ + int32_t halError = 0; + int32_t i = 0; + uint8_t txData[3] = { 0 }; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_AD9528_VERBOSE > 0 + ADI_FUNCTION_ENTRY_VARIABLE_LOG(&device->common, ADI_COMMON_LOG_SPI, "%s(0x%04X, 0x%02X)", addr, data); +#endif + + txData[0] = (uint8_t)(0x7F & (addr >> 8)); + txData[1] = (uint8_t)(addr & 0x00FF); + txData[2] = data; + + for (i = 0; i < ADI_AD9528_NUMBER_SPI_RETRY; i++) + { + halError = adi_hal_SpiWrite(device->common.devHalInfo, txData, 3); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_ADI_HAL, halError, ADI_COMMON_ACT_ERR_RESET_INTERFACE, NULL, "SpiWriteByte failed"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adi_ad9528_SpiByteRead(adi_ad9528_Device_t *device, uint16_t addr, uint8_t *data) +{ + int32_t trxHalAction = 0; + int32_t halError = 0; + int32_t i = 0; + uint8_t txData[3] = { 0 }; + uint8_t rxData[3] = { 0 }; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, data); + + txData[0] = (uint8_t)(0x80 | (addr >> 8)); + txData[1] = (uint8_t)(addr & 0x00FF); + txData[2] = 0; + + for (i = 0; i < ADI_AD9528_NUMBER_SPI_RETRY; i++) + { + halError = adi_hal_SpiRead(device->common.devHalInfo, txData, rxData, 3); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_ADI_HAL, halError, ADI_COMMON_ACT_ERR_RESET_INTERFACE, NULL, "SpiWriteByte failed"); + ADI_ERROR_RETURN(device->common.error.newAction); + + *data = rxData[2]; + +#if ADI_AD9528_VERBOSE > 0 + ADI_FUNCTION_ENTRY_VARIABLE_LOG(&device->common, ADI_COMMON_LOG_SPI, "%s(0x%04X, 0x%02X)", addr, data); + if (trxHalAction != 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_ADI_HAL, trxHalAction, ADI_COMMON_ACT_WARN_RESET_LOG, NULL, "Logging failed"); + } +#endif + + return ADI_COMMON_ACT_NO_ACTION; +} + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/src/adi_ad9528_utilities.c b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/src/adi_ad9528_utilities.c new file mode 100644 index 0000000..82c5f92 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/ad9528/public/src/adi_ad9528_utilities.c @@ -0,0 +1,564 @@ +/** +* \file adi_ad9528_utilities.c +* \brief Contains source code for AD9528 utility functions. +*/ +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ +#include "adi_ad9528_user.h" +#include "adi_ad9528_utilities.h" +#include "adi_common_error.h" +#include "adi_common_error_types.h" +#include +#include +#include +#include +#include + + +int32_t adi_ad9528_ConfigFileLoad(const char *configFile, adi_ad9528_Init_t *init) +{ + FILE *fp; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + char line[ADI_AD9528_MAX_BUFFER]; + char *id_string; + uint8_t ad9528 = 0; + uint8_t outSource = 0; + uint8_t outBufferCtrl = 0; + uint8_t outAnalogDelay = 0; + uint8_t outDigitalDelay = 0; + uint8_t outChannelDiv = 0; + uint8_t outFrequency_Hz = 0; + //void *outArrayHelper = 0; + int32_t index = 0; + //uint8_t outArrayFillFlag = 0; + uint32_t int32; + int32_t ret; + +#ifdef __GNUC__ + fp = fopen(configFile, "r"); +#else + fopen_s(&fp, configFile, "r"); +#endif + + if (fp == NULL) + { + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + + while (fgets(line, ADI_AD9528_MAX_BUFFER, fp)) + { + + if (!ad9528 && strstr(line, "deviceId) != 1) + { + (void)fclose(fp); + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + } +#else + if (sscanf_s(id_string, "id=%u", &init->deviceId) != 1) + { + (void)fclose(fp); + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + } +#endif + } + else + { + init->deviceId = 0; + } + ad9528 = 1; + continue; + } + + if (ad9528) + { + if (strstr(line, "")) + { + break; + } + + if (!outSource && strstr(line, "")) + { + outSource = 1; + //outArrayFillFlag = 1; + //outArrayHelper = init->outputSettings.outSource; + continue; + } + if (outSource && strstr(line, "")) + { + outSource = 0; + //outArrayFillFlag = 0; + index = 0; + continue; + } + + if (!outBufferCtrl && strstr(line, "")) + { + outBufferCtrl = 1; + //outArrayFillFlag = 1; + //outArrayHelper = init->outputSettings.outBufferCtrl; + continue; + } + if (outBufferCtrl && strstr(line, "")) + { + outBufferCtrl = 0; + //outArrayFillFlag = 0; + index = 0; + continue; + } + + if (!outAnalogDelay && strstr(line, "")) + { + outAnalogDelay = 1; + //outArrayFillFlag = 1; + //outArrayHelper = init->outputSettings.outAnalogDelay; + continue; + } + if (outAnalogDelay && strstr(line, "")) + { + outAnalogDelay = 0; + //outArrayFillFlag = 0; + index = 0; + continue; + } + + if (!outDigitalDelay && strstr(line, "")) + { + outDigitalDelay = 1; + //outArrayFillFlag = 1; + //outArrayHelper = init->outputSettings.outDigitalDelay; + continue; + } + if (outDigitalDelay && strstr(line, "")) + { + outDigitalDelay = 0; + //outArrayFillFlag = 0; + index = 0; + continue; + } + + if (!outChannelDiv && strstr(line, "")) + { + outChannelDiv = 1; + //outArrayFillFlag = 1; + // outArrayHelper = init->outputSettings.outChannelDiv; + continue; + } + if (outChannelDiv && strstr(line, "")) + { + outChannelDiv = 0; + //outArrayFillFlag = 0; + index = 0; + continue; + } + + if (!outFrequency_Hz && strstr(line, "")) + { + outFrequency_Hz = 1; + //outArrayFillFlag = 1; + //outArrayHelper = init->outputSettings.outFrequency_Hz; + continue; + } + if (outFrequency_Hz && strstr(line, "")) + { + outFrequency_Hz = 0; + //outArrayFillFlag = 0; + index = 0; + continue; + } + + GET_TOKEN(init->spiSettings, msbFirst, ret, line, &int32, int32); + //GET_TOKEN(init->spiSettings, enSpiStreaming, ret, line, &int32, int32); + GET_TOKEN(init->spiSettings, autoIncAddrUp, ret, line, &int32, int32); + GET_TOKEN(init->spiSettings, fourWireMode, ret, line, &int32, int32); + + GET_TOKEN(init->pll1Settings, refA_Frequency_Hz, ret, line, &int32, int32); + GET_TOKEN(init->pll1Settings, refA_Divider, ret, line, &int32, int32); + GET_TOKEN_CAST(init->pll1Settings, refA_bufferCtrl, adi_ad9528_RefBuffer_e, ret, line, &int32, int32); + GET_TOKEN(init->pll1Settings, refB_Frequency_Hz, ret, line, &int32, int32); + GET_TOKEN(init->pll1Settings, refB_Divider, ret, line, &int32, int32); + GET_TOKEN_CAST(init->pll1Settings, refB_bufferCtrl, adi_ad9528_RefBuffer_e, ret, line, &int32, int32); + GET_TOKEN(init->pll1Settings, vcxo_Frequency_Hz, ret, line, &int32, int32); + GET_TOKEN_CAST(init->pll1Settings, vcxoBufferCtrl, adi_ad9528_RefBuffer_e, ret, line, &int32, int32); + GET_TOKEN(init->pll1Settings, nDividerPll1, ret, line, &int32, int32); + + GET_TOKEN_CAST(init->sysrefSettings, sysrefRequestMethod, adi_ad9528_SysrefRequestMethod_e, ret, line, &int32, int32); + GET_TOKEN_CAST(init->sysrefSettings, sysrefSource, adi_ad9528_SysrefSourceSelection_e, ret, line, &int32, int32); + GET_TOKEN_CAST(init->sysrefSettings, sysrefPinEdgeMode, adi_ad9528_SysrefPinEdgeMode_e, ret, line, &int32, int32); + GET_TOKEN_CAST(init->sysrefSettings, sysrefPinBufferMode, adi_ad9528_RefBuffer_e, ret, line, &int32, int32); + GET_TOKEN_CAST(init->sysrefSettings, sysrefPatternMode, adi_ad9528_SysrefPatternMode_e, ret, line, &int32, int32); + GET_TOKEN_CAST(init->sysrefSettings, sysrefNshotMode, adi_ad9528_SysrefNshotMode_e, ret, line, &int32, int32); + GET_TOKEN(init->sysrefSettings, sysrefDivide, ret, line, &int32, int32); + + GET_TOKEN(init->pll2Settings, rfDivider, ret, line, &int32, int32); + GET_TOKEN(init->pll2Settings, n2Divider, ret, line, &int32, int32); + GET_TOKEN(init->pll2Settings, totalNdiv, ret, line, &int32, int32); + + GET_TOKEN(init->outputSettings, outPowerDown, ret, line, &int32, int32); + + if (outSource) + { + if (index >= ADI_AD9528_NUM_OUTPUT_CHANNELS) + { + (void)fclose(fp); + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + if (sscanf_s(line, " %d", &ret) == 1) { + init->outputSettings.outSource[index++] = (adi_ad9528_OutSourceSel_e)ret; + continue; + } + } + + if (outBufferCtrl) + { + if (index >= ADI_AD9528_NUM_OUTPUT_CHANNELS) + { + (void)fclose(fp); + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + if (sscanf_s(line, " %d", &ret) == 1) { + init->outputSettings.outBufferCtrl[index++] = (adi_ad9528_OutBufferControl_e)ret; + continue; + } + } + + if (outAnalogDelay) + { + if (index >= ADI_AD9528_NUM_OUTPUT_CHANNELS) + { + (void)fclose(fp); + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + if (sscanf_s(line, " %d", &ret) == 1) { + init->outputSettings.outAnalogDelay[index++] = ret; + continue; + } + } + + if (outDigitalDelay) + { + if (index >= ADI_AD9528_NUM_OUTPUT_CHANNELS) + { + (void)fclose(fp); + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + if (sscanf_s(line, " %d", &ret) == 1) { + init->outputSettings.outDigitalDelay[index++] = ret; + continue; + } + } + + if (outChannelDiv) + { + if (index >= ADI_AD9528_NUM_OUTPUT_CHANNELS) + { + (void)fclose(fp); + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + if (sscanf_s(line, " %d", &ret) == 1) { + init->outputSettings.outChannelDiv[index++] = ret; + continue; + } + } + + if (outFrequency_Hz) + { + if (index >= ADI_AD9528_NUM_OUTPUT_CHANNELS) + { + (void)fclose(fp); + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + } + if (sscanf_s(line, " %d", &ret) == 1) { + init->outputSettings.outFrequency_Hz[index++] = ret; + continue; + } + } + } + } + + (void)fclose(fp); + return recoveryAction; +} + +int32_t adi_ad9528_InitStructConfig(adi_ad9528_Device_t *device, adi_ad9528_ClockFrequencySettings_t *clockFrequencies, adi_ad9528_Init_t *init) +{ + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t i = 0; + uint8_t j = 0; + uint32_t pll1PfdFreq_Hz = 0; + uint8_t pll1Ndiv = 0; + uint8_t validPll1DivSetting = 0; + // ? remov warn by daya uint16_t refAdiv = 1; + uint8_t pll2RfDiv = 3; /* Valid values 3,4,5 */ + uint16_t pll2Ndiv = 1; /* Valid values 1-256 */ + uint16_t totalPll2NDiv = 0; + uint8_t pll2R1Div = 1; /* Valid values 1-31 */ + uint32_t pll2InputFreq_Hz = 0; + uint64_t pll2VcoFreq_Hz = 0; + uint64_t pll2VcoDivRFFreq_Hz = 0; + uint16_t pll2NdivStart = 0; + uint8_t validPll2DivSetting = 0; + uint8_t validPll2ChannelDivSetting = 0; + uint64_t chDivU64 = 0; + uint64_t sysrefRetimingClock_Hz = 0; + + static const uint64_t PLL2_MIN_VCO_FREQ_HZ = 3450000000ULL; + static const uint64_t PLL2_MAX_VCO_FREQ_HZ = 4025000000ULL; + static const uint64_t SYSREF_MAX_RETIMING_CLOCK_FREQ_HZ = 1000000000ULL; + + init->outputSettings.outPowerDown = 0; + /******************************************************************* + * PLL1 Settings + ******************************************************************* + */ + + + if (clockFrequencies->refAFrequency_Hz == 0) + { + /* Bypass PLL1, routing VCXO out of PLL1 */ + init->pll1Settings.nDividerPll1 = 0; //This init function always runs PLL1 at 30.72MHz Pfd rate + init->pll1Settings.refA_bufferCtrl = ADI_AD9528_DISABLED; //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL + init->pll1Settings.refA_Divider = 1; + init->pll1Settings.refA_Frequency_Hz = 0; + init->pll1Settings.refB_bufferCtrl = ADI_AD9528_DISABLED; //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL + init->pll1Settings.refB_Divider = 1; + init->pll1Settings.refB_Frequency_Hz = 0; + init->pll1Settings.vcxoBufferCtrl = ADI_AD9528_DIFFERENTIAL; //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL + init->pll1Settings.vcxo_Frequency_Hz = clockFrequencies->vcxoFrequency_Hz; + } + else + { + /* find valid PLL1 Ndiv and REFA div */ + for (pll1Ndiv = 1; pll1Ndiv < 20; pll1Ndiv++) + { + pll1PfdFreq_Hz = clockFrequencies->vcxoFrequency_Hz / pll1Ndiv; + + if ((pll1PfdFreq_Hz <= 110000000) && (pll1PfdFreq_Hz >= 1000000) && + (pll1PfdFreq_Hz <= clockFrequencies->refAFrequency_Hz) && + (clockFrequencies->refAFrequency_Hz % pll1PfdFreq_Hz == 0)) + { + validPll1DivSetting = 1; + // ? remov warn by daya refAdiv = clockFrequencies->refAFrequency_Hz / pll1PfdFreq_Hz; + break; + } + } + + if (validPll1DivSetting == 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ACT_ERR_CHECK_PARAM, ADI_COMMON_ERR_INV_PARAM, NULL, "Cannot find valid settings for PLL1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + init->pll1Settings.nDividerPll1 = 4; //This init function always runs PLL1 at 30.72MHz Pfd rate + init->pll1Settings.refA_bufferCtrl = ADI_AD9528_DIFFERENTIAL; //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL + init->pll1Settings.refA_Divider = 1; + init->pll1Settings.refA_Frequency_Hz = 30720000; + init->pll1Settings.refB_bufferCtrl = ADI_AD9528_DISABLED; //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL + init->pll1Settings.refB_Divider = 1; + init->pll1Settings.refB_Frequency_Hz = 0; + + init->pll1Settings.vcxoBufferCtrl = ADI_AD9528_SINGLE_ENDED; //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL + init->pll1Settings.vcxo_Frequency_Hz = 122880000; // clockFrequencies->vcxoFrequency_Hz; + } + + + + + /******************************************************************* + * PLL2 Settings + ******************************************************************* + */ + + /******************************************************************* + * Output Distribution Settings + * 9369CE02A uses the following clock outputs + * OUT 1: FPGA REFCLK + * OUT 3: FPGA SYSREF + * OUT 12: DUT SYSREF + * OUT 13: DUT REFCLK + ******************************************************************* + */ + + /* PLL 2 input clock can be several different things. Currently hard coded by this init function to use + * PLL 1 output (VCXO Frequency) with no scaling + */ + validPll2DivSetting = 0; + + if ((init->pll1Settings.vcxo_Frequency_Hz == 0) || + (init->pll1Settings.vcxo_Frequency_Hz > 400000000)) + { + /* TODO: VCXO max is 1200MHz if VCXO is in buffer mode */ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ACT_ERR_CHECK_PARAM, + ADI_COMMON_ERR_INV_PARAM, init->pll1Settings.vcxo_Frequency_Hz, + "Invalid VCXO Frequency"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (pll2R1Div = 1; pll2R1Div <= 31; pll2R1Div++) + { + pll2InputFreq_Hz = init->pll1Settings.vcxo_Frequency_Hz / pll2R1Div; + + /* Sweep PLL2 Divider settings to find something that has a valid integer divide (3,4,5)*/ + for (pll2RfDiv = 3; pll2RfDiv <= 5; pll2RfDiv++) + { + pll2NdivStart = (uint16_t)(PLL2_MIN_VCO_FREQ_HZ / pll2RfDiv / pll2InputFreq_Hz); + /* find valid PLL2 Ndiv (1-256) */ + for (pll2Ndiv = pll2NdivStart; pll2Ndiv <= 256; pll2Ndiv++) + { + totalPll2NDiv = pll2RfDiv * pll2Ndiv; + if (totalPll2NDiv < 16) + { + /* Continue to next PLL2 N div */ + continue; + } + + pll2VcoFreq_Hz = (uint64_t)pll2InputFreq_Hz * totalPll2NDiv; + + if (pll2VcoFreq_Hz < PLL2_MIN_VCO_FREQ_HZ) + { + /* Continue to next PLL2 N div */ + continue; + } + else if (pll2VcoFreq_Hz > PLL2_MAX_VCO_FREQ_HZ) + { + /* Break to next PLL2 RF div */ + break; + } + + /* Loop through all desired output settings to make sure + * this PLL2 setting makes them all possible + */ + validPll2ChannelDivSetting = 0; + pll2VcoDivRFFreq_Hz = pll2VcoFreq_Hz / pll2RfDiv; + for (i = 0; i < 14; i++) + { + if ((clockFrequencies->outputClock_Hz[i] != 0) && + ((clockFrequencies->outSource[i] == ADI_AD9528_CHANNEL_DIV) || (clockFrequencies->outSource[i] == ADI_AD9528_SYSREF)) && + ((pll2VcoDivRFFreq_Hz % clockFrequencies->outputClock_Hz[i]) != 0)) + { + validPll2ChannelDivSetting = 1; + break; + } + } + + if (validPll2ChannelDivSetting == 0) + { + + for (i = 0; i < 14; i++) + { + if (clockFrequencies->outputClock_Hz[i] != 0) + { + init->outputSettings.outPowerDown |= (1 << i); + + if (clockFrequencies->outSource[i] == ADI_AD9528_CHANNEL_DIV) + { + chDivU64 = (pll2VcoDivRFFreq_Hz / clockFrequencies->outputClock_Hz[i]); + + if ((chDivU64 < 1) || (chDivU64 > 256)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ACT_ERR_CHECK_PARAM, ADI_COMMON_ERR_INV_PARAM, NULL, "Cannot find valid settings for Channel divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + init->outputSettings.outChannelDiv[i] = (uint16_t)(chDivU64); + init->outputSettings.outAnalogDelay[i] = 0; // daya debug + init->outputSettings.outDigitalDelay[i] = 0;// daya debug + } + } + else if (clockFrequencies->outSource[i] == ADI_AD9528_SYSREF) + { + /* At this point we already guaranteed that pll2VcoDivRFFreq_Hz is multiple of clockFrequencies->outputClock_Hz[i] */ + /* Iterate over all possible divider values, try to find minimum possible divider(i.e.maximize retiming clk freq)*/ + for(j = 1; j <= 255; j++) + { + if((pll2VcoDivRFFreq_Hz % j) == 0) + { + sysrefRetimingClock_Hz = pll2VcoDivRFFreq_Hz / j; + if((sysrefRetimingClock_Hz < SYSREF_MAX_RETIMING_CLOCK_FREQ_HZ) && ((sysrefRetimingClock_Hz % clockFrequencies->outputClock_Hz[i]) == 0)) + { + init->outputSettings.outChannelDiv[i] = 10; // j; + init->outputSettings.outAnalogDelay[i] = (0x10 | 15); // daya debug + init->outputSettings.outDigitalDelay[i] = 5; // daya debug + break; + } + } + } + } + } + + if (init->outputSettings.outChannelDiv[i] == 0) + { + init->outputSettings.outChannelDiv[i] = 20; /* Unused channel output divider, set to a valid value */ + } + + init->outputSettings.outSource[i] = clockFrequencies->outSource[i]; + init->outputSettings.outFrequency_Hz[i] = clockFrequencies->outputClock_Hz[i]; + + /* currently hardcoded to default values */ + init->outputSettings.outBufferCtrl[i] = ADI_AD9528_LVDS; /* LVDS, LVDS_BOOST, HSTL */ + // init->outputSettings.outAnalogDelay[i] = 0; // daya debug + // init->outputSettings.outDigitalDelay[i] = 0; // daya debug + } + + + + /* Only set this to valid after checking the output clock dividers above */ + init->pll2Settings.rfDivider = pll2RfDiv; + init->pll2Settings.totalNdiv = pll2RfDiv * pll2Ndiv; + init->pll2Settings.n2Divider = pll2Ndiv; + init->pll2Settings.r1Divider = pll2R1Div; + validPll2DivSetting = 1; + break; + } + } + + if (validPll2DivSetting == 1) + { + break; + } + } + + if (validPll2DivSetting == 1) + { + break; + } + } + + if (validPll2DivSetting == 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ACT_ERR_CHECK_PARAM, ADI_COMMON_ERR_INV_PARAM, NULL, "Cannot find valid settings for PLL2"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* loop above asserted those bits for used output channels but powerdown bits should be negated */ + init->outputSettings.outPowerDown = (uint16_t)(~init->outputSettings.outPowerDown); + init->sysrefSettings.sysrefDivide = 32; //SYSREF frequency = VCXO / 2 / sysrefDivde + init->sysrefSettings.sysrefNshotMode = ADI_AD9528_EIGHT_PULSES; //ONE_PULSE=0, TWO_PULSES=2, FOUR_PULSES=3, SIX_PULSES=4, EIGHT_PULSES=5 + init->sysrefSettings.sysrefPatternMode = ADI_AD9528_NSHOT; // ADI_AD9528_NSHOT; ; //NSHOT=0, CONTINUOUS=1, PRBS=2, STOP=3 + init->sysrefSettings.sysrefPinBufferMode = ADI_AD9528_DIFFERENTIAL; //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL + init->sysrefSettings.sysrefPinEdgeMode = ADI_AD9528_RISING_EDGE; //LEVEL_ACTIVE_HIGH=0, LEVEL_ACTIVE_LOW=1, RISING_EDGE=2, FALLING_EDGE=3 + init->sysrefSettings.sysrefRequestMethod = ADI_AD9528_SPI; //SPI=0,PIN=1 + init->sysrefSettings.sysrefSource = ADI_AD9528_INTERNAL; //EXTERNAL=0, EXT_RESAMPLED=1, INTERNAL=2 + + /* Default timeout set to 1sec */ + init->pllLockTimeout_ms = 1000; + + /* Default SPI settings */ + init->spiSettings.autoIncAddrUp = 1; + init->spiSettings.fourWireMode = 1; + init->spiSettings.msbFirst = 1; + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/makefile b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/makefile new file mode 100644 index 0000000..691a4d1 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/makefile @@ -0,0 +1,37 @@ +LIB_ADI_ADRV9025_DEVICE = libadi_adrv9025.a +#CC = aarch64-linux-gnu-gcc +ADI_ADRV9025_SRC = ./public/src +ADI_ADRV9025_PRIVATE_SRC = ./private/src +ARFLAGS = -rv +CFLAGS = -Werror -Wall -I./public/include -I../../platforms/ -I../../common -I../../common/adi_error -I../../common/adi_logging -I../../common/adi_hal -I../../../os +ADI_PLATFORM_SRC = ../../platforms +ADI_COMMON_SRC = ../../common +EXT = c + +SRC = $(wildcard $(ADI_ADRV9025_PRIVATE_SRC)/*.$(EXT)) \ + $(wildcard $(ADI_ADRV9025_SRC)/*.$(EXT)) + +OBJS = $(SRC:.$(EXT)=.o) + +all: adi_platform_lib \ + adi_common_lib \ + $(LIB_ADI_ADRV9025_DEVICE) + +.$(EXT).o: + $(CC) $(CFLAGS) -o $@ -c $< + +$(LIB_ADI_ADRV9025_DEVICE): $(OBJS) + ar $(ARFLAGS) $(LIB_ADI_ADRV9025_DEVICE) $(OBJS) + +adi_platform_lib: + $(MAKE) -C $(ADI_PLATFORM_SRC) + +adi_common_lib: + $(MAKE) -C $(ADI_COMMON_SRC) + +clean: + rm -rf $(ADI_ADRV9025_SRC)/*.o + rm -rf $(ADI_ADRV9025_PRIVATE_SRC)/*.o + rm -rf *.a + $(MAKE) -C $(ADI_PLATFORM_SRC) clean + $(MAKE) -C $(ADI_COMMON_SRC) clean \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_orx_mem_map.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_orx_mem_map.h new file mode 100644 index 0000000..99c2a1a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_orx_mem_map.h @@ -0,0 +1,31 @@ +/** + * \file Automatically generated file: adrv9025_bf_analog_orx_mem_map.h + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_ANALOG_ORX_MEM_MAP_H__ +#define __ADRV9025_BF_ANALOG_ORX_MEM_MAP_H__ +#include "./../../private/include/adrv9025_bf_analog_orx_mem_map_types.h" +#include "adi_adrv9025.h" +#ifdef __cplusplus +extern "C"{ +#endif + +int32_t adrv9025_AnalogOrxMemMapLomuxSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogOrxMemMapChanAddr_e baseAddr, + uint8_t* bfValue); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_orx_mem_map_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_orx_mem_map_types.h new file mode 100644 index 0000000..4aa9589 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_orx_mem_map_types.h @@ -0,0 +1,35 @@ +/** + * \file adrv9025_bf_analog_orx_mem_map_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_ANALOG_ORX_MEM_MAP_TYPES_H__ +#define __ADRV9025_BF_ANALOG_ORX_MEM_MAP_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum adrv9025_BfAnalogOrxMemMapChanAddr +{ + ADRV9025_BF_ANALOG_ORX_CH0 = 0x4C00, + ADRV9025_BF_ANALOG_ORX_CH1 = 0x5400 +} adrv9025_BfAnalogOrxMemMapChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __ADRV9025_BF_ANALOG_ORX_MEM_MAP_TYPES_H__ + +/* EOF: adrv9025_bf_analog_orx_mem_map_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_rx_mem_map.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_rx_mem_map.h new file mode 100644 index 0000000..9f1adcb --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_rx_mem_map.h @@ -0,0 +1,55 @@ +/** + * \file Automatically generated file: adrv9025_bf_analog_rx_mem_map.h + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_ANALOG_RX_MEM_MAP_H__ +#define __ADRV9025_BF_ANALOG_RX_MEM_MAP_H__ +#include "./../../private/include/adrv9025_bf_analog_rx_mem_map_types.h" +#include "adi_adrv9025.h" +#ifdef __cplusplus +extern "C"{ +#endif + +int32_t adrv9025_AnalogRxMemMapRxBlockDetDecayBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogRxMemMapChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_AnalogRxMemMapRxBlockDetLlbthBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogRxMemMapChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t adrv9025_AnalogRxMemMapRxBlockDetLlbthBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogRxMemMapChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_AnalogRxMemMapRxBlockDetUlbthBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogRxMemMapChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t adrv9025_AnalogRxMemMapRxBlockDetUlbthBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogRxMemMapChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_AnalogRxMemMapRxTiaForceUpdateBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogRxMemMapChanAddr_e baseAddr, + uint8_t bfValue); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_rx_mem_map_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_rx_mem_map_types.h new file mode 100644 index 0000000..06b6892 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_rx_mem_map_types.h @@ -0,0 +1,38 @@ +/** + * \file adrv9025_bf_analog_rx_mem_map_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_ANALOG_RX_MEM_MAP_TYPES_H__ +#define __ADRV9025_BF_ANALOG_RX_MEM_MAP_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum adrv9025_BfAnalogRxMemMapChanAddr +{ + ADRV9025_BF_ALL_ANALOG_RX = 0xC00, + ADRV9025_BF_ANALOG_RX_CH1 = 0x2C00, + ADRV9025_BF_ANALOG_RX_CH2 = 0x3400, + ADRV9025_BF_ANALOG_RX_CH3 = 0x3C00, + ADRV9025_BF_ANALOG_RX_CH0 = 0x4400 +} adrv9025_BfAnalogRxMemMapChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif /* __ADRV9025_BF_ANALOG_RX_MEM_MAP_TYPES_H__ */ + +/* EOF: adrv9025_bf_analog_rx_mem_map_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_tx_mem_map.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_tx_mem_map.h new file mode 100644 index 0000000..6d8d2b8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_tx_mem_map.h @@ -0,0 +1,79 @@ +/** + * \file Automatically generated file: adrv9025_bf_analog_tx_mem_map.h + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_ANALOG_TX_MEM_MAP_H__ +#define __ADRV9025_BF_ANALOG_TX_MEM_MAP_H__ +#include "./../../private/include/adrv9025_bf_analog_tx_mem_map_types.h" +#include "adi_adrv9025.h" +#ifdef __cplusplus +extern "C"{ +#endif + +int32_t adrv9025_AnalogTxMemMapAuxdac0BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_AnalogTxMemMapAuxdac0BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_AnalogTxMemMapAuxdac0ConfigBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_AnalogTxMemMapAuxdac1BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_AnalogTxMemMapAuxdac1BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_AnalogTxMemMapAuxdac1ConfigBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_AnalogTxMemMapAuxdac2BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_AnalogTxMemMapAuxdac2BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_AnalogTxMemMapAuxdac2ConfigBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_AnalogTxMemMapAuxdac3BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_AnalogTxMemMapAuxdac3BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_AnalogTxMemMapAuxdac3ConfigBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_AnalogTxMemMapAuxdacLatchEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint8_t bfValue); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_tx_mem_map_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_tx_mem_map_types.h new file mode 100644 index 0000000..d6bfd83 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_analog_tx_mem_map_types.h @@ -0,0 +1,38 @@ +/** + * \file adrv9025_bf_analog_tx_mem_map_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_ANALOG_TX_MEM_MAP_TYPES_H__ +#define __ADRV9025_BF_ANALOG_TX_MEM_MAP_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum adrv9025_BfAnalogTxMemMapChanAddr +{ + ADRV9025_BF_ALL_ANALOG_TX = 0xE00, + ADRV9025_BF_ANALOG_TX_CH1 = 0x5C00, + ADRV9025_BF_ANALOG_TX_CH2 = 0x5E00, + ADRV9025_BF_ANALOG_TX_CH3 = 0x6000, + ADRV9025_BF_ANALOG_TX_CH0 = 0x6200 +} adrv9025_BfAnalogTxMemMapChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __ADRV9025_BF_ANALOG_TX_MEM_MAP_TYPES_H__ + +/* EOF: adrv9025_bf_analog_tx_mem_map_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_core.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_core.h new file mode 100644 index 0000000..e78834f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_core.h @@ -0,0 +1,439 @@ +/** + * \file Automatically generated file: adrv9025_bf_core.h + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_CORE_H__ +#define __ADRV9025_BF_CORE_H__ +#include "./../../private/include/adrv9025_bf_core_types.h" +#include "adi_adrv9025.h" +#ifdef __cplusplus +extern "C"{ +#endif + +int32_t adrv9025_CoreArmCommandBusyBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreArmDCommandBusyBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreArmM3RunBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreArmOverrideControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreArmOverrideControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreAuxAdcClkDivide1BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreAuxAdcClkDivide1BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreAuxAdcClkDivide2BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreAuxAdcClkDivide2BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreAuxAdcClkPd1BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreAuxAdcClkPd2BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreEnCtrl0BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreEnCtrl0BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreEnCtrl1BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreEnCtrl1BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreEnCtrl2BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreEnCtrl2BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreEnCtrl3BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreEnCtrl3BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreEnCtrl4BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreEnCtrl4BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreEnCtrl5BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreEnCtrl5BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreEnCtrl6BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreEnCtrl6BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreEnCtrl7BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreEnCtrl7BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreGpInterruptsMaskPin0BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint64_t bfValue); + +int32_t adrv9025_CoreGpInterruptsMaskPin0BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint64_t* bfValue); + +int32_t adrv9025_CoreGpInterruptsMaskPin1BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint64_t bfValue); + +int32_t adrv9025_CoreGpInterruptsMaskPin1BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint64_t* bfValue); + +int32_t adrv9025_CoreGpInterruptsStatusWordBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint64_t* bfValue); + +int32_t adrv9025_CoreGpInterruptsStickyBitMaskBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint64_t bfValue); + +int32_t adrv9025_CoreGpInterruptsStickyBitMaskBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint64_t* bfValue); + +int32_t adrv9025_CoreGpioAnalogDirectionControlOeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreGpioAnalogDirectionControlOeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreGpioAnalogLowerNibbleSourceControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreGpioAnalogLowerNibbleSourceControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreGpioAnalogUpperNibbleSourceControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreGpioAnalogUpperNibbleSourceControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreGpioDirectionControlOeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t adrv9025_CoreGpioDirectionControlOeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t adrv9025_CoreGpioExtraBitsSourceControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreGpioExtraBitsSourceControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreGpioLowerByteLowerNibbleSourceControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreGpioLowerByteLowerNibbleSourceControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreGpioSpiReadBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t adrv9025_CoreGpioSpiSourceBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t adrv9025_CoreGpioSpiSourceBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreMonitorOutBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreMonitorOutBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreOrxEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreOrxEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreOrxPinModeEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreOrxPinModeEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreOrxPinModeUsingSpiSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreOrxPinModeUsingSpiSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreOrxSelectInPinModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreOrxSelectInPinModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreOrxSingleChannelModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreOrxSingleChannelModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreOrxSingleChannelMode1aBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreOrxSingleChannelMode1aBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreOrxSingleChannelMode1aHighChannelEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreOrxSingleChannelMode1aHighChannelEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreOrxSingleChannelMode1aLowChannelEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreOrxSingleChannelMode1aLowChannelEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CorePdAuxdacBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CorePdAuxdacBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CorePinSelectSettlingDelayBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CorePinSelectSettlingDelayBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreRxOrxAnySourceMuxSel10BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreRxOrxAnySourceMuxSel10BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreRxOrxAnySourceMuxSel32BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreRxOrxAnySourceMuxSel32BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreRxOrxAnySourceMuxSel54BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreRxOrxAnySourceMuxSel54BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreRxOrxAnySourceMuxSel76BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreRxOrxAnySourceMuxSel76BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreRxSync1PadLvdsModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreRxSync1PadLvdsPnInvBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreRxSync2PadLvdsModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreRxSync2PadLvdsPnInvBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreRxSync3PadLvdsModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreRxSync3PadLvdsPnInvBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreSpi2EnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreSpi2EnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreStreamProcGpioPinMaskBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_CoreStreamProcGpioPinMaskBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_CoreTxAttenUpdCoreSpiBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreTxAttenUpdCoreSpiEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_CoreTxAttenUpdCoreSpiEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreTxSync1PadLvdsModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreTxSync1PadLvdsPnInvBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreTxSync2PadLvdsModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreTxSync2PadLvdsPnInvBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_CoreTxSyncDrvSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_core_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_core_types.h new file mode 100644 index 0000000..105f022 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_core_types.h @@ -0,0 +1,34 @@ +/** + * \file adrv9025_bf_core_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_CORE_TYPES_H__ +#define __ADRV9025_BF_CORE_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum adrv9025_BfCoreChanAddr +{ + ADRV9025_BF_CORE = 0x0 +} adrv9025_BfCoreChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif /* __ADRV9025_BF_CORE_TYPES_H__ */ + +/* EOF: adrv9025_bf_core_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_deser.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_deser.h new file mode 100644 index 0000000..85a5ef1 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_deser.h @@ -0,0 +1,47 @@ +/** + * \file Automatically generated file: adrv9025_bf_deser.h + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_DESER_H__ +#define __ADRV9025_BF_DESER_H__ +#include "./../../private/include/adrv9025_bf_deser_types.h" +#include "adi_adrv9025.h" +#ifdef __cplusplus +extern "C"{ +#endif + +int32_t adrv9025_DeserCbusAddrDesRcBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfDeserChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_DeserCbusRdataDesRsBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfDeserChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_DeserCbusRenDesRcChBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfDeserChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_DeserCbusWdataDesRcBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfDeserChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_DeserCbusWstrobeDesRcChBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfDeserChanAddr_e baseAddr, + uint8_t bfValue); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_deser_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_deser_types.h new file mode 100644 index 0000000..fec273f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_deser_types.h @@ -0,0 +1,49 @@ +/** + * \file adrv9025_bf_deser_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support ADRV9025 transciever device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_DESER_TYPES_H__ +#define __ADRV9025_BF_DESER_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum adrv9025_BfDeserChanAddr +{ + ADRV9025_BF_JESD_DESERIALIZER = 0x6800 +} adrv9025_BfDeserChanAddr_e; + +/** + * \brief Enumeration for rxdivrateLcpllRc + */ +typedef enum adrv9025_BfDeserRxdivrateLcpllRc +{ + ADRV9025_BF_DESER_RXDIVRATE_LCPLL_RC_8 = 8 /*!< Half-rate CDR; 1X oversampling */ +} adrv9025_BfDeserRxdivrateLcpllRc_e; +/** + * \brief Enumeration for rxdivrateLcpllRs + */ +typedef enum adrv9025_BfDeserRxdivrateLcpllRs +{ + ADRV9025_BF_DESER_RXDIVRATE_LCPLL_RS_8 = 8 /*!< Half-rate CDR; 1X oversampling */ +} adrv9025_BfDeserRxdivrateLcpllRs_e; +#ifdef __cplusplus +} +#endif + +#endif // __ADRV9025_BF_DESER_TYPES_H__ + +/* EOF: adrv9025_bf_deser_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_hal.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_hal.h new file mode 100644 index 0000000..dd46e45 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_hal.h @@ -0,0 +1,268 @@ +#ifndef ADRV9025_BF_HAL_H_ +#define ADRV9025_BF_HAL_H_ + +#include +#include + +#include "adi_adrv9025.h" +#include "adi_common_hal.h" +#include "./../../private/include/adrv9025_bf_hal_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief allows the user to set the Write cache state. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param wrCacheState the cache state to be set. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adrv9025_BfWriteCacheEn(adi_adrv9025_Device_t* device, + adrv9025_Bf_WrCache_State_e wrCacheState); + +/** +* \brief allows the user to set the read cache state. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param rdCacheState the cache state to be set. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adrv9025_BfReadCacheEn(adi_adrv9025_Device_t* device, + adrv9025_Bf_RdCache_State_e rdCacheState); + +/** +* \brief ensures the cache is empty. if not it writes the cache to the part. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* +* \retval ADRV9025_ Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adrv9025_BfReadCacheInit(adi_adrv9025_Device_t* device); + +/** +* \brief ensures the cache is empty. if not it writes the cache to the part. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adrv9025_BfWriteCacheInit(adi_adrv9025_Device_t* device); + +/** +* \brief Used to read a register. +* Merges the write if merging is on +* Caches the write if caching is on, +* Immediately writes the value if caching is off. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep{SPIARRAYSIZE} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param addr The address of the Register to read. +* \param regVal The value to be written to the register. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adrv9025_BfByteWrite(adi_adrv9025_Device_t* device, + uint16_t addr, + uint8_t regVal); + +/** +* \brief Used to read a register. +* Caches the read if caching is on, immediately reads the value with caching off. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep{ADRV9025_BF_RDCACHE_ARRAY_TRIP_SIZE} +* \dep{SPIARRAYSIZE} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param addr The address of the Register to read. +* \param regVal The value of the register just read. +* \param endOfBf when using read caching the upper nibble of this field indicates the end of bitfield with the Value F. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adrv9025_BfByteRead(adi_adrv9025_Device_t* device, + uint16_t addr, + uint8_t* regVal, + uint8_t endOfBf); + +/** +* \brief Used to write to a sub part of a register. +* Caches the write if caching is on, immediately writes the value with caching off. +* Uses the HW_RMW function if the HW_RMW is enabled otherwise used a spi transaction to read the register +* and a spi write transaction to write the modified byte back to the register. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep{SPIARRAYSIZE} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param addr The Register address that contains the field. +* \param fieldVal The value of the field to be written. +* \param mask The mask to use when inserting the data into the register. +* \param startBit The location of the first bit of the field within the register. +* when using read caching the upper nibble of this field indicates the end of bitfield with the Value F. +* This value is used to shift the value so that it aligns with the location of the field within the register. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adrv9025_BfFieldWrite(adi_adrv9025_Device_t* device, + uint16_t addr, + uint8_t fieldVal, + uint8_t mask, + uint8_t startBit); + +/** +* \brief Used to read a sub part of a register +* caches the read if caching is on, immediately read the value with caching off +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep{ADRV9025_BF_RDCACHE_ARRAY_TRIP_SIZE} +* \dep{SPIARRAYSIZE} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param addr The Register address that contains the field. +* \param fieldVal The value of the field to be written. +* \param mask The mask to use when inserting the data into the register. +* \param startBit The location of the first bit of the field within the register. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adrv9025_BfFieldRead(adi_adrv9025_Device_t* device, + uint16_t addr, + uint8_t* fieldVal, + uint8_t mask, + uint8_t startBit); + +/** +* \brief Used by the bitField API to ensure the cache is flushed when using BitField Caching +* and to assemble the register bytes when caching is not used. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxBfData The raw data read from the registers prior to concatenation. +* \param numRdBfData The number of elements used in the rdBfData. +* \param rdData The assembled bitfield value. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adrv9025_BfReadAssembleData(adi_adrv9025_Device_t* device, + uint8_t* rxBfData, + uint8_t numRdBfData, + uint64_t* rdData); + +/** +* \brief Used to send multiple spi register reads in one spi transaction. +* multiple register data and sub register data is concatenated and shifted appropriately. +* +* warning ensure the rdData is big enough to contain the expected number of bitfield values +* +* \dep_begin +* \dep{SPIARRAYSIZE} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rdData The bytefield data being returned in the order it was read. +* \param numRxBitFields The number of bitfields being returned +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adrv9025_BfReadCacheFlush(adi_adrv9025_Device_t* device, + uint64_t* rdData, + uint16_t* numRxBitFields); + +/** +* \brief Used to send multiple spi register writes in one spi transaction. +* if the spi buffer size is exceeded the data will be sent in buffer size blocks. +* Only full bytes are written ie there are no RMW operations +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adrv9025_BfWriteCacheFlush(adi_adrv9025_Device_t* device); + +#ifdef __cplusplus +} +#endif + +#endif /* ADRV9025_BF_HAL_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_hal_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_hal_types.h new file mode 100644 index 0000000..001259f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_hal_types.h @@ -0,0 +1,45 @@ +/** +* \brief Contains BitField definitions to support ADRV9025 transciever device. +* +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef __ADRV9025_BF_HAL_TYPES_H__ +#define __ADRV9025_BF_HAL_TYPES_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Enum of all possible states of SPI write Caching. +*/ +typedef enum adrv9025_Bf_WrCache_State +{ + ADRV9025_WR_CACHE_OFF = 0x0, /*!< disable caching. spi writes will occur immediately and HW-RMW will not be used*/ + ADRV9025_WR_HW_RMW_ON = 0x1, /*!< use the Hardware Read-Modify-write if it is enabled.*/ + ADRV9025_WR_BF_CACHE_ON = 0x2, /*!< use caching only within a bitfield function. cache is auto flushed at the end of the function.*/ + ADRV9025_WR_GBL_CACHE_ON = 0x4, /*!< use caching for multiple bitfield functions. cache is auto flushed when cache is full.*/ + ADRV9025_WR_GBL_MERGE_ON = 0x8 /*!< use merging to combine multiple bitfield field functions. cache is auto flushed when cache is full.*/ +} adrv9025_Bf_WrCache_State_e; + +/** +* \brief Enum of all possible states of SPI Read Caching . +*/ +typedef enum adrv9025_Bf_RdCache_State +{ + ADRV9025_RD_CACHE_OFF = 0x0, /*!< disable caching. spi reads will occurr immediately*/ + ADRV9025_RD_BF_CACHE_ON = 0x1, /*!< use caching only within a bitfield function. cache is auto flushed at the end of the function.*/ + ADRV9025_RD_GBL_CACHE_ON = 0x2 /*!< use caching for multiple bitfield functions. the user must managing flushing*/ +} adrv9025_Bf_RdCache_State_e; + +#ifdef __cplusplus +} +#endif + +#endif // __ADRV9025_BF_HAL_TYPES_H__ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jesd_common.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jesd_common.h new file mode 100644 index 0000000..b17f71d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jesd_common.h @@ -0,0 +1,115 @@ +/** + * \file Automatically generated file: adrv9025_bf_jesd_common.h + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_JESD_COMMON_H__ +#define __ADRV9025_BF_JESD_COMMON_H__ +#include "./../../private/include/adrv9025_bf_jesd_common_types.h" +#include "adi_adrv9025.h" +#ifdef __cplusplus +extern "C"{ +#endif + +int32_t adrv9025_JesdCommonJrxTestLaneClearErrorsBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_JesdCommonJrxTestLaneErrorCountBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t channelId, + uint32_t* bfValue); + +int32_t adrv9025_JesdCommonJrxTestLaneErrorFlagBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JesdCommonJrxTestLaneInvBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JesdCommonJrxTestLaneInvalidDataFlagBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JesdCommonJrxTestLaneUpdateErrorCountBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_JesdCommonJrxTestModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_JesdCommonJrxTestModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JesdCommonJrxTestSampleClearErrorsBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_JesdCommonJrxTestSampleClearErrorsBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JesdCommonJrxTestSampleErrorCountBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JesdCommonJrxTestSampleErrorFlagBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JesdCommonJrxTestSampleUpdateErrorCountBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_JesdCommonJrxTestSourceBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_JesdCommonJrxTestSourceBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JesdCommonJtxLinkEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JesdCommonJtxOverrideSrstEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_JesdCommonJtxOverrideSrstEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JesdCommonJtxTriggerSrstNBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_JesdCommonJtxTriggerSrstNBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JesdCommonJrxLinkEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jesd_common_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jesd_common_types.h new file mode 100644 index 0000000..cc2879b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jesd_common_types.h @@ -0,0 +1,34 @@ +/** + * \file adrv9025_bf_jesd_common_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_JESD_COMMON_TYPES_H__ +#define __ADRV9025_BF_JESD_COMMON_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum adrv9025_BfJesdCommonChanAddr +{ + ADRV9025_BF_JESD_COMMON = 0x6600 +} adrv9025_BfJesdCommonChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif /* __ADRV9025_BF_JESD_COMMON_TYPES_H__ */ + +/* EOF: adrv9025_bf_jesd_common_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jrx_link.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jrx_link.h new file mode 100644 index 0000000..2fb5a7d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jrx_link.h @@ -0,0 +1,374 @@ +/** + * \file Automatically generated file: adrv9025_bf_jrx_link.h + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_JRX_LINK_H__ +#define __ADRV9025_BF_JRX_LINK_H__ +#include "./../../private/include/adrv9025_bf_jrx_link_types.h" +#include "adi_adrv9025.h" +#ifdef __cplusplus +extern "C"{ +#endif + +int32_t adrv9025_JrxLinkJrxChksumCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxConvSelBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t adrv9025_JrxLinkJrxConvSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxCsCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDidCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bBdCntBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bBdeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bCgsBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bCksBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bEcntEnaBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bEcntEnaBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bEcntRstBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bEcntTchBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bEcntTchBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bEofEventBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bEomfEventBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bEthBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bFsBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bFsLostBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bIldBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bIlsBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bIrqClrBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bIrqClrBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bIrqVecBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint16_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg0BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg1BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg10BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg13BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg2BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg3BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg4BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg5BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg6BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg7BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg8BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg9BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bNitBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bNitCntBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bSyncNBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bUekBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bUekCntBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bUserDataBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204bValidCksumBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204cMbReqdCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204cStateGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDl204hIrqClrBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_JrxLinkJrxDl204hIrqClrBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_JrxLinkJrxDscrCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxFCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxHdCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxKCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxLCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxLidCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxLinkLaneSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxLinkTypeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxMCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxNCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxNpCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxSCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxSyncNSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxSysrefForRelinkBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxSysrefForStartupBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxTplPhaseAdjustBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_JrxLinkJrxTplSysrefIgnoreWhenLinkedBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxTplSysrefMaskBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_JrxLinkJrxTplSysrefMaskBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxTplSysrefNShotCountBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxTplSysrefNShotEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxTplSysrefRcvdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxTplUsrDataRdyBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxTplBufDepthBfGet(adi_adrv9025_Device_t *device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue); + +int32_t adrv9025_JrxLinkJrxTplBufProtectionBfGet(adi_adrv9025_Device_t *device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t *bfValue); + +int32_t adrv9025_JrxLinkJrxTplBufProtectEnBfSet(adi_adrv9025_Device_t *device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_JrxLinkJrxTplBufProtectEnBfGet(adi_adrv9025_Device_t *device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JrxLinkJrxTplPhaseAdjustBfSet(adi_adrv9025_Device_t *device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_JrxLinkJrxTplPhaseDiffBfGet(adi_adrv9025_Device_t *device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jrx_link_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jrx_link_types.h new file mode 100644 index 0000000..7dccb9c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jrx_link_types.h @@ -0,0 +1,35 @@ +/** + * \file adrv9025_bf_jrx_link_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_JRX_LINK_TYPES_H__ +#define __ADRV9025_BF_JRX_LINK_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum adrv9025_BfJrxLinkChanAddr +{ + ADRV9025_BF_JRX_LINK0 = 0x6A00, + ADRV9025_BF_JRX_LINK1 = 0x6C00 +} adrv9025_BfJrxLinkChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __ADRV9025_BF_JRX_LINK_TYPES_H__ + +/* EOF: adrv9025_bf_jrx_link_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jtx_link.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jtx_link.h new file mode 100644 index 0000000..4d8898d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jtx_link.h @@ -0,0 +1,168 @@ +/** + * \file Automatically generated file: adrv9025_bf_jtx_link.h + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_JTX_LINK_H__ +#define __ADRV9025_BF_JTX_LINK_H__ +#include "./../../private/include/adrv9025_bf_jtx_link_types.h" +#include "adi_adrv9025.h" +#ifdef __cplusplus +extern "C"{ +#endif + +int32_t adrv9025_JtxLinkJtxBidCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxConvSelBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t adrv9025_JtxLinkJtxConvSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxDidCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxDl204bStateBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxDl204bSyncNBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxDl204bSyncNeCountBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxDl204cSysrefRcvdGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxECfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxFCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxKCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxLaneInvBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t adrv9025_JtxLinkJtxLaneInvBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxLaneSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxLidCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxMCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxNpCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxScrCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxSyncNSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxSysrefForRelinkBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxSysrefForStartupBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxTestGenModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_JtxLinkJtxTestGenModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxTestGenSelBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_JtxLinkJtxTestGenSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxTplCfgInvalidBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxTplPhaseAdjustBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_JtxLinkJtxTplSysrefIgnoreWhenLinkedBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxTplSysrefMaskBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_JtxLinkJtxTplSysrefMaskBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxTplSysrefNShotCountBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxTplSysrefNShotEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxTplSysrefPhaseErrBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_JtxLinkJtxTplSysrefRcvdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jtx_link_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jtx_link_types.h new file mode 100644 index 0000000..808b451 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_jtx_link_types.h @@ -0,0 +1,36 @@ +/** + * \file adrv9025_bf_jtx_link_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_JTX_LINK_TYPES_H__ +#define __ADRV9025_BF_JTX_LINK_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum adrv9025_BfJtxLinkChanAddr +{ + ADRV9025_BF_JTX_LINK0 = 0x6E00, + ADRV9025_BF_JTX_LINK1 = 0x7000, + ADRV9025_BF_JTX_LINK2 = 0x7200 +} adrv9025_BfJtxLinkChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __ADRV9025_BF_JTX_LINK_TYPES_H__ + +/* EOF: adrv9025_bf_jtx_link_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_orx.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_orx.h new file mode 100644 index 0000000..fc60af7 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_orx.h @@ -0,0 +1,367 @@ +/** + * \file Automatically generated file: adrv9025_bf_orx.h + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_ORX_H__ +#define __ADRV9025_BF_ORX_H__ +#include "./../../private/include/adrv9025_bf_orx_types.h" +#include "adi_adrv9025.h" +#ifdef __cplusplus +extern "C"{ +#endif + +int32_t adrv9025_OrxAgcEnableFastRecoveryLoopBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxAuxAdcDecimationCtlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxAuxAdcPdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxAuxAdcPdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxAuxAdcReadBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_OrxAuxAdcReadbackLockBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxAuxAdcResetBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxAuxAdcSelBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxAuxAdcSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxBbdcLoopback1TrackingEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxBbdcLoopback1TrackingEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxBbdcLoopback2TrackingEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxBbdcLoopback2TrackingEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxBbdcLoopbackMShiftBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxBbdcLoopbackMShiftBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxBbdcMShiftBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxBbdcMShiftBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxBbdcOrx2MShiftBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxBbdcOrx2MShiftBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxBbdcOrx2TrackingEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxBbdcOrx2TrackingEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxBbdcTrackingEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxBbdcTrackingEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxDecPowerBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxDynamicSlicerAgcSyncEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxDynamicSlicerAgcSyncEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxDynamicSlicerModeEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxDynamicSlicerModeEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxDynamicSlicerResendBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxDynamicSlicerSyncHeadBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t adrv9025_OrxDynamicSlicerSyncHeadBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t adrv9025_OrxFpEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxFpEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxFpExponentBitsBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + adrv9025_BfOrxFpExponentBits_e bfValue); + +int32_t adrv9025_OrxFpExponentBitsBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + adrv9025_BfOrxFpExponentBits_e* bfValue); + +int32_t adrv9025_OrxFpFloatDataFormatBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxFpFloatDataFormatBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxFpHideLeadingOnesBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxFpHideLeadingOnesBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxFpIntDataAttenBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxFpIntDataAttenBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxFpNanEncEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxFpNanEncEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxFpRoundModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + adrv9025_BfOrxFpRoundMode_e bfValue); + +int32_t adrv9025_OrxFpRoundModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + adrv9025_BfOrxFpRoundMode_e* bfValue); + +int32_t adrv9025_OrxGainCompEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxGainCompEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxGainCompForExtGainBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxGainCompForExtGainBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxGainCompForTempGainBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxGainCompForTempGainBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxIntDataFormatBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxIntDataFormatBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxIntDataResolutionBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxIntDataResolutionBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxIntEmbedSlicerBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxIntEmbedSlicerBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxIntEmbedSlicerNumberBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxIntEmbedSlicerNumberBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxIntEmbedSlicerPosBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxIntEmbedSlicerPosBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxIntEvenParityBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxIntEvenParityBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxIntParitySupportBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxIntParitySupportBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxIntSlicerLsbOnQBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxIntSlicerLsbOnQBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxMaxSlicerOverrideBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxOrx1AgcGainIndexBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxOrx1AgcManualGainIndexBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxOrx1AgcManualGainIndexBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxOrx1AgcSetupBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxOrx1AgcSetupBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxOrx2AgcGainIndexBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxOrx2AgcManualGainIndexBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxOrx2AgcManualGainIndexBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxOrx2AgcSetupBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxOrx2AgcSetupBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxRxTempGainCompBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxRxTempGainCompBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxRxdpSlicerPinCntrlGpioSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxRxdpSlicerPositionBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxSlicerPinControlStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_OrxSlicerPinControlStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxStatic3bitSlicerModeEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_orx_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_orx_types.h new file mode 100644 index 0000000..bd75cbb --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_orx_types.h @@ -0,0 +1,58 @@ +/** + * \file adrv9025_bf_orx_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support ADRV9025 transciever device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_ORX_TYPES_H__ +#define __ADRV9025_BF_ORX_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum adrv9025_BfOrxChanAddr +{ + ADRV9025_BF_ALL_ORX_CHANNELS = 0x600, + ADRV9025_BF_ORX_CH0 = 0x1A00, + ADRV9025_BF_ORX_CH1 = 0x1C00 +} adrv9025_BfOrxChanAddr_e; + +/** + * \brief Enumeration for fpExponentBits + */ +typedef enum adrv9025_BfOrxFpExponentBits +{ + ADRV9025_BF_ORX_RX1_EXP_2 = 0, /*!< Two bits of exponent */ + ADRV9025_BF_ORX_RX1_EXP_3 = 1, /*!< Three bits of exponent */ + ADRV9025_BF_ORX_RX1_EXP_4 = 2, /*!< Four bits of exponent */ + ADRV9025_BF_ORX_RX1_EXP_5 = 3 /*!< Five bits of exponent */ +} adrv9025_BfOrxFpExponentBits_e; +/** + * \brief Enumeration for fpRoundMode + */ +typedef enum adrv9025_BfOrxFpRoundMode +{ + ADRV9025_BF_ORX_ROUNDTIESTOEVEN = 0, /*!< No description provided */ + ADRV9025_BF_ORX_ROUNDTOWARDSPOSITIVE = 1, /*!< No description provided */ + ADRV9025_BF_ORX_ROUNDTOWARDSNEGATIVE = 2, /*!< No description provided */ + ADRV9025_BF_ORX_ROUNDTOWARDSZERO = 3, /*!< No description provided */ + ADRV9025_BF_ORX_ROUNDTIESTOAWAY = 4 /*!< No description provided */ +} adrv9025_BfOrxFpRoundMode_e; +#ifdef __cplusplus +} +#endif + +#endif /* __ADRV9025_BF_ORX_TYPES_H__ */ + +/* EOF: adrv9025_bf_orx_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_pll_mem_map.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_pll_mem_map.h new file mode 100644 index 0000000..d776593 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_pll_mem_map.h @@ -0,0 +1,51 @@ +/** + * \file Automatically generated file: adrv9025_bf_pll_mem_map.h + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_PLL_MEM_MAP_H__ +#define __ADRV9025_BF_PLL_MEM_MAP_H__ +#include "./../../private/include/adrv9025_bf_pll_mem_map_types.h" +#include "adi_adrv9025.h" +#ifdef __cplusplus +extern "C"{ +#endif + +int32_t adrv9025_PllMemMapAuxAdcReadyBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfPllMemMapChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_PllMemMapRx12SelLo2BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfPllMemMapChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_PllMemMapRx34SelLo2BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfPllMemMapChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_PllMemMapSynLockBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfPllMemMapChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_PllMemMapTx12SelLo2BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfPllMemMapChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_PllMemMapTx34SelLo2BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfPllMemMapChanAddr_e baseAddr, + uint8_t* bfValue); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_pll_mem_map_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_pll_mem_map_types.h new file mode 100644 index 0000000..850eed8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_pll_mem_map_types.h @@ -0,0 +1,153 @@ +/** + * \file adrv9025_bf_pll_mem_map_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support ADRV9025 transciever device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_PLL_MEM_MAP_TYPES_H__ +#define __ADRV9025_BF_PLL_MEM_MAP_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum adrv9025_BfPllMemMapChanAddr +{ + ADRV9025_BF_ALL_PLLS = 0x800, + ADRV9025_BF_AUX_PLL = 0x2600, + ADRV9025_BF_CLK_PLL = 0x2800, + ADRV9025_BF_RF1_PLL = 0x2A00, + ADRV9025_BF_RF2_PLL = 0x6400 +} adrv9025_BfPllMemMapChanAddr_e; + +/** + * \brief Enumeration for calper + */ +typedef enum adrv9025_BfPllMemMapCalper +{ + ADRV9025_BF_PLL_MEM_MAP_CALPER1 = 0, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_CALPER2 = 1, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_CALPER4 = 2, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_CALPER8 = 3, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_CALPER16 = 4, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_CALPER32 = 5, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_CALPER64 = 6, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_CALPER128 = 7 /*!< No description provided */ +} adrv9025_BfPllMemMapCalper_e; +/** + * \brief Enumeration for caltyp + */ +typedef enum adrv9025_BfPllMemMapCaltyp +{ + ADRV9025_BF_PLL_MEM_MAP_IDLE = 0, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_ICAL = 1, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_TCAL = 2, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_CTCAL = 3, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_CRCAL = 4, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_ICALC = 5, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_TCALC = 6, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_CTCALC = 7 /*!< No description provided */ +} adrv9025_BfPllMemMapCaltyp_e; +/** + * \brief Enumeration for icalwait + */ +typedef enum adrv9025_BfPllMemMapIcalwait +{ + ADRV9025_BF_PLL_MEM_MAP_ICALWAIT_1K = 0, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_ICALWAIT_2K = 1, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_ICALWAIT_4K = 2, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_ICALWAIT_8K = 3 /*!< No description provided */ +} adrv9025_BfPllMemMapIcalwait_e; +/** + * \brief Enumeration for mcsPulseDelayDigSerdes + */ +typedef enum adrv9025_BfPllMemMapMcsPulseDelayDigSerdes +{ + ADRV9025_BF_PLL_MEM_MAP_MCS_PULSE_DELAY_DIG_SERDES_2 = 0, /*!< mcs_pulse_delay_dig_serdes = 2 prescaler clocks */ + ADRV9025_BF_PLL_MEM_MAP_MCS_PULSE_DELAY_DIG_SERDES_3 = 1, /*!< mcs_pulse_delay_dig_serdes = 3 prescaler clocks */ + ADRV9025_BF_PLL_MEM_MAP_MCS_PULSE_DELAY_DIG_SERDES_4 = 2, /*!< mcs_pulse_delay_dig_serdes = 4 prescaler clocks */ + ADRV9025_BF_PLL_MEM_MAP_MCS_PULSE_DELAY_DIG_SERDES_5 = 3 /*!< mcs_pulse_delay_dig_serdes = 5 prescaler clocks */ +} adrv9025_BfPllMemMapMcsPulseDelayDigSerdes_e; +/** + * \brief Enumeration for mcsPulseWidthDigSerdes + */ +typedef enum adrv9025_BfPllMemMapMcsPulseWidthDigSerdes +{ + ADRV9025_BF_PLL_MEM_MAP_MCS_PULSE_WIDTH_DIG_SERDES_2 = 0, /*!< mcs_pulse_delay_dig_serdes = 2 prescaler clocks */ + ADRV9025_BF_PLL_MEM_MAP_MCS_PULSE_WIDTH_DIG_SERDES_3 = 1, /*!< mcs_pulse_delay_dig_serdes = 3 prescaler clocks */ + ADRV9025_BF_PLL_MEM_MAP_MCS_PULSE_WIDTH_DIG_SERDES_4 = 2, /*!< mcs_pulse_delay_dig_serdes = 4 prescaler clocks */ + ADRV9025_BF_PLL_MEM_MAP_MCS_PULSE_WIDTH_DIG_SERDES_5 = 3 /*!< mcs_pulse_delay_dig_serdes = 5 prescaler clocks */ +} adrv9025_BfPllMemMapMcsPulseWidthDigSerdes_e; +/** + * \brief Enumeration for mcsSerdesAlign + */ +typedef enum adrv9025_BfPllMemMapMcsSerdesAlign +{ + ADRV9025_BF_PLL_MEM_MAP_MCS_PULSE_ALIGN_DIG_SERDES_2 = 0, /*!< mcs_pulse_delay_dig_serdes = 2 prescaler clocks */ + ADRV9025_BF_PLL_MEM_MAP_MCS_PULSE_ALIGN_DIG_SERDES_3 = 1, /*!< mcs_pulse_delay_dig_serdes = 3 prescaler clocks */ + ADRV9025_BF_PLL_MEM_MAP_MCS_PULSE_ALIGN_DIG_SERDES_4 = 2, /*!< mcs_pulse_delay_dig_serdes = 4 prescaler clocks */ + ADRV9025_BF_PLL_MEM_MAP_MCS_PULSE_ALIGN_DIG_SERDES_5 = 3 /*!< mcs_pulse_delay_dig_serdes = 5 prescaler clocks */ +} adrv9025_BfPllMemMapMcsSerdesAlign_e; +/** + * \brief Enumeration for qthr + */ +typedef enum adrv9025_BfPllMemMapQthr +{ + ADRV9025_BF_PLL_MEM_MAP_QTHR0 = 0, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_QTHR1 = 1, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_QTHR2 = 2, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_QTHR3 = 3, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_QTHR4 = 4, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_QTHR5 = 5, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_QTHR6 = 6, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_QTHR7 = 7, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_QTHR8 = 8, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_QTHR9 = 9, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_QTHR10 = 10, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_QTHR11 = 11, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_QTHR12 = 12, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_QTHR13 = 13, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_QTHR14 = 14, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_QTHR15 = 15 /*!< No description provided */ +} adrv9025_BfPllMemMapQthr_e; +/** + * \brief Enumeration for tsprsc + */ +typedef enum adrv9025_BfPllMemMapTsprsc +{ + ADRV9025_BF_PLL_MEM_MAP_TPRSC_1 = 0, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_TPRSC_2 = 1, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_TPRSC_4 = 2, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_TPRSC_8 = 3, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_TPRSC_16 = 4, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_TPRSC_32 = 5, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_TPRSC_64 = 6, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_TPRSC_128 = 7 /*!< No description provided */ +} adrv9025_BfPllMemMapTsprsc_e; +/** + * \brief Enumeration for vcoCalInitDel + */ +typedef enum adrv9025_BfPllMemMapVcoCalInitDel +{ + ADRV9025_BF_PLL_MEM_MAP_VCOCCAL_DEL_32 = 0, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_VCOCCAL_DEL_64 = 1, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_VCOCCAL_DEL_128 = 2, /*!< No description provided */ + ADRV9025_BF_PLL_MEM_MAP_VCOCCAL_DEL_256 = 3 /*!< No description provided */ +} adrv9025_BfPllMemMapVcoCalInitDel_e; +#ifdef __cplusplus +} +#endif + +#endif // __ADRV9025_BF_PLL_MEM_MAP_TYPES_H__ + +/* EOF: adrv9025_bf_pll_mem_map_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_rx.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_rx.h new file mode 100644 index 0000000..09a6997 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_rx.h @@ -0,0 +1,1018 @@ +/** + * \file Automatically generated file: adrv9025_bf_rx.h + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_RX_H__ +#define __ADRV9025_BF_RX_H__ +#include "./../../private/include/adrv9025_bf_rx_types.h" +#include "./../../private/include/adrv9025_bf_orx_types.h" +#include "adi_adrv9025.h" +#ifdef __cplusplus +extern "C"{ +#endif + +int32_t adrv9025_RxAdcOverloadResetEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAdcOverloadResetEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAdcovrg2ndHighCounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcAdcHighOvrgExceededCounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcAdcHighOvrgExceededCounterBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcAdcLowOvrgExceededCounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcAdcLowOvrgExceededCounterBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcAdcResetGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcAdcResetGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcAdcovrgLowInt0CounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcAdcovrgLowInt0CounterBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcAdcovrgLowInt1CounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcAdcovrgLowInt1CounterBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcApdLowFreqErrorMitigationModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcAttackDelayBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcAttackDelayBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcChangeGainIfAdcovrgHighBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcChangeGainIfAdcovrgHighBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcChangeGainIfUlbthHighBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcChangeGainIfUlbthHighBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcDecGainGpioSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcDecGainGpioSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcDecrGainStepSizeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcDecrGainStepSizeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcEnableFastRecoveryLoopBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcEnableFastRecoveryLoopBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcEnableGainIndexUpdateBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_OrxAgcEnableGainIndexUpdateBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcEnableSyncPulseForGainCounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcEnableSyncPulseForGainCounterBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcGainIndexBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcGainUpdateCounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t adrv9025_RxAgcGainUpdateCounterBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t adrv9025_RxAgcIncGainGpioSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcIncGainGpioSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcIncrGainStepSizeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcIncrGainStepSizeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcLlbGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcLlbGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcLlbThresholdExceededCounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcLlbThresholdExceededCounterBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcLockLevelBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcLockLevelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcLowThsPreventGainIncBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcLowThsPreventGainIncBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcLower0ThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcLower0ThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcLower0ThresholdExceededGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcLower0ThresholdExceededGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcLower1ThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcLower1ThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcLower1ThresholdExceededGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcLower1ThresholdExceededGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcManualGainIndexBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcManualGainIndexBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcManualGainPinControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcManualGainPinControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcMaximumGainIndexBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcMaximumGainIndexBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcMinimumGainIndexBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcMinimumGainIndexBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcOvrgHighGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcOvrgHighGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcOvrgLowGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcOvrgLowGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcOvrgLowInt0GainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcOvrgLowInt0GainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcOvrgLowInt1GainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcOvrgLowInt1GainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcPeakThresholdGainControlModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcPeakThresholdGainControlModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcPeakWaitTimeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcPeakWaitTimeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcResetOnRxonBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcResetOnRxonBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcSetupBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcSetupBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcSlowLoopSettlingDelayBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcSlowLoopSettlingDelayBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcSlowloopFastGainChangeBlockEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcSoftResetBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcUlSigPowerMeasDelayBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_RxAgcUlSigPowerMeasDelayBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_RxAgcUlSigPowerMeasDurationBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_RxAgcUlSigPowerMeasDurationBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_RxAgcUlbGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcUlbGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcUlbThresholdExceededCounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcUlbThresholdExceededCounterBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcUpper0ThresholdExceededGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcUpper0ThresholdExceededGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcUpper1ThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcUpper1ThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcUpper1ThresholdExceededGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcUpper1ThresholdExceededGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcUrangeInterval0BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_RxAgcUrangeInterval0BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_RxAgcUrangeInterval1MultBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcUrangeInterval1MultBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxAgcUrangeInterval2MultBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcUrangeInterval2MultBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxApdHighSrcSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxApdHighSrcSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxApdLowSrcSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxApdLowSrcSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxArmOverrideControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxArmOverrideControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxBbdcMShiftBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxBbdcMShiftBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxBbdcTrackingEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxBbdcTrackingEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxControlOutMuxAddressBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxDecOverloadDurationCountBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxDecOverloadDurationCountBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxDecOverloadPowerModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxDecOverloadPowerModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxDecOverloadThresholdCountBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxDecOverloadThresholdCountBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxDecPowerBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxDecPowerEnableMeasBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxDecPowerEnableMeasBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxDecPowerInputSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxDecPowerInputSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxDecPowerLogShiftBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxDecPowerLogShiftBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxDecPowerMeasurementDurationBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxDecPowerMeasurementDurationBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxDecThresholdConfigBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxDecThresholdConfigBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxDecimatedDataOverloadInt0LowerThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_RxDecimatedDataOverloadInt0LowerThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_RxDecimatedDataOverloadInt1LowerThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_RxDecimatedDataOverloadInt1LowerThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_RxDecimatedDataOverloadLowerThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_RxDecimatedDataOverloadLowerThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_RxDecimatedDataOverloadSecondaryUpperThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_RxDecimatedDataOverloadUpperThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_RxDecimatedDataOverloadUpperThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_RxDynamicSlicerAgcSyncEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxDynamicSlicerAgcSyncEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxDynamicSlicerModeEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxDynamicSlicerModeEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxDynamicSlicerResendBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxDynamicSlicerSyncHeadBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t adrv9025_RxDynamicSlicerSyncHeadBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t adrv9025_RxEnableDecOverloadBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxEnableDecOverloadBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxExternalSlicerPinControlStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxExternalSlicerPinControlStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxFpEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxFpEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxFpExponentBitsBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + adrv9025_BfRxFpExponentBits_e bfValue); + +int32_t adrv9025_RxFpExponentBitsBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + adrv9025_BfRxFpExponentBits_e* bfValue); + +int32_t adrv9025_RxFpFloatDataFormatBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxFpFloatDataFormatBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxFpHideLeadingOnesBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxFpHideLeadingOnesBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxFpIntDataAttenBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxFpIntDataAttenBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxFpNanEncEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxFpNanEncEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxFpRoundModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + adrv9025_BfRxFpRoundMode_e bfValue); + +int32_t adrv9025_RxFpRoundModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + adrv9025_BfRxFpRoundMode_e* bfValue); + +int32_t adrv9025_RxGainCompEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxGainCompEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxGainCompForExtGainBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxGainCompForExtGainBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxGainCompForTempGainBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxGainCompForTempGainBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxHb2HighSrcSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxHb2HighSrcSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxHb2LowSrcSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxHb2LowSrcSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxHb2OverloadUseHb2InBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxHb2OverloadUseHb2InBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxIntDataFormatBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxIntDataFormatBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxIntDataResolutionBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxIntDataResolutionBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxIntEmbedSlicerBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxIntEmbedSlicerBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxIntEmbedSlicerNumberBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxIntEmbedSlicerNumberBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxIntEmbedSlicerPosBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxIntEmbedSlicerPosBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxIntEvenParityBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxIntEvenParityBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxIntParitySupportBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxIntParitySupportBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxIntSlicerLsbOnQBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxIntSlicerLsbOnQBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxInvertApdLowBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxInvertApdLowBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxInvertHb2LowBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxInvertHb2LowBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxMaxSlicerOverrideBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxPcaGainControlModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxPcaGainControlModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxPcaGainIndexOffsetBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxPcaGainIndexOffsetBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxPcaGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxPcaGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxPcaPinSelBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxPcaPinSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxPcaUpdateManualGainModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxRxEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxRxEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxRxFdDwellThreshBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_RxRxFdDwellThreshBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_RxRxFdFineEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxRxFdLowThreshBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_RxRxFdLowThreshBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_RxRxFdUpThreshBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_RxRxFdUpThreshBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_RxRxFdUseEnvelopMeasBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxRxFdUseEnvelopMeasBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxRxMonFormatIBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t adrv9025_RxRxMonFormatIBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_RxRxMonFormatQBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t adrv9025_RxRxMonFormatQBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t adrv9025_RxRxPinModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxRxPinModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxRxSmonOffsetShiftBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxRxSmonPeakEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxRxSmonPeakEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxRxSmonPeriodBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t adrv9025_RxRxSmonPeriodBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t adrv9025_RxRxSmonSourceBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxRxSmonSourceBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxRxSmonSqrtEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxRxSmonSqrtEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxRxTempGainCompBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxRxTempGainCompBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxRxdpSlicerPinCntrlGpioSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxRxdpSlicerPinCntrlGpioSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxRxdpSlicerPositionBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxSlicerPinControlModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxSlicerPinControlModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxSlicerPinControlStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxSlicerPinControlStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxStatic3bitSlicerModeEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcClkDivideRatioBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_RxAgcClkDivideRatioBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_RxReferenceClockCyclesBfSet(adi_adrv9025_Device_t *device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); +int32_t adrv9025_RxReferenceClockCyclesBfGet(adi_adrv9025_Device_t *device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t *bfValue); + +int32_t adrv9025_RxAgcDelayCounterBaseRateBfSet(adi_adrv9025_Device_t *device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue); +int32_t adrv9025_RxAgcDelayCounterBaseRateBfGet(adi_adrv9025_Device_t *device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t *bfValue); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_rx_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_rx_types.h new file mode 100644 index 0000000..c6dbe8c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_rx_types.h @@ -0,0 +1,60 @@ +/** + * \file adrv9025_bf_rx_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support ADRV9025 transciever device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_RX_TYPES_H__ +#define __ADRV9025_BF_RX_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum adrv9025_BfRxChanAddr +{ + ADRV9025_BF_ALL_RX_CHANNELS = 0x200, + ADRV9025_BF_RX_CH0 = 0x1200, + ADRV9025_BF_RX_CH1 = 0x1400, + ADRV9025_BF_RX_CH2 = 0x1600, + ADRV9025_BF_RX_CH3 = 0x1800 +} adrv9025_BfRxChanAddr_e; + +/** + * \brief Enumeration for fpExponentBits + */ +typedef enum adrv9025_BfRxFpExponentBits +{ + ADRV9025_BF_RX_RX1_EXP_2 = 0, /*!< Two bits of exponent */ + ADRV9025_BF_RX_RX1_EXP_3 = 1, /*!< Three bits of exponent */ + ADRV9025_BF_RX_RX1_EXP_4 = 2, /*!< Four bits of exponent */ + ADRV9025_BF_RX_RX1_EXP_5 = 3 /*!< Five bits of exponent */ +} adrv9025_BfRxFpExponentBits_e; +/** + * \brief Enumeration for fpRoundMode + */ +typedef enum adrv9025_BfRxFpRoundMode +{ + ADRV9025_BF_RX_ROUNDTIESTOEVEN = 0, /*!< No description provided */ + ADRV9025_BF_RX_ROUNDTOWARDSPOSITIVE = 1, /*!< No description provided */ + ADRV9025_BF_RX_ROUNDTOWARDSNEGATIVE = 2, /*!< No description provided */ + ADRV9025_BF_RX_ROUNDTOWARDSZERO = 3, /*!< No description provided */ + ADRV9025_BF_RX_ROUNDTIESTOAWAY = 4 /*!< No description provided */ +} adrv9025_BfRxFpRoundMode_e; +#ifdef __cplusplus +} +#endif + +#endif /* __ADRV9025_BF_RX_TYPES_H__ */ + +/* EOF: adrv9025_bf_rx_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_tx.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_tx.h new file mode 100644 index 0000000..6341439 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_tx.h @@ -0,0 +1,423 @@ +/** + * \file Automatically generated file: adrv9025_bf_tx.h + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_TX_H__ +#define __ADRV9025_BF_TX_H__ +#include "./../../private/include/adrv9025_bf_tx_types.h" +#include "adi_adrv9025.h" +#ifdef __cplusplus +extern "C"{ +#endif + +int32_t adrv9025_TxArmOverrideControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxArmOverrideControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxCfrBasePulse21bBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxCfrBasePulse21bBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxCfrHalfPulseLenBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_TxDpdActClkEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxDpdActClkEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxJesdDfrmMaskBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxJesdDfrmMaskBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxNcoTestEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxNcoTestEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxPaProtectionAprEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionAprEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxPaProtectionAveragePeakRatioBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_TxPaProtectionAveragePowerBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_TxPaProtectionAvgThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_TxPaProtectionAvgThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_TxPaProtectionAvgpowerEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionAvgpowerEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxPaProtectionAvgpowerErrorBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxPaProtectionAvgpowerErrorClearBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionAvgpowerErrorClearRequiredBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionAvrgDurBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionAvrgDurBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxPaProtectionErrorPowerBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_TxPaProtectionGainRampDownEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionGainRampDownEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxPaProtectionGainRampUpEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionGainRampUpEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxPaProtectionGainStepDownEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionInputSelBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionInputSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxPaProtectionPeakCountBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionPeakCountBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxPaProtectionPeakDurBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionPeakDurBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxPaProtectionPeakThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_TxPaProtectionPeakThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_TxPaProtectionPeakpowerEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionPeakpowerEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxPaProtectionPeakpowerErrorBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxPaProtectionPeakpowerErrorClearBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionPeakpowerErrorClearRequiredBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionRampMaxAttenuationBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionRampMaxAttenuationBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxPaProtectionRampStepDurationBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionRampStepDurationBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxPaProtectionRampStepSizeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPaProtectionRampStepSizeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxPaProtectionTxAttenStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPllJesdProtClrBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPllJesdProtClrReqdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPllJesdProtEventBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxPllUnlockMaskBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxPllUnlockMaskBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxSpi2TxAttenGpioSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxSpi2TxAttenGpioSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxSrlIrqBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxSrlIrqEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxSrlIrqEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxSrlSlewOffsetBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxSrlSlewOffsetBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxSrlStatBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_TxSrlStatEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxSrlStatEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxSrlStatModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxSrlTableSelBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxSrlTableSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxTpcDecrAttenGpioSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxTpcDecrAttenGpioSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxTpcIncrAttenGpioSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxTpcIncrAttenGpioSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxTxAttenConfigBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxTxAttenConfigBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxTxAttenModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxTxAttenUpdGpioEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxTxAttenUpdGpioEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxTxAttenUpdGpioSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxTxAttenUpdGpioSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxTxAttenuationBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t adrv9025_TxTxAttenuationBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t adrv9025_TxTxDataRampDownOnJesdDfrmIrqBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxTxDataRampDownOnJesdDfrmIrqBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxTxDataRampDownOnPllUnlockBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxTxDataRampDownOnPllUnlockBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxTxDpNcoEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxTxDpNcoFtwBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t adrv9025_TxTxDpNcoFtwBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t adrv9025_TxTxDpNcoFtwUpdateBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxTxEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxTxEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxTxIncrDecrWordBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxTxIncrDecrWordBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxTxNcoGainBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxTxNcoGainBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxTxPinModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxTxPinModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t adrv9025_TxTxAttenuationEarlyDelayCounterForAnalogBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxTxAttenuationEarlyDelayCounterForAnalogBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_tx_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_tx_types.h new file mode 100644 index 0000000..da0fe24 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_tx_types.h @@ -0,0 +1,38 @@ +/** + * \file adrv9025_bf_tx_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_TX_TYPES_H__ +#define __ADRV9025_BF_TX_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum adrv9025_BfTxChanAddr +{ + ADRV9025_BF_ALL_TX_CHANNELS = 0x400, + ADRV9025_BF_TX_CH0 = 0x1E00, + ADRV9025_BF_TX_CH1 = 0x2000, + ADRV9025_BF_TX_CH2 = 0x2200, + ADRV9025_BF_TX_CH3 = 0x2400 +} adrv9025_BfTxChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif /* __ADRV9025_BF_TX_TYPES_H__ */ + +/* EOF: adrv9025_bf_tx_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_txdac_mem_map.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_txdac_mem_map.h new file mode 100644 index 0000000..5fbc179 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_txdac_mem_map.h @@ -0,0 +1,47 @@ +/** + * \file Automatically generated file: adrv9025_bf_txdac_mem_map.h + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_TXDAC_MEM_MAP_H__ +#define __ADRV9025_BF_TXDAC_MEM_MAP_H__ +#include "./../../private/include/adrv9025_bf_txdac_mem_map_types.h" +#include "adi_adrv9025.h" +#ifdef __cplusplus +extern "C"{ +#endif + +int32_t adrv9025_TxdacMemMapTxdacFscBoostIBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxdacMemMapChanAddr_e baseAddr, + adrv9025_BfTxdacMemMapTxdacFscBoostI_e bfValue); + +int32_t adrv9025_TxdacMemMapTxdacFscBoostIBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxdacMemMapChanAddr_e baseAddr, + adrv9025_BfTxdacMemMapTxdacFscBoostI_e* bfValue); + +int32_t adrv9025_TxdacMemMapTxdacFscBoostQBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxdacMemMapChanAddr_e baseAddr, + adrv9025_BfTxdacMemMapTxdacFscBoostQ_e bfValue); + +int32_t adrv9025_TxdacMemMapTxdacFscTuneIBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxdacMemMapChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t adrv9025_TxdacMemMapTxdacFscTuneQBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxdacMemMapChanAddr_e baseAddr, + uint8_t bfValue); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_txdac_mem_map_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_txdac_mem_map_types.h new file mode 100644 index 0000000..099ed78 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_bf_txdac_mem_map_types.h @@ -0,0 +1,400 @@ +/** + * \file adrv9025_bf_txdac_mem_map_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support ADRV9025 transciever device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADRV9025_BF_TXDAC_MEM_MAP_TYPES_H__ +#define __ADRV9025_BF_TXDAC_MEM_MAP_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum adrv9025_BfTxdacMemMapChanAddr +{ + ADRV9025_BF_ALL_TXDAC = 0x1000, + ADRV9025_BF_TXDAC_CH1 = 0x7400, + ADRV9025_BF_TXDAC_CH2 = 0x7600, + ADRV9025_BF_TXDAC_CH3 = 0x7800, + ADRV9025_BF_TXDAC_CH0 = 0x7A00 +} adrv9025_BfTxdacMemMapChanAddr_e; + +/** + * \brief Enumeration for txdacCalAddrI + */ +typedef enum adrv9025_BfTxdacMemMapTxdacCalAddrI +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISBREF = 0, /*!< ISB_REF (Reference For Calibration, Does not affect INL/DNL) */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISB0 = 1, /*!< ISB0 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISB1 = 2, /*!< ISB1 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISB2 = 3, /*!< ISB2 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISB3 = 4, /*!< ISB3 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISB4 = 5, /*!< ISB4 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISB5 = 6, /*!< ISB5 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISB6 = 7, /*!< ISB6 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISB7 = 8, /*!< ISB7 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISB8 = 9, /*!< ISB8 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISB9 = 10, /*!< ISB9 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISB10 = 11, /*!< ISB10 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISB11 = 12, /*!< ISB11 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISB12 = 13, /*!< ISB12 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISB13 = 14, /*!< ISB13 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISB14 = 15, /*!< ISB14 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_LSBSUM = 16, /*!< LSB Sum */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_UNUSED0 = 17, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_UNUSED1 = 18, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_UNUSED2 = 19, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_UNUSED3 = 20, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_UNUSED4 = 21, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_UNUSED5 = 22, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_UNUSED6 = 23, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSBCOMPPOS = 24, /*!< MSB Comparator Positive */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSBCOMPNEG = 25, /*!< MSB Comparator Negative */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISBCOMPPOS = 26, /*!< ISB Comparator Positive */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_ISBCOMPNEG = 27, /*!< ISB Comparator Negative */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_UNUSED7 = 28, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_UNUSED8 = 29, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_UNUSED9 = 30, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSBREF = 31, /*!< MSB Reference (Reference for Calibration, Does not affect INL/DNL) */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSBGAIN = 32, /*!< MSB Gain (Fullscale Current Adjustment, Does not affect INL/DNL) */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB0 = 33, /*!< MSB0 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB1 = 34, /*!< MSB1 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB2 = 35, /*!< MSB2 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB3 = 36, /*!< MSB3 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB4 = 37, /*!< MSB4 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB5 = 38, /*!< MSB5 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB6 = 39, /*!< MSB6 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB7 = 40, /*!< MSB7 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB8 = 41, /*!< MSB8 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB9 = 42, /*!< MSB9 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB10 = 43, /*!< MSB10 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB11 = 44, /*!< MSB11 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB12 = 45, /*!< MSB12 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB13 = 46, /*!< MSB13 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB14 = 47, /*!< MSB14 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB15 = 48, /*!< MSB15 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB16 = 49, /*!< MSB16 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB17 = 50, /*!< MSB17 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB18 = 51, /*!< MSB18 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB19 = 52, /*!< MSB19 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB20 = 53, /*!< MSB20 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB21 = 54, /*!< MSB21 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB22 = 55, /*!< MSB22 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB23 = 56, /*!< MSB23 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB24 = 57, /*!< MSB24 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB25 = 58, /*!< MSB25 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB26 = 59, /*!< MSB26 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB27 = 60, /*!< MSB27 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB28 = 61, /*!< MSB28 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB29 = 62, /*!< MSB29 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_CALADDR_MSB30 = 63 /*!< MSB30 */ +} adrv9025_BfTxdacMemMapTxdacCalAddrI_e; +/** + * \brief Enumeration for txdacCalAddrQ + */ +typedef enum adrv9025_BfTxdacMemMapTxdacCalAddrQ +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISBREF = 0, /*!< ISB_REF (Reference For Calibration, Does not affect INL/DNL) */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISB0 = 1, /*!< ISB0 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISB1 = 2, /*!< ISB1 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISB2 = 3, /*!< ISB2 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISB3 = 4, /*!< ISB3 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISB4 = 5, /*!< ISB4 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISB5 = 6, /*!< ISB5 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISB6 = 7, /*!< ISB6 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISB7 = 8, /*!< ISB7 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISB8 = 9, /*!< ISB8 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISB9 = 10, /*!< ISB9 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISB10 = 11, /*!< ISB10 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISB11 = 12, /*!< ISB11 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISB12 = 13, /*!< ISB12 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISB13 = 14, /*!< ISB13 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISB14 = 15, /*!< ISB14 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_LSBSUM = 16, /*!< LSB Sum */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_UNUSED0 = 17, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_UNUSED1 = 18, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_UNUSED2 = 19, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_UNUSED3 = 20, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_UNUSED4 = 21, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_UNUSED5 = 22, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_UNUSED6 = 23, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSBCOMPPOS = 24, /*!< MSB Comparator Positive */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSBCOMPNEG = 25, /*!< MSB Comparator Negative */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISBCOMPPOS = 26, /*!< ISB Comparator Positive */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_ISBCOMPNEG = 27, /*!< ISB Comparator Negative */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_UNUSED7 = 28, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_UNUSED8 = 29, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_UNUSED9 = 30, /*!< Unassigned */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSBREF = 31, /*!< MSB Reference (Reference for Calibration, Does not affect INL/DNL) */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSBGAIN = 32, /*!< MSB Gain (Fullscale Current Adjustment, Does not affect INL/DNL) */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB0 = 33, /*!< MSB0 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB1 = 34, /*!< MSB1 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB2 = 35, /*!< MSB2 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB3 = 36, /*!< MSB3 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB4 = 37, /*!< MSB4 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB5 = 38, /*!< MSB5 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB6 = 39, /*!< MSB6 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB7 = 40, /*!< MSB7 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB8 = 41, /*!< MSB8 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB9 = 42, /*!< MSB9 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB10 = 43, /*!< MSB10 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB11 = 44, /*!< MSB11 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB12 = 45, /*!< MSB12 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB13 = 46, /*!< MSB13 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB14 = 47, /*!< MSB14 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB15 = 48, /*!< MSB15 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB16 = 49, /*!< MSB16 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB17 = 50, /*!< MSB17 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB18 = 51, /*!< MSB18 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB19 = 52, /*!< MSB19 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB20 = 53, /*!< MSB20 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB21 = 54, /*!< MSB21 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB22 = 55, /*!< MSB22 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB23 = 56, /*!< MSB23 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB24 = 57, /*!< MSB24 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB25 = 58, /*!< MSB25 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB26 = 59, /*!< MSB26 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB27 = 60, /*!< MSB27 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB28 = 61, /*!< MSB28 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB29 = 62, /*!< MSB29 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_CALADDR_MSB30 = 63 /*!< MSB30 */ +} adrv9025_BfTxdacMemMapTxdacCalAddrQ_e; +/** + * \brief Enumeration for txdacCalDebugI + */ +typedef enum adrv9025_BfTxdacMemMapTxdacCalDebugI +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CAL_IDAC_NORMAL = 0, /*!< State machine operates normally and performs I DAC calibration. */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CAL_IDAC_DEBUG = 1 /*!< State machine ONLY performs a SAR operation of the CALDAC specified by txdac_cal_addr_i, then saves the SAR value to the specified CALDAC. */ +} adrv9025_BfTxdacMemMapTxdacCalDebugI_e; +/** + * \brief Enumeration for txdacCalDebugQ + */ +typedef enum adrv9025_BfTxdacMemMapTxdacCalDebugQ +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CAL_QDAC_NORMAL = 0, /*!< State machine operates normally and performs Q DAC calibration. */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CAL_QDAC_DEBUG = 1 /*!< State machine ONLY performs a SAR operation of the CALDAC specified by txdac_cal_addr_q, then saves the SAR value to the specified CALDAC. */ +} adrv9025_BfTxdacMemMapTxdacCalDebugQ_e; +/** + * \brief Enumeration for txdacCalStartI + */ +typedef enum adrv9025_BfTxdacMemMapTxdacCalStartI +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CAL_START_I_DISABLE = 0, /*!< Calibration state machine is immediately stopped and reset. */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CAL_START_I_TRIGGER = 1 /*!< 0 to 1 transition starts DAC calibration. */ +} adrv9025_BfTxdacMemMapTxdacCalStartI_e; +/** + * \brief Enumeration for txdacCalStartQ + */ +typedef enum adrv9025_BfTxdacMemMapTxdacCalStartQ +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CAL_START_Q_DISABLE = 0, /*!< Calibration state machine is immediately stopped and reset. */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CAL_START_Q_TRIGGER = 1 /*!< 0 to 1 transition starts DAC calibration. */ +} adrv9025_BfTxdacMemMapTxdacCalStartQ_e; +/** + * \brief Enumeration for txdacCalclkDiv + */ +typedef enum adrv9025_BfTxdacMemMapTxdacCalclkDiv +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALCLK_OFF = 0, /*!< Calibration clock is OFF */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALCLK_DIV17 = 1, /*!< DAC clock divided by 2^17 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALCLK_DIV16 = 2, /*!< DAC clock divided by 2^16 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALCLK_DIV15 = 3, /*!< DAC clock divided by 2^15 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALCLK_DIV14 = 4, /*!< DAC clock divided by 2^14 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALCLK_DIV13 = 5, /*!< DAC clock divided by 2^13 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALCLK_DIV12 = 6, /*!< DAC clock divided by 2^12 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALCLK_DIV11 = 7, /*!< DAC clock divided by 2^11 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALCLK_DIV10 = 8, /*!< DAC clock divided by 2^10 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALCLK_DIV9 = 9, /*!< DAC clock divided by 2^9 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALCLK_DIV8 = 10, /*!< DAC clock divided by 2^8 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALCLK_DIV7 = 11, /*!< DAC clock divided by 2^7 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALCLK_DIV6 = 12, /*!< DAC clock divided by 2^6 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALCLK_DIV6_13 = 13, /*!< DAC clock divided by 2^6 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALCLK_DIV6_14 = 14, /*!< DAC clock divided by 2^6 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALCLK_DIV6_15 = 15 /*!< DAC clock divided by 2^6 */ +} adrv9025_BfTxdacMemMapTxdacCalclkDiv_e; +/** + * \brief Enumeration for txdacCaldacFsc + */ +typedef enum adrv9025_BfTxdacMemMapTxdacCaldacFsc +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALDAC_STEP_0P04 = 0, /*!< 0.04 LSB Step Size (0.67x) */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALDAC_STEP_0P06 = 1, /*!< 0.06 LSB Step Size (1x) */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALDAC_STEP_0P08 = 2, /*!< 0.08 LSB Step Size (1.33x) */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALDAC_STEP_0P12 = 3 /*!< 0.12 LSB Step Size (2x) */ +} adrv9025_BfTxdacMemMapTxdacCaldacFsc_e; +/** + * \brief Enumeration for txdacCaldacOffset + */ +typedef enum adrv9025_BfTxdacMemMapTxdacCaldacOffset +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALDAC_OFFSET_0P0 = 0, /*!< Offset = 0 LSB */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALDAC_OFFSET_3P5 = 1, /*!< Offset = 3.5 LSB */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALDAC_OFFSET_4P0 = 2, /*!< Offset = 4 LSB */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALDAC_OFFSET_4P5 = 3, /*!< Offset = 4.5 LSB */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CALDAC_OFFSET_5P0 = 4 /*!< Offset = 5 LSB */ +} adrv9025_BfTxdacMemMapTxdacCaldacOffset_e; +/** + * \brief Enumeration for txdacCmCtrl + */ +typedef enum adrv9025_BfTxdacMemMapTxdacCmCtrl +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CM_240MV = 0, /*!< Vcommon = 240mV */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CM_270MV = 1, /*!< Vcommon = 270mV */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CM_300MV = 2, /*!< Vcommon = 300mV */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CM_330MV = 3, /*!< Vcommon = 330mV */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CM_360MV = 4, /*!< Vcommon = 360mV */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CM_390MV = 5, /*!< Vcommon = 390mV */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CM_420MV = 6, /*!< Vcommon = 420mV */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_CM_450MV = 7 /*!< Vcommon = 450mV */ +} adrv9025_BfTxdacMemMapTxdacCmCtrl_e; +/** + * \brief Enumeration for txdacCompGainIsb + */ +typedef enum adrv9025_BfTxdacMemMapTxdacCompGainIsb +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_GAIN_ISB_LOW = 0, /*!< Low Accuracy, Fast Settling */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_GAIN_ISB_HIGH = 1 /*!< High Accuracy, Slow Settling */ +} adrv9025_BfTxdacMemMapTxdacCompGainIsb_e; +/** + * \brief Enumeration for txdacCompGainMsb + */ +typedef enum adrv9025_BfTxdacMemMapTxdacCompGainMsb +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_GAIN_MSB_LOWER = 0, /*!< Low Accuracy, Fast Settling */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_GAIN_MSB_LOW = 1, /*!< Medium Accuracy/Settling */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_GAIN_MSB_HIGH = 2, /*!< Not Allowed */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_GAIN_MSB_HIGHER = 3 /*!< High Accuracy, Slow Settling */ +} adrv9025_BfTxdacMemMapTxdacCompGainMsb_e; +/** + * \brief Enumeration for txdacCompIsbavg + */ +typedef enum adrv9025_BfTxdacMemMapTxdacCompIsbavg +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_ISBAVG_1 = 0, /*!< run SAR once */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_ISBAVG_2 = 1, /*!< average 2 SAR runs */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_ISBAVG_4 = 2, /*!< average 4 SAR runs */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_ISBAVG_8 = 3, /*!< average 8 SAR runs */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_ISBAVG_16 = 4, /*!< average 16 SAR runs */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_ISBAVG_32 = 5, /*!< average 32 SAR runs */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_ISBAVG_64 = 6, /*!< average 64 SAR runs */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_ISBAVG_128 = 7 /*!< average 128 SAR runs */ +} adrv9025_BfTxdacMemMapTxdacCompIsbavg_e; +/** + * \brief Enumeration for txdacCompMsbavg + */ +typedef enum adrv9025_BfTxdacMemMapTxdacCompMsbavg +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_MSBAVG_1 = 0, /*!< run SAR once */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_MSBAVG_2 = 1, /*!< average 2 SAR runs */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_MSBAVG_4 = 2, /*!< average 4 SAR runs */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_MSBAVG_8 = 3, /*!< average 8 SAR runs */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_MSBAVG_16 = 4, /*!< average 16 SAR runs */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_MSBAVG_32 = 5, /*!< average 32 SAR runs */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_MSBAVG_64 = 6, /*!< average 64 SAR runs */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_COMP_MSBAVG_128 = 7 /*!< average 128 SAR runs */ +} adrv9025_BfTxdacMemMapTxdacCompMsbavg_e; +/** + * \brief Enumeration for txdacFscBoostI + */ +typedef enum adrv9025_BfTxdacMemMapTxdacFscBoostI +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_FSC4MA = 0, /*!< FSC = 4mA */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_FSC5P6MA = 1 /*!< FSC = 5.6mA */ +} adrv9025_BfTxdacMemMapTxdacFscBoostI_e; +/** + * \brief Enumeration for txdacFscBoostQ + */ +typedef enum adrv9025_BfTxdacMemMapTxdacFscBoostQ +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_FSC4MA = 0, /*!< FSC = 4mA */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_FSC5P6MA = 1 /*!< FSC = 5.6mA */ +} adrv9025_BfTxdacMemMapTxdacFscBoostQ_e; +/** + * \brief Enumeration for txdacPowerdownClkdiv + */ +typedef enum adrv9025_BfTxdacMemMapTxdacPowerdownClkdiv +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_PDCLK_OFF = 0, /*!< Powerdown state machine clock is OFF */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_PDCLK_DIV17 = 1, /*!< DAC clock divided by 2^17 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_PDCLK_DIV16 = 2, /*!< DAC clock divided by 2^16 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_PDCLK_DIV15 = 3, /*!< DAC clock divided by 2^15 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_PDCLK_DIV14 = 4, /*!< DAC clock divided by 2^14 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_PDCLK_DIV13 = 5, /*!< DAC clock divided by 2^13 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_PDCLK_DIV12 = 6, /*!< DAC clock divided by 2^12 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_PDCLK_DIV11 = 7, /*!< DAC clock divided by 2^11 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_PDCLK_DIV10 = 8, /*!< DAC clock divided by 2^10 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_PDCLK_DIV9 = 9, /*!< DAC clock divided by 2^9 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_PDCLK_DIV8 = 10, /*!< DAC clock divided by 2^8 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_PDCLK_DIV7 = 11, /*!< DAC clock divided by 2^7 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_PDCLK_DIV6 = 12, /*!< DAC clock divided by 2^6 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_PDCLK_DIV6_13 = 13, /*!< DAC clock divided by 2^6 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_PDCLK_DIV6_14 = 14, /*!< DAC clock divided by 2^6 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_PDCLK_DIV6_15 = 15 /*!< DAC clock divided by 2^6 */ +} adrv9025_BfTxdacMemMapTxdacPowerdownClkdiv_e; +/** + * \brief Enumeration for txdacSelCalToPin + */ +typedef enum adrv9025_BfTxdacMemMapTxdacSelCalToPin +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_ISBREF_TO_PIN = 0, /*!< isb_ref */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_ISB_TO_PIN = 1, /*!< isb */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_MSBREF_TO_PIN = 2, /*!< msb_ref */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_MSB_TO_PIN = 3 /*!< msb */ +} adrv9025_BfTxdacMemMapTxdacSelCalToPin_e; +/** + * \brief Enumeration for txdacStartupMansel + */ +typedef enum adrv9025_BfTxdacMemMapTxdacStartupMansel +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_STARTUP_SEL_DACCLK = 0, /*!< Normal mode: use txdac_powerdown_clkdiv to generate clock */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_STARTUP_SEL_SPI = 1 /*!< Debug mode: use txdac_startup_manclk to directly drive the clock */ +} adrv9025_BfTxdacMemMapTxdacStartupMansel_e; +/** + * \brief Enumeration for txdacThrowIsbCtrl + */ +typedef enum adrv9025_BfTxdacMemMapTxdacThrowIsbCtrl +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_ISBTHROW_0UA = 0, /*!< 0% ISB throw away current (worst performance) */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_ISBTHROW_600UA = 1, /*!< 33% ISB throw away current (worse performance) */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_ISBTHROW_1200UA = 2, /*!< 66% ISB throw away current (better performance) */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_ISBTHROW_1800UA = 3 /*!< 100% ISB throw away current (best performance) */ +} adrv9025_BfTxdacMemMapTxdacThrowIsbCtrl_e; +/** + * \brief Enumeration for txdacThrowLsbCtrl + */ +typedef enum adrv9025_BfTxdacMemMapTxdacThrowLsbCtrl +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_LSBTHROW_0UA = 0, /*!< 0% LSB throw away current (worst performance) */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_LSBTHROW_400UA = 1, /*!< 33% LSB throw away current (worse performance) */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_LSBTHROW_800UA = 2, /*!< 66% LSB throw away current (better performance) */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_LSBTHROW_1200UA = 3 /*!< 100% LSB throw away current (best performance) */ +} adrv9025_BfTxdacMemMapTxdacThrowLsbCtrl_e; +/** + * \brief Enumeration for txdacWalkPeriod + */ +typedef enum adrv9025_BfTxdacMemMapTxdacWalkPeriod +{ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_WALK_PERIOD_20 = 0, /*!< Update rate = DAC clock divided by 2^20 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_WALK_PERIOD_23 = 1, /*!< Update rate = DAC clock divided by 2^23 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_WALK_PERIOD_26 = 2, /*!< Update rate = DAC clock divided by 2^26 */ + ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_WALK_PERIOD_29 = 3 /*!< Update rate = DAC clock divided by 2^29 */ +} adrv9025_BfTxdacMemMapTxdacWalkPeriod_e; +#ifdef __cplusplus +} +#endif + +#endif // __ADRV9025_BF_TXDAC_MEM_MAP_TYPES_H__ + +/* EOF: adrv9025_bf_txdac_mem_map_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_cals.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_cals.h new file mode 100644 index 0000000..14f7880 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_cals.h @@ -0,0 +1,68 @@ +/** + * \file adrv9025_cals.h + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +/** + * \file adrv9025_cals.h + * \brief Contains ADRV9025 calibration related private function prototypes for + * adrv9025_cals.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADRV9025_CALS_H_ +#define _ADRV9025_CALS_H_ + +#include "adi_adrv9025.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADRV9025_INITOVERRIDE 0xFFFFFFFF + +/** +* \brief Private Helper function to return ARM Calibration error strings. +* +* This is a private function and is automatically called by the API. +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param errCode Error code that allows looking up +* a ARM specific error message. +* +* \retval Returns a character array with the error message specified by +* errCode. +*/ +const char* adrv9025_CalsErrMsgGet(adi_adrv9025_Device_t* device, + uint32_t errCode); + +/** +* \brief Private Helper function to validate initcal structure. +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param initCals Structure pointer to ADRV9025 initcal settings. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_InitCalStructureCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_InitCals_t* initCals); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_cpu.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_cpu.h new file mode 100644 index 0000000..11cac8d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_cpu.h @@ -0,0 +1,315 @@ +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ +# ifndef _ADRV_9025_CPU_H_ +#define _ADRV_9025_CPU_H_ + +#include +#include "adi_adrv9025_types.h" +#include "adi_adrv9025_cpu_types.h" +#include "../../private/include/adrv9025_cpu_macros.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Private Helper function to initialize cpu's data structure +* +* This is a private function and is automatically called by the API. +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* +* \retval Returns a character array with the error message specified by +* errCode. +*/ +void adrv9025_CpuInitialize( + adi_adrv9025_Device_t* device); + +/** +* \brief Private Helper function to get a CPU's key addresses +* +* This is a private function and is automatically called by the API. +* +* \param cpu Structure pointer to the ADRV9025's CPU data structure containing settings +* \param cpuType type of cpu +* \param size size of memory to check starting from addr +* +* \retval Returns a character array with the error message specified by +* errCode. +*/ +adi_adrv9025_CpuAddr_t* adrv9025_CpuAddrGet( + adi_adrv9025_Cpu_t* cpu, + adi_adrv9025_CpuType_e cpuType); + +/** +* \brief Private Helper function to validate cpu memory address before read/write operation +* +* This is a private function and is automatically called by the API. +* +* \param cpu Structure pointer to the ADRV9025's CPU data structure containing settings +* \param addr memory address to check +* \param size size of memory to check starting from addr +* +* \retval Returns a character array with the error message specified by +* errCode. +*/ +uint8_t adrv9025_CpuValidateMemoryAddr( + adi_adrv9025_Cpu_t* cpu, + uint32_t addr, + uint32_t size); + +/** +* \brief Macro to disable spi streaming in case of an error. +* +* \param device Device variable of which spi streaming bit to be restored +* \param recoveryAction Action to be tested against ADI_COMMON_ACT_NO_ACTION +*/ +#define ADRV9025_SPI_STREAM_DISABLE_ON_ERROR(device, recoveryAction) \ + if(recoveryAction != ADI_COMMON_ACT_NO_ACTION) \ + { device->spiSettings.enSpiStreaming = 0; \ + adrv9025_SpiCfgSet(device, &device->spiSettings); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, device->common.error.newAction, NULL, "Failed to set SPI Config"); \ + ADI_ERROR_RETURN(device->common.error.newAction);} + +/** +* \brief Macro to disable spi streaming. +* +* \param device Device variable of which spi streaming bit to be restored +*/ +#define ADRV9025_SPI_STREAM_DISABLE(device) \ + device->spiSettings.enSpiStreaming = 0; \ + adrv9025_SpiCfgSet(device, &device->spiSettings); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, device->common.error.newAction, NULL, "Failed to set SPI Config"); \ + ADI_ERROR_RETURN(device->common.error.newAction); + +/** +* \brief Macro to enable spi streaming. +* When spi streaming is enabled API will write full DMA words +* as A A D D D D packages +* +* \param device Device variable of which spi streaming bit to be restored +*/ +#define ADRV9025_SPI_STREAM_ENABLE(device) \ + device->spiSettings.enSpiStreaming = 1; \ + device->spiSettings.autoIncAddrUp = 1; \ + adrv9025_SpiCfgSet(device, &device->spiSettings); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, device->common.error.newAction, NULL, "Failed to set SPI Config"); \ + ADI_ERROR_RETURN(device->common.error.newAction); + +/** +* \brief Write to the ADRV9025 CPU program or data memory +* +* The user must make sure the memory addresses are valid. +* +* \pre This function is private and is not called directly by the user. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param address The 32-bit CPU address to write +* \param data Byte array (uint8_t) containing data to be written to CPU memory +* \param byteCount Number of bytes in the data array to be written +* \param autoInc is boolean flag to enable or disable auto-increment of CPU register address +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_CpuDmaMemWrite( + adi_adrv9025_Device_t* device, + uint32_t address, + const uint8_t data[], + uint32_t byteCount, + uint8_t autoIncrement); + +/** +* \brief Read from the ADRV9025 CPU program or data memory +* +* The user must make sure the memory addresses are valid. +* +* \pre This function is private and is not called directly by the user. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param address The 32bit CPU address to read from. +* \param returnData Byte(uint8_t) array containing the data read from the CPU memory. +* \param byteCount Number of bytes in the returnData array. +* \param autoIncrement is boolean flag to enable or disable auto-increment of CPU register address +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_CpuDmaMemRead( + adi_adrv9025_Device_t* device, + uint32_t address, + uint8_t returnData[], + uint32_t byteCount, + uint8_t autoIncrement); + +/** +* \brief Private Helper function to return CPU error strings based on the error code. +* +* This is a private function and is automatically called by the API. +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param errCode Error code for looking up CPU a specific error message from a table. +* +* \retval Returns a character array with the error message specified by +* errCode. +*/ +const char* adrv9025_CpuErrCodeToString( + adi_adrv9025_Device_t* device, + uint32_t errCode); + +/** +* \brief Private Helper function to process detected errors reported from the +* cpu to determine recovery action. +* +* This is a private function and is automatically called by the API. +* +* \param device Pointer to device data structure identifying desired device instance +* \param cpuType type of cpu to be checked +* \param errHdl Error Handler type +* \param detErr Error detected to be processed by handler (CPU opcode << 16 | CPU object ID <<8 | CPU cmdStatusByte) +* \param recoveryAction current Recovery Action, +* \param recAction new Recovery Action to be returned should error handler determine an error +* +* \retval uint32_t Value representing the latest recovery Action following processing of detected cpu error. +*/ +int32_t adrv9025_CpuCmdErrorHandler( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + int32_t errHdl, + uint32_t detErr, + int32_t recoveryAction); + +/** +* \brief Writes the ADRV9025 CPU configuration settings +* +* \pre This function is called automatically during adi_adrv9025_CpuStart(), and +* this function must be called after loading the CPU firmware. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{init-> (most members)} +* \dep_end +* +* \param device Pointer to the ADRV9025 device settings data structure +* \param init Pointer to the ADRV9025 initialization settings data structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_CpuAdcProfilesWrite( + adi_adrv9025_Device_t* device, + const adi_adrv9025_AdcProfiles_t* adcProfiles); + +/** +* \brief Loads the ADC profile data into CPU memory +* +* This function writes ADC profile into the CPU data memory before +* loading the CPU firmware. When the CPU firmware is loaded and begins +* to initialize, the CPU init sequence copies the ADC profiles from CPU +* memory and loads them into the CPU firmware internal data strucutures. +* +* \pre This function is called during device after downloading CPU code +* +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device settings data structure +* \param adcProfiles Pointer to the ADRV9025 ADC profile data structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_CpuProfileWrite( + adi_adrv9025_Device_t* device, + const adi_adrv9025_Init_t* init); + +/** +* \brief Private helper function to return CPU System error code +* +* This is a private function and is automatically called by the API. BBIC +* should use the adi_adrv9025_CpuSystemErrorGet function. +* +* \param device Pointer to the ADRV9025 device settings data structure +* \param cpuType Type of cpu +* \param systemErrCode Return systemErrCode read from device +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_CpuSystemErrCodeGet(adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint16_t* systemErrCode); + +/** +* \brief Private helper function to enter serdes test mode +* +* This is a private function that should be used to put the arm into serdes test mode +* +* \param device Pointer to the ADRV9025 device settings data structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_CpuSerdesTestModeEnter(adi_adrv9025_Device_t *device); + +/** +* \brief Private helper function to exit serdes test mode +* +* This is a private function that should be used to exit serdes test mode +* +* \param device Pointer to the ADRV9025 device settings data structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_CpuSerdesTestModeExit(adi_adrv9025_Device_t *device); + +/** +* \brief This function sets the Deserializer configuration. +* This function is used to load the correct setting for the desCfg configuration which is in the init structure depending on the device ID. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param init Pointer to init data structure +* +* \retval ADI_ADRV9025_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JesdDesCfgSet(adi_adrv9025_Device_t *device, + adi_adrv9025_Init_t *init); +#ifdef __cplusplus +} +#endif + +#endif /* _ADRV_9025_CPU_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_cpu_error_mapping.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_cpu_error_mapping.h new file mode 100644 index 0000000..a3e0c9b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_cpu_error_mapping.h @@ -0,0 +1,545 @@ +/** +* \file adrv9025_arm_error_mapping.h +* \brief Contains ARM error tables +* +* \note This file was autogenerated. DO NOT MODIFY. +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2022 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADRV9025_ARM_ERROR_MAPPING_H_ +#define _ADRV9025_ARM_ERROR_MAPPING_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* The firmware revision required for this API */ +#define ADRV9025_ERROR_TABLE_EXPECTED_FW_MAJOR_REV 6u +#define ADRV9025_ERROR_TABLE_EXPECTED_FW_MINOR_REV 4u +#define ADRV9025_ERROR_TABLE_EXPECTED_FW_MAINT_REV 0u +#define ADRV9025_ERROR_TABLE_EXPECTED_FW_BUILD_NUM 6u + +typedef struct adrv9025_arm_api_error +{ + const uint32_t errcode; + const char* const errstr; +} adrv9025_arm_api_error_t; + +const adrv9025_arm_api_error_t adrv9025_error_table_ArmBootStatus[] = +{ + { 0UL, "Used to put API in wait for ARM state" }, + { 1UL, "ARM booted with no failure" }, + { 2UL, "ARM Firmware checksum error" }, + { 3UL, "ARM data memory error" }, + { 4UL, "Stream image checksum error" }, + { 5UL, "Device profile checksum error" }, + { 6UL, "Bootup clkgen setup error" }, + { 7UL, "Bootup Jesd setup error" }, + { 8UL, "Power init setup error" }, + { 9UL, "Jtag build status ready indication" }, + { 10UL, "Bootup clock LOGEN error" }, + { 11UL, "Error initializing RxQEC hardware" }, + { 12UL, "Failed to create Health monitor timers" }, + { 13UL, "ADC RCAL error" }, + { 14UL, "Stream Run error" }, + { 15UL, "Bootup clkgen setup after RCAL error" }, + { 16UL, "LDO configured incorrectly" }, + { 17UL, "Invalid Efuse Channel Config Error" }, + { 18UL, "ARM-D booted with no failure" }, + { 19UL, "ARM-D Firmware checksum error" }, + { 20UL, "ARM-D did not boot, unknown reason" } +}; + +const adrv9025_arm_api_error_t adrv9025_error_table_CmdCtrlMboxCmdError[] = +{ + { 0UL, "No Error" }, + { 1UL, "Nested Mailbox command" }, + { 2UL, "Command not supported" }, + { 3UL, "Invalid state" }, + { 4UL, "Timed out waiting on busy bit" }, + { 5UL, "Timed out waiting on status bit" }, + { 6UL, "Reserved 3" }, + { 7UL, "Command error" } +}; + +const adrv9025_arm_api_error_t adrv9025_error_table_ErrorCode[] = +{ + { 0x0000UL, "No Error" }, + { 0x0001UL, "TXBBF:TX is disabled" }, + { 0x0002UL, "TXBBF:Calibration timed-out" }, + { 0x0003UL, "TXBBF:Calibration results are invalid" }, + { 0x0004UL, "TXBBF:PFIR Set/Read verification failed" }, + { 0x0005UL, "TXBBF:DAC Image capacitor estimate too high" }, + { 0x0006UL, "TXBBF:DAC Image capacitor estimate too low" }, + { 0x0007UL, "TXBBF:DAC Image capacitor estimate above maximum" }, + { 0x0008UL, "TXBBF:Control command not supported" }, + { 0x0009UL, "TXBBF:Invalid filter frequency." }, + { 0x0101UL, "ADCTuner:Calibration Timed-out" }, + { 0x0102UL, "ADCTuner:Invalid channel" }, + { 0x0103UL, "ADCTuner:Self-Test Error" }, + { 0x0104UL, "ADCTuner:Param Profile Select Error" }, + { 0x0201UL, "TIARx:CAL aborted" }, + { 0x0202UL, "TIARx:No solution for RX" }, + { 0x0203UL, "TIARx:RX Stream error" }, + { 0x0204UL, "TIARx:Cal tone error" }, + { 0x0205UL, "TIARx:Control command not supported" }, + { 0x0206UL, "TIARx:Flatness error for RX" }, + { 0x0207UL, "TIARx:Sig Present error for RX" }, + { 0x0208UL, "TIARx:ADC Cal Not run error for RX" }, + { 0x0301UL, "TIAORx:CAL aborted" }, + { 0x0302UL, "TIAORx:No solution for ORX" }, + { 0x0303UL, "TIAORx:ORX Stream error" }, + { 0x0304UL, "TIAORx:Cal tone error" }, + { 0x0305UL, "TIAORx:Control command not supported" }, + { 0x0306UL, "TIAORx:Flatness error for ORX" }, + { 0x0307UL, "TIAORx:Sig Present error for ORX" }, + { 0x0308UL, "TIAORx:ADC Cal Not run error for ORX" }, + { 0x0401UL, "TIALBRx:CAL aborted" }, + { 0x0402UL, "TIALBRx:No solution for LBRX" }, + { 0x0403UL, "TIALBRx:LBRX Stream error" }, + { 0x0404UL, "TIALBRx:Cal tone error" }, + { 0x0405UL, "TIALBRx:Control command not supported" }, + { 0x0406UL, "TIALBRx:Flatness error for LBRX" }, + { 0x0407UL, "TIALBRx:Sig Present error for LBRX" }, + { 0x0408UL, "TIALBRx:ADC Cal Not run error for LBRX" }, + { 0x0501UL, "DCOffsetRx:Calibration timed out" }, + { 0x0502UL, "DCOffsetRx:RXON HI stream errored out" }, + { 0x0503UL, "DCOffsetRx:RXON LOW stream errored out" }, + { 0x0504UL, "DCOffsetRx:Undefined API function called" }, + { 0x0601UL, "DCOffsetORx:Calibration timed out" }, + { 0x0602UL, "DCOffsetORx:ORXON HI stream errored out" }, + { 0x0603UL, "DCOffsetORx:ORXON LOW stream errored out" }, + { 0x0604UL, "DCOffsetORx:Undefined API function called" }, + { 0x0701UL, "DCOffsetLBRx:Calibration timed out" }, + { 0x0702UL, "DCOffsetLBRx:LBRXON HI stream errored out" }, + { 0x0703UL, "DCOffsetLBRx:LBRXON LOW stream errored out" }, + { 0x0801UL, "FlashCal:Calibration aborted" }, + { 0x0802UL, "FlashCal:Calibration timed-out" }, + { 0x0803UL, "FlashCal:No channel is selected" }, + { 0x0804UL, "FlashCal:Rx is disabled" }, + { 0x0805UL, "FlashCal:ORx is disabled" }, + { 0x0806UL, "FlashCal:Final cal result failed threshold test" }, + { 0x0807UL, "FlashCal:Restored data during warm boot is invalid" }, + { 0x0808UL, "FlashCal:Stream reported an error trying to enable Rx/ORx ADCs" }, + { 0x0901UL, "PathDelay:Did not detect a measurable pathdelay" }, + { 0x0902UL, "PathDelay:Measured TX power is too low" }, + { 0x0903UL, "PathDelay:Measured correlated power too low" }, + { 0x0904UL, "PathDelay:TXQEC pathdelay peak is not strong (bad PFIR?)" }, + { 0x0905UL, "PathDelay:No loopback is enabled for pathdelay" }, + { 0x0A01UL, "TxLOLIntInit:Pathdelay invalid" }, + { 0x0A02UL, "TxLOLIntInit:Data capture timed-out due to HW setup" }, + { 0x0A03UL, "TxLOLIntInit:Batch time too small" }, + { 0x0A04UL, "TxLOLIntInit:Offset LO not enabled" }, + { 0x0A05UL, "TxLOLIntInit:Data capture was aborted" }, + { 0x0A06UL, "TxLOLIntInit:Data capture timed-out" }, + { 0x0A07UL, "TxLOLIntInit:Data capture failed due to channel pause" }, + { 0x0A08UL, "TxLOLIntInit:No data was captured" }, + { 0x0B0AUL, "TxLOLIntInit:Wrong baseband is active" }, + { 0x0B01UL, "TxLOLExtInit:Initial Cal did not run first" }, + { 0x0B02UL, "TxLOLExtInit:Pathdelay invalid" }, + { 0x0B03UL, "TxLOLExtInit:Data capture error due to HW" }, + { 0x0B04UL, "TxLOLExtInit:Batch time too small" }, + { 0x0B05UL, "TxLOLExtInit:Data capture was aborted" }, + { 0x0B06UL, "TxLOLExtInit:Data capture timed-out" }, + { 0x0B07UL, "TxLOLExtInit:No data was captured" }, + { 0x0B08UL, "TxLOLExtInit:No Orx assigned to the TX channel" }, + { 0x0B09UL, "TxLOLExtInit:Orx assigned to the TX channel, is not configured" }, + { 0x0B0AUL, "TxLOLExtInit:Wrong baseband is active" }, + { 0x0C01UL, "TxQECInit:TX is disabled" }, + { 0x0C02UL, "TxQECInit:LBRX is disabled" }, + { 0x0C03UL, "TxQECInit:No pathdelay estimate present" }, + { 0x0C04UL, "TxQECInit:Offset LO not enabled" }, + { 0x0C05UL, "TxQECInit:Channel estimate never reached variance" }, + { 0x0C06UL, "TxQECInit:Channel estimate calculation error" }, + { 0x0C07UL, "TxQECInit:Correlation capture timed-out or was aborted" }, + { 0x0C08UL, "TxQECInit:Correlation capture timed-out or was aborted" }, + { 0x0C09UL, "TxQECInit:Correlation capture error" }, + { 0x0C0AUL, "TxQECInit:Tone measurement error" }, + { 0x0C0BUL, "TxQECInit:No signal present" }, + { 0x0C0CUL, "TxQECInit:Need estimate for coarse change transition point" }, + { 0x0C0DUL, "TxQECInit:Decrementing fine phase, coarse value railed" }, + { 0x0C0EUL, "TxQECInit:Incrementing fine phase, coarse value railed" }, + { 0x0C0FUL, "TxQECInit:Tone measurement saturated error" }, + { 0x0D01UL, "LBRxLODelay:TX is disabled" }, + { 0x0D02UL, "LBRxLODelay:LBRX is disabled" }, + { 0x0D03UL, "LBRxLODelay:PLL setup error" }, + { 0x0D04UL, "LBRxLODelay:Data Capture Error" }, + { 0x0D05UL, "LBRxLODelay:Coarse phase estimate Error" }, + { 0x0D06UL, "LBRxLODelay:Fine phase estimate Error" }, + { 0x0D07UL, "LBRxLODelay:Output phase error too large (self-test)" }, + { 0x0D08UL, "LBRxLODelay:Data Capture Abort Error" }, + { 0x0D09UL, "LBRxLODelay:Loop-back tone signal power too weak" }, + { 0x0E01UL, "LBRxTCAL:LBRX TCAL RxQec3 obs image power error" }, + { 0x0E02UL, "LBRxTCAL:LBRX TCAL RxQec3 obs insufficient power error" }, + { 0x0E03UL, "LBRxTCAL:LBRX TCAL RxQec3 obs numerical error" }, + { 0x0E04UL, "LBRxTCAL:LBRX TCAL RxQec3 obs no new data" }, + { 0x0E05UL, "LBRxTCAL:LBRX TCAL data capture error" }, + { 0x0E06UL, "LBRxTCAL:Hclip error" }, + { 0x0F01UL, "RxLODelay:RX is disabled" }, + { 0x0F02UL, "RxLODelay:Data Capture Error" }, + { 0x1001UL, "RxTCAL:RxQec3 obs image power error" }, + { 0x1002UL, "RxTCAL:RxQec3 obs insufficient power error" }, + { 0x1003UL, "RxTCAL:RxQec3 obs numerical error" }, + { 0x1004UL, "RxTCAL:RxQec3 obs no new data" }, + { 0x1005UL, "RxTCAL:Data capture error" }, + { 0x1006UL, "RxTCAL:Hclip error" }, + { 0x1101UL, "ORXLODelay:ORX is disabled" }, + { 0x1102UL, "ORXLODelay:Data Capture Error" }, + { 0x1201UL, "ORxTCAL:RxQec3 obs image power error" }, + { 0x1202UL, "ORxTCAL:RxQec3 obs insufficient power error" }, + { 0x1203UL, "ORxTCAL:RxQec3 obs numerical error" }, + { 0x1204UL, "ORxTCAL:RxQec3 obs no new data" }, + { 0x1205UL, "ORxTCAL:data capture error" }, + { 0x1206UL, "ORxTCAL:Hclip error" }, + { 0x1301UL, "TxDAC:DAC supply clock error" }, + { 0x1302UL, "TxDAC:DAC channel I not powered up" }, + { 0x1303UL, "TxDAC:DAC channel Q not powered up" }, + { 0x1304UL, "TxDAC:DAC channel I calibration didn't finish" }, + { 0x1305UL, "TxDAC:DAC channel Q calibration didn't finish" }, + { 0x1306UL, "TxDAC:DAC channel I saturated" }, + { 0x1307UL, "TxDAC:DAC channel Q saturated" }, + { 0x1308UL, "TxDAC:DAC channel I clock not powered down" }, + { 0x1309UL, "TxDAC:DAC channel Q clock not powered down" }, + { 0x1401UL, "DPDExt:DPD hardware is being used by other cals" }, + { 0x1402UL, "DPDExt:Stream Error" }, + { 0x1403UL, "DPDExt:Tx transition occurs during capture" }, + { 0x1404UL, "DPDExt:Global peak copy didn't complete in time" }, + { 0x1405UL, "DPDExt:Failed to create external DPD task" }, + { 0x1406UL, "DPDExt:Failed to create the event group" }, + { 0x1407UL, "DPDExt:The given model number is beyond number of models supported" }, + { 0x1408UL, "DPDExt:Recieved a new model update command while one is in progress" }, + { 0x1801UL, "TxAttenDelay:Invalid value" }, + { 0x1802UL, "TxAttenDelay:Invalid NCO power level" }, + { 0x1803UL, "TxAttenDelay:Calibration failed to start" }, + { 0x1804UL, "TxAttenDelay:Calibration value too low" }, + { 0x1805UL, "TxAttenDelay:Calibration value too high" }, + { 0x1806UL, "TxAttenDelay:Max deviation in cal results reached" }, + { 0x1807UL, "TxAttenDelay:Calibration timed-out" }, + { 0x1901UL, "TxAtten:Log timeout error" }, + { 0x1902UL, "TxAtten:Log read error" }, + { 0x1903UL, "TxAtten:Gain table error" }, + { 0x1904UL, "TxAtten:Rxqec hw log error" }, + { 0x1905UL, "TxAtten:Rxqec hw log error" }, + { 0x1906UL, "TxAtten:Phase measurement tone is OOB, not NCO shiftable for Phase measurement" }, + { 0x1907UL, "TxAtten:Phase measurement curve fit error" }, + { 0x1908UL, "TxAtten:Tx LO and Aux LO are not synchronized" }, + { 0x1A01UL, "RxGainDelay:Tone power too low" }, + { 0x1A02UL, "RxGainDelay:Calibration failed to start" }, + { 0x1A03UL, "RxGainDelay:Calibration value too low" }, + { 0x1A04UL, "RxGainDelay:Calibration value too high" }, + { 0x1A05UL, "RxGainDelay:Max deviation in cal results reached" }, + { 0x1A06UL, "RxGainDelay:Calibration timed-out" }, + { 0x1B01UL, "RxPhaseInit:log timeout error" }, + { 0x1B02UL, "RxPhaseInit:log read error" }, + { 0x1B03UL, "RxPhaseInit:gain table error" }, + { 0x1B04UL, "RxPhaseInit:rxqec hw log error" }, + { 0x1B05UL, "RxPhaseInit:rxqec hw log error" }, + { 0x1E01UL, "SERDES:Lane is powered down" }, + { 0x1E02UL, "SERDES:Control command not supported" }, + { 0x1E03UL, "SERDES:Best rset value not found" }, + { 0x1E04UL, "SERDES:Set Cal args Error" }, + { 0x1E05UL, "SERDES:Invalid temperature" }, + { 0x1E06UL, "SERDES:ALC calibration timeout" }, + { 0x1E07UL, "SERDES: Failed to create serdes semaphore" }, + { 0x1E08UL, "SERDES: Failed to take serdes semaphore" }, + { 0x1D01UL, "TxCFR:configuration error" }, + { 0x1D02UL, "TxCFR:unknown programming pulse mode" }, + { 0x1D03UL, "TxCFR:input rate exceeds max supported" }, + { 0x1D04UL, "TxCFR:control command not supported" }, + { 0x3001UL, "RxQECTrack:data capture error" }, + { 0x3002UL, "RxQECTrack:observation clipping, indicating setup error" }, + { 0x3003UL, "RxQECTrack:correction update semaphore error" }, + { 0x3004UL, "RxQECTrack:model has diverged and has been reset" }, + { 0x3201UL, "TxLOLTrack:Capture error" }, + { 0x3202UL, "TxLOLTrack:Capture abort error" }, + { 0x3203UL, "TxLOLTrack:Overflow warning" }, + { 0x3204UL, "TxLOLTrack:Pathdelay invalid" }, + { 0x3205UL, "TxLOLTrack:LOL Internal init calibration not done" }, + { 0x3206UL, "TxLOLTrack:No data was captured" }, + { 0x3207UL, "TxLOLTrack:No Orx assigned to the TX channel" }, + { 0x3208UL, "TxLOLTrack:Not all batches were run" }, + { 0x3209UL, "TxLOLTrack:Orx assigned to the TX channel, is not configured" }, + { 0x320AUL, "TxLOLTrack:Capture timed-out" }, + { 0x320BUL, "TxLOLTrack:Dummy capture failed" }, + { 0x320CUL, "TxLOLTrack:LOL External init calibration not done" }, + { 0x320DUL, "TxLOLTrack:Performed channel reset due to PLL changes" }, + { 0x320EUL, "TxLOLTrack:Wrong baseband is active" }, + { 0x3301UL, "TxQECTrack:Correlation capture error" }, + { 0x3302UL, "TxQECTrack:Correlation capture error" }, + { 0x3303UL, "TxQECTrack:Initial calibration not done" }, + { 0x3304UL, "TxQECTrack:No signal present" }, + { 0x3305UL, "TxQECTrack:Channel variance is invalid" }, + { 0x3306UL, "TxQECTrack:Correlation output buffer is null" }, + { 0x3307UL, "TxQECTrack:Correlation output buffer is not full" }, + { 0x3308UL, "TxQECTrack:Capture timed-out" }, + { 0x3309UL, "TxQECTrack:Capture ended with no solution" }, + { 0x320AUL, "TxQECTrack:Wrong baseband is active" }, + { 0x3401UL, "DPDTrack:reserved" }, + { 0x3402UL, "DPDTrack:reserved" }, + { 0x3403UL, "DPDTrack:Pathdelay not setup yet" }, + { 0x3404UL, "DPDTrack:reserved" }, + { 0x3405UL, "DPDTrack:ORx signal is too small" }, + { 0x3406UL, "DPDTrack:ORx signal is saturating" }, + { 0x3407UL, "DPDTrack:TX signal is too small" }, + { 0x3408UL, "DPDTrack:TX signal is saturating" }, + { 0x3409UL, "DPDTrack:reserved" }, + { 0x340AUL, "DPDTrack:Too many AM-AM outliers" }, + { 0x340BUL, "DPDTrack:DPD coefficients unavailable" }, + { 0x340CUL, "DPDTrack:DPD data capture loop time out" }, + { 0x340DUL, "DPDTrack:Unity model unavailable error" }, + { 0x340EUL, "DPDTrack:DPD LDL negative diagonal or INF detected" }, + { 0x340FUL, "DPDTrack:Maximum partial partitions reached" }, + { 0x3410UL, "DPDTrack:RPC send failed" }, + { 0x3411UL, "DPDTrack:Unknown RPC message received" }, + { 0x3412UL, "DPDTrack:Timed out waiting for RPC message" }, + { 0x3413UL, "DPDTrack:Could not create mutex" }, + { 0x3414UL, "DPDTrack:ACT I assignment conflict error" }, + { 0x3415UL, "DPDTrack:ACT K assignment exceed limit error" }, + { 0x3416UL, "DPDTrack:ACT multiplier row assignment conflict error" }, + { 0x3417UL, "DPDTrack:ACT LUT out of range error" }, + { 0x3418UL, "DPDTrack:ACT no free multiplier error" }, + { 0x3419UL, "DPDTrack:ACT write LUT error" }, + { 0x341AUL, "DPDTrack:DPD hardware is being used by other cals" }, + { 0x341BUL, "DPDTrack:DPD data capture error" }, + { 0x341CUL, "DPDTrack:DPD x-correlation error" }, + { 0x341DUL, "DPDTrack:DPD stability error occurs" }, + { 0x341EUL, "DPDTrack:DPD cholesky diagonal term too small" }, + { 0x341FUL, "DPDTrack:DPD-CLGC synchronization error" }, + { 0x3420UL, "DPDTrack:ACT LUT Entry Saturated" }, + { 0x3421UL, "DPDTrack:DPD data capture timeout error" }, + { 0x3422UL, "DPDTrack:Message Send RPC send failed" }, + { 0x3423UL, "DPDTrack:Do Reset RPC send failed" }, + { 0x3424UL, "DPDTrack:Message Get RPC send failed" }, + { 0x3501UL, "CLGCTrack:Correlation capture error" }, + { 0x3502UL, "CLGCTrack:Correlation capture abort error" }, + { 0x3503UL, "CLGCTrack:Pathdelay not found error" }, + { 0x3504UL, "CLGCTrack:Fail to apply tx atten error" }, + { 0x3505UL, "CLGCTrack:Tx atten limit error" }, + { 0x3506UL, "CLGCTrack:Convergence limit error" }, + { 0x3507UL, "CLGCTrack:PA protection error" }, + { 0x3508UL, "CLGCTrack:CLGC-DPD synchronization error" }, + { 0x3509UL, "CLGCTrack:Tx power level too low error" }, + { 0x350AUL, "CLGCTrack:ORx power level too low error" }, + { 0x350BUL, "CLGCTrack:Tx power measurement error" }, + { 0x350CUL, "CLGCTrack:ORx power measurement error" }, + { 0x350DUL, "CLGCTrack:Data capture timeout caused by invalid tx-to-orx mapping" }, + { 0x3701UL, "HD2Track: HD2 correction filter mapping error" }, + { 0x3801UL, "Initial calibration not done" }, + { 0x3802UL, "Serdes lane powered down" }, + { 0x3803UL, "Capture error" }, + { 0x3804UL, "Cal exit requested" }, + { 0x3804UL, "Status request argument invalid" }, + { 0x6001UL, "GPIOCtrl:Given signal ID is invalid" }, + { 0x6002UL, "GPIOCtrl:The given GPIO number is invalid" }, + { 0x6B01UL, "Loopfilter:PLL Selected invalid" }, + { 0x6B02UL, "Loopfilter:Input Selected invalid" }, + { 0x7701UL, "SRL:Slew Rate Limiter detected overload" }, + { 0x7702UL, "SRL:Init cals can't run when SRL is enabled" }, + { 0x7703UL, "SRL:Operation failed because SRL violation is in active progress" }, + { 0x7E01UL, "CaptureORx:Capture timed-out" }, + { 0x7E02UL, "CaptureORx:Number of samples not a power of 2" }, + { 0x7E03UL, "CaptureORx:Invalid TX input channel mask" }, + { 0x7E04UL, "CaptureORx:Invalid ORX input channel mask" }, + { 0x7E05UL, "CaptureORx:Required TX stream is disabled" }, + { 0x7E06UL, "CaptureORx:Required ORX stream is disabled" }, + { 0x7E07UL, "CaptureORx:For playback" }, + { 0x8001UL, "DeviceProfile:Checksum error" }, + { 0x8002UL, "DeviceProfile:Missing data for enabled channel" }, + { 0x8003UL, "DeviceProfile:ADC tuner profile checksum error" }, + { 0x8301UL, "Scheduler:A cal timed out while waiting for Scheduler to abort a data capture" }, + { 0x8302UL, "Scheduler:An invalid cal ID is passed to the Scheduler" }, + { 0x8303UL, "Scheduler:Scheduler received a PAUSED event that it was not expecting" }, + { 0x8101UL, "RadioEvent:TXCAL_ENADIS command cannot be issued as a pin is mapped to control it" }, + { 0xB001UL, "NCO:Invalid input parameters" }, + { 0xB101UL, "Stream:Invalid input parameters" }, + { 0xB102UL, "Stream:Timer expired waiting for stream completion" }, + { 0xB103UL, "Stream:Triggered stream reported an error" }, + { 0xB104UL, "Stream:Failed checksum verification" }, + { 0xB105UL, "Stream:Reported a FIFO error" }, + { 0xB106UL, "Stream:Reported an external timer error" }, + { 0xB107UL, "Stream:Reported an invalid instruction" }, + { 0xB108UL, "Stream:Reported an invalid AHB address" }, + { 0xB109UL, "Stream:Reported an invalid stream number" }, + { 0xB10AUL, "Stream:Reported a stack overflow" }, + { 0xB10BUL, "Stream:Reported a timeout error" }, + { 0xB10CUL, "Stream:Reported a check instruction error" }, + { 0xB10DUL, "Stream:Reported an invalid SPI address" }, + { 0xB10EUL, "Stream:Previous Stream didn't finish" }, + { 0xB10FUL, "Stream:Undefined Error" }, + { 0xB201UL, "PFIR:Invalid configuration" }, + { 0xB301UL, "JESD:Framer lane overlap" }, + { 0xB302UL, "JESD:Deframer lane overlap" }, + { 0xB303UL, "JESD:Framer number too larger" }, + { 0xB304UL, "JESD:Deframer number too larger" }, + { 0xB305UL, "JESD:Framer S is not a power of 2" }, + { 0xB306UL, "JESD:Deframer M not a power of 2" }, + { 0xB307UL, "JESD:Number of framer lanes must be more than 0" }, + { 0xB308UL, "JESD:No enabled deframer lanes" }, + { 0xB309UL, "JESD:Framer number of converters (M) set to 0" }, + { 0xB30AUL, "JESD:Framer number of converters is not a power of 2" }, + { 0xB30BUL, "JESD:Framer sample rate divide ratio not power of 2" }, + { 0xB30CUL, "JESD:Deframer sample rate divide ratio not power of 2" }, + { 0xB30DUL, "JESD:Framer0 must be enabled" }, + { 0xB30EUL, "JESD:bitRepeatRatio is not a power of 2" }, + { 0xB30FUL, "JESD:bitSplitRatio is not a power of 2" }, + { 0xB310UL, "JESD:Framer pclk divide ratio not a power of 2" }, + { 0xB311UL, "JESD:Failed to configure line clock" }, + { 0xB312UL, "JESD:Serdes PLL invalid input parameters" }, + { 0xB313UL, "JESD:Serdes PLL failed to calibrate or lock" }, + { 0xB314UL, "JESD:Driver not initialized" }, + { 0xB315UL, "JESD:Framer lane clock invalid" }, + { 0xB316UL, "JESD:Deframer lane clock invalid" }, + { 0xB317UL, "JESD:Unsupported configuration" }, + { 0xB318UL, "JESD:Framer sample rate is zero" }, + { 0xB319UL, "JESD:Deframer sample rate is zero" }, + { 0xB31AUL, "JESD:Invalid TX config detected by Jesd h/w block" }, + { 0xB31BUL, "JESD:Invalid RX config detected by Jesd h/w block" }, + { 0xB31CUL, "JESD:Invalid Framer Sample Xbar entry" }, + { 0xB31DUL, "JESD:Framer fast pclk divide ratio not integer" }, + { 0xB31EUL, "JESD:Framer pclk divide ratio not integer" }, + { 0xB31FUL, "JESD:Invalid Framer Sync Pad configuration" }, + { 0xB320UL, "JESD:Invalid Deframer Sync Pad configuration" }, + { 0xB321UL, "JESD:Deframer S is not a power of 2" }, + { 0xB322UL, "JESD:Framer link sharing configuration invalid" }, + { 0xB323UL, "JESD:Serdes Master Reset active" }, + { 0xB324UL, "JESD:Invalid Deframer Sample Xbar entry" }, + { 0xB325UL, "JESD:Invalid Framer link layer mode of operation" }, + { 0xB326UL, "JESD:Invalid Deframer link layer mode of operation" }, + { 0xB327UL, "JESD:Framer link sharing number of converters (M) invalid" }, + { 0xB401UL, "RxQECHWDrv:Error configuring RxQEC core clocks" }, + { 0xB402UL, "RxQECHWDrv:Error configuring RxQEC channel clocks" }, + { 0xB403UL, "RxQECHWDrv:QFIR overflow error, unable to represent desired filter in hardware" }, + { 0xB404UL, "RxQECHWDrv:LOC overflor error, unable to represent desired phase coefficient in hardware" }, + { 0xB405UL, "RxQECHWDrv:CFIR overflor error, unable to represent desired filter in hardware" }, + { 0xB406UL, "RxQECHWDrv:Error while attempting to halt an OBS engine" }, + { 0xB407UL, "RxQECHWDrv:Attempted to use an observation engine that was already allocated to another cal" }, + { 0xB408UL, "RxQECHWDrv:Attempted to release an observation engine that was allocated to another cal" }, + { 0xB409UL, "RxQECHWDrv:Error configuring RxQEC observation profiles" }, + { 0xB40AUL, "RxQECHWDrv:Observation data FIFO full" }, + { 0xB501UL, "TxAttenDrv:Wrong SPI mode for operation" }, + { 0xB502UL, "TxAttenDrv:Invalid HP attenuation value" }, + { 0xB503UL, "TxAttenDrv:Invalid digital attenuation value" }, + { 0xB504UL, "TxAttenDrv:Set attenuation state using invalid structure" }, + { 0xB601UL, "TxQECDrv:NCO synchronization timed-out" }, + { 0xB602UL, "TxQECDrv:NCO Set frequency is invalid" }, + { 0xB603UL, "TxQECDrv:Txqec correlator didn't finish" }, + { 0xB604UL, "TxQECDrv:NCO Offset LO Sync is inactive" }, + { 0xB605UL, "TxQECDrv:NCO Offset LO is not synced" }, + { 0x7F01UL, "TestMode:Invalid test task requested" }, + { 0xF001UL, "TestModeClkPll:Not in CLKPLL_SWEEP Test Mode" }, + { 0xF002UL, "TestModeClkPll:Frequency is out of range" }, + { 0xF003UL, "TestModeClkPll:BW parameter is out of range" }, + { 0xF101UL, "TestModeTxBBF:Not in TXBBF_3DB_SWEEP Test Mode" }, + { 0xF201UL, "TestModeTIA:Not in TIA_3DB_SWEEP Test Mode" }, + { 0xF202UL, "TestModeTIA:Frequency is out of range" }, + { 0xF203UL, "TestModeTIA:Invalid Channel Type" }, + { 0xF301UL, "TestModeLBRx:Not in LOOPBACK Ctrl Test Mode" }, + { 0xF302UL, "TestModeLBRx:Invalid Channel Type" }, + { 0xF401UL, "TestModeCBus:Not in CBUS R/W Ctrl Test Mode" }, + { 0xF402UL, "TestModeCBus:Invalid address Type" }, + { 0xFA01UL, "TestModeSerdes:Mode not supported on this platform" }, + { 0xFA02UL, "TestModeSerdes:Not in Serdes Test Mode" }, + { 0xFC01UL, "TestModeSerdes:Mode not supported on this platform" }, + { 0xFC02UL, "TestModeSerdes:Not in Serdes BG Cals Test Mode" }, + { 0xFF01UL, "System:PLL Synth Lock Failed" }, + { 0xFF02UL, "System:PLL Charge Pump Calibration error" }, + { 0xFF03UL, "System:PLL Calculation error" }, + { 0xFF04UL, "System:PLL input freq out of range" }, + { 0xFF05UL, "System:PLL Invalid PLL type" }, + { 0xFF06UL, "System:SysClk parameter out of range" }, + { 0xFF07UL, "System:HSDig calculations did not match API settings" }, + { 0xFF08UL, "System:Rx Setup Error" }, + { 0xFF09UL, "System:Orx Setup Error" }, + { 0xFF0AUL, "System:Tx Setup Error" }, + { 0xFF0BUL, "System:SysPLL Flagged an error." }, + { 0xFF0CUL, "System:Logen range error." }, + { 0xFF0DUL, "System:Logen bad path error." }, + { 0xFF0EUL, "System:MCS did not complete" }, + { 0xFF0FUL, "System:SERDES PLL Synth Lock Failed" }, + { 0xFF10UL, "System:SERDES PLL Invalid Input Parameter" }, + { 0xFF11UL, "System:Init cal invalid sequenct length" }, + { 0xFF12UL, "System:RF PLL Frequency not set" }, + { 0xFF13UL, "System:Tone path not configured" }, + { 0xFF14UL, "System:Init cal interrupted by ABORT command" }, + { 0xFF15UL, "System:Init cal warm boot checksum error" }, + { 0xFF16UL, "System:Init cal invalid channel mask error" }, + { 0xFF17UL, "System:Profile checksum failed or bad profile wrt to EFUSE" }, + { 0xFF18UL, "System:Clock generation error" }, + { 0xFF19UL, "System:JESD Error" }, + { 0xFF1AUL, "System:Stream checksum failed" }, + { 0xFF1BUL, "System:Could not create the task" }, + { 0xFF1CUL, "System:Could not create the event" }, + { 0xFF1DUL, "System:Could not create the Queue" }, + { 0xFF1EUL, "System:Could not create the timer" }, + { 0xFF1FUL, "System:Failed to post the message" }, + { 0xFF20UL, "System:Failed to receive the message" }, + { 0xFF21UL, "System:GP Timer driver error" }, + { 0xFF22UL, "System:Mailbox critical error" }, + { 0xFF23UL, "System:Health monitoring timer timedout" }, + { 0xFF24UL, "System:Commands sent to task that does not exist" }, + { 0xFF25UL, "System:Invalid message passed to ctrl task" }, + { 0xFF26UL, "System:Invalid mailbox command passed to ctrl task" }, + { 0xFF27UL, "System:The given cal does not support the control function" }, + { 0xFF28UL, "System:The given cal does not support the set config function" }, + { 0xFF29UL, "System:The given cal does not support the get config function" }, + { 0xFF2AUL, "System:The given cal does not support the get status function" }, + { 0xFF2BUL, "System:The given channel is not enabled in the profile" }, + { 0xFF2CUL, "System:The given target configuration object is invalid" }, + { 0xFF2DUL, "System:The given configuration size is invalid" }, + { 0xFF2EUL, "System:The given configuration offset is invalid" }, + { 0xFF2FUL, "System:The config cannot be updated in current state of module" }, + { 0xFF30UL, "System:AUX PLL NORMAL VCO failed to start" }, + { 0xFF31UL, "System:AUX PLL NORMAL VCO to complete" }, + { 0xFF32UL, "System:AUX PLL FAST VCO failed to start" }, + { 0xFF33UL, "System:AUX PLL FAST VCO failed to complete" }, + { 0xFF34UL, "System:PLL Temperature Time Out error" }, + { 0xFF35UL, "System:PLL Not Enabled" }, + { 0xFF36UL, "System:PLL Phase Sync Invalide Setting error" }, + { 0xFF37UL, "System:PLL Phase Sync cal timeout error" }, + { 0xFF38UL, "System:SERDES PLL Invalid divM value" }, + { 0xFF39UL, "System:SERDES PLL Invalid rxdivrate value" }, + { 0xFF3AUL, "System:JTAG Debug Build Error Code" }, + { 0xFF3BUL, "System:Internal MCS did not complete" }, + { 0xFF3CUL, "System:DDC calculations were out of bounds" }, + { 0xFF3DUL, "System:DDC Invalid band selected for Get_DCC parameters" }, + { 0xFF3EUL, "System:WDT config invalid (most likely in Debug mode = no WDT)" }, + { 0xFF3FUL, "System:AHB slice error" }, + { 0xFF40UL, "System:LDO Bypass not configured correctly" }, + { 0xFF41UL, "System:AUX Adc timed out" }, + { 0xFF42UL, "System:Semaphore take operation failure" }, + { 0xFF43UL, "System:RF1 PLL NORMAL VCO failed to start" }, + { 0xFF44UL, "System:RF1 PLL NORMAL VCO to complete" }, + { 0xFF45UL, "System:RF1 PLL FAST VCO failed to start" }, + { 0xFF46UL, "System:RF1 PLL FAST VCO failed to complete" }, + { 0xFF47UL, "System:RF2 PLL NORMAL VCO failed to start" }, + { 0xFF48UL, "System:RF2 PLL NORMAL VCO to complete" }, + { 0xFF49UL, "System:RF2 PLL FAST VCO failed to start" }, + { 0xFF4AUL, "System:RF2 PLL FAST VCO failed to complete" }, + { 0xFF4BUL, "System:SERDES PLL Invalid value of B parameter" }, + { 0xFF4CUL, "System:SERDES PLL Invalid value of refClkIn" }, + { 0xFF4DUL, "System:Pre init cal AUX:Synth Lock Failed" }, + { 0xFF4EUL, "System:Post init cal AUX Synth Lock Failed" }, + { 0xFF4FUL, "System:Pre Init cal TxQEC NCO lock failed" }, + { 0xFF50UL, "System:Post Init cal TxQEC NCO lock failed" }, + { 0xFF51UL, "System:DualBand Configuration Error" }, + { 0xFF52UL, "System:Semaphore create error" }, + { 0xFF53UL, "System:Semaphore give error" }, + { 0xFF54UL, "System:Tx Tracking cals cannot be scheduled" }, + { 0xFF55UL, "System:Core stream external timer error" }, + { 0xFF56UL, "System:Unable to read EFUSE" }, + { 0xFF57UL, "System:ARMD did not complete booting" }, + { 0xFF58UL, "System:pll and jesd gain ramp down event active" } +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_cpu_macros.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_cpu_macros.h new file mode 100644 index 0000000..098983a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_cpu_macros.h @@ -0,0 +1,277 @@ +/** + * \file adrv9025_cpu_macros.h + * \brief Contains ADRV9025 API miscellaneous macro definitions for CPU + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADRV_9025_CPU_MACROS_H_ +#define _ADRV_9025_CPU_MACROS_H_ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define ADRV9025_CPU_JESD_FRAMERB_OFFSET 0x28 +#define ADRV9025_CPU_JESD_DEFRAMERB_OFFSET 0x50 + +/* The mailbox interface 3 bit error flag has a subset of error flags +* that are common to all cpu commands. +*/ +#define ADRV9025_CPU_NUM_COMMON_ERR_FLAGS 0x04 +#define ADRV9025_CPU_NUM_COMMON_SET_ERR_FLAGS 0x05 +#define ADRV9025_CPU_NUM_COMMON_GET_ERR_FLAGS 0x05 + +/* Cpu Error Flag Source */ +#define ADRV9025_CPU_EFSRC_INITCALS 0x10 +#define ADRV9025_CPU_EFSRC_SETRFPLL 0x20 +#define ADRV9025_CPU_EFSRC_SETPENDING 0x30 +#define ADRV9025_CPU_EFSRC_SETGPIOCTRL 0x40 +#define ADRV9025_CPU_EFSRC_BOOTUP 0x100 + +#define ADRV9025_CPU_ABORT_OPCODE 0x00 +#define ADRV9025_CPU_RUNINIT_OPCODE 0x02 +#define ADRV9025_CPU_RADIOON_OPCODE 0x04 +#define ADRV9025_CPU_SET_OPCODE 0x0A +#define ADRV9025_CPU_GET_OPCODE 0x0C +#define ADRV9025_CPU_TEST_OPCODE 0x0E +#define ADRV9025_CPU_STREAM_TRIGGER_OPCODE 0x1F + +#define ADRV9025_CPU_ORX1_TX_SEL0_SIGNALID 0x00 +#define ADRV9025_CPU_ORX1_TX_SEL1_SIGNALID 0x01 +#define ADRV9025_CPU_ORX2_TX_SEL0_SIGNALID 0x02 +#define ADRV9025_CPU_ORX2_TX_SEL1_SIGNALID 0x03 +#define ADRV9025_CPU_ORX3_TX_SEL0_SIGNALID 0x04 +#define ADRV9025_CPU_ORX3_TX_SEL1_SIGNALID 0x05 +#define ADRV9025_CPU_ORX4_TX_SEL0_SIGNALID 0x06 +#define ADRV9025_CPU_ORX4_TX_SEL1_SIGNALID 0x07 +#define ADRV9025_CPU_TX12CAL_ENA_SIGNALID 0x08 +#define ADRV9025_CPU_TX34CAL_ENA_SIGNALID 0x09 +#define ADRV9025_CPU_CAL_UPDATE0_SIGNALID 0x0A +#define ADRV9025_CPU_CAL_UPDATE1_SIGNALID 0x0B +#define ADRV9025_CPU_CAL_UPDATE2_SIGNALID 0x0C +#define ADRV9025_CPU_RF_PLL_FREQ_HOP_SIGNALID 0x0D +#define ADRV9025_CPU_EXT_DPD_CAPTURE_TRIG_SIGNALID 0x0E +#define ADRV9025_CPU_EXT_DPD_MODEL_SEL0_SIGNALID 0x0F +#define ADRV9025_CPU_EXT_DPD_MODEL_SEL1_SIGNALID 0x10 +#define ADRV9025_CPU_EXT_DPD_CAPTURE_DONE_SIGNALID 0x11 + +#define ADRV9025_CPU_OBJECTID_TXBBF_INIT 0x00 +#define ADRV9025_CPU_OBJECTID_ADCTUNER_INIT 0x01 +#define ADRV9025_CPU_OBJECTID_TIA_INIT 0x02 +#define ADRV9025_CPU_OBJECTID_ORXTIA_INIT 0x03 +#define ADRV9025_CPU_OBJECTID_LBRXTIA_INIT 0x04 +#define ADRV9025_CPU_OBJECTID_DCOFFSET_INIT 0x05 +#define ADRV9025_CPU_OBJECTID_ORXDCOFFSET_INIT 0x06 +#define ADRV9025_CPU_OBJECTID_LBRXDCOFFSET_INIT 0x07 +#define ADRV9025_CPU_OBJECTID_ADCFLASH_INIT 0x08 +#define ADRV9025_CPU_OBJECTID_PATHDELAY_INIT 0x09 +#define ADRV9025_CPU_OBJECTID_TXLOLINT_INIT 0x0A +#define ADRV9025_CPU_OBJECTID_TXLOLEXT_INIT 0x0B +#define ADRV9025_CPU_OBJECTID_TXQEC_INIT 0x0C +#define ADRV9025_CPU_OBJECTID_LBLODELAY_INIT 0x0D +#define ADRV9025_CPU_OBJECTID_LBRXTCAL_INIT 0x0E +#define ADRV9025_CPU_OBJECTID_RXLODELAY_INIT 0x0F +#define ADRV9025_CPU_OBJECTID_RXTCAL_INIT 0x10 +#define ADRV9025_CPU_OBJECTID_ORXLODELAY_INIT 0x11 +#define ADRV9025_CPU_OBJECTID_ORXTCAL_INIT 0x12 +#define ADRV9025_CPU_OBJECTID_TXDAC_INIT 0x13 +#define ADRV9025_CPU_OBJECTID_DPD_INIT 0x14 +#define ADRV9025_CPU_OBJECTID_CLGC_INIT 0x15 +#define ADRV9025_CPU_OBJECTID_VSWR_INIT 0x16 +#define ADRV9025_CPU_OBJECTID_HD2_INIT 0x17 +#define ADRV9025_CPU_OBJECTID_TXATTENDELAY_INIT 0x18 +#define ADRV9025_CPU_OBJECTID_TXATTENTABLECAL_INIT 0x19 +#define ADRV9025_CPU_OBJECTID_RXGAINDELAY_INIT 0x1A +#define ADRV9025_CPU_OBJECTID_RXGAINPHASECAL_INIT 0x1B +#define ADRV9025_CPU_OBJECTID_CFR_INIT 0x1D + +#define ADRV9025_CPU_OBJECTID_RXQEC_TRACKING 0x30 +#define ADRV9025_CPU_OBJECTID_ORXQEC_TRACKING 0x31 +#define ADRV9025_CPU_OBJECTID_TXLOL_TRACKING 0x32 +#define ADRV9025_CPU_OBJECTID_TXQEC_TRACKING 0x33 +#define ADRV9025_CPU_OBJECTID_DPD_TRACKING 0x34 +#define ADRV9025_CPU_OBJECTID_CLGC_TRACKING 0x35 +#define ADRV9025_CPU_OBJECTID_VSWR_TRACKING 0x36 +#define ADRV9025_CPU_OBJECTID_RXHD2_TRACKING 0x37 +#define ADRV9025_CPU_OBJECTID_DES_TRACKING 0x38 + +#define ADRV9025_CPU_OBJECTID_TEMP_SENSOR 0x40 +#define ADRV9025_CPU_OBJECTID_RSSI 0x41 +#define ADRV9025_CPU_OBJECTID_CAL_STATUS 0x42 +#define ADRV9025_CPU_OBJECTID_INITCAL_STATUS 0x43 +#define ADRV9025_CPU_OBJECTID_GO_GET_GP_INT_SOURCE 0x46 +#define ADRV9025_CPU_OBJECTID_TRACKING_CALS_STATE 0x47 +#define ADRV9025_CPU_OBJECTID_BANDSWITCH_STAT 0x4B + +#define ADRV9025_CPU_OBJECTID_GPIO_CTRL 0x60 +#define ADRV9025_CPU_OBJECTID_TX_ORX_MAPPING 0x4A +#define ADRV9025_CPU_OBJECTID_TXCAL_ENA_DIS 0x62 +#define ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY 0x63 +#define ADRV9025_CPU_OBJECTID_MCS_DONE 0x64 +#define ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE 0x65 +#define ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL 0x66 +#define ADRV9025_CPU_OBJECTID_TRACKING_CAL_PENDING 0x67 +#define ADRV9025_CPU_OBJECTID_TRACKING_CAL_UPDATE 0x68 +#define ADRV9025_CPU_OBJECTID_CPU_EXCEPTION 0x69 +#define ADRV9025_CPU_OBJECTID_PLL_LOOP_BW 0x6B +#define ADRV9025_CPU_OBJECTID_CONFIG 0x6F +#define ADRV9025_CPU_OBJECTID_MCS 0x70 +#define ADRV9025_CPU_OBJECTID_TX_NCO 0x71 +#define ADRV9025_CPU_OBJECTID_EXT_DPD_ENABLE_DISABLE 0x73 +#define ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_TRIG 0x74 +#define ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_DONE 0x75 +#define ADRV9025_CPU_OBJECTID_EXT_DPD_MODEL_SELECT 0x76 +#define ADRV9025_CPU_OBJECTID_SRL_CONFIG 0x77 +#define ADRV9025_CPU_OBJECTID_SRL_STATISTICS 0x78 +#define ADRV9025_CPU_OBJECTID_GS_RX_DDC 0x79 +#define ADRV9025_CPU_OBJECTID_CAPTURE_ORX 0x7E +#define ADRV9025_CPU_OBJECTID_GS_TEST_MODE 0x7F + +#define ADRV9025_CPU_OBJECTID_DEVICE_PROFILE 0x80 +#define ADRV9025_CPU_OBJECTID_RADIO_CONTROL 0x81 +#define ADRV9025_CPU_OBJECTID_INITIAL_CAL_SEQUENCE 0x82 +#define ADRV9025_CPU_OBJECTID_CAL_SCHEDULER 0x83 +#define ADRV9025_CPU_OBJECTID_HEALTH_MONITORING 0x84 +#define ADRV9025_CPU_OBJECTID_ECC_CONFIGURATION 0x85 +#define ADRV9025_CPU_OBJECTID_SYSTEM_INFO 0x86 +#define ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE 0x88 +#define ADRV9025_CPU_OBJECTID_EXT_DPD_MODEL 0x89 +#define ADRV9025_CPU_OBJECTID_EXT_DPD_SWAP_MODE_EN 0x8A +#define ADRV9025_CPU_OBJECTID_EXT_DPD_GAIN_MONITOR 0x8B +#define ADRV9025_CPU_OBJECTID_DUALBANDCFG 0x8D +#define ADRV9025_CPU_OBJECTID_EXT_DPD_MULTIMODEL 0x8E + +#define ADRV9025_CPU_OBJECTID_NCO_DRIVER 0xB0 +#define ADRV9025_CPU_OBJECTID_STREAM_DRIVER 0xB1 +#define ADRV9025_CPU_OBJECTID_PFIR_DRIVER 0xB2 +#define ADRV9025_CPU_OBJECTID_JESD_DRIVER 0xB3 +#define ADRV9025_CPU_OBJECTID_RXQEC_DRIVER 0xB4 +#define ADRV9025_CPU_OBJECTID_TXATTEN_DRIVER 0xB5 +#define ADRV9025_CPU_OBJECTID_TXQEC_DRIVER 0xB6 + +#define ADRV9025_CPU_OBJECTID_TM_SERDES_TASK_VERT_ISI 0x04 + +#define ADRV9025_CPU_OBJECTID_TM_CLKPLL_SWEEP 0xF0 +#define ADRV9025_CPU_OBJECTID_TM_TTXBFF_3DB_SWEEP 0xF1 +#define ADRV9025_CPU_OBJECTID_TM_TIA_3DB_SWEEP 0xF2 +#define ADRV9025_CPU_OBJECTID_TM_LPBK_CTRL 0xF3 +#define ADRV9025_CPU_OBJECTID_TM_SERDES 0xFA +#define ADRV9025_CPU_OBJECTID_TM_EXIT 0xFE +#define ADRV9025_CPU_OBJECTID_SYSTEM_CONFIG 0xFF + +/* CPU-C memory map */ +#define ADRV9025_CPU_C_ADDR_PROG_START 0x01018000 +#define ADRV9025_CPU_C_ADDR_PROG_END 0x0104FFFF +#define ADRV9025_CPU_C_ADDR_DATA_START 0x20028000 +#define ADRV9025_CPU_C_ADDR_DATA_END 0x2004FFFF +#define ADRV9025_CPU_C_ADDR_VERSION 0x01018240 +#define ADRV9025_CPU_C_ADDR_CFR_PULSE 0x010182A8 +#define ADRV9025_CPU_C_ADDR_DEV_PROFILE 0x01018274 +#define ADRV9025_CPU_C_ADDR_ADC_PROFILE 0x01018278 +#define ADRV9025_CPU_C_ADDR_DEBUG_PTR 0x0101827C +#define ADRV9025_CPU_C_ADDR_BUILD_CHKSUM 0x01047FFC +#define ADRV9025_CPU_C_ADDR_CALC_CHKSUM_PTR 0x01018270 +#define ADRV9025_CPU_C_ADDR_MAILBOX_SET 0x20028000 +#define ADRV9025_CPU_C_ADDR_MAILBOX_GET 0x20028100 +#define ADRV9025_CPU_C_ADDR_MAILBOX_RUN_INIT 0x20028200 +#define ADRV9025_CPU_C_ADDR_MAILBOX_FHM 0x20028208 + +/* CPU-D memory map */ +#define ADRV9025_CPU_D_INVALID_ADDRESS 0xFFFFFFFF +#define ADRV9025_CPU_D_ADDR_PROG_START 0x01000000 +#define ADRV9025_CPU_D_ADDR_PROG_END 0x01017FFF +#define ADRV9025_CPU_D_ADDR_DATA_START 0x20000000 +#define ADRV9025_CPU_D_ADDR_DATA_END 0x20027FFF +#define ADRV9025_CPU_D_ADDR_VERSION 0x01000240 +#define ADRV9025_CPU_D_ADDR_CFR_PULSE ADRV9025_CPU_D_INVALID_ADDRESS /* ARM-D doesn't have this address */ +#define ADRV9025_CPU_D_ADDR_DEBUG_PTR ADRV9025_CPU_D_INVALID_ADDRESS /* ARM-D doesn't have this address */ +#define ADRV9025_CPU_D_ADDR_BUILD_CHKSUM ADRV9025_CPU_D_INVALID_ADDRESS /* ARM-D doesn't have this address */ +#define ADRV9025_CPU_D_ADDR_CALC_CHKSUM_PTR ADRV9025_CPU_D_INVALID_ADDRESS /* ARM-D doesn't have this address */ +#define ADRV9025_CPU_D_ADDR_MAILBOX_SET ADRV9025_CPU_D_INVALID_ADDRESS /* ARM-D doesn't have this address */ +#define ADRV9025_CPU_D_ADDR_MAILBOX_GET ADRV9025_CPU_D_INVALID_ADDRESS /* ARM-D doesn't have this address */ +#define ADRV9025_CPU_D_ADDR_MAILBOX_RUN_INIT ADRV9025_CPU_D_INVALID_ADDRESS /* ARM-D doesn't have this address */ +#define ADRV9025_CPU_D_ADDR_MAILBOX_FHM ADRV9025_CPU_D_INVALID_ADDRESS /* ARM-D doesn't have this address */ + +/* ARM average temperature measurement */ +#define ADRV9025_CPU_ADDR_AVG_TEMP_ADDR 0x010002B0 + +/*StringVersion address in ARM*/ +#define ADRV9025_CPU_ADDR_STREAM_VERSION 0x2004E808 +/* Cpu MailBox */ +#define ADRV9025_CPU_ADDR_MAILBOX_STATUS_OFFSET 0x00 +#define ADRV9025_CPU_MAILBOX_STATUS_OK 0x00 +#define ADRV9025_CPU_ADDR_MAILBOX_ERROR_OFFSET 0x01 +#define ADRV9025_CPU_MAILBOX_ERROR_DEVICE_PROFILE 0x00 +#define ADRV9025_CPU_MAILBOX_ERROR_ADC_PROFILE 0x01 +#define ADRV9025_CPU_MAILBOX_ERROR_VCOFREGKHZ 0x02 +#define ADRV9025_CPU_MAILBOX_ERROR_HSDIGHZ_API 0x03 +#define ADRV9025_CPU_MAILBOX_ERROR_DEVICECLOCKHZ 0x04 +#define ADRV9025_CPU_MAILBOX_ERROR_RXOUTPUTRATEHZ 0x05 +#define ADRV9025_CPU_MAILBOX_ERROR_TXINPUTRATEHZ 0x06 +#define ADRV9025_CPU_MAILBOX_ERROR_ORXOUTPUTRATEHZ 0x07 + +#define ADRV9025_CPU_ADC_PROFILE_SIZE 56 +/* number of uint16_t words per ADC profile */ + +#define ADRV9025_CPU_ADCP_ROFILE_NUM_CAP_COND_CURR_VALUES 16 +#define ADRV9025_CPU_ADC_PROFILE_NUM_BIAS_VBG_VALUES 22 +#define ADRV9025_CPU_ADC_PROFILE_NUM_DACG_VALUES 2 +#define ADRV9025_CPU_ADC_PROFILE_NUM_ES1_VALUES 1 +#define ADRV9025_CPU_ADC_PROFILE_NUM_ALTG_VALUES 1 + +/* Firmware Status */ +#define ADRV9025_CPU_FW_STATUS_POWERUP 0 +#define ADRV9025_CPU_FW_STATUS_READY 1 +#define ADRV9025_CPU_FW_STATUS_FW_CHECKSUM_ERROR 2 +#define ADRV9025_CPU_FW_STATUS_DATA_MEMORY_ERROR 3 +#define ADRV9025_CPU_FW_STATUS_STREAM_CHECKSUM_ERROR 4 +#define ADRV9025_CPU_FW_STATUS_PROFILE_ERROR 5 +#define ADRV9025_CPU_FW_STATUS_CLKPLL_PROGRAMING_ERROR 6 +#define ADRV9025_CPU_FW_STATUS_JESD_SETUP_CONFIG_ERROR 7 +#define ADRV9025_CPU_FW_STATUS_POWER_UP_INIT_ERROR 8 +#define ADRV9025_CPU_FW_STATUS_CPU_DEBUG_READY 9 +#define ADRV9025_CPU_FW_STATUS_CLKLOGEN_ERROR 10 +#define ADRV9025_CPU_FW_STATUS_RXQEC_HARDWARE_ERROR 11 +#define ADRV9025_CPU_FW_STATUS_HW_TIMER_ERROR 12 +#define ADRV9025_CPU_FW_STATUS_ADC_RCAL_ERROR 13 +#define ADRV9025_CPU_FW_STATUS_STREAM_RUNTIME_ERROR 14 +#define ADRV9025_CPU_FW_STATUS_BOOT_CLKGEN_RCAL_ERROR 15 +#define ADRV9025_CPU_FW_STATUS_BOOT_LDO_CONFIG_ERROR 16 +#define ADRV9025_CPU_FW_STATUS_INVCHN_CONFIG_ERROR 17 +#define ADRV9025_CPU_D_FW_STATUS_CHECKSUM_ERROR 19 +#define ADRV9025_CPU_D_FW_STATUS_BOOT_ERROR 20 + +#define ADRV9025_CPU_OPCODE_MASK 0xFFFF0000 +#define ADRV9025_CPU_OPCODE_SHIFT 16 +#define ADRV9025_CPU_OBJ_ID_MASK 0x0000FF00 +#define ADRV9025_CPU_OBJ_ID_SHIFT 8 +#define ADRV9025_CPU_ERROR_MASK 0x000000FF +#define ADRV9025_CPU_ERROR_SHIFT 1 + +#define ADRV9025_CPU_CMD_ERRCODE(armOpCode, armObjId, armErrorFlag) \ + ((armOpCode << ADRV9025_CPU_OPCODE_SHIFT) | \ + (armObjId << ADRV9025_CPU_OBJ_ID_SHIFT) | \ + armErrorFlag) + +#define ADRV9025_CPU_OPCODE_VALID(a) \ + (((a) != 0) && (((a) % 2) || ((a) > 30))) + +#define ADRV9025_MAX_CPUS 2u +#define ADRV9025_MAX_CPU_FW_PATH 128u +#define ADRV9025_CPU_FW_PATH_SEP ';' + +#ifdef __cplusplus +} +#endif + +#endif /* _ADRV_9025_CPU__MACROS_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_crc32.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_crc32.h new file mode 100644 index 0000000..9980f02 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_crc32.h @@ -0,0 +1,45 @@ +/** + * \file adrv9025_crc32.h + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADRV9025_CRC32_H_ +#define _ADRV9025_CRC32_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Run Cyclic Redundancy Check on the specified block of memory in chunk. +* +* \details CRC32 algorithm, operating on 8-bit words +* +* Parameters: +* \param buf - array of bytes on which CRC is run +* \param bufLen - length of the input array in bytes +* \param seedCrc - Seed for the next block of memory, use 0 for initial seedCrc. +* \param finalCrc - 0: return the CRC use for seedSrc. 1: return the final CRC32. +* +* \retval 32-bit checksum +* +* +******************************************************************************* +*/ +uint32_t adrv9025_Crc32ForChunk(const uint8_t buf[], + uint32_t bufLen, + uint32_t seedCrc, + uint8_t finalCrc); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_data_interface.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_data_interface.h new file mode 100644 index 0000000..8d476bc --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_data_interface.h @@ -0,0 +1,315 @@ +/** + * \file adrv9025_data_interface.h + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +/** +* \file adrv9025_data_interface.h +* \brief Contains private ADRV9025 functions to aid the data interface public +* API functions. +* +* ADRV9025 API Version: 6.4.0.14 +* +* Copyright 2015-2019 Analog Devices Inc. +* Released under the AD9378-AD9379 API license, for more information see the "LICENSE.pdf" file. +*/ + +#ifndef _ADRV9025_DATA_INTERFACE_H_ +#define _ADRV9025_DATA_INTERFACE_H_ + +#include "adi_adrv9025_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Private function called by API's to get the serializer lane offset at +* the die due to laminate lane swaps in the device package. +* +* This function allows passing in a serializer lane number (0-7) at the +* package ball, and returns the lane number at the die. It corrects the +* lane swaps in the package laminate. +* +* \pre This function can be called anytime. +* +* \param laneAtPackageBall Serializer package ball lane number (Valid: 0-7) +* +* \retval Returns the lane number at the die pad after the lamainate swaps have been applied. +*/ +uint8_t adrv9025_SerializerLamLaneOffsetGet(uint8_t laneAtPackageBall); + +/** +* \brief Private function called by API's to translate pad to ball number +* +* \pre This function can be called anytime. +* +* \param pad - pad number (Valid: 0-7) +* +* \retval Returns the ball number corresponding to the pad number +*/ +uint8_t adrv9025_FramerPadToBallTranslate(uint8_t pad); + +/** +* \brief Private function called by API's to translate pad mask to ball mask +* +* \pre This function can be called anytime. +* +* \param padMask - pad mask +* +* \retval Returns the ball mask corresponding to the pad mask +*/ +uint8_t adrv9025_FramerPadToBallMaskTranslate(uint8_t padMask); + +/** +* \brief Private function called by API's to get the deserializer lane offset +* at the die due to laminate lane swaps in the device package. +* +* This function receives the deserializer lane number at the package ball and +* returns the lane number(offset) at the die after the laminate lane swaps +* are applied. +* +* +* \pre This function can be called anytime. +* +* \param laneAtPackageBall Deserializer package ball lane number (Valid: 0-7) +* +* \retval Returns the lane number at the die pad after the laminate swaps have been applied. +*/ +uint8_t adrv9025_DeserializerLamLaneOffsetGet(uint8_t laneAtPackageBall); + +/** +* \brief Private function called by API's to get the deserializer lane +* at the ball due to laminate lane swaps in the device package. +* +* This function receives the deserializer lane number(offset) at the die and +* returns the lane number at the package ball after the laminate lane swaps +* are applied. +* +* +* \pre This function can be called anytime. +* +* \param laneAtDie Deserializer package die pad lane number (Valid: 0-7) +* +* \retval Returns the lane number at the ball lane after the laminate swaps have been applied. +*/ +uint8_t adrv9025_DeframerLamLaneOffsetGet(uint8_t laneAtDie); + +/** +* \brief Private function called by API's to translate deframer lane enable bits from lane +* numbers at die to ball lane numbers +* +* This function receives bitmask of deframer lane enable bits with lane numbers at die and +* returns converted bitmask at ball lane numbers +* +* +* \pre This function can be called anytime. +* +* \param inBitMask Deframer lane enable bitmask with die lane numbers +* +* \retval Returns the deframer lane enable bitmask with ball lane numbers +*/ +uint8_t adrv9025_DeframerLaneTranslateBitmask(uint8_t inBitMask); + +/** +* \brief Private function to read from the specified CBUS register +* +* +* \pre This function can be called anytime. +* +* \param device - device structure pointer +* \param addr - CBUS address to read data from +* \param rxLaneSel - lane select mask +* \param data - pointer to a uint8_t variable used to hold data read back from a particular address i.e. addr param +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_CbusRegisterRead(adi_adrv9025_Device_t* device, + uint8_t addr, + uint8_t rxLaneSel, + uint8_t* data); + +/** +* \brief Private function to write from the specified CBUS register +* +* +* \pre This function can be called anytime. +* +*\param device - device structure pointer +* \param addr CBUS address +* \param rxLaneSel bitmask to select which rx lanes to write +* \param data - value to write to a given address i.e. the addr param +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_CbusRegisterWrite(adi_adrv9025_Device_t* device, + uint8_t addr, + uint8_t rxLaneSel, + uint8_t data); + +/** +* \brief Private function to read from the specified CBUS register using SPI reads +* +* \pre This function can be called anytime. Need to calculate lane mask (rxLaneSel) prior to calling API +* +* \param device - device structure pointer +* \param addr - CBUS address +* \param rxLaneSel - lane select mask +* \param data - pointer to a uint8_t variable used to hold data read back from a particular address i.e. addr param +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_CbusRegisterSpiRead(adi_adrv9025_Device_t *device, + uint8_t addr, + uint8_t rxLaneSel, + uint8_t *data); + +/** +* \brief Private function to write from the specified CBUS register using SPI Writes +* +* +* \pre This function can be called anytime. Need to calculate lane mask (rxLaneSel) prior to calling API +* +* \param device CBUS address +* \param addr CBUS address +* \param rxLaneSel lane select mask +* \param data pointer to uint8_t to hold data read back in addr +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_CbusRegisterSpiWrite(adi_adrv9025_Device_t *device, + uint8_t addr, + uint8_t rxLaneSel, + uint8_t data); + +/** +* \brief Private function to write a SPO value using SPI for the selected lanes. Sets & clears the latch bit. +* +* +* \pre This function can be called anytime. +* +* \param addr CBUS address +* \param rxLaneSel bitmask to select which rx lanes to write +* \param data value to write to addr +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_SpoSpiSet(adi_adrv9025_Device_t* device, + uint8_t rxLaneSel, + uint8_t data); + +/** +* \brief Private function to write a SPO value for the selected lanes. Sets & clears the latch bit. +* +* +* \pre This function can be called anytime. +* +* \param addr CBUS address +* \param rxLaneSel bitmask to select which rx lanes to write +* \param data value to write to addr +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_SpoSet(adi_adrv9025_Device_t* device, + uint8_t rxLaneSel, + uint8_t data); + +/** +* \brief Used to enable selected deserializer lanes using lane bitmask. +* +* \pre This function may be called anytime. +* +* \dep_begin +* \dep{device->devHalInfo} +* \dep_end +* +* \param device is a pointer to the device settings structure +* \param laneMask is an eight bit mask allowing selection of lanes. Bit 0 maps to Lane 0(A), Bit 7 maps to Lane 7(H). +* \param enable 0 = Disable the selected lanes, 1 = enable the selected lanes +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_DeserializerLaneEnable(adi_adrv9025_Device_t* device, + uint8_t laneMask, + uint8_t enable); + +/** +* \brief This function generates eyeDiagram results for a programmed JESD Quarter Rate Configuration +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param lane - number describing which lane to generate a diagram for (0-3) +* \param results array of adi_adrv9025_EyeDiagramResultsQR_t results structures which contains output from arm command +* \param numResults number of members in adi_adrv9025_EyeDiagramResultsQR_t* results +* \param direction - which part of the eye direction to scan (1 = positive eye, 0 = negative eye) +* +* \retval ADI_ADRV9025_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_GenerateEyeDiagram_Direction(adi_adrv9025_Device_t *device, + uint8_t lane, + adi_adrv9025_EyeDiagramResultsQR_t **results, + uint8_t numResults, + uint8_t direction); + +/** +* \brief This function generates vertical isi results for a given SPO (static phase offset) +* this function utilizes ARM serdes test mode in order to generate the results +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* + +* \param device Pointer to the ADRV9025 data structure +* \param lane - number describing which lane to generate a diagram for (0-3) +* \param data - array of results structures which contains output from arm serdes test mode i.e. vertisi_sum_s0f1 vertisi_sum_s1f1 vertisi_diff_s0f1 and vertisi_diff_s1f1 +* \param config - configuration structure to tell arm how to perform the vertical isi test mode task +* +* \retval ADI_ADRV9025_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_VerticalIsiGet(adi_adrv9025_Device_t *device, + uint8_t lane, + uint8_t *data, + adi_adrv9025_VerticalISIConfig_t config); +#ifdef __cplusplus +} +#endif + +#endif /* _ADRV9025_DATA_INTERFACE_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_dynamic_slicer.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_dynamic_slicer.h new file mode 100644 index 0000000..f60fa98 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_dynamic_slicer.h @@ -0,0 +1,70 @@ +/** +* \file adrv9025_dynamic_slicer.h +* \brief Contains ADRV9025 private function prototypes for +* adrv9025_dynamic_slicer.c that helps adi_adrv9025_dynamic_slicer.c +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADRV9025_DYNAMIC_SLICER_H_ +#define _ADRV9025_DYNAMIC_SLICER_H_ + +#include "adi_adrv9025_dynamic_slicer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Sets up the dynamic slicer config +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param dynamicSlicerCfg Pointer to the dynamic slicer configuration structure +* \param enable Parameter to enable(1)/disable(0) dynamic slicer configuration +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxDynamicSlicerEnableSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxDynamicSlicerConfig_t* dynamicSlicerCfg, + uint8_t enable); + +/** +* \brief Performs range check on Rx dynamic slicer settings +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxDynamicSlicerConfig Array of Rx dynamic slicer config settings +* \param arraySize No. of elements in rxDynamicSlicerConfig array +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxDynamicSlicerConfigSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxDynamicSlicerConfig_t rxDynamicSlicerConfig[], + uint8_t arraySize); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_gpio.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_gpio.h new file mode 100644 index 0000000..830ff03 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_gpio.h @@ -0,0 +1,233 @@ +/** +* \file adrv9025_gpio.h +* \brief Contains ADRV9025 transmit related function prototypes for +* adrv9025_gpio.c +* +* ADRV9025 API Version: 6.4.0.14 +* +* Copyright 2015-2019 Analog Devices Inc. +* Released under the AD9378-AD9379 API license, for more information see the "LICENSE.pdf" file. +*/ + +#ifndef _ADRV9025_GPIO_H_ +#define _ADRV9025_GPIO_H_ + +#include "adi_adrv9025_types.h" +#include "adi_adrv9025_gpio_types.h" +#include "adi_common_error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief [TOK A0] Private function called by API's adi_adrv9025_GpInt1Handler and adi_adrv9025_GpInt0Handler. This +* function performs all possible recover actions for any GP_INT source as well as returning the required +* BBIC recovery action. This handles GP Interrupts specific to A0 silicon +* +* \pre This function can only be called by the adi_adrv9025_GpInt1Handler or adi_adrv9025_GpInt0Handler. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param gpIntStatus Pointer containing all information for the gp interrupt. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for ARM/WATCHDOG errors +* \retval ADI_COMMON_ACT_ERR_RERUN_INIT_CALS Recovery actions for INIT CALIBRATION errors +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_GpIntHandler(adi_adrv9025_Device_t* device, + adi_adrv9025_gpIntStatus_t* gpIntStatus); + +/** +* \brief [TOK B0] Private function called by API's adi_adrv9025_GpInt1Handler and adi_adrv9025_GpInt0Handler. This +* function performs all possible recover actions for any GP_INT source as well as returning the required +* BBIC recovery action. This handles GP Interrupts specific to B0 silicon +* +* \pre This function can only be called by the adi_adrv9025_GpInt1Handler or adi_adrv9025_GpInt0Handler. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param gpIntStatus Pointer containing all information for the gp interrupt. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for ARM/WATCHDOG errors +* \retval ADI_COMMON_ACT_ERR_RERUN_INIT_CALS Recovery actions for INIT CALIBRATION errors +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_b0_GpIntHandler(adi_adrv9025_Device_t* device, + adi_adrv9025_gpIntStatus_t* gpIntStatus); + +/** +* \brief This function performs range check on the parameters for adi_adrv9025_AuxDacCfg_t. +* +* This function verifies that the requested configuration for AuxDAC is valid +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param auxDacCfg Pointer to the configuration struct to be tested +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_AuxDacCfgRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxDacCfg_t* auxDacCfg); + +/** +* \brief This function sets the configuration for selected AuxDAC. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param auxDacSel AuxDAC selection to set the configuration +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_AuxDacCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxDacs_e auxDacSel); + +/** +* \brief This function sets the 12 bit DAC word for selected AuxDAC. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param auxDacSel AuxDAC selection to set the configuration +* \param dacWord 12 bit DAC word 0-4095 maps to 0-1.8V +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_AuxDacValueSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxDacs_e auxDacSel, + uint16_t dacWord); + +/** +* \brief Private function called by API's adi_adrv9025_AuxAdcCfgSet function. This +* function validates the supplied configuration in terms of acceptable ranges +* and values. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param auxAdcConfig Pointer to the auxiliary ADC configuration structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for ARM/WATCHDOG errors +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_AuxAdcCfgRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcCfg_t* auxAdcConfig); + +/** +* \brief Private function called by API's adi_adrv9025_AuxAdcCfgSet function. This +* function writes the supplied configuration to the selected ADC's +* configuration registers +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param auxAdcConfig Pointer to the auxiliary ADC configuration structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for ARM/WATCHDOG errors +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_AuxAdcCfgWrite(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcCfg_t* auxAdcConfig); + +/** +* \brief Private function called by API's adi_adrv9025_AuxAdcCfgGet function. This +* function writes the configuration to the selected ADC configuration registers +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param auxAdcSelect The auxiliary ADC to obtain a sample from +* \param auxAdcConfig Pointer to the auxiliary ADC configuration structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for ARM/WATCHDOG errors +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_AuxAdcCfgRead(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcSelect_e auxAdcSelect, + adi_adrv9025_AuxAdcCfg_t* auxAdcConfig); + +/** +* \brief Private function called by API's adi_adrv9025_AuxAdcMeasurementStart function. +* This function starts AuxADC measurement by toggling the reset bit for selected AuxADC +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param auxAdcSelect The auxiliary ADC to start measurement +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for ARM/WATCHDOG errors +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_AuxAdcMeasurementStart(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcSelect_e auxAdcSelect); + +/** +* \brief Private function called by API's adi_adrv9025_AuxAdcValueGet function. +* This function reads the selected ADC sample value. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param auxAdcSelect The auxiliary ADC to obtain a sample from +* \param auxAdcValue A pointer to the supplied value structure to populate with +* the obtained ADC sample data +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for ARM/WATCHDOG errors +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_AuxAdcValueGet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcSelect_e auxAdcSelect, + adi_adrv9025_AuxAdcValue_t* auxAdcValue); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADRV9025_GPIO_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_init.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_init.h new file mode 100644 index 0000000..d9368c9 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_init.h @@ -0,0 +1,256 @@ +/** +* \file adrv9025_init.h +* \brief Contains ADRV9025 init related private function prototypes for +* adrv9025_init.c that helps adi_adrv9025_init.c +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +# ifndef _ADRV9025_INIT_H_ +#define _ADRV9025_INIT_H_ + +#include "adi_adrv9025.h" + + + +#ifdef __cplusplus +extern "C" { +#endif + + +#define ADRV9025_BUGINFO(x) +#define ADRV9025_BUGINFO_NUM(x,n) + +#define ADRV9025_DMAINFO(text, addr, count) + +#define ADRV9025_SPIDMAINFO(s,a,b,c) + + +#define ADRV9025_SPIWRITEBYTESDMA(text, addr, addrArray, dataArray, count) \ +{\ + recoveryAction = adi_adrv9025_SpiBytesWrite(device, (addrArray), (dataArray), (count)); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recoveryAction, NULL, "Error while writing bytes to DMA over Spi"); \ + ADI_ERROR_RETURN(device->common.error.newAction); \ + ADRV9025_DMAINFO((text), (addr), (count)); \ +} + +#define ADRV9025_SPIREADBYTESDMA(text, addr, addrArray, dataArray, count) \ +{\ + recoveryAction = adi_adrv9025_SpiBytesRead(device, (addrArray), (dataArray), (count)); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recoveryAction, NULL, "Error while reading bytes through DMA over Spi"); \ + ADI_ERROR_RETURN(device->common.error.newAction); \ + ADRV9025_DMAINFO((text), (addr), (count)); \ +} + +#define ADRV9025_SPIWRITEWORDDMA(text, addr, data) \ +{\ + recoveryAction = adi_adrv9025_SpiDmaWordWrite(device, (data), (addr)); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recoveryAction, NULL, "Error while writing word to DMA over Spi"); \ + ADI_ERROR_RETURN(device->common.error.newAction); \ + ADRV9025_SPIDMAINFO("MESSAGE:WORD WRITE: %30s: addr=0x%04x, data=0x%02x \n", (text), (addr), (data)); \ +} + +#define ADRV9025_SPIREADWORDDMA(text, addr, data) \ +{\ + recoveryAction = adi_adrv9025_SpiDmaWordRead(device, (data), (addr)); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recoveryAction, NULL, "Error while reading word from DMA over Spi"); \ + ADI_ERROR_RETURN(device->common.error.newAction); \ + ADRV9025_SPIDMAINFO("MESSAGE:WORD READ: %30s: addr=0x%04x, data=0x%02x \n", (text), (addr), (data)); \ +} + +#define ADRV9025_SPIWRITEWORDDMASTREAMWITHCUSTOMHALFUNCTION(text, addr, data, byteCount) \ +{\ + recoveryAction = adi_adrv9025_SpiWriteStreamWithCustomHalFunction(device, data, byteCount, (uint16_t)addr); \ + ADRV9025_SPI_STREAM_DISABLE_ON_ERROR(device, recoveryAction); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recoveryAction, NULL, "Error while writing bytes through DMA over Spi"); \ + ADI_ERROR_RETURN(device->common.error.newAction); \ + ADRV9025_SPIDMAINFO("MESSAGE:WRITE STREAM: %30s: addr=0x%04x, count=0x%02x \n", (text), (addr), (byteCount)); \ +} + +#define ADRV9025_SPIREADWORDDMASTREAMWITHCUSTOMHALFUNCTION(text, addr, readData, byteCount) \ +{\ + recoveryAction = adi_adrv9025_SpiReadStreamWithCustomHalFunction(device, readData, byteCount, (uint16_t)addr); \ + ADRV9025_SPI_STREAM_DISABLE_ON_ERROR(device, recoveryAction); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recoveryAction, NULL, "Error while reading bytes through DMA over Spi"); \ + ADI_ERROR_RETURN(device->common.error.newAction); \ + ADRV9025_SPIDMAINFO("MESSAGE:READ STREAM: %30s: addr=0x%04x, count=0x%02x \n", (text), (addr), (byteCount)); \ +} + +#define ADRV9025_SPIWRITEWORDDMASTREAM(text, addr, data, byteCount) \ +{\ + recoveryAction = adi_adrv9025_SpiDmaWordWriteStream(device, data, byteCount, (uint16_t)addr); \ + ADRV9025_SPI_STREAM_DISABLE_ON_ERROR(device, recoveryAction); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recoveryAction, NULL, "Error while writing bytes through DMA over Spi"); \ + ADI_ERROR_RETURN(device->common.error.newAction); \ + ADRV9025_SPIDMAINFO("MESSAGE:WRITE STREAM: %30s: addr=0x%04x, count=0x%02x \n", (text), (addr), (byteCount)); \ +} + +#define ADRV9025_SPIREADWORDDMASTREAM(text, addr, returnData, byteCount) \ +{\ + recoveryAction = adi_adrv9025_SpiDmaWordReadStream(device, returnData, byteCount, (uint16_t)addr); \ + ADRV9025_SPI_STREAM_DISABLE_ON_ERROR(device, recoveryAction); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recoveryAction, NULL, "Error while reading bytes through DMA over Spi"); \ + ADI_ERROR_RETURN(device->common.error.newAction); \ + ADRV9025_SPIDMAINFO("MESSAGE:READ STREAM: %30s: addr=0x%04x, count=0x%02x \n", (text), (addr), (byteCount)); \ +} + + +#define ADRV9025_SPIWRITEBYTEDMA(text, addr, data) \ +{\ + recoveryAction = adi_adrv9025_SpiByteWrite(device, (addr), (data)); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recoveryAction, NULL, "Error while writing byte to DMA over Spi"); \ + ADI_ERROR_RETURN(device->common.error.newAction); \ + ADRV9025_SPIDMAINFO("MESSAGE: WRITE: %30s: addr=0x%04x, data=0x%02x \n", (text), (addr), (data)); \ +} + +#define ADRV9025_SPIREADBYTEDMA(text, addr, data) \ +{\ + recoveryAction = adi_adrv9025_SpiByteRead(device, (addr), (data)); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recoveryAction, NULL, "Error while Reading byte from DMA over Spi"); \ + ADI_ERROR_RETURN(device->common.error.newAction); \ + ADRV9025_SPIDMAINFO("MESSAGE: READ: %30s: addr=0x%04x, data=0x%02x \n", (text), (addr), (*(uint8_t*)(data))); \ +} + +#define ADRV9025_SPIINFO(s,a,b,c) +#define ADRV9025_SPI_FIELD_INFO(s,a,b,c,d) + +#define ADRV9025_SPIWRITEBYTE(text, addr, data) \ +{\ + int32_t recAct = 0; \ + recAct = adi_adrv9025_SpiByteWrite(device, (addr), (data)); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recAct, NULL, "Error while writing byte to Spi"); \ + ADI_ERROR_RETURN(device->common.error.newAction); \ + ADRV9025_SPIINFO("MESSAGE: WRITE: %30s: addr=0x%04x, data=0x%02x \n", (text), (addr), (data)); \ +} + +#define ADRV9025_SPIREADBYTE(text, addr, data) \ +{\ + int32_t recAct = 0; \ + recAct = adi_adrv9025_SpiByteRead(device, (addr), (data)); \ + ADI_ERROR_RETURN(device->common.error.newAction); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recAct, NULL, "Error while reading byte from Spi"); \ + ADRV9025_SPIINFO("MESSAGE: READ: %30s: addr=0x%04x, data=0x%02x \n", (text), (addr), (*(uint8_t*)(data))); \ +} + +#define ADRV9025_SPIFIELDWRITE(device, addr, fieldVal, mask, startBit, text) \ +{ \ + int32_t recAct = 0; \ + recAct = adi_adrv9025_SpiFieldWrite(device, addr, fieldVal, mask, startBit); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recAct, NULL, "Error while Spi field write"); \ + ADI_ERROR_RETURN(device->common.error.newAction); \ + ADRV9025_SPI_FIELD_INFO("MESSAGE: WRITE FIELD: %30s: addr=0x%04x, data=0x%02x \n", (text), (addr), (fieldVal), (startBit)); \ +} + +#define ADRV9025_SPIFIELDREAD(device, addr, fieldVal, mask, startBit, text) \ +{ \ + int32_t recAct = 0; \ + recAct = adi_adrv9025_SpiFieldRead(device, addr, (fieldVal), mask, startBit); \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recAct, NULL, "Error while Spi field read"); \ + ADI_ERROR_RETURN(device->common.error.newAction); \ + ADRV9025_SPI_FIELD_INFO("MESSAGE: READ: %30s: addr=0x%04x, data=0x%02x \n", (text), (addr), (fieldVal), (startBit)); \ +} + +/** +* \brief Set various clock in the B0 silicon version device +* Configure the pad DEV_CLK divider so that output of pad divider is less than 500MHz. +* Configure ARM_clk_divide_ratio and reg_clk_divide_ratio (register bus clock). +* Maximum rate for ARM clock and REGBUS clock is 500MHz. +* Use DEVCLK to clock the HSDIGCLK input bypassing the PLL (write clock_config_6[7] to 1) +* The clock_config_6 register needs to be written to configure the clock divide ratios indicated +* Write SPI bit digital_clock_power_up to enable digital clocks (core.clock_control_6[4]) +* +* \pre This function is private and is not called directly by the user. +* +* \dep_begin +* \dep{device->devStateInfo} +* \dep{init-> (most members)} +* \dep_end +* +* \param device Structure pointer to ADRV9025 device data structure +* \param init Pointer to ADRV9025 initialization settings structures +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_ClocksSet(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init); + +/** +* \brief Verifies the init structure profiles are valid combinations +* +* This function checks that the Rx/Tx/ORx profiles have valid clock rates in +* order to operate together. Rx/Tx and ORx share a common high speed digital +* clock. If an invalid combination of profiles is detected, an error will be +* returned. If a profile in the init structure is unused, the user should zero +* out all members of that particular profile structure. If a Rx/Tx/ORx profile +* has an IQ rate = 0, it is assumed that the profile is disabled. +* +* \pre This function is private and is not called directly by the user. +* +* This function uses Adrv9025_TxProfileVerify(), Adrv9025_RxProfileVerify(), and +* Adrv9025_OrxProfileVerify() as helper functions. +* +* \dep_begin +* \dep{device->devStateInfo} +* \dep{init-> (most members)} +* \dep_end +* +* \param device Structure pointer to ADRV9025 device data structure +* \param init Pointer to ADRV9025 initialization settings structures +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_ProfilesVerify(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init); + +/** +* \brief Set various LDO in the device +* +* \pre This function is private and is not called directly by the user. +* +* \dep_begin +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to ADRV9025 device data structure +* \param ldoSelect Value indicating how to configure the LDO selection +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_LdoEnable(adi_adrv9025_Device_t* device, + uint8_t ldoSelect); + +/** +* \brief Sets up the thresholds on Rx channel which triggers overload bits +* if the input level exceeds threshold. +* +* \pre This function is private and is not called directly by the user. +* This function can only be called once the clocks are setup via +* adrv9025_ClocksSet() function. +* +* \dep_begin +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to ADRV9025 device data structure +* \param rxChannel Channel for which overload protection config is desired +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxOverloadProtectionSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_radioctrl.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_radioctrl.h new file mode 100644 index 0000000..82e0316 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_radioctrl.h @@ -0,0 +1,623 @@ +/** +* \file adrv9025_radioctrl.h +* \brief Contains ADRV9025 radio control related private function prototypes for +* adrv9025_radioctrl.c that helps adi_adrv9025_radioctrl.c +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADRV9025_RADIOCTRL_H_ +#define _ADRV9025_RADIOCTRL_H_ + +#include "../devices/adrv9025/public/include/adi_adrv9025_types.h" +#include "../devices/adrv9025/public/include/adi_adrv9025_radioctrl_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief This private sets the Tx channels to be enabled or disabled in the +* transceiver if the signal chain control is configured to be in SPI mode +* +* For use cases where pin mode is not required, this function can be used to +* enable/disable the Tx signal paths. This +* function should be called after initialization and loading the stream +* processor. +* +* \pre This function should be called after initialization and loading the stream +* processor. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param txChannelMask Desired Tx signal chains (channel) to power up +* +* \retval ADI_ADRV9025_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxEnableSet(adi_adrv9025_Device_t* device, + uint32_t txChannelMask); + +/** +* \brief This private sets the Rx channels to be enabled or disabled in the +* transceiver if the signal chain control is configured to be in SPI mode +* +* For use cases where pin mode is not required, this function can be used to +* enable/disable the Rx signal paths. This +* function should be called after initialization and loading the stream +* processor. +* +* \pre This function should be called after initialization and loading the stream +* processor. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param rxChannelMask Desired Rx signal chains (channel) to power up +* +* \retval ADI_ADRV9025_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxEnableSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask); + +/** +* \brief This private sets the ORx channels to be enabled or disabled in the +* transceiver if the signal chain control is configured to be in SPI mode +* +* For use cases where pin mode is not required, this function can be used to +* enable/disable the ORx signal paths. This +* function should be called after initialization and loading the stream +* processor. +* +* \pre This function should be called after initialization and loading the stream +* processor. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param rxChannelMask Desired ORx signal chains (channel) to power up +* +* \retval ADI_ADRV9025_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_OrxEnableSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask); + +/** +* \brief This API reads back the Tx channels that are powered up in the +* transceiver +* +* For use cases where pin mode is not required, this function can be used to +* read the current state of the Tx channel enable (power up) signals. +* This function should be called after initialization and loading the stream +* processor. +* +* \pre This function can be called after initialization. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param txChannelMask Current Tx signal chains enabled returned to this pointer address +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxEnableGet(adi_adrv9025_Device_t* device, + uint32_t* txChannelMask); + +/** +* \brief This API reads back the Rx channels that are powered up in the +* transceiver +* +* For use cases where pin mode is not required, this function can be used to +* read the current state of the Rx channel enable (power up) signals. +* This function should be called after initialization and loading the stream +* processor. +* +* \pre This function can be called after initialization. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param rxChannelMask Current Rx/ORx signal chains enabled returned to this pointer address +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxEnableGet(adi_adrv9025_Device_t* device, + uint32_t* rxChannelMask); + +/** +* \brief This API reads back the ORx channels that are powered up in the +* transceiver +* +* For use cases where pin mode is not required, this function can be used to +* read the current state of the ORx channel enable (power up) signals. +* This function should be called after initialization and loading the stream +* processor. +* +* \pre This function can be called after initialization. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param rxChannelMask Current Rx/ORx signal chains enabled returned to this pointer address +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_OrxEnableGet(adi_adrv9025_Device_t* device, + uint32_t* rxChannelMask); + +/** +* \brief This function masks/unmasks the PLL unlock GP interrupt for a requested PLL +* +* When the PLL frequency is being updated, the PLL is unlocked which generates +* a GP interrupt. For use cases where PLL frequency is required to be changed, +* the GP interrupt needs to be masked so that it does not flag a false interrupt. +* +* \pre +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param pllName PLL for which frequency needs to be set +* \param gpInterruptPin0Mask flag to mask(1) / unmask(0) the requested PLL unlock interrupt on Pin0 +* \param gpInterruptPin1Mask flag to mask(1) / unmask(0) the requested PLL unlock interrupt on Pin1 +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_PllUnlockGpInterruptMaskSet(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + uint8_t gpInterruptPin0Mask, + uint8_t gpInterruptPin1Mask); + +/** +* \brief This reads the PLL unlock GP interrupt mask for a requested PLL +* +* This function can be used to retrieve current GP Interrupt mask status +* for the requested PLL. +* +* \pre +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param pllName PLL for which PLL unlock GP Interrupt mask is requested +* \param pllGpInterruptPin0Mask Current mask/unmask status of the requested PLL unlock GP Interrupt on Pin0 +* \param pllGpInterruptPin1Mask Current mask/unmask status of the requested PLL unlock GP Interrupt on Pin1 +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_PllUnlockGpInterruptMaskGet(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + uint8_t* pllGpInterruptPin0Mask, + uint8_t* pllGpInterruptPin1Mask); + +/** +* \brief This function masks/unmasks the PLL overrange GP interrupt for a requested PLL +* +* When the PLL frequency is being updated, the PLL is unlocked which generates +* a GP interrupt. For use cases where PLL frequency is required to be changed, +* the GP interrupt needs to be masked so that it does not flag a false interrupt. +* +* \pre +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param pllName PLL for which frequency needs to be set +* \param gpInterruptPin0Mask flag to mask(1) / unmask(0) the requested PLL unlock interrupt on Pin0 +* \param gpInterruptPin1Mask flag to mask(1) / unmask(0) the requested PLL unlock interrupt on Pin1 +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_PllOverrangeGpInterruptMaskSet(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + uint8_t gpInterruptPin0Mask, + uint8_t gpInterruptPin1Mask); + +/** +* \brief This reads the GP Interrupt overrange mask status +* +* This function can be used to retrieve current GP Interrupt mask status +* for the requested PLL. +* +* \pre +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param pllName PLL for which GP Interrupt overrange mask is requested +* \param pllGpInterruptPin0Mask Current mask/unmask status of the requested PLL unlock GP Interrupt on Pin0 +* \param pllGpInterruptPin1Mask Current mask/unmask status of the requested PLL unlock GP Interrupt on Pin1 +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_PllOverrangeGpInterruptMaskGet(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + uint8_t* pllGpInterruptPin0Mask, + uint8_t* pllGpInterruptPin1Mask); + +/** +* \brief This function sets up the ORx signal chain Radio Ctrl configuration +* +* The table below outlines the various ORx enable modes and corresponding ORx select mechanisms. +* +* ORx PIN Mode | ORx Select Mechanism +* -----------------------------|------------------------------------------------------------------------------------ +* SPI Mode | ORx enable and channel select is accomplished through SPI registers +* Single Channel 3 Pin Mode | ORX_ENABLE[0] is enable/disable ctrl. ORx select is accomplished by ORX_ENABLE[2:1] +* Single Channel 2 Pin Mode | ORX_ENABLE[0] is enable/disable ctrl. ORx select is accomplished by SPI registers. +* | ORx select is multiplexed between 2 possible ORx channels depending on the level of ORx_ENABLE[1] pin +* Single Channel 1 Pin Mode | ORX_ENABLE[0] is enable/disable ctrl. ORx select is accomplished by SPI registers. +* Dual Channel 4 Pin Mode | ORX_ENABLE[1:0] pins are enable/disable ctrl. ORx select is accomplished by ORX_ENABLE[3:2] +* Dual Channel 2 Pin Mode | ORX_ENABLE[1:0] pins are enable/disable ctrl. ORx select is accomplished by SPI registers +* +* \pre This function can be called after initialization and completion of stream loading. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param orxRadioCtrlModeCfg Pointer to ORx radio ctrl mode configuration settings +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_OrxRadioCtrlCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_ORxRadioCtrlModeCfg_t* orxRadioCtrlModeCfg); + +/** +* \brief This function sets up the Rx signal chain Radio Ctrl configuration +* +* In Pin mode, the Rx signal chain is controlled via dedicated pins RX_ENABLE<3:0>. In +* Non-pin mode, the API command is used to configure Rx radio ctrl settings. +* +* \pre This function can be called after initialization and completion of stream loading. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param rxRadioCtrlModeCfg Pointer to ORx radio ctrl mode configuration settings +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxRadioCtrlCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxRadioCtrlModeCfg_t* rxRadioCtrlModeCfg); + +/** +* \brief This function sets up the Tx signal chain Radio Ctrl configuration +* +* In Pin mode, the Tx signal chain is controlled via dedicated pins TX_ENABLE<3:0>. In +* Non-pin mode, the API command is used to configure Tx radio ctrl settings. +* +* \pre This function can be called after initialization and completion of stream loading. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param txRadioCtrlModeCfg Pointer to ORx radio ctrl mode configuration settings +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxRadioCtrlCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxRadioCtrlModeCfg_t* txRadioCtrlModeCfg); + +/** +* \brief This function reads back the ORx signal chain Radio Ctrl configuration +* +* \pre This function can be called after initialization. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param orxRadioCtrlModeCfg Pointer to ORx radio ctrl mode configuration settings +* which will be updated with read back configuration +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_OrxRadioCtrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_ORxRadioCtrlModeCfg_t* orxRadioCtrlModeCfg); + +/** +* \brief This function reads back the Rx signal chain Radio Ctrl configuration +* +* \pre This function can be called after initialization. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param rxChannel Desired RxChannel +* \param rxRadioCtrlModeCfg Pointer to Rx radio ctrl mode configuration settings +* which will be updated with read back configuration +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxRadioCtrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxRadioCtrlModeCfg_t* rxRadioCtrlModeCfg); + +/** +* \brief This function reads back the Tx signal chain Radio Ctrl configuration +* +* \pre This function can be called after initialization. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param txChannel Desired TxChannel +* \param txRadioCtrlModeCfg Pointer to Tx radio ctrl mode configuration settings +* which will be updated with read back configuration +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxRadioCtrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxRadioCtrlModeCfg_t* txRadioCtrlModeCfg); + +/** +* \brief This function attempts to configure the ADRV9025 ARM TDD Control GPIO pin for the requested signal ID +* +* The GPIO configuration includes +* +* \pre This function can be called after ARM binary has been loaded. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param signalId Input parameter to this function representing signal for which GPIO assignment is requested +* \param armGpioPin Pointer to ARM GPIO pin structure requested for configuration +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_ArmGpioPinSet(adi_adrv9025_Device_t* device, + uint8_t signalId, + adi_adrv9025_ArmGpioPinCfg_t* armGpioPin); + +/** +* \brief This function attempts to retrieve the ADRV9025 ARM TDD Control GPIO pin for the requested signal ID +* +* \pre This function can be called after ARM binary has been loaded. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param signalId Represents the signal for which GPIO pin config is requested +* \param gpioPinSel Output parameter which is a pointer to a GPIO pin sel enum. The pointer +* memory will be updated with the GPIO pin assigned to the requested signal ID. +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_ArmGpioPinGet(adi_adrv9025_Device_t* device, + uint8_t signalId, + adi_adrv9025_GpioPinSel_e* gpioPinSel); + +/** +* \brief This function commands the ARM to trigger the execution of a stream +* +* \pre This function can be called after the stream binary has been loaded. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param streamId unique stream identification no. of the stream to execute +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_StreamTrigger(adi_adrv9025_Device_t* device, + uint8_t streamId); + +/** +* \brief This function configures the stream trigger GPIO pin for the requested stream signal ID +* +* This function assigns the GPIO pin for the requested stream signal, enables the stream GPIO signal +* and sets the direction of the GPIO to input w.r.t ADRV9025 +* +* \pre This function can be called after the stream binary has been loaded. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param signalId Represents the stream trigger GPIO signal for which GPIO pin is required to be configured +* \param streamTriggerGpio GPIO pin select to be mapped to stream trigger functionality +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_StreamGpioPinSet(adi_adrv9025_Device_t* device, + uint8_t signalId, + adi_adrv9025_GpioPinSel_e streamTriggerGpio); + +/** +* \brief This function retrieves the current GPIO assignments to stream trigger signals +* +* \pre This function can be called after the Stream binary has been loaded. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param signalId Represents the stream trigger GPIO signal for which GPIO pin config is requested +* \param streamTriggerGpio GPIO pin currently assigned to the requested stream trigger signal +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_StreamGpioPinGet(adi_adrv9025_Device_t* device, + uint8_t signalId, + adi_adrv9025_GpioPinSel_e* streamTriggerGpio); + +/** +* \brief This function performs range check for adi_adrv9025_StreamGpioConfigSet API params +* +* \pre This function is automatically called as part of adi_adrv9025_StreamGpioConfigSet if +* ADI_ADRV9025_RADIOCTRL_RANGE_CHECK is set to 1. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param streamGpioPinCfg pointer to structure holding stream GPIO control signals +* +* \retval ADI_ADRV9025_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_StreamGpioConfigSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_StreamGpioPinCfg_t* streamGpioPinCfg); + +/** +* \brief This function performs range check for adi_adrv9025_TxToOrxMappingSet API +* +* \pre This function is automatically called as part of adi_adrv9025_TxToOrxMappingSet if +* ADI_ADRV9025_RADIOCTRL_RANGE_CHECK is set to 1. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param orxChannel Target ORx Front end for Tx-ORx mapping +* \param txChannel Target Tx channel that is routed back into the requested ORx channel +* +* \retval ADI_ADRV9025_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxToOrxMappingSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e orxChannel, + adi_adrv9025_TxChannels_e txChannel); + +/** +* \brief This function decodes the encoded Tx-ORx mapping received from ARM +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param encodedTxToORxMapping Encoded Tx-ORx mapping received from ARM +* \param orxChannel ORx channel for which Tx channel is requested +* \param txChannel Tx channel mapped to the requested ORx channel +* +* \retval ADI_ADRV9025_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_OrxMapDecode(adi_adrv9025_Device_t* device, + uint16_t encodedTxToORxMapping, + adi_adrv9025_RxChannels_e orxChannel, + adi_adrv9025_TxChannels_e* txChannel); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_reg_addr_macros.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_reg_addr_macros.h new file mode 100644 index 0000000..ea8a004 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_reg_addr_macros.h @@ -0,0 +1,417 @@ +/** +* \file adrv9025_reg_addr_macros.h +* \brief Contains ADRV9025 API miscellaneous macro definitions +* Use these register Address only for initialize and before MCS. +* Should use Bitfield function after MCS. +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADRV9025_REG_ADDR_MACROS_H +#define _ADRV9025_REG_ADDR_MACROS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADRV9025_BF_ENCODE(value, mask, shift) (((value) << (shift)) & (mask)) +#define ADRV9025_BF_DECODE(value, mask, shift) (((value) & (mask)) >> (shift)) +#define ADRV9025_BF_CLEAR(result, mask) (result = ((result) & ~(mask))) +#define ADRV9025_BF_SET(result, mask) (result = (result) | (mask)) +#define ADRV9025_BF_UPDATE(result, value, mask, shift) (result = ((result) & ~(mask)) | ( ((value) << (shift)) & (mask))) +#define ADRV9025_BF_EQUAL(value, mask) ((mask) == ((value) & (mask))) + +#define ADRV9025_ADDR_SPI_INTERFACE_CONFIG_A 0x0000 +#define ADRV9025_CONFIG_A_SPI_LSB_FIRST 0x42 +#define ADRV9025_CONFIG_A_SPI_ADDR_ASCENSION 0x24 +#define ADRV9025_CONFIG_A_SPI_SDO_ACTIVE 0x18 + +#define ADRV9025_ADDR_SPI_INTERFACE_CONFIG_B 0x0001 +#define ADRV9025_CONFIG_B_SINGLE_INSTRUCTION 0x80 + +#define ADRV9025_ADDR_PRODUCT_ID_0 0x0004 +#define ADRV9025_ADDR_PRODUCT_ID_1 0x0005 +#define ADRV9025_ADDR_SCRATCH_PAD 0x000A +#define ADRV9025_ADDR_VENDOR_ID_0 0x000C +#define ADRV9025_ADDR_VENDOR_ID_1 0x000D +#define ADRV9025_ADDR_SCRATCH_PAD_UPPER_ADDRESS_SPACE 0x7217 /* JTX_LINK Converter select */ + +#define ADRV9025_ADDR_DIGITAL_IO_CONTROL 0x0010 +#define ADRV9025_IO_CONTROL_SPI2_OUTS_DRV_SEL 0x02 +#define ADRV9025_IO_CONTROL_SPI_OUTS_DRV_SEL 0x01 + +#define ADRV9025_ADDR_SPI2_CONFIG 0x0011 +/* Same as CoreSpiInterfaceConfigA */ +#define ADRV9025_ADDR_SPI2_CONFIG2 0x0012 +#define ADRV9025_SPI2_CONFIG2_SPI_2_EN 0x1 + +#define ADRV9025_ADDR_CLOCK_CONTROL_0 0x0013 +#define ADRV9025_CC0_DIG_REF_CLK_DIV_RATIO_MASK 0xE0 +#define ADRV9025_CC0_DIG_REF_CLK_DIV_RATIO_SHIFT 5 +#define ADRV9025_CC0_REG_CLK_DIVIDE_RATIO_MASK 0x18 +#define ADRV9025_CC0_REG_CLK_DIVIDE_RATIO_SHIFT 3 +#define ADRV9025_CC0_CPU_CLK_ENABLE 0x04 +#define ADRV9025_CC0_CPU_CLK_DIVIDE_RATIO_MASK 0x03 +#define ADRV9025_CC0_CPU_CLK_DIVIDE_RATIO_SHIFT 0 + +#define ADRV9025_ADDR_CLOCK_CONTROL_7 0x001A +#define ADRV9025_CC7_DIGITAL_CLOCK_POWER_UP 0x40 +#define ADRV9025_CC7_USE_DEVICE_CLK_AS_HSDIGCLK 0x80 +#define ADRV9025_CC7_USE_DEVICE_CLK_AS_HSDIGCLK_UNTIL_MCS 0x20 + +#define ADRV9025_ADDR_REFERENCE_CLOCK_CYCLE 0x0025 +#define ADRV9025_ADDR_AHB_SPI_BRIDGE 0x0026 +#define ADRV9025_AHB_SPI_BRIDGE_RESET 0x0E +#define ADRV9025_AHB_SPI_BRIDGE_EN 0x01 + +#define ADRV9025_ADDR_SYSREF_PAD_CONFIG 0x0047 +#define ADRV9025_SYSREF_PAD_LVDS_MODE 0x2 +#define ADRV9025_SYSREF_PAD_PD 0x1 + +#define ADRV9025_ADDR_SYSREF_CONTROL_1 0x0048 +#define ADRV9025_SYSREF_BUFFER_ENABLE 0x40 +#define ADRV9025_SYSREF_SAMPLE_ENABLE 0x10 +#define ADRV9025_SYSREF_REGISTER_ENABLE 0x08 + +#define ADRV9025_ADDR_DEVICE_CLK_CONTROL_1 0x004A +#define ADRV9025_ADDR_REFCLK_CORE_0 0x0178 +#define ADRV9025_ADDR_REFCLK_CORE_2 0x017A +#define ADRV9025_DCC1_RESETB_TFLASH 0x80 +#define ADRV9025_DCC1_DEVCLK_DIVIDER_MCS_RESETB 0x10 +#define ADRV9025_DCC1_DEVICE_CLK_DIVIDE_RATIO_MASK 0x0C +#define ADRV9025_DCC1_DEVICE_CLK_DIVIDE_RATIO_SHIFT 2 +#define ADRV9025_DCC1_DEVICE_CLK_BUFFER_ENABLE 0x02 +#define ADRV9025_DCC1_DEV_CLKBUF_OFFSET_EN 0x01 + +#define ADRV9025_DCC1_REFCLK_PLL_DRVR_STRENGTH 0x18 +#define ADRV9025_DCC1_REFCLK_ROOT_DRVR_STRENGTH 0x18 +#define ADRV9025_DCC1_REFCLK_DIGCORE_DRVR_STRENGTH 0xC0 + +#define ADRV9025_ADDR_TX_SYNC_PAD_CONFIG 0x0051 +#define ADRV9025_TX_SYNC_DRV_SELECT_MASK 0xC0 +#define ADRV9025_TX_SYNC_DRV_SELECT_SHIFT 6 +#define ADRV9025_TX_SYNC2_PAD_LVSD_PN_INV 0x20 +#define ADRV9025_TX_SYNC2_PAD_LVDS_MODE 0x10 +#define ADRV9025_TX_SYNC2_PAD_PD 0x08 +#define ADRV9025_TX_SYNC1_PAD_LVSD_PN_INV 0x04 +#define ADRV9025_TX_SYNC1_PAD_LVDS_MODE 0x02 +#define ADRV9025_TX_SYNC1_PAD_PD 0x01 + +#define ADRV9025_ADDR_RX_SYNC12_PAD_CONFIG 0x0052 +#define ADRV9025_RX_SYNC2_PAD_ONCHIP_TERM 0x80 +#define ADRV9025_RX_SYNC2_PAD_LVSD_PN_INV 0x40 +#define ADRV9025_RX_SYNC2_PAD_LVDS_MODE 0x20 +#define ADRV9025_RX_SYNC2_PAD_PD 0x10 +#define ADRV9025_RX_SYNC1_PAD_ONCHIP_TERM 0x08 +#define ADRV9025_RX_SYNC1_PAD_LVSD_PN_INV 0x04 +#define ADRV9025_RX_SYNC1_PAD_LVDS_MODE 0x02 +#define ADRV9025_RX_SYNC1_PAD_PD 0x01 + +#define ADRV9025_ADDR_RX_SYNC3_PAD_CONFIG 0x0053 +#define ADRV9025_RX_SYNC3_PAD_ONCHIP_TERM 0x08 +#define ADRV9025_RX_SYNC3_PAD_LVSD_PN_INV 0x04 +#define ADRV9025_RX_SYNC3_PAD_LVDS_MODE 0x02 +#define ADRV9025_RX_SYNC3_PAD_PD 0x01 + +/* CPU-C subsystem register */ +#define ADRV9025_CPU_C_ADDR_CTL_1 0x008C +#define ADRV9025_CPU_C_ADDR_BOOT_ADDR_BYTE0 0x0096 +#define ADRV9025_CPU_C_ADDR_BOOT_ADDR_BYTE1 0x0097 +#define ADRV9025_CPU_C_ADDR_BOOT_ADDR_BYTE2 0x0098 +#define ADRV9025_CPU_C_ADDR_BOOT_ADDR_BYTE3 0x0099 +#define ADRV9025_CPU_C_ADDR_STACK_PTR_BYTE0 0x009a +#define ADRV9025_CPU_C_ADDR_STACK_PTR_BYTE1 0x009b +#define ADRV9025_CPU_C_ADDR_STACK_PTR_BYTE2 0x009c +#define ADRV9025_CPU_C_ADDR_STACK_PTR_BYTE3 0x009d + +/* CPU-D subsystem register */ +# define ADRV9025_CPU_D_ADDR_CTL_1 0x015f +# define ADRV9025_CPU_D_ADDR_BOOT_ADDR_BYTE0 0x0160 +# define ADRV9025_CPU_D_ADDR_BOOT_ADDR_BYTE1 0x0161 +# define ADRV9025_CPU_D_ADDR_BOOT_ADDR_BYTE2 0x0162 +# define ADRV9025_CPU_D_ADDR_BOOT_ADDR_BYTE3 0x0163 +# define ADRV9025_CPU_D_ADDR_STACK_PTR_BYTE0 0x0164 +# define ADRV9025_CPU_D_ADDR_STACK_PTR_BYTE1 0x0165 +# define ADRV9025_CPU_D_ADDR_STACK_PTR_BYTE2 0x0166 +# define ADRV9025_CPU_D_ADDR_STACK_PTR_BYTE3 0x0167 + +/* CPU subsystem mask */ +#define ADRV9025_CPU_MASK_CTL1_DEBUG_ENABLE 0x80 +#define ADRV9025_CPU_MASK_CTL1_MEM_HRESP 0x08 +#define ADRV9025_CPU_MASK_CTL1_ERROR 0x02 +#define ADRV9025_CPU_MASK_CTL1_M3_RUN 0x01 +#define ADRV9025_CPU_MASK_DMA_CTL_RD_WRB 0x80 +#define ADRV9025_CPU_MASK_DMA_CTL_SYS_CODEB 0x40 +#define ADRV9025_CPU_MASK_DMA_CTL_BUS_WAITING 0x20 +#define ADRV9025_CPU_MASK_DMA_CTL_BUS_RESPONSE 0x10 +#define ADRV9025_CPU_MASK_DMA_CTL_BUS_SIZE 0x0C +#define ADRV9025_CPU_SHIFT_DMA_CTL_BUS_SIZE 0x2 +#define ADRV9025_CPU_MASK_DMA_CTL_AUTO_INCR 0x02 +#define ADRV9025_CPU_MASK_DMA_CTL_BUS_SELECT 0x01 /* write 1 for CPU-D, 0 for CPU-C */ + +/* DMA registers*/ +#define ADRV9025_CPU_ADDR_DMA_CTL 0x00ba +#define ADRV9025_CPU_ADDR_DMA_ADDR0 0x00be /* BUS_ADDR */ +#define ADRV9025_CPU_ADDR_DMA_ADDR1 0x00bd +#define ADRV9025_CPU_ADDR_DMA_ADDR2 0x00bc +#define ADRV9025_CPU_ADDR_DMA_ADDR3 0x00bb +#define ADRV9025_CPU_ADDR_DMA_DATA0 0x00c2 /* MEM_WRITE_DATA */ +#define ADRV9025_CPU_ADDR_DMA_DATA1 0x00c1 +#define ADRV9025_CPU_ADDR_DMA_DATA2 0x00c0 +#define ADRV9025_CPU_ADDR_DMA_DATA3 0x00bf + +/* CPU-C mailbox registers */ +#define ADRV9025_CPU_C_ADDR_COMMAND 0x00c3 +#define ADRV9025_CPU_C_ADDR_EXT_CMD_BYTE_1 0x00c4 +#define ADRV9025_CPU_C_ADDR_EXT_CMD_BYTE_2 0x00c5 +#define ADRV9025_CPU_C_ADDR_EXT_CMD_BYTE_3 0x00c6 +#define ADRV9025_CPU_C_ADDR_EXT_CMD_BYTE_4 0x00c7 +#define ADRV9025_CPU_C_ADDR_CMD_STATUS_0 0x00cb +#define ADRV9025_CPU_C_ADDR_CMD_STATUS_1 0x00cc +#define ADRV9025_CPU_C_ADDR_CMD_STATUS_2 0x00cd +#define ADRV9025_CPU_C_ADDR_CMD_STATUS_3 0x00ce +#define ADRV9025_CPU_C_ADDR_CMD_STATUS_4 0x00cf +#define ADRV9025_CPU_C_ADDR_CMD_STATUS_5 0x00d0 +#define ADRV9025_CPU_C_ADDR_CMD_STATUS_6 0x00d1 +#define ADRV9025_CPU_C_ADDR_CMD_STATUS_7 0x00d2 +#define ADRV9025_CPU_C_ADDR_CMD_STATUS_8 0x00d3 +#define ADRV9025_CPU_C_ADDR_CMD_STATUS_9 0x00d4 +#define ADRV9025_CPU_C_ADDR_CMD_STATUS_10 0x00d5 +#define ADRV9025_CPU_C_ADDR_CMD_STATUS_11 0x00d6 +#define ADRV9025_CPU_C_ADDR_CMD_STATUS_12 0x00d7 +#define ADRV9025_CPU_C_ADDR_CMD_STATUS_13 0x00d8 +#define ADRV9025_CPU_C_ADDR_CMD_STATUS_14 0x00d9 +#define ADRV9025_CPU_C_ADDR_CMD_STATUS_15 0x00da + +/* CPU-D mailbox registers */ +#define ADRV9025_CPU_D_ADDR_COMMAND 0x0147 +#define ADRV9025_CPU_D_ADDR_EXT_CMD_BYTE_1 0x0148 +#define ADRV9025_CPU_D_ADDR_EXT_CMD_BYTE_2 0x0149 +#define ADRV9025_CPU_D_ADDR_EXT_CMD_BYTE_3 0x014a +#define ADRV9025_CPU_D_ADDR_EXT_CMD_BYTE_4 0x014b +#define ADRV9025_CPU_D_ADDR_CMD_STATUS_0 0x014f +#define ADRV9025_CPU_D_ADDR_CMD_STATUS_1 0x0150 +#define ADRV9025_CPU_D_ADDR_CMD_STATUS_2 0x0151 +#define ADRV9025_CPU_D_ADDR_CMD_STATUS_3 0x0152 +#define ADRV9025_CPU_D_ADDR_CMD_STATUS_4 0x0153 +#define ADRV9025_CPU_D_ADDR_CMD_STATUS_5 0x0154 +#define ADRV9025_CPU_D_ADDR_CMD_STATUS_6 0x0155 +#define ADRV9025_CPU_D_ADDR_CMD_STATUS_7 0x0156 +#define ADRV9025_CPU_D_ADDR_CMD_STATUS_8 0x0157 +#define ADRV9025_CPU_D_ADDR_CMD_STATUS_9 0x0158 +#define ADRV9025_CPU_D_ADDR_CMD_STATUS_10 0x0159 +#define ADRV9025_CPU_D_ADDR_CMD_STATUS_11 0x015a +#define ADRV9025_CPU_D_ADDR_CMD_STATUS_12 0x015b +#define ADRV9025_CPU_D_ADDR_CMD_STATUS_13 0x015c +#define ADRV9025_CPU_D_ADDR_CMD_STATUS_14 0x015d +#define ADRV9025_CPU_D_ADDR_CMD_STATUS_15 0x015e + +#define ADRV9025_ADDR_MASTERBIAS_CONFIG_0 0x0111 +#define ADRV9025_CONFIG_0_PD_MASTERBIAS 0x80 +#define ADRV9025_CONFIG_0_TRM_VBG_ABS 0x08 + +#define ADRV9025_ADDR_MASTERBIAS_CONFIG_1 0x0112 +#define ADRV9025_CONFIG_1_TRM_VBG_TEMPCO 0x28 + +#define ADRV9025_ADDR_GP_LDO_BYTE1N 0x0120 +#define ADRV9025_ADDR_DEV_CLK_LDO_BYTE1 0x0124 +#define ADRV9025_ADDR_DEV_CLK_LDO_BYTE2 0x0125 +#define ADRV9025_DEV_CLK_LDO_PD 0x04 + +#define ADRV9025_ADDR_MCS_CONTROL_OFFSET 0x45 +#define ADRV9025_ADDR_MCS_CONTROL_3_OFFSET 0x47 + +#define ADRV9025_ADDR_ALL_RX 0x0200 +#define ADRV9025_ADDR_ALL_TX 0x0400 +#define ADRV9025_ADDR_ALL_ORX 0x0600 +#define ADRV9025_ADDR_ALL_PLLS 0x0800 + +#define ADRV9025_ADDR_CH0_RX 0x1200 +#define ADRV9025_ADDR_CH1_RX 0x1400 +#define ADRV9025_ADDR_CH2_RX 0x1600 +#define ADRV9025_ADDR_CH3_RX 0x1800 +#define ADRV9025_ADDR_CH0_ORX 0x1A00 +#define ADRV9025_ADDR_CH1_ORX 0x1C00 +#define ADRV9025_ADDR_CH0_TX 0x1E00 +#define ADRV9025_ADDR_CH1_TX 0x2000 +#define ADRV9025_ADDR_CH2_TX 0x2200 +#define ADRV9025_ADDR_CH3_TX 0x2400 +#define ADRV9025_ADDR_AUX_PLL 0x2600 +#define ADRV9025_ADDR_CLK_PLL 0x2800 +#define ADRV9025_ADDR_RF1_PLL 0x2A00 +#define ADRV9025_ADDR_RF2_PLL 0x6400 + +#define ADRV9025_ADDR_RX_CLOCK_CONFIG_0_OFFSET 0x0001 +#define ADRV9025_RCC0_CPU_CLK_ENABLE 0x80 +#define ADRV9025_RCC0_CLKGEN_OUTPUT_BUFFER_EN 0x40 +#define ADRV9025_RCC0_AGC_CLK_DIVIDE_RATIO_MASK 0x30 +#define ADRV9025_RCC0_AGC_CLK_DIVIDE_RATIO_SHIFT 4 +#define ADRV9025_RCC0_REG_CLK_DIVIDE_RATIO_MASK 0x0C +#define ADRV9025_RCC0_REG_CLK_DIVIDE_RATIO_SHIFT 2 +#define ADRV9025_RCC0_CPU_CLK_DIVIDE_RATIO_MASK 0x03 +#define ADRV9025_RCC0_CPU_CLK_DIVIDE_RATIO_SHIFT 0 + +#define ADRV9025_ADDR_RX_CLOCK_CONFIG_6_OFFSET 0x0007 +#define ADRV9025_RCC6_RPFIR_CLK_DIVIDE_RATIO_MASK 0x03 +#define ADRV9025_RCC6_RPFIR_CLK_DIVIDE_RATIO_SHIFT 0 + +#define ADRV9025_ADDR_RX_REFERENCE_CLOCK_CYCLE_OFFSET 0x000A +#define ADRV9025_ADDR_ORX_REFERENCE_CLOCK_CYCLE_OFFSET 0x000C +#define ADRV9025_ADDR_TX_REFERENCE_CLOCK_CYCLE_OFFSET 0x0008 + +#define ADRV9025_ADDR_TX_CLOCK_CONTROL_0_OFFSET 0x0003 +#define ADRV9025_TCC0_CPU_CLK_ENABLE 0x80 +#define ADRV9025_TCC0_TX_ENABLE_CG_GATES_CFR_CLOCKS 0x40 +#define ADRV9025_TCC0_TX_ATTEN_CLK_DIVIDE_RATIO_MASK 0x30 +#define ADRV9025_TCC0_TX_ATTEN_CLK_DIVIDE_RATIO_SHIFT 4 +#define ADRV9025_TCC0_REG_CLK_DIVIDE_RATIO_MASK 0x0C +#define ADRV9025_TCC0_REG_CLK_DIVIDE_RATIO_SHIFT 2 +#define ADRV9025_TCC0_CPU_CLK_DIVIDE_RATIO_MASK 0x03 +#define ADRV9025_TCC0_CPU_CLK_DIVIDE_RATIO_SHIFT 0 + +#define ADRV9025_ADDR_TX_CLOCK_CONTROL_2_OFFSET 0x0005 +#define ADRV9025_TCC2_TPFIR_CLK_DIVIDE_RATIO_MASK 0x03 +#define ADRV9025_TCC2_TPFIR_CLK_DIVIDE_RATIO_SHIFT 0 + +#define ADRV9025_ADDR_TX_CLOCK_CONTROL_3_OFFSET 0x0006 +#define ADRV9025_TCC3_TX_ATTEN_CLK_ENABLE_MASK 0x80 +#define ADRV9025_TCC3_TX_ATTEN_CLK_ENABLE_SHIFT 7 + +#define ADRV9025_ADDR_TX_FILTER_CONFIG_OFFSET 0x0020 +#define ADRV9025_TX_PFIR_TAPS_MASK 0x60 +#define ADRV9025_TX_PFIR_TAPS_SHIFT 5 +#define ADRV9025_TX_PFIR_GAIN_MASK 0x03 +#define ADRV9025_TX_PFIR_GAIN_SHIFT 0 + +#define ADRV9025_ADDR_TX_PFIR_COEFF_CTL_OFFSET 0x0021 +#define ADRV9025_PFIR_COEFF_PROG_CLK_EN 0x80 +#define ADRV9025_PFIR_COEFF_WR_ENABLE 0x40 +#define ADRV9025_PFIR_COEFF_AUTO_INCR 0x20 +#define ADRV9025_ADDR_TX_PFIR_COEFF_DATA_OFFSET 0x0022 +#define ADRV9025_ADDR_TX_PFIR_COEFF_ADDR_OFFSET 0x0023 + +#define ADRV9025_ADDR_RX_PFIR_SETTINGS_OFFSET 0x003a +#define ADRV9025_RX_PFIR_TAPS_MASK 0x30 +#define ADRV9025_RX_PFIR_TAPS_SHIFT 4 +#define ADRV9025_RX_PFIR_GAIN_MASK 0x0C +#define ADRV9025_RX_PFIR_GAIN_SHIFT 2 +#define ADRV9025_RX_PFIR_DECIMATION_MASK 0x03 +#define ADRV9025_RX_PFIR_DECIMATION_SHIFT 0 + +#define ADRV9025_ADDR_RX_PFIR_COEFF_CTL_OFFSET 0x003b +#define ADRV9025_ADDR_RX_PFIR_COEFF_DATA_OFFSET 0x003c +#define ADRV9025_ADDR_RX_PFIR_COEFF_ADDR_OFFSET 0x003d + +#define ADRV9025_ADDR_ORX_PFIR_COEFF_CTL_OFFSET 0x0013 +#define ADRV9025_ADDR_ORX_PFIR_COEFF_DATA_OFFSET 0x0014 +#define ADRV9025_ADDR_ORX_PFIR_COEFF_ADDR_OFFSET 0x0015 +#define ADRV9025_PFIR_COEFF_RX_C_SEL 0x04 +#define ADRV9025_PFIR_COEFF_RX_B_SEL 0x02 +#define ADRV9025_PFIR_COEFF_RX_A_SEL 0x01 + +#define ADRV9025_ADDR_RX_PFIR_CONFIG_SETTINGSN_OFFSET 0x001a + +#define ADRV9025_ADDR_RX_PFIR_BANK_SEL_OFFSET 0x0019 +#define ADRV9025_PFIR_CONFIG_FOR_ORX_2_MASK 0xC0 +#define ADRV9025_PFIR_CONFIG_FOR_ORX_2_SHIFT 6 +#define ADRV9025_PFIR_CONFIG_FOR_ORX_1_MASK 0x30 +#define ADRV9025_PFIR_CONFIG_FOR_ORX_1_SHIFT 4 +#define ADRV9025_PFIR_CONFIG_FOR_LOOPBACK_2_MASK 0x0C +#define ADRV9025_PFIR_CONFIG_FOR_LOOPBACK_2_SHIFT 2 +#define ADRV9025_PFIR_CONFIG_FOR_LOOPBACK_1_MASK 0x03 +#define ADRV9025_PFIR_CONFIG_FOR_LOOPBACK_1_SHIFT 0 + +#define ADRV9025_ADDR_PLL_POWER_DOWNS 0x0050 + +#define ADRV9025_ADDR_MAIN_STREAM_CTL_OFFSET 0x00DB +#define ADRV9025_ADDR_TX0_STREAM_CTL_OFFSET ADRV9025_ADDR_CH0_TX+0x00AD +#define ADRV9025_ADDR_TX1_STREAM_CTL_OFFSET ADRV9025_ADDR_CH1_TX+0x00AD +#define ADRV9025_ADDR_TX2_STREAM_CTL_OFFSET ADRV9025_ADDR_CH2_TX+0x00AD +#define ADRV9025_ADDR_TX3_STREAM_CTL_OFFSET ADRV9025_ADDR_CH3_TX+0x00AD +#define ADRV9025_ADDR_RX0_STREAM_CTL_OFFSET ADRV9025_ADDR_CH0_RX+0x01A8 +#define ADRV9025_ADDR_RX1_STREAM_CTL_OFFSET ADRV9025_ADDR_CH1_RX+0x01A8 +#define ADRV9025_ADDR_RX2_STREAM_CTL_OFFSET ADRV9025_ADDR_CH2_RX+0x01A8 +#define ADRV9025_ADDR_RX3_STREAM_CTL_OFFSET ADRV9025_ADDR_CH3_RX+0x01A8 +#define ADRV9025_ADDR_ORX0_STREAM_CTL_OFFSET ADRV9025_ADDR_CH0_ORX+0x0173 +#define ADRV9025_ADDR_ORX1_STREAM_CTL_OFFSET ADRV9025_ADDR_CH1_ORX+0x0173 +#define ADRV9025_STREAM_RESET 0x01 +#define ADRV9025_STREAM_BASE_BYTE0_OFFSET 1 +#define ADRV9025_STREAM_BASE_BYTE1_OFFSET 2 +#define ADRV9025_LAST_STREAM_NUMBER_OFFSET 3 + +#define ADRV9025_ADDR_PLL_REF_CLK_REG 0x28D0 +#define ADRV9025_REF_CLK_DIVIDE_RATIO_MASK 0x03 +#define ADRV9025_REF_CLK_DIVIDE_RATIO_SHIFT 0 + +#define ADRV9025_ADDR_SYSREF_DES_MASTER_PD 0x6800 +#define ADRV9025_ADDR_SYSREF_DES_PHY_PD 0x6801 + +#define ADRV9025_ADDR_JTX_COMMON_0 0x00006689 +#define ADRV9025_ADDR_JRX_COMMON_0 0x0000667C + +#define ADRV9025_ADDR_RXALL_BBIC_ENABLE 0x03BD +#define ADRV9025_ADDR_TXALL_BBIC_ENABLE 0x04E8 +#define ADRV9025_ADDR_RXALL_DEC_OVERLOAD_CONFIG2 0x02F5 +#define ADRV9025_ADDR_DEC_OVERLOAD_CONFIG2_OFFSET 0x00F5 + +#define ADRV9025_ADDR_RX_DECIMATED_PWR_OFFSET 0x00C1 +#define ADRV9025_ADDR_ORX_DECIMATED_PWR_OFFSET 0x0034 + +#define ADRV9025_ADDR_RX_DIGITAL_GAIN_CONFIG2_OFFSET 0x00C8 +#define ADRV9025_ADDR_ORX_DIGITAL_GAIN_CONFIG2_OFFSET 0x0039 + +#define ADRV9025_ADDR_RX_DEC_POWER_CONFIG1_OFFSET 0x00B2 +#define ADRV9025_ADDR_ORX_DEC_POWER_CONFIG1_OFFSET 0x002D + +#define ADRV9025_ADDR_DPD_ADP_MMR_ADP_INT 0x6200C10CU +#define ADRV9025_ADDR_DPD_ACT_MMR_CAP_STAT_TX1 0xA082011CU +#define ADRV9025_ADDR_DPD_ACT_MMR_CAP_STAT_TX2 0xA882011CU +#define ADRV9025_ADDR_DPD_ACT_MMR_CAP_STAT_TX3 0xB082011CU +#define ADRV9025_ADDR_DPD_ACT_MMR_CAP_STAT_TX4 0xB882011CU +#define ADRV9025_ADDR_DPD_ACT_MMR_STAT_TX1 0xA08200F0U +#define ADRV9025_ADDR_DPD_ACT_MMR_STAT_TX2 0xA88200F0U +#define ADRV9025_ADDR_DPD_ACT_MMR_STAT_TX3 0xB08200F0U +#define ADRV9025_ADDR_DPD_ACT_MMR_STAT_TX4 0xB88200F0U +#define ADRV9025_ADDR_DPD_TX_CAPTURE_DATA 0x62000000U +#define ADRV9025_ADDR_DPD_ALT_TX_CAPTURE_DATA 0x62008000U + +#define ADRV9025_ADDR_DPD_ORX_CAPTURE_DATA 0x62004000U + +#define ADRV9025_ADDR_DPD_ACT_MMR_LUT_OFF_TX1 0xA0820088U +#define ADRV9025_ADDR_DPD_ACT_MMR_LUT_OFF_TX2 0xA8820088U +#define ADRV9025_ADDR_DPD_ACT_MMR_LUT_OFF_TX3 0xB0820088U +#define ADRV9025_ADDR_DPD_ACT_MMR_LUT_OFF_TX4 0xB8820088U + +#define ADRV9025_ADDR_DPD_ACT_MMR_DPD_CFG_TX1 0xA0820000U +#define ADRV9025_ADDR_DPD_ACT_MMR_DPD_CFG_TX2 0xA8820000U +#define ADRV9025_ADDR_DPD_ACT_MMR_DPD_CFG_TX3 0xB0820000U +#define ADRV9025_ADDR_DPD_ACT_MMR_DPD_CFG_TX4 0xB8820000U + +#define ADRV9025_ADDR_DPD_ACT_MMR_DPD_MOD_TX1 0xA0820004U +#define ADRV9025_ADDR_DPD_ACT_MMR_DPD_MOD_TX2 0xA8820004U +#define ADRV9025_ADDR_DPD_ACT_MMR_DPD_MOD_TX3 0xB0820004U +#define ADRV9025_ADDR_DPD_ACT_MMR_DPD_MOD_TX4 0xB8820004U + +#define ADRV9025_EXT_DPD_ACTUATOR_TX1_LUT_BASEADDR 0xA0800000U +#define ADRV9025_EXT_DPD_ACTUATOR_TX2_LUT_BASEADDR 0xA8800000U +#define ADRV9025_EXT_DPD_ACTUATOR_TX3_LUT_BASEADDR 0xB0800000U +#define ADRV9025_EXT_DPD_ACTUATOR_TX4_LUT_BASEADDR 0xB8800000U + +#define ADRV9025_DES_CBUS_CONTROL_ADDRESS 0x6805 +#define ADRV9025_DES_CBUS_PHY_WSTROBE 0x6806 +#define ADRV9025_DES_CBUS_DATA_WRITE 0x6808 +#define ADRV9025_DES_CBUS_CONTROL_CHANNEL 0x6809 +#define ADRV9025_DES_CBUS_PLL_SELECT 0x680A +#define ADRV9025_DES_CBUS_DATA_READBACK 0x680B + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_rx.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_rx.h new file mode 100644 index 0000000..b3e9f5e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_rx.h @@ -0,0 +1,1130 @@ +/** +* \file adrv9025_rx.h +* \brief Contains ADRV9025 Rx related private function prototypes for +* adrv9025_rx.c which helsp adi_adrv9025_rx.c +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADRV9025_RX_H_ +#define _ADRV9025_RX_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "adi_adrv9025_rx.h" +#include "../devices/adrv9025/private/include/adrv9025_bf_rx.h" +#include "../devices/adrv9025/private/include/adrv9025_bf_orx.h" +#include "../devices/adrv9025/private/include/adrv9025_bf_analog_rx_mem_map.h" +#include "../devices/adrv9025/private/include/adrv9025_bf_analog_orx_mem_map.h" +#include "../devices/adrv9025/private/include/adrv9025_bf_orx.h" +#include "../devices/adrv9025/private/include/adrv9025_reg_addr_macros.h" + +/** +* \brief Formats gain table structure input into a format expected by ARM DMA +* +* Format Gain Table Data as follows : +* No. of Bytes per Gain Table Entry = 8 +* Addr 8 x gainIndex : {13'b0 , rx_fe_gain[7:0], dig_gain[10:0]} +* Addr 8 x gainIndex + 4 : {12'b0, tia_control, adc_control, ext_control[1:0], phase_offset[15:0]} +* +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param gainTablePtr Input gain table +* \param formattedGainTablePtr memory to store formatted gain table data +* \param numGainIndicesInTable number of gain table entries +* +* \retval ADI_COMMON_ERR_NULL_PARAM Recovery action for NULL parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxGainTableFormat(adi_adrv9025_Device_t* device, + adi_adrv9025_RxGainTableRow_t* gainTablePtr, + uint8_t* formattedGainTablePtr, + uint16_t numGainIndicesInTable); + +/** +* \brief Parses gain table in ARM DMA data format into a gain table row structure +* +* Format Gain Table Data as follows : +* No. of Bytes per Gain Table Entry = 8 +* armDmaDataGainIndex[8 x gainIndex] : {13'b0 , rx_fe_gain[7:0], dig_gain[10:0]} +* armDmaDataGainIndex[8 x gainIndex + 4] : {12'b0, tia_control, adc_control, ext_control[1:0], phase_offset[15:0]} +* +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param gainTablePtr pointer to gain table row entry structure where parsed data is stored +* \param armDmaDataGainTablePtr memory containing data from ARM DMA +* \param numGainIndicesInTable number of gain table entries +* +* \retval ADI_COMMON_ERR_NULL_PARAM Recovery action for NULL parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxGainTableParse(adi_adrv9025_Device_t* device, + adi_adrv9025_RxGainTableRow_t* gainTablePtr, + uint8_t* armDmaDataGainTablePtr, + uint16_t numGainIndicesInTable); + +/** +* \brief Calculates parameters required to read Rx Gain Table from ADRV9025 SRAM +* +* This function calculates the number of gain indices to read and the SRAM base +* address for the read operation given the maximum read size and gain index offset +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannel is the channel for which gain table read is requested +* \param maxReadGainIndices is the maximum no. of gain indices allowed to be read +* \param gainIndexOffset is the offsetted index from maximum gain index which is +* the starting gain index to read from +* \param numGainIndicesToRead output from this function which provides the no. of gain table +* row entry reads to be performed +* \param baseAddr is the starting SRAM address for read operation (output) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxGainTableReadParamsCompute(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint16_t maxReadGainIndices, + uint8_t gainIndexOffset, + uint16_t* numGainIndicesToRead, + uint32_t* baseAddr); + +/** +* \brief Returns the Rx Bitfield function channel base addresses for a given Rx Channel +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannel is the channel for which Rx bit field base address is requested +* \param rxChannelBitfieldAddr pointer to the Rx baseaddresses reqd by the bitfield. +* This function updates the memory pointed to by the pointer which can be used +* by the calling function. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxBitfieldAddressGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adrv9025_BfRxChanAddr_e* rxChannelBitfieldAddr); + +/** +* \brief Returns the ORx Bitfield function channel base addresses for a given Rx Channel +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param orxChannel is the channel for which ORx bit field base address is requested +* \param orxChannelBitfieldAddr pointer to the ORx baseaddresses reqd by the bitfield. +* This function updates the pointer memory passed by the calling function +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_OrxBitfieldAddressGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e orxChannel, + adrv9025_BfOrxChanAddr_e* orxChannelBitfieldAddr); + +/** +* \brief Returns the analog Rx Bitfield function channel base addresses for a given Rx Channel +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannel is the channel for which analog Rx bit field base address is requested +* \param rxChannelAnalogBitfieldAddr pointer to the Rx analog baseaddresses reqd by the bitfield(output) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxAnalogBitfieldAddressGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adrv9025_BfAnalogRxMemMapChanAddr_e* rxChannelAnalogBitfieldAddr); + +/** +* \brief Returns the analog ORx Bitfield function channel base addresses for a req ORx Channel +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param orxChannel is the channel for which analog Orx bit field base address is requested +* \param orxChannelAnalogBitfieldAddr pointer to the ORx analog baseaddresses reqd by the bitfield(output) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_OrxAnalogBitfieldAddressGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e orxChannel, + adrv9025_BfAnalogOrxMemMapChanAddr_e* orxChannelAnalogBitfieldAddr); + +/** +* \brief This function unassigns gain ctrl pin GPIOs and reports error if +* the recovery action is an error from a previous function call +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param sharedResourceArr is the array containing currently assigned gain ctrl GPIOs +* \param recoveryAction is the recovery action from a previous function call +* \param customError is the error to be reported in case of an error recovery action +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxGainCtrlPinReportError(adi_adrv9025_Device_t* device, + int32_t sharedResourceArr[], + int32_t recoveryAction, + const char* customError); + +/** +* \brief Returns the Rx SPI channel base addresses for a given Rx Channel +* +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param channelMask is the channel for which Rx base address is requested +* +* \retval uint16_t Return Base Address for Rx channel +*/ +uint16_t adrv9025_RxAddrDecode(adi_adrv9025_Device_t* device, + uint32_t channelMask); + +/** +* \brief Configures one or more RX FIR filters in the device +* +* The device stores 1 RX FIR filter per channel. +* The device stores an independent filter for each ORx front end (ORx1, ORx2, ORx3, ORx4). +* Internal Loopback 1 and 2 share a FIR filter, and Internal loopback 3 and 4 share a FIR filter. +* Rx and ORx channel can have 24, 48, or 72 taps. +* +* The function is not called directly. It is called as a part of the adi_adrv9025_initialize() function. +* The function could be used to change A FIR filter later, but would require calibrations to be rerun. +* +* \pre This function is called during device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* \param device Pointer to the ADRV9025 data structure +* \param rxChanMask One or more RX channel from adi_adrv9025_RxChannels_e. +* \param gain_dB The gain_dB value (-12, -6, 0, 6) +* \param numFirCoefs The number of Fir Coefs in coefs array (24, 48, 72) +* \param coefs[] Pointer to coefs array +* \param arraySize The size of coefs array +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* \ +*/ +int32_t adrv9025_RxFirWrite(adi_adrv9025_Device_t* device, + uint32_t rxChanMask, + int8_t gain_dB, + uint8_t numFirCoefs, + int16_t coefs[], + uint8_t arraySize); + +/** +* \brief This function unassigns ext ctrl word GPIOs and reports error if the +* recovery action is an error from a previous function call +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param sharedResourceArr is the array containing currently assigned ext ctrl GPIOs +* \param numSharedResources is the number of array +* \param recoveryAction is the recovery action from a previous function call +* \param customError is the error to be reported in case of an error recovery action +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxExtCtrlPinReportError(adi_adrv9025_Device_t* device, + int32_t sharedResourceArr[], + uint8_t numSharedResources, + int32_t recoveryAction, + const char* customError); + +/** +* \brief This function unassigns dualband ctrl word GPIOs and reports error if the +* recovery action is an error from a previous function call +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param sharedResourceArr is the array containing currently assigned dualband ctrl GPIOs +* \param numSharedResources is the number of array +* \param recoveryAction is the recovery action from a previous function call +* \param customError is the error to be reported in case of an error recovery action +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxDualbandLnaCtrlPinReportError(adi_adrv9025_Device_t* device, + int32_t sharedResourceArr[], + uint8_t numSharedResources, + int32_t recoveryAction, + const char* customError); + +/** +* \brief Performs range check on Rx floating point formatter configuration settings +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param floatingPointConfig Structure pointer to floating point formatter settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxDataFormatSetFloatingPointRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_FloatingPointConfigSettings_t* floatingPointConfig); + +/** +* \brief Performs range check on Rx integer and slicer format settings +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannelMask channels which need to be configured with floating point rx +* \param formatSelect select from adi_adrv9025_RxDataFormatModes_e +* \param integerConfigSettings Structure pointer to integer formatter config settings +* \param slicerConfigSettings Structure pointer to slicer config settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxDataFormatSetIntegerRangeCheck(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + adi_adrv9025_RxDataFormatModes_e formatSelect, + adi_adrv9025_IntegerConfigSettings_t* integerConfigSettings, + adi_adrv9025_SlicerConfigSettings_t* slicerConfigSettings); + +/** +* \brief Performs range check on Rx embedded overload monitor formatter configuration settings +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param embOvldConfigSettings Structure pointer to embedded overload monitor formatter settings +* \param intSampleResolution Integer sample resolution of the JESD Rx data samples +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxDataFormatSetEmbOvldMonitorRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_EmbOverloadMonitorConfigSettings_t* embOvldConfigSettings, + adi_adrv9025_RxIntSampleResolution_e intSampleResolution); + +/** +* \brief Sets the Rx Data format to floating point format. +* +* Following settings are configured through this function +* -> Floating point data format ({Sign, Exp, Significand} or {Sign, Significand, Exp}) +* -> Floating point round mode +* -> No. of exponent bits +* -> Attenuation step size for the floating point config +* -> Leading one for floating point and NaN encoding +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param floatingPointConfig Structure pointer to floating point formatter settings +* \param rxChannelMask channels which need to be configured with floating point rx +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxDataFormatFloatingPointSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + adi_adrv9025_FloatingPointConfigSettings_t* floatingPointConfig); + +/** +* \brief Returns the Rx Data format floating point format settings. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannel is the channel for which Rx Data Format is requested +* \param floatingPointConfig is the pointer to floating point config which +* is updated with the floating point config readback value +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxDataFormatFloatingPointGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_FloatingPointConfigSettings_t* floatingPointConfig); + +/** +* \brief Sets the Rx Data format to integer and configures slicer settings. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannelMask channels which need to be configured with integer settings requested +* \param formatSelect Integer formatter mode select +* \param integerConfigSettings contains the integer formatter settings for Rx channels requested +* \param slicerConfigSettings contains the integer formatter settings for Rx channels requested +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxDataFormatIntegerSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + adi_adrv9025_RxDataFormatModes_e formatSelect, + adi_adrv9025_IntegerConfigSettings_t* integerConfigSettings, + adi_adrv9025_SlicerConfigSettings_t* slicerConfigSettings); + +/** +* \brief Returns the Rx Data formatter integer and slicer settings. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannel channels which need to be configured with floating point rx +* \param integerConfigSettings Pointer to integer config settings updated with readback value +* \param slicerConfigSettings Pointer to slicer config settings updated with readback value +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxDataFormatIntegerGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_IntegerConfigSettings_t* integerConfigSettings, + adi_adrv9025_SlicerConfigSettings_t* slicerConfigSettings); + +/** +* \brief Sets the Rx Data format to embedded overload indicator format and configures the embedded overload monitor settings. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannelMask Rx channels for which embedded overload indicator format has to be configured +* \param embOvldConfigSettings Structure pointer to embedded overload monitor formatter settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxDataFormatEmbOvldMonitorSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + adi_adrv9025_EmbOverloadMonitorConfigSettings_t* embOvldConfigSettings); + +/** +* \brief Retrieves the Rx embedded overload indicator format settings configured in the device +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannel Rx channel for which embedded overload indicator format has to be retrieved +* \param embOvldConfigSettings Structure pointer to embedded overload monitor formatter settings +* which will be updated with the settings retrieved from the device (output) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxDataFormatEmbOvldMonitorGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_EmbOverloadMonitorConfigSettings_t* embOvldConfigSettings); + +/** +* \brief Sets gain compensation for external LNA gain enable +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannelMask channels which need to be configured with floating point rx +* \param externalLnaGain enable(1) or disable(0) gain compensation to consider LNA gain +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxGainCompExtLnaSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint8_t externalLnaGain); + +/** +* \brief Returns gain compensation for external LNA gain enable status +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannel channels which need to be configured with floating point rx +* \param externalLnaGain returns the current status of external LNA gain comp enable +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxGainCompExtLnaGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint8_t* externalLnaGain); + +/** +* \brief Sets gain compensation for temperature enable +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannelMask channels which need to be configured with floating point rx +* \param tempCompensationEnable enable(1) or disable(0) gain compensation to consider temperature +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxGainCompTempEnableSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint8_t tempCompensationEnable); + +/** +* \brief Returns gain compensation for temperature enable status +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannel channels which need to be configured with floating point rx +* \param tempCompensationEnable returns the current status of temperature gain comp enable +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxGainCompTempEnableGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint8_t* tempCompensationEnable); + +/** +* \brief Returns the Rx Data formatter mode currently configured on ADRV9025 device +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannel Receiver channel for which Rx data format select read back is requested +* \param rxDataFormat output representing currently configured Rx data format +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxDataFormatSelectGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxDataFormatModes_e* rxDataFormat); + +/** +* \brief Resolves the embedded slicer position and no. of embedded slicer bits for integer formatter. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param formatSelect Input parameter conveying the integer format select requested +* \param intEmbeddedBits Enum conveying the embedded bits mode selected +* \param intEmbedSlicer pointer updated with embedded slicer enable/disable +* \param intEmbedSlicerPos pointer updated with embedded slicer position +* \param intEmbedSlicerNumber pointer updated with no. of embedded slicer bits +* \param staticSlicer3bitModeEn pointer updated with the enable value for a 3 bit slicer +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxIntEmbSlicerConfigResolve(adi_adrv9025_Device_t* device, + adi_adrv9025_RxDataFormatModes_e formatSelect, + adi_adrv9025_RxSlicerEmbeddedBits_e intEmbeddedBits, + uint8_t* intEmbedSlicer, + uint8_t* intEmbedSlicerPos, + uint8_t* intEmbedSlicerNumber, + uint8_t* staticSlicer3bitModeEn); + +/** +* \brief Resolves the embedded slicer position and no. of embedded slicer bits for integer formatter. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannel Receiver channel for which Rx data format select read back is requested +* \param intEmbedSlicer embedded slicer enable/disable status read back from ADRV9025 +* \param intEmbedSlicerPos embedded slicer position status read back from ADRV9025 +* \param intEmbedSlicerNumber embedded slicer bits status read back from ADRV9025 +* \param integerConfigSettingsEmbSlicer enum pointer to integer formatter settings updated with +* encoded value for embedded slicer config +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxIntEmbSlicerConfigEncode(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint8_t intEmbedSlicer, + uint8_t intEmbedSlicerPos, + uint8_t intEmbedSlicerNumber, + adi_adrv9025_RxSlicerEmbeddedBits_e* integerConfigSettingsEmbSlicer); + +/** +* \brief Resolves the integer data resolution and format for integer formatter. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param integerConfigSettings Structure pointer to integer formatter settings +* \param intDataResolution pointer updated with integer resolution +* \param intDataFormat pointer updated integer data format (2's complement or signed magnitude) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxIntSampleResFormatResolve(adi_adrv9025_Device_t* device, + const adi_adrv9025_IntegerConfigSettings_t* integerConfigSettings, + uint8_t* intDataResolution, + uint8_t* intDataFormat); + +/** +* \brief Encodes the integer data resolution and format for integer formatter. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param intDataResolution integer resolution of Rx data formatter +* \param intDataFormat integer data format (2's complement or signed magnitude) of Rx Data formatter +* \param intSampleResolution Pointer to integer sample resolution updated with sample resolution +* resolved from intDataResolution and intDataFormat parameters +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxIntSampleResFormatEncode(adi_adrv9025_Device_t* device, + uint8_t intDataResolution, + uint8_t intDataFormat, + adi_adrv9025_RxIntSampleResolution_e* intSampleResolution); + +/** +* \brief Resolves the integer parity support for integer formatter. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param integerConfigSettings Structure pointer to integer formatter settings +* \param intParitySupport pointer updated with integer parity support (enable/disable) +* \param intEvenParity pointer updated integer even/odd parity +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxIntParitySupportResolve(adi_adrv9025_Device_t* device, + const adi_adrv9025_IntegerConfigSettings_t* integerConfigSettings, + uint8_t* intParitySupport, + uint8_t* intEvenParity); + +/** +* \brief Encodes the integer parity support for integer formatter. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannel Receiver channel for which Rx data format select read back is requested +* \param intParitySupport integer parity support (enable/disable) +* \param intEvenParity integer even/odd parity +* \param integerParity Enum pointer to integer formatter parity settings updated +* with value encoded from intParitySupport & intEvenParity parameters +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxIntParitySupportEncode(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint8_t intParitySupport, + uint8_t intEvenParity, + adi_adrv9025_RxIntParity_e* integerParity); + +/** +* \brief Allocates GPIOs for internal slicer ctrl observatio functionality and sets their direction to output. +* Internal slicer ctrl GPIO outputs are mapped to the following GPIOs +* +* === Internal Slicer 4 Pin mode ==== +* rxChannel | ADRV9025 GPIOs set to internal slicer ctrl +* ---------------------|------------------------------------------------------------------------- +* ADI_ADRV9025_RX1 | ADRV9025_GPIO_11, ADRV9025_GPIO_10, ADRV9025_GPIO_09, ADRV9025_GPIO_08 +* ADI_ADRV9025_RX2 | ADRV9025_GPIO_15, ADRV9025_GPIO_14, ADRV9025_GPIO_13, ADRV9025_GPIO_12 +* ADI_ADRV9025_RX3 | ADRV9025_GPIO_07, ADRV9025_GPIO_06, ADRV9025_GPIO_05, ADRV9025_GPIO_04 +* ADI_ADRV9025_RX4 | ADRV9025_GPIO_03, ADRV9025_GPIO_02, ADRV9025_GPIO_01, ADRV9025_GPIO_00 +* +* === Internal Slicer 3 Pin mode ==== +* rxChannel | ADRV9025 GPIOs set to internal slicer ctrl +* ---------------------|------------------------------------------------------------------------- +* ADI_ADRV9025_RX1 | ADRV9025_GPIO_06, ADRV9025_GPIO_07, ADRV9025_GPIO_08 +* ADI_ADRV9025_RX2 | ADRV9025_GPIO_09, ADRV9025_GPIO_10, ADRV9025_GPIO_11 +* ADI_ADRV9025_RX3 | ADRV9025_GPIO_12, ADRV9025_GPIO_13, ADRV9025_GPIO_14 +* ADI_ADRV9025_RX4 | ADRV9025_GPIO_15, ADRV9025_GPIO_16, ADRV9025_GPIO_17 +* +* It has to be noted that no two channels can share the same internal slicer ctrl GPIOs. Furthermore +* it is possible to observe Rx slicer positions only. ORx slicer positions cannot be observed via +* internal slicer observation GPIOs +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param intSlicerFormatSel Internal slicer 3pin / 4 pin mode select +* \param rxChannel Receiver channel for which internal slicer ctrl GPIO observation is required +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxInternalSlicerGpioEnable(adi_adrv9025_Device_t* device, + adi_adrv9025_RxDataFormatModes_e intSlicerFormatSel, + adi_adrv9025_RxChannels_e rxChannel); + +/** +* \brief Reads the GPIO source control register to determine if GPIOs are assigned to internal slicer +* control word observation +* +* === For 4 Pin mode ==== +* rxChannel | ADRV9025 GPIOs set to internal slicer ctrl +* ---------------------|------------------------------------------------------------------------- +* ADI_ADRV9025_RX1 | gpio_upper_byte_lower_nibble_source_control = 0x0A +* ADI_ADRV9025_RX2 | gpio_upper_byte_upper_nibble_source_control = 0x0A +* ADI_ADRV9025_RX3 | gpio_lower_byte_upper_nibble_source_control = 0x0A +* ADI_ADRV9025_RX4 | gpio_lower_byte_lower_nibble_source_control = 0x0A +* +* === For 3 Pin mode ==== +* rxChannel | ADRV9025 GPIOs set to internal slicer ctrl +* ---------------------|------------------------------------------------------------------------- +* ADI_ADRV9025_RX1 | gpio_upper_byte_lower_nibble_source_control, gpio_lower_byte_upper_nibble_source_control = 0x0B +* ADI_ADRV9025_RX2 | gpio_upper_byte_lower_nibble_source_control = 0x0B +* ADI_ADRV9025_RX3 | gpio_upper_byte_upper_nibble_source_control = 0x0B +* ADI_ADRV9025_RX4 | gpio_upper_byte_upper_nibble_source_control, gpio_extra_bits_source_control = 0x0B +* +* ORx slicer positions cannot be observed via internal slicer observation GPIOs +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannel Receiver channel for which internal slicer ctrl GPIO observation is required +* \param intSlicerFormatSel Pointer to an Rx data format select enum which will be updated with the active Internal Slicer format in the device. +* This param is only valid if enableStatus is set to 1. +* \param enableStatus output flag indicating if the requested channel has it's slicer control +* word routed to observation GPIOs based on GPIO source ctrl readback +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxInternalSlicerGpioEnableGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxDataFormatModes_e* intSlicerFormatSel, + uint8_t* enableStatus); + +/** +* \brief Sets GPIO source ctrl assigned for internal slicer ctrl observation functionality +* and sets their direction to input. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannel Receiver channel for which internal slicer ctrl GPIO observation is required to be disabled +* \param intSlicerFormatSel The target internal slicer mode to disable (3pin or 4pin mode) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxInternalSlicerGpioDisable(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxDataFormatModes_e intSlicerFormatSel); + +/** +* \brief Allocates GPIOs for external slicer ctrl functionality and sets their direction to input. +* External ctrl GPIOs can be set to one of the following +* +* slicerConfigSettings->rx(n)ExtSlicerGpioSelect | ADRV9025 GPIOs set to external slicer ctrl +* -----------------------------------------------|------------------------------------------------------- +* ADI_ADRV9025_EXTSLICER_RX_GPIO_2_DOWNTO_0 | ADRV9025_GPIO_00, ADRV9025_GPIO_01, ADRV9025_GPIO_02 +* ADI_ADRV9025_EXTSLICER_RX_GPIO_5_DOWNTO_3 | ADRV9025_GPIO_03, ADRV9025_GPIO_04, ADRV9025_GPIO_05 +* ADI_ADRV9025_EXTSLICER_RX_GPIO_8_DOWNTO_6 | ADRV9025_GPIO_06, ADRV9025_GPIO_07, ADRV9025_GPIO_08 +* ADI_ADRV9025_EXTSLICER_RX_GPIO_11_DOWNTO_9 | ADRV9025_GPIO_09, ADRV9025_GPIO_10, ADRV9025_GPIO_11 +* ADI_ADRV9025_EXTSLICER_RX_GPIO_14_DOWNTO_12 | ADRV9025_GPIO_12, ADRV9025_GPIO_13, ADRV9025_GPIO_14 +* ADI_ADRV9025_EXTSLICER_RX_GPIO_17_DOWNTO_15 | ADRV9025_GPIO_15, ADRV9025_GPIO_16, ADRV9025_GPIO_17 +* +* It has to be noted that no two channels can share the same external slicer ctrl GPIOs +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param slicerConfigSettings Structure pointer to slicer configuration settings +* \param rxChannel Receiver channel for which external slicer ctrl is being rebuilt for +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxExternalSlicerGpioEnable(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + const adi_adrv9025_SlicerConfigSettings_t* slicerConfigSettings); + +/** +* \brief Clears GPIO select assigned for external slicer ctrl functionality +* and sets the external slicer ctrl GPIO direction to input. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannel Receiver channel for which internal slicer ctrl GPIO observation is required to be disabled +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxExternalSlicerGpioDisable(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel); + +/** +* \brief Disables gain compensation for the requested Rx Channels +* +* Please note that even though gain compensation is disabled, +* the embedded slicer bits have to be explicitly set to 0 failing +* which the received data will contain slicer bits if it was previously +* enabled. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannelMask specifies the channels for which gain compensation is to be disabled +* \param intDataFormat integer data format on disabling gain compensation (2s complement vs signed) +* \param intDataResolution integer data resolution (12/16/24 bit) on disabling gain compensation +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxDataFormatGainCompDisable(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint8_t intDataFormat, + uint8_t intDataResolution); + +/** +* \brief Performs range check on adi_adrv9025_RxDecPowerGet() API. +* +* \pre This function is called automatically as part of adi_adrv9025_RxDecPowerGet() +* function if ADI_ADRV9025_RX_RANGE_CHECK > 0. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param rxChannel Channel selection to read back gain index for (Valid Rx1-Rx4, ORx1-ORx4 only) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxDecPowerGetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel); + +/** +* \brief This function performs range check on the parameters for adrv9025_RxLoSourceGet API. +* +* This function verifies that the requested Rx channel is valid and that it is initialized +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxChannel Enum to select Rx Channel. +* \param rxLoSource Pointer to store Rx channel LO source mapping read back (Output) +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxLoSourceGetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_LoSel_e* rxLoSource); + +/** +* \brief This function reads back the LO Source Mapping to the requested Rx channel. +* +* The LO source select for a given channel is configured during init time. This function +* can be used to read back the configuration during run time. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxChannel Enum to select Rx Channel. +* \param rxLoSource Pointer to store Rx channel LO source mapping read back (Output) +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxLoSourceGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_LoSel_e* rxLoSource); + +/** +* \brief This function reads back the LO Source Mapping to the requested ORx channel. +* +* The LO source select for a given channel is configured during init time. This function +* can be used to read back the configuration during run time. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxChannel Enum to select ORx Channel. +* \param rxLoSource Pointer to store ORx channel LO source mapping read back (Output) +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_OrxLoSourceGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_LoSel_e* rxLoSource); + +/** +* \brief This function sets a dummy value to the agc_gain_index so it can latch. +* +* When agc_enable_gain_index_update is set to one, then agc_gain_index will not +* have valid data unless you write a dummy value to it first so that it latches. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9010 device data structure +* \param rxChannelBitFieldAddr Enum to select Rx Channel. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RxAgcEnableGainIndexUpdateLatch(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e rxChannelBitFieldAddr); + +/** +* \brief This function sets a dummy value to the agc_gain_index for Orx1 so it can latch. +* +* When agc_enable_gain_index_update is set to one, then agc_gain_index will not +* have valid data unless you write a dummy value to it first so that it latches. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9010 device data structure +* \param rxChannelBitFieldAddr Enum to select Rx Channel. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_OrxOrx1AgcEnableGainIndexUpdateLatch(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e orxChannelBitFieldAddr); + +/** +* \brief This function sets a dummy value to the agc_gain_index for Orx2 so it can latch. +* +* When agc_enable_gain_index_update is set to one, then agc_gain_index will not +* have valid data unless you write a dummy value to it first so that it latches. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9010 device data structure +* \param rxChannelBitFieldAddr Enum to select Rx Channel. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_OrxOrx2AgcEnableGainIndexUpdateLatch(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e orxChannelBitFieldAddr); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_shared_resource_manager.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_shared_resource_manager.h new file mode 100644 index 0000000..7564573 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_shared_resource_manager.h @@ -0,0 +1,270 @@ +/** +* \file adrv9025_shared_resource_manager.h +* \brief Contains ADRV9025 shared resource related private function prototypes for +* adrv9025_shared_resource_manager.c +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADRV9025_SHARED_RESOURCE_MANAGER_H_ +#define _ADRV9025_SHARED_RESOURCE_MANAGER_H_ + +#include "../../private/include/adrv9025_shared_resource_manager_types.h" +#include "adi_adrv9025_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Resets the shared resource pool for a given adrv9025 device +* +* Each shared resource is associated with a feature. On reset, all the +* shared resources are assigned to 'UNUSED' and are ready for use by a given feature. +* +* \pre This function is required to be called during initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the adrv9025 device data structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_SharedResourceMgrReset(adi_adrv9025_Device_t* device); + +/** +* \brief Returns if a requested shared resource is available for use +* +* Each shared resource is associated with a feature. Returns a success if the shared resource +* is unused and a failure if already in use. +* +* \pre This function is a private function used internally by the API and can be called +* anytime after initialization by the API to test shared resource availability +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the adrv9025 device data structure +* \param sharedResourceID is the shared resource whose availability is being enquired +* \param sharedResourceAvailable result - ADI_TRUE or ADI_FALSE is returned depending +* on availability of shared resource +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_SharedResourceAvailabilityCheck(adi_adrv9025_Device_t* device, + adrv9025_SharedResourceID_e sharedResourceID, + uint8_t* sharedResourceAvailable); + +/** +* \brief Returns the shared resource ID for a shared resource +* +* \pre This function is a private function used internally by the API and can be called +* anytime after initialization by the API to test shared resource availability +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the adrv9025 device data structure +* \param sharedResourceType is the shared resource type(GPIO, MEMORY etc) for which ID is being requested +* \param sharedResource is typically the enum value of the shared resource for which ID is being requested +* \param sharedResourceID result shared resource ID is updated in this variable +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_SharedResourceIdGet(adi_adrv9025_Device_t* device, + adrv9025_SharedResourceType_e sharedResourceType, + int32_t sharedResource, + adrv9025_SharedResourceID_e* sharedResourceID); + +/** +* \brief Returns the feature currently consuming the shared resource. +* +* Each shared resource is associated with a feature in the resource pool. +* This function returns the feature currently associated with the shared resource +* +* \pre This function is a private function used internally by the API and can be called +* anytime after initialization by the API to enquire shared +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the adrv9025 device data structure +* \param sharedResourceID is the shared resource whose availability is under query +* \param featureID pointer to the feature associated with the requested shared resrouce ID +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_SharedResourceFeatureGet(adi_adrv9025_Device_t* device, + adrv9025_SharedResourceID_e sharedResourceID, + adrv9025_FeatureID_e* featureID); + +/** +* \brief Returns the maximum semaphore count for a given feature. +* +* Each shared resource is associated with a feature in the resource pool. +* Some features share the shared resource with multiple consumers necessitating +* a semaphore associated with each feature. This function can be used to enquire +* the maximum semaphore count associated with the feature. +* +* \pre This function is a private function used internally by the API and can be called +* anytime after initialization by the API to enquire the maximum semaphore count associated +* with a feature +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the adrv9025 device data structure +* \param featureID The feature ID for which the maximum semaphore count is requested +* \param maxSemaphoreCount Pointer to the max semaphore count variable which will be updated +* with the maximum semaphore count for a given feature. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_SharedResourceFeatureMaxSemaphoreCntGet(adi_adrv9025_Device_t* device, + adrv9025_FeatureID_e featureID, + uint8_t* maxSemaphoreCount); + +/** +* \brief Attempts to acquire the requested shared resource for a requested from the +* adrv9025 device data structure shared resource pool +* +* \pre This function is a private function used internally by the API and can be called +* anytime after initialization by the API to acquire a shared resource +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the adrv9025 device data structure +* \param sharedResourceID is the shared resource whose availability is under query +* \param featureID feature requesting the shared resource +* \param resourceAcquistionStatus stores ADI_SUCCESS if resrouce acquisition was successful, +* ADI_FAILURE otherwise +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_SharedResourceAcquire(adi_adrv9025_Device_t* device, + adrv9025_SharedResourceID_e sharedResourceID, + adrv9025_FeatureID_e featureID, + uint8_t* resourceAcquistionStatus); + +/** +* \brief Attempts to acquire multiple shared resources for a requested feature from the +* adrv9025 device data structure shared resource pool +* +* This function returns a failure even if a single resource acquisition fails +* +* \pre This function is a private function used internally by the API and can be called +* anytime after initialization by the API to acquire multiple shared resources for +* the same feature +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the adrv9025 device data structure +* \param sharedResourceType is the enum of the shared resource type to be acquired +* \param sharedResourceArr is the array of shared resources to be acquired +* \param numSharedResources is the size of sharedResourceArr +* \param featureID feature requesting the shared resource +* \param resourceAcquistionStatus stores ADI_SUCCESS if resrouce acquisition was successful, +* ADI_FAILURE otherwise +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_SharedResourcesAcquire(adi_adrv9025_Device_t* device, + adrv9025_SharedResourceType_e sharedResourceType, + int32_t sharedResourceArr[], + uint32_t numSharedResources, + adrv9025_FeatureID_e featureID, + uint8_t* resourceAcquistionStatus); + +/** +* \brief Attempts to release the shared resource under consumption by the given feature +* +* \pre This function is a private function used internally by the API and can be called +* anytime after initialization by the API to test shared resource availability +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the adrv9025 device data structure +* \param sharedResourceID is the shared resource whose availability is under query +* \param featureID feature requesting the shared resource +* \param resourceReleaseStatus stores ADI_SUCCESS if resrouce release was successful, +* ADI_FAILURE otherwise +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_SharedResourceRelease(adi_adrv9025_Device_t* device, + adrv9025_SharedResourceID_e sharedResourceID, + adrv9025_FeatureID_e featureID, + uint8_t* resourceReleaseStatus); + +/** +* \brief Attempts to release multiple shared resources for a requested feature from the +* adrv9025 device data structure shared resource pool +* +* This function returns a failure even if a single resource release fails +* +* \pre This function is a private function used internally by the API and can be called +* anytime after initialization by the API to release multiple shared resources for +* the same feature +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the adrv9025 device data structure +* \param sharedResourceType is the enum of the shared resource type to be released +* \param sharedResourceArr is the array of shared resources to be acquired +* \param numSharedResources is the size of sharedResourceArr +* \param featureID feature requesting the shared resource +* \param resourceReleaseStatus stores ADI_SUCCESS if resource release was successful, +* ADI_FAILURE otherwise +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_SharedResourcesRelease(adi_adrv9025_Device_t* device, + adrv9025_SharedResourceType_e sharedResourceType, + int32_t sharedResourceArr[], + uint32_t numSharedResources, + adrv9025_FeatureID_e featureID, + uint8_t* resourceReleaseStatus); + +#ifdef __cplusplus +} +#endif + +#endif /* ! _ADRV9025_SHARED_RESOURCE_MANAGER_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_shared_resource_manager_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_shared_resource_manager_types.h new file mode 100644 index 0000000..6e3fa9e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_shared_resource_manager_types.h @@ -0,0 +1,134 @@ +/** + * \file adrv9025_shared_resource_manager_types.h + * \brief Contains ADRV9025 shared resource related private data prototypes for + * adrv9025_shared_resource_manager.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + + /** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADRV9025_SHARED_RESOURCE_MANAGER_TYPES_H_ +#define _ADRV9025_SHARED_RESOURCE_MANAGER_TYPES_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADI_ADRV9025_NUM_GPIOS_IN_AGCOOVERLOADINDICATOR_FEATURE 12 + +/* Macros defining the maximum semaphore count for a given feature */ +#define ADRV9025_FEATURE_RX_GAIN_CTRL_PIN_MAX_SEMAPHORE_COUNT 4 +#define ADRV9025_FEATURE_RX_PIN_CTRL_ATTN_MAX_SEMAPHORE_COUNT 4 +#define ADRV9025_FEATURE_RX_EXT_CTRL_WORD_OUTPUT_MAX_SEMAPHORE_COUNT 1 +#define ADRV9025_FEATURE_RX_DUALBAND_LNA_CTRL_WORD_OUTPUT_MAX_SEMAPHORE_COUNT 1 +#define ADRV9025_FEATURE_TX_ATTEN_CTRL_PIN_MAX_SEMAPHORE_COUNT 4 +#define ADRV9025_FEATURE_TX_ATTEN_UPDATE_PIN_MAX_SEMAPHORE_COUNT 4 +#define ADRV9025_FEATURE_SPI2_CTRL_PIN_MAX_SEMAPHORE_COUNT 1 +#define ADRV9025_FEATURE_RX_EXT_SLICER_CTRL_MAX_SEMAPHORE_COUNT 4 +#define ADRV9025_FEATURE_RX_INT_SLICER_CTRL_OUT_MAX_SEMAPHORE_COUNT 1 +#define ADRV9025_FEATURE_AUX_DAC_OUT_MAX_SEMAPHORE_COUNT 1 +#define ADRV9025_FEATURE_GPIO_STREAM_TRIGGER_MAX_SEMAPHORE_COUNT 1 +#define ADRV9025_FEATURE_FOVR_MAX_SEMAPHORE_COUNT 1 +#define ADRV9025_FEATURE_PCA_MAX_SEMAPHORE_COUNT 4 +#define ADRV9025_FEATURE_RX_DUALBAND_CTRL_OUTPUT_MAX_SEMAPHORE_COUNT 1 +#define ADRV9025_FEATURE_ARM_GPIO_PIN_MAX_SEMAPHORE_COUNT 1 +#define ADRV9025_FEATURE_EXT_DPD_CAPTURE_DONE_PIN_MAX_SEMAPHORE_COUNT 1 +#define ADRV9025_FEATURE_ADC_OVERLOAD_INDICATION_TO_GPIOS_OUT_MAX_SEMAPHORE_COUNT 11 +#define ADRV9025_FEATURE_SYNC_AGC_PIN_COUNT 1 +/*** Please add shared resource maximum semaphore count above this line ****/ + +typedef enum adrv9025_SharedResourceType +{ + ADRV9025_SHARED_RESOURCE_GPIO = 0, /*!< Select GPIO as the Shared Resource type*/ + ADRV9025_SHARED_RESOURCE_GPIO_ANALOG = 1, /*!< Select GPIO Analog as the Shared Resource type*/ + /***Please add shared resource type above this line****/ + ADRV9025_NUM_SHARED_RESOURCE_TYPES +} adrv9025_SharedResourceType_e; + +typedef enum adrv9025_SharedResourceID +{ + /******START OF GPIO********/ + ADRV9025_GPIO_00 = 0, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_00*/ + ADRV9025_GPIO_01, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_01*/ + ADRV9025_GPIO_02, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_02*/ + ADRV9025_GPIO_03, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_03*/ + ADRV9025_GPIO_04, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_04*/ + ADRV9025_GPIO_05, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_05*/ + ADRV9025_GPIO_06, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_06*/ + ADRV9025_GPIO_07, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_07*/ + ADRV9025_GPIO_08, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_08*/ + ADRV9025_GPIO_09, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_09*/ + ADRV9025_GPIO_10, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_11*/ + ADRV9025_GPIO_11, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_12*/ + ADRV9025_GPIO_12, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_13*/ + ADRV9025_GPIO_13, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_14*/ + ADRV9025_GPIO_14, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_15*/ + ADRV9025_GPIO_15, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_16*/ + ADRV9025_GPIO_16, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_17*/ + ADRV9025_GPIO_17, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_18*/ + ADRV9025_GPIO_18, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_19*/ + /******START OF GPIO Analog********/ + ADRV9025_GPIO_ANA_00, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_ANA_00*/ + ADRV9025_GPIO_ANA_01, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_ANA_01*/ + ADRV9025_GPIO_ANA_02, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_ANA_02*/ + ADRV9025_GPIO_ANA_03, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_ANA_03*/ + ADRV9025_GPIO_ANA_04, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_ANA_04*/ + ADRV9025_GPIO_ANA_05, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_ANA_05*/ + ADRV9025_GPIO_ANA_06, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_ANA_06*/ + ADRV9025_GPIO_ANA_07, /*!< Unique Shared Resource ID for ADI_ADRV9025_GPIO_ANA_07*/ + /***Please add shared resources above this line***/ + ADRV9025_NUM_SHARED_RESOURCES, + ADRV9025_SHARED_RESOURCE_INVALID +} adrv9025_SharedResourceID_e; + +typedef enum adrv9025_FeatureID +{ + ADRV9025_FEATURE_UNUSED = 0, /*!< Default feature ID associated with a shared resource when unused*/ + ADRV9025_FEATURE_RX_GAIN_CTRL_PIN, /*!< Associates Rx Gain Ctrl Pin feature with a shared resource*/ + ADRV9025_FEATURE_RX_PIN_CTRL_ATTN, /*!< Associates Rx Parallel Pin Ctrl Attenuation feature with a shared resource*/ + ADRV9025_FEATURE_RX_EXT_CTRL_WORD_OUTPUT, /*!< Associates Rx External Ctrl Word Output feature with a shared resource*/ + ADRV9025_FEATURE_RX_DUALBAND_LNA_CTRL_WORD_OUTPUT, /*!< Associates Rx Dualband LNA Ctrl Word Output feature with a shared resource*/ + ADRV9025_FEATURE_TX_ATTEN_CTRL_PIN, /*!< Associates Tx Attenuation Ctrl Pin feature with a shared resource*/ + ADRV9025_FEATURE_SPI2_CTRL_PIN, /*!< Associates SPI2 Ctrl Pin feature with a shared resource */ + ADRV9025_FEATURE_ARM_GPIO_PIN, /*!< Associates ARM TDD Ctrl feature with a shared resource */ + ADRV9025_FEATURE_RX_EXT_SLICER_CTRL, /*!< Associates Rx External Slicer Ctrl Word Input feature with a shared resource*/ + ADRV9025_FEATURE_RX_INT_SLICER_CTRL_OUT, /*!< Associates Rx Internal Slicer Ctrl Word Input feature with a shared resource*/ + ADRV9025_FEATURE_AUX_DAC_OUT, /*!< Associates AuxDAC feature with a shared resource*/ + ADRV9025_FEATURE_GPIO_STREAM_TRIGGER, /*!< Associates GPIO stream trigger mapping feature with a shared resource*/ + ADRV9025_FEATURE_FOVR, /*!< Associates FOVR mapping feature with a shared resource*/ + ADRV9025_FEATURE_PCA, /*!< Associates PCA mapping feature with a shared resource*/ + ADRV9025_FEATURE_RX_DUALBAND_CTRL_OUTPUT, /*!< Associates Rx Dualband Ctrl Word Output feature with a shared resource*/ + ADRV9025_FEATURE_TX_ATTEN_UPDATE_PIN, /*!< Associates Tx Attenuation Update Pin feature with a shared resource*/ + ADRV9025_FEATURE_EXT_DPD_CAPTURE_DONE_PIN, /*!< Associates External DPD capture done indication GPIO feature with a shared resource*/ + ADRV9025_FEATURE_ADC_OVERLOAD_INDICATION, /*!< Associates Rx Overload feature with a shared resource */ + ADRV9025_FEATURE_RX_AGC_HYBRID_MODE, /*!< Associates Rx AGC Hybrid mode feature with a shared resource */ + /*** Please add Feature IDs which use shared resources above this line ***/ + ADRV9025_NUM_FEATURES, + ADRV9025_FEATURE_INVALID +} adrv9025_FeatureID_e; + +typedef struct adrv9025_SharedResourceLut +{ + adrv9025_SharedResourceType_e sharedResourceType; /*!< Specifies the type of shared resource for a Look Up Table entry*/ + int32_t sharedResource; /*!< Specifies the shared resource value associated with the type for a Look Up Table entry*/ + adrv9025_SharedResourceID_e sharedResourceId; /*!< Specifies the unique shared resource ID associated with the shared resource for a Look Up Table entry*/ +} adrv9025_SharedResourceLut_t; + +typedef struct adrv9025_SharedResourcePool +{ + adrv9025_FeatureID_e featureID; /*!< Holds the feature ID of a shared resource pool member */ + uint8_t semaphoreCount; /*!< Holds the semaphore count of a shared resource pool member */ +} adrv9025_SharedResourcePool_t; + +#ifdef __cplusplus +} +#endif + +#endif /* ! _ADRV9025_SHARED_RESOURCE_MANAGER_TYPES_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_tx.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_tx.h new file mode 100644 index 0000000..70eede8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_tx.h @@ -0,0 +1,381 @@ +/** +* \file adrv9025_tx.h +* \brief Contains ADRV9025 transmit related function prototypes for +* adrv9025_tx.c which helps adi_adrv9025_tx.c +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADRV9025_TX_H_ +#define _ADRV9025_TX_H_ + +#include "adi_adrv9025_tx.h" +#include "../../private/include/adrv9025_bf_tx.h" +#include "../../private/include/adrv9025_reg_addr_macros.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Returns the Tx SPI channel base addresses for a given Tx Channel +* +* \param device Pointer to the device settings structure +* \param channelMask is the channel for which Tx base address is requested +* +* \retval uint16_t Return Base Address for Tx channel +*/ +uint16_t adrv9025_TxAddrDecode(adi_adrv9025_Device_t* device, + uint32_t channelMask); + +/** +* \brief Returns the Tx Dac SPI channel base addresses for a given Tx Channel +* +* \param device Pointer to the device settings structure +* \param channelMask is the channel for which Tx base address is requested +* +* \retval Return Base Address for Tx channel +*/ +uint16_t adrv9025_TxDacAddrDecode(adi_adrv9025_Device_t* device, + uint32_t channelMask); + +/** +* \brief Returns the Tx SPI channel base addresses for a given Tx Channel +* +* \param device Pointer to the device settings structure +* \param channelMask is the channel for which Tx base address is requested +* +* \retval uint32_t Return Base Address for Tx channel +*/ +uint32_t adrv9025_txAttenAddrLookup(adi_adrv9025_Device_t* device, + uint32_t channelMask); + +/** +* \brief +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device +* \param sharedResourceArr +* \param recoveryAction +* \param customError +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxAttenCtrlPinReportError(adi_adrv9025_Device_t* device, + int32_t sharedResourceArr[], + int32_t recoveryAction, + const char* customError); + +/** +* \brief +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device +* \param sharedResourceArr +* \param recoveryAction +* \param customError +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxAttenSpi2CtrlPinReportError(adi_adrv9025_Device_t* device, + int32_t sharedResourceArr[], + int32_t recoveryAction, + const char* customError); + +/** +* \brief Performs a range check on the GPIO mode attenuation control config +* +* This API function checks that: +* -The GPIO pins are in the range GPIO[15:0] +* -Increment and decrement steps are in the range 0-31 +* -Increment and decrement are not sharing the same GPIO pin +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param txAttenPinCtrlCfg Pointer to a adi_adrv9025_TxAttenPinCfg_t structure that +* configures the Tx attenuation pin control. +* +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxAttenPinCtrlCfgSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_TxAttenPinCfg_t* txAttenPinCtrlCfg); + +/** +* \brief Performs a range check on the attenuation mode set parameters + +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param txAttenMode Selected attenuation mode to be checked +* \param simultaneousUpdateCfg Selected simultaneous update config struct to be checked +* \param gpioModePinCfg Selected gpio config struct to be checked +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxAttenModeSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_TxAttenMode_e txAttenMode, + adi_adrv9025_TxAttenSimultUpdateCfg_t simultaneousUpdateCfg, + adi_adrv9025_TxAttenPinCfg_t gpioModePinCfg); + +/** +* \brief Performs a range check on the attenuation control config +* +* This API function checks that: +* -The channel mask, Attenuation step size, dacScale and attenMode are in range +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param txAttenCfg Pointer to a adi_adrv9025_TxAttenCfg_t structure that +* configures the Tx attenuation. +* +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxAttenCfgSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_TxAttenCfg_t* txAttenCfg); + +/** +* \brief * +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param txToneCfg Pointer to a adi_adrv9025_TxTestToneCfg_t structure that +* configures the Tx Test tone. +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxTestToneCfgSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_TxTestToneCfg_t* txToneCfg); + +/** +* \brief Configures one or more TX FIR filters in the device +* +* The device stores 1 Tx filter per channel. +* Tx filters can have 20, 40, 60, or 80 taps. +* +* The function is not called directly. It is called as a part of the adi_adrv9025_initialize() function. +* The function could be used to change A FIR filter later, but would require calibrations to be rerun. +* +* \pre This function is called during device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param txChanMask One or more TX Channel from adi_adrv9025_TxChannels_e. +* \param gain_dB The gain_dB value (-12, -6, 0, 6). +* \param numFirCoefs The number of Fir Coefs in coefs array (20, 40, 60, 80). +* \param coefs[] Pointer to coefs array +* \param arraySize The size of coefs array +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxFirWrite(adi_adrv9025_Device_t* device, + uint32_t txChanMask, + int8_t gain_dB, + uint8_t numFirCoefs, + int16_t coefs[], + uint8_t arraySize); + +/** +* \brief Checks whether the pa protection configuration values are within valid range. +* +* \param device Pointer to the ADRV9025 data structure +* \param txPaProtectCfg pointer to the structure that is going to be checked +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxPaProtectCfgRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_TxPaProtectCfg_t* txPaProtectCfg); + +/** +* \brief This API function will check the Tx RF output attenuation table for each Tx output channel +* +* txAttenTableRows->txAttenMult: Tx Atten Multi, set to (0-4095) from table. set to max value if not in table. +* txAttenTableRows->txAttenHp : Tx Atten HP, set to (0 - 63) from table. Set to max value if not in table. +* +* The full TxAtten table can be loaded in a single call. +* Or the table can be loaded in several calls, loading a subset of the table with each function call using the txAttenIndexOffset parameter. +* +* \pre This function may be called any time after device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device's data structure +* \param txChannelMask The Mask of one or more Tx Channels +* \param txAttenIndexOffset Offset of the TxAttentable in the Device from the minimum index (0 - 1023). +* \param txAttenTableRows The Array contain TxAttenTableRows +* \param numTxAttenEntries The number of elements in the TxAttenTableRows array (1 - 1024). +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxAttenTableWriteRangeCheck(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + uint32_t txAttenIndexOffset, + adi_adrv9025_TxAttenTableRow_t txAttenTableRows[], + uint32_t numTxAttenEntries); + +/** +* \brief This function performs range check on the parameters for adrv9025_TxLoSourceGet API. +* +* This function verifies that the requested Tx channel is valid and that it is initialized +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannel Enum to select Tx Channel. +* \param txLoSource Pointer to store Tx channel LO source mapping read back (Output) +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxLoSourceGetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_LoSel_e* txLoSource); + +/** +* \brief This function reads back the LO Source Mapping to the requested Tx channel. +* +* The LO source select for a given channel is configured during init time. This function +* can be used to read back the configuration during run time. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannel Enum to select Tx Channel. +* \param txLoSource Pointer to store Tx channel LO source mapping read back (Output) +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxLoSourceGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_LoSel_e* txLoSource); + +/** +* \brief Configures GPIO pin for Tx attenuation simultaneous update for given Tx channel address +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param txChannelBaseAddr Base address of Tx channel to be configured +* \param gpioSelection Gpio selection for Tx simultaneous update +* \param releaseCurrentPin 0: Don't release current pin, Other: Release current pin +* \param acquireNewPin 0: Don't acquire new pin, Other: Acquire new pin +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxAttenUpdateGpioPinCtrlCfgSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e txChannelBaseAddr, + adi_adrv9025_GpioPinSel_e gpioSelection, + uint8_t releaseCurrentPin, + uint8_t acquireNewPin); + +/** +* \brief Configures GPIO pins for Tx attenuation GPIO control for given Tx channel address +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param txChannelBaseAddr Base address of Tx channel to be configured +* \param txAttenPinCfg Gpio attenuation control configuration structure to be written +* \param releaseCurrentPins 0:Don't release current pins // Other:Release current pins +* \param acquireNewPins 0:Don't acquire new pins // Other:Acquire pins +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxAttenPinCtrlCfgSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e txChannelBaseAddr, + adi_adrv9025_TxAttenPinCfg_t txAttenPinCfg, + uint8_t releaseCurrentPins, + uint8_t acquireNewPins); + +/** +* \brief This function sets master enable bits ('tx_data_ramp_down_on_pll_unlock' and 'tx_data_ramp_down_on_jesd_dfrm_irq') + of Pll Unlock and Jesd Dfrm Tx ramp down functionality for selected Tx channel. It masks all the ramp down events + and unmasks the ones selected through txRampDownInitCfg. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txRampDownInitCfg Init time Tx ramp down configuration populated from init struct. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_TxRampDownInit(adi_adrv9025_Device_t* device, + adi_adrv9025_TxRampDownInitCfg_t* txRampDownInitCfg); + +#ifdef __cplusplus +} +#endif + +#endif /*__ADRV9025_TX_H__ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_utilities.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_utilities.h new file mode 100644 index 0000000..53aaed6 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/include/adrv9025_utilities.h @@ -0,0 +1,734 @@ +/** +* \file adrv9025_utilities.h +* \brief Contains Utility features related private function definitions +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADRV9025_UTILITIES_H_ +#define _ADRV9025_UTILITIES_H_ + +#include "adi_adrv9025_utilities_types.h" + +#define ADRV9025_MAX_FILE_BUFFER 128 + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief This utility function initializes radioctrl parameters +* +* This function performs the following +* -> Sets up the ARM GPIO Pins +* -> Sets up the Radio Ctrl Mode (Pin or SPI mode) for signal chain enable/disable +* -> Initializes PLL frequencies +* -> Enables/Disables Rx and Tx signal chains(only applicable for SPI mode) +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param radioCtrlInit Pointer to ADRV9025 Radioctrl init settings structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_RadioctrlInit(adi_adrv9025_Device_t* device, + adi_adrv9025_RadioctrlInit_t* radioCtrlInit); + +/** +* \brief This utility function commands the ARM processor to run init cals +* +* The init cals to run are communicated via a mask passed to this function +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param initCals Pointer to ADRV9025 cals init settings structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_CalsInit(adi_adrv9025_Device_t* device, + adi_adrv9025_InitCals_t* initCals); + +/** +* \brief This utility function initialize the ADC Profiles +* +* The ADC profiles is initialize using fix profile with ADC bandwidth and ADC clock. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param init Pointer to ADRV9025 init settings structure +* \param adcProfile Pointer to ADRV9025 ADC profile settings structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_AdcProfilesInit(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init, + adi_adrv9025_AdcProfiles_t* adcProfile); + +/** +* \brief Parses SPI init settings from a JSON file +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param spiSettings Pointer to ADRV9025 init SPI settings structure +* \param fp FILE pointer to the JSON file containing init settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseInitSpiSettings(adi_adrv9025_Device_t* device, + adi_adrv9025_SpiSettings_t* spiSettings, + FILE* fp); + +/** +* \brief Parses clock init settings from a JSON file +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param clockSettings Pointer to ADRV9025 init clock settings structure +* \param fp FILE pointer to the JSON file containing init settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseInitClockSettings(adi_adrv9025_Device_t* device, + adi_adrv9025_ClockSettings_t* clockSettings, + FILE* fp); + +/** +* \brief Parses Rx init settings from a JSON file +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param rxSettings Pointer to ADRV9025 init Rx settings structure +* \param fp FILE pointer to the JSON file containing init settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseInitRxSettings(adi_adrv9025_Device_t* device, + adi_adrv9025_RxSettings_t* rxSettings, + FILE* fp); + +/** +* \brief Parses Tx init settings from a JSON file +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param txSettings Pointer to ADRV9025 init Tx settings structure +* \param fp FILE pointer to the JSON file containing init settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseInitTxSettings(adi_adrv9025_Device_t* device, + adi_adrv9025_TxSettings_t* txSettings, + FILE* fp); + +/** +* \brief Parses Rx ADC Profiles init settings from a JSON file +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param adcProfies Pointer to ADRV9025 Adc Profiles structure +* \param fp FILE pointer to the JSON file containing init settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ + int32_t adrv9025_JsonParseInitAdcProfileSettings(adi_adrv9025_Device_t* device, + adi_adrv9025_AdcProfiles_t* adcProfiles, + FILE* fp); + +/** +* \brief Parses Datapath(JESD) init settings from a JSON file +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param dataPathSettings Pointer to ADRV9025 init datapath settings structure +* \param fp FILE pointer to the JSON file containing init settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseInitDataInterfaceSettings(adi_adrv9025_Device_t* device, + adi_adrv9025_DataInterfaceCfg_t* dataPathSettings, + FILE* fp); + +/** +* \brief Parses GP Interrupt mask init settings from a JSON file +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param GpInterruptSettings Pointer to ADRV9025 init GP Interrupt init settings structure +* \param fp FILE pointer to the JSON file containing init settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseInitGpInterruptSettings(adi_adrv9025_Device_t* device, + adi_adrv9025_GpInterruptSettings_t* gpInterruptSettings, + FILE* fp); + +/** +* \brief Parses RadioCtrl settings from a JSON file +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param radioCtrlInit Pointer to ADRV9025 radio control structure +* \param fp FILE pointer to the JSON file containing init settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseUtilRadioctrlInit(adi_adrv9025_Device_t* device, + adi_adrv9025_RadioctrlInit_t* radioCtrlInit, + FILE* fp); + +/** +* \brief Parses InitCals settings from a JSON file +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param initCals Pointer to ADRV9025 init cals structure +* \param fp FILE pointer to the JSON file containing init settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseUtilInitCals(adi_adrv9025_Device_t* device, + adi_adrv9025_InitCals_t* initCals, + FILE* fp); + +/** +* \brief Finds the Start of JSON file to parse +* +* The start of file is usually an open curly brace "{" +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param objNameStr Expected object name +* \param currChar Pointer to index location of the string to parse +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonFindStartOfFile(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar); + +/** +* \brief Finds the End of JSON file currently being parsed +* +* The start of file is usually a closed curly brace "}" +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param objNameStr Expected object name +* \param currChar Pointer to index location of the string to parse +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonFindEndOfFile(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar); + +/** +* \brief Finds the Start of an object node in the given JSON file +* +* The token usually is of the form ": {" +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param objNameStr Expected object name +* \param currChar Pointer to index location of the string to parse +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonFindStartOfObject(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar); + +/** +* \brief Finds the corresponding end of a given object node in the given JSON file +* +* The token usually is of the form "}," +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param objNameStr Expected object name +* \param currChar Pointer to index location of the string to parse +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonFindEndOfObject(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar); + +/** +* \brief Finds the start of an array object node in the given JSON file +* +* The token usually is of the form ": [" +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param objNameStr Expected object name +* \param currChar Pointer to index location of the string to parse +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonFindStartOfArray(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar); + +/** +* \brief Finds the corresponding end of an array object node in the given JSON file +* +* The token usually is of the form "]," +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param objNameStr Expected object name +* \param currChar Pointer to index location of the string to parse +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonFindEndOfArray(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar); + +/** +* \brief Finds the start of an object in an array node in the given JSON file +* +* The token usually is of the form "{" +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param objNameStr Expected object name +* \param currChar Pointer to index location of the string to parse +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonFindOpenCurlBrace(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar); + +/** +* \brief Finds the end of an object in an array node in the given JSON file +* +* The token usually is of the form "}" +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param objNameStr Expected object name +* \param currChar Pointer to index location of the string to parse +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonFindClosedCurlBrace(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar); + +/** +* \brief Parses an unsigned integer word value of a given property name +* +* The token usually is of the form " : value" +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param objNameStr Expected object name +* \param currChar Pointer to index location of the string to parse +* \param value Pointer to memory where parsed uint64 value is stored +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseU64(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar, + uint64_t* value); + +/** +* \brief Parses a signed integer word value of a given property name +* +* The token usually is of the form " : value" +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param objNameStr Expected object name +* \param currChar Pointer to index location of the string to parse +* \param value Pointer to memory where parsed int32 value is stored +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseI32(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar, + int32_t* value); + +/** +* \brief Parses an unsigned integer word value of a given property name +* +* The token usually is of the form " : value" +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param objNameStr Expected object name +* \param currChar Pointer to index location of the string to parse +* \param value Pointer to memory where parsed uint32 value is stored +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseU32(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar, + uint32_t* value); + +/** +* \brief Parses an unsigned half word value of a given property name +* +* The token usually is of the form " : value" +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param objNameStr Expected object name +* \param currChar Pointer to index location of the string to parse +* \param value Pointer to memory where parsed uint16 value is stored +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseU16(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar, + uint16_t* value); + +/** +* \brief Parses an unsigned byte value of a given property name +* +* The token usually is of the form " : value" +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param objNameStr Expected object name +* \param currChar Pointer to index location of the string to parse +* \param value Pointer to memory where parsed uint8 value is stored +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseU8(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar, + uint8_t* value); + +/** +* \brief Parses a signed byte value of a given property name +* +* The token usually is of the form " : value" +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param objNameStr Expected object name +* \param currChar Pointer to index location of the string to parse +* \param value Pointer to memory where parsed int8 value is stored +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseI8(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar, + int8_t* value); + +/** +* \brief Parses an unsigned byte value of a given property name +* +* The token usually is of the form " : value" +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param objNameStr Expected object name +* \param currChar Pointer to index location of the string to parse +* \param value Pointer to memory where parsed uint8 value is stored +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseUI8(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar, + uint8_t* value); + +/** +* \brief Parses an individual array element of type signed half word +* +* The token usually is of the form " : value" +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param currChar Pointer to index location of the string to parse +* \param value Pointer to memory where parsed Int16 array element is stored +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseArrayElementI16(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + int* currChar, + int16_t* value); + +/** +* \brief Parses an individual array element of type unsigned half word +* +* The token usually is of the form " : value" +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param currChar Pointer to index location of the string to parse +* \param value Pointer to memory where parsed uint16 array element is stored +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +uint32_t adrv9025_JsonParseArrayElementU16(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + int* currChar, + uint16_t* value); +/** +* \brief Used to skip past CalRsltsFileStr in Json file +* +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fp Pointer to the JSON file to be parsed +* \param fullStr Object and value parsed from the JSON file +* \param currChar Pointer to index location of the string to parse +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adrv9025_JsonParseCalRsltFileStr(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + int32_t* currChar); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_analog_orx_mem_map.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_analog_orx_mem_map.c new file mode 100644 index 0000000..0d0b329 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_analog_orx_mem_map.c @@ -0,0 +1,61 @@ +/** + * \file Automatically generated file: adrv9025_bf_analog_orx_mem_map.c + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/adrv9025_bf_analog_orx_mem_map.h" +#include "./../../private/include/adrv9025_bf_hal.h" +#include "adi_common_error.h" + +int32_t adrv9025_AnalogOrxMemMapLomuxSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogOrxMemMapChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ANALOG_ORX_CH0) && + (baseAddr != ADRV9025_BF_ANALOG_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogOrxMemMapLomuxSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xAA), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_analog_rx_mem_map.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_analog_rx_mem_map.c new file mode 100644 index 0000000..6c2fff8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_analog_rx_mem_map.c @@ -0,0 +1,370 @@ +/** + * \file Automatically generated file: adrv9025_bf_analog_rx_mem_map.c + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/adrv9025_bf_analog_rx_mem_map.h" +#include "./../../private/include/adrv9025_bf_hal.h" +#include "adi_common_error.h" + +int32_t adrv9025_AnalogRxMemMapRxBlockDetDecayBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogRxMemMapChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_AnalogRxMemMapRxBlockDetDecayBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_RX) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogRxMemMapRxBlockDetDecayBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x62), + (uint8_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogRxMemMapRxBlockDetLlbthBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogRxMemMapChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 63U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_AnalogRxMemMapRxBlockDetLlbthBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_RX) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogRxMemMapRxBlockDetLlbthBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_AnalogRxMemMapRxBlockDetLlbthBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldWrite(device, + (baseAddr + 0x63 + channelId * 1), + (uint8_t)bfValue, + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogRxMemMapRxBlockDetLlbthBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogRxMemMapChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_RX) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogRxMemMapRxBlockDetLlbthBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_AnalogRxMemMapRxBlockDetLlbthBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x63 + channelId * 1), + &rxBfData[0], + 0x3F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogRxMemMapRxBlockDetUlbthBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogRxMemMapChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 63U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_AnalogRxMemMapRxBlockDetUlbthBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_RX) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogRxMemMapRxBlockDetUlbthBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_AnalogRxMemMapRxBlockDetUlbthBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldWrite(device, + (baseAddr + 0x65 + channelId * 1), + (uint8_t)bfValue, + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogRxMemMapRxBlockDetUlbthBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogRxMemMapChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_RX) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogRxMemMapRxBlockDetUlbthBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_AnalogRxMemMapRxBlockDetUlbthBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x65 + channelId * 1), + &rxBfData[0], + 0x3F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogRxMemMapRxTiaForceUpdateBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogRxMemMapChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_AnalogRxMemMapRxTiaForceUpdateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_RX) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_RX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogRxMemMapRxTiaForceUpdateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x3E), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_analog_tx_mem_map.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_analog_tx_mem_map.c new file mode 100644 index 0000000..d941545 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_analog_tx_mem_map.c @@ -0,0 +1,679 @@ +/** + * \file Automatically generated file: adrv9025_bf_analog_tx_mem_map.c + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/adrv9025_bf_analog_tx_mem_map.h" +#include "./../../private/include/adrv9025_bf_hal.h" +#include "adi_common_error.h" + +int32_t adrv9025_AnalogTxMemMapAuxdac0BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 4095U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_AnalogTxMemMapAuxdac0BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_TX) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogTxMemMapAuxdac0BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x6F), + (uint8_t)(bfValue >> 8), + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x70), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogTxMemMapAuxdac0BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_TX) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogTxMemMapAuxdac0BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x6F), + &rxBfData[0x0], + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x70), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogTxMemMapAuxdac0ConfigBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_AnalogTxMemMapAuxdac0ConfigBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_TX) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogTxMemMapAuxdac0ConfigBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x6F), + (uint8_t)bfValue, + 0xF0, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogTxMemMapAuxdac1BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 4095U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_AnalogTxMemMapAuxdac1BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_TX) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogTxMemMapAuxdac1BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x71), + (uint8_t)(bfValue >> 8), + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x72), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogTxMemMapAuxdac1BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_TX) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogTxMemMapAuxdac1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x71), + &rxBfData[0x0], + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x72), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogTxMemMapAuxdac1ConfigBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_AnalogTxMemMapAuxdac1ConfigBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_TX) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogTxMemMapAuxdac1ConfigBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x71), + (uint8_t)bfValue, + 0xF0, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogTxMemMapAuxdac2BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 4095U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_AnalogTxMemMapAuxdac2BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_TX) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogTxMemMapAuxdac2BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x73), + (uint8_t)(bfValue >> 8), + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x74), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogTxMemMapAuxdac2BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_TX) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogTxMemMapAuxdac2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x73), + &rxBfData[0x0], + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x74), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogTxMemMapAuxdac2ConfigBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_AnalogTxMemMapAuxdac2ConfigBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_TX) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogTxMemMapAuxdac2ConfigBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x73), + (uint8_t)bfValue, + 0xF0, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogTxMemMapAuxdac3BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 4095U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_AnalogTxMemMapAuxdac3BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_TX) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogTxMemMapAuxdac3BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x75), + (uint8_t)(bfValue >> 8), + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x76), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogTxMemMapAuxdac3BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_TX) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogTxMemMapAuxdac3BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x75), + &rxBfData[0x0], + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x76), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogTxMemMapAuxdac3ConfigBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_AnalogTxMemMapAuxdac3ConfigBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_TX) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogTxMemMapAuxdac3ConfigBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x75), + (uint8_t)bfValue, + 0xF0, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_AnalogTxMemMapAuxdacLatchEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_AnalogTxMemMapAuxdacLatchEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ANALOG_TX) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH1) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH2) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH3) && + (baseAddr != ADRV9025_BF_ANALOG_TX_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_AnalogTxMemMapAuxdacLatchEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x77), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_core.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_core.c new file mode 100644 index 0000000..c0977c7 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_core.c @@ -0,0 +1,4739 @@ +/** + * \file Automatically generated file: adrv9025_bf_core.c + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/adrv9025_bf_core.h" +#include "./../../private/include/adrv9025_bf_hal.h" +#include "adi_common_error.h" + +int32_t adrv9025_CoreArmCommandBusyBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreArmCommandBusyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xC3), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreArmDCommandBusyBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreArmDCommandBusyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x147), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreArmM3RunBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreArmM3RunBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreArmM3RunBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x8C), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreArmOverrideControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreArmOverrideControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreArmOverrideControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x107), + (uint8_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreArmOverrideControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreArmOverrideControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x107), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreAuxAdcClkDivide1BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreAuxAdcClkDivide1BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreAuxAdcClkDivide1BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x114), + (uint8_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreAuxAdcClkDivide1BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreAuxAdcClkDivide1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x114), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreAuxAdcClkDivide2BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreAuxAdcClkDivide2BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreAuxAdcClkDivide2BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x115), + (uint8_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreAuxAdcClkDivide2BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreAuxAdcClkDivide2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x115), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreAuxAdcClkPd1BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreAuxAdcClkPd1BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreAuxAdcClkPd1BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x114), + (uint8_t)bfValue, + 0x80, + 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreAuxAdcClkPd2BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreAuxAdcClkPd2BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreAuxAdcClkPd2BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x115), + (uint8_t)bfValue, + 0x80, + 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreEnCtrl0BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreEnCtrl0BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreEnCtrl0BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x55), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreEnCtrl0BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreEnCtrl0BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x55), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreEnCtrl1BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreEnCtrl1BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreEnCtrl1BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x55), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreEnCtrl1BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreEnCtrl1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x55), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreEnCtrl2BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreEnCtrl2BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreEnCtrl2BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x55), + (uint8_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreEnCtrl2BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreEnCtrl2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x55), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreEnCtrl3BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreEnCtrl3BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreEnCtrl3BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x55), + (uint8_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreEnCtrl3BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreEnCtrl3BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x55), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreEnCtrl4BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreEnCtrl4BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreEnCtrl4BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x55), + (uint8_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreEnCtrl4BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreEnCtrl4BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x55), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreEnCtrl5BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreEnCtrl5BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreEnCtrl5BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x55), + (uint8_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreEnCtrl5BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreEnCtrl5BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x55), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreEnCtrl6BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreEnCtrl6BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreEnCtrl6BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x55), + (uint8_t)bfValue, + 0x40, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreEnCtrl6BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreEnCtrl6BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x55), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreEnCtrl7BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreEnCtrl7BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreEnCtrl7BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x55), + (uint8_t)bfValue, + 0x80, + 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreEnCtrl7BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreEnCtrl7BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x55), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpInterruptsMaskPin0BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint64_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 18446744073709551615U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreGpInterruptsMaskPin0BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpInterruptsMaskPin0BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x79), + (uint8_t)(bfValue >> 56)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x78), + (uint8_t)(bfValue >> 48)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x77), + (uint8_t)(bfValue >> 40)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x76), + (uint8_t)(bfValue >> 32)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x75), + (uint8_t)(bfValue >> 24)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x74), + (uint8_t)(bfValue >> 16)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x73), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x72), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpInterruptsMaskPin0BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint64_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpInterruptsMaskPin0BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x79), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x78), + &rxBfData[0x1], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x77), + &rxBfData[0x2], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x76), + &rxBfData[0x3], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x75), + &rxBfData[0x4], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x74), + &rxBfData[0x5], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x73), + &rxBfData[0x6], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x72), + &rxBfData[0x7], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x8, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint64_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpInterruptsMaskPin1BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint64_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 18446744073709551615U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreGpInterruptsMaskPin1BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpInterruptsMaskPin1BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x71), + (uint8_t)(bfValue >> 56)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x70), + (uint8_t)(bfValue >> 48)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x6F), + (uint8_t)(bfValue >> 40)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x6E), + (uint8_t)(bfValue >> 32)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x6D), + (uint8_t)(bfValue >> 24)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x6C), + (uint8_t)(bfValue >> 16)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x6B), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x6A), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpInterruptsMaskPin1BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint64_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpInterruptsMaskPin1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x71), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x70), + &rxBfData[0x1], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x6F), + &rxBfData[0x2], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x6E), + &rxBfData[0x3], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x6D), + &rxBfData[0x4], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x6C), + &rxBfData[0x5], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x6B), + &rxBfData[0x6], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x6A), + &rxBfData[0x7], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x8, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint64_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpInterruptsStatusWordBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint64_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpInterruptsStatusWordBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x81), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x80), + &rxBfData[0x1], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x7F), + &rxBfData[0x2], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x7E), + &rxBfData[0x3], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x7D), + &rxBfData[0x4], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x7C), + &rxBfData[0x5], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x7B), + &rxBfData[0x6], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x7A), + &rxBfData[0x7], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x8, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint64_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpInterruptsStickyBitMaskBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint64_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 18446744073709551615U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreGpInterruptsStickyBitMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpInterruptsStickyBitMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x13D), + (uint8_t)(bfValue >> 56)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x13C), + (uint8_t)(bfValue >> 48)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x13B), + (uint8_t)(bfValue >> 40)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x13A), + (uint8_t)(bfValue >> 32)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x139), + (uint8_t)(bfValue >> 24)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x138), + (uint8_t)(bfValue >> 16)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x137), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x136), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpInterruptsStickyBitMaskBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint64_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpInterruptsStickyBitMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x13D), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x13C), + &rxBfData[0x1], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x13B), + &rxBfData[0x2], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x13A), + &rxBfData[0x3], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x139), + &rxBfData[0x4], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x138), + &rxBfData[0x5], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x137), + &rxBfData[0x6], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x136), + &rxBfData[0x7], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x8, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint64_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioAnalogDirectionControlOeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreGpioAnalogDirectionControlOeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioAnalogDirectionControlOeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x82), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioAnalogDirectionControlOeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioAnalogDirectionControlOeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x82), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioAnalogLowerNibbleSourceControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreGpioAnalogLowerNibbleSourceControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioAnalogLowerNibbleSourceControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x88), + (uint8_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioAnalogLowerNibbleSourceControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioAnalogLowerNibbleSourceControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x88), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioAnalogUpperNibbleSourceControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreGpioAnalogUpperNibbleSourceControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioAnalogUpperNibbleSourceControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x88), + (uint8_t)bfValue, + 0xF0, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioAnalogUpperNibbleSourceControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioAnalogUpperNibbleSourceControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x88), + &rxBfData[0], + 0xF0, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioDirectionControlOeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint32_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 524287U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreGpioDirectionControlOeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioDirectionControlOeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x2B), + (uint8_t)(bfValue >> 16), + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x2A), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x29), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioDirectionControlOeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint32_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioDirectionControlOeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x2B), + &rxBfData[0x0], + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x2A), + &rxBfData[0x1], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x29), + &rxBfData[0x2], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x3, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint32_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioExtraBitsSourceControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreGpioExtraBitsSourceControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioExtraBitsSourceControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x34), + (uint8_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioExtraBitsSourceControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioExtraBitsSourceControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x34), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioLowerByteLowerNibbleSourceControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreGpioLowerByteLowerNibbleSourceControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioLowerByteLowerNibbleSourceControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x32), + (uint8_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioLowerByteLowerNibbleSourceControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioLowerByteLowerNibbleSourceControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x32), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x32), + (uint8_t)bfValue, + 0xF0, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x32), + &rxBfData[0], + 0xF0, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioSpiReadBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint32_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioSpiReadBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x31), + &rxBfData[0x0], + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x30), + &rxBfData[0x1], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x2F), + &rxBfData[0x2], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x3, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint32_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioSpiSourceBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint32_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 524287U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreGpioSpiSourceBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioSpiSourceBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x2E), + (uint8_t)(bfValue >> 16), + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x2D), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x2C), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioSpiSourceBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint32_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioSpiSourceBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x2E), + &rxBfData[0x0], + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x2D), + &rxBfData[0x1], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x2C), + &rxBfData[0x2], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x3, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint32_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x33), + (uint8_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x33), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x33), + (uint8_t)bfValue, + 0xF0, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x33), + &rxBfData[0], + 0xF0, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreMonitorOutBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreMonitorOutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreMonitorOutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x54), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreMonitorOutBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreMonitorOutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x54), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreOrxEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreOrxEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreOrxEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x106), + (uint8_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreOrxEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreOrxEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x106), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreOrxPinModeEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreOrxPinModeEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreOrxPinModeEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x103), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreOrxPinModeEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreOrxPinModeEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x103), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreOrxPinModeUsingSpiSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreOrxPinModeUsingSpiSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreOrxPinModeUsingSpiSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x103), + (uint8_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreOrxPinModeUsingSpiSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreOrxPinModeUsingSpiSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x103), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreOrxSelectInPinModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreOrxSelectInPinModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreOrxSelectInPinModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x104), + (uint8_t)bfValue, + 0x6, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreOrxSelectInPinModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreOrxSelectInPinModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x104), + &rxBfData[0], + 0x6, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreOrxSingleChannelModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreOrxSingleChannelModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreOrxSingleChannelModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x103), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreOrxSingleChannelModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreOrxSingleChannelModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x103), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreOrxSingleChannelMode1aBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreOrxSingleChannelMode1aBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreOrxSingleChannelMode1aBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x105), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreOrxSingleChannelMode1aBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreOrxSingleChannelMode1aBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x105), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreOrxSingleChannelMode1aHighChannelEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreOrxSingleChannelMode1aHighChannelEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreOrxSingleChannelMode1aHighChannelEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x105), + (uint8_t)bfValue, + 0xC0, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreOrxSingleChannelMode1aHighChannelEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreOrxSingleChannelMode1aHighChannelEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x105), + &rxBfData[0], + 0xC0, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreOrxSingleChannelMode1aLowChannelEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreOrxSingleChannelMode1aLowChannelEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreOrxSingleChannelMode1aLowChannelEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x105), + (uint8_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreOrxSingleChannelMode1aLowChannelEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreOrxSingleChannelMode1aLowChannelEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x105), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CorePdAuxdacBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CorePdAuxdacBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CorePdAuxdacBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x117), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CorePdAuxdacBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CorePdAuxdacBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x117), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CorePinSelectSettlingDelayBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CorePinSelectSettlingDelayBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CorePinSelectSettlingDelayBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x104), + (uint8_t)bfValue, + 0x78, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CorePinSelectSettlingDelayBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CorePinSelectSettlingDelayBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x104), + &rxBfData[0], + 0x78, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreRxOrxAnySourceMuxSel10BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreRxOrxAnySourceMuxSel10BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreRxOrxAnySourceMuxSel10BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x5A), + (uint8_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreRxOrxAnySourceMuxSel10BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreRxOrxAnySourceMuxSel10BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x5A), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreRxOrxAnySourceMuxSel32BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreRxOrxAnySourceMuxSel32BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreRxOrxAnySourceMuxSel32BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x5A), + (uint8_t)bfValue, + 0x38, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreRxOrxAnySourceMuxSel32BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreRxOrxAnySourceMuxSel32BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x5A), + &rxBfData[0], + 0x38, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreRxOrxAnySourceMuxSel54BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreRxOrxAnySourceMuxSel54BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreRxOrxAnySourceMuxSel54BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x5B), + (uint8_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreRxOrxAnySourceMuxSel54BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreRxOrxAnySourceMuxSel54BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x5B), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreRxOrxAnySourceMuxSel76BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreRxOrxAnySourceMuxSel76BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreRxOrxAnySourceMuxSel76BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x5B), + (uint8_t)bfValue, + 0x38, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreRxOrxAnySourceMuxSel76BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreRxOrxAnySourceMuxSel76BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x5B), + &rxBfData[0], + 0x38, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreRxSync1PadLvdsModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreRxSync1PadLvdsModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x52), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreRxSync1PadLvdsPnInvBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreRxSync1PadLvdsPnInvBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x52), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreRxSync2PadLvdsModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreRxSync2PadLvdsModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x52), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreRxSync2PadLvdsPnInvBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreRxSync2PadLvdsPnInvBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x52), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreRxSync3PadLvdsModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreRxSync3PadLvdsModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x53), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreRxSync3PadLvdsPnInvBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreRxSync3PadLvdsPnInvBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x53), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreSpi2EnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreSpi2EnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreSpi2EnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x12), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreSpi2EnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreSpi2EnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x12), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreStreamProcGpioPinMaskBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreStreamProcGpioPinMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreStreamProcGpioPinMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x13F), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x13E), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreStreamProcGpioPinMaskBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreStreamProcGpioPinMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x13F), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x13E), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreTxAttenUpdCoreSpiBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreTxAttenUpdCoreSpiBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreTxAttenUpdCoreSpiBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x16E), + (uint8_t)bfValue, + 0x1E, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreTxAttenUpdCoreSpiEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_CoreTxAttenUpdCoreSpiEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreTxAttenUpdCoreSpiEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x16E), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_CoreTxAttenUpdCoreSpiEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreTxAttenUpdCoreSpiEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x16E), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreTxSync1PadLvdsModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreTxSync1PadLvdsModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x51), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreTxSync1PadLvdsPnInvBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreTxSync1PadLvdsPnInvBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x51), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreTxSync2PadLvdsModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreTxSync2PadLvdsModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x51), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreTxSync2PadLvdsPnInvBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreTxSync2PadLvdsPnInvBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x51), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_CoreTxSyncDrvSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfCoreChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_CORE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_CoreTxSyncDrvSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x51), + &rxBfData[0], + 0xC0, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_deser.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_deser.c new file mode 100644 index 0000000..e771adc --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_deser.c @@ -0,0 +1,231 @@ +/** + * \file Automatically generated file: adrv9025_bf_deser.c + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/adrv9025_bf_deser.h" +#include "./../../private/include/adrv9025_bf_hal.h" +#include "adi_common_error.h" + +int32_t adrv9025_DeserCbusAddrDesRcBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfDeserChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_DeserCbusAddrDesRcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_DESERIALIZER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_DeserCbusAddrDesRcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x5), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_DeserCbusRdataDesRsBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfDeserChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_DESERIALIZER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_DeserCbusRdataDesRsBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0xB), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_DeserCbusRenDesRcChBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfDeserChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_DeserCbusRenDesRcChBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_DESERIALIZER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_DeserCbusRenDesRcChBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x9), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_DeserCbusWdataDesRcBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfDeserChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_DeserCbusWdataDesRcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_DESERIALIZER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_DeserCbusWdataDesRcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x8), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_DeserCbusWstrobeDesRcChBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfDeserChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_DeserCbusWstrobeDesRcChBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_DESERIALIZER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_DeserCbusWstrobeDesRcChBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x6), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_hal.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_hal.c new file mode 100644 index 0000000..3cfffe6 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_hal.c @@ -0,0 +1,747 @@ +/** +* \file adrv9025_bf_hal.c +* \brief Contains ADI Transceiver Hardware Abstraction functions +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_common_hal.h" +#include "adi_adrv9025.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_error.h" +#include "./../../private/include/adrv9025_bf_hal.h" + +int32_t adrv9025_BfWriteCacheEn(adi_adrv9025_Device_t* device, + adrv9025_Bf_WrCache_State_e wrCacheState) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + if (wrCacheState > ADRV9025_WR_HW_RMW_ON) + { + if (device->common.cacheInfo.HW_RMW_Enabled == ADI_FALSE && device->common.cacheInfo.wrOnly == ADI_FALSE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Caching not available"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + device->common.cacheInfo.wrCacheState = (uint8_t)wrCacheState; + /* if merge caching is selected ensure merge distance is at least = 1*/ + if ((device->common.cacheInfo.mergeDistance == 0) && (wrCacheState == ADRV9025_WR_GBL_MERGE_ON)) + { + device->common.cacheInfo.mergeDistance = 1; + } + + return recoveryAction; +} + +int32_t adrv9025_BfReadCacheEn(adi_adrv9025_Device_t* device, + adrv9025_Bf_RdCache_State_e rdCacheState) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + + device->common.cacheInfo.rdCacheState = rdCacheState; + + return recoveryAction; +} + +int32_t adrv9025_BfReadCacheInit(adi_adrv9025_Device_t* device) +{ + uint64_t rdData = 0; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint16_t numRdBytes = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + + if (device->common.cacheInfo.rdCacheState == ADRV9025_RD_BF_CACHE_ON) + { + recoveryAction = adrv9025_BfReadCacheFlush(device, + &rdData, + &numRdBytes); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + "Cache init failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + /* if Global Caching is being used, no further flushing should be performed + * until the user calls bf flush */ + } + + return recoveryAction; +} + +int32_t adrv9025_BfWriteCacheInit(adi_adrv9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + + if (device->common.cacheInfo.wrCacheState > ADRV9025_WR_HW_RMW_ON) + { + if ((device->common.cacheInfo.HW_RMW_Enabled == ADI_FALSE) && (device->common.cacheInfo.wrOnly == ADI_FALSE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Caching not available"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* skip cacheInit if Global level Cache is on. */ + if (device->common.cacheInfo.wrCacheState == ADRV9025_WR_BF_CACHE_ON) + { + /* Ensures the cache is empty if bitField Level Caching is on */ + recoveryAction = adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + device->common.cacheInfo.wrFlushEn, + "Wr Cache flush failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* if using bitField level caching re-enable caching after each flush */ + device->common.cacheInfo.wrFlushEn = ADI_ENABLE; + } + else + { + /* disable flushing within the bitfield function when global + * caching is being used */ + device->common.cacheInfo.wrFlushEn = ADI_DISABLE; + } + + return recoveryAction; +} + +int32_t adrv9025_BfByteWrite(adi_adrv9025_Device_t* device, + uint16_t addr, + uint8_t regVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t i = 0; + uint8_t addrFoundInCache = ADI_FALSE; + uint8_t wrFlushEnSaved = device->common.cacheInfo.wrFlushEn; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + + if (device->common.cacheInfo.wrCacheState == ADRV9025_WR_GBL_MERGE_ON) + { + /* Write merging is on, so the cache is searched to see if address is in the cache */ + for (i = 0; i < device->common.cacheInfo.wrCacheIdx; i++) + { + /* The cache is packed in the form AABBMMDD + * where AA is MSB Addr, BB is the LSB addr, + * MM is the mask and DD is the Data. + */ + /* if the address part of the cache word = wanted address */ + if ((uint16_t)(device->common.cacheInfo.wrCache[i] >> SPI_ADDR_SIZE) == addr) + { + addrFoundInCache = ADI_TRUE; + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + /* preserve the address but clear the data. */ + + device->common.cacheInfo.wrCache[i] &= 0xFFFFFF00; + device->common.cacheInfo.wrCache[i] |= (((uint32_t)0xFF << SPI_MASK_SIZE) | regVal); + } + } + } + + if ((device->common.cacheInfo.wrCacheState > ADRV9025_WR_HW_RMW_ON) && + (addrFoundInCache == ADI_FALSE)) + { + /* Write caching is turned on and the bitField has not been merged */ + if ((device->common.cacheInfo.spiWrBufferCnt + ADRV9025_SPI_BYTES) >= ADI_COMMON_HAL_SPIARRAYSIZE) + { + /* if cache is full then flush cache and add next instruction. + * should not be a problem flushing a write cache. */ + device->common.cacheInfo.wrFlushEn = ADI_ENABLE; + recoveryAction = adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + device->common.cacheInfo.spiWrBufferCnt, + "Wr Cache flush failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + device->common.cacheInfo.wrFlushEn = wrFlushEnSaved; + } + + device->common.cacheInfo.wrCache[device->common.cacheInfo.wrCacheIdx++] = + ((uint32_t)addr << SPI_ADDR_SIZE) | (0xFF << SPI_MASK_SIZE) | regVal; + /* track the size of the spibuffer needed to write the cache. */ + device->common.cacheInfo.spiWrBufferCnt += ADRV9025_SPI_BYTES; + } + + if (device->common.cacheInfo.wrCacheState < ADRV9025_WR_BF_CACHE_ON) + { + /* Write caching is not being used, so do an immediate write */ + if (device->common.devHalInfo != NULL) + { + recoveryAction = adi_adrv9025_SpiByteWrite(device, + addr, + regVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "SPI write failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_BfByteRead(adi_adrv9025_Device_t* device, + uint16_t addr, + uint8_t* regVal, + uint8_t endOfBf) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + + ADI_NULL_PTR_RETURN(&device->common, + regVal); + + if (device->common.cacheInfo.wrOnly == ADI_TRUE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->common.cacheInfo.wrOnly, + "Read Operations cannot be called when wrOnly is enabled"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (device->common.cacheInfo.rdCacheState > ADRV9025_RD_CACHE_OFF) + { + /* Read Caching is turned on */ + if ((device->common.cacheInfo.spiRdBufferCnt + ADRV9025_SPI_BYTES) >= ADI_COMMON_HAL_SPIARRAYSIZE) + { + /* if the cache is full then raise an error */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Rx Cache size exceeded error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* set bits [31:16] of the cache to the 16 bit address + * set bits [15:8] of cache to the 8 bit mask address + * set bits [7:0] of cache to the 8 bit endOfBf. + * endOfBf contains two 4 bit fields. + * [7:4] is 0xF or 0x0 and masks a end of bitField data value. + * [3:0] is the register startBit ie where the value resides in the register. + */ + device->common.cacheInfo.rdCache[device->common.cacheInfo.rdCacheIdx++] = + ((uint32_t)addr << SPI_ADDR_SIZE) | (0xFF << SPI_DATA_SIZE) | (uint32_t)endOfBf; + } + else + { + recoveryAction = adi_adrv9025_SpiByteRead(device, + addr, + regVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_SPI_FAIL, + recoveryAction, + NULL, + "SPI byte read failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_BfFieldWrite(adi_adrv9025_Device_t* device, + uint16_t addr, + uint8_t fieldVal, + uint8_t mask, + uint8_t startBit) +{ + static const uint8_t MAX_START_BIT = 7; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t i = 0; + int16_t mergeIdx = 0; + uint8_t regVal = 0; + uint8_t addrFoundInCache = ADI_FALSE; + uint8_t cachemask = 0; + uint8_t newMask = 0; + uint8_t cacheVal = 0; + uint8_t newVal = 0; + uint8_t registerVal = 0; + uint8_t newRegVal = 0; + uint8_t wrFlushEnSaved = device->common.cacheInfo.wrFlushEn; + uint8_t wrCacheStateLocal = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + + if (startBit > MAX_START_BIT) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_ADRV9025_ACT_ERR_FLUSH_CACHE, + NULL, + "startbit exceeded its max value of 7 "); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((device->common.cacheInfo.wrCacheState > ADRV9025_WR_CACHE_OFF) && (device->common.cacheInfo.HW_RMW_Enabled == ADI_DISABLE)) + { + /* If HW_RMW functionality is unavailable, we should force the manual read/modify/write operation since + * it's not possible to call adi_adrv9025SpiDataPack with a mask different than 0xFF */ + wrCacheStateLocal = ADRV9025_WR_CACHE_OFF; + } + else + { + wrCacheStateLocal = device->common.cacheInfo.wrCacheState; + } + + regVal = ((fieldVal << startBit) & mask); + + if (wrCacheStateLocal == ADRV9025_WR_GBL_MERGE_ON) + { + /* if the cache is larger then the merge distance start looking for + * the address merge distance indexes back else search from the beginning + * if found merge the new data and mask with the existing data + */ + if (device->common.cacheInfo.wrCacheIdx > device->common.cacheInfo.mergeDistance) + { + mergeIdx = device->common.cacheInfo.wrCacheIdx - device->common.cacheInfo.mergeDistance; + if (mergeIdx < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_ADRV9025_ACT_ERR_RESET_CACHE, + NULL, + "mergIdx cannot be negative"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + for (i = mergeIdx; i < device->common.cacheInfo.wrCacheIdx; i++) + { + /* search the cache for addr in the cache + * if found merge field val and the mask into the original values + */ + if ((uint16_t)(device->common.cacheInfo.wrCache[i] >> SPI_ADDR_SIZE) == addr) + { + addrFoundInCache = ADI_TRUE; + cachemask = (uint8_t)((device->common.cacheInfo.wrCache[i] & 0x0000FF00) >> SPI_MASK_SIZE); + newMask = cachemask | mask; + cacheVal = (uint8_t)(device->common.cacheInfo.wrCache[i] & 0x000000FF); + cacheVal &= ~mask; + newVal = cacheVal | regVal; + + /* clear org mask and data. */ + device->common.cacheInfo.wrCache[i] &= 0xFFFF0000; + device->common.cacheInfo.wrCache[i] |= (uint32_t)(newMask << SPI_MASK_SIZE) | newVal; + } + } + } + + if ((wrCacheStateLocal > ADRV9025_WR_HW_RMW_ON) && !addrFoundInCache) + { + /* if caching is on or merging is on + * but addr was not found in the cache + * add the wr instruction to the cache. + */ + /* if the cache requirements will exceed the spi buffer flush it now. */ + if ((device->common.cacheInfo.spiWrBufferCnt + ADRV9025_HW_RMW_BYTES) >= ADI_COMMON_HAL_SPIARRAYSIZE) + { + device->common.cacheInfo.wrFlushEn = ADI_ENABLE; + recoveryAction = adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + device->common.cacheInfo.wrFlushEn = wrFlushEnSaved; + } + + device->common.cacheInfo.wrCache[device->common.cacheInfo.wrCacheIdx++] = + ((uint32_t)addr << SPI_ADDR_SIZE) | ((uint32_t)mask << 8) | regVal; + + /* track the size of the spibuffer needed to write the cache.*/ + if (mask == 0xFF) + { + device->common.cacheInfo.spiWrBufferCnt += ADRV9025_SPI_BYTES; + } + else + { + device->common.cacheInfo.spiWrBufferCnt += ADRV9025_HW_RMW_BYTES; + } + } + + /* Immediate Read modify write using HW_RMW function */ + if (wrCacheStateLocal == ADRV9025_WR_HW_RMW_ON) + { + /* if HW-RMW is turned on write the data immediately using HW-RMW */ + device->common.cacheInfo.wrCache[0] = ((uint32_t)addr << SPI_ADDR_SIZE) | ((uint32_t)mask << 8) | regVal; + + recoveryAction = adi_adrv9025_SpiCacheWrite(device, + &device->common.cacheInfo.wrCache[0], + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (wrCacheStateLocal == ADRV9025_WR_CACHE_OFF) + { + if (device->common.cacheInfo.wrOnly == ADI_TRUE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->common.cacheInfo.wrOnly, + "Cannot write this field with manual RMW since wrOnly is true"); + + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Immediate Standard read Modify Write using separate read + * and writespi transactions. + */ + recoveryAction = adi_adrv9025_SpiByteRead(device, + addr, + ®isterVal); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* modify the register value */ + newRegVal = (registerVal & ~mask) | regVal; + + /* write to the register with modified value */ + recoveryAction = adi_adrv9025_SpiByteWrite(device, + addr, + newRegVal); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_BfFieldRead(adi_adrv9025_Device_t* device, + uint16_t addr, + uint8_t* fieldVal, + uint8_t mask, + uint8_t startBit) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + + ADI_NULL_PTR_RETURN(&device->common, + fieldVal); + + if (device->common.cacheInfo.wrOnly == ADI_TRUE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->common.cacheInfo.wrOnly, + "Read Operations cannot be called when wrOnly is enabled"); + + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (device->common.cacheInfo.rdCacheState > ADRV9025_RD_CACHE_OFF) + { + /* adds spi call to cache */ + if ((device->common.cacheInfo.spiRdBufferCnt + ADRV9025_SPI_BYTES) >= ADI_COMMON_HAL_SPIARRAYSIZE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Rx Cache size exceeded error"); + + ADI_ERROR_RETURN(device->common.error.newAction); + } + device->common.cacheInfo.rdCache[device->common.cacheInfo.rdCacheIdx++] = + ((uint32_t)addr << SPI_ADDR_SIZE) | ((uint32_t)mask << SPI_MASK_SIZE) | startBit; + device->common.cacheInfo.spiRdBufferCnt += ADRV9025_SPI_BYTES; + } + else + { + /* Implements immediate spi transaction call only used when caching is turned off. */ + recoveryAction = adi_adrv9025_SpiFieldRead(device, + addr, + fieldVal, + mask, + startBit); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_SPI_FAIL, + recoveryAction, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + "Bitfield read failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_BfReadAssembleData(adi_adrv9025_Device_t* device, + uint8_t* rxBfData, + uint8_t numRxBfData, + uint64_t* rxData) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t i = 0; + uint16_t numRxBitFields = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + + ADI_NULL_PTR_RETURN(&device->common, + rxBfData); + + ADI_NULL_PTR_RETURN(&device->common, + rxData); + + if (device->common.cacheInfo.rdCacheState == ADRV9025_RD_BF_CACHE_ON) + { + recoveryAction = adrv9025_BfReadCacheFlush(device, + rxData, + &numRxBitFields); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_SPI_FAIL, + recoveryAction, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + "Read cache flush failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (device->common.cacheInfo.rdCacheState == ADRV9025_RD_CACHE_OFF) + { + /* Caching is not used so then assembly the bitFiled register values + * into a bitField Value. The max bitField Value is 64bits long. + * so rdData could be shifted 8 times to concatenate a 64 bit value. + */ + for (i = 0; i < numRxBfData; i++) + { + /* shift rxData to the left to make room for the next lower byte + * in the bitField + */ + *rxData = (*rxData << 8) | (uint64_t)rxBfData[i]; + } + } + + return recoveryAction; +} + +int32_t adrv9025_BfReadCacheFlush(adi_adrv9025_Device_t* device, + uint64_t* rdData, + uint16_t* numRdBitFields) +{ + static const uint8_t SHIFT_BYTE = 8; + static const uint8_t MAX_START_BIT = 7; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t bfValue = 0; + uint32_t i = 0; + uint8_t regVal = 0; + uint8_t mask = 0; + uint8_t startBit = 0; + uint8_t endOfBitfield = 0; + uint8_t regData[ADI_COMMON_HAL_SPIARRAYSIZE] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + + ADI_NULL_PTR_RETURN(&device->common, + rdData); + + ADI_NULL_PTR_RETURN(&device->common, + numRdBitFields); + + if (device->common.cacheInfo.wrOnly == ADI_TRUE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->common.cacheInfo.wrOnly, + "Read Operations cannot be called when wrOnly is enabled"); + + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *numRdBitFields = 0; + + if (device->common.cacheInfo.spiRdBufferCnt > ADI_COMMON_HAL_SPIARRAYSIZE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_ADRV9025_ACT_ERR_FLUSH_CACHE, + NULL, + "Rd Cache index exceeded the spi cache Size "); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (device->common.cacheInfo.rdCacheIdx > 0) + { + recoveryAction = adi_adrv9025_SpiCacheRead(device, + device->common.cacheInfo.rdCache, + ®Data[0], + device->common.cacheInfo.rdCacheIdx); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Rd Cache failure "); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* depack the array of register values into an array of bitField values*/ + for (i = 0; i < device->common.cacheInfo.rdCacheIdx; i++) + { + /* for each of the register values in the cache (if any) + combine the data into a bitfield value*/ + + mask = (uint8_t)(device->common.cacheInfo.rdCache[i] >> SHIFT_BYTE); + startBit = (uint8_t)(device->common.cacheInfo.rdCache[i]); + + /* The last byte in the bit field is marked by setting the upper + * nible of the startBit to F, this allows the lower nible to + * handle the byte with values from 0 to 7. + * This marker is added within the get bitfield function. + */ + endOfBitfield = startBit > 0xC; + + if (endOfBitfield) + { + /*remove the endofbitField marker*/ + startBit = startBit & 0x3F; + } + + regVal = regData[((3 * i) + 2)]; + + if (startBit > MAX_START_BIT) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_ADRV9025_ACT_ERR_FLUSH_CACHE, + NULL, + "startbit exceeded its max value of 7 "); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + bfValue = ((uint32_t)bfValue << SHIFT_BYTE) | ((regVal & mask) >> startBit); + + if (endOfBitfield) + { + rdData[(*numRdBitFields)++] = bfValue; + bfValue = 0; + } + + device->common.cacheInfo.rdCache[device->common.cacheInfo.rdCacheIdx] = '\0'; + } + + device->common.cacheInfo.rdCacheIdx = 0; + device->common.cacheInfo.spiRdBufferCnt = 0; + } + + return recoveryAction; +} + +int32_t adrv9025_BfWriteCacheFlush(adi_adrv9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t i = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + + if (device->common.cacheInfo.spiWrBufferCnt > ADI_COMMON_HAL_SPIARRAYSIZE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_ADRV9025_ACT_ERR_FLUSH_CACHE, + NULL, + "Wr Cache index exceeded the spi cache Size "); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* only call flush if there is something in the cache */ + if ((device->common.cacheInfo.wrFlushEn == ADI_ENABLE) && (device->common.cacheInfo.wrCacheIdx > 0)) + { + recoveryAction = adi_adrv9025_SpiCacheWrite(device, + device->common.cacheInfo.wrCache, + device->common.cacheInfo.wrCacheIdx); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_SPI_FAIL, + recoveryAction, + NULL, + "Wr Cache failure "); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < device->common.cacheInfo.wrCacheIdx; i++) + { + device->common.cacheInfo.wrCache[i] = '\0'; + } + device->common.cacheInfo.wrCacheIdx = 0; + device->common.cacheInfo.spiWrBufferCnt = 0; + } + + device->common.cacheInfo.wrFlushEn = ADI_ENABLE; + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_jesd_common.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_jesd_common.c new file mode 100644 index 0000000..37cb8df --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_jesd_common.c @@ -0,0 +1,1034 @@ +/** + * \file Automatically generated file: adrv9025_bf_jesd_common.c + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/adrv9025_bf_jesd_common.h" +#include "./../../private/include/adrv9025_bf_hal.h" +#include "adi_common_error.h" + +int32_t adrv9025_JesdCommonJrxTestLaneClearErrorsBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JesdCommonJrxTestLaneClearErrorsBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJrxTestLaneClearErrorsBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x2C), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJrxTestLaneErrorCountBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t channelId, + uint32_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJrxTestLaneErrorCountBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JesdCommonJrxTestLaneErrorCountBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0x5F + channelId * 1), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x4F + channelId * 1), + &rxBfData[0x1], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x3F + channelId * 1), + &rxBfData[0x2], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x3, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint32_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJrxTestLaneErrorFlagBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJrxTestLaneErrorFlagBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JesdCommonJrxTestLaneErrorFlagBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x2F + channelId * 1), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJrxTestLaneInvBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJrxTestLaneInvBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JesdCommonJrxTestLaneInvBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x2F + channelId * 1), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJrxTestLaneInvalidDataFlagBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJrxTestLaneInvalidDataFlagBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JesdCommonJrxTestLaneInvalidDataFlagBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x2F + channelId * 1), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJrxTestLaneUpdateErrorCountBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JesdCommonJrxTestLaneUpdateErrorCountBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJrxTestLaneUpdateErrorCountBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x2C), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJrxTestModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JesdCommonJrxTestModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJrxTestModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x2E), + (uint8_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJrxTestModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJrxTestModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x2E), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJrxTestSampleClearErrorsBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JesdCommonJrxTestSampleClearErrorsBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJrxTestSampleClearErrorsBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x2C), + bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJrxTestSampleClearErrorsBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJrxTestSampleClearErrorsBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x2C), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJrxTestSampleErrorCountBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJrxTestSampleErrorCountBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x2D), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJrxTestSampleErrorFlagBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJrxTestSampleErrorFlagBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x2C), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJrxTestSampleUpdateErrorCountBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JesdCommonJrxTestSampleUpdateErrorCountBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJrxTestSampleUpdateErrorCountBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x2C), + (uint8_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJrxTestSourceBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JesdCommonJrxTestSourceBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJrxTestSourceBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x2E), + (uint8_t)bfValue, + 0x80, + 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJrxTestSourceBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJrxTestSourceBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x2E), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJtxLinkEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJtxLinkEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x89), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJtxOverrideSrstEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JesdCommonJtxOverrideSrstEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJtxOverrideSrstEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x8A), + (uint8_t)bfValue, + 0x40, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJtxOverrideSrstEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif /* ADRV9025_BITFIELD_NULL_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJtxOverrideSrstEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + adrv9025_BfFieldRead(device, + (baseAddr + 0x8A), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJtxTriggerSrstNBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JesdCommonJtxTriggerSrstNBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJtxTriggerSrstNBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x8A), + (uint8_t)bfValue, + 0x80, + 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJtxTriggerSrstNBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif /* ADRV9025_BITFIELD_NULL_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJtxTriggerSrstNBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + adrv9025_BfFieldRead(device, + (baseAddr + 0x8A), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return device->common.error.newAction; +} + +int32_t adrv9025_JesdCommonJrxLinkEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJesdCommonChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif /* ADRV9025_BITFIELD_NULL_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_JESD_COMMON)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JesdCommonJrxLinkEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + adrv9025_BfFieldRead(device, + (baseAddr + 0x7C), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return device->common.error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_jrx_link.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_jrx_link.c new file mode 100644 index 0000000..8c761bb --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_jrx_link.c @@ -0,0 +1,4134 @@ +/** + * \file Automatically generated file: adrv9025_bf_jrx_link.c + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/adrv9025_bf_jrx_link.h" +#include "./../../private/include/adrv9025_bf_hal.h" +#include "adi_common_error.h" + +int32_t adrv9025_JrxLinkJrxChksumCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxChksumCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxChksumCfgBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0xA5 + channelId * 1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxConvSelBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 127U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JrxLinkJrxConvSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxConvSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxConvSelBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldWrite(device, + (baseAddr + 0x5D + channelId * 1), + (uint8_t)bfValue, + 0x7F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxConvSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxConvSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxConvSelBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x5D + channelId * 1), + &rxBfData[0], + 0x7F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxCsCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxCsCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x9F), + &rxBfData[0], + 0xC0, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDidCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDidCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x95), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bBdCntBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bBdCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bBdCntBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0xF9 + channelId * 1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bBdeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bBdeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bBdeBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0xF5 + channelId * 1), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bCgsBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bCgsBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bCgsBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0xF5 + channelId * 1), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bCksBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bCksBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bCksBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0xF5 + channelId * 1), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bEcntEnaBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JrxLinkJrxDl204bEcntEnaBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bEcntEnaBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bEcntEnaBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldWrite(device, + (baseAddr + 0xED + channelId * 1), + (uint8_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bEcntEnaBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bEcntEnaBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bEcntEnaBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0xED + channelId * 1), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bEcntRstBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JrxLinkJrxDl204bEcntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bEcntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bEcntRstBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldWrite(device, + (baseAddr + 0xED + channelId * 1), + (uint8_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bEcntTchBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JrxLinkJrxDl204bEcntTchBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bEcntTchBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bEcntTchBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldWrite(device, + (baseAddr + 0xF1 + channelId * 1), + (uint8_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bEcntTchBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bEcntTchBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bEcntTchBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0xF1 + channelId * 1), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bEofEventBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bEofEventBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bEofEventBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x111 + channelId * 1), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bEomfEventBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bEomfEventBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bEomfEventBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x111 + channelId * 1), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bEthBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JrxLinkJrxDl204bEthBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bEthBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0xB2), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bFsBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bFsBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bFsBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0xF5 + channelId * 1), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bFsLostBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bFsLostBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bFsLostBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x111 + channelId * 1), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bIldBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bIldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bIldBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0xF5 + channelId * 1), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bIlsBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bIlsBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bIlsBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0xF5 + channelId * 1), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bIrqClrBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 511U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JrxLinkJrxDl204bIrqClrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bIrqClrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xB1), + (uint8_t)(bfValue >> 8), + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0xB0), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bIrqClrBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bIrqClrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xB1), + &rxBfData[0x0], + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0xB0), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bIrqVecBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bIrqVecBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bIrqVecBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x119 + channelId * 1), + &rxBfData[0x0], + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x115 + channelId * 1), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg0BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg0BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg0BfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0xB5 + channelId * 1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg1BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg1BfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0xB9 + channelId * 1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg10BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg10BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg10BfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0xDD + channelId * 1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg13BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg13BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg13BfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0xE9 + channelId * 1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg2BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg2BfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0xBD + channelId * 1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg3BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg3BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg3BfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0xC1 + channelId * 1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg4BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg4BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg4BfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0xC5 + channelId * 1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg5BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg5BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg5BfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0xC9 + channelId * 1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg6BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg6BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg6BfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0xCD + channelId * 1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg7BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg7BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg7BfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0xD1 + channelId * 1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg8BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg8BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg8BfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0xD5 + channelId * 1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bL0Rxcfg9BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg9BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bL0Rxcfg9BfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0xD9 + channelId * 1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bNitBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bNitBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bNitBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0xF5 + channelId * 1), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bNitCntBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bNitCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bNitCntBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0x101 + channelId * 1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bSyncNBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bSyncNBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bSyncNBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x111 + channelId * 1), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bUekBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bUekBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bUekBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0xF5 + channelId * 1), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bUekCntBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bUekCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bUekCntBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfByteRead(device, + (baseAddr + 0xFD + channelId * 1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bUserDataBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bUserDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bUserDataBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x111 + channelId * 1), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204bValidCksumBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204bValidCksumBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204bValidCksumBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x111 + channelId * 1), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204cMbReqdCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204cMbReqdCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x11F), + &rxBfData[0], + 0xF0, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204cStateGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204cStateGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxDl204cStateGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x12b + channelId * 1), + &rxBfData[0], + 0x07, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204hIrqClrBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 511U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JrxLinkJrxDl204hIrqClrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204hIrqClrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x147), + (uint8_t)(bfValue >> 8), + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x146), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDl204hIrqClrBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDl204hIrqClrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x147), + &rxBfData[0x0], + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x146), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxDscrCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxDscrCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x9B), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxFCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxFCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x9C), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxHdCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxHdCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xA2), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxKCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxKCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x9D), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxLCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxLCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x9B), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxLidCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxLidCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxLidCfgBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x97 + channelId * 1), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxLinkLaneSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxLinkLaneSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxLinkLaneSelBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x66 + channelId * 1), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxLinkTypeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxLinkTypeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x65), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxMCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxMCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x9E), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxNCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxNCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x9F), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxNpCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxNpCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xA0), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxSCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxSCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xA1), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxSyncNSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxSyncNSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x6A), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxSysrefForRelinkBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxSysrefForRelinkBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x65), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxSysrefForStartupBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxSysrefForStartupBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x65), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxTplPhaseAdjustBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxTplPhaseAdjustBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x8F), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x8E), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxTplSysrefIgnoreWhenLinkedBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxTplSysrefIgnoreWhenLinkedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x89), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxTplSysrefMaskBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JrxLinkJrxTplSysrefMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxTplSysrefMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x89), + (uint8_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxTplSysrefMaskBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxTplSysrefMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x89), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxTplSysrefNShotCountBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxTplSysrefNShotCountBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x88), + &rxBfData[0], + 0xF0, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxTplSysrefNShotEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxTplSysrefNShotEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x88), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxTplSysrefRcvdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxTplSysrefRcvdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x88), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxTplUsrDataRdyBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxTplUsrDataRdyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x88), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JrxLinkJrxTplBufDepthBfGet(adi_adrv9025_Device_t *device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* ADRV9025_BITFIELD_NULL_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxTplBufDepthBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if ADRV9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxTplBufDepthBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read to Single Byte */ + recoveryAction = adrv9025_BfByteRead(device, (baseAddr + 0x8A + channelId*1), &rxBfData[0], 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return recoveryAction; +} + +int32_t adrv9025_JrxLinkJrxTplBufProtectionBfGet(adi_adrv9025_Device_t *device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t *bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* ADRV9025_BITFIELD_NULL_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxTplBufProtectionBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = adrv9025_BfFieldRead(device, (baseAddr + 0x89), &rxBfData[0], 0x80, 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return recoveryAction; +} + +int32_t adrv9025_JrxLinkJrxTplBufProtectEnBfSet(adi_adrv9025_Device_t *device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JrxLinkJrxTplBufProtectEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_VALUE_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxTplBufProtectEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = adrv9025_BfFieldWrite(device, (baseAddr + 0x89), (uint8_t)bfValue, 0x40, 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_JrxLinkJrxTplBufProtectEnBfGet(adi_adrv9025_Device_t *device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t *bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* ADRV9025_BITFIELD_NULL_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxTplBufProtectEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = adrv9025_BfFieldRead(device, (baseAddr + 0x89), &rxBfData[0], 0x40, 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return recoveryAction; +} + +int32_t adrv9025_JrxLinkJrxTplPhaseAdjustBfSet(adi_adrv9025_Device_t *device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JrxLinkJrxTplPhaseAdjustBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_VALUE_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxTplPhaseAdjustBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field 8 bits */ + recoveryAction = adrv9025_BfByteWrite(device, (baseAddr + 0x8F), (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field 8 bits */ + recoveryAction = adrv9025_BfByteWrite(device, (baseAddr + 0x8E), (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_JrxLinkJrxTplPhaseDiffBfGet(adi_adrv9025_Device_t *device, + adrv9025_BfJrxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* ADRV9025_BITFIELD_NULL_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_JRX_LINK0) && + (baseAddr != ADRV9025_BF_JRX_LINK1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JrxLinkJrxTplPhaseDiffBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if ADRV9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JrxLinkJrxTplPhaseDiffBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read to Single Byte */ + recoveryAction = adrv9025_BfByteRead(device, (baseAddr + 0x90 + channelId * 1), &rxBfData[0], 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_jtx_link.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_jtx_link.c new file mode 100644 index 0000000..c61efbe --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_jtx_link.c @@ -0,0 +1,1657 @@ +/** + * \file Automatically generated file: adrv9025_bf_jtx_link.c + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/adrv9025_bf_jtx_link.h" +#include "./../../private/include/adrv9025_bf_hal.h" +#include "adi_common_error.h" + +int32_t adrv9025_JtxLinkJtxBidCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxBidCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x47), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxConvSelBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 127U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JtxLinkJtxConvSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxConvSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JtxLinkJtxConvSelBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldWrite(device, + (baseAddr + 0x0 + channelId * 1), + (uint8_t)bfValue, + 0x7F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxConvSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxConvSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JtxLinkJtxConvSelBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x0 + channelId * 1), + &rxBfData[0], + 0x7F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxDidCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxDidCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x46), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxDl204bStateBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxDl204bStateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x67), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxDl204bSyncNBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxDl204bSyncNBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x68), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxDl204bSyncNeCountBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxDl204bSyncNeCountBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x6A), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxDl204cSysrefRcvdGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxDl204cSysrefRcvdGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x7C), + &rxBfData[0], + 0x01, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; + +} + +int32_t adrv9025_JtxLinkJtxECfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxECfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x7D), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxFCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxFCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x4A), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxKCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxKCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x4B), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxLaneInvBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JtxLinkJtxLaneInvBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxLaneInvBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JtxLinkJtxLaneInvBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldWrite(device, + (baseAddr + 0x21 + channelId * 1), + (uint8_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxLaneInvBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxLaneInvBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JtxLinkJtxLaneInvBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x21 + channelId * 1), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxLaneSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxLaneSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_JtxLinkJtxLaneSelBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x21 + channelId * 1), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxLidCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxLidCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x48), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxMCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxMCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x4C), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxNpCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxNpCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x4E), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxScrCfgBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxScrCfgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x49), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxSyncNSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxSyncNSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x3B), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxSysrefForRelinkBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxSysrefForRelinkBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxSysrefForStartupBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxSysrefForStartupBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxTestGenModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JtxLinkJtxTestGenModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxTestGenModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x31), + (uint8_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxTestGenModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxTestGenModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x31), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxTestGenSelBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JtxLinkJtxTestGenSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxTestGenSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x31), + (uint8_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxTestGenSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxTestGenSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x31), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxTplCfgInvalidBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxTplCfgInvalidBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x3D), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxTplPhaseAdjustBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxTplPhaseAdjustBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x40), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x3F), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxTplSysrefIgnoreWhenLinkedBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxTplSysrefIgnoreWhenLinkedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x3D), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxTplSysrefMaskBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_JtxLinkJtxTplSysrefMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxTplSysrefMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x3D), + (uint8_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxTplSysrefMaskBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxTplSysrefMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x3D), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxTplSysrefNShotCountBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxTplSysrefNShotCountBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x43), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxTplSysrefNShotEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxTplSysrefNShotEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x43), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxTplSysrefPhaseErrBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxTplSysrefPhaseErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x3D), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_JtxLinkJtxTplSysrefRcvdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfJtxLinkChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_JTX_LINK0) && + (baseAddr != ADRV9025_BF_JTX_LINK1) && + (baseAddr != ADRV9025_BF_JTX_LINK2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_JtxLinkJtxTplSysrefRcvdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x3D), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_orx.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_orx.c new file mode 100644 index 0000000..9ec396b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_orx.c @@ -0,0 +1,3916 @@ +/** + * \file Automatically generated file: adrv9025_bf_orx.c + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/adrv9025_bf_orx.h" +#include "./../../private/include/adrv9025_bf_hal.h" +#include "adi_common_error.h" + +int32_t adrv9025_OrxAgcEnableFastRecoveryLoopBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxAgcEnableFastRecoveryLoopBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxAgcEnableFastRecoveryLoopBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x9A), + (uint8_t)bfValue, + 0x40, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxAuxAdcDecimationCtlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxAuxAdcDecimationCtlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxAuxAdcDecimationCtlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1BC), + (uint8_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxAuxAdcPdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxAuxAdcPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxAuxAdcPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1BC), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxAuxAdcPdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxAuxAdcPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1BC), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxAuxAdcReadBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxAuxAdcReadBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1BE), + &rxBfData[0x0], + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1BD), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxAuxAdcReadbackLockBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxAuxAdcReadbackLockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxAuxAdcReadbackLockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1BC), + (uint8_t)bfValue, + 0x80, + 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxAuxAdcResetBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxAuxAdcResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxAuxAdcResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1BC), + (uint8_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxAuxAdcSelBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxAuxAdcSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxAuxAdcSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1BC), + (uint8_t)bfValue, + 0x6, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxAuxAdcSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxAuxAdcSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1BC), + &rxBfData[0], + 0x6, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxBbdcLoopback1TrackingEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxBbdcLoopback1TrackingEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxBbdcLoopback1TrackingEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x158), + (uint8_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxBbdcLoopback1TrackingEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxBbdcLoopback1TrackingEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x158), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxBbdcLoopback2TrackingEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxBbdcLoopback2TrackingEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxBbdcLoopback2TrackingEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x158), + (uint8_t)bfValue, + 0x40, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxBbdcLoopback2TrackingEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxBbdcLoopback2TrackingEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x158), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxBbdcLoopbackMShiftBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxBbdcLoopbackMShiftBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxBbdcLoopbackMShiftBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x159), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxBbdcLoopbackMShiftBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxBbdcLoopbackMShiftBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x159), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxBbdcMShiftBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxBbdcMShiftBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxBbdcMShiftBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x14E), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxBbdcMShiftBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxBbdcMShiftBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x14E), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxBbdcOrx2MShiftBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxBbdcOrx2MShiftBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxBbdcOrx2MShiftBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x15B), + (uint8_t)bfValue, + 0x7C, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxBbdcOrx2MShiftBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxBbdcOrx2MShiftBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x15B), + &rxBfData[0], + 0x7C, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxBbdcOrx2TrackingEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxBbdcOrx2TrackingEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxBbdcOrx2TrackingEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x15B), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxBbdcOrx2TrackingEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxBbdcOrx2TrackingEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x15B), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxBbdcTrackingEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxBbdcTrackingEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxBbdcTrackingEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x14F), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxBbdcTrackingEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxBbdcTrackingEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x14F), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxDecPowerBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxDecPowerBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x34), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxDynamicSlicerAgcSyncEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxDynamicSlicerAgcSyncEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxDynamicSlicerAgcSyncEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1D4), + (uint8_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxDynamicSlicerAgcSyncEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxDynamicSlicerAgcSyncEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1D4), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxDynamicSlicerModeEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxDynamicSlicerModeEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxDynamicSlicerModeEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1D4), + (uint8_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxDynamicSlicerModeEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxDynamicSlicerModeEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1D4), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxDynamicSlicerResendBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxDynamicSlicerResendBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxDynamicSlicerResendBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1D4), + (uint8_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxDynamicSlicerSyncHeadBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint32_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxDynamicSlicerSyncHeadBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxDynamicSlicerSyncHeadBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1D3), + (uint8_t)(bfValue >> 24)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1D2), + (uint8_t)(bfValue >> 16)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1D1), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1D0), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxDynamicSlicerSyncHeadBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint32_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxDynamicSlicerSyncHeadBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1D3), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1D2), + &rxBfData[0x1], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1D1), + &rxBfData[0x2], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1D0), + &rxBfData[0x3], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x4, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint32_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxFpEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxFpEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxFpEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x170), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxFpEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxFpEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x170), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxFpExponentBitsBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + adrv9025_BfOrxFpExponentBits_e bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ( + (bfValue != ADRV9025_BF_RX1_EXP_2 ) && + (bfValue != ADRV9025_BF_RX1_EXP_3 ) && + (bfValue != ADRV9025_BF_RX1_EXP_4 ) && + (bfValue != ADRV9025_BF_RX1_EXP_5 ) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxFpExponentBitsBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxFpExponentBitsBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x16E), + (uint8_t)bfValue, + 0x6, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxFpExponentBitsBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + adrv9025_BfOrxFpExponentBits_e* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxFpExponentBitsBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x16E), + &rxBfData[0], + 0x6, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (adrv9025_BfOrxFpExponentBits_e)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxFpFloatDataFormatBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxFpFloatDataFormatBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxFpFloatDataFormatBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x16E), + (uint8_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxFpFloatDataFormatBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxFpFloatDataFormatBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x16E), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxFpHideLeadingOnesBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxFpHideLeadingOnesBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxFpHideLeadingOnesBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x16E), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxFpHideLeadingOnesBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxFpHideLeadingOnesBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x16E), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxFpIntDataAttenBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxFpIntDataAttenBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxFpIntDataAttenBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x16F), + (uint8_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxFpIntDataAttenBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxFpIntDataAttenBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x16F), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxFpNanEncEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxFpNanEncEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxFpNanEncEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x16E), + (uint8_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxFpNanEncEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxFpNanEncEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x16E), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxFpRoundModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + adrv9025_BfOrxFpRoundMode_e bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ( + (bfValue != ADRV9025_BF_ROUNDTIESTOEVEN ) && + (bfValue != ADRV9025_BF_ROUNDTOWARDSPOSITIVE) && + (bfValue != ADRV9025_BF_ROUNDTOWARDSNEGATIVE) && + (bfValue != ADRV9025_BF_ROUNDTOWARDSZERO ) && + (bfValue != ADRV9025_BF_ROUNDTIESTOAWAY ) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxFpRoundModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxFpRoundModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x16E), + (uint8_t)bfValue, + 0xE0, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxFpRoundModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + adrv9025_BfOrxFpRoundMode_e* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxFpRoundModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x16E), + &rxBfData[0], + 0xE0, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (adrv9025_BfOrxFpRoundMode_e)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxGainCompEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxGainCompEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxGainCompEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x3A), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxGainCompEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxGainCompEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x3A), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxGainCompForExtGainBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxGainCompForExtGainBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxGainCompForExtGainBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x3D), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxGainCompForExtGainBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxGainCompForExtGainBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x3D), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxGainCompForTempGainBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxGainCompForTempGainBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxGainCompForTempGainBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x3D), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxGainCompForTempGainBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxGainCompForTempGainBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x3D), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxIntDataFormatBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxIntDataFormatBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxIntDataFormatBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x171), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxIntDataFormatBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxIntDataFormatBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x171), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxIntDataResolutionBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxIntDataResolutionBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxIntDataResolutionBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x171), + (uint8_t)bfValue, + 0x6, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxIntDataResolutionBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxIntDataResolutionBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x171), + &rxBfData[0], + 0x6, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxIntEmbedSlicerBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxIntEmbedSlicerBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxIntEmbedSlicerBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x171), + (uint8_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxIntEmbedSlicerBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxIntEmbedSlicerBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x171), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxIntEmbedSlicerNumberBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxIntEmbedSlicerNumberBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxIntEmbedSlicerNumberBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x171), + (uint8_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxIntEmbedSlicerNumberBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxIntEmbedSlicerNumberBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x171), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxIntEmbedSlicerPosBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxIntEmbedSlicerPosBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxIntEmbedSlicerPosBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x171), + (uint8_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxIntEmbedSlicerPosBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxIntEmbedSlicerPosBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x171), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxIntEvenParityBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxIntEvenParityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxIntEvenParityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x171), + (uint8_t)bfValue, + 0x80, + 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxIntEvenParityBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxIntEvenParityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x171), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxIntParitySupportBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxIntParitySupportBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxIntParitySupportBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x171), + (uint8_t)bfValue, + 0x40, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxIntParitySupportBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxIntParitySupportBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x171), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxIntSlicerLsbOnQBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxIntSlicerLsbOnQBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxIntSlicerLsbOnQBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x170), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxIntSlicerLsbOnQBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxIntSlicerLsbOnQBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x170), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxMaxSlicerOverrideBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxMaxSlicerOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxMaxSlicerOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1D5), + (uint8_t)bfValue, + 0x80, + 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxOrx1AgcGainIndexBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxOrx1AgcGainIndexBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0xBB), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxOrx1AgcManualGainIndexBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxOrx1AgcManualGainIndexBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxOrx1AgcManualGainIndexBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x75), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxOrx1AgcManualGainIndexBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxOrx1AgcManualGainIndexBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x75), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxOrx1AgcSetupBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxOrx1AgcSetupBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxOrx1AgcSetupBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x73), + (uint8_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxOrx1AgcSetupBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxOrx1AgcSetupBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x73), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxOrx2AgcGainIndexBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxOrx2AgcGainIndexBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0xBC), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxOrx2AgcManualGainIndexBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxOrx2AgcManualGainIndexBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxOrx2AgcManualGainIndexBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x76), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxOrx2AgcManualGainIndexBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxOrx2AgcManualGainIndexBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x76), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxOrx2AgcSetupBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxOrx2AgcSetupBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxOrx2AgcSetupBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x73), + (uint8_t)bfValue, + 0xC, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxOrx2AgcSetupBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxOrx2AgcSetupBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x73), + &rxBfData[0], + 0xC, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxRxTempGainCompBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 127U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxRxTempGainCompBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxRxTempGainCompBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x20), + (uint8_t)bfValue, + 0x7F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxRxTempGainCompBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxRxTempGainCompBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x7F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxRxdpSlicerPinCntrlGpioSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxRxdpSlicerPinCntrlGpioSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x197), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxRxdpSlicerPositionBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxRxdpSlicerPositionBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x3C), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxSlicerPinControlStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxSlicerPinControlStepBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxSlicerPinControlStepBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x3B), + (uint8_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_OrxSlicerPinControlStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxSlicerPinControlStepBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x3B), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxStatic3bitSlicerModeEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_OrxStatic3bitSlicerModeEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxStatic3bitSlicerModeEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1D4), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_pll_mem_map.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_pll_mem_map.c new file mode 100644 index 0000000..8ff0c30 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_pll_mem_map.c @@ -0,0 +1,294 @@ +/** + * \file Automatically generated file: adrv9025_bf_pll_mem_map.c + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/adrv9025_bf_pll_mem_map.h" +#include "./../../private/include/adrv9025_bf_hal.h" +#include "adi_common_error.h" + +int32_t adrv9025_PllMemMapAuxAdcReadyBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfPllMemMapChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_PLLS) && + (baseAddr != ADRV9025_BF_AUX_PLL) && + (baseAddr != ADRV9025_BF_CLK_PLL) && + (baseAddr != ADRV9025_BF_RF1_PLL) && + (baseAddr != ADRV9025_BF_RF2_PLL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_PllMemMapAuxAdcReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xE0), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_PllMemMapRx12SelLo2BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfPllMemMapChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_PLLS) && + (baseAddr != ADRV9025_BF_AUX_PLL) && + (baseAddr != ADRV9025_BF_CLK_PLL) && + (baseAddr != ADRV9025_BF_RF1_PLL) && + (baseAddr != ADRV9025_BF_RF2_PLL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_PllMemMapRx12SelLo2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xB0), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_PllMemMapRx34SelLo2BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfPllMemMapChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_PLLS) && + (baseAddr != ADRV9025_BF_AUX_PLL) && + (baseAddr != ADRV9025_BF_CLK_PLL) && + (baseAddr != ADRV9025_BF_RF1_PLL) && + (baseAddr != ADRV9025_BF_RF2_PLL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_PllMemMapRx34SelLo2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xB0), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_PllMemMapSynLockBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfPllMemMapChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_PLLS) && + (baseAddr != ADRV9025_BF_AUX_PLL) && + (baseAddr != ADRV9025_BF_CLK_PLL) && + (baseAddr != ADRV9025_BF_RF1_PLL) && + (baseAddr != ADRV9025_BF_RF2_PLL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_PllMemMapSynLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x2B), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_PllMemMapTx12SelLo2BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfPllMemMapChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_PLLS) && + (baseAddr != ADRV9025_BF_AUX_PLL) && + (baseAddr != ADRV9025_BF_CLK_PLL) && + (baseAddr != ADRV9025_BF_RF1_PLL) && + (baseAddr != ADRV9025_BF_RF2_PLL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_PllMemMapTx12SelLo2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xB0), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_PllMemMapTx34SelLo2BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfPllMemMapChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_PLLS) && + (baseAddr != ADRV9025_BF_AUX_PLL) && + (baseAddr != ADRV9025_BF_CLK_PLL) && + (baseAddr != ADRV9025_BF_RF1_PLL) && + (baseAddr != ADRV9025_BF_RF2_PLL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_PllMemMapTx34SelLo2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xB0), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_rx.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_rx.c new file mode 100644 index 0000000..551872c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_rx.c @@ -0,0 +1,11957 @@ +/** + * \file Automatically generated file: adrv9025_bf_rx.c + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/adrv9025_bf_rx.h" +#include "./../../private/include/adrv9025_bf_hal.h" +#include "adi_common_error.h" + +int32_t adrv9025_RxAdcOverloadResetEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAdcOverloadResetEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAdcOverloadResetEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1DD), + (uint8_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAdcOverloadResetEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAdcOverloadResetEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1DD), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAdcovrg2ndHighCounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAdcovrg2ndHighCounterBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAdcovrg2ndHighCounterBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x9C), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcAdcHighOvrgExceededCounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcAdcHighOvrgExceededCounterBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcAdcHighOvrgExceededCounterBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x70), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcAdcHighOvrgExceededCounterBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcAdcHighOvrgExceededCounterBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x70), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcAdcLowOvrgExceededCounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcAdcLowOvrgExceededCounterBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcAdcLowOvrgExceededCounterBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x71), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcAdcLowOvrgExceededCounterBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcAdcLowOvrgExceededCounterBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x71), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcAdcResetGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcAdcResetGainStepBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcAdcResetGainStepBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x8F), + (uint8_t)bfValue, + 0xF8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcAdcResetGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcAdcResetGainStepBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x8F), + &rxBfData[0], + 0xF8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcAdcovrgLowInt0CounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcAdcovrgLowInt0CounterBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcAdcovrgLowInt0CounterBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x8B), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcAdcovrgLowInt0CounterBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcAdcovrgLowInt0CounterBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x8B), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcAdcovrgLowInt1CounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcAdcovrgLowInt1CounterBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcAdcovrgLowInt1CounterBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x8C), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcAdcovrgLowInt1CounterBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcAdcovrgLowInt1CounterBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x8C), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcApdLowFreqErrorMitigationModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcApdLowFreqErrorMitigationModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcApdLowFreqErrorMitigationModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x8F), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcAttackDelayBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 63U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcAttackDelayBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcAttackDelayBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x57), + (uint8_t)bfValue, + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcAttackDelayBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcAttackDelayBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x57), + &rxBfData[0], + 0x3F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcChangeGainIfAdcovrgHighBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcChangeGainIfAdcovrgHighBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcChangeGainIfAdcovrgHighBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x7A), + (uint8_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcChangeGainIfAdcovrgHighBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcChangeGainIfAdcovrgHighBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x7A), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcChangeGainIfUlbthHighBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcChangeGainIfUlbthHighBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcChangeGainIfUlbthHighBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x7A), + (uint8_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcChangeGainIfUlbthHighBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcChangeGainIfUlbthHighBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x7A), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcDecGainGpioSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcDecGainGpioSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcDecGainGpioSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1CA), + (uint8_t)bfValue, + 0xF0, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcDecGainGpioSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcDecGainGpioSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1CA), + &rxBfData[0], + 0xF0, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcDecrGainStepSizeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcDecrGainStepSizeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcDecrGainStepSizeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x45), + (uint8_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcDecrGainStepSizeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcDecrGainStepSizeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x45), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcEnableFastRecoveryLoopBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcEnableFastRecoveryLoopBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcEnableFastRecoveryLoopBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x7A), + (uint8_t)bfValue, + 0x40, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcEnableFastRecoveryLoopBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcEnableFastRecoveryLoopBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x7A), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcEnableGainIndexUpdateBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcEnableGainIndexUpdateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x43), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_OrxAgcEnableGainIndexUpdateBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t orxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_ORX_CHANNELS) && + (baseAddr != ADRV9025_BF_ORX_CH0) && + (baseAddr != ADRV9025_BF_ORX_CH1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_OrxAgcEnableGainIndexUpdateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x65), + &orxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &orxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcEnableSyncPulseForGainCounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcEnableSyncPulseForGainCounterBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcEnableSyncPulseForGainCounterBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x7A), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcEnableSyncPulseForGainCounterBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcEnableSyncPulseForGainCounterBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x7A), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcGainIndexBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcGainIndexBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x9E), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcGainUpdateCounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint32_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 4194303U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcGainUpdateCounterBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcGainUpdateCounterBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x79), + (uint8_t)(bfValue >> 16), + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x78), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x77), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcGainUpdateCounterBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint32_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcGainUpdateCounterBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x79), + &rxBfData[0x0], + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x78), + &rxBfData[0x1], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x77), + &rxBfData[0x2], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x3, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint32_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcIncGainGpioSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcIncGainGpioSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcIncGainGpioSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1CA), + (uint8_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcIncGainGpioSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcIncGainGpioSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1CA), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcIncrGainStepSizeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcIncrGainStepSizeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcIncrGainStepSizeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x45), + (uint8_t)bfValue, + 0x38, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcIncrGainStepSizeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcIncrGainStepSizeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x45), + &rxBfData[0], + 0x38, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcLlbGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcLlbGainStepBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcLlbGainStepBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x4A), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcLlbGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcLlbGainStepBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x4A), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcLlbThresholdExceededCounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcLlbThresholdExceededCounterBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcLlbThresholdExceededCounterBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x6F), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcLlbThresholdExceededCounterBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcLlbThresholdExceededCounterBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x6F), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcLockLevelBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 127U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcLockLevelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcLockLevelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x46), + (uint8_t)bfValue, + 0x7F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcLockLevelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcLockLevelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x46), + &rxBfData[0], + 0x7F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcLowThsPreventGainIncBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcLowThsPreventGainIncBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcLowThsPreventGainIncBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x7A), + (uint8_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcLowThsPreventGainIncBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcLowThsPreventGainIncBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x7A), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcLower0ThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 127U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcLower0ThresholdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcLower0ThresholdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x6D), + (uint8_t)bfValue, + 0x7F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcLower0ThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcLower0ThresholdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x6D), + &rxBfData[0], + 0x7F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcLower0ThresholdExceededGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcLower0ThresholdExceededGainStepBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcLower0ThresholdExceededGainStepBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x74), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcLower0ThresholdExceededGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcLower0ThresholdExceededGainStepBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x74), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcLower1ThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcLower1ThresholdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcLower1ThresholdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x7D), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcLower1ThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcLower1ThresholdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x7D), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcLower1ThresholdExceededGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcLower1ThresholdExceededGainStepBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcLower1ThresholdExceededGainStepBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x76), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcLower1ThresholdExceededGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcLower1ThresholdExceededGainStepBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x76), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcManualGainIndexBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcManualGainIndexBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcManualGainIndexBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x53), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcManualGainIndexBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcManualGainIndexBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x53), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcManualGainPinControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcManualGainPinControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcManualGainPinControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x52), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcManualGainPinControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcManualGainPinControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x52), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcMaximumGainIndexBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcMaximumGainIndexBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcMaximumGainIndexBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x58), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcMaximumGainIndexBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcMaximumGainIndexBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x58), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcMinimumGainIndexBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcMinimumGainIndexBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcMinimumGainIndexBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x59), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcMinimumGainIndexBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcMinimumGainIndexBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x59), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcOvrgHighGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcOvrgHighGainStepBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcOvrgHighGainStepBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x48), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcOvrgHighGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcOvrgHighGainStepBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x48), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcOvrgLowGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcOvrgLowGainStepBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcOvrgLowGainStepBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x4B), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcOvrgLowGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcOvrgLowGainStepBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x4B), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcOvrgLowInt0GainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcOvrgLowInt0GainStepBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcOvrgLowInt0GainStepBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x8D), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcOvrgLowInt0GainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcOvrgLowInt0GainStepBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x8D), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcOvrgLowInt1GainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcOvrgLowInt1GainStepBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcOvrgLowInt1GainStepBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x8E), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcOvrgLowInt1GainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcOvrgLowInt1GainStepBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x8E), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcPeakThresholdGainControlModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcPeakThresholdGainControlModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcPeakThresholdGainControlModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x7A), + (uint8_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcPeakThresholdGainControlModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcPeakThresholdGainControlModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x7A), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcPeakWaitTimeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcPeakWaitTimeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcPeakWaitTimeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x43), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcPeakWaitTimeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcPeakWaitTimeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x43), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcResetOnRxonBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcResetOnRxonBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcResetOnRxonBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x7A), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcResetOnRxonBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcResetOnRxonBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x7A), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcSetupBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcSetupBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcSetupBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x51), + (uint8_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcSetupBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcSetupBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x51), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcSlowLoopSettlingDelayBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcSlowLoopSettlingDelayBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcSlowLoopSettlingDelayBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x7B), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcSlowLoopSettlingDelayBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcSlowLoopSettlingDelayBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x7B), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcSlowloopFastGainChangeBlockEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcSlowloopFastGainChangeBlockEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcSlowloopFastGainChangeBlockEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x44), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcSoftResetBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcSoftResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcSoftResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x44), + (uint8_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUlSigPowerMeasDelayBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcUlSigPowerMeasDelayBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUlSigPowerMeasDelayBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x7F), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x7E), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUlSigPowerMeasDelayBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUlSigPowerMeasDelayBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x7F), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x7E), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUlSigPowerMeasDurationBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcUlSigPowerMeasDurationBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUlSigPowerMeasDurationBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x81), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x80), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUlSigPowerMeasDurationBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUlSigPowerMeasDurationBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x81), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x80), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUlbGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcUlbGainStepBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUlbGainStepBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x47), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUlbGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUlbGainStepBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x47), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUlbThresholdExceededCounterBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcUlbThresholdExceededCounterBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUlbThresholdExceededCounterBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x6E), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUlbThresholdExceededCounterBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUlbThresholdExceededCounterBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x6E), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUpper0ThresholdExceededGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcUpper0ThresholdExceededGainStepBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUpper0ThresholdExceededGainStepBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x73), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUpper0ThresholdExceededGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUpper0ThresholdExceededGainStepBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x73), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUpper1ThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcUpper1ThresholdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUpper1ThresholdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x99), + (uint8_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUpper1ThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUpper1ThresholdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x99), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUpper1ThresholdExceededGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcUpper1ThresholdExceededGainStepBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUpper1ThresholdExceededGainStepBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x75), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUpper1ThresholdExceededGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUpper1ThresholdExceededGainStepBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x75), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUrangeInterval0BfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcUrangeInterval0BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUrangeInterval0BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x86), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x85), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUrangeInterval0BfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUrangeInterval0BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x86), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x85), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUrangeInterval1MultBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 63U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcUrangeInterval1MultBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUrangeInterval1MultBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x87), + (uint8_t)bfValue, + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUrangeInterval1MultBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUrangeInterval1MultBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x87), + &rxBfData[0], + 0x3F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUrangeInterval2MultBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 63U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcUrangeInterval2MultBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUrangeInterval2MultBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x88), + (uint8_t)bfValue, + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcUrangeInterval2MultBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcUrangeInterval2MultBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x88), + &rxBfData[0], + 0x3F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxApdHighSrcSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxApdHighSrcSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxApdHighSrcSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x5C), + (uint8_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxApdHighSrcSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxApdHighSrcSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x5C), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxApdLowSrcSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxApdLowSrcSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxApdLowSrcSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x5C), + (uint8_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxApdLowSrcSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxApdLowSrcSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x5C), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxArmOverrideControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxArmOverrideControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxArmOverrideControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1BF), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxArmOverrideControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxArmOverrideControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1BF), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxBbdcMShiftBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxBbdcMShiftBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxBbdcMShiftBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x178), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxBbdcMShiftBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxBbdcMShiftBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x178), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxBbdcTrackingEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxBbdcTrackingEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxBbdcTrackingEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x179), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxBbdcTrackingEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxBbdcTrackingEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x179), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxControlOutMuxAddressBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxControlOutMuxAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxControlOutMuxAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1C7), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecOverloadDurationCountBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDecOverloadDurationCountBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecOverloadDurationCountBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xF4), + (uint8_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecOverloadDurationCountBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecOverloadDurationCountBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xF4), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecOverloadPowerModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDecOverloadPowerModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecOverloadPowerModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xF5), + (uint8_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecOverloadPowerModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecOverloadPowerModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xF5), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecOverloadThresholdCountBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDecOverloadThresholdCountBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecOverloadThresholdCountBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xF4), + (uint8_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecOverloadThresholdCountBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecOverloadThresholdCountBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xF4), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecPowerBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecPowerBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0xC1), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecPowerEnableMeasBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDecPowerEnableMeasBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecPowerEnableMeasBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xB2), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecPowerEnableMeasBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecPowerEnableMeasBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xB2), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecPowerInputSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDecPowerInputSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecPowerInputSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xB2), + (uint8_t)bfValue, + 0x6, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecPowerInputSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecPowerInputSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xB2), + &rxBfData[0], + 0x6, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecPowerLogShiftBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDecPowerLogShiftBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecPowerLogShiftBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xB2), + (uint8_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecPowerLogShiftBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecPowerLogShiftBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xB2), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecPowerMeasurementDurationBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDecPowerMeasurementDurationBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecPowerMeasurementDurationBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xB3), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecPowerMeasurementDurationBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecPowerMeasurementDurationBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xB3), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecThresholdConfigBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDecThresholdConfigBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecThresholdConfigBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xF5), + (uint8_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecThresholdConfigBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecThresholdConfigBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xF5), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecimatedDataOverloadInt0LowerThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 16383U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDecimatedDataOverloadInt0LowerThresholdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecimatedDataOverloadInt0LowerThresholdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xFB), + (uint8_t)(bfValue >> 8), + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0xFA), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecimatedDataOverloadInt0LowerThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecimatedDataOverloadInt0LowerThresholdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xFB), + &rxBfData[0x0], + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0xFA), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecimatedDataOverloadInt1LowerThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 16383U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDecimatedDataOverloadInt1LowerThresholdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecimatedDataOverloadInt1LowerThresholdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xFD), + (uint8_t)(bfValue >> 8), + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0xFC), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecimatedDataOverloadInt1LowerThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecimatedDataOverloadInt1LowerThresholdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xFD), + &rxBfData[0x0], + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0xFC), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecimatedDataOverloadLowerThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 16383U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDecimatedDataOverloadLowerThresholdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecimatedDataOverloadLowerThresholdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xF9), + (uint8_t)(bfValue >> 8), + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0xF8), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecimatedDataOverloadLowerThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecimatedDataOverloadLowerThresholdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xF9), + &rxBfData[0x0], + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0xF8), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecimatedDataOverloadSecondaryUpperThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 16383U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDecimatedDataOverloadSecondaryUpperThresholdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecimatedDataOverloadSecondaryUpperThresholdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x101), + (uint8_t)(bfValue >> 8), + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x100), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecimatedDataOverloadUpperThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 16383U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDecimatedDataOverloadUpperThresholdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecimatedDataOverloadUpperThresholdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xF7), + (uint8_t)(bfValue >> 8), + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0xF6), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDecimatedDataOverloadUpperThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDecimatedDataOverloadUpperThresholdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xF7), + &rxBfData[0x0], + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0xF6), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxDynamicSlicerAgcSyncEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDynamicSlicerAgcSyncEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDynamicSlicerAgcSyncEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1F4), + (uint8_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDynamicSlicerAgcSyncEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDynamicSlicerAgcSyncEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1F4), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxDynamicSlicerModeEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDynamicSlicerModeEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDynamicSlicerModeEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1F4), + (uint8_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDynamicSlicerModeEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDynamicSlicerModeEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1F4), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxDynamicSlicerResendBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDynamicSlicerResendBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDynamicSlicerResendBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1F4), + (uint8_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDynamicSlicerSyncHeadBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint32_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxDynamicSlicerSyncHeadBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDynamicSlicerSyncHeadBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1F3), + (uint8_t)(bfValue >> 24)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1F2), + (uint8_t)(bfValue >> 16)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1F1), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1F0), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxDynamicSlicerSyncHeadBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint32_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxDynamicSlicerSyncHeadBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1F3), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1F2), + &rxBfData[0x1], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1F1), + &rxBfData[0x2], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1F0), + &rxBfData[0x3], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x4, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint32_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxEnableDecOverloadBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxEnableDecOverloadBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxEnableDecOverloadBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xF4), + (uint8_t)bfValue, + 0x80, + 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxEnableDecOverloadBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxEnableDecOverloadBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xF4), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxExternalSlicerPinControlStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxExternalSlicerPinControlStepBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxExternalSlicerPinControlStepBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xCA), + (uint8_t)bfValue, + 0x38, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxExternalSlicerPinControlStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxExternalSlicerPinControlStepBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xCA), + &rxBfData[0], + 0x38, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxFpEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxFpEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxFpEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1A0), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxFpEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxFpEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1A0), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxFpExponentBitsBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + adrv9025_BfRxFpExponentBits_e bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ( + (bfValue != ADRV9025_BF_RX1_EXP_2) && + (bfValue != ADRV9025_BF_RX1_EXP_3) && + (bfValue != ADRV9025_BF_RX1_EXP_4) && + (bfValue != ADRV9025_BF_RX1_EXP_5) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxFpExponentBitsBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxFpExponentBitsBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x19E), + (uint8_t)bfValue, + 0x6, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxFpExponentBitsBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + adrv9025_BfRxFpExponentBits_e* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxFpExponentBitsBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x19E), + &rxBfData[0], + 0x6, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (adrv9025_BfRxFpExponentBits_e)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxFpFloatDataFormatBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxFpFloatDataFormatBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxFpFloatDataFormatBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x19E), + (uint8_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxFpFloatDataFormatBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxFpFloatDataFormatBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x19E), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxFpHideLeadingOnesBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxFpHideLeadingOnesBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxFpHideLeadingOnesBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x19E), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxFpHideLeadingOnesBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxFpHideLeadingOnesBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x19E), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxFpIntDataAttenBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxFpIntDataAttenBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxFpIntDataAttenBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x19F), + (uint8_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxFpIntDataAttenBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxFpIntDataAttenBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x19F), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxFpNanEncEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxFpNanEncEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxFpNanEncEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x19E), + (uint8_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxFpNanEncEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxFpNanEncEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x19E), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxFpRoundModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + adrv9025_BfRxFpRoundMode_e bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ( + (bfValue != ADRV9025_BF_ROUNDTIESTOEVEN ) && + (bfValue != ADRV9025_BF_ROUNDTOWARDSPOSITIVE) && + (bfValue != ADRV9025_BF_ROUNDTOWARDSNEGATIVE) && + (bfValue != ADRV9025_BF_ROUNDTOWARDSZERO ) && + (bfValue != ADRV9025_BF_ROUNDTIESTOAWAY ) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxFpRoundModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxFpRoundModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x19E), + (uint8_t)bfValue, + 0xE0, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxFpRoundModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + adrv9025_BfRxFpRoundMode_e* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxFpRoundModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x19E), + &rxBfData[0], + 0xE0, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (adrv9025_BfRxFpRoundMode_e)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxGainCompEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxGainCompEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxGainCompEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xC9), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxGainCompEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxGainCompEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xC9), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxGainCompForExtGainBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxGainCompForExtGainBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxGainCompForExtGainBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xCC), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxGainCompForExtGainBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxGainCompForExtGainBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xCC), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxGainCompForTempGainBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxGainCompForTempGainBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxGainCompForTempGainBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xCC), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxGainCompForTempGainBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxGainCompForTempGainBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xCC), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxHb2HighSrcSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxHb2HighSrcSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxHb2HighSrcSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x5C), + (uint8_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxHb2HighSrcSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxHb2HighSrcSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x5C), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxHb2LowSrcSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxHb2LowSrcSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxHb2LowSrcSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x5C), + (uint8_t)bfValue, + 0xE0, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxHb2LowSrcSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxHb2LowSrcSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x5C), + &rxBfData[0], + 0xE0, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxHb2OverloadUseHb2InBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxHb2OverloadUseHb2InBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxHb2OverloadUseHb2InBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xF5), + (uint8_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxHb2OverloadUseHb2InBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxHb2OverloadUseHb2InBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xF5), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxIntDataFormatBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxIntDataFormatBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxIntDataFormatBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1A1), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxIntDataFormatBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxIntDataFormatBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1A1), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxIntDataResolutionBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxIntDataResolutionBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxIntDataResolutionBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1A1), + (uint8_t)bfValue, + 0x6, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxIntDataResolutionBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxIntDataResolutionBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1A1), + &rxBfData[0], + 0x6, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxIntEmbedSlicerBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxIntEmbedSlicerBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxIntEmbedSlicerBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1A1), + (uint8_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxIntEmbedSlicerBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxIntEmbedSlicerBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1A1), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxIntEmbedSlicerNumberBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxIntEmbedSlicerNumberBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxIntEmbedSlicerNumberBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1A1), + (uint8_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxIntEmbedSlicerNumberBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxIntEmbedSlicerNumberBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1A1), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxIntEmbedSlicerPosBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxIntEmbedSlicerPosBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxIntEmbedSlicerPosBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1A1), + (uint8_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxIntEmbedSlicerPosBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxIntEmbedSlicerPosBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1A1), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxIntEvenParityBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxIntEvenParityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxIntEvenParityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1A1), + (uint8_t)bfValue, + 0x80, + 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxIntEvenParityBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxIntEvenParityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1A1), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxIntParitySupportBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxIntParitySupportBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxIntParitySupportBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1A1), + (uint8_t)bfValue, + 0x40, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxIntParitySupportBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxIntParitySupportBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1A1), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxIntSlicerLsbOnQBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxIntSlicerLsbOnQBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxIntSlicerLsbOnQBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1A0), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxIntSlicerLsbOnQBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxIntSlicerLsbOnQBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1A0), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxInvertApdLowBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxInvertApdLowBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxInvertApdLowBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x5C), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxInvertApdLowBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxInvertApdLowBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x5C), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxInvertHb2LowBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxInvertHb2LowBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxInvertHb2LowBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x44), + (uint8_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxInvertHb2LowBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxInvertHb2LowBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x44), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxMaxSlicerOverrideBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxMaxSlicerOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxMaxSlicerOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1F5), + (uint8_t)bfValue, + 0x80, + 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxPcaGainControlModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxPcaGainControlModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxPcaGainControlModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x5D), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxPcaGainControlModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxPcaGainControlModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x5D), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxPcaGainIndexOffsetBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxPcaGainIndexOffsetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxPcaGainIndexOffsetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x5E), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxPcaGainIndexOffsetBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxPcaGainIndexOffsetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x5E), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxPcaGainStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxPcaGainStepBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxPcaGainStepBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x5F), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxPcaGainStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxPcaGainStepBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x5F), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxPcaPinSelBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxPcaPinSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxPcaPinSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1CC), + (uint8_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxPcaPinSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxPcaPinSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1CC), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxPcaUpdateManualGainModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxPcaUpdateManualGainModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxPcaUpdateManualGainModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x5D), + (uint8_t)bfValue, + 0x80, + 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxRxEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1BD), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1BD), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxFdDwellThreshBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxRxFdDwellThreshBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxFdDwellThreshBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1E3), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1E2), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxFdDwellThreshBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxFdDwellThreshBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1E3), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1E2), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxFdFineEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxRxFdFineEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxFdFineEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1DD), + (uint8_t)bfValue, + 0x80, + 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxFdLowThreshBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxRxFdLowThreshBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxFdLowThreshBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1E1), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1E0), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxFdLowThreshBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxFdLowThreshBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1E1), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1E0), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxFdUpThreshBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxRxFdUpThreshBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxFdUpThreshBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1DF), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1DE), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxFdUpThreshBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxFdUpThreshBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1DF), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1DE), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxFdUseEnvelopMeasBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxRxFdUseEnvelopMeasBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxFdUseEnvelopMeasBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1DD), + (uint8_t)bfValue, + 0x40, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxFdUseEnvelopMeasBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxFdUseEnvelopMeasBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1DD), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxMonFormatIBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxRxMonFormatIBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxMonFormatIBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_RxRxMonFormatIBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1A5 + channelId * 1), + (uint8_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxMonFormatIBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxMonFormatIBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_RxRxMonFormatIBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x1A5 + channelId * 1), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxMonFormatQBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxRxMonFormatQBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxMonFormatQBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_RxRxMonFormatQBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1A5 + channelId * 1), + (uint8_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxMonFormatQBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxMonFormatQBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); +#if ADRV9025_CHANNELID_CHECK > 0 + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid adrv9025_RxRxMonFormatQBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfFieldRead(device, + (baseAddr + 0x1A5 + channelId * 1), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxPinModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxRxPinModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxPinModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1BD), + (uint8_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxPinModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxPinModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1BD), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxSmonOffsetShiftBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxRxSmonOffsetShiftBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxSmonOffsetShiftBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1DC), + (uint8_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxSmonPeakEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxRxSmonPeakEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxSmonPeakEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1D4), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxSmonPeakEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxSmonPeakEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1D4), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxSmonPeriodBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint32_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 16777215U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxRxSmonPeriodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxSmonPeriodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1D7), + (uint8_t)(bfValue >> 16)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1D6), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x1D5), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxSmonPeriodBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint32_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxSmonPeriodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1D7), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1D6), + &rxBfData[0x1], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x1D5), + &rxBfData[0x2], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x3, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint32_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxSmonSourceBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxRxSmonSourceBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxSmonSourceBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1D4), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxSmonSourceBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxSmonSourceBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1D4), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxSmonSqrtEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxRxSmonSqrtEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxSmonSqrtEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1D4), + (uint8_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxSmonSqrtEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxSmonSqrtEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1D4), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxTempGainCompBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 127U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxRxTempGainCompBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxTempGainCompBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x40), + (uint8_t)bfValue, + 0x7F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxTempGainCompBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxTempGainCompBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x40), + &rxBfData[0], + 0x7F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxdpSlicerPinCntrlGpioSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxRxdpSlicerPinCntrlGpioSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxdpSlicerPinCntrlGpioSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1CD), + (uint8_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxdpSlicerPinCntrlGpioSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxdpSlicerPinCntrlGpioSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x1CD), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxRxdpSlicerPositionBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxRxdpSlicerPositionBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xCB), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxSlicerPinControlModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxSlicerPinControlModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxSlicerPinControlModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xC9), + (uint8_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxSlicerPinControlModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxSlicerPinControlModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xC9), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxSlicerPinControlStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxSlicerPinControlStepBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxSlicerPinControlStepBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xCA), + (uint8_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxSlicerPinControlStepBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxSlicerPinControlStepBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xCA), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_RxStatic3bitSlicerModeEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxStatic3bitSlicerModeEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxStatic3bitSlicerModeEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x1F4), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_RxAgcClkDivideRatioBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcClkDivideRatioBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_VALUE_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcClkDivideRatioBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = adrv9025_BfFieldWrite(device, (baseAddr + 0x1), (uint8_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_RxAgcClkDivideRatioBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* ADRV9025_BITFIELD_NULL_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcClkDivideRatioBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = adrv9025_BfFieldRead(device, (baseAddr + 0x1), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return recoveryAction; +} + +int32_t adrv9025_RxAgcDelayCounterBaseRateBfSet(adi_adrv9025_Device_t *device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxAgcDelayCounterBaseRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_VALUE_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcDelayCounterBaseRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Byte */ + recoveryAction = adrv9025_BfByteWrite(device, (baseAddr + 0x55), ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_RxAgcDelayCounterBaseRateBfGet(adi_adrv9025_Device_t *device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t *bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* ADRV9025_BITFIELD_NULL_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxAgcDelayCounterBaseRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Byte */ + recoveryAction = adrv9025_BfByteRead(device, (baseAddr + 0x55), &rxBfData[0], 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return recoveryAction; +} + +int32_t adrv9025_RxReferenceClockCyclesBfSet(adi_adrv9025_Device_t *device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_RxReferenceClockCyclesBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_VALUE_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxReferenceClockCyclesBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Byte */ + recoveryAction = adrv9025_BfByteWrite(device, (baseAddr + 0xA), ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_RxReferenceClockCyclesBfGet(adi_adrv9025_Device_t *device, + adrv9025_BfRxChanAddr_e baseAddr, + uint8_t *bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* ADRV9025_BITFIELD_NULL_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_ALL_RX_CHANNELS) && + (baseAddr != ADRV9025_BF_RX_CH0) && + (baseAddr != ADRV9025_BF_RX_CH1) && + (baseAddr != ADRV9025_BF_RX_CH2) && + (baseAddr != ADRV9025_BF_RX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_RxReferenceClockCyclesBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Byte */ + recoveryAction = adrv9025_BfByteRead(device, (baseAddr + 0xA), &rxBfData[0], 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return recoveryAction; +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_tx.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_tx.c new file mode 100644 index 0000000..4b65972 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_tx.c @@ -0,0 +1,4848 @@ +/** + * \file Automatically generated file: adrv9025_bf_tx.c + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/adrv9025_bf_tx.h" +#include "./../../private/include/adrv9025_bf_hal.h" +#include "adi_common_error.h" + +int32_t adrv9025_TxArmOverrideControlBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxArmOverrideControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxArmOverrideControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xEA), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxArmOverrideControlBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxArmOverrideControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xEA), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxCfrBasePulse21bBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxCfrBasePulse21bBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxCfrBasePulse21bBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xF), + (uint8_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxCfrBasePulse21bBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxCfrBasePulse21bBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xF), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxCfrHalfPulseLenBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxCfrHalfPulseLenBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x12), + &rxBfData[0x0], + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x11), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxDpdActClkEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxDpdActClkEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxDpdActClkEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x7), + (uint8_t)bfValue, + 0x40, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxDpdActClkEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxDpdActClkEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x7), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxJesdDfrmMaskBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxJesdDfrmMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxJesdDfrmMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x32), + (uint8_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxJesdDfrmMaskBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxJesdDfrmMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x32), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxNcoTestEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxNcoTestEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxNcoTestEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xC5), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxNcoTestEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxNcoTestEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xC5), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionAprEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionAprEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionAprEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x9A), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionAprEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionAprEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x9A), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionAveragePeakRatioBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionAveragePeakRatioBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xA6), + &rxBfData[0x0], + 0x7F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0xA5), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionAveragePowerBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionAveragePowerBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0xA4), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0xA3), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionAvgThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 8191U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionAvgThresholdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionAvgThresholdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x9C), + (uint8_t)(bfValue >> 8), + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x9B), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionAvgThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionAvgThresholdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x9C), + &rxBfData[0x0], + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x9B), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionAvgpowerEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionAvgpowerEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionAvgpowerEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x99), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionAvgpowerEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionAvgpowerEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x99), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionAvgpowerErrorBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionAvgpowerErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xA2), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionAvgpowerErrorClearBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionAvgpowerErrorClearBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionAvgpowerErrorClearBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xA2), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionAvgpowerErrorClearRequiredBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionAvgpowerErrorClearRequiredBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionAvgpowerErrorClearRequiredBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x99), + (uint8_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionAvrgDurBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionAvrgDurBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionAvrgDurBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x99), + (uint8_t)bfValue, + 0xF0, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionAvrgDurBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionAvrgDurBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x99), + &rxBfData[0], + 0xF0, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionErrorPowerBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionErrorPowerBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0xA8), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0xA7), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionGainRampDownEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionGainRampDownEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionGainRampDownEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xA0), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionGainRampDownEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionGainRampDownEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xA0), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionGainRampUpEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionGainRampUpEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionGainRampUpEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xA2), + (uint8_t)bfValue, + 0x80, + 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +/** + * \brief PA Protection Gain ramp Up Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::adrv9025_BfTxChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t adrv9025_TxPaProtectionGainRampUpEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif /* ADRV9025_BITFIELD_NULL_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionGainRampUpEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = adrv9025_BfFieldRead(device, + (baseAddr + 0xA2), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +int32_t adrv9025_TxPaProtectionGainStepDownEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionGainStepDownEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionGainStepDownEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x9F), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionInputSelBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionInputSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionInputSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x99), + (uint8_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionInputSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionInputSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x99), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionPeakCountBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionPeakCountBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionPeakCountBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x9E), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionPeakCountBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionPeakCountBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x9E), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionPeakDurBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionPeakDurBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionPeakDurBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x9A), + (uint8_t)bfValue, + 0xF0, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionPeakDurBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionPeakDurBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x9A), + &rxBfData[0], + 0xF0, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionPeakThresholdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 8191U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionPeakThresholdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionPeakThresholdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xAA), + (uint8_t)(bfValue >> 8), + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0xA9), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionPeakThresholdBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionPeakThresholdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xAA), + &rxBfData[0x0], + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0xA9), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionPeakpowerEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionPeakpowerEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionPeakpowerEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x9A), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionPeakpowerEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionPeakpowerEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x9A), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionPeakpowerErrorBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionPeakpowerErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xA2), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionPeakpowerErrorClearBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionPeakpowerErrorClearBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionPeakpowerErrorClearBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xA2), + (uint8_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionPeakpowerErrorClearRequiredBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionPeakpowerErrorClearRequiredBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionPeakpowerErrorClearRequiredBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x9A), + (uint8_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionRampMaxAttenuationBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 127U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionRampMaxAttenuationBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionRampMaxAttenuationBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xA0), + (uint8_t)bfValue, + 0xFE, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionRampMaxAttenuationBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionRampMaxAttenuationBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xA0), + &rxBfData[0], + 0xFE, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionRampStepDurationBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionRampStepDurationBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionRampStepDurationBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xA1), + (uint8_t)bfValue, + 0xF0, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionRampStepDurationBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionRampStepDurationBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xA1), + &rxBfData[0], + 0xF0, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionRampStepSizeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionRampStepSizeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionRampStepSizeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xA1), + (uint8_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionRampStepSizeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionRampStepSizeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xA1), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPaProtectionTxAttenStepBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 127U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPaProtectionTxAttenStepBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPaProtectionTxAttenStepBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x9F), + (uint8_t)bfValue, + 0xFE, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPllJesdProtClrBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPllJesdProtClrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPllJesdProtClrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x32), + (uint8_t)bfValue, + 0x40, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPllJesdProtClrReqdBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPllJesdProtClrReqdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPllJesdProtClrReqdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x32), + (uint8_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPllJesdProtEventBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPllJesdProtEventBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x32), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxPllUnlockMaskBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxPllUnlockMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPllUnlockMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x31), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxPllUnlockMaskBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxPllUnlockMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x31), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxSpi2TxAttenGpioSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxSpi2TxAttenGpioSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxSpi2TxAttenGpioSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xF1), + (uint8_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxSpi2TxAttenGpioSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxSpi2TxAttenGpioSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xF1), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxSrlIrqBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxSrlIrqBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x69), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxSrlIrqEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxSrlIrqEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxSrlIrqEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x69), + (uint8_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxSrlIrqEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxSrlIrqEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x69), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxSrlSlewOffsetBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxSrlSlewOffsetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxSrlSlewOffsetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x68), + (uint8_t)bfValue, + 0x1E, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxSrlSlewOffsetBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxSrlSlewOffsetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x68), + &rxBfData[0], + 0x1E, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxSrlStatBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxSrlStatBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x6A), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x6B), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxSrlStatEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxSrlStatEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxSrlStatEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x69), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxSrlStatEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxSrlStatEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x69), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxSrlStatModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxSrlStatModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxSrlStatModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x69), + (uint8_t)bfValue, + 0x6, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxSrlTableSelBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxSrlTableSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxSrlTableSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x68), + (uint8_t)bfValue, + 0xC0, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxSrlTableSelBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxSrlTableSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x68), + &rxBfData[0], + 0xC0, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxTpcDecrAttenGpioSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTpcDecrAttenGpioSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTpcDecrAttenGpioSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xF0), + (uint8_t)bfValue, + 0xF0, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxTpcDecrAttenGpioSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTpcDecrAttenGpioSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xF0), + &rxBfData[0], + 0xF0, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxTpcIncrAttenGpioSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTpcIncrAttenGpioSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTpcIncrAttenGpioSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xF0), + (uint8_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxTpcIncrAttenGpioSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTpcIncrAttenGpioSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xF0), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxAttenConfigBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTxAttenConfigBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxAttenConfigBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x30), + (uint8_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxAttenConfigBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxAttenConfigBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x30), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxAttenModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTxAttenModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxAttenModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x30), + (uint8_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxAttenUpdGpioEnBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTxAttenUpdGpioEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxAttenUpdGpioEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x42), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxAttenUpdGpioEnBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxAttenUpdGpioEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x42), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxAttenUpdGpioSelectBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTxAttenUpdGpioSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxAttenUpdGpioSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x42), + (uint8_t)bfValue, + 0x1E, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxAttenUpdGpioSelectBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxAttenUpdGpioSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x42), + &rxBfData[0], + 0x1E, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxAttenuationBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1023U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTxAttenuationBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxAttenuationBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x34), + (uint8_t)(bfValue >> 8), + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x33), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxAttenuationBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint16_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxAttenuationBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x34), + &rxBfData[0x0], + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x33), + &rxBfData[0x1], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x2, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint16_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxDataRampDownOnJesdDfrmIrqBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTxDataRampDownOnJesdDfrmIrqBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxDataRampDownOnJesdDfrmIrqBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x32), + (uint8_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxDataRampDownOnJesdDfrmIrqBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxDataRampDownOnJesdDfrmIrqBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x32), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxDataRampDownOnPllUnlockBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTxDataRampDownOnPllUnlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxDataRampDownOnPllUnlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x30), + (uint8_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxDataRampDownOnPllUnlockBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxDataRampDownOnPllUnlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x30), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxDpNcoEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTxDpNcoEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxDpNcoEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x88), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxDpNcoFtwBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint32_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTxDpNcoFtwBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxDpNcoFtwBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x89), + (uint8_t)(bfValue >> 24)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x8A), + (uint8_t)(bfValue >> 16)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x8B), + (uint8_t)(bfValue >> 8)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteWrite(device, + (baseAddr + 0x8C), + (uint8_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxDpNcoFtwBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint32_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxDpNcoFtwBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x89), + &rxBfData[0x0], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x8A), + &rxBfData[0x1], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x8B), + &rxBfData[0x2], + 0x00); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfByteRead(device, + (baseAddr + 0x8C), + &rxBfData[0x3], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x4, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint32_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxDpNcoFtwUpdateBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTxDpNcoFtwUpdateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxDpNcoFtwUpdateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x96), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxEnableBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTxEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xE8), + (uint8_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxEnableBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xE8), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxIncrDecrWordBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTxIncrDecrWordBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxIncrDecrWordBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x38), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxIncrDecrWordBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxIncrDecrWordBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x38), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxNcoGainBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTxNcoGainBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxNcoGainBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x88), + (uint8_t)bfValue, + 0xC0, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxNcoGainBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxNcoGainBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x88), + &rxBfData[0], + 0xC0, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxPinModeBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTxPinModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxPinModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0xE8), + (uint8_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxPinModeBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxPinModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0xE8), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (uint8_t)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxTxAttenuationEarlyDelayCounterForAnalogBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxTxAttenuationEarlyDelayCounterForAnalogBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_VALUE_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxAttenuationEarlyDelayCounterForAnalogBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Byte */ + recoveryAction = adrv9025_BfByteWrite(device, + (baseAddr + 0x3E), + ((uint8_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_TxTxAttenuationEarlyDelayCounterForAnalogBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif /* ADRV9025_BITFIELD_NULL_CHECK */ + +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != ADRV9025_BF_ALL_TX_CHANNELS) && + (baseAddr != ADRV9025_BF_TX_CH0) && + (baseAddr != ADRV9025_BF_TX_CH1) && + (baseAddr != ADRV9025_BF_TX_CH2) && + (baseAddr != ADRV9025_BF_TX_CH3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxTxAttenuationEarlyDelayCounterForAnalogBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* ADRV9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Byte */ + recoveryAction = adrv9025_BfByteRead(device, + (baseAddr + 0x3E), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_txdac_mem_map.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_txdac_mem_map.c new file mode 100644 index 0000000..7553ef8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_bf_txdac_mem_map.c @@ -0,0 +1,264 @@ +/** + * \file Automatically generated file: adrv9025_bf_txdac_mem_map.c + * + * \brief Contains BitField functions to support ADRV9025 transceiver device. + * + * ADRV9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/adrv9025_bf_txdac_mem_map.h" +#include "./../../private/include/adrv9025_bf_hal.h" +#include "adi_common_error.h" + +int32_t adrv9025_TxdacMemMapTxdacFscBoostIBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxdacMemMapChanAddr_e baseAddr, + adrv9025_BfTxdacMemMapTxdacFscBoostI_e bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ( + (bfValue != ADRV9025_BF_TXDAC_IDAC_FSC4MA ) && + (bfValue != ADRV9025_BF_TXDAC_IDAC_FSC5P6MA ) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxdacMemMapTxdacFscBoostIBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TXDAC) && + (baseAddr != ADRV9025_BF_TXDAC_CH1) && + (baseAddr != ADRV9025_BF_TXDAC_CH2) && + (baseAddr != ADRV9025_BF_TXDAC_CH3) && + (baseAddr != ADRV9025_BF_TXDAC_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxdacMemMapTxdacFscBoostIBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x20), + (uint8_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxdacMemMapTxdacFscBoostIBfGet(adi_adrv9025_Device_t* device, + adrv9025_BfTxdacMemMapChanAddr_e baseAddr, + adrv9025_BfTxdacMemMapTxdacFscBoostI_e* bfValue) +{ + uint8_t rxBfData[8] = {0}; + uint64_t data = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_NULL_CHECK > 0 + ADI_NULL_PTR_RETURN(&device->common, + bfValue); +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TXDAC) && + (baseAddr != ADRV9025_BF_TXDAC_CH1) && + (baseAddr != ADRV9025_BF_TXDAC_CH2) && + (baseAddr != ADRV9025_BF_TXDAC_CH3) && + (baseAddr != ADRV9025_BF_TXDAC_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxdacMemMapTxdacFscBoostIBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + *bfValue = (adrv9025_BfTxdacMemMapTxdacFscBoostI_e)data; + return device->common.error.newAction; +} + +int32_t adrv9025_TxdacMemMapTxdacFscBoostQBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxdacMemMapChanAddr_e baseAddr, + adrv9025_BfTxdacMemMapTxdacFscBoostQ_e bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ( + (bfValue != ADRV9025_BF_TXDAC_QDAC_FSC4MA ) && + (bfValue != ADRV9025_BF_TXDAC_QDAC_FSC5P6MA ) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxdacMemMapTxdacFscBoostQBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TXDAC) && + (baseAddr != ADRV9025_BF_TXDAC_CH1) && + (baseAddr != ADRV9025_BF_TXDAC_CH2) && + (baseAddr != ADRV9025_BF_TXDAC_CH3) && + (baseAddr != ADRV9025_BF_TXDAC_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxdacMemMapTxdacFscBoostQBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x21), + (uint8_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxdacMemMapTxdacFscTuneIBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxdacMemMapChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxdacMemMapTxdacFscTuneIBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TXDAC) && + (baseAddr != ADRV9025_BF_TXDAC_CH1) && + (baseAddr != ADRV9025_BF_TXDAC_CH2) && + (baseAddr != ADRV9025_BF_TXDAC_CH3) && + (baseAddr != ADRV9025_BF_TXDAC_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxdacMemMapTxdacFscTuneIBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x20), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adrv9025_TxdacMemMapTxdacFscTuneQBfSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxdacMemMapChanAddr_e baseAddr, + uint8_t bfValue) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); +#if ADRV9025_BITFIELD_VALUE_CHECK > 0 + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid adrv9025_TxdacMemMapTxdacFscTuneQBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif +#if ADRV9025_BITFIELD_ADDR_CHECK > 0 + if ((baseAddr != ADRV9025_BF_ALL_TXDAC) && + (baseAddr != ADRV9025_BF_TXDAC_CH1) && + (baseAddr != ADRV9025_BF_TXDAC_CH2) && + (baseAddr != ADRV9025_BF_TXDAC_CH3) && + (baseAddr != ADRV9025_BF_TXDAC_CH0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid adrv9025_TxdacMemMapTxdacFscTuneQBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + adrv9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfFieldWrite(device, + (baseAddr + 0x21), + (uint8_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_cals.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_cals.c new file mode 100644 index 0000000..55b8c8f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_cals.c @@ -0,0 +1,93 @@ +/** + * \file adrv9025_cals.c + * \brief Contains ADRV9025 calibration related private function implementation + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_error.h" +#include "adi_adrv9025_cpu.h" +#include "adi_adrv9025_cals_types.h" +#include "../../private/include/adrv9025_cals.h" +#include "../../private/include/adrv9025_reg_addr_macros.h" +#include "../../private/include/adrv9025_cpu_macros.h" +#include "../../private/include/adrv9025_init.h" +#include "../../private/include/adrv9025_cpu.h" + +#include /* needed for memset */ + +#ifdef _RELEASE_BUILD_ +#line __LINE__ "adrv9025_cals.c" +#endif + +const char* adrv9025_CalsErrMsgGet(adi_adrv9025_Device_t* device, + uint32_t errCode) +{ +#if ADI_ADRV9025_ARM_VERBOSE == 0 + UNUSED_PARA(device); + UNUSED_PARA(errCode); + return ""; +#else + const char *errorString = NULL; + + if (errCode > 0) + { + errorString = adrv9025_CpuErrCodeToString(device, errCode); + + if (errorString != NULL) + { + return (errorString); + } + } + + return "Unknown Init Calibration Error\n"; +#endif +} + +int32_t adrv9025_InitCalStructureCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_InitCals_t* initCals) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + initCals); + + /* Check if the mask is out of range*/ + if (initCals->calMask > ADI_ADRV9025_MAX_INIT_CAL_MASK) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + initCals->calMask, + "Invalid Initcal Cal Mask Selected - Mask contains one more more invalid bits"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((initCals->channelMask < ADI_ADRV9025_CAL_CH_1) || (initCals->channelMask > ADI_ADRV9025_CAL_CH_ALL)) + { + /* Error condition channelMask is outside range of allowed values */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + initCals->channelMask, + "Invalid Initcal Channel Mask - Channel Mask out of range (0x01 - 0x0F)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* No errors found return ADI_COMMON_ACT_NO_ACTION */ + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_cpu.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_cpu.c new file mode 100644 index 0000000..a353faf --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_cpu.c @@ -0,0 +1,3766 @@ +/** +* \file adrv9025_cpu.c +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +/** +* \file adrv9025_cpu.c +* \brief Contains CPU private features related function implementation defined in +* adrv9025_cpu.h +* +* ADRV9025 API Version: 6.4.0.14 +*/ +#include +#include + +#include "adi_adrv9025_user.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_cpu.h" +#include "adi_adrv9025_cpu_types.h" +#include "adi_adrv9025_error.h" +#include "adi_common_error.h" +#include "../../private/include/adrv9025_cpu.h" +#include "../../private/include/adrv9025_cpu_macros.h" +#include "../../private/include/adrv9025_reg_addr_macros.h" +#include "../../private/include/adrv9025_init.h" +#include "../../private/include/adrv9025_cpu_error_mapping.h" +#include "../../private/include/adrv9025_crc32.h" + +#ifdef _RELEASE_BUILD_ +#line __LINE__ "adrv9025_cpu.c" +#endif + +#define ADRV9025_PROFILE_CHUNK_MAX 256u + +/*****************************************************************************/ +/***** Local data types ******************************************************/ +/*****************************************************************************/ +enum adrv9025_CpuErrorFlag +{ + ADRV9025_CPU_ERROR_FLAG_INVALID = 0, + ADRV9025_CPU_ERROR_FLAG_1, + ADRV9025_CPU_ERROR_FLAG_2, + ADRV9025_CPU_ERROR_FLAG_3, + ADRV9025_CPU_ERROR_FLAG_4, + ADRV9025_CPU_ERROR_FLAG_5, + ADRV9025_CPU_ERROR_FLAG_6, + ADRV9025_CPU_ERROR_FLAG_7 +}; + +/*****************************************************************************/ +/***** Helper functions' prototypes ******************************************/ +/*****************************************************************************/ +static uint8_t adrv9025_cpuTypeIsValid( + adi_adrv9025_CpuType_e type); + +static void adrv9025_CpuAddrInitialize( + adi_adrv9025_CpuAddr_t* cpuAddr, + adi_adrv9025_CpuType_e type); + +static uint8_t adrv9025_CpuIsAddrInProgRegion( + adi_adrv9025_Cpu_t* cpu, + uint32_t addr); + +static int32_t adrv9025_CpuDmaSetup( + adi_adrv9025_Device_t* device, + uint32_t address, + uint8_t isWrite, + uint8_t isByte, + uint8_t autoInc); + +static int32_t adrv9025_CpuDmaMemWriteByte( + adi_adrv9025_Device_t* device, + uint32_t address, + const uint8_t data[], + uint32_t byteCount, + uint8_t autoInc); + +static adi_adrv9025_CpuType_e adrv9025_CpuWhichTypeAddressBelongs( + adi_adrv9025_Cpu_t* cpu, + uint32_t addr); + +static int32_t adrv9025_CpuDmaMemReadByte( + adi_adrv9025_Device_t* device, + uint32_t address, + uint8_t returnData[], + uint32_t byteCount, + uint8_t autoIncrement); + +static int32_t adrv9025_CpuMailBoxErrCodeGet( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint16_t* mailboxErrCode); + +static const char* adrv9025_CpuErrMsgGet( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint32_t errCode, + uint16_t* mailboxErrCodeRet); + +static enum adrv9025_CpuErrorFlag adrv9025_CpuErrorFlagGet( + uint32_t err); + +static void adrv9025_CpuDataSet( + uint8_t* cfgData, + uint8_t value, + int count); + +static void adrv9025_CpuLoadAdcBytes( + uint32_t start, + uint8_t cfgData[], + const uint16_t* data); + +static void adrv9025_CpuLoadTwoBytes( + uint32_t start, + uint8_t cfgData[], + const uint16_t data); + +static void adrv9025_CpuLoadFourBytes( + uint32_t start, + uint8_t cfgData[], + const uint32_t data); + +static void adrv9025_CpuLoadRxBytes( + uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_RxProfile_t* rxProfile); + +static void adrv9025_CpuLoadOrxBytes( + uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_RxProfile_t* rxProfile); + +static void adrv9025_CpuLoadTxByte( + uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_TxProfile_t* txProfile); + +static void adrv9025_CpuLoadFramerBytes( + uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_FrmCfg_t* framer); + +static void adrv9025_CpuLoadDeframerBytes( + uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_DfrmCfg_t* deframer); + +static void adrv9025_CpuLoadLinkSharing( + uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_LinkSharingCfg_t* linkSharing); + +static void adrv9025_CpuLoadSerBytes( + uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_SerCfg_t* serdes); + +static void adrv9025_CpuLoadDesBytes( + uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_DesCfg_t* serdes); + +static void adrv9025_CpuLoadNoiseCancelBytes( + uint32_t start, + uint8_t cfgData[]); + +static void adrv9025_CpuLoadDataConfig( + uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_JesdDataConfigCtrl_t* dataCfg); + +static int32_t adrv9025_SpiCfgSet( + adi_adrv9025_Device_t* device, + adi_adrv9025_SpiSettings_t* spi); + +static uint8_t adrv9025_DesCfgHasData( + adi_adrv9025_Device_t* device, + adi_adrv9025_DesCfg_t* config); + +/*****************************************************************************/ +/***** Helper functions' definition ******************************************/ +/*****************************************************************************/ + +int32_t adrv9025_SpiCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_SpiSettings_t* spi) +{ + uint8_t spiConfigA = 0; + uint8_t spiConfigB = 0; + uint8_t ioControl = 0; + static const uint8_t SPICFG_MSBFIRST_OFF = 0; + static const uint8_t SPICFG_AUTOINC_DOWN = 0; + static const uint8_t SPICFG_FOURWIREMODE_OFF = 0; + static const uint8_t SPICFG_ENSPISTREAMING_OFF = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + spi); + + ADRV9025_BUGINFO(__FUNCTION__); + + if ((spi->cmosPadDrvStrength != ADI_ADRV9025_CMOSPAD_DRV_WEAK) && + (spi->cmosPadDrvStrength != ADI_ADRV9025_CMOSPAD_DRV_STRONG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + spi->cmosPadDrvStrength, + "Invalid Cmos Pad Drive Strength\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* core.spi_interface_config_A */ + /* SPI bit is 1 = LSB first */ + if (spi->msbFirst == SPICFG_MSBFIRST_OFF) + { + spiConfigA |= ADRV9025_CONFIG_A_SPI_LSB_FIRST; + } + + if (spi->autoIncAddrUp != SPICFG_AUTOINC_DOWN) + { + spiConfigA |= ADRV9025_CONFIG_A_SPI_ADDR_ASCENSION; + } + + if (spi->fourWireMode != SPICFG_FOURWIREMODE_OFF) + { + spiConfigA |= ADRV9025_CONFIG_A_SPI_SDO_ACTIVE; + } + + ADRV9025_SPIWRITEBYTE("SPI_INTERFACE_CONFIG_A", + ADRV9025_ADDR_SPI_INTERFACE_CONFIG_A, + spiConfigA); + + if (spi->cmosPadDrvStrength == ADI_ADRV9025_CMOSPAD_DRV_STRONG) + { + ioControl |= ADRV9025_IO_CONTROL_SPI_OUTS_DRV_SEL; + } + + /* Force PAD mode */ + ADRV9025_SPIWRITEBYTE("DIGITAL_IO_CONTROL", + ADRV9025_ADDR_DIGITAL_IO_CONTROL, + ioControl); + + /* core.spi_interface_config_B */ + if (spi->enSpiStreaming == SPICFG_ENSPISTREAMING_OFF) + { + spiConfigB |= ADRV9025_CONFIG_B_SINGLE_INSTRUCTION; + } + + /* Force single instruction mode */ + ADRV9025_SPIWRITEBYTE("SPI_INTERFACE_CONFIG_B", + ADRV9025_ADDR_SPI_INTERFACE_CONFIG_B, + spiConfigB); + + return (device->common.error.newAction); +} + +/* +NCO Shifter Structure NcoShifter_t +Size : 16 bytes +Element Type Range Description +Band InputBandWidth uint32 BandWidth in Hz of the Band input signal +Band InputCenterFreq int32 Center freq in Hz of the Band input signal +Band Nco1Freq int32 Band NCO1 Frequency shift in Hz +Band Nco2Freq int32 Band NCO2 Frequency shift in Hz +Table 5 - NCO Shifter Structure + +*/ + +/* +Element Type Range Description +primaryBwHz +uint32 20-300 Mhz Primary Rx baseband bandwidth in Hz. +Corner3db uint32 112-300 Mhz 3db corner in Hz used for TIA calibration. +rxOutputRateHz uint32 30.72-368.64 Mhz +Rx sample rate in Hz. + +ADC Corner uint32 < 225 Mhz ADC corner freq in Hz +NCO Shifter A NcoShifter_t [16] NCO Shifter +NCO Shifter B NcoShifter_t [16] NCO Shifter +TIA Power Setting uint8 0-3 TIA Power Setting +dec5Enable uint8 1 or 5 Use Dec 5 filter = 5 + +fir2Enable uint8 1 or 2 Fir2 enable. +fir1Enable uint8 1 or 2 Fir1 enable. +hb3Enable uint8 1 or 2 HB3 enable. +hb2Enable uint8 1 or 2 HB2 enable. +hb1Enable uint8 1 or 2 HB1 enable. +pfirNumTaps uint8 24-96 in incr of 24. +0 = bypassed. Number of PFIR taps. For bypass, set pfirNumTaps = 0, pfirDecimation=1. +pfirDecimation uint8 1,2,4 PFIR decimation. +ddcHBMode uint8 0-7 +DDC HB mode: +0: No Half Band Enabled +1: Half Band Filters only +2: Half Band Interpolation by 2 +3: Half Band Decimate by 2 +4: No Half Band Enabled (Real I/F MODE) +5: Half Band Filters only (Real I/F MODE) +6: Half Band Interpolation by 2 (Real I/F MODE) +7: Half Band Decimate by 2 (Real I/F MODE) +Bit 7: 1 = Combine dualband AB, 0 disable combine dualband on AB. +RxHb1WidebandEnable uint8 0, 1 1 = Wide band select, 0 = Narrow band select +Reserved[13] uint8 13 bytes reserved. + +*/ +void adrv9025_CpuLoadRxBytes(uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_RxProfile_t* rxProfile) +{ + adrv9025_CpuLoadFourBytes(start + 0, + cfgData, + rxProfile->rfBandwidth_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 4, + cfgData, + rxProfile->rxBbf3dBCorner_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 8, + cfgData, + rxProfile->rxOutputRate_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 12, + cfgData, + rxProfile->rxAdcBandWidth_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 16, + cfgData, + rxProfile->rxNcoShifterCfg.bandAInputBandWidth_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 20, + cfgData, + rxProfile->rxNcoShifterCfg.bandAInputCenterFreq_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 24, + cfgData, + rxProfile->rxNcoShifterCfg.bandANco1Freq_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 28, + cfgData, + rxProfile->rxNcoShifterCfg.bandANco2Freq_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 32, + cfgData, + rxProfile->rxNcoShifterCfg.bandBInputBandWidth_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 36, + cfgData, + rxProfile->rxNcoShifterCfg.bandBInputCenterFreq_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 40, + cfgData, + rxProfile->rxNcoShifterCfg.bandBNco1Freq_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 44, + cfgData, + rxProfile->rxNcoShifterCfg.bandBNco2Freq_kHz * 1000); + cfgData[start + 48] = rxProfile->tiaPowerMode; + cfgData[start + 49] = rxProfile->rxDec5Decimation; + cfgData[start + 50] = rxProfile->rxFir2Decimation; + cfgData[start + 51] = rxProfile->rxFir1Decimation; + cfgData[start + 52] = rxProfile->rhb3Decimation; + cfgData[start + 53] = rxProfile->rhb2Decimation; + cfgData[start + 54] = rxProfile->rhb1Decimation; + cfgData[start + 55] = rxProfile->rxFir.numFirCoefs; + cfgData[start + 56] = rxProfile->rxFirDecimation; + /* For bypass, set pfirNumTaps = 0, pfirDecimation=1. */ + if (rxProfile->rxFir.numFirCoefs == 0) + { + cfgData[start + 56] = 1; /* rxProfile->rxFirDecimation; */ + } + + if (rxProfile->rxNcoShifterCfg.bandAbCombinedEnable == 1) + { + cfgData[start + 57] = rxProfile->rxDdcMode | 0x80; /* Set left most bit */ + } + else + { + cfgData[start + 57] = rxProfile->rxDdcMode; + } + + cfgData[start + 58] = rxProfile->rhb1WideBandMode; + cfgData[start + 59] = 0; + + cfgData[start + 60] = 0; + cfgData[start + 61] = 0; + cfgData[start + 62] = 0; + cfgData[start + 63] = 0; + + cfgData[start + 64] = 0; + cfgData[start + 65] = 0; + cfgData[start + 66] = 0; + cfgData[start + 67] = 0; + + cfgData[start + 68] = 0; + cfgData[start + 69] = 0; + cfgData[start + 70] = 0; + cfgData[start + 71] = 0; +} + +/* +Orx Baseband Receiver Structure : OrxConfig_t +Size : 56 bytes +Element Type Range Description +RfBw +uint32 112-450 Mhz Total baseband RF Bandwidth in Hz. +Corner3dB uint32 112-450 Mhz 3db corner in Hz used for TIA calibration. +orxOutputRateHz uint32 112.88 -491.52 Mhz +Orx Output Rate in Hz. +ADC Corner uint32 < 225 Mhz ADC corner freq in Hz +NCO Shifter NcoShifter_t [16] NCO Shifter +TIA Power Setting uint8 0-3 TIA Power Setting +dec5Enable uint8 1 or 5 Decimation 4/5. +fir1Enable uint8 1 or 2 Fir1 enable. +hb3Enable uint8 1 or 2 HB3 enable. +hb2Enable uint8 1 or 2 HB2 enable. +hb1Enable uint8 1 or 2 HB1 enable. +pfirNumTaps uint8 24-96 in incr of 24. +0 = bypassed. Number of PFIR taps. For bypass, set pfirNumTaps = 0, pfirDecimation=1. +pfirDecimation uint8 1,2,4 PFIR decimation. +ddcHBMode uint8 0,1,2 DDC HB mode: +0: No Half Band Enabled +1: Half Band Filters only +2: Half Band Interpolation by 2 +3: Half Band Decimate by 2 +4: No Half Band Enabled (Real I/F MODE) +5: Half Band Filters only (Real I/F MODE) +6: Half Band Interpolation by 2 (Real I/F MODE) +7: Half Band Decimate by 2 (Real I/F MODE) +Reserved[15] uint8 15 bytes reserved. +Table 5 - Orx Profile Structure + +*/ +void adrv9025_CpuLoadOrxBytes(uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_RxProfile_t* rxProfile) +{ + adrv9025_CpuLoadFourBytes(start + 0, + cfgData, + rxProfile->rfBandwidth_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 4, + cfgData, + rxProfile->rxBbf3dBCorner_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 8, + cfgData, + rxProfile->rxOutputRate_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 12, + cfgData, + rxProfile->rxAdcBandWidth_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 16, + cfgData, + rxProfile->rxNcoShifterCfg.bandAInputBandWidth_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 20, + cfgData, + rxProfile->rxNcoShifterCfg.bandAInputCenterFreq_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 24, + cfgData, + rxProfile->rxNcoShifterCfg.bandANco1Freq_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 28, + cfgData, + rxProfile->rxNcoShifterCfg.bandANco2Freq_kHz * 1000); + cfgData[start + 32] = rxProfile->tiaPowerMode; + cfgData[start + 33] = rxProfile->rxDec5Decimation; + cfgData[start + 34] = rxProfile->rxFir1Decimation; + cfgData[start + 35] = rxProfile->rhb3Decimation; + cfgData[start + 36] = rxProfile->rhb2Decimation; + cfgData[start + 37] = rxProfile->rhb1Decimation; + cfgData[start + 38] = rxProfile->rxFir.numFirCoefs; + cfgData[start + 39] = rxProfile->rxFirDecimation; + /* For bypass, set pfirNumTaps = 0, pfirDecimation=1. */ + if (rxProfile->rxFir.numFirCoefs == 0) + { + cfgData[start + 39] = 1; /* rxProfile->rxFirDecimation; */ + } + + cfgData[start + 40] = rxProfile->rxDdcMode; + cfgData[start + 41] = 0; + cfgData[start + 42] = 0; + cfgData[start + 43] = 0; + + cfgData[start + 44] = 0; + cfgData[start + 45] = 0; + cfgData[start + 46] = 0; + cfgData[start + 47] = 0; + + cfgData[start + 48] = 0; + cfgData[start + 49] = 0; + cfgData[start + 50] = 0; + cfgData[start + 51] = 0; + + cfgData[start + 52] = 0; + cfgData[start + 53] = 0; + cfgData[start + 54] = 0; + cfgData[start + 55] = 0; +} + +/* +Transmitter Structure: TxConfig_t +Size : 40 Bytes +Element Type Range Description +primaryBwHz +uint32 50-200 Mhz Primary Tx baseband bandwidth in Hz. +DpdBwHz +uint32 112-491 Mhz Primary DPD Tx bandwidth in Hz. +Butter filter fc uint32 50-225 Mhz TxBBF filter tuning value in Hz. +Pre-PD Real pole fc uint32 112-491 Mhz ???? +TxInputRateHz uint32 ???? Transmitter input rate in Hz. +TxDpdHb1Enable +uint8 1 or 2 DPD Halfband 1 setting. +TxDpdHb2Enable +uint8 1 or 2 DPD Halfband 2 setting. +TxPfirInter +uint8 0, 1, 2, 4 +Transmitter Pfir interpolation. +TxThb1Enable +uint8 1 or 2 Transmitter Halfband 1 setting. +TxThb2Enable +uint8 1 or 2 Transmitter Halfband 2 setting. +TxThb3Enable +uint8 1 or 2 Transmitter Halfband 3 setting. +TxInt5Enable +uint8 1 or 5 Transmitter interpolate setting. +pfirNumTaps +uint8 20-100 24-96 in incr of 20 Transmitter number of Pfir tap. +Reserved[12] uint8 12 bytes reserved. +Table 4 - Tx Profile Structure + +*/ +void adrv9025_CpuLoadTxByte(uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_TxProfile_t* txProfile) +{ + adrv9025_CpuLoadFourBytes(start + 0, + cfgData, + txProfile->primarySigBandwidth_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 4, + cfgData, + txProfile->rfBandwidth_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 8, + cfgData, + txProfile->txBbf3dBCorner_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 12, + cfgData, + txProfile->txDac3dBCorner_kHz * 1000); + adrv9025_CpuLoadFourBytes(start + 16, + cfgData, + txProfile->txInputRate_kHz * 1000); + cfgData[start + 20] = txProfile->dpdHb1Interpolation; + cfgData[start + 21] = txProfile->dpdHb2Interpolation; + cfgData[start + 22] = txProfile->txFirInterpolation; + cfgData[start + 23] = txProfile->thb1Interpolation; + cfgData[start + 24] = txProfile->thb2Interpolation; + cfgData[start + 25] = txProfile->thb3Interpolation; + cfgData[start + 26] = txProfile->txInt5Interpolation; + cfgData[start + 27] = txProfile->txFir.numFirCoefs; + cfgData[start + 28] = txProfile->txBbfPowerMode; + cfgData[start + 29] = 0; + cfgData[start + 30] = 0; + cfgData[start + 31] = 0; + + cfgData[start + 32] = 0; + cfgData[start + 33] = 0; + cfgData[start + 34] = 0; + cfgData[start + 35] = 0; + + cfgData[start + 36] = 0; + cfgData[start + 37] = 0; + cfgData[start + 38] = 0; + cfgData[start + 39] = 0; +} + +/* +JESD Framer Init: JESD_FramerConfig_t +Size : 53 Bytes +*/ +void adrv9025_CpuLoadFramerBytes(uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_FrmCfg_t* framer) +{ + uint8_t newSysref = ((framer->newSysrefOnRelink > 0 ? 1 : 0) | + ((framer->sysrefForStartup > 0 ? 1 : 0) << 1) | + ((framer->sysrefNShotCount & 0x0F) << 2) | + ((framer->sysrefNShotEnable > 0 ? 1 : 0) << 6) | + ((framer->sysrefIgnoreWhenLinked > 0 ? 1 : 0) << 7)); + uint8_t offset = 0; + + cfgData[start + offset++] = framer->enableJesd204C; + cfgData[start + offset++] = framer->jesd204E; + cfgData[start + offset++] = framer->bankId; + cfgData[start + offset++] = framer->deviceId; + cfgData[start + offset++] = framer->lane0Id; + cfgData[start + offset++] = framer->jesd204M; + cfgData[start + offset++] = framer->jesd204K - 1; + cfgData[start + offset++] = framer->jesd204F; + cfgData[start + offset++] = framer->jesd204Np; + cfgData[start + offset++] = framer->scramble; + cfgData[start + offset++] = framer->serializerLanesEnabled; + cfgData[start + offset++] = (framer->lmfcOffset & 0xFF); + cfgData[start + offset++] = ((framer->lmfcOffset >> 8) & 0xFF); + cfgData[start + offset++] = newSysref; + cfgData[start + offset++] = framer->syncbInSelect; + cfgData[start + offset++] = framer->overSample; + cfgData[start + offset++] = framer->syncbInLvdsMode; + cfgData[start + offset++] = framer->syncbInLvdsPnInvert; + cfgData[start + offset++] = framer->serializerLaneCrossbar.lane0FramerOutSel; + cfgData[start + offset++] = framer->serializerLaneCrossbar.lane1FramerOutSel; + cfgData[start + offset++] = framer->serializerLaneCrossbar.lane2FramerOutSel; + cfgData[start + offset++] = framer->serializerLaneCrossbar.lane3FramerOutSel; + cfgData[start + offset++] = framer->adcCrossbar.conv0; + cfgData[start + offset++] = framer->adcCrossbar.conv1; + cfgData[start + offset++] = framer->adcCrossbar.conv2; + cfgData[start + offset++] = framer->adcCrossbar.conv3; + cfgData[start + offset++] = framer->adcCrossbar.conv4; + cfgData[start + offset++] = framer->adcCrossbar.conv5; + cfgData[start + offset++] = framer->adcCrossbar.conv6; + cfgData[start + offset++] = framer->adcCrossbar.conv7; + cfgData[start + offset++] = framer->adcCrossbar.conv8; + cfgData[start + offset++] = framer->adcCrossbar.conv9; + cfgData[start + offset++] = framer->adcCrossbar.conv10; + cfgData[start + offset++] = framer->adcCrossbar.conv11; + cfgData[start + offset++] = framer->adcCrossbar.conv12; + cfgData[start + offset++] = framer->adcCrossbar.conv13; + cfgData[start + offset++] = framer->adcCrossbar.conv14; + cfgData[start + offset++] = framer->adcCrossbar.conv15; + cfgData[start + offset++] = framer->adcCrossbar.conv16; + cfgData[start + offset++] = framer->adcCrossbar.conv17; + cfgData[start + offset++] = framer->adcCrossbar.conv18; + cfgData[start + offset++] = framer->adcCrossbar.conv19; + cfgData[start + offset++] = framer->adcCrossbar.conv20; + cfgData[start + offset++] = framer->adcCrossbar.conv21; + cfgData[start + offset++] = framer->adcCrossbar.conv22; + cfgData[start + offset++] = framer->adcCrossbar.conv23; + cfgData[start + offset++] = 0; + cfgData[start + offset++] = 0; + cfgData[start + offset++] = 0; + cfgData[start + offset++] = 0; + cfgData[start + offset++] = 0; + cfgData[start + offset++] = 0; + cfgData[start + offset++] = 0; +} + +/* +JESD De-framer Init: Jesd204bDeframerConfig_t +Size : 38 Bytes +*/ +void adrv9025_CpuLoadDeframerBytes(uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_DfrmCfg_t* deframer) +{ + uint8_t newSysref = ((deframer->newSysrefOnRelink > 0 ? 1 : 0) | + ((deframer->sysrefForStartup > 0 ? 1 : 0) << 1) | + ((deframer->sysrefNShotCount & 0x0F) << 2) | + ((deframer->sysrefNShotEnable > 0 ? 1 : 0) << 6) | + ((deframer->sysrefIgnoreWhenLinked > 0 ? 1 : 0) << 7)); + uint8_t offset = 0; + + cfgData[start + offset++] = deframer->enableJesd204C; + cfgData[start + offset++] = deframer->jesd204E; + cfgData[start + offset++] = deframer->bankId; + cfgData[start + offset++] = deframer->deviceId; + cfgData[start + offset++] = deframer->lane0Id; + cfgData[start + offset++] = deframer->jesd204M; + cfgData[start + offset++] = deframer->jesd204K - 1; + cfgData[start + offset++] = deframer->jesd204F; + cfgData[start + offset++] = deframer->jesd204Np; + cfgData[start + offset++] = deframer->scramble; + cfgData[start + offset++] = deframer->deserializerLanesEnabled; + cfgData[start + offset++] = (deframer->lmfcOffset & 0xFF); + cfgData[start + offset++] = ((deframer->lmfcOffset >> 8) & 0xFF); + cfgData[start + offset++] = newSysref; + cfgData[start + offset++] = deframer->syncbOutSelect; + cfgData[start + offset++] = deframer->syncbOutLvdsMode; + cfgData[start + offset++] = deframer->syncbOutLvdsPnInvert; + cfgData[start + offset++] = deframer->syncbOutCmosSlewRate; + cfgData[start + offset++] = deframer->syncbOutCmosDriveLevel; + cfgData[start + offset++] = deframer->deserializerLaneCrossbar.deframerInput0LaneSel; + cfgData[start + offset++] = deframer->deserializerLaneCrossbar.deframerInput1LaneSel; + cfgData[start + offset++] = deframer->deserializerLaneCrossbar.deframerInput2LaneSel; + cfgData[start + offset++] = deframer->deserializerLaneCrossbar.deframerInput3LaneSel; + cfgData[start + offset++] = deframer->dacCrossbar.tx1DacChanI; + cfgData[start + offset++] = deframer->dacCrossbar.tx1DacChanQ; + cfgData[start + offset++] = deframer->dacCrossbar.tx2DacChanI; + cfgData[start + offset++] = deframer->dacCrossbar.tx2DacChanQ; + cfgData[start + offset++] = deframer->dacCrossbar.tx3DacChanI; + cfgData[start + offset++] = deframer->dacCrossbar.tx3DacChanQ; + cfgData[start + offset++] = deframer->dacCrossbar.tx4DacChanI; + cfgData[start + offset++] = deframer->dacCrossbar.tx4DacChanQ; + cfgData[start + offset++] = 0; + cfgData[start + offset++] = 0; + cfgData[start + offset++] = 0; + cfgData[start + offset++] = 0; + cfgData[start + offset++] = 0; + cfgData[start + offset++] = 0; + cfgData[start + offset++] = 0; +} + +/* +JESD Data Configuration: adi_adrv9025_JesdDataConfigCtrl_t +Size : 3 bytes +*/ +void adrv9025_CpuLoadDataConfig( + uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_JesdDataConfigCtrl_t* dataCfg) +{ + cfgData[start + 0] = dataCfg->enable; + cfgData[start + 1] = dataCfg->configOption1; + cfgData[start + 2] = dataCfg->configOption2; +} + +/* +JESD Link Sharing Init: adi_adrv9025_LinkSharingCfg_t +Size : 20 bytes +*/ +void adrv9025_CpuLoadLinkSharing(uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_LinkSharingCfg_t* linkSharing) +{ + cfgData[start + 0] = linkSharing->linkSharingEnabled; + cfgData[start + 1] = linkSharing->linkSharingM; + cfgData[start + 2] = linkSharing->linkSharingS; + cfgData[start + 3] = linkSharing->linkSharingNp; + cfgData[start + 4] = linkSharing->linkSharingAdcCrossbar.conv0; + cfgData[start + 5] = linkSharing->linkSharingAdcCrossbar.conv1; + cfgData[start + 6] = linkSharing->linkSharingAdcCrossbar.conv2; + cfgData[start + 7] = linkSharing->linkSharingAdcCrossbar.conv3; + cfgData[start + 8] = linkSharing->linkSharingAdcCrossbar.conv4; + cfgData[start + 9] = linkSharing->linkSharingAdcCrossbar.conv5; + cfgData[start + 10] = linkSharing->linkSharingAdcCrossbar.conv6; + cfgData[start + 11] = linkSharing->linkSharingAdcCrossbar.conv7; + cfgData[start + 12] = linkSharing->linkSharingAdcCrossbar.conv8; + cfgData[start + 13] = linkSharing->linkSharingAdcCrossbar.conv9; + cfgData[start + 14] = linkSharing->linkSharingAdcCrossbar.conv10; + cfgData[start + 15] = linkSharing->linkSharingAdcCrossbar.conv11; + cfgData[start + 16] = linkSharing->linkSharingAdcCrossbar.conv12; + cfgData[start + 17] = linkSharing->linkSharingAdcCrossbar.conv13; + cfgData[start + 18] = linkSharing->linkSharingAdcCrossbar.conv14; + cfgData[start + 19] = linkSharing->linkSharingAdcCrossbar.conv15; +} + +/* +JESD Framer Init: JESD_SerializerLane_t +Size : 8 Bytes +Element Type Range Description +serAmplitude uint8 0-15 Serializer amplitude setting. Default = 15. +serPreEmphasis uint8 0-4 Serializer pre-emphasis setting. Default = 1. +serInvertLanePolarity uint8 +Reserved[5] uint8 5 bytes reserved. +*/ +void adrv9025_CpuLoadSerBytes(uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_SerCfg_t* serdes) +{ + cfgData[start + 0] = serdes->serAmplitude; + cfgData[start + 1] = serdes->serPreEmphasis; + cfgData[start + 2] = serdes->serPostEmphasis; + cfgData[start + 3] = serdes->serInvertLanePolarity; + cfgData[start + 4] = 0; + cfgData[start + 5] = 0; + cfgData[start + 6] = 0; + cfgData[start + 7] = 0; +} + +/* +JESD Framer Init: JESD_DeserializerLane_t +Size : 44 Bytes +Element Type Range Description +desInvertLanePolarity uint8 +desEqSetting[2] uint8 +Reserved[5] uint8 5 bytes reserved. +Table 8 - JESD Desterilizer Lane Structure + +*/ +void adrv9025_CpuLoadDesBytes(uint32_t start, + uint8_t cfgData[], + const adi_adrv9025_DesCfg_t* serdes) +{ + uint8_t offset = 0; + + cfgData[start + offset++] = serdes->highBoost; + cfgData[start + offset++] = serdes->desInvertLanePolarity; + cfgData[start + offset++] = 0; // reserved for memory alignment + cfgData[start + offset++] = 0; // reserved for memory alignment + + adrv9025_CpuLoadFourBytes(start + offset, + cfgData, + serdes->configOption1); + offset = offset + 4; + adrv9025_CpuLoadFourBytes(start + offset, + cfgData, + serdes->configOption2); + offset = offset + 4; + adrv9025_CpuLoadFourBytes(start + offset, + cfgData, + serdes->configOption3); + offset = offset + 4; + adrv9025_CpuLoadFourBytes(start + offset, + cfgData, + serdes->configOption4); + offset = offset + 4; + adrv9025_CpuLoadFourBytes(start + offset, + cfgData, + serdes->configOption5); + offset = offset + 4; + adrv9025_CpuLoadFourBytes(start + offset, + cfgData, + serdes->configOption6); + offset = offset + 4; + adrv9025_CpuLoadFourBytes(start + offset, + cfgData, + serdes->configOption7); + offset = offset + 4; + adrv9025_CpuLoadFourBytes(start + offset, + cfgData, + serdes->configOption8); + offset = offset + 4; + adrv9025_CpuLoadFourBytes(start + offset, + cfgData, + serdes->configOption9); + offset = offset + 4; + adrv9025_CpuLoadFourBytes(start + offset, + cfgData, + serdes->configOption10); + offset = offset + 4; +} + +/* +Noise Cancel Config Init: noiseCancel_t +Size : 36 Bytes +Element Type Range Description +Start Frequency 1 uint32_t Start of Noise Cancel band 1 +End Frequency 1 uint32_t End of Noise Cancel band 1 +Start Frequency 2 uint32_t Start of Noise Cancel band 2 +End Frequency 2 uint32_t End of Noise Cancel band 2 +Start Frequency 3 uint32_t Start of Noise Cancel band 3 +End Frequency 3 uint32_t End of Noise Cancel band 3 +Flip uint32_t Flip Channel 1/2 +Reserved[8] uint8 8 bytes reserved. + +Table 6 - Noise Cancellation Config Structure +*/ +void adrv9025_CpuLoadNoiseCancelBytes(uint32_t start, + uint8_t cfgData[]) +{ + adrv9025_CpuLoadFourBytes(start + 0, + cfgData, + 0); + adrv9025_CpuLoadFourBytes(start + 4, + cfgData, + 0); + adrv9025_CpuLoadFourBytes(start + 8, + cfgData, + 0); + adrv9025_CpuLoadFourBytes(start + 12, + cfgData, + 0); + adrv9025_CpuLoadFourBytes(start + 16, + cfgData, + 0); + adrv9025_CpuLoadFourBytes(start + 20, + cfgData, + 0); + adrv9025_CpuLoadFourBytes(start + 24, + cfgData, + 0); + adrv9025_CpuLoadFourBytes(start + 28, + cfgData, + 0); + adrv9025_CpuLoadFourBytes(start + 32, + cfgData, + 0); +} + +static void adrv9025_cfgDataSet(uint8_t cfgData[], + uint8_t value, + int count) +{ + int i = 0; + for (i = 0; i < count; i++) + { + cfgData[i] = value; + } +} + +void adrv9025_CpuLoadTwoBytes(uint32_t start, + uint8_t cfgData[], + const uint16_t data) +{ + cfgData[start] = (uint8_t)(data & 0x00FF); + cfgData[start + 1] = (uint8_t)((data >> 8) & 0x00FF); +} + +void adrv9025_CpuLoadFourBytes(uint32_t start, + uint8_t cfgData[], + const uint32_t data) +{ + cfgData[start] = (uint8_t)(data & 0x000000FF); + cfgData[start + 1] = (uint8_t)((data >> 8) & 0x000000FF); + cfgData[start + 2] = (uint8_t)((data >> 16) & 0x000000FF); + cfgData[start + 3] = (uint8_t)((data >> 24) & 0x000000FF); +} + +void adrv9025_CpuLoadAdcBytes(uint32_t start, + uint8_t cfgData[], + const uint16_t* data) +{ + uint32_t i = 0; + + adrv9025_CpuLoadTwoBytes(start + 0, + &cfgData[0], + data[0]); + adrv9025_CpuLoadTwoBytes(start + 2, + &cfgData[0], + data[1]); + adrv9025_CpuLoadTwoBytes(start + 4, + &cfgData[0], + data[2]); + adrv9025_CpuLoadTwoBytes(start + 6, + &cfgData[0], + data[3]); + + cfgData[start + 8] = (uint8_t)(data[4] & 0x00FF); //Loop filter R4. + cfgData[start + 9] = 0; + + adrv9025_CpuLoadTwoBytes(start + 10, + &cfgData[0], + data[5]); + adrv9025_CpuLoadTwoBytes(start + 12, + &cfgData[0], + data[6]); + + cfgData[start + 14] = (uint8_t)(data[7] & 0x00FF); //Loop filter C3. + cfgData[start + 15] = (uint8_t)(data[8] & 0x00FF); //Feedback ILSB3. + + adrv9025_CpuLoadTwoBytes(start + 16, + &cfgData[0], + data[9]); + + /* All 1 byte */ + for (i = 0; (i + 18) < ADRV9025_CPU_ADC_PROFILE_SIZE; i++) + { + cfgData[start + 18 + i] = (uint8_t)(data[10 + i] & 0x00FF); + } +} + +void adrv9025_CpuDataSet( + uint8_t* cfgData, + uint8_t value, + int count) +{ + int i = 0; + for (i = 0; i < count; i++) + { + cfgData[i] = value; + } +} + +enum adrv9025_CpuErrorFlag adrv9025_CpuErrorFlagGet(uint32_t err) +{ + enum adrv9025_CpuErrorFlag result = ADRV9025_CPU_ERROR_FLAG_INVALID; + + switch (err) + { + /* CPU Error flag = 1 */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_RUNINIT_OPCODE, + 0, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CPU_EXCEPTION, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_MCS, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_MCS, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TX_ORX_MAPPING, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TX_ORX_MAPPING, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TXCAL_ENA_DIS, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TXCAL_ENA_DIS, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_PLL_LOOP_BW, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_PLL_LOOP_BW, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TEMP_SENSOR, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_GPIO_CTRL, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_GPIO_CTRL, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_MODEL_SELECT, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_MODEL_SELECT, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_ENABLE_DISABLE, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_TRIG, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_DONE, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_DONE, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_SRL_CONFIG, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_SRL_CONFIG, + 1): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_SRL_STATISTICS, + 1): + result = ADRV9025_CPU_ERROR_FLAG_1; + break; + + /* CPU Error flag = 2 */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_RUNINIT_OPCODE, + 0, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CPU_EXCEPTION, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_MCS, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_MCS, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TX_ORX_MAPPING, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TX_ORX_MAPPING, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TXCAL_ENA_DIS, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TXCAL_ENA_DIS, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_PLL_LOOP_BW, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_PLL_LOOP_BW, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TEMP_SENSOR, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_GPIO_CTRL, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_GPIO_CTRL, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_MODEL_SELECT, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_MODEL_SELECT, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_ENABLE_DISABLE, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_TRIG, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_DONE, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_DONE, + 2): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL, + 2): + result = ADRV9025_CPU_ERROR_FLAG_2; + break; + + /* CPU Error flag = 3 */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_RUNINIT_OPCODE, + 0, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CPU_EXCEPTION, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_MCS, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_MCS, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TX_ORX_MAPPING, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TX_ORX_MAPPING, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TXCAL_ENA_DIS, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TXCAL_ENA_DIS, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_PLL_LOOP_BW, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_PLL_LOOP_BW, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TEMP_SENSOR, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_GPIO_CTRL, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_GPIO_CTRL, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_MODEL_SELECT, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_MODEL_SELECT, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_ENABLE_DISABLE, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_TRIG, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_DONE, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_DONE, + 3): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL, + 3): + result = ADRV9025_CPU_ERROR_FLAG_3; + break; + + /* CPU Error flag = 4 */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_RUNINIT_OPCODE, + 0, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CPU_EXCEPTION, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_MCS, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_MCS, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TX_ORX_MAPPING, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TX_ORX_MAPPING, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TXCAL_ENA_DIS, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TXCAL_ENA_DIS, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_PLL_LOOP_BW, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_PLL_LOOP_BW, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_GPIO_CTRL, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_GPIO_CTRL, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_MODEL_SELECT, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_MODEL_SELECT, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_ENABLE_DISABLE, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_TRIG, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_DONE, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_DONE, + 4): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL, + 4): + result = ADRV9025_CPU_ERROR_FLAG_4; + break; + + /* CPU Error flag = 5 */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_RUNINIT_OPCODE, + 0, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CPU_EXCEPTION, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_MCS, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_MCS, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TX_ORX_MAPPING, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TX_ORX_MAPPING, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TXCAL_ENA_DIS, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TXCAL_ENA_DIS, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_PLL_LOOP_BW, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_PLL_LOOP_BW, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_GPIO_CTRL, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_GPIO_CTRL, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_MODEL_SELECT, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_MODEL_SELECT, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_ENABLE_DISABLE, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_TRIG, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_DONE, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_DONE, + 5): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL, + 5): + result = ADRV9025_CPU_ERROR_FLAG_5; + break; + + /* CPU Error flag = 6 */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_RUNINIT_OPCODE, + 0, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CPU_EXCEPTION, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_MCS, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_MCS, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TX_ORX_MAPPING, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TX_ORX_MAPPING, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TXCAL_ENA_DIS, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TXCAL_ENA_DIS, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_PLL_LOOP_BW, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_PLL_LOOP_BW, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_GPIO_CTRL, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_GPIO_CTRL, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_MODEL_SELECT, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_MODEL_SELECT, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_ENABLE_DISABLE, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_TRIG, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_DONE, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_EXT_DPD_CAPTURE_DONE, + 6): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL, + 6): + result = ADRV9025_CPU_ERROR_FLAG_6; + break; + + /* CPU Error flag = 7 */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_RUNINIT_OPCODE, + 0, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_PLL_LOOP_BW, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_PLL_LOOP_BW, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_GPIO_CTRL, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_GPIO_CTRL, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CPU_EXCEPTION, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_MCS, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_MCS, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TX_ORX_MAPPING, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TX_ORX_MAPPING, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_TXCAL_ENA_DIS, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TXCAL_ENA_DIS, + 7): /* Fall through */ + case ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL, + 7): + result = ADRV9025_CPU_ERROR_FLAG_7; + break; + + default: + result = ADRV9025_CPU_ERROR_FLAG_INVALID; + break; + } + + return result; +}; + +const char* adrv9025_CpuErrMsgGet( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint32_t errCode, + uint16_t* mailboxErrCodeRet) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + static const uint8_t ERR_FLAG_MASK = 0x0E; + static const uint8_t ERR_FLAG_SHIFT = 1; + static const uint8_t ERR_FLAG_MAILBOX = 7; + uint32_t cpuErrorFlag = ADRV9025_BF_DECODE(errCode, + ERR_FLAG_MASK, + ERR_FLAG_SHIFT); + uint16_t mailboxErrCode = 0; + + if (cpuErrorFlag == ERR_FLAG_MAILBOX) + { + /*Clear the error so that CPU Mailbox functions execute*/ + recoveryAction = adi_common_ErrorClear(&device->common); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + return "Error clearing MailBox Error Code.\n"; + } + + recoveryAction = adrv9025_CpuMailBoxErrCodeGet(device, + cpuType, + &mailboxErrCode); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + return "Error getting MailBox Error Code.\n"; + } + + *mailboxErrCodeRet = mailboxErrCode; + } + + errCode = ((errCode & (ADRV9025_CPU_OPCODE_MASK | ADRV9025_CPU_OBJ_ID_MASK)) | cpuErrorFlag); + + if (cpuErrorFlag > 0) + { + switch (adrv9025_CpuErrorFlagGet(errCode)) + { + case ADRV9025_CPU_ERROR_FLAG_1: + return "Detected nested ADRV9025 CPU commands, second command ignored\n"; + case ADRV9025_CPU_ERROR_FLAG_2: + return "ADRV9025 CPU Command is not supported\n"; + case ADRV9025_CPU_ERROR_FLAG_3: + return "ADRV9025 CPU Invalid State\n"; + case ADRV9025_CPU_ERROR_FLAG_4: + return "ADRV9025 CPU Reserved 4\n"; + case ADRV9025_CPU_ERROR_FLAG_5: + return "ADRV9025 CPU Reserved 5\n"; + case ADRV9025_CPU_ERROR_FLAG_6: + return "ADRV9025 CPU Reserved 6\n"; + case ADRV9025_CPU_ERROR_FLAG_7: + return "ADRV9025 CPU Command Error\n"; + default: + return "Invalid CPU error passed, not in error list\n"; + } + } + return "Wrong error handler - not a ADRV9025 CPU error\n"; +} + +int32_t adrv9025_CpuMailBoxErrCodeGet( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint16_t* mailboxErrCode) +{ + /* reading the command status register for given opcode */ + uint8_t errCode = 0; + uint8_t objId = 0; + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + + cpuAddr = adrv9025_CpuAddrGet(&device->devStateInfo.cpu, + cpuType); + ADI_NULL_PTR_RETURN(&device->common, + cpuAddr); + + ADRV9025_SPIREADBYTE("CPU_CMD_STATUS_10", + cpuAddr->cmdStatusAddr + 10u, + &errCode); + ADRV9025_SPIREADBYTE("CPU_CMD_STATUS_11", + cpuAddr->cmdStatusAddr + 11u, + &objId); + + *mailboxErrCode = ((uint16_t)objId << 8) | errCode; + return (device->common.error.newAction); +} + +int32_t adrv9025_CpuSystemErrCodeGet(adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint16_t* systemErrCode) +{ + /* Reading the ARM system error code and ObjID */ + uint8_t errCode = 0; + uint8_t objId = 0; + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + + cpuAddr = adrv9025_CpuAddrGet(&device->devStateInfo.cpu, + cpuType); + ADI_NULL_PTR_RETURN(&device->common, + cpuAddr); + + ADRV9025_SPIREADBYTE("CPU_CMD_STATUS_10", + cpuAddr->cmdStatusAddr + 12u, + &errCode); + ADRV9025_SPIREADBYTE("CPU_CMD_STATUS_11", + cpuAddr->cmdStatusAddr + 13u, + &objId); + + *systemErrCode = ((uint16_t)objId << 8) | errCode; + return (device->common.error.newAction); +} + +int32_t adrv9025_CpuDmaMemReadByte( + adi_adrv9025_Device_t* device, + uint32_t address, + uint8_t returnData[], + uint32_t byteCount, + uint8_t autoIncrement) +{ + uint32_t i = 0; + uint8_t dataRead0 = 0; + int32_t recoveryAction = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + returnData); + + ADRV9025_BUGINFO(__FUNCTION__); + + ADRV9025_DMAINFO("CPU_MEM_READ", + address, + byteCount); + + if (byteCount == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_NULL_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "byteCount is zero"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* starting write at zero address offset */ + for (i = 0; i < byteCount; i++) + { + /* Always read byte0 even if target byte is not located on full word boundary */ + ADRV9025_SPIREADBYTEDMA("CPU_DMA_DATA_0+", + ADRV9025_CPU_ADDR_DMA_DATA0, + &dataRead0); + returnData[i] = dataRead0; + + if (autoIncrement == ADI_FALSE) + { + address++; + ADRV9025_SPIWRITEWORDDMA("CPU_DMA_ADDR", + ADRV9025_CPU_ADDR_DMA_ADDR3, + address); + } + } + + return (device->common.error.newAction); +} + +int32_t adrv9025_CpuDmaMemWriteByte( + adi_adrv9025_Device_t* device, + uint32_t address, + const uint8_t data[], + uint32_t byteCount, + uint8_t autoInc) +{ + uint32_t i = 0; + int32_t recoveryAction = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + data); + + ADRV9025_BUGINFO(__FUNCTION__); + + ADRV9025_DMAINFO("CPU_MEM_WRITE", + address, + byteCount); + + if (byteCount == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_NULL_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + byteCount, + "byteCount is zero"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < byteCount; i++) + { + /* Always write to byte0 even if target byte is not at full word boundary */ + ADRV9025_SPIWRITEBYTEDMA("CPU_DMA_DATA_0+", + ADRV9025_CPU_ADDR_DMA_DATA0, + data[i]); + + if (autoInc == ADI_FALSE) + { + address++; + /* core_bf.bus_addr.write(bf_status, 32'hxxxxxxxx); */ + ADRV9025_SPIWRITEWORDDMA("CPU_DMA_ADDR", + ADRV9025_CPU_ADDR_DMA_ADDR3, + address); + } + } + + return (device->common.error.newAction); +} + +int32_t adrv9025_CpuDmaSetup(adi_adrv9025_Device_t* device, + uint32_t address, + uint8_t isWrite, + uint8_t isByte, + uint8_t autoInc) +{ + uint8_t reg = 0u; + int32_t recoveryAction = 0; + /* + Use SPI DMA for Write + */ + /* Write */ + /* 1 = read, 0 = write */ + /* core_bf.rd_wrb.write(bf_status, 1'b1); */ + if (isWrite == ADI_FALSE) + { + reg |= ADRV9025_CPU_MASK_DMA_CTL_RD_WRB; + } + else + { + reg &= ~ADRV9025_CPU_MASK_DMA_CTL_RD_WRB; + } + + /* system AHB bus slave or code AHB bus slave */ + /* 1'b0=code bus; 1'b1=system bus */ + /* core_bf.sys_codeb.write(bf_status, 1'b1); */ + /* determining the data space and setting dataMem bit accordingly */ + if (adrv9025_CpuIsAddrInProgRegion(&device->devStateInfo.cpu, + address) == ADI_FALSE) + { + reg |= ADRV9025_CPU_MASK_DMA_CTL_SYS_CODEB; + } + + /* bus size, 2'b00=byte; 2'b01=half-word; 2'b10=full-word; 2'b11=invalid */ + /* core_bf.bus_size.write(bf_status, 2'b10); */ + reg |= ADRV9025_BF_ENCODE((isByte == ADI_FALSE)? 2:0, + ADRV9025_CPU_MASK_DMA_CTL_BUS_SIZE, + ADRV9025_CPU_SHIFT_DMA_CTL_BUS_SIZE); + + /* address auto incremental, 1'b0=no; 1'b1=yes */ + /* core_bf.auto_incr.write(bf_status, 1'b0); */ + if (autoInc != ADI_FALSE) + { + reg |= ADRV9025_CPU_MASK_DMA_CTL_AUTO_INCR; + } + + /* spi_dma_ahb_bus_select */ + /* 1 = CPU D, 0 = CPU. */ + /* When 1, SPI DMA can access resources connected to CPU D's AHB subsystem. */ + if (adrv9025_CpuWhichTypeAddressBelongs(&device->devStateInfo.cpu, + address) == ADI_ADRV9025_CPU_TYPE_D) + { + reg |= ADRV9025_CPU_MASK_DMA_CTL_BUS_SELECT; + } + + /* setting up the DMA control register for a write */ + ADRV9025_SPIWRITEBYTEDMA("CPU_DMA_CTL", + ADRV9025_CPU_ADDR_DMA_CTL, + reg); + + /* core_bf.bus_addr.write(bf_status, 32'hxxxxxxxx); */ + ADRV9025_SPIWRITEWORDDMA("CPU_DMA_ADDR", + ADRV9025_CPU_ADDR_DMA_ADDR3, + address); + + return (device->common.error.newAction); +} + +adi_adrv9025_CpuType_e adrv9025_CpuWhichTypeAddressBelongs( + adi_adrv9025_Cpu_t* cpu, + uint32_t addr) +{ + adi_adrv9025_CpuType_e result = ADI_ADRV9025_CPU_TYPE_UNKNOWN; + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + uint8_t i = 0u; + + for (i = 0u; i < ADRV9025_MAX_CPUS && result == ADI_ADRV9025_CPU_TYPE_UNKNOWN; i++) + { + cpuAddr = &cpu->cpuAddr[i]; + if ((addr >= cpuAddr->progStartAddr && addr <= cpuAddr->progEndAddr) || + (addr >= cpuAddr->dataStartAddr && addr <= cpuAddr->dataEndAddr)) + { + result = (adi_adrv9025_CpuType_e)i; + } + } + return result; +} + +uint8_t adrv9025_CpuIsAddrInProgRegion( + adi_adrv9025_Cpu_t* cpu, + uint32_t addr) +{ + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + uint8_t result = ADI_FALSE; + uint8_t i = 0u; + + for (i = 0; i < ADRV9025_MAX_CPUS && result == ADI_FALSE; i++) + { + cpuAddr = &cpu->cpuAddr[i]; + if (addr >= cpuAddr->progStartAddr && addr <= cpuAddr->progEndAddr) + { + result = ADI_TRUE; + } + } + + return result; +} + +void adrv9025_CpuAddrInitialize( + adi_adrv9025_CpuAddr_t* cpuAddr, + adi_adrv9025_CpuType_e type) +{ + if (adrv9025_cpuTypeIsValid(type) != 0) + { + switch (type) + { + case ADI_ADRV9025_CPU_TYPE_C: + cpuAddr->enabled = ADI_TRUE; + cpuAddr->ctlAddr = ADRV9025_CPU_C_ADDR_CTL_1; + cpuAddr->bootAddr = ADRV9025_CPU_C_ADDR_BOOT_ADDR_BYTE0; + cpuAddr->stackPtrAddr = ADRV9025_CPU_C_ADDR_STACK_PTR_BYTE0; + cpuAddr->cmdAddr = ADRV9025_CPU_C_ADDR_COMMAND; + cpuAddr->extCmdAddr = ADRV9025_CPU_C_ADDR_EXT_CMD_BYTE_1; + cpuAddr->cmdStatusAddr = ADRV9025_CPU_C_ADDR_CMD_STATUS_0; + cpuAddr->progStartAddr = ADRV9025_CPU_C_ADDR_PROG_START; + cpuAddr->progEndAddr = ADRV9025_CPU_C_ADDR_PROG_END; + cpuAddr->versionAddr = ADRV9025_CPU_C_ADDR_VERSION; + cpuAddr->structChecksumAddr = ADRV9025_CPU_C_ADDR_CALC_CHKSUM_PTR; + cpuAddr->debugPointersAddr = ADRV9025_CPU_C_ADDR_DEBUG_PTR; + cpuAddr->buildChecksumAddr = ADRV9025_CPU_C_ADDR_BUILD_CHKSUM; + cpuAddr->dataStartAddr = ADRV9025_CPU_C_ADDR_DATA_START; + cpuAddr->dataEndAddr = ADRV9025_CPU_C_ADDR_DATA_END; + cpuAddr->cfrPulseAddr = ADRV9025_CPU_C_ADDR_CFR_PULSE; + cpuAddr->mailboxSetAddr = ADRV9025_CPU_C_ADDR_MAILBOX_SET; + cpuAddr->mailboxGetAddr = ADRV9025_CPU_C_ADDR_MAILBOX_GET; + cpuAddr->mailboxRunInitAddr = ADRV9025_CPU_C_ADDR_MAILBOX_RUN_INIT; + cpuAddr->mailboxFhmAddr = ADRV9025_CPU_C_ADDR_MAILBOX_FHM; + break; + case ADI_ADRV9025_CPU_TYPE_D: + cpuAddr->enabled = ADI_FALSE; + cpuAddr->ctlAddr = ADRV9025_CPU_D_ADDR_CTL_1; + cpuAddr->bootAddr = ADRV9025_CPU_D_ADDR_BOOT_ADDR_BYTE0; + cpuAddr->stackPtrAddr = ADRV9025_CPU_D_ADDR_STACK_PTR_BYTE0; + cpuAddr->cmdAddr = ADRV9025_CPU_D_ADDR_COMMAND; + cpuAddr->extCmdAddr = ADRV9025_CPU_D_ADDR_EXT_CMD_BYTE_1; + cpuAddr->cmdStatusAddr = ADRV9025_CPU_D_ADDR_CMD_STATUS_0; + cpuAddr->progStartAddr = ADRV9025_CPU_D_ADDR_PROG_START; + cpuAddr->progEndAddr = ADRV9025_CPU_D_ADDR_PROG_END; + cpuAddr->versionAddr = ADRV9025_CPU_D_ADDR_VERSION; + cpuAddr->structChecksumAddr = ADRV9025_CPU_D_ADDR_CALC_CHKSUM_PTR; + cpuAddr->debugPointersAddr = ADRV9025_CPU_D_ADDR_DEBUG_PTR; + cpuAddr->buildChecksumAddr = ADRV9025_CPU_D_ADDR_BUILD_CHKSUM; + cpuAddr->dataStartAddr = ADRV9025_CPU_D_ADDR_DATA_START; + cpuAddr->dataEndAddr = ADRV9025_CPU_D_ADDR_DATA_END; + cpuAddr->cfrPulseAddr = ADRV9025_CPU_D_ADDR_CFR_PULSE; + cpuAddr->mailboxSetAddr = ADRV9025_CPU_D_ADDR_MAILBOX_SET; + cpuAddr->mailboxGetAddr = ADRV9025_CPU_D_ADDR_MAILBOX_GET; + cpuAddr->mailboxRunInitAddr = ADRV9025_CPU_D_ADDR_MAILBOX_RUN_INIT; + cpuAddr->mailboxFhmAddr = ADRV9025_CPU_D_ADDR_MAILBOX_FHM; + break; + default: + break; + } + } +} + +uint8_t adrv9025_cpuTypeIsValid(adi_adrv9025_CpuType_e type) +{ + uint8_t result = ADI_FALSE; + + if (type > ADI_ADRV9025_CPU_TYPE_UNKNOWN && + type < ADI_ADRV9025_CPU_TYPE_MAX) + { + result = ADI_TRUE; + } + + return result; +} + +/*****************************************************************************/ +/***** Public functions' definition ******************************************/ +/*****************************************************************************/ +adi_adrv9025_CpuAddr_t* adrv9025_CpuAddrGet( + adi_adrv9025_Cpu_t* cpu, + adi_adrv9025_CpuType_e cpuType) +{ + return &cpu->cpuAddr[cpuType]; +} + +void adrv9025_CpuInitialize( + adi_adrv9025_Device_t* device) +{ + adi_adrv9025_Cpu_t* cpu = &device->devStateInfo.cpu; + uint8_t i = 0; + + cpu->devProfileAddr = ADRV9025_CPU_C_ADDR_DEV_PROFILE; + cpu->adcProfileAddr = ADRV9025_CPU_C_ADDR_ADC_PROFILE; + for (i = 0; i < ADRV9025_MAX_CPUS; i++) + { + adrv9025_CpuAddrInitialize(&cpu->cpuAddr[i], + (adi_adrv9025_CpuType_e)i); + } +} + +uint8_t adrv9025_CpuValidateMemoryAddr( + adi_adrv9025_Cpu_t* cpu, + uint32_t addr, + uint32_t size) +{ + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + uint8_t isValid = ADI_FALSE; + uint8_t i = 0u; + uint32_t endAddr = addr + size - 1u; + + for (i = 0; i < ADRV9025_MAX_CPUS && isValid == ADI_FALSE; i++) + { + cpuAddr = &cpu->cpuAddr[i]; + if ((addr >= cpuAddr->progStartAddr && endAddr <= cpuAddr->progEndAddr) || + (addr >= cpuAddr->dataStartAddr && endAddr <= cpuAddr->dataEndAddr)) + { + isValid = ADI_TRUE; + } + } + + return isValid; +} + +int32_t adrv9025_CpuDmaMemWrite( + adi_adrv9025_Device_t* device, + uint32_t address, + const uint8_t data[], + uint32_t byteCount, + uint8_t autoIncrement) +{ + static const uint32_t ADDR_CPU_DMA_DATA[4] = + { + ADRV9025_CPU_ADDR_DMA_DATA3, + ADRV9025_CPU_ADDR_DMA_DATA2, + ADRV9025_CPU_ADDR_DMA_DATA1, + ADRV9025_CPU_ADDR_DMA_DATA0 + }; + static const uint32_t WORD_LENGTH = 4; + static const uint8_t cacheEnable = ADI_ADRV9025_CPU_MEMWRITE_CACHE_ENABLE; + + int32_t recoveryAction = 0; + uint32_t i = 0; + uint32_t addrIndex = 0; + uint32_t dataIndex = 0; + uint16_t addrArray[(ADI_COMMON_HAL_SPIARRAYSIZE / 3)] = {0}; + uint8_t dataArray[(ADI_COMMON_HAL_SPIARRAYSIZE / 3)] = {0}; + uint32_t spiBufferSize = (uint32_t)(sizeof(addrArray) / sizeof(addrArray[0])); + uint32_t index = 0; + uint8_t isByteWrite = ADI_FALSE; + uint8_t addrArrayStream[4] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + data); + + ADRV9025_DMAINFO("CPU_MEM_WRITE", + address, + byteCount); + + if (byteCount == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_NULL_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + byteCount, + "byteCount is zero"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* If Address is not on word boundary, Or ByteCount is not on Word boundary, write byte by byte */ + if (((address & 0x00000003) > 0) || ((byteCount & 0x00000003) > 0)) + { + isByteWrite = ADI_TRUE; + } + + /* setup DMA control register for write operation */ + adrv9025_CpuDmaSetup(device, + address, + ADI_TRUE, + isByteWrite, + autoIncrement); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* If Address is not on word boundary, Or ByteCount is not on Word boundary */ + if (isByteWrite != ADI_FALSE) + { + adrv9025_CpuDmaMemWriteByte(device, + address, + data, + byteCount, + autoIncrement); + } + else + { +#if ADI_ADRV9025_SPI_WRITE_STREAMING_ENABLE == 1 + /* Enable Spi streaming */ + ADRV9025_SPI_STREAM_ENABLE(device); +#endif + + if ((device->spiSettings.enSpiStreaming == 1) && (autoIncrement == ADI_TRUE)) + { + /* 1) STREAMING WITH AUTO INCREMENT */ + /* Send sequential words without address */ + +#ifdef ADI_ADRV9025_USER_DEFINED_SPI_WRITE_STREAM + /* Streaming with custom hal layer function(adi_hal_CustomSpiStreamWrite) */ + ADRV9025_SPIWRITEWORDDMASTREAMWITHCUSTOMHALFUNCTION("DMA_MEM_WRITE_STREAM", ADRV9025_CPU_ADDR_DMA_DATA3, data, byteCount); +#else + /* Streaming with standard hal layer function(adi_hal_SpiWrite) */ + ADRV9025_SPIWRITEWORDDMASTREAM("DMA_MEM_WRITE_STREAM", + ADRV9025_CPU_ADDR_DMA_DATA3, + data, + byteCount); +#endif + } + else if ((device->spiSettings.enSpiStreaming == 1) && (autoIncrement == ADI_FALSE)) + { + /* 2) STREAMING WITHOUT AUTO INCREMENT */ + /* Send each word with its address */ + for (i = 0; i < byteCount; i += WORD_LENGTH) + { + addrArrayStream[0] = (uint8_t)((address & 0x000000FF) >> 0); + addrArrayStream[1] = (uint8_t)((address & 0x0000FF00) >> 8); + addrArrayStream[2] = (uint8_t)((address & 0x00FF0000) >> 16); + addrArrayStream[3] = (uint8_t)((address & 0xFF000000) >> 24); + + ADRV9025_SPIWRITEWORDDMASTREAM("DMA_MEM_WRITE_STREAM", + ADRV9025_CPU_ADDR_DMA_ADDR3, + addrArrayStream, + WORD_LENGTH); + + address += WORD_LENGTH; + + ADRV9025_SPIWRITEWORDDMASTREAM("DMA_MEM_WRITE_STREAM", + ADRV9025_CPU_ADDR_DMA_DATA3, + &data[i], + WORD_LENGTH); + } + } + else if ((cacheEnable == ADI_TRUE) && (autoIncrement == ADI_TRUE)) + { + /* 3) NON-STREAMING WITH CACHE AND AUTO INCREMENT */ + /* Cache Enable and Auto Inc */ + for (i = 0; i < byteCount; i++) + { + /* Write mem_write_data bitfield (mem_write_data[7:0] has to be the last register written) */ + /* core_bf.mem_write_data.write(bf_status, 32'hxxxxxxxx); */ + index = address % 4; + + /* Writing byte order: 3,2,1,0 */ + if (index == 0) + { + dataIndex = i + 3; + } + else + { + dataIndex--; + } + + dataArray[addrIndex] = data[dataIndex]; + addrArray[addrIndex] = ADDR_CPU_DMA_DATA[index]; + + addrIndex++; + address++; + + if (addrIndex >= spiBufferSize) + { + ADRV9025_SPIWRITEBYTESDMA("DMA_MEM_WRITE_CACHE", + (address - addrIndex), + &addrArray[0], + &dataArray[0], + addrIndex); + addrIndex = 0; + } + } + + if (addrIndex > 0) + { + ADRV9025_SPIWRITEBYTESDMA("DMA_MEM_WRITE_CACHE_LAST", + (address - addrIndex), + &addrArray[0], + &dataArray[0], + addrIndex); + } + } + else + { + /* 4) NON-STREAMING WITHOUT CACHE */ + /* starting write at zero address offset */ + for (i = 0; i < byteCount; i += 4) + { + /* Write mem_write_data bitfield (mem_write_data[7:0] has to be the last register written) */ + /* core_bf.bus_addr.write(bf_status, 32'hxxxxxxxx); */ + ADRV9025_SPIWRITEWORDDMA("CPU_DMA_ADDR", + ADRV9025_CPU_ADDR_DMA_DATA3, + (uint32_t)(data[i + 3] << 24) | (uint32_t)(data[i + 2] << 16) | + (uint32_t)(data[i + 1] << 8) | (uint32_t)(data[i + 0] << 0)); + if (autoIncrement == ADI_FALSE) + { + /* AHB address for write */ + /* core_bf.bus_addr.write(bf_status, 32'hxxxxxxxx); */ + address += 4; + ADRV9025_SPIWRITEWORDDMA("CPU_DMA_ADDR", + ADRV9025_CPU_ADDR_DMA_ADDR3, + address); + } + } + } +#if ADI_ADRV9025_SPI_WRITE_STREAMING_ENABLE == 1 + /* Disable Spi streaming */ + ADRV9025_SPI_STREAM_DISABLE(device); +#endif + } + + /* setting up the DMA control register for a read to avoid accidental writing */ + adrv9025_CpuDmaSetup(device, + address, + ADI_FALSE, + isByteWrite, + autoIncrement); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_CpuDmaMemRead( + adi_adrv9025_Device_t* device, + uint32_t address, + uint8_t returnData[], + uint32_t byteCount, + uint8_t autoIncrement) +{ + static const uint32_t ADDR_ARM_DMA_DATA[4] = { + ADRV9025_CPU_ADDR_DMA_DATA3, + ADRV9025_CPU_ADDR_DMA_DATA2, + ADRV9025_CPU_ADDR_DMA_DATA1, + ADRV9025_CPU_ADDR_DMA_DATA0 + }; + static const uint8_t cacheEnable = ADI_ADRV9025_CPU_MEMREAD_CACHE_ENABLE; + static const uint32_t SHIFT_FOR_NUM_OF_WORDS = 2; + static const uint32_t WORD_LENGTH = 4; + + int32_t recoveryAction = 0; + uint32_t dataRead = 0; + uint8_t isByteRead = ADI_FALSE; + uint32_t dataCounter = 0; + uint32_t wordCount = 0; + uint8_t tempByte = 0; + uint32_t i = 0; + uint32_t index = 0; + uint32_t addrIndex = 0; + uint16_t addrArray[(ADI_COMMON_HAL_SPIARRAYSIZE / 3)] = {0}; + uint32_t spiBufferSize = (uint32_t)(sizeof(addrArray) / sizeof(addrArray[0])); + uint8_t addrArrayStream[4] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + returnData); + + ADRV9025_BUGINFO(__FUNCTION__); + + ADRV9025_DMAINFO("CPU_MEM_READ", + address, + byteCount); + + if (byteCount == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_NULL_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + byteCount, + "byteCount is zero"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* If Address is not on word boundary, Or ByteCount is not on Word boundary, read byte by byte */ + if (((address & 0x00000003) > 0) || ((byteCount & 0x00000003) > 0)) + { + isByteRead = ADI_TRUE; + } + + /* setup DMA control register for write operation */ + adrv9025_CpuDmaSetup(device, + address, + ADI_FALSE, + isByteRead, + autoIncrement); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* If Address is not on word boundary, Or ByteCount is not on Word boundary */ + if (isByteRead != ADI_FALSE) + { + return adrv9025_CpuDmaMemReadByte(device, + address, + returnData, + byteCount, + autoIncrement); + } + +#if ADI_ADRV9025_SPI_READ_STREAMING_ENABLE == 1 + /* Enable Spi streaming */ + ADRV9025_SPI_STREAM_ENABLE(device); +#endif + + wordCount = byteCount >> SHIFT_FOR_NUM_OF_WORDS; + + if ((device->spiSettings.enSpiStreaming == 1) && (autoIncrement == ADI_TRUE)) + { + /* 1) STREAMING WITH AUTO INCREMENT */ + /* Send sequential words without address */ + +#ifdef ADI_ADRV9025_USER_DEFINED_SPI_READ_STREAM + /* Streaming with custom hal layer function(adi_hal_CustomSpiStreamRead) */ + ADRV9025_SPIREADWORDDMASTREAMWITHCUSTOMHALFUNCTION("DMA_MEM_READ_STREAM", ADRV9025_CPU_ADDR_DMA_DATA3, returnData, byteCount); +#else + /* Streaming with standard hal layer function(adi_hal_SpiRead) */ + ADRV9025_SPIREADWORDDMASTREAM("DMA_MEM_READ_STREAM", + ADRV9025_CPU_ADDR_DMA_DATA3, + returnData, + byteCount); +#endif + } + else if ((device->spiSettings.enSpiStreaming == 1) && (autoIncrement == ADI_FALSE)) + { + /* 2) STREAMING WITHOUT AUTO INCREMENT */ + /* Send each word with its address */ + for (i = 0; i < byteCount; i += WORD_LENGTH) + { + addrArrayStream[0] = (uint8_t)((address & 0x000000FF) >> 0); + addrArrayStream[1] = (uint8_t)((address & 0x0000FF00) >> 8); + addrArrayStream[2] = (uint8_t)((address & 0x00FF0000) >> 16); + addrArrayStream[3] = (uint8_t)((address & 0xFF000000) >> 24); + + ADRV9025_SPIWRITEWORDDMASTREAM("DMA_MEM_WRITE_STREAM", + ADRV9025_CPU_ADDR_DMA_ADDR3, + addrArrayStream, + WORD_LENGTH); + + address += WORD_LENGTH; + + ADRV9025_SPIREADWORDDMASTREAM("DMA_MEM_READ_STREAM", + ADRV9025_CPU_ADDR_DMA_DATA3, + &returnData[i], + WORD_LENGTH); + } + } + else if ((cacheEnable == ADI_TRUE) && (autoIncrement == ADI_TRUE)) + { + /* 3) NON-STREAMING WITH CACHE AND AUTO INCREMENT */ + /* Cache Enable and Auto Inc */ + for (i = 0; i < byteCount; i++) + { + /* Read mem_write_data bitfield (mem_write_data[7:0] has to be the last register read) */ + /* core_bf.mem_write_data.write(bf_status, 32'hxxxxxxxx); */ + index = address % WORD_LENGTH; + + addrArray[addrIndex] = ADDR_ARM_DMA_DATA[index]; + + addrIndex++; + address++; + + if (addrIndex >= spiBufferSize) + { + ADRV9025_SPIREADBYTESDMA("DMA_MEM_READ_CACHE", + (address - addrIndex), + &addrArray[0], + &returnData[dataCounter], + addrIndex); + dataCounter += addrIndex; + addrIndex = 0; + } + } + + if (addrIndex > 0) + { + ADRV9025_SPIREADBYTESDMA("DMA_MEM_READ_CACHE_LAST", + (address - addrIndex), + &addrArray[0], + &returnData[dataCounter], + addrIndex); + } + + for (i = 0; i < wordCount; i++) + { + /* Reorder bytes from Data3-2-1-0 to Data0-1-2-3. This is required because API reads data starting from Data3(lower address) to hit Data0(higher address) last */ + tempByte = returnData[i * WORD_LENGTH]; + returnData[i * WORD_LENGTH] = returnData[(i * WORD_LENGTH) + 3]; + returnData[(i * WORD_LENGTH) + 3] = tempByte; + + tempByte = returnData[(i * WORD_LENGTH) + 1]; + returnData[(i * WORD_LENGTH) + 1] = returnData[(i * WORD_LENGTH) + 2]; + returnData[(i * WORD_LENGTH) + 2] = tempByte; + } + } + else + { + /* 4) NON-STREAMING WITHOUT CACHE */ + /* starting write at zero address offset */ + for (i = 0; i < byteCount; i += 4) + { + /* Write mem_write_data bitfield (mem_write_data[7:0] has to be the last register written) */ + /* core_bf.mem_write_data.write(bf_status, 32'hxxxxxxxx); */ + ADRV9025_SPIREADWORDDMA("ARM_DMA_ADDR", + ADRV9025_CPU_ADDR_DMA_DATA3, + &dataRead) + + returnData[i + 3] = (uint8_t)(dataRead >> 24); + returnData[i + 2] = (uint8_t)(dataRead >> 16); + returnData[i + 1] = (uint8_t)(dataRead >> 8); + returnData[i + 0] = (uint8_t)(dataRead >> 0); + + if (autoIncrement == ADI_FALSE) + { + /* AHB address for read */ + /* core_bf.bus_addr.write(bf_status, 32'hxxxxxxxx); */ + address += 4; + ADRV9025_SPIWRITEWORDDMA("ARM_DMA_ADDR", + ADRV9025_CPU_ADDR_DMA_ADDR3, + address); + } + } + } + +#if ADI_ADRV9025_SPI_READ_STREAMING_ENABLE == 1 + /* Disable Spi streaming */ + ADRV9025_SPI_STREAM_DISABLE(device); +#endif + + return (device->common.error.newAction); +} + +const char* adrv9025_CpuErrCodeToString( + adi_adrv9025_Device_t* device, + uint32_t errCode) +{ + UNUSED_PARA(device); +#if ADI_ADRV9025_CPU_VERBOSE == 0 + return ""; +#else + const char* result = NULL; + uint32_t min = 0u; + uint32_t max = (sizeof(adrv9025_error_table_ErrorCode) / sizeof(adrv9025_arm_api_error_t)) - 1u; + uint32_t curr = (min + max) / 2; + + /* do a binary search */ + while (min <= max && result == NULL) + { + if (errCode == adrv9025_error_table_ErrorCode[curr].errcode) + { + result = adrv9025_error_table_ErrorCode[curr].errstr; + } + else if (errCode < adrv9025_error_table_ErrorCode[curr].errcode) + { + max = curr - 1u; + } + else + { + min = curr + 1u; + } + + curr = (min + max) / 2; + } + + return result; +#endif +} + +int32_t adrv9025_CpuCmdErrorHandler( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + int32_t errHdl, + uint32_t detErr, + int32_t recoveryAction) +{ + UNUSED_PARA(errHdl); + int32_t recAction = recoveryAction; + uint8_t cpuOpCode = 0; + uint8_t cpuObjId = 0; + uint8_t cmdStatusByte = 0; + uint32_t cpuErrorFlag = 0; + uint32_t cpuErrorCode = 0; + uint16_t mailboxErrCode = 0; + const char* errorString = NULL; + static const uint8_t ERR_FLAG_MASK = 0x0E; + static const uint8_t ERR_FLAG_SHIFT = 1; + + cpuOpCode = (uint8_t)(detErr >> ADRV9025_CPU_OPCODE_SHIFT); + cpuObjId = (uint8_t)(detErr >> ADRV9025_CPU_OBJ_ID_SHIFT); + cmdStatusByte = (uint8_t)(detErr); + + /* perform object id overrides for opcodes Abort, RunInit, RadioOn */ + if ((cpuOpCode == ADRV9025_CPU_ABORT_OPCODE) + || (cpuOpCode == ADRV9025_CPU_RUNINIT_OPCODE) + || (cpuOpCode == ADRV9025_CPU_RADIOON_OPCODE)) + { + cpuObjId = 0x00; + } + + cpuErrorFlag = ADRV9025_BF_DECODE(cmdStatusByte, + ERR_FLAG_MASK, + ERR_FLAG_SHIFT); + + if (cpuErrorFlag > 0) + { + cpuErrorCode = ADRV9025_CPU_CMD_ERRCODE(cpuOpCode, + cpuObjId, + cpuErrorFlag); + if (cpuErrorCode == ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_RUNINIT_OPCODE, + 0, + 7)) + { + recAction = ADI_ADRV9025_ACT_ERR_RERUN_INIT_CALS; + } + else + { + switch (adrv9025_CpuErrorFlagGet(cpuErrorCode)) + { + case ADRV9025_CPU_ERROR_FLAG_1: + case ADRV9025_CPU_ERROR_FLAG_2: + case ADRV9025_CPU_ERROR_FLAG_3: + case ADRV9025_CPU_ERROR_FLAG_4: + case ADRV9025_CPU_ERROR_FLAG_5: + case ADRV9025_CPU_ERROR_FLAG_6: + case ADRV9025_CPU_ERROR_FLAG_7: + recAction = ADI_COMMON_ACT_ERR_CHECK_PARAM; + break; + default: + recAction = ADI_COMMON_ACT_NO_ACTION; + } + } + + if (recAction != ADI_COMMON_ACT_NO_ACTION) + { + errorString = adrv9025_CpuErrMsgGet(device, + cpuType, + detErr, + &mailboxErrCode); + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUCMD, + detErr, + recAction, + detErr, + errorString); + + /* Report Cpu mailboxErrCode*/ + if ((cpuErrorFlag == 7) && (mailboxErrCode > 0)) + { + errorString = adrv9025_CpuErrCodeToString(device, + mailboxErrCode); + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUCMD, + mailboxErrCode, + recAction, + mailboxErrCode, + errorString); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recAction; +} + +int32_t adrv9025_CpuAdcProfilesWrite(adi_adrv9025_Device_t* device, + const adi_adrv9025_AdcProfiles_t* adcProfiles) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t cfgData[ADRV9025_PROFILE_CHUNK_MAX + 10] = {0}; + uint32_t profileAddr = 0; + uint32_t checksum = 0; + uint32_t start = 0; + + static const uint32_t ADRV9025_ADDR_DEVICE_PROFILE = 0x20000000; + static const uint32_t ADRV9025_ADC_PROFILE_MAX = 684; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + adcProfiles); + + ADRV9025_BUGINFO(__FUNCTION__); + + if (device->devStateInfo.cpu.adcProfileAddr < ADRV9025_ADDR_DEVICE_PROFILE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid ADC profile Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + adrv9025_CpuDataSet(cfgData, + 0, + ADRV9025_PROFILE_CHUNK_MAX); + start = 0; + /* RX CONFIG 96 bytes: 20 - 115 */ + adrv9025_CpuLoadAdcBytes(start, + &cfgData[0], + &adcProfiles->RxChannel1[0]); + start += ADRV9025_CPU_ADC_PROFILE_SIZE; + adrv9025_CpuLoadAdcBytes(start, + &cfgData[0], + &adcProfiles->RxChannel2[0]); + start += ADRV9025_CPU_ADC_PROFILE_SIZE; + adrv9025_CpuLoadAdcBytes(start, + &cfgData[0], + &adcProfiles->RxChannel3[0]); + start += ADRV9025_CPU_ADC_PROFILE_SIZE; + adrv9025_CpuLoadAdcBytes(start, + &cfgData[0], + &adcProfiles->RxChannel4[0]); + start += ADRV9025_CPU_ADC_PROFILE_SIZE; + + profileAddr = device->devStateInfo.cpu.adcProfileAddr; + checksum = adrv9025_Crc32ForChunk(&cfgData[0], + start, + checksum, + 0); + recoveryAction = adi_adrv9025_CpuMemWrite(device, + profileAddr, + &cfgData[0], + start, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Error from adi_adrv9025_CpuMemWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + + profileAddr += start; + start = 0; + adrv9025_CpuDataSet(&cfgData[0], + 0, + ADRV9025_PROFILE_CHUNK_MAX); + adrv9025_CpuLoadAdcBytes(start, + &cfgData[0], + &adcProfiles->OrxChannel1Profile0[0]); + start += ADRV9025_CPU_ADC_PROFILE_SIZE; + adrv9025_CpuLoadAdcBytes(start, + &cfgData[0], + &adcProfiles->OrxChannel1Profile1[0]); + start += ADRV9025_CPU_ADC_PROFILE_SIZE; + adrv9025_CpuLoadAdcBytes(start, + &cfgData[0], + &adcProfiles->OrxChannel1Profile2[0]); + start += ADRV9025_CPU_ADC_PROFILE_SIZE; + adrv9025_CpuLoadAdcBytes(start, + &cfgData[0], + &adcProfiles->OrxChannel1Profile3[0]); + start += ADRV9025_CPU_ADC_PROFILE_SIZE; + + checksum = adrv9025_Crc32ForChunk(&cfgData[0], + start, + checksum, + 0); + recoveryAction = adi_adrv9025_CpuMemWrite(device, + profileAddr, + &cfgData[0], + start, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Error from adi_adrv9025_CpuMemWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + + profileAddr += start; + start = 0; + adrv9025_CpuDataSet(&cfgData[0], + 0, + ADRV9025_PROFILE_CHUNK_MAX); + + adrv9025_CpuLoadAdcBytes(start, + &cfgData[0], + &adcProfiles->OrxChannel2Profile0[0]); + start += ADRV9025_CPU_ADC_PROFILE_SIZE; + adrv9025_CpuLoadAdcBytes(start, + &cfgData[0], + &adcProfiles->OrxChannel2Profile1[0]); + start += ADRV9025_CPU_ADC_PROFILE_SIZE; + adrv9025_CpuLoadAdcBytes(start, + &cfgData[0], + &adcProfiles->OrxChannel2Profile2[0]); + start += ADRV9025_CPU_ADC_PROFILE_SIZE; + adrv9025_CpuLoadAdcBytes(start, + &cfgData[0], + &adcProfiles->OrxChannel2Profile3[0]); + start += ADRV9025_CPU_ADC_PROFILE_SIZE; + + cfgData[start++] = adcProfiles->OrxChannel1Index; + + cfgData[start++] = adcProfiles->OrxChannel2Index; + + /* Reserved 6 bytes */ + start += 6; + + /* Profile Checksum 4 bytes: 608 - 611 */ + checksum = adrv9025_Crc32ForChunk(&cfgData[0], + start, + checksum, + 1); /* last checksum */ + adrv9025_CpuLoadFourBytes(start, + &cfgData[0], + checksum); + start += 4; + + recoveryAction = adi_adrv9025_CpuMemWrite(device, + profileAddr, + &cfgData[0], + start, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Error from adi_adrv9025_CpuMemWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + + profileAddr += start; + start = 0; + + if (profileAddr != (device->devStateInfo.cpu.adcProfileAddr + ADRV9025_ADC_PROFILE_MAX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + profileAddr, + "Exceed Max ADC Profile bytes"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +/* +API to CPU Clock Profile: Structure DeviceProfile_t +Size: 1256 bytes +Element Size Type Range Description +VcoFreqKhz 4 uint32 4915.2- 12288 Mhz VCO frequency of the system as set by API, in Khz. +hsDigHz_api 4 uint32 490-1250 Mhz System HS Dig clock setting calculated by the API in Hz. +deviceClockHz 4 uint32 61.44-983.04 Mhz + System device clock setting, in multiples of 61.44 in Hz. +clkGenSel 1 uint8 0 or 1 PLL select (Serdes or ClkPLL). Typically ClkPll will be selected but for debug it will be possible to use Serdes. +LoPhaseSync 1 uint8 0-2 0 = Don't Sync +1 = Run Init and sync +2 = Run init and Continuous tracking +LoSelect 1 uint8 0-0x3F D0 - Rx12 Sel 0 = LO1 to Rx12, 1 = LO2 to Rx12 +D1 - Rx34 Sel 0 = LO1 to Rx34, 1 = LO2 to Rx34 +D2 - Tx12 Sel 0 = LO1 to Tx12, 1 = LO2 to Tx12 +D3 - Tx34 Sel 0 = LO1 to Tx34, 1 = LO2 to Tx34 +D4 - Orx12 Sel 0 = TxLO to Orx12, 1 = AuxLO to Orx12 +D5 - Orx34 Sel 0 = TxLO to Orx34, 1 = AuxLO to Orx34 +NOTE: The TxLO is the LO that is routed to the Tx. +NOTE: LO1 = RxLO, LO2 = TxLO +extLoSel 1 uint8 0-0xF D0-2 - LO1 Sel: +0 = Inter LO1, 0x1 = Ext out, 0x2 = Ext in x2, 0x3 = Extin x4, 0x4 = Ext in x8 + +D3-5 - LO2 Sel: +0 = Inter LO2, 0x1 = Ext out, 0x2 = Ext in x2, 0x3 = Extin x4, 0x4 = Ext in x8 + +D6 - Swap cntrl for Ext LO1 : Def = 0 no-swap,1=swap +D7 - Swap cntrl for Ext LO2: Def = 0 no-swap,1=swap +Ext LO Freq 1 4 uint32 25Mhz to 12 Ghz External LO 1 freq in Khz +Ext LO Freq 2 4 uint32 25Mhz to 12 Ghz External LO 1 freq in Khz + +chanConfig 2 uint16 0-0xFFF D0 - Tx1 0 = Disabled, 1 = Enabled +D1 - Tx2 0 = Disabled, 1 = Enabled +D2 - Tx3 0 = Disabled, 1 = Enabled +D3 - Tx4 0 = Disabled, 1 = Enabled +D4 - Rx1 0 = Disabled, 1 = Enabled +D5 - Rx2 0 = Disabled, 1 = Enabled +D6 - Rx3 0 = Disabled, 1 = Enabled +D7 - Rx4 0 = Disabled, 1 = Enabled +D8 - Orx1 0 = Disabled, 1 = Enabled +D9 - Orx2 0 = Disabled, 1 = Enabled +D10 - Orx3 0 = Disabled, 1 = Enabled +D11 - Orx4 0 = Disabled, 1 = Enabled +D12 - Lbrx1/2 0 = Disabled, 1 = Enabled +D13 - Lbrx3/4 0 = Disabled, 1 = Enabled +Ext LO1 Divider 1 ExtLo1Div This divider is independent from internal LO1 gen divider +(valid 1, 2, 4, 8, 16, 32, 64, 128) +Ext LO2 Divider 1 ExtLo2Div This divider is independent from internal LO1 gen divider +(valid 1, 2, 4, 8, 16, 32, 64, 128) +Padding[8] 8 uint8 +RxConfig[4] 288 RxConfig_t Receiver profile for channels 1 to 4, refer to Table 3. + +TxConfig[4] 160 TxConfig_t Transmit profile for channels 1 to 4, refer to Table 4. + +OrxConfig[4] 224 OrxConfig_t Orx profile for channels 1 to 4, refer to Table 5. + +LbConfig[2] 112 OrxConfig_t Loopback profile for channels 1 to 2, refer to Table 5. + +JESD Profile 380 JesdSettings_t JSED profile, refer to Table 7. + +Noise Cancellation 36 noiseCancel_t Noise cancellation configuration, refer to +Reserved[16] 16 uint8 16 bytes reserved memory. +Profile checksum 4 uint32 Checksum of the entire profile excluding ADC profiles, Using the CRC32 algorithm. + + + **/ + +int32_t adrv9025_CpuProfileWrite(adi_adrv9025_Device_t* device, + const adi_adrv9025_Init_t* init) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t profileAddr = 0; + uint32_t cpuChannels = 0; + uint32_t checksum = 0; + uint32_t start = 0; + uint32_t i = 0; + uint8_t cfgData[ADRV9025_PROFILE_CHUNK_MAX + 10] = {0}; + + static const uint32_t ADRV9025_ADDR_DEVICE_PROFILE = 0x20000000; + static const uint32_t ADRV9025_PROFILE_MAX = 1352; + + static const uint32_t ADRV9025_PROFILE_TX = 40; + static const uint32_t ADRV9025_PROFILE_RX = 72; + static const uint32_t ADRV9025_PROFILE_ORX = 56; + + static const uint32_t ADRV9025_PROFILE_JESD_FRAMER = 53; + static const uint32_t ADRV9025_PROFILE_JESD_DEFRAMER = 38; + static const uint32_t ADRV9025_PROFILE_JESD_SERCFG = 8; + static const uint32_t ADRV9025_PROFILE_JESD_DESCFG = 44; + static const uint32_t ADRV9025_PROFILE_JESD_LINKSHARING = 20; + static const uint32_t ADRV9025_PROFILE_JESD_DATACONFIG = 3; + static const uint32_t ADRV9025_PROFILE_JESD_END = 8; + static const uint32_t ADRV9025_PROFILE_NOISE_CANCEL = 36; + + static const uint32_t ADRV9025_TX1 = 0x001; /*!< Rx1 channel enabled */ + static const uint32_t ADRV9025_TX2 = 0x002; /*!< Rx2 channel enabled */ + static const uint32_t ADRV9025_TX3 = 0x004; /*!< Rx3 channel enabled */ + static const uint32_t ADRV9025_TX4 = 0x008; /*!< Rx4 channel enabled */ + static const uint32_t ADRV9025_RX1 = 0x010; /*!< Rx1 channel enabled */ + static const uint32_t ADRV9025_RX2 = 0x020; /*!< Rx2 channel enabled */ + static const uint32_t ADRV9025_RX3 = 0x040; /*!< Rx3 channel enabled */ + static const uint32_t ADRV9025_RX4 = 0x080; /*!< Rx4 channel enabled */ + static const uint32_t ADRV9025_ORX1 = 0x100; /*!< ORx1 channel enabled */ + static const uint32_t ADRV9025_ORX2 = 0x200; /*!< ORx2 channel enabled */ + static const uint32_t ADRV9025_ORX3 = 0x400; /*!< ORx3 channel enabled */ + static const uint32_t ADRV9025_ORX4 = 0x800; /*!< ORx4 channel enabled */ + static const uint32_t ADRV9025_LB12 = 0x1000; /*!< LBx12 channel enabled */ + static const uint32_t ADRV9025_LB34 = 0x2000; /*!< LBx34 channel enabled */ + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + init); + + ADRV9025_BUGINFO(__FUNCTION__); + + if (device->devStateInfo.cpu.devProfileAddr < ADRV9025_ADDR_DEVICE_PROFILE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid profile Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + adrv9025_CpuDataSet(&cfgData[0], + 0, + ADRV9025_PROFILE_CHUNK_MAX); + + adrv9025_CpuLoadFourBytes(0, + &cfgData[0], + (init->clocks.clkPllVcoFreq_kHz)); + adrv9025_CpuLoadFourBytes(4, + &cfgData[0], + (device->devStateInfo.hsDigClk_kHz * 1000)); + adrv9025_CpuLoadFourBytes(8, + &cfgData[0], + (init->clocks.deviceClock_kHz * 1000)); + + cfgData[12] = 1; /* clkGenSel User PLL */ +#ifdef API_ADRV9025_USE_SERDES + cfgData[12] = 0; /* clkGenSel User SERDES */ +#endif + + if ((init->clocks.rx12LoSelect != ADI_ADRV9025_LOSEL_LO1) && + (init->clocks.rx12LoSelect != ADI_ADRV9025_LOSEL_LO2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + init->clocks.rx12LoSelect, + "Invalid LO Select for Rx1/Rx2. Valid values are LO1(1) and LO2(2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((init->clocks.rx34LoSelect != ADI_ADRV9025_LOSEL_LO1) && + (init->clocks.rx34LoSelect != ADI_ADRV9025_LOSEL_LO2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + init->clocks.rx34LoSelect, + "Invalid LO Select for Rx3/Rx4. Valid values are LO1(1) and LO2(2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((init->clocks.tx12LoSelect != ADI_ADRV9025_LOSEL_LO1) && + (init->clocks.tx12LoSelect != ADI_ADRV9025_LOSEL_LO2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + init->clocks.tx12LoSelect, + "Invalid LO Select for Tx1/Tx2. Valid values are LO1(1) and LO2(2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((init->clocks.tx34LoSelect != ADI_ADRV9025_LOSEL_LO1) && + (init->clocks.tx34LoSelect != ADI_ADRV9025_LOSEL_LO2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + init->clocks.tx34LoSelect, + "Invalid LO Select for Tx3/Tx4. Valid values are LO1(1) and LO2(2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((init->clocks.orx12LoSelect != ADI_ADRV9025_ORXLOSEL_TXLO) && + (init->clocks.orx12LoSelect != ADI_ADRV9025_ORXLOSEL_AUXLO)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + init->clocks.orx12LoSelect, + "Invalid LO Select for Orx1/Orx2. Valid values are TXLO(1) and AuxLO(2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((init->clocks.orx34LoSelect != ADI_ADRV9025_ORXLOSEL_TXLO) && + (init->clocks.orx34LoSelect != ADI_ADRV9025_ORXLOSEL_AUXLO)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + init->clocks.orx34LoSelect, + "Invalid LO Select for Orx3/Orx4. Valid values are TXLO(1) and AuxLO(2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + cfgData[13] = init->clocks.rfPllPhaseSyncMode; /* lophaseSync ?*/ + cfgData[14] = ((uint8_t)init->clocks.rx12LoSelect - 1) & 0x01; + cfgData[14] |= ((((uint8_t)init->clocks.rx34LoSelect - 1) & 0x01) << 1); + cfgData[14] |= ((((uint8_t)init->clocks.tx12LoSelect - 1) & 0x01) << 2); + cfgData[14] |= ((((uint8_t)init->clocks.tx34LoSelect - 1) & 0x01) << 3); + cfgData[14] |= ((((uint8_t)init->clocks.orx12LoSelect - 1) & 0x01) << 4); + cfgData[14] |= ((((uint8_t)init->clocks.orx34LoSelect - 1) & 0x01) << 5); + + if ((init->clocks.rfPll1LoMode != ADI_ADRV9025_INTLO_NOOUTPUT) && + (init->clocks.rfPll1LoMode != ADI_ADRV9025_INTLO_OUTPUT) && + (init->clocks.rfPll1LoMode != ADI_ADRV9025_EXTLO_2X_INPUT) && + (init->clocks.rfPll1LoMode != ADI_ADRV9025_EXTLO_4X_INPUT) && + (init->clocks.rfPll1LoMode != ADI_ADRV9025_EXTLO_8X_INPUT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + init->clocks.rfPll1LoMode, + "Invalid Rf Pll1 LO Mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((init->clocks.rfPll2LoMode != ADI_ADRV9025_INTLO_NOOUTPUT) && + (init->clocks.rfPll2LoMode != ADI_ADRV9025_INTLO_OUTPUT) && + (init->clocks.rfPll2LoMode != ADI_ADRV9025_EXTLO_2X_INPUT) && + (init->clocks.rfPll2LoMode != ADI_ADRV9025_EXTLO_4X_INPUT) && + (init->clocks.rfPll2LoMode != ADI_ADRV9025_EXTLO_8X_INPUT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + init->clocks.rfPll2LoMode, + "Invalid Rf Pll2 LO Mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + cfgData[15] = (uint8_t)(init->clocks.rfPll1LoMode & 0x07); + cfgData[15] |= (uint8_t)((init->clocks.rfPll2LoMode & 0x07) << 3); + + adrv9025_CpuLoadFourBytes(16, + &cfgData[0], + (init->clocks.extLoFreq1_kHz)); /* External LO freq 1 in Khz */ + adrv9025_CpuLoadFourBytes(20, + &cfgData[0], + (init->clocks.extLoFreq2_kHz)); /* External LO freq 2 in Khz */ + + if (ADRV9025_BF_EQUAL(device->devStateInfo.profilesValid, + ADI_ADRV9025_RX_PROFILE_VALID)) + { + if (ADRV9025_BF_EQUAL(init->rx.rxInitChannelMask, + ADI_ADRV9025_RX1)) + { + cpuChannels |= ADRV9025_RX1; + } + if (ADRV9025_BF_EQUAL(init->rx.rxInitChannelMask, + ADI_ADRV9025_RX2)) + { + cpuChannels |= ADRV9025_RX2; + } + if (ADRV9025_BF_EQUAL(init->rx.rxInitChannelMask, + ADI_ADRV9025_RX3)) + { + cpuChannels |= ADRV9025_RX3; + } + if (ADRV9025_BF_EQUAL(init->rx.rxInitChannelMask, + ADI_ADRV9025_RX4)) + { + cpuChannels |= ADRV9025_RX4; + } + } + + if (ADRV9025_BF_EQUAL(device->devStateInfo.profilesValid, + ADI_ADRV9025_TX_PROFILE_VALID)) + { + if (ADRV9025_BF_EQUAL(init->tx.txInitChannelMask, + ADI_ADRV9025_TX1)) + { + cpuChannels |= ADRV9025_TX1; + } + if (ADRV9025_BF_EQUAL(init->tx.txInitChannelMask, + ADI_ADRV9025_TX2)) + { + cpuChannels |= ADRV9025_TX2; + } + if (ADRV9025_BF_EQUAL(init->tx.txInitChannelMask, + ADI_ADRV9025_TX3)) + { + cpuChannels |= ADRV9025_TX3; + } + if (ADRV9025_BF_EQUAL(init->tx.txInitChannelMask, + ADI_ADRV9025_TX4)) + { + cpuChannels |= ADRV9025_TX4; + } + } + + if (ADRV9025_BF_EQUAL(device->devStateInfo.profilesValid, + ADI_ADRV9025_ORX_PROFILE_VALID)) + { + if (ADRV9025_BF_EQUAL(init->rx.rxInitChannelMask, + ADI_ADRV9025_ORX1)) + { + cpuChannels |= ADRV9025_ORX1; + } + if (ADRV9025_BF_EQUAL(init->rx.rxInitChannelMask, + ADI_ADRV9025_ORX2)) + { + cpuChannels |= ADRV9025_ORX2; + } + if (ADRV9025_BF_EQUAL(init->rx.rxInitChannelMask, + ADI_ADRV9025_ORX3)) + { + cpuChannels |= ADRV9025_ORX3; + } + if (ADRV9025_BF_EQUAL(init->rx.rxInitChannelMask, + ADI_ADRV9025_ORX4)) + { + cpuChannels |= ADRV9025_ORX4; + } + } + + if (ADRV9025_BF_EQUAL(device->devStateInfo.profilesValid, + ADI_ADRV9025_LB_PROFILE_VALID)) + { + if (ADRV9025_BF_EQUAL(init->rx.rxInitChannelMask, + ADI_ADRV9025_LB12)) + { + cpuChannels |= ADRV9025_LB12; + } + if (ADRV9025_BF_EQUAL(init->rx.rxInitChannelMask, + ADI_ADRV9025_LB34)) + { + cpuChannels |= ADRV9025_LB34; + } + } + + cfgData[24] = (uint8_t)((cpuChannels) & 0x000000FF); + cfgData[25] = (uint8_t)((cpuChannels >> 8) & 0x000000FF); + + if ((init->clocks.rfPll1LoOutDivider != 0) && + (init->clocks.rfPll1LoOutDivider != 1) && + (init->clocks.rfPll1LoOutDivider != 2) && + (init->clocks.rfPll1LoOutDivider != 4) && + (init->clocks.rfPll1LoOutDivider != 8) && + (init->clocks.rfPll1LoOutDivider != 16) && + (init->clocks.rfPll1LoOutDivider != 32) && + (init->clocks.rfPll1LoOutDivider != 64) && + (init->clocks.rfPll1LoOutDivider != 128)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + init->clocks.rfPll1LoOutDivider, + "Invalid clock rfPll1LoOutDivider. Valid values are 0, 1, 2, 4, 8, 16, 32, 64, 128"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + cfgData[26] = (uint8_t)(init->clocks.rfPll1LoOutDivider); + + if ((init->clocks.rfPll2LoOutDivider != 0) && + (init->clocks.rfPll2LoOutDivider != 1) && + (init->clocks.rfPll2LoOutDivider != 2) && + (init->clocks.rfPll2LoOutDivider != 4) && + (init->clocks.rfPll2LoOutDivider != 8) && + (init->clocks.rfPll2LoOutDivider != 16) && + (init->clocks.rfPll2LoOutDivider != 32) && + (init->clocks.rfPll2LoOutDivider != 64) && + (init->clocks.rfPll2LoOutDivider != 128)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + init->clocks.rfPll2LoOutDivider, + "Invalid clock rfPll2LoOutDivider. Valid values are 0, 1, 2, 4, 8, 16, 32, 64, 128"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + cfgData[27] = (uint8_t)(init->clocks.rfPll2LoOutDivider); + + /* Pass LDO Select to CPU */ + cfgData[28] = init->clocks.ldoSelect; + cfgData[29] = 0; + cfgData[30] = 0; + cfgData[31] = 0; + cfgData[32] = 0; + cfgData[33] = 0; + cfgData[34] = 0; + cfgData[35] = 0; + + start = 36; + + profileAddr = device->devStateInfo.cpu.devProfileAddr; + + checksum = adrv9025_Crc32ForChunk(&cfgData[0], + start, + checksum, + 0); + recoveryAction = adi_adrv9025_CpuMemWrite(device, + profileAddr, + &cfgData[0], + start, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Error from adi_adrv9025_CpuMemWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + + profileAddr += start; // offset = 36 + start = 0; + adrv9025_cfgDataSet(&cfgData[0], + 0, + ADRV9025_PROFILE_CHUNK_MAX); + + /* RX CONFIG 144 bytes */ + for (i = 0; i < 2; i++) + { + adrv9025_CpuLoadRxBytes(start, + &cfgData[0], + &init->rx.rxChannelCfg[i].profile); + start += ADRV9025_PROFILE_RX; + } + + checksum = adrv9025_Crc32ForChunk(&cfgData[0], + start, + checksum, + 0); + recoveryAction = adi_adrv9025_CpuMemWrite(device, + profileAddr, + &cfgData[0], + start, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + profileAddr += start; //offset = 180 + start = 0; + adrv9025_cfgDataSet(&cfgData[0], + 0, + ADRV9025_PROFILE_CHUNK_MAX); + + /* ORx config 144 bytes */ + for (i = 2; i < 4; i++) + { + adrv9025_CpuLoadRxBytes(start, + &cfgData[0], + &init->rx.rxChannelCfg[i].profile); + start += ADRV9025_PROFILE_RX; + } + + checksum = adrv9025_Crc32ForChunk(&cfgData[0], + start, + checksum, + 0); + recoveryAction = adi_adrv9025_CpuMemWrite(device, + profileAddr, + &cfgData[0], + start, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Error from adi_adrv9025_CpuMemWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + + profileAddr += start; // offset = 324 + start = 0; + adrv9025_cfgDataSet(&cfgData[0], + 0, + ADRV9025_PROFILE_CHUNK_MAX); + + /* TX CONFIG 160 bytes */ + for (i = 0; i < 4; i++) + { + adrv9025_CpuLoadTxByte(start, + &cfgData[0], + &init->tx.txChannelCfg[i].profile); + start += ADRV9025_PROFILE_TX; + } + + checksum = adrv9025_Crc32ForChunk(&cfgData[0], + start, + checksum, + 0); + recoveryAction = adi_adrv9025_CpuMemWrite(device, + profileAddr, + &cfgData[0], + start, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Error from adi_adrv9025_CpuMemWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + + profileAddr += start; // offset = 484 + start = 0; + + /* ORX CONFIG 224 bytes */ + for (i = 4; i < 8; i++) + { + adrv9025_CpuLoadOrxBytes(start, + &cfgData[0], + &init->rx.rxChannelCfg[i].profile); + start += ADRV9025_PROFILE_ORX; + } + + checksum = adrv9025_Crc32ForChunk(&cfgData[0], + start, + checksum, + 0); + recoveryAction = adi_adrv9025_CpuMemWrite(device, + profileAddr, + &cfgData[0], + start, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Error from adi_adrv9025_CpuMemWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + + profileAddr += start; // offset = 708 + start = 0; + adrv9025_cfgDataSet(&cfgData[0], + 0, + ADRV9025_PROFILE_CHUNK_MAX); + + /* LB ORX CONFIG 112 bytes */ + for (i = 8; i < 10; i++) + { + adrv9025_CpuLoadOrxBytes(start, + &cfgData[0], + &init->rx.rxChannelCfg[i].profile); + start += ADRV9025_PROFILE_ORX; + } + + checksum = adrv9025_Crc32ForChunk(&cfgData[0], + start, + checksum, + 0); + recoveryAction = adi_adrv9025_CpuMemWrite(device, + profileAddr, + &cfgData[0], + start, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Error from adi_adrv9025_CpuMemWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + + profileAddr += start; // offset = 820 + start = 0; + adrv9025_cfgDataSet(&cfgData[0], + 0, + ADRV9025_PROFILE_CHUNK_MAX); + + /* JESD CONFIG 342 bytes */ + /* Frammer 3 * 53byte = 159 bytes */ + for (i = 0; i < 3; i++) + { + adrv9025_CpuLoadFramerBytes(start, + &cfgData[0], + &init->dataInterface.framer[i]); + start += ADRV9025_PROFILE_JESD_FRAMER; + } + + checksum = adrv9025_Crc32ForChunk(&cfgData[0], + start, + checksum, + 0); + recoveryAction = adi_adrv9025_CpuMemWrite(device, + profileAddr, + &cfgData[0], + start, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Error from adi_adrv9025_CpuMemWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + + profileAddr += start; // offset = 979 + start = 0; + adrv9025_cfgDataSet(&cfgData[0], + 0, + ADRV9025_PROFILE_CHUNK_MAX); + + /* Deframer: 2 * 38 bytes = 76 bytes */ + for (i = 0; i < 2; i++) + { + adrv9025_CpuLoadDeframerBytes(start, + &cfgData[0], + &init->dataInterface.deframer[i]); + start += ADRV9025_PROFILE_JESD_DEFRAMER; + } + + checksum = adrv9025_Crc32ForChunk(&cfgData[0], + start, + checksum, + 0); + recoveryAction = adi_adrv9025_CpuMemWrite(device, + profileAddr, + &cfgData[0], + start, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Error from adi_adrv9025_CpuMemWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + + profileAddr += start; // offset = 1055 + start = 0; + adrv9025_cfgDataSet(&cfgData[0], + 0, + ADRV9025_PROFILE_CHUNK_MAX); + + /* Serializer ADI_ADRV9025_NUM_LANES * 8 bytes = 32 bytes */ + for (i = 0; i < ADI_ADRV9025_NUM_LANES; i++) + { + adrv9025_CpuLoadSerBytes(start, + &cfgData[0], + &init->dataInterface.serCfg[i]); + start += ADRV9025_PROFILE_JESD_SERCFG; + } + + cfgData[start++] = 0; + + /* Deserializer ADI_ADRV9025_NUM_LANES * 44 bytes = 176 bytes */ + for (i = 0; i < ADI_ADRV9025_NUM_LANES; i++) + { + adrv9025_CpuLoadDesBytes(start, + &cfgData[0], + &init->dataInterface.desCfg[i]); + start += ADRV9025_PROFILE_JESD_DESCFG; + } + + /* Link sharing 20 bytes */ + adrv9025_CpuLoadLinkSharing(start, + &cfgData[0], + &init->dataInterface.linkSharingCfg); + start += ADRV9025_PROFILE_JESD_LINKSHARING; + + /* Data configuration 3 bytes */ + adrv9025_CpuLoadDataConfig(start, + &cfgData[0], + &init->dataInterface.dataCfg); + start += ADRV9025_PROFILE_JESD_DATACONFIG; + + checksum = adrv9025_Crc32ForChunk(&cfgData[0], + start, + checksum, + 0); + recoveryAction = adi_adrv9025_CpuMemWrite(device, + profileAddr, + &cfgData[0], + start, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Error from adi_adrv9025_CpuMemWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + + profileAddr += start; // offset = 1287 (extra padded byte before deserializer structs) + start = 0; + adrv9025_cfgDataSet(&cfgData[0], + 0, + ADRV9025_PROFILE_CHUNK_MAX); + + /* Jesd 8 bytes */ + cfgData[start + 0] = init->dataInterface.channelSelect; + cfgData[start + 1] = init->dataInterface.channelMode; + cfgData[start + 2] = 0; + cfgData[start + 3] = 0; + cfgData[start + 4] = 0; + cfgData[start + 5] = 0; + cfgData[start + 6] = 0; + cfgData[start + 7] = 0; + + start += ADRV9025_PROFILE_JESD_END; + + cfgData[start++] = 0; + + /* Noise Cancellation 36 bytes */ + adrv9025_CpuLoadNoiseCancelBytes(start, + &cfgData[0]); + start += ADRV9025_PROFILE_NOISE_CANCEL; + + /* Reserved 16 bytes */ + adrv9025_CpuLoadFourBytes(start + 0, + &cfgData[0], + 0); + adrv9025_CpuLoadFourBytes(start + 4, + &cfgData[0], + 0); + adrv9025_CpuLoadFourBytes(start + 8, + &cfgData[0], + 0); + adrv9025_CpuLoadFourBytes(start + 12, + &cfgData[0], + 0); + + start += 16; + /* Profile Checksum 4 bytes */ + checksum = adrv9025_Crc32ForChunk(&cfgData[0], + start, + checksum, + 1); /* last checksum */ + adrv9025_CpuLoadFourBytes(start, + &cfgData[0], + checksum); + start += 4; + + /* Final bytes */ + recoveryAction = adi_adrv9025_CpuMemWrite(device, + profileAddr, + &cfgData[0], + start, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Error from adi_adrv9025_CpuMemWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + + profileAddr += start; // offset = 1352 (extra padded byte before noise cancel struct) + start = 0; + + if (profileAddr != (device->devStateInfo.cpu.devProfileAddr + ADRV9025_PROFILE_MAX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + profileAddr, + "Exceed Max Profile bytes"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} +int32_t adrv9025_CpuSerdesTestModeEnter(adi_adrv9025_Device_t* device) +{ + int32_t recoverAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t extData[4] = { 0 }; + uint8_t cmdStatusByte = 0; + + static const uint8_t SERDES_QR_MODE = 1; + static const uint8_t ARM_ERR_CODE = 0x0E; + static const uint8_t SERDES_TEST_MODE = 0x08; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API_PRIV); + + /* Arm Test Mode Configuration */ + extData[0] = ADRV9025_CPU_OBJECTID_GS_TEST_MODE; + extData[1] = SERDES_TEST_MODE; /* test_mode_serdes */ + extData[2] = SERDES_QR_MODE; /* serdes qr mode */ + + /* Write the extData - arm configuration to ADI_ADRV9025_CPU_TYPE_C */ + recoverAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_SET_OPCODE, + &extData[0], + 4); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoverAction, + NULL, + "Failed to write ARM Command"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait up to a maximum of ADI_ADRV9025_TEST_MODE_TIMEOUT_US checking for set opcode status to return */ + recoverAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_SET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_TEST_MODE_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_TEST_MODE_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte & ARM_ERR_CODE) > 0) + { + recoverAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + extData[0], + cmdStatusByte), + recoverAction, + ADI_ADRV9025_ACT_ERR_RESET_CPU); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoverAction; +} + +int32_t adrv9025_CpuSerdesTestModeExit(adi_adrv9025_Device_t* device) +{ + int32_t recoverAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t extData[4] = { 0 }; + uint8_t cmdStatusByte = 0; + + static const uint8_t ARM_ERR_CODE = 0x0E; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API_PRIV); + + /* Arm Test Mode Exit config */ + extData[0] = ADRV9025_CPU_OBJECTID_TM_EXIT; + extData[1] = 0; + + /* Exit Serdes Test Mode */ + recoverAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_TEST_OPCODE, + &extData[0], + 4); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoverAction, + NULL, + "Failed to write ARM Command"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoverAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_TEST_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_TEST_MODE_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_TEST_MODE_INTERVAL_US); + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte & ARM_ERR_CODE) > 0) + { + recoverAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_TEST_OPCODE, + extData[0], + cmdStatusByte), + recoverAction, + ADI_ADRV9025_ACT_ERR_RESET_CPU); + ADI_ERROR_RETURN(device->common.error.newAction); + } + return recoverAction; +} + + +static uint8_t adrv9025_DesCfgHasData(adi_adrv9025_Device_t* device, + adi_adrv9025_DesCfg_t* config) +{ + static const uint32_t ADRV9025_JESD_DESCFG_LANES = 4; + uint8_t i = 0; + uint8_t retVal = 0; + + for (i = 0; i < ADRV9025_JESD_DESCFG_LANES; i++) + { + if ((config[i].configOption1 != 0) || + (config[i].configOption2 != 0) || + (config[i].configOption3 != 0) || + (config[i].configOption4 != 0) || + (config[i].configOption5 != 0) || + (config[i].configOption6 != 0) || + (config[i].configOption7 != 0) || + (config[i].configOption8 != 0) || + (config[i].configOption9 != 0) || + (config[i].configOption10 != 0)) + { + retVal = 1; + break; + } + } + + return retVal; +} + +int32_t adrv9025_JesdDesCfgSet(adi_adrv9025_Device_t *device, + adi_adrv9025_Init_t *init) +{ + static const uint32_t ADRV9025_PROFILE_JESD_DESCFG_OFFSET = 1088; + static const uint32_t ADRV9025_PROFILE_JESD_DESCFG = 44; + static const uint32_t ADRV9025_PROFILE_JESD_DESCFG_LENGTH_BYTES = 4 * 44; + + int32_t recoverAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t cfgData[4*44] = { 0 }; + uint8_t i = 0; + uint8_t hasData = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_DEVICE_PTR_RETURN(init); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API_PRIV); + + hasData = adrv9025_DesCfgHasData(device, init->dataInterface.desCfg); + + if ((init->dataInterface.deframer[0].enableJesd204C == 1) && (hasData == 0)) + { + /* Check Silicon Rev */ + if ((device->devStateInfo.deviceSiRev & 0xB0) == 0xB0) + { + init->dataInterface.desCfg[0].configOption1 = 806223887U; + init->dataInterface.desCfg[0].configOption2 = 51123472U; + init->dataInterface.desCfg[0].configOption3 = 1129575U; + init->dataInterface.desCfg[0].configOption4 = 2690707553U; + init->dataInterface.desCfg[0].configOption5 = 1349654899U; + init->dataInterface.desCfg[0].configOption6 = 386304022U; + init->dataInterface.desCfg[0].configOption7 = 1578626072U; + init->dataInterface.desCfg[0].configOption8 = 4279845916U; + init->dataInterface.desCfg[0].configOption9 = 1209860126U; + init->dataInterface.desCfg[0].configOption10 = 2031636U; + init->dataInterface.desCfg[0].highBoost = 162U; + + init->dataInterface.desCfg[1].configOption1 = 714081178U; + init->dataInterface.desCfg[1].configOption2 = 27525806U; + init->dataInterface.desCfg[1].configOption3 = 817365442U; + init->dataInterface.desCfg[1].configOption4 = 1088291812U; + init->dataInterface.desCfg[1].configOption5 = 82119142U; + init->dataInterface.desCfg[1].configOption6 = 4254142363U; + init->dataInterface.desCfg[1].configOption7 = 421U; + init->dataInterface.desCfg[1].configOption8 = 0U; + init->dataInterface.desCfg[1].configOption9 = 0U; + init->dataInterface.desCfg[1].configOption10 = 0U; + init->dataInterface.desCfg[1].highBoost = 106U; + + init->dataInterface.desCfg[2].configOption1 = 1007919116U; + init->dataInterface.desCfg[2].configOption2 = 4027383838U; + init->dataInterface.desCfg[2].configOption3 = 52404284U; + init->dataInterface.desCfg[2].configOption4 = 4030529862U; + init->dataInterface.desCfg[2].configOption5 = 90966637U; + init->dataInterface.desCfg[2].configOption6 = 7277168U; + init->dataInterface.desCfg[2].configOption7 = 0U; + init->dataInterface.desCfg[2].configOption8 = 0U; + init->dataInterface.desCfg[2].configOption9 = 0U; + init->dataInterface.desCfg[2].configOption10 = 0U; + init->dataInterface.desCfg[2].highBoost = 100U; + + init->dataInterface.desCfg[3].configOption1 = 0U; + init->dataInterface.desCfg[3].configOption2 = 0U; + init->dataInterface.desCfg[3].configOption3 = 0U; + init->dataInterface.desCfg[3].configOption4 = 0U; + init->dataInterface.desCfg[3].configOption5 = 0U; + init->dataInterface.desCfg[3].configOption6 = 0U; + init->dataInterface.desCfg[3].configOption7 = 0U; + init->dataInterface.desCfg[3].configOption8 = 0U; + init->dataInterface.desCfg[3].configOption9 = 0U; + init->dataInterface.desCfg[3].configOption10 = 0U; + init->dataInterface.desCfg[3].highBoost = 0U; + } + else + { + init->dataInterface.desCfg[0].configOption1 = 925455U; + init->dataInterface.desCfg[0].configOption2 = 17563664U; + init->dataInterface.desCfg[0].configOption3 = 34684007U; + init->dataInterface.desCfg[0].configOption4 = 2690707553U; + init->dataInterface.desCfg[0].configOption5 = 1349661043U; + init->dataInterface.desCfg[0].configOption6 = 386322966U; + init->dataInterface.desCfg[0].configOption7 = 1696065816U; + init->dataInterface.desCfg[0].configOption8 = 4279868700U; + init->dataInterface.desCfg[0].configOption9 = 354286110U; + init->dataInterface.desCfg[0].configOption10 = 4280260130U; + init->dataInterface.desCfg[0].highBoost = 162U; + + init->dataInterface.desCfg[1].configOption1 = 1008952340U; + init->dataInterface.desCfg[1].configOption2 = 85324176U; + init->dataInterface.desCfg[1].configOption3 = 1620705444U; + init->dataInterface.desCfg[1].configOption4 = 714149019U; + init->dataInterface.desCfg[1].configOption5 = 10875282U; + init->dataInterface.desCfg[1].configOption6 = 530317990U; + init->dataInterface.desCfg[1].configOption7 = 1672413112U; + init->dataInterface.desCfg[1].configOption8 = 12729298U; + init->dataInterface.desCfg[1].configOption9 = 601034708U; + init->dataInterface.desCfg[1].configOption10 = 417206232U; + init->dataInterface.desCfg[1].highBoost = 162U; + + init->dataInterface.desCfg[2].configOption1 = 98107862U; + init->dataInterface.desCfg[2].configOption2 = 4259447780U; + init->dataInterface.desCfg[2].configOption3 = 0U; + init->dataInterface.desCfg[2].configOption4 = 0U; + init->dataInterface.desCfg[2].configOption5 = 0U; + init->dataInterface.desCfg[2].configOption6 = 0U; + init->dataInterface.desCfg[2].configOption7 = 0U; + init->dataInterface.desCfg[2].configOption8 = 0U; + init->dataInterface.desCfg[2].configOption9 = 0U; + init->dataInterface.desCfg[2].configOption10 = 0U; + init->dataInterface.desCfg[2].highBoost = 34U; + + init->dataInterface.desCfg[3].configOption1 = 1007885845U; + init->dataInterface.desCfg[3].configOption2 = 1344118796U; + init->dataInterface.desCfg[3].configOption3 = 4027383838U; + init->dataInterface.desCfg[3].configOption4 = 52404284U; + init->dataInterface.desCfg[3].configOption5 = 4030529862U; + init->dataInterface.desCfg[3].configOption6 = 90966637U; + init->dataInterface.desCfg[3].configOption7 = 7277168U; + init->dataInterface.desCfg[3].configOption8 = 0U; + init->dataInterface.desCfg[3].configOption9 = 0U; + init->dataInterface.desCfg[3].configOption10 = 0U; + init->dataInterface.desCfg[3].highBoost = 116U; + } + + /* Deserialize desCfg data to cfgData to be transferred to Memory */ + for (i = 0; i < ADI_ADRV9025_NUM_LANES; i++) + { + adrv9025_CpuLoadDesBytes(i * ADRV9025_PROFILE_JESD_DESCFG, + &cfgData[0], + &init->dataInterface.desCfg[i]); + } + + recoverAction = adi_adrv9025_CpuConfigWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_OBJECTID_DEVICE_PROFILE, + ADRV9025_PROFILE_JESD_DESCFG_OFFSET, + &cfgData[0], + ADRV9025_PROFILE_JESD_DESCFG_LENGTH_BYTES); + } + + return recoverAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_crc32.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_crc32.c new file mode 100644 index 0000000..ae2673b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_crc32.c @@ -0,0 +1,150 @@ +/** +* \file adrv9025_crc32.c +* \brief Contains ARM private features related function implementation defined in +* adrv9025_crc32.h +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_error.h" +#include "../devices/adrv9025/private/include/adrv9025_crc32.h" + +static const uint32_t LUT_CRC32[16] = { + 0x00000000u, + 0x04c11db7u, + 0x09823b6eu, + 0x0d4326d9u, + 0x130476dcu, + 0x17c56b6bu, + 0x1a864db2u, + 0x1e475005u, + 0x2608edb8u, + 0x22c9f00fu, + 0x2f8ad6d6u, + 0x2b4bcb61u, + 0x350c9b64u, + 0x31cd86d3u, + 0x3c8ea00au, + 0x384fbdbdu +}; + +/* + * \brief Run Cyclic Redundancy Check on the specified block of memory in chunk. + * + * This function was based on the Crc32 function but can be used on chunk of memory block. + * The function can be call multiple times. + * The first call, set seedCrc to 0, finalCrc to 0. + * The return CRC is use as seedCrc for the next call. + * The last call, set finalCrc to 1. + * + * \details CRC32 algorithm, operating on 8-bit words + * + * Parameters: + * \param buf - array of bytes on which CRC is run + * \param bufLen - length of the input array in bytes + * \param seedCrc - Seed for the next block of memory, use 0 for initial seedCrc. + * \param finalCrc - 0: return the CRC use for seedSrc. 1: return the final CRC32. + * + * \retval 32-bit checksum + */ +uint32_t adrv9025_Crc32ForChunk(const uint8_t buf[], + uint32_t bufLen, + uint32_t seedCrc, + uint8_t finalCrc) +{ + uint32_t i; + uint32_t a, b, c, d; + + a = seedCrc; + + for (i = 0u; i < bufLen; i++) + { + b = (a >> 28u) & 0xfu; + c = LUT_CRC32[b]; + d = buf[i]; + a = (a << 4u) | (d >> 4u); + a = a ^ c; + b = (a >> 28u) & 0xfu; + c = LUT_CRC32[b]; + a = (a << 4u) | (d & 0xfu); + a = a ^ c; + } + + if (finalCrc > 0) + { + for (i = 0u; i < 4u; i++) + { + b = (a >> 28u) & 0xfu; + c = LUT_CRC32[b]; + a = (a << 4u); + a = a ^ c; + b = (a >> 28u) & 0xfu; + c = LUT_CRC32[b]; + a = (a << 4u); + a = a ^ c; + } + } + + return a; +} + +/*! **************************************************************************** +* Function: Crc32 +* +* brief Run Cyclic Redundancy Check on the specified block of memory +* +* details CRC32 algorithm, operating on 8-bit words +* +* Parameters: +* param [in] buf - array of bytes on which CRC is run +* param [in] bufLen - length of the input array in bytes +* +* return 32-bit checksum +* +* Reference to other related functions +* @sa +* +******************************************************************************* +*/ +/* +uint32_t Crc32(const uint8_t buf[], uint32_t bufLen) +{ + uint32_t i; + uint32_t a, b, c, d; + + a = 0x00000000u; + + for (i = 0u; i < bufLen; i++) { + b = (a >> 28u) & 0xfu; + c = LUT_CRC32[b]; + d = buf[i]; + a = (a << 4u) | (d >> 4u); + a = a ^ c; + b = (a >> 28u) & 0xfu; + c = LUT_CRC32[b]; + a = (a << 4u) | (d & 0xfu); + a = a ^ c; + } + + for (i = 0u; i < 4u; i++) { + b = (a >> 28u) & 0xfu; + c = LUT_CRC32[b]; + a = (a << 4u); + a = a ^ c; + b = (a >> 28u) & 0xfu; + c = LUT_CRC32[b]; + a = (a << 4u); + a = a ^ c; + } + + return a; +} +*/ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_data_interface.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_data_interface.c new file mode 100644 index 0000000..ac8b935 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_data_interface.c @@ -0,0 +1,856 @@ +/** +* \file adrv9025_data_interface.c +* \brief Contains private helper functions to assist the ADRV9025 data interface +* API functions. +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_error.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_cpu.h" +#include "../../private/include/adrv9025_data_interface.h" +#include "../../private/include/adrv9025_bf_deser.h" +#include "../../private/include/adrv9025_init.h" +#include "../../private/include/adrv9025_reg_addr_macros.h" +#include "../devices/adrv9025/private/include/adrv9025_cpu.h" +#include "../devices/adrv9025/private/include/adrv9025_cpu_macros.h" + +uint8_t adrv9025_SerializerLamLaneOffsetGet(uint8_t laneAtPackageBall) +{ + uint8_t laneAtDie = 0; + + static const uint8_t framerLaneLamTbl[] = + { + 1u, /* [0] SEROUT A */ + 3u, /* [1] SEROUT B */ + 5u, /* [2] SEROUT C */ + 7u, /* [3] SEROUT D */ + 0u, /* [4] SEROUT E */ + 2u, /* [5] SEROUT F */ + 4u, /* [6] SEROUT G */ + 6u /* [7] SEROUT H */ + }; + + if (laneAtPackageBall <= 7u) + { + laneAtDie = framerLaneLamTbl[laneAtPackageBall]; + } + else + { + laneAtDie = 7u; + } + + return laneAtDie; +} + +uint8_t adrv9025_FramerPadToBallTranslate(uint8_t pad) +{ + uint8_t result = pad; + const uint8_t framerTranslationTable[] = + { + 0u, /*SERDOUTA*/ + 1u, /*SERDOUTB*/ + 2u, /*SERDOUTC*/ + 3u /*SERDOUTD*/ + }; + + if (pad < 4u) + { + result = framerTranslationTable[pad]; + } + + return result; +} + +uint8_t adrv9025_FramerPadToBallMaskTranslate(uint8_t padMask) +{ + uint8_t i = 0u; + uint8_t max = 8u * sizeof(uint8_t); + uint8_t result = 0u; + + for (i = 0u; i < max; ++i) + { + if (padMask & (0x1 << i)) + { + result |= 0x1 << adrv9025_FramerPadToBallTranslate(i); + } + } + return result; +} + +uint8_t adrv9025_DeserializerLamLaneOffsetGet(uint8_t laneAtPackageBall) +{ + uint8_t laneAtDie = 0; + + static const uint8_t deframerLaneLamTbl[] = + { + 7u, /* [0] SEROUT A */ + 5u, /* [1] SEROUT B */ + 3u, /* [2] SEROUT C */ + 1u, /* [3] SEROUT D */ + 6u, /* [4] SEROUT E */ + 4u, /* [5] SEROUT F */ + 2u, /* [6] SEROUT G */ + 0u /* [7] SEROUT H */ + }; + + if (laneAtPackageBall <= 7u) + { + laneAtDie = deframerLaneLamTbl[laneAtPackageBall]; + } + else + { + laneAtDie = 7u; + } + + return laneAtDie; +} + +uint8_t adrv9025_DeframerLamLaneOffsetGet(uint8_t laneAtDie) +{ + uint8_t laneAtPackageBall = 0; + + static const uint8_t deframerInvLaneLamTbl[] = + { + 7u, /* [0] pad_ch0 */ + 3u, /* [1] pad_ch1 */ + 6u, /* [2] pad_ch2 */ + 2u, /* [3] pad_ch3 */ + 5u, /* [4] pad_ch4 */ + 1u, /* [5] pad_ch5 */ + 4u, /* [6] pad_ch6 */ + 0u /* [7] pad_ch7 */ + }; + + /* Return value from table if index is valid, 31(invalid) corresponds to lane select 7*/ + if (laneAtDie <= 7u) + { + laneAtPackageBall = deframerInvLaneLamTbl[laneAtDie]; + } + else if (laneAtDie == 31u) + { + laneAtPackageBall = 7u; + } + else + { + laneAtPackageBall = laneAtDie; + } + + return laneAtPackageBall; +} + +uint8_t adrv9025_DeframerLaneTranslateBitmask(uint8_t inBitMask) +{ + uint8_t i = 0u; + uint8_t outBitMask = 0u; + + static const uint8_t deframerInvLaneLamTbl[] = + { + 7u, /* [0] pad_ch0 */ + 3u, /* [1] pad_ch1 */ + 6u, /* [2] pad_ch2 */ + 2u, /* [3] pad_ch3 */ + 5u, /* [4] pad_ch4 */ + 1u, /* [5] pad_ch5 */ + 4u, /* [6] pad_ch6 */ + 0u /* [7] pad_ch7 */ + }; + + for (i = 0u; i < 8u; i++) + { + if (inBitMask & (1u << i)) + { + outBitMask |= (1u << deframerInvLaneLamTbl[i]); + } + } + + return outBitMask; +} + +int32_t adrv9025_CbusRegisterRead(adi_adrv9025_Device_t* device, + uint8_t addr, + uint8_t rxLaneSel, + uint8_t* data) +{ + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + data); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if ((rxLaneSel & (rxLaneSel - 1)) > 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Only one lane is allowed at a time for readback"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + retVal = adrv9025_DeserCbusAddrDesRcBfSet(device, + ADRV9025_BF_JESD_DESERIALIZER, + addr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to write cbus addr"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_DeserCbusRenDesRcChBfSet(device, + ADRV9025_BF_JESD_DESERIALIZER, + rxLaneSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to write read enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_DeserCbusRdataDesRsBfGet(device, + ADRV9025_BF_JESD_DESERIALIZER, + data); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read cbus rdata"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_DeserCbusRenDesRcChBfSet(device, + ADRV9025_BF_JESD_DESERIALIZER, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to clear read enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adrv9025_CbusRegisterWrite(adi_adrv9025_Device_t* device, + uint8_t addr, + uint8_t rxLaneSel, + uint8_t data) +{ + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if (rxLaneSel > 0x0F) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Invalid lane selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + retVal = adrv9025_DeserCbusAddrDesRcBfSet(device, + ADRV9025_BF_JESD_DESERIALIZER, + addr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to write cbus addr"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_DeserCbusWdataDesRcBfSet(device, + ADRV9025_BF_JESD_DESERIALIZER, + data); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to write cbus wdata"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_DeserCbusWstrobeDesRcChBfSet(device, + ADRV9025_BF_JESD_DESERIALIZER, + rxLaneSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to write cbus wstrobe"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Must reset strobe register on exit */ + retVal = adrv9025_DeserCbusWstrobeDesRcChBfSet(device, + ADRV9025_BF_JESD_DESERIALIZER, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to clear cbus wstrobe"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adrv9025_CbusRegisterSpiRead(adi_adrv9025_Device_t *device, + uint8_t addr, + uint8_t rxLaneSel, + uint8_t* data) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, data); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API_PRIV); + + ADRV9025_SPIWRITEBYTE("CBUS_CONTROL_ADDRESS", ADRV9025_DES_CBUS_CONTROL_ADDRESS, addr); /* Write Cbus control address */ + ADRV9025_SPIWRITEBYTE("CBUS_CONTROL_CHANNEL", ADRV9025_DES_CBUS_CONTROL_CHANNEL, 0x00); /* select channel to read back data from cbus_rdata_ser<7:0>. Active high. <0> = ch0, <1>=ch1. */ + ADRV9025_SPIWRITEBYTE("CBUS_CONTROL_LANE", ADRV9025_DES_CBUS_CONTROL_CHANNEL, rxLaneSel); /* Write down which lane is being selected. */ + + ADRV9025_SPIREADBYTE("CBUS_READBACK_VALUE", ADRV9025_DES_CBUS_DATA_READBACK, data); /* Readback value from bus */ + + ADRV9025_SPIWRITEBYTE("CBUS_PLL_SELECT_ADDRESS", ADRV9025_DES_CBUS_PLL_SELECT, 0x00); /* Select PLL */ + ADRV9025_SPIWRITEBYTE("CBUS_CONTROL_ADDRESS", ADRV9025_DES_CBUS_CONTROL_CHANNEL, 0x00); + + return (device->common.error.newAction); +} + +int32_t adrv9025_CbusRegisterSpiWrite(adi_adrv9025_Device_t *device, + uint8_t addr, + uint8_t rxLaneSel, + uint8_t data) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API_PRIV); + + ADRV9025_SPIWRITEBYTE("CBUS_CONTROL_ADDRESS", ADRV9025_DES_CBUS_CONTROL_ADDRESS, addr); /* Write Cbus control address */ + ADRV9025_SPIWRITEBYTE("CBUS_CONTROL_VALUE", ADRV9025_DES_CBUS_DATA_WRITE, data); /* Write Cbus data */ + ADRV9025_SPIWRITEBYTE("CBUS_CONTROL_LANE", ADRV9025_DES_CBUS_PHY_WSTROBE, rxLaneSel); /* Strobe the cbus lane */ + ADRV9025_SPIWRITEBYTE("CBUS_CONTROL_LANE", ADRV9025_DES_CBUS_PHY_WSTROBE, 0x00); /* Strobe the cbus lane */ + return (device->common.error.newAction); +} + +int32_t adrv9025_SpoSpiSet(adi_adrv9025_Device_t *device, + uint8_t rxLaneSel, + uint8_t data) +{ + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + + static const uint8_t LF_SPO = 0x0D; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API_PRIV); + + /* write to sel_lf_spo_des_rc and CLEAR the latch bit */ + retVal = adrv9025_CbusRegisterSpiWrite(device, + LF_SPO, + rxLaneSel, + (data)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + "Failed to write LF_SPO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write to sel_lf_spo_des_rc and SET the latch bit */ + retVal = adrv9025_CbusRegisterSpiWrite(device, + LF_SPO, + rxLaneSel, + (data | 0x80)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + "Failed to write LF_SPO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write to sel_lf_spo_des_rc and CLEAR the latch bit */ + retVal = adrv9025_CbusRegisterSpiWrite(device, + LF_SPO, + rxLaneSel, + (data)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + "Failed to write LF_SPO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adrv9025_SpoSet(adi_adrv9025_Device_t* device, + uint8_t rxLaneSel, + uint8_t data) +{ + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + + static const uint8_t LF_SPO = 0x0D; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* write to sel_lf_spo_des_rc and CLEAR the latch bit */ + retVal = adrv9025_CbusRegisterWrite(device, + LF_SPO, + rxLaneSel, + (data & 0x7F)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + "Failed to write LF_SPO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write to sel_lf_spo_des_rc and SET the latch bit */ + retVal = adrv9025_CbusRegisterWrite(device, + LF_SPO, + rxLaneSel, + (data | 0x80)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + "Failed to write LF_SPO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write to sel_lf_spo_des_rc and CLEAR the latch bit */ + retVal = adrv9025_CbusRegisterWrite(device, + LF_SPO, + rxLaneSel, + (data & 0x7F)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + "Failed to write LF_SPO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adrv9025_DeserializerLaneEnable(adi_adrv9025_Device_t* device, + uint8_t laneMask, + uint8_t enable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t lanePdVal = 0xFF; /* Initialize to ones because we'll clear the bit only when enable is true */ + uint8_t i = 0; + uint8_t currentLane = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + for (i = 0; i < 4; i++) + { + currentLane = 1 << i; + if ((laneMask & currentLane) > 0) + { + if (enable > 0) + { + lanePdVal &= ~(1 << i); + } + } + } + + /* Note that we are not using a bitfield, since the destination fields are not channelized. */ + ADRV9025_SPIFIELDWRITE(device, + ADRV9025_ADDR_SYSREF_DES_PHY_PD, + lanePdVal, + laneMask, + 0, + "ADRV9025_ADDR_SYSREF_DES_PHY_PD"); + + return recoveryAction; +} + +int32_t adrv9025_VerticalIsiGet(adi_adrv9025_Device_t *device, + uint8_t lane, + uint8_t *data, + adi_adrv9025_VerticalISIConfig_t config) + +{ + int32_t recoverAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t error_threshold = config.error_threshold; + uint8_t start_eyemon_step = config.start_eyemon_step; + uint8_t num_flashes = config.num_flashes; + uint8_t c0_notc1 = config.c0_notc1; + uint8_t search_up_down = config.search_up_down; + uint8_t extData[4] = { 0 }; + uint8_t armData[16] = { 0 }; + uint8_t cmdStatusByte = 0; + uint8_t readBackData[24] = { 0 }; + + static const uint8_t ARM_ERR_CODE = 0x0E; + static const uint32_t N = 0x01F4; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_DEVICE_PTR_RETURN(data); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API_PRIV); + + /* Vertical ISI ARM Command configuration structure */ + armData[0] = (uint8_t)(N & 0x000000FF); + armData[1] = (uint8_t)((N & 0x0000FF00) >> 8); + armData[2] = 0x00; + armData[3] = 0x00; + armData[4] = (uint8_t)(error_threshold & 0x000000FF); + armData[5] = (uint8_t)((error_threshold & 0x0000FF00) >> 8); + armData[6] = (uint8_t)((error_threshold & 0x00FF0000) >> 16); + armData[7] = (uint8_t)((error_threshold & 0xFF000000) >> 24); + armData[8] = start_eyemon_step; + armData[9] = num_flashes; + armData[10] = c0_notc1; + armData[11] = search_up_down; + armData[12] = 0x00; + armData[13] = 0x00; + armData[14] = 0x00; + armData[15] = 0x00; + + /* Arm Serdes Test mode run ISI task command */ + extData[0] = ADRV9025_CPU_OBJECTID_TM_SERDES; + extData[1] = lane; + extData[2] = ADRV9025_CPU_OBJECTID_TM_SERDES_TASK_VERT_ISI; + + /* Enter Serdes test Mode */ + recoverAction = adrv9025_CpuSerdesTestModeEnter(device); + if (recoverAction != ADI_COMMON_ACT_NO_ACTION) + { + adrv9025_CpuSerdesTestModeExit(device); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoverAction, + NULL, + "Failed to enter serdes test mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Send Test mode configuration data to arm */ + recoverAction = adi_adrv9025_CpuMemWrite(device, + ADRV9025_CPU_C_ADDR_MAILBOX_SET, + &armData[0], + 16, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + if (recoverAction != ADI_COMMON_ACT_NO_ACTION) + { + adrv9025_CpuSerdesTestModeExit(device); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoverAction, + NULL, + "Failed to write Arm Data"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoverAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_TEST_OPCODE, + &extData[0], + 4); + if (recoverAction != ADI_COMMON_ACT_NO_ACTION) + { + adrv9025_CpuSerdesTestModeExit(device); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoverAction, + NULL, + "Failed to write ARM Command"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + recoverAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_TEST_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_TEST_MODE_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_TEST_MODE_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte & ARM_ERR_CODE) > 0) + { + recoverAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_TEST_OPCODE, + extData[0], + cmdStatusByte), + recoverAction, + ADI_ADRV9025_ACT_ERR_RESET_CPU); + adrv9025_CpuSerdesTestModeExit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoverAction = adi_adrv9025_CpuMemRead(device, + ADRV9025_CPU_C_ADDR_MAILBOX_SET, + &readBackData[0], + sizeof(readBackData), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + + data[0] = readBackData[4]; /* vertisi_sum_s0f1 */ + data[1] = readBackData[5]; /* vertisi_sum_s1f1 */ + data[2] = readBackData[6]; /* vertisi_diff_s0f1 */ + data[3] = readBackData[7]; /* vertisi_diff_s1f1 */ + + /* Exit Serdes Test mode */ + recoverAction = adrv9025_CpuSerdesTestModeExit(device); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoverAction, + NULL, + "Failed to exit serdes test mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + return recoverAction; +} + +int32_t adrv9025_GenerateEyeDiagram_Direction(adi_adrv9025_Device_t *device, + uint8_t lane, + adi_adrv9025_EyeDiagramResultsQR_t **results, + uint8_t numResults, + uint8_t direction) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + uint8_t loopFilterDLLSlewRegVal = 0; /* Variable to store value of loop filter dll slew register */ + uint8_t enFlashMaskDesRCValOrig = 0; /* */ + uint8_t s0BThresholdb1Val = 0; /* slice 0 threshold b1 value register */ + uint8_t sweepRange = 18; /* how far to sweep along signal phase in a given direction (1/2 a UI plus a margin either side for transition) */ + uint8_t resultPos = 0; + int8_t invertVal = 0; /* depending on direction we need to do a different calculation, this val can be used to change a value negative */ + int phasePosition = 0; /* Loop counter */ + int phaseStart = sweepRange - 1 ; /* Keep track of which position you are at in the array offsetting based on phase i.e. position 15 = phase 0 */ + int phaseCurrent = phasePosition; + int laneSelMask = 0; + + adi_adrv9025_VerticalISIConfig_t configuration = { 0 }; + uint8_t verticalisiData[4] = { 0 }; + + static const uint8_t DLL_SLEW_SETTINGS_REG = 0x08; + static const uint8_t EN_FLASH_MASK_DES_RC_REG = 0xFA; + static const uint8_t S0_B_THRB1_REG = 0xCA; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_DEVICE_PTR_RETURN(results); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API_PRIV); + + if (direction == 1) + { + configuration.c0_notc1 = 1; /* Choose edge comparitor 0 */ + invertVal = 1; + } + else + { + resultPos = 1; + invertVal = -1; + configuration.c0_notc1 = 0; /* Invert edge comparitor to use comparitor 1 */ + } + + configuration.error_threshold = 0x0000; /* Error threshold value */ + configuration.num_flashes = 2; + configuration.search_up_down = 1; + configuration.start_eyemon_step = 0x20; /* Step size */ + + laneSelMask = 1 << lane; /* Calculate lane select mask */ + + /* Read loop filter dll slew value from register */ + recoveryAction = adrv9025_CbusRegisterSpiRead(device, DLL_SLEW_SETTINGS_REG, laneSelMask, &loopFilterDLLSlewRegVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to read Loopfilter DLL Slew Settings Register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read en_flash_mask_des_rc from DFE Control Register */ + recoveryAction = adrv9025_CbusRegisterSpiRead(device, EN_FLASH_MASK_DES_RC_REG, laneSelMask, &enFlashMaskDesRCValOrig); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to read en_flash_mask_des_rc from DFE Control Register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read s0_b_thrb1 from DFE Control Register */ + recoveryAction = adrv9025_CbusRegisterSpiRead(device, S0_B_THRB1_REG, laneSelMask, &s0BThresholdb1Val); + s0BThresholdb1Val &= 0x3f; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to read s0_b_thrb1 from DFE Control Register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_SpoSpiSet(device, laneSelMask, 0x00); /* Clear and setup the SPO */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to write static phase offset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Enable digital counting of flash outputs toward DLL phase accumulator */ + recoveryAction = adrv9025_CbusRegisterSpiWrite(device, EN_FLASH_MASK_DES_RC_REG, laneSelMask, 0xA0 | enFlashMaskDesRCValOrig); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to write updated flash mask des rc value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Slew SPO to negative value */ + for (phasePosition = 127; phasePosition > 127 - sweepRange; phasePosition --) + { + recoveryAction = adrv9025_SpoSpiSet(device, laneSelMask, phasePosition); /* Adjust the SPO */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to write static phase offset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Use ARM to Calculate Vertical ISI at particular phase position */ + adrv9025_VerticalIsiGet(device, lane, &verticalisiData[0], configuration); + results[resultPos][phaseStart].phase = phasePosition; + results[resultPos][phaseStart].b1Threshold = s0BThresholdb1Val; + results[resultPos][phaseStart].eyeStepUp = (s0BThresholdb1Val * invertVal) + verticalisiData[0]; /* s0BThresholdb1Val + vertisi_sum_s0f1 (-b1 or +b1 threshold value) */ + results[resultPos][phaseStart].eyeStepDown = (s0BThresholdb1Val * invertVal) - verticalisiData[1]; /* s0BThresholdb1Val - vertisi_sum_s1f1 (-b1 or +b1 threshold value) */ + phaseStart--; /* decrement phaseStart array position accessor */ + phaseCurrent = phasePosition; + } + + phaseCurrent--; + + // slew phase / spo back to starting point + for (phasePosition = phaseCurrent; phasePosition < 128; phasePosition ++) + { + recoveryAction = adrv9025_SpoSpiSet(device, laneSelMask, phasePosition); /* Adjust the SPO */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to write static phase offset"); + ADI_ERROR_RETURN(device->common.error.newAction); + phaseStart++; /* increment phaseStart array position accessor */ + phaseCurrent = phasePosition; + } + + /* Iterate through all SPO's based negative and positive directions */ + for (phasePosition = 0; phasePosition < sweepRange; phasePosition ++) + { + recoveryAction = adrv9025_SpoSpiSet(device, laneSelMask, phasePosition); /* Adjust the SPO */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to write static phase offset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Use FW Serdes Test mode to calculate eye metrics */ + adrv9025_VerticalIsiGet(device, lane, &verticalisiData[0], configuration); + results[resultPos][phaseStart].phase = phasePosition; + results[resultPos][phaseStart].b1Threshold = s0BThresholdb1Val; + results[resultPos][phaseStart].eyeStepUp = (s0BThresholdb1Val * invertVal) + verticalisiData[0]; /* s0BThresholdb1Val + vertisi_sum_s0f1 (-b1 or +b1 threshold value) */ + results[resultPos][phaseStart].eyeStepDown = (s0BThresholdb1Val * invertVal) - verticalisiData[1]; /* s0BThresholdb1Val - vertisi_sum_s1f1 (-b1 or +b1 threshold value) */ + phaseStart++; /* increment phaseStart array position accessor */ + phaseCurrent = phasePosition; + } + + phaseCurrent++; + + for (phasePosition = phaseCurrent; phasePosition > 0; phasePosition --) + { + recoveryAction = adrv9025_SpoSpiSet(device, laneSelMask, phasePosition); /* Adjust the SPO */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to write static phase offset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + phaseStart--; /* decrement phaseStart array position accessor */ + phaseCurrent = phasePosition; + } + + recoveryAction = adrv9025_SpoSpiSet(device, laneSelMask, 0x00); /* Clear and setup the SPO */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to write static phase offset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* restore original system state of DLL slew settings register */ + recoveryAction = adrv9025_CbusRegisterSpiWrite(device, DLL_SLEW_SETTINGS_REG, laneSelMask, loopFilterDLLSlewRegVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to write original Loopfilter DLL Slew Settings Register value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* restore original system state of flash mask des rc */ + recoveryAction = adrv9025_CbusRegisterSpiWrite(device, EN_FLASH_MASK_DES_RC_REG, laneSelMask, enFlashMaskDesRCValOrig); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to write original flash mask des rc value"); + ADI_ERROR_RETURN(device->common.error.newAction); + return recoveryAction; +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_dynamic_slicer.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_dynamic_slicer.c new file mode 100644 index 0000000..687ae2c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_dynamic_slicer.c @@ -0,0 +1,310 @@ +/** +* \file adrv9025_dynamic_slicer.c +* \brief Contains ADRV9025 dynamic slicer related private function implementation +* defined in adrv9025_dynamic_slicer.h +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "adi_adrv9025_cpu.h" +#include "adi_adrv9025_error.h" +#include "../../private/include/adrv9025_dynamic_slicer.h" +#include "../../private/include/adrv9025_rx.h" +#include "../../private/include/adrv9025_bf_rx.h" +#include "../../private/include/adrv9025_bf_orx.h" + +int32_t adrv9025_RxDynamicSlicerConfigSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxDynamicSlicerConfig_t rxDynamicSlicerConfig[], + uint8_t arraySize) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t dynamicSlicerCfgIndex = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check that dynamic slicer configuration struct array is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + rxDynamicSlicerConfig); + + for (dynamicSlicerCfgIndex = 0; dynamicSlicerCfgIndex < arraySize; dynamicSlicerCfgIndex++) + { + if ((rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSampleResolution != ADI_ADRV9025_INTEGER_12BIT_2SCOMP) && + (rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSampleResolution != ADI_ADRV9025_INTEGER_12BIT_SIGNED) && + (rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSampleResolution != ADI_ADRV9025_INTEGER_16BIT_2SCOMP) && + (rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSampleResolution != ADI_ADRV9025_INTEGER_16BIT_SIGNED) && + (rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSampleResolution != ADI_ADRV9025_INTEGER_24BIT_2SCOMP) && + (rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSampleResolution != ADI_ADRV9025_INTEGER_24BIT_SIGNED)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSampleResolution, + "Invalid integer sample resolution encountered during dynamic slicer config"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (rxDynamicSlicerConfig[dynamicSlicerCfgIndex].dynamicSlicerEnable > 0) + { + if ((rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSampleResolution == ADI_ADRV9025_INTEGER_16BIT_SIGNED) || + (rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSampleResolution == ADI_ADRV9025_INTEGER_12BIT_SIGNED)) + { + if ((rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intEmbeddedBits != ADI_ADRV9025_EMBED_1_SLICERBIT_AT_MSB) && + (rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intEmbeddedBits != ADI_ADRV9025_EMBED_1_SLICERBIT_AT_LSB)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSampleResolution, + "Invalid integer embedded bits config encountered during dynamic slicer config. For dyamic slicer 16/12 bit signed format 1 dynamic slicer bit at (MSB-1)/LSB can be embedded"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else if ((rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSampleResolution == ADI_ADRV9025_INTEGER_16BIT_2SCOMP) || + (rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSampleResolution == ADI_ADRV9025_INTEGER_12BIT_2SCOMP)) + { + if (rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intEmbeddedBits != ADI_ADRV9025_EMBED_1_SLICERBIT_AT_LSB) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSampleResolution, + "Invalid integer embedded bits config encountered during dynamic slicer config. For dyamic slicer 16/12 bit 2s complement format 1 dynamic bit at LSB can be embedded"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Range check the slicer step size */ + if ((rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSlicerStepSize != ADI_ADRV9025_INTSLICER_STEPSIZE_1DB) && + (rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSlicerStepSize != ADI_ADRV9025_INTSLICER_STEPSIZE_2DB) && + (rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSlicerStepSize != ADI_ADRV9025_INTSLICER_STEPSIZE_3DB) && + (rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSlicerStepSize != ADI_ADRV9025_INTSLICER_STEPSIZE_4DB) && + (rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSlicerStepSize != ADI_ADRV9025_INTSLICER_STEPSIZE_6DB) && + (rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSlicerStepSize != ADI_ADRV9025_INTSLICER_STEPSIZE_8DB)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxDynamicSlicerConfig[dynamicSlicerCfgIndex].intSlicerStepSize, + "Invalid slicer step size encountered while attempting to configure the dynamic slicer. Valid step sizes are 1dB,2dB,3dB,4dB,6dB and 8dB"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxDynamicSlicerEnableSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxDynamicSlicerConfig_t* dynamicSlicerCfg, + uint8_t enable) +{ + static const adi_adrv9025_RxChannels_e RX_CHANNEL_ARR[] = {ADI_ADRV9025_RX1, ADI_ADRV9025_RX2, ADI_ADRV9025_RX3, ADI_ADRV9025_RX4}; + static const adi_adrv9025_RxChannels_e ORX_CHANNEL_ARR[] = {ADI_ADRV9025_ORX1, ADI_ADRV9025_ORX2, ADI_ADRV9025_ORX3, ADI_ADRV9025_ORX4}; + static const uint8_t GAIN_COMP_ENABLE = 1; + static const uint8_t DYNAMIC_SLICER_MODE_ENABLE = 1; + static const uint8_t MAX_SLICER_VAL_OVERRIDE_ENABLE = 1; + static const uint8_t GAIN_COMP_DISABLE = 0; + static const uint8_t DYNAMIC_SLICER_MODE_DISABLE = 0; + static const uint8_t MAX_SLICER_VAL_OVERRIDE_DISABLE = 0; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxChannelIndex = 0; + uint8_t intDataResolution = 0; + uint8_t intDataFormat = 0; + uint8_t intEmbedSlicer = 0; + uint8_t intEmbedSlicerPos = 0; + uint8_t intEmbedSlicerNumber = 0; + uint8_t staticSlicer3BitModeEn = 0; + uint8_t dynamicSlicerModeEn = 0; + uint8_t gainCompEn = 0; + uint8_t maxSlicerOverrideEnable = 0; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddress = (adrv9025_BfRxChanAddr_e)0; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddress = (adrv9025_BfOrxChanAddr_e)0; + adi_adrv9025_IntegerConfigSettings_t integerConfigSettings = {ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check that dynamicSlicerCfg struct is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + dynamicSlicerCfg); + + /*Resolve Sample Resolution, int embedded bits and format*/ + integerConfigSettings.intSampleResolution = dynamicSlicerCfg->intSampleResolution; + recoveryAction = adrv9025_RxIntSampleResFormatResolve(device, + &integerConfigSettings, + &intDataResolution, + &intDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (enable > 0) + { + dynamicSlicerModeEn = DYNAMIC_SLICER_MODE_ENABLE; + gainCompEn = GAIN_COMP_ENABLE; + maxSlicerOverrideEnable = MAX_SLICER_VAL_OVERRIDE_ENABLE; + recoveryAction = adrv9025_RxIntEmbSlicerConfigResolve(device, + ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO, + dynamicSlicerCfg->intEmbeddedBits, + &intEmbedSlicer, + &intEmbedSlicerPos, + &intEmbedSlicerNumber, + &staticSlicer3BitModeEn); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + dynamicSlicerModeEn = DYNAMIC_SLICER_MODE_DISABLE; + gainCompEn = GAIN_COMP_DISABLE; + maxSlicerOverrideEnable = MAX_SLICER_VAL_OVERRIDE_DISABLE; + recoveryAction = adrv9025_RxIntEmbSlicerConfigResolve(device, + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED, + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS, + &intEmbedSlicer, + &intEmbedSlicerPos, + &intEmbedSlicerNumber, + &staticSlicer3BitModeEn); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (rxChannelIndex = 0; rxChannelIndex < (sizeof(RX_CHANNEL_ARR) / sizeof(RX_CHANNEL_ARR[0])); rxChannelIndex++) + { + if ((dynamicSlicerCfg->rxChannelMask & RX_CHANNEL_ARR[rxChannelIndex]) != ADI_ADRV9025_RXOFF) + { + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + RX_CHANNEL_ARR[rxChannelIndex], + &rxChannelBitfieldAddress); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxGainCompEnableBfSet(device, + rxChannelBitfieldAddress, + gainCompEn); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxDynamicSlicerModeEnBfSet(device, + rxChannelBitfieldAddress, + dynamicSlicerModeEn); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxDynamicSlicerSyncHeadBfSet(device, + rxChannelBitfieldAddress, + dynamicSlicerCfg->dynamicSlicerSyncHeader); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxDynamicSlicerAgcSyncEnableBfSet(device, + rxChannelBitfieldAddress, + dynamicSlicerCfg->dynamicSlicerAgcSyncEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntDataResolutionBfSet(device, + rxChannelBitfieldAddress, + intDataResolution); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntDataFormatBfSet(device, + rxChannelBitfieldAddress, + intDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntEmbedSlicerNumberBfSet(device, + rxChannelBitfieldAddress, + intEmbedSlicerNumber); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntEmbedSlicerPosBfSet(device, + rxChannelBitfieldAddress, + intEmbedSlicerPos); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxSlicerPinControlStepBfSet(device, + rxChannelBitfieldAddress, + (uint8_t)dynamicSlicerCfg->intSlicerStepSize); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxMaxSlicerOverrideBfSet(device, + rxChannelBitfieldAddress, + maxSlicerOverrideEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + for (rxChannelIndex = 0; rxChannelIndex < (sizeof(ORX_CHANNEL_ARR) / sizeof(ORX_CHANNEL_ARR[0])); rxChannelIndex++) + { + if ((dynamicSlicerCfg->rxChannelMask & ORX_CHANNEL_ARR[rxChannelIndex]) == ORX_CHANNEL_ARR[rxChannelIndex]) + { + recoveryAction = adrv9025_OrxBitfieldAddressGet(device, + ORX_CHANNEL_ARR[rxChannelIndex], + &orxChannelBitfieldAddress); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxGainCompEnableBfSet(device, + orxChannelBitfieldAddress, + gainCompEn); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxDynamicSlicerModeEnBfSet(device, + orxChannelBitfieldAddress, + dynamicSlicerModeEn); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxDynamicSlicerSyncHeadBfSet(device, + orxChannelBitfieldAddress, + dynamicSlicerCfg->dynamicSlicerSyncHeader); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxDynamicSlicerAgcSyncEnableBfSet(device, + orxChannelBitfieldAddress, + dynamicSlicerCfg->dynamicSlicerAgcSyncEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntDataResolutionBfSet(device, + orxChannelBitfieldAddress, + intDataResolution); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntDataFormatBfSet(device, + orxChannelBitfieldAddress, + intDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntEmbedSlicerNumberBfSet(device, + orxChannelBitfieldAddress, + intEmbedSlicerNumber); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntEmbedSlicerPosBfSet(device, + orxChannelBitfieldAddress, + intEmbedSlicerPos); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxSlicerPinControlStepBfSet(device, + orxChannelBitfieldAddress, + (uint8_t)dynamicSlicerCfg->intSlicerStepSize); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxMaxSlicerOverrideBfSet(device, + orxChannelBitfieldAddress, + maxSlicerOverrideEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_gpio.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_gpio.c new file mode 100644 index 0000000..bdf3bff --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_gpio.c @@ -0,0 +1,1145 @@ +#include "adi_adrv9025_user.h" +#include "adi_adrv9025_gpio.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_error.h" +#include "adi_adrv9025.h" +#include "../../private/include/adrv9025_bf_core.h" +#include "../../private/include/adrv9025_gpio.h" +#include "../../private/include/adrv9025_bf_analog_tx_mem_map.h" +#include "../../private/include/adrv9025_bf_pll_mem_map.h" +#include "../../private/include/adrv9025_reg_addr_macros.h" +#include "../../private/include/adrv9025_bf_orx.h" + +#ifdef _RELEASE_BUILD_ +#line __LINE__ "adrv9025_gpio.c" +#endif + +int32_t adrv9025_GpIntHandler(adi_adrv9025_Device_t* device, + adi_adrv9025_gpIntStatus_t* gpIntStatus) +{ + UNUSED_PARA(device); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + const char* errMsg = "No Interrupt Detected"; + static const uint64_t ADI_ADRV9025_GP_MASK_ARM_D_WATCHDOG_TIMEOUT = 0x0010000000000000; /* bit52 */ + static const uint64_t ADI_ADRV9025_GP_MASK_ARM_D_CALIBRATION_ERROR = 0x0008000000000000; /* bit51 */ + static const uint64_t ADI_ADRV9025_GP_MASK_ARM_D_SYSTEM_ERROR = 0x0004000000000000; /* bit50 */ + static const uint64_t ADI_ADRV9025_GP_MASK_DEFRAMER11_IRQ = 0x0002000000000000; /* bit49 */ + static const uint64_t ADI_ADRV9025_GP_MASK_DEFRAMER10_IRQ = 0x0001000000000000; /* bit48 */ + static const uint64_t ADI_ADRV9025_GP_MASK_RF1PLL_UNLOCK = 0x0000800000000000; /* bit47 */ + static const uint64_t ADI_ADRV9025_GP_MASK_RF2PLL_UNLOCK = 0x0000400000000000; /* bit46 */ + static const uint64_t ADI_ADRV9025_GP_MASK_AUXPLL_UNLOCK = 0x0000200000000000; /* bit45 */ + static const uint64_t ADI_ADRV9025_GP_MASK_CLKPLL_UNLOCK = 0x0000100000000000; /* bit44 */ + static const uint64_t ADI_ADRV9025_GP_MASK_RF1PLL_CP_OVR_RANGE = 0x0000080000000000; /* bit43 */ + static const uint64_t ADI_ADRV9025_GP_MASK_RF2PLL_CP_OVR_RANGE = 0x0000040000000000; /* bit42 */ + static const uint64_t ADI_ADRV9025_GP_MASK_AUXPLL_OVR_RANGE = 0x0000020000000000; /* bit41 */ + static const uint64_t ADI_ADRV9025_GP_MASK_CLKPLL_OVR_RANGE = 0x0000010000000000; /* bit40 */ + static const uint64_t ADI_ADRV9025_GP_MASK_SERDES_PLL_UNLOCK = 0x0000008000000000; /* bit39 */ + static const uint64_t ADI_ADRV9025_GP_MASK_DEFRAMER9_IRQ = 0x0000004000000000; /* bit38 */ + static const uint64_t ADI_ADRV9025_GP_MASK_DEFRAMER8_IRQ = 0x0000002000000000; /* bit37 */ + static const uint64_t ADI_ADRV9025_GP_MASK_DEFRAMER7_IRQ = 0x0000001000000000; /* bit36 */ + static const uint64_t ADI_ADRV9025_GP_MASK_DEFRAMER6_IRQ = 0x0000000800000000; /* bit35 */ + static const uint64_t ADI_ADRV9025_GP_MASK_DEFRAMER5_IRQ = 0x0000000400000000; /* bit34 */ + static const uint64_t ADI_ADRV9025_GP_MASK_DEFRAMER4_IRQ = 0x0000000200000000; /* bit33 */ + static const uint64_t ADI_ADRV9025_GP_MASK_DEFRAMER3_IRQ = 0x0000000100000000; /* bit32 */ + static const uint64_t ADI_ADRV9025_GP_MASK_DEFRAMER2_IRQ = 0x0000000080000000; /* bit31 */ + static const uint64_t ADI_ADRV9025_GP_MASK_DEFRAMER1_IRQ = 0x0000000040000000; /* bit30 */ + static const uint64_t ADI_ADRV9025_GP_MASK_DEFRAMER0_IRQ = 0x0000000020000000; /* bit29 */ + static const uint64_t ADI_ADRV9025_GP_MASK_FRAMER8_IRQ = 0x0000000010000000; /* bit28 */ + static const uint64_t ADI_ADRV9025_GP_MASK_FRAMER7_IRQ = 0x0000000008000000; /* bit27 */ + static const uint64_t ADI_ADRV9025_GP_MASK_FRAMER6_IRQ = 0x0000000004000000; /* bit26 */ + static const uint64_t ADI_ADRV9025_GP_MASK_FRAMER5_IRQ = 0x0000000002000000; /* bit25 */ + static const uint64_t ADI_ADRV9025_GP_MASK_FRAMER4_IRQ = 0x0000000001000000; /* bit24 */ + static const uint64_t ADI_ADRV9025_GP_MASK_FRAMER3_IRQ = 0x0000000000800000; /* bit23 */ + static const uint64_t ADI_ADRV9025_GP_MASK_FRAMER2_IRQ = 0x0000000000400000; /* bit22 */ + static const uint64_t ADI_ADRV9025_GP_MASK_FRAMER1_IRQ = 0x0000000000200000; /* bit21 */ + static const uint64_t ADI_ADRV9025_GP_MASK_FRAMER0_IRQ = 0x0000000000100000; /* bit20 */ + static const uint64_t ADI_ADRV9025_GP_MASK_PA_PROTECTION_TX3_ERROR = 0x0000000000080000; /* bit19 */ + static const uint64_t ADI_ADRV9025_GP_MASK_PA_PROTECTION_TX2_ERROR = 0x0000000000040000; /* bit18 */ + static const uint64_t ADI_ADRV9025_GP_MASK_PA_PROTECTION_TX1_ERROR = 0x0000000000020000; /* bit17 */ + static const uint64_t ADI_ADRV9025_GP_MASK_PA_PROTECTION_TX0_ERROR = 0x0000000000010000; /* bit16 */ + static const uint64_t ADI_ADRV9025_GP_MASK_FORCE_INTERRUPT = 0x0000000000008000; /* bit15 */ + static const uint64_t ADI_ADRV9025_GP_MASK_ARM_C_WATCHDOG_TIMEOUT = 0x0000000000004000; /* bit14 */ + static const uint64_t ADI_ADRV9025_GP_MASK_ARM_C_CALIBRATION_ERROR = 0x0000000000002000; /* bit13 */ + static const uint64_t ADI_ADRV9025_GP_MASK_ARM_C_SYSTEM_ERROR = 0x0000000000001000; /* bit12 */ + static const uint64_t ADI_ADRV9025_GP_MASK_ORX1_STREAM_ERROR = 0x0000000000000800; /* bit11 */ + static const uint64_t ADI_ADRV9025_GP_MASK_ORX0_STREAM_ERROR = 0x0000000000000400; /* bit10 */ + static const uint64_t ADI_ADRV9025_GP_MASK_TX3_STREAM_ERROR = 0x0000000000000200; /* bit09 */ + static const uint64_t ADI_ADRV9025_GP_MASK_TX2_STREAM_ERROR = 0x0000000000000100; /* bit08 */ + static const uint64_t ADI_ADRV9025_GP_MASK_TX1_STREAM_ERROR = 0x0000000000000080; /* bit07 */ + static const uint64_t ADI_ADRV9025_GP_MASK_TX0_STREAM_ERROR = 0x0000000000000040; /* bit06 */ + static const uint64_t ADI_ADRV9025_GP_MASK_RX3_STREAM_ERROR = 0x0000000000000020; /* bit05 */ + static const uint64_t ADI_ADRV9025_GP_MASK_RX2_STREAM_ERROR = 0x0000000000000010; /* bit04 */ + static const uint64_t ADI_ADRV9025_GP_MASK_RX1_STREAM_ERROR = 0x0000000000000008; /* bit03 */ + static const uint64_t ADI_ADRV9025_GP_MASK_RX0_STREAM_ERROR = 0x0000000000000004; /* bit02 */ + static const uint64_t ADI_ADRV9025_GP_MASK_CORE_STREAM_ERROR = 0x0000000000000002; /* bit01 */ + static const uint64_t ADI_ADRV9025_GP_MASK_MEMORY_ECC_ERROR = 0x0000000000000001; /* bit00 */ + + /* test for RF1 PLL Unlock 47 */ + if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_RF1PLL_UNLOCK) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_MODULE; + errMsg = "GP Interrupt from source RF1PLL Unlock"; + } + + /* test for RF2 PLL Unlock 46 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_RF2PLL_UNLOCK) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_MODULE; + errMsg = "GP Interrupt from source RF2PLL Unlock"; + } + + /* test for AUX PLL Unlock 45 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_AUXPLL_UNLOCK) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_MODULE; + errMsg = "GP Interrupt from source AUXPLL Unlock"; + } + + /* test for ClK PLL Unlock 44 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_CLKPLL_UNLOCK) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "GP Interrupt from source CLKPLL Unlock"; + } + + /* test for SERDES PLL Unlock 39 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_SERDES_PLL_UNLOCK) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "GP Interrupt from source SERDESPLL Unlock"; + } + + /* test for Deframer11 IRQ 49 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_DEFRAMER11_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Deframer IRQ11 - JESD 204C link 1 CRC error"; + } + + /* test for Deframer10 IRQ 48 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_DEFRAMER10_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Deframer IRQ10 - JESD 204C link 1 sync loss"; + } + + /* test for Deframer9 IRQ 38 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_DEFRAMER9_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Deframer IRQ9 - JESD 204B link 1 QBD Error"; + } + + /* test for Deframer8 IRQ 37 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_DEFRAMER8_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Deframer IRQ8 - JESD Link 1 Sysref at wrong phase"; + } + + /* test for Deframer7 IRQ 36 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_DEFRAMER7_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Deframer IRQ7 - JESD Link 1 phase shift with respect to global LMFC"; + } + + /* test for Deframer6 IRQ 35 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_DEFRAMER6_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Deframer IRQ6 - JESD Link 1 Lane FIFO pointer error"; + } + + /* test for Deframer5 IRQ 34 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_DEFRAMER5_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Deframer IRQ5 - JESD 204C link 0 CRC error"; + } + + /* test for Deframer4 IRQ 33 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_DEFRAMER4_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Deframer IRQ4 - JESD 204C link 1 sync loss"; + } + + /* test for Deframer3 IRQ 32 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_DEFRAMER3_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Deframer IRQ3 - JESD 204B link 1 QBD Error"; + } + + /* test for Deframer2 IRQ 31 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_DEFRAMER2_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Deframer IRQ2 - JESD Link 0 Sysref at wrong phase"; + } + + /* test for Deframer1 IRQ bit 30 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_DEFRAMER1_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Deframer IRQ1 - JESD Link 0 phase shift with respect to global LMFC"; + } + + /* test for Deframer0 IRQ bit 29 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_DEFRAMER0_IRQ) > 0) + { + recoveryAction = ADI_COMMON_ACT_WARN_RESET_LOG; + errMsg = "GP Interrupt from source Deframer IRQ0 - JESD Link 0 Lane FIFO pointer error"; + } + + /* test for framer8 IRQ bit 28 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_FRAMER8_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Framer IRQ8 - LMFC phase error Link2"; + } + + /* test for framer7 IRQ bit 27 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_FRAMER7_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Framer IRQ7 - Sysref at wrong phase Link2"; + } + + /* test for framer6 IRQ bit 26 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_FRAMER6_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Framer IRQ6 - Lane FIFO pointer error Link2"; + } + + /* test for framer5 IRQ bit 25 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_FRAMER5_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Framer IRQ5 - LMFC phase error Link1"; + } + + /* test for framer4 IRQ bit 24 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_FRAMER4_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Framer IRQ4 - Sysref at wrong phase Link1"; + } + + /* test for framer3 IRQ bit 23 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_FRAMER3_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Framer IRQ3 - Lane FIFO pointer error Link1"; + } + + /* test for framer2 IRQ bit 22 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_FRAMER2_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Framer IRQ2 - LMFC phase error Link0"; + } + + /* test for framer1 IRQ bit 21 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_FRAMER1_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Framer IRQ1 - Sysref at wrong phase Link0"; + } + + /* test for framer0 IRQ bit 20 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_FRAMER0_IRQ) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source Framer IRQ0 - Lane FIFO pointer error Link0"; + } + + /* test for ORX1 Stream Error bit 11 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_ORX1_STREAM_ERROR) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "GP Interrupt from source ORX1 Stream Error"; + } + + /* test for ORX0 Stream Error bit 10 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_ORX0_STREAM_ERROR) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "GP Interrupt from source ORX0 Stream Error"; + } + + /* test for TX3 Stream Error bit 9 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_TX3_STREAM_ERROR) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "GP Interrupt from source TX3 Stream Error"; + } + + /* test for TX2 Stream Error bit 8 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_TX2_STREAM_ERROR) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "GP Interrupt from source TX2 Stream Error"; + } + + /* test for TX1 Stream Error bit 7 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_TX1_STREAM_ERROR) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "GP Interrupt from source TX1 Stream Error"; + } + + /* test for TX0 Stream Error bit 6 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_TX0_STREAM_ERROR) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "GP Interrupt from source TX0 Stream Error"; + } + + /* test for RX3 Stream Error bit 5 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_RX3_STREAM_ERROR) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "GP Interrupt from source RX3 Stream Error"; + } + + /* test for RX2 Stream Error bit 4 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_RX2_STREAM_ERROR) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "GP Interrupt from source RX2 Stream Error"; + } + + /* test for RX1 Stream Error bit 3 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_RX1_STREAM_ERROR) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "GP Interrupt from source RX1 Stream Error"; + } + + /* test for RX0 Stream Error bit 2 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_RX0_STREAM_ERROR) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "GP Interrupt from source RX0 Stream Error"; + } + + /* test for CORE Stream Error bit 1 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_CORE_STREAM_ERROR) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "GP Interrupt from source CORE Stream Error"; + } + + /* test for PA Protection TX3 bit 19 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_PA_PROTECTION_TX3_ERROR) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source PA Protection TX3 Error"; + } + + /* test for PA Protection TX2 bit 18 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_PA_PROTECTION_TX2_ERROR) > 0) + { + recoveryAction = ADI_COMMON_ACT_WARN_RESET_LOG; + errMsg = "GP Interrupt from source PA Protection TX2 Error"; + } + + /* test for PA Protection TX1 bit 17 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_PA_PROTECTION_TX1_ERROR) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source PA Protection TX1 Error"; + } + + /* test for PA Protection TX0 bit 16 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_PA_PROTECTION_TX0_ERROR) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source PA Protection TX0 Error"; + } + + /* test for Forced IRQ bit 15 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_FORCE_INTERRUPT) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "GP Interrupt from source Forced IRQ"; + } + + /* test for ARM-C Watchdog Timeout bit 14 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_ARM_C_WATCHDOG_TIMEOUT) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "GP Interrupt from source ARM-C WatchDog Time Out"; + } + + /* test for ARM-C Calibration Error bit 13 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_ARM_C_CALIBRATION_ERROR) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_WARN_CHECK_TX_DATA; + errMsg = "GP Interrupt from source SRL violation"; + } + + /* test for ARM-C System Error bit 12 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_ARM_C_SYSTEM_ERROR) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source ARM-C System Error"; + } + + /* test for ARM-D Watchdog Timeout bit 52 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_ARM_D_WATCHDOG_TIMEOUT) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "GP Interrupt from source ARM-D WatchDog Time Out"; + } + + /* test for ARM-D Calibration Error bit 51 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_ARM_D_CALIBRATION_ERROR) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_WARN_RERUN_TRCK_CAL; + errMsg = "GP Interrupt from source ARM-D Calibration Error"; + } + + /* test for ARM-D System Error bit 50 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_ARM_D_SYSTEM_ERROR) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source ARM-D System Error"; + } + + /* test for RF1 PLL OverRange 43 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_RF1PLL_CP_OVR_RANGE) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source RF1PLL OverRange"; + } + + /* test for RF2 PLL OverRange 42 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_RF2PLL_CP_OVR_RANGE) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source RF2PLL OverRange"; + } + + /* test for AUX PLL OverRange 41 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_AUXPLL_OVR_RANGE) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source AUXPLL OverRange"; + } + + /* test for CLK PLL OverRange 40 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_CLKPLL_OVR_RANGE) > 0) + { + recoveryAction = ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR; + errMsg = "GP Interrupt from source CLKPLL OverRange"; + } + + /* test for Memory ECC Error 0 */ + else if ((gpIntStatus->gp_Int_Active_Sources & ADI_ADRV9025_GP_MASK_MEMORY_ECC_ERROR) > 0) + { + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + errMsg = "Memory ECC Error"; + } + + gpIntStatus->gp_Int_Recovery_Action = recoveryAction; + gpIntStatus->gp_Int_Error_Message = errMsg; + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_AuxDacCfgRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxDacCfg_t* auxDacCfg) +{ + static const uint32_t ALL_AUXDAC_MASK = (uint32_t)ADI_ADRV9025_AUXDAC0 | (uint32_t)ADI_ADRV9025_AUXDAC1 | + (uint32_t)ADI_ADRV9025_AUXDAC2 | (uint32_t)ADI_ADRV9025_AUXDAC3 | + (uint32_t)ADI_ADRV9025_AUXDAC4 | (uint32_t)ADI_ADRV9025_AUXDAC5 | + (uint32_t)ADI_ADRV9025_AUXDAC6 | (uint32_t)ADI_ADRV9025_AUXDAC7; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + auxDacCfg); + + /*Check that the requested AuxDAC is valid*/ + if (((auxDacCfg->auxDacMask & (~ALL_AUXDAC_MASK)) != 0) || auxDacCfg->auxDacMask == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + auxDacMask, + "Invalid AuxDAC index is selected for AuxDAC. Valid values are between 1-255."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_AuxDacCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxDacs_e auxDacSel) +{ + static const uint8_t AUXDAC_DEFAULT_MODE = 0x01; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr = ADRV9025_BF_ANALOG_TX_CH1; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + if (((uint8_t)auxDacSel & 0x0F) == 0) + { + auxDacSel = (adi_adrv9025_AuxDacs_e)(((uint8_t)auxDacSel & 0xF0) >> 4); + baseAddr = ADRV9025_BF_ANALOG_TX_CH2; + } + + if (ADRV9025_BF_EQUAL(auxDacSel, + ADI_ADRV9025_AUXDAC0)) + { + recoveryAction = adrv9025_AnalogTxMemMapAuxdac0ConfigBfSet(device, + baseAddr, + AUXDAC_DEFAULT_MODE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (ADRV9025_BF_EQUAL(auxDacSel, + ADI_ADRV9025_AUXDAC1)) + { + recoveryAction = adrv9025_AnalogTxMemMapAuxdac1ConfigBfSet(device, + baseAddr, + AUXDAC_DEFAULT_MODE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (ADRV9025_BF_EQUAL(auxDacSel, + ADI_ADRV9025_AUXDAC2)) + { + recoveryAction = adrv9025_AnalogTxMemMapAuxdac2ConfigBfSet(device, + baseAddr, + AUXDAC_DEFAULT_MODE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_AnalogTxMemMapAuxdac3ConfigBfSet(device, + baseAddr, + AUXDAC_DEFAULT_MODE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_AuxDacValueSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxDacs_e auxDacSel, + uint16_t dacWord) +{ + static const uint16_t MAX_DAC_WORD = 4095; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfAnalogTxMemMapChanAddr_e baseAddr = ADRV9025_BF_ANALOG_TX_CH1; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + if (dacWord > MAX_DAC_WORD) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + dacWord, + "Requested analog voltage is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint8_t)auxDacSel & 0x0F) == 0) + { + auxDacSel = (adi_adrv9025_AuxDacs_e)(((uint8_t)auxDacSel & 0xF0) >> 4); + baseAddr = ADRV9025_BF_ANALOG_TX_CH2; + } + + if (ADRV9025_BF_EQUAL(auxDacSel, + ADI_ADRV9025_AUXDAC0)) + { + recoveryAction = adrv9025_AnalogTxMemMapAuxdac0BfSet(device, + baseAddr, + dacWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (ADRV9025_BF_EQUAL(auxDacSel, + ADI_ADRV9025_AUXDAC1)) + { + recoveryAction = adrv9025_AnalogTxMemMapAuxdac1BfSet(device, + baseAddr, + dacWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (ADRV9025_BF_EQUAL(auxDacSel, + ADI_ADRV9025_AUXDAC2)) + { + recoveryAction = adrv9025_AnalogTxMemMapAuxdac2BfSet(device, + baseAddr, + dacWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_AnalogTxMemMapAuxdac3BfSet(device, + baseAddr, + dacWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_AnalogTxMemMapAuxdacLatchEnBfSet(device, + baseAddr, + 0x01); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while setting latch enable bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_AnalogTxMemMapAuxdacLatchEnBfSet(device, + baseAddr, + 0x00); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while clearing latch enable bit"); + + return device->common.error.newAction; +} + +int32_t adrv9025_AuxAdcCfgRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcCfg_t* auxAdcConfig) +{ + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + auxAdcConfig); + + /* Range check the enable */ + if ((auxAdcConfig->auxAdcEnable < ADI_ADRV9025_AUXADC_DISABLE) || + (auxAdcConfig->auxAdcEnable >= ADI_ADRV9025_AUXADC_ENABLE_NUM)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + auxAdcConfig->auxAdcEnable, + "auxAdcEnable is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Range check the ADC selection */ + if ((auxAdcConfig->auxAdcSelect < ADI_ADRV9025_AUXADC_A) || + (auxAdcConfig->auxAdcSelect >= ADI_ADRV9025_AUXADC_NUM)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + auxAdcConfig->auxAdcSelect, + "auxAdcSelect is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Range check ADC input selection */ + if ((auxAdcConfig->auxAdcInputSelect != ADI_ADRV9025_AUXADC_INPUT_0) && + (auxAdcConfig->auxAdcInputSelect != ADI_ADRV9025_AUXADC_INPUT_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + auxAdcConfig->auxAdcInputSelect, + "auxAdcInputSelect is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Range check the clock divide setting */ + if ((auxAdcConfig->auxAdcClkDivide < ADI_ADRV9025_AUXADC_CLKDIVIDE_32) || + (auxAdcConfig->auxAdcClkDivide >= ADI_ADRV9025_AUXADC_CLKDIVIDE_NUM_DIVIDE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + auxAdcConfig->auxAdcClkDivide, + "auxAdcClkDivide is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adrv9025_AuxAdcCfgRead(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcSelect_e auxAdcSelect, + adi_adrv9025_AuxAdcCfg_t* auxAdcConfig) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfOrxChanAddr_e baseAddr = ADRV9025_BF_ORX_CH0; + uint8_t readValue = 0; /* bit field read back */ + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + auxAdcConfig); + + switch (auxAdcSelect) + { + case ADI_ADRV9025_AUXADC_A: + baseAddr = ADRV9025_BF_ORX_CH0; + break; + case ADI_ADRV9025_AUXADC_B: + baseAddr = ADRV9025_BF_ORX_CH1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + auxAdcSelect, + "auxAdcSelect is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + /* update configuration structure with the selected ADC */ + auxAdcConfig->auxAdcSelect = auxAdcSelect; + + /* read the aux ADC input selection */ + recoveryAction = adrv9025_OrxAuxAdcSelBfGet(device, + baseAddr, + &readValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read aux ADC input selection control register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((readValue != ADI_ADRV9025_AUXADC_INPUT_0) && + (readValue != ADI_ADRV9025_AUXADC_INPUT_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + readValue, + "Read back invalid or default aux ADC input selection."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + auxAdcConfig->auxAdcInputSelect = (adi_adrv9025_AuxAdcInputSelect_e)readValue; + } + + /* update enable flag based only on the power down bit */ + recoveryAction = adrv9025_OrxAuxAdcPdBfGet(device, + baseAddr, + &readValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read aux ADC power down control register"); + ADI_ERROR_RETURN(device->common.error.newAction); + auxAdcConfig->auxAdcEnable = (adi_adrv9025_AuxAdcEnable_e)(readValue == 0x1) + ? ADI_ADRV9025_AUXADC_DISABLE + : ADI_ADRV9025_AUXADC_ENABLE; + + switch (auxAdcSelect) + { + case ADI_ADRV9025_AUXADC_A: + recoveryAction = adrv9025_CoreAuxAdcClkDivide1BfGet(device, + ADRV9025_BF_CORE, + &readValue); + break; + case ADI_ADRV9025_AUXADC_B: + recoveryAction = adrv9025_CoreAuxAdcClkDivide2BfGet(device, + ADRV9025_BF_CORE, + &readValue); + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + auxAdcSelect, + "auxAdcSelect is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read aux ADC clk divide register"); + ADI_ERROR_RETURN(device->common.error.newAction); + auxAdcConfig->auxAdcClkDivide = (adi_adrv9025_AuxAdcClkDivide_e)readValue; + + return device->common.error.newAction; +} + +int32_t adrv9025_AuxAdcCfgWrite(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcCfg_t* auxAdcConfig) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + /* bit field write variable */ + uint8_t powerDownValue = 0x0; + adrv9025_BfOrxChanAddr_e baseAddr = ADRV9025_BF_ORX_CH0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + auxAdcConfig); + + /* auxAdcSelect is already range checked prior to calling this function */ + baseAddr = (auxAdcConfig->auxAdcSelect == ADI_ADRV9025_AUXADC_A) + ? ADRV9025_BF_ORX_CH0 + : ADRV9025_BF_ORX_CH1; + + /* hold ADC in reset while it's being configured */ + recoveryAction = adrv9025_OrxAuxAdcResetBfSet(device, + baseAddr, + 0x1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to write aux ADC reset register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure the ADC input */ + recoveryAction = adrv9025_OrxAuxAdcSelBfSet(device, + baseAddr, + auxAdcConfig->auxAdcInputSelect); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + auxAdcConfig->auxAdcInputSelect, + "Error while attempting to write aux ADC input register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* set the decimation rate. Only one mode is available to the user which is + * mode zero as it's the most accurate */ + recoveryAction = adrv9025_OrxAuxAdcDecimationCtlBfSet(device, + baseAddr, + 0x0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to write aux ADC decimation register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure clock power down */ + powerDownValue = (auxAdcConfig->auxAdcEnable == ADI_ADRV9025_AUXADC_ENABLE) + ? 0x0 + : 0x1; + + if (auxAdcConfig->auxAdcSelect == ADI_ADRV9025_AUXADC_A) + { + /* configure clock divide */ + recoveryAction = adrv9025_CoreAuxAdcClkDivide1BfSet(device, + ADRV9025_BF_CORE, + auxAdcConfig->auxAdcClkDivide); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + auxAdcConfig->auxAdcClkDivide, + "Error while attempting to write aux ADC A clk divide register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreAuxAdcClkPd1BfSet(device, + ADRV9025_BF_CORE, + powerDownValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + auxAdcConfig->auxAdcEnable, + "Error while attempting to write aux ADC A clk power down register"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* configure clock divide */ + recoveryAction = adrv9025_CoreAuxAdcClkDivide2BfSet(device, + ADRV9025_BF_CORE, + auxAdcConfig->auxAdcClkDivide); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + auxAdcConfig->auxAdcClkDivide, + "Error while attempting to write aux ADC B clk divide register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure clock power down */ + recoveryAction = adrv9025_CoreAuxAdcClkPd2BfSet(device, + ADRV9025_BF_CORE, + powerDownValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + auxAdcConfig->auxAdcEnable, + "Error while attempting to write aux ADC B clk power down register"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* set the aux ADC's reset bit based on the value of the supplied enable */ + recoveryAction = adrv9025_OrxAuxAdcResetBfSet(device, + baseAddr, + powerDownValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + auxAdcConfig->auxAdcEnable, + "Error while attempting to write aux ADC reset register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* set the aux ADC's power down bit based on the value of the supplied enable */ + recoveryAction = adrv9025_OrxAuxAdcPdBfSet(device, + baseAddr, + powerDownValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + auxAdcConfig->auxAdcEnable, + "Error while attempting to write aux ADC power down register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adrv9025_AuxAdcMeasurementStart(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcSelect_e auxAdcSelect) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + adrv9025_BfOrxChanAddr_e baseAddr = ADRV9025_BF_ORX_CH1; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + if (auxAdcSelect == ADI_ADRV9025_AUXADC_A) + { + baseAddr = ADRV9025_BF_ORX_CH0; + } + else + { + baseAddr = ADRV9025_BF_ORX_CH1; + } + + /* toggle the reset bit */ + recoveryAction = adrv9025_OrxAuxAdcResetBfSet(device, + baseAddr, + 0x1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to write aux ADC reset register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxAuxAdcResetBfSet(device, + baseAddr, + 0x0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to write aux ADC reset register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adrv9025_AuxAdcValueGet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcSelect_e auxAdcSelect, + adi_adrv9025_AuxAdcValue_t* auxAdcValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint16_t readValue = 0u; + uint8_t readyValue = 0u; + /* auxAdcSelect is already range checked prior to calling this function */ + adrv9025_BfOrxChanAddr_e baseAddr = ADRV9025_BF_ORX_CH1; + adrv9025_BfPllMemMapChanAddr_e pllBaseAddr = ADRV9025_BF_RF2_PLL; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + auxAdcValue); + + if (auxAdcSelect == ADI_ADRV9025_AUXADC_A) + { + baseAddr = ADRV9025_BF_ORX_CH0; + pllBaseAddr = ADRV9025_BF_RF1_PLL; + } + else + { + baseAddr = ADRV9025_BF_ORX_CH1; + pllBaseAddr = ADRV9025_BF_RF2_PLL; + } + + /* Clear the readback lock */ + recoveryAction = adrv9025_OrxAuxAdcReadbackLockBfSet(device, + baseAddr, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to write aux adc readback lock register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Check the ready bit */ + recoveryAction = adrv9025_PllMemMapAuxAdcReadyBfGet(device, + pllBaseAddr, + &readyValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read aux ADC ready register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (readyValue == 0u) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_WARN_RERUN_FEATURE, + readyValue, + "Aux adc is not ready"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* lock the readback lock */ + recoveryAction = adrv9025_OrxAuxAdcReadbackLockBfSet(device, + baseAddr, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to write aux adc readback lock register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read the ADC's sample data */ + recoveryAction = adrv9025_OrxAuxAdcReadBfGet(device, + baseAddr, + &readValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read aux ADC sample registers"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* populate the supplied auxAdcValue structure */ + auxAdcValue->auxAdcSelect = auxAdcSelect; + auxAdcValue->auxAdcValue = readValue; + + return device->common.error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_init.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_init.c new file mode 100644 index 0000000..d84fa28 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_init.c @@ -0,0 +1,1745 @@ +/** + * \file adrv9025_init.c + * \brief Contains ADRV9025 init related private function implementations + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "adi_adrv9025.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_error.h" +#include "../devices/adrv9025/private/include/adrv9025_init.h" +#include "../devices/adrv9025/private/include/adrv9025_rx.h" +#include "../devices/adrv9025/private/include/adrv9025_reg_addr_macros.h" +#include "../devices/adrv9025/private/include/adrv9025_cpu_macros.h" + +#line __LINE__ "adrv9025_init.c" + +int32_t adrv9025_LdoEnable(adi_adrv9025_Device_t* device, + uint8_t ldoSelect) +{ + static const uint8_t NONBYPASS_DEVCLK_LDO = 0x04; + static const uint8_t BYPASS_DEVCLK_LDO = 0x84; + static const uint8_t BYPASS_DEVCLK_LDO_VOUT_TRIM = 0x00; + static const uint8_t NONBYPASS_GP_LDO_1P0V_OUT = 0x04; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* If LDO Select = 1, set LDO's to BYPASS */ + if (ldoSelect == 1) + { + ADRV9025_SPIWRITEBYTE("DEV_CLK_LDO_BYTE1", + ADRV9025_ADDR_DEV_CLK_LDO_BYTE1, + BYPASS_DEVCLK_LDO); + + /* write the LDO Vout Trim to allow a lower reference voltage to the amp */ + ADRV9025_SPIWRITEBYTE("DEV_CLK_LDO_BYTE2", + ADRV9025_ADDR_DEV_CLK_LDO_BYTE2, + BYPASS_DEVCLK_LDO_VOUT_TRIM); + + /* Enable GP_LDO_BYTE1N (non bypass) */ + ADRV9025_SPIWRITEBYTE("GP_LDO_BYTE1N", + ADRV9025_ADDR_GP_LDO_BYTE1N, + NONBYPASS_GP_LDO_1P0V_OUT); + ADRV9025_SPIWRITEBYTE("GP_LDO_BYTE1N+1", + (ADRV9025_ADDR_GP_LDO_BYTE1N + 1), + NONBYPASS_GP_LDO_1P0V_OUT); + + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (ldoSelect == 0) /* If LDO Select = 0, set LDO's to NON-BYPASS */ + { + ADRV9025_SPIWRITEBYTE("DEV_CLK_LDO_BYTE1", + ADRV9025_ADDR_DEV_CLK_LDO_BYTE1, + NONBYPASS_DEVCLK_LDO); + + /* Set GP_LDO_BYTE1N non-bypass */ + ADRV9025_SPIWRITEBYTE("GP_LDO_BYTE1N", + ADRV9025_ADDR_GP_LDO_BYTE1N, + NONBYPASS_GP_LDO_1P0V_OUT); + ADRV9025_SPIWRITEBYTE("GP_LDO_BYTE1N+1", + (ADRV9025_ADDR_GP_LDO_BYTE1N + 1), + NONBYPASS_GP_LDO_1P0V_OUT); + + /* Allow time for internal LDOs to power up */ + + + ADI_ERROR_RETURN(device->common.error.newAction); + + } + else /* Report Error if LDO Select is not either 0 or 1 */ + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid LDO Configuration Specified"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adi_common_hal_Wait_ms(&device->common, 200); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + return (recoveryAction); + } + + return (device->common.error.newAction); +} + +uint32_t adrv9025_ClockDiv(uint32_t clock, + uint32_t clock_max) +{ + uint32_t div = 0; + static const uint32_t ADRV9025_POWER2_MAX = 8; + + for (div = 0; div < ADRV9025_POWER2_MAX; div++) + { + if (clock <= (clock_max << div)) + { + return div; + } + } + + return div; +} + +/* +* Configure the pad DEV_CLK divider so that output of pad divider is less than 500MHz. +* Configure ARM_clk_divide_ratio and reg_clk_divide_ratio (register bus clock). Maximum rate for ARM clock and REGBUS clock is 500MHz. Use DEVCLK to clock the HSDIGCLK input bypassing the PLL (write clock_config_6[7] to 1) +* The clock_config_6 register needs to be written to configure the clock divide ratios indicated +* Write SPI bit "digital_clock_power_up" to enable digital clocks (core.clock_control_6[4]) +*/ +int32_t adrv9025_ClocksSet(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init) +{ + adi_adrv9025_ClockSettings_t* clocks; + uint32_t digDeviceClockDiv = 0; + uint32_t refDeviceClockDiv = 0; + uint32_t regDeviceClockDiv = 0; + uint32_t armDeviceClockDiv = 0; + uint32_t agcDeviceClockDiv = 0; + uint32_t txAttenDeviceClockDiv = 0; + uint32_t digRefClock_MHz = 0; + uint8_t deviceClkControl1 = 0; + uint8_t clockControl7 = 0; + uint8_t clockControl0 = 0; + uint8_t clockConfig0 = 0; + uint8_t clockConfig6 = 0; + uint8_t txClockControl0 = 0; + uint8_t txClockControl2 = 0; + uint8_t txClockControl3 = 0; + uint8_t i = 0; + uint8_t armCtl1 = 0; + uint32_t refClockDiv = 0; + uint8_t refClkByte0 = 0; + + static const uint32_t DEV_CLOCK_MAX = 310000; + static const uint32_t REF_CLOCK_MAX = 250000; + static const uint32_t DIG_CLOCK_MAX = 500000; + static const uint32_t PFIR_MIN_CLOCK_RATE = 0x03; + static const uint32_t DIGDEVICECLOCKDIVMAX = 3; + static const uint32_t REFDEVICECLOCKDIVMAX = 7; + static const uint32_t REFCLOCKDIVMAX = 1; + static const uint32_t REGDEVICECLOCKDIVMAX = 3; + + static const uint32_t ADRV9025_ADDR_CH_RX_SIZE = 6; + static const uint32_t ADRV9025_ADDR_CH_TX_SIZE = 4; + static const uint8_t TXATTEN_CLK_ENABLE = 1; + + static const uint16_t ADRV9025_ADDR_CH_RX_BASE[6] = + { + ADRV9025_ADDR_CH0_RX, + ADRV9025_ADDR_CH1_RX, + ADRV9025_ADDR_CH2_RX, + ADRV9025_ADDR_CH3_RX, + ADRV9025_ADDR_CH0_ORX, + ADRV9025_ADDR_CH1_ORX + }; + + static const uint16_t ADRV9025_ADDR_CH_TX_BASE[4] = + {ADRV9025_ADDR_CH0_TX, ADRV9025_ADDR_CH1_TX, ADRV9025_ADDR_CH2_TX, ADRV9025_ADDR_CH3_TX}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + init); + + ADRV9025_BUGINFO(__FUNCTION__); + + clocks = &init->clocks; + + /* Set Digital device clock divider */ + digDeviceClockDiv = adrv9025_ClockDiv(clocks->deviceClock_kHz, + DEV_CLOCK_MAX); + if (digDeviceClockDiv > DIGDEVICECLOCKDIVMAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid clocks deviceClock_kHz"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Set Digital Ref device clock divider */ + refDeviceClockDiv = adrv9025_ClockDiv(clocks->deviceClock_kHz, + REF_CLOCK_MAX); + if (refDeviceClockDiv > REFDEVICECLOCKDIVMAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid clocks deviceClock_kHz"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + digRefClock_MHz = (((clocks->deviceClock_kHz / 1000) >> digDeviceClockDiv) >> refDeviceClockDiv); + + /* Set Digital Reg device clock divider */ + regDeviceClockDiv = adrv9025_ClockDiv(device->devStateInfo.hsDigClk_kHz, + DIG_CLOCK_MAX); + if (regDeviceClockDiv > REGDEVICECLOCKDIVMAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid clocks hsDigClk_kHz"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + armDeviceClockDiv = regDeviceClockDiv; + agcDeviceClockDiv = regDeviceClockDiv; + txAttenDeviceClockDiv = regDeviceClockDiv; + + /* Set Ref clock divider */ + refClockDiv = adrv9025_ClockDiv((clocks->deviceClock_kHz >> digDeviceClockDiv), + DEV_CLOCK_MAX); + if (refClockDiv > REFCLOCKDIVMAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid clocks deviceClock_kHz"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Set Device clock divider ratio */ + deviceClkControl1 = 0; + deviceClkControl1 = ADRV9025_BF_ENCODE(digDeviceClockDiv, + ADRV9025_DCC1_DEVICE_CLK_DIVIDE_RATIO_MASK, + ADRV9025_DCC1_DEVICE_CLK_DIVIDE_RATIO_SHIFT); + deviceClkControl1 |= ADRV9025_DCC1_DEVICE_CLK_BUFFER_ENABLE; + deviceClkControl1 |= ADRV9025_DCC1_RESETB_TFLASH; + deviceClkControl1 |= ADRV9025_DCC1_DEVCLK_DIVIDER_MCS_RESETB; + ADRV9025_SPIWRITEBYTE("DEVICE_CLK_CONTROL_1", + ADRV9025_ADDR_DEVICE_CLK_CONTROL_1, + deviceClkControl1); + + /* core.clock_control_6 use_device_clk_as_hsdigclk 1 */ + clockControl7 = 0; + clockControl7 |= ADRV9025_CC7_USE_DEVICE_CLK_AS_HSDIGCLK; + ADRV9025_SPIWRITEBYTE("CLOCK_CONTROL_7", + ADRV9025_ADDR_CLOCK_CONTROL_7, + clockControl7); + + /* core.clock_control_0 arm_clk_divide_ratio 0 ; same as hsdigclk */ + clockControl0 = 0; + clockControl0 |= ADRV9025_BF_ENCODE(armDeviceClockDiv, + ADRV9025_CC0_CPU_CLK_DIVIDE_RATIO_MASK, + ADRV9025_CC0_CPU_CLK_DIVIDE_RATIO_SHIFT); + /* SIM +coreArmClkEnable*/ + clockControl0 |= ADRV9025_CC0_CPU_CLK_ENABLE; + /* core.clock_control_0 reg_clk_divide_ratio 0 ; same as hsdigclk */ + clockControl0 |= ADRV9025_BF_ENCODE(regDeviceClockDiv, + ADRV9025_CC0_REG_CLK_DIVIDE_RATIO_MASK, + ADRV9025_CC0_REG_CLK_DIVIDE_RATIO_SHIFT); + + /* core.clock_control_0 dig_ref_clk_div_ratio 0 */ + clockControl0 |= ADRV9025_BF_ENCODE(refDeviceClockDiv, + ADRV9025_CC0_DIG_REF_CLK_DIV_RATIO_MASK, + ADRV9025_CC0_DIG_REF_CLK_DIV_RATIO_SHIFT); + ADRV9025_SPIWRITEBYTE("CLOCK_CONTROL_0", + ADRV9025_ADDR_CLOCK_CONTROL_0, + clockControl0); + + /* clkpll.ref_clk_divide_ratio */ + refClkByte0 |= ADRV9025_BF_ENCODE(refClockDiv, + ADRV9025_REF_CLK_DIVIDE_RATIO_MASK, + ADRV9025_REF_CLK_DIVIDE_RATIO_SHIFT); + ADRV9025_SPIWRITEBYTE("PLL_REF_CLK_REG", + ADRV9025_ADDR_PLL_REF_CLK_REG, + refClkByte0); + + ADRV9025_SPIWRITEBYTE("REFERENCE_CLOCK_CYCLE", + ADRV9025_ADDR_REFERENCE_CLOCK_CYCLE, + (digRefClock_MHz - 1)); + + /* All RX */ + clockConfig0 = 0; + clockConfig0 |= ADRV9025_BF_ENCODE(armDeviceClockDiv, + ADRV9025_RCC0_CPU_CLK_DIVIDE_RATIO_MASK, + ADRV9025_RCC0_CPU_CLK_DIVIDE_RATIO_SHIFT); + clockConfig0 |= ADRV9025_RCC0_CPU_CLK_ENABLE; + clockConfig0 |= ADRV9025_BF_ENCODE(regDeviceClockDiv, + ADRV9025_RCC0_REG_CLK_DIVIDE_RATIO_MASK, + ADRV9025_RCC0_REG_CLK_DIVIDE_RATIO_SHIFT); + clockConfig0 |= ADRV9025_BF_ENCODE(agcDeviceClockDiv, + ADRV9025_RCC0_AGC_CLK_DIVIDE_RATIO_MASK, + ADRV9025_RCC0_AGC_CLK_DIVIDE_RATIO_SHIFT); + + clockConfig6 = 0; + clockConfig6 |= ADRV9025_BF_ENCODE(PFIR_MIN_CLOCK_RATE, + ADRV9025_RCC6_RPFIR_CLK_DIVIDE_RATIO_MASK, + ADRV9025_RCC6_RPFIR_CLK_DIVIDE_RATIO_SHIFT); + + for (i = 0; i < ADRV9025_ADDR_CH_RX_SIZE; i++) + { + ADRV9025_SPIWRITEBYTE("RX_CLOCK_CONFIG_0", + (ADRV9025_ADDR_CH_RX_BASE[i] + ADRV9025_ADDR_RX_CLOCK_CONFIG_0_OFFSET), + clockConfig0); + + ADRV9025_SPIWRITEBYTE("RX_CLOCK_CONFIG_6", + (ADRV9025_ADDR_CH_RX_BASE[i] + ADRV9025_ADDR_RX_CLOCK_CONFIG_6_OFFSET), + clockConfig6); + if (i < 4) + { + ADRV9025_SPIWRITEBYTE("RX_REFERENCE_CLOCK_CYCLE", + (ADRV9025_ADDR_CH_RX_BASE[i] + ADRV9025_ADDR_RX_REFERENCE_CLOCK_CYCLE_OFFSET), + (digRefClock_MHz - 1)); + } + else + { + ADRV9025_SPIWRITEBYTE("RX_REFERENCE_CLOCK_CYCLE", + (ADRV9025_ADDR_CH_RX_BASE[i] + ADRV9025_ADDR_ORX_REFERENCE_CLOCK_CYCLE_OFFSET), + (digRefClock_MHz - 1)); + } + } + + /* All TX */ + txClockControl0 = 0; + txClockControl0 |= ADRV9025_BF_ENCODE(armDeviceClockDiv, + ADRV9025_TCC0_CPU_CLK_DIVIDE_RATIO_MASK, + ADRV9025_TCC0_CPU_CLK_DIVIDE_RATIO_SHIFT); + txClockControl0 |= ADRV9025_TCC0_CPU_CLK_ENABLE; + txClockControl0 |= ADRV9025_BF_ENCODE(regDeviceClockDiv, + ADRV9025_TCC0_REG_CLK_DIVIDE_RATIO_MASK, + ADRV9025_TCC0_REG_CLK_DIVIDE_RATIO_SHIFT); + txClockControl0 |= ADRV9025_BF_ENCODE(txAttenDeviceClockDiv, + ADRV9025_TCC0_TX_ATTEN_CLK_DIVIDE_RATIO_MASK, + ADRV9025_TCC0_TX_ATTEN_CLK_DIVIDE_RATIO_SHIFT); + + txClockControl2 = 0; + txClockControl2 |= ADRV9025_BF_ENCODE(PFIR_MIN_CLOCK_RATE, + ADRV9025_TCC2_TPFIR_CLK_DIVIDE_RATIO_MASK, + ADRV9025_TCC2_TPFIR_CLK_DIVIDE_RATIO_SHIFT); + + txClockControl3 = 0; + txClockControl3 |= ADRV9025_BF_ENCODE(TXATTEN_CLK_ENABLE, + ADRV9025_TCC3_TX_ATTEN_CLK_ENABLE_MASK, + ADRV9025_TCC3_TX_ATTEN_CLK_ENABLE_SHIFT); + + for (i = 0; i < ADRV9025_ADDR_CH_TX_SIZE; i++) + { + ADRV9025_SPIWRITEBYTE("TX_CLOCK_CONTROL_0", + (ADRV9025_ADDR_CH_TX_BASE[i] + ADRV9025_ADDR_TX_CLOCK_CONTROL_0_OFFSET), + txClockControl0); + + ADRV9025_SPIWRITEBYTE("TX_CLOCK_CONTROL_2", + (ADRV9025_ADDR_CH_TX_BASE[i] + ADRV9025_ADDR_TX_CLOCK_CONTROL_2_OFFSET), + txClockControl2); + + ADRV9025_SPIWRITEBYTE("TX_REFERENCE_CLOCK_CYCLE", + (ADRV9025_ADDR_CH_TX_BASE[i] + ADRV9025_ADDR_TX_REFERENCE_CLOCK_CYCLE_OFFSET), + (digRefClock_MHz - 1)); + + /* Enable Tx Atten table clock for Tx channels */ + ADRV9025_SPIWRITEBYTE("TX_ATTEN_CLK_ENABLE", + (ADRV9025_ADDR_CH_TX_BASE[i] + ADRV9025_ADDR_TX_CLOCK_CONTROL_3_OFFSET), + txClockControl3); + } + + /* core.clock_control_6 digital_clock_power_up */ + clockControl7 |= ADRV9025_CC7_DIGITAL_CLOCK_POWER_UP; + ADRV9025_SPIWRITEBYTE("CLOCK_CONTROL_7", + ADRV9025_ADDR_CLOCK_CONTROL_7, + clockControl7); + + /* Enable SPI AHB bridge for ARM */ + ADRV9025_SPIWRITEBYTE("AHB_SPI_BRIDGE", + ADRV9025_ADDR_AHB_SPI_BRIDGE, + (ADRV9025_AHB_SPI_BRIDGE_RESET | ADRV9025_AHB_SPI_BRIDGE_EN)); + + /* Init ARM C */ + armCtl1 = ADRV9025_CPU_MASK_CTL1_DEBUG_ENABLE | ADRV9025_CPU_MASK_CTL1_MEM_HRESP; + armCtl1 &= ~ADRV9025_CPU_MASK_CTL1_M3_RUN; + ADRV9025_SPIWRITEBYTE("ADRV9025_ADDR_CPU_CTL_1", + ADRV9025_CPU_C_ADDR_CTL_1, + armCtl1); + + /* Init ARM D */ + armCtl1 = ADRV9025_CPU_MASK_CTL1_DEBUG_ENABLE; /* ARM-D doesn't have HRESP mask, HRESP mask bit for ARM-C is being shared by 2 CPUs */ + armCtl1 &= ~ADRV9025_CPU_MASK_CTL1_M3_RUN; + ADRV9025_SPIWRITEBYTE("ADRV9025_ADDR_CPU_D_CTL_1", + ADRV9025_CPU_D_ADDR_CTL_1, + armCtl1); + + device->devStateInfo.clkDivideRatios.agcClkDivideRatio = agcDeviceClockDiv; + device->devStateInfo.clkDivideRatios.armClkDivideRatio = armDeviceClockDiv; + device->devStateInfo.clkDivideRatios.regClkDivideRatio = regDeviceClockDiv; + device->devStateInfo.clkDivideRatios.txAttenDeviceClockDivideRatio = txAttenDeviceClockDiv; + + return (device->common.error.newAction); +} + +/** +* \brief Verifies the Tx profile members are valid (in range) in the init structure +* +* If the Tx profile IQ data rate = 0, it is assumed that the Tx profile is +* not used. If Tx IQ data rate > 0, and Tx profile members are out of range, +* the function stores the error code describing the error, and returns a +* Recovery action to check the configuration settings. +* +* \pre This function is private and is not called directly by the user. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to ADRV9025 device data structure +* \param txProfile txProfile settings to be verified +* \param txHsDigClk_kHz Return value of the calculated HS Dig Clock required by the Tx profile +* \param txChannelBitMask the bit mask position corresponding the TX Channel. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +static int32_t adrv9025_VerifyTxProfile(adi_adrv9025_Device_t* device, + adi_adrv9025_TxProfile_t* txProfile, + uint32_t* txHsDigClk_kHz, + int32_t txChannelBitMask) +{ + static const uint32_t TXINPUTRATEMIN = 61440; + static const uint32_t TXINPUTRATEMAX = 500000; + + static const uint32_t RFBANDWIDTHMIN = 20000; + static const uint32_t RFBANDWIDTHMAX = 450000; + + static const uint32_t TXSRLRATEMAX1 = 500000; + static const uint32_t TXSRLRATEMAX2 = 625000; + uint32_t srlInputRate = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + txProfile); + + ADI_NULL_PTR_RETURN(&device->common, + txHsDigClk_kHz); + + ADRV9025_BUGINFO(__FUNCTION__); + + *txHsDigClk_kHz = 0; + /********************************/ + /* Check for a valid Tx profile */ + /********************************/ + if ((txProfile->txInputRate_kHz < TXINPUTRATEMIN) || + (txProfile->txInputRate_kHz > TXINPUTRATEMAX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Tx Profile IQRate is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txProfile->rfBandwidth_kHz < RFBANDWIDTHMIN) || + (txProfile->rfBandwidth_kHz > RFBANDWIDTHMAX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Tx Profile RF bandwidth is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txProfile->thb1Interpolation != 1) && + (txProfile->thb1Interpolation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Tx Profile halfband 1 FIR filter interpolation is out of range (1,2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txProfile->thb2Interpolation != 1) && + (txProfile->thb2Interpolation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Tx Profile halfband 2 FIR filter interpolation is out of range (1,2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txProfile->thb3Interpolation != 1) && + (txProfile->thb3Interpolation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Tx Profile halfband 3 FIR filter interpolation is out of range (1,2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txProfile->txInt5Interpolation != 1) && + (txProfile->txInt5Interpolation != 5)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Tx Profile Interpolate by 5 FIR filter interpolation is out of range (1,5)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Int5 and thb2/3 should be mutually exclusive */ + if ((txProfile->txInt5Interpolation == 5) && + ((txProfile->thb2Interpolation != 1) || + (txProfile->thb3Interpolation != 1))) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Tx Profile Interpolate by 5 FIR filter should be mutually exclusive to halfband 1,2,3 filters"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txProfile->txFirInterpolation != 1) && + (txProfile->txFirInterpolation != 2) && + (txProfile->txFirInterpolation != 4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Tx Profile programmable FIR filter interpolation is out of range(1,2,4)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txProfile->txFir.numFirCoefs == 0) && + (txProfile->txFirInterpolation != 1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Tx Profile PFIR coef array is NULL and filter is not disabled"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txProfile->dpdHb1Interpolation != 1) && + (txProfile->dpdHb1Interpolation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Tx Profile dpd halfband 1 FIR filter interpolation is out of range (1,2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txProfile->dpdHb2Interpolation != 1) && + (txProfile->dpdHb2Interpolation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Tx Profile dpd halfband 2 FIR filter interpolation is out of range (1,2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txProfile->txBbfPowerMode != 0) && (txProfile->txBbfPowerMode != 8)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid Tx Profile BBF power mode. Allowable values are 0 and 8"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + uint32_t HsDigClk_kHz = (txProfile->txInputRate_kHz * txProfile->txFirInterpolation * + txProfile->dpdHb1Interpolation * txProfile->dpdHb2Interpolation * + txProfile->thb1Interpolation * txProfile->thb2Interpolation * + txProfile->thb3Interpolation * txProfile->txInt5Interpolation); + + if (txProfile->txInt5Interpolation == 5) + { + HsDigClk_kHz /= 5; + } + else + { + HsDigClk_kHz /= 4; + } + + *txHsDigClk_kHz = HsDigClk_kHz; + + /* Checking for SRL limitations */ + srlInputRate = txProfile->txInputRate_kHz * txProfile->dpdHb1Interpolation * txProfile->dpdHb2Interpolation; + if (((txProfile->txInt5Interpolation == 5) && (srlInputRate > TXSRLRATEMAX1)) || + ((txProfile->txInt5Interpolation == 1) && (srlInputRate > TXSRLRATEMAX2))) + { + device->devStateInfo.txSrlRateInvalidMask |= (1 << txChannelBitMask); + } + + return (device->common.error.newAction); +} + +/** +* \brief Verifies the Rx profile members are valid (in range) and calculates HS Dig Clock require for the Rx Profile +* +* Private helper function to verify the Rx profile members are valid (in range) +* and calculates HS Dig Clock require for the Rx Profile +* If the Rx profile IQ data rate = 0, it is assumed that the Rx profile is +* not used. If Rx IQ data rate > 0, and Rx profile members are out of range, +* the function stores the error code describing the error, and returns a +* Recovery action to check the configuration settings. +* +* \pre This function is private and is not called directly by the user. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to ADRV9025 device data structure +* \param rxProfile rxProfile settings to be verified +* \param rxHsDigClk_kHz Return value of the calculated HS Dig Clock required by the Rx profile +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +static int32_t adrv9025_VerifyRxProfile(adi_adrv9025_Device_t* device, + adi_adrv9025_RxProfile_t* rxProfile, + uint32_t* rxHsDigClk_kHz) +{ + uint8_t ddcMultiply = 1; + uint8_t ddcDivide = 1; + + static const uint32_t RXOUTPUTRATEMIN = 61440; + static const uint32_t RXOUTPUTRATEMAX = 500000; + + static const uint32_t RXBANDWIDTHMIN = 20000; + static const uint32_t RXBANDWIDTHMAX = 300000; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + rxProfile); + + ADI_NULL_PTR_RETURN(&device->common, + rxHsDigClk_kHz); + + ADRV9025_BUGINFO(__FUNCTION__); + + *rxHsDigClk_kHz = 0; + + /********************************/ + /* Check for a valid Rx profile */ + /********************************/ + if ((rxProfile->rxOutputRate_kHz < RXOUTPUTRATEMIN) || + (rxProfile->rxOutputRate_kHz > RXOUTPUTRATEMAX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Rx Profile IQRate is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxProfile->rfBandwidth_kHz < RXBANDWIDTHMIN) || + (rxProfile->rfBandwidth_kHz > RXBANDWIDTHMAX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Rx Profile RF bandwidth is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxProfile->rhb1Decimation != 1) && + (rxProfile->rhb1Decimation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Rx Profile halfband 1 FIR filter decimation out of range(1, 2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxProfile->rhb2Decimation != 1) && + (rxProfile->rhb2Decimation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Rx Profile halfband 2 FIR filter decimation out of range(1, 2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxProfile->rhb3Decimation != 1) && + (rxProfile->rhb3Decimation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Rx Profile halfband 3 FIR filter decimation out of range(1, 2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxProfile->rxDec5Decimation != 1) && + (rxProfile->rxDec5Decimation != 5)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Rx Profile Dec5 FIR filter decimation out of range(1,5)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxProfile->rxFirDecimation != 1) && + (rxProfile->rxFirDecimation != 2) && + (rxProfile->rxFirDecimation != 4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Rx Profile programmable FIR decimation out of range (1,2,4)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxProfile->rxFir1Decimation != 1) && + (rxProfile->rxFir1Decimation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Rx Profile FIR 1 decimation out of range (1,2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxProfile->rxFir2Decimation != 1) && + (rxProfile->rxFir2Decimation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Rx Profile FIR 2 decimation out of range (1,2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxProfile->rxFir.numFirCoefs == 0) && + (rxProfile->rxFirDecimation != 1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Rx Profile PFIR coefficient array is NULL and filter is not bypassed"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (rxProfile->tiaPowerMode > 4) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Rx Profile TIA Power mode is out of range (0 - 4)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + switch (rxProfile->rxDdcMode) + { + case ADI_ADRV9025_RXDDC_BYPASS_REALIF: + case ADI_ADRV9025_RXDDC_BYPASS: + ddcMultiply = 1; + ddcDivide = 1; + break; + case ADI_ADRV9025_RXDDC_DEC2_REALIF: + case ADI_ADRV9025_RXDDC_DEC2: + ddcMultiply = 2; + ddcDivide = 1; + break; + case ADI_ADRV9025_RXDDC_INT2_REALIF: + case ADI_ADRV9025_RXDDC_INT2: + ddcMultiply = 1; + ddcDivide = 2; + break; + case ADI_ADRV9025_RXDDC_FILTERONLY_REALIF: + case ADI_ADRV9025_RXDDC_FILTERONLY: + ddcMultiply = 1; + ddcDivide = 1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Rx Profile DDC mode is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + uint32_t HsDigClk_kHz = (rxProfile->rxOutputRate_kHz * rxProfile->rxFirDecimation * + rxProfile->rxFir1Decimation * rxProfile->rxFir2Decimation * + rxProfile->rhb1Decimation * rxProfile->rhb2Decimation * rxProfile->rhb3Decimation * + rxProfile->rxDec5Decimation * ddcMultiply) / ddcDivide; + + if (rxProfile->rxDec5Decimation == 5) + { + HsDigClk_kHz /= 5; + } + else + { + HsDigClk_kHz /= 4; + } + + *rxHsDigClk_kHz = HsDigClk_kHz; + + return (device->common.error.newAction); +} + +/** +* \brief Verifies the Rx profile members are valid (in range) and calculates HS Dig Clock require for the Rx Profile +* +* Private helper function to verify the Rx profile members are valid (in range) +* and calculates HS Dig Clock require for the Rx Profile +* If the Rx profile IQ data rate = 0, it is assumed that the Rx profile is +* not used. If Rx IQ data rate > 0, and Rx profile members are out of range, +* the function stores the error code describing the error, and returns a +* Recovery action to check the configuration settings. +* +* \pre This function is private and is not called directly by the user. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to ADRV9025 device data structure +* \param orxProfile rxProfile settings to be verified +* \param orxHsDigClk_kHz Return value of the calculated HS Dig Clock required by the Rx profile +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +static int32_t adrv9025_VerifyOrxProfile(adi_adrv9025_Device_t* device, + adi_adrv9025_RxProfile_t* orxProfile, + uint32_t* orxHsDigClk_kHz) +{ + uint8_t ddcMultiply = 1; + uint8_t ddcDivide = 1; + + static const uint32_t RXOUTPUTRATEMIN = 122880; + static const uint32_t RXOUTPUTRATEMAX = 500000; + + static const uint32_t RXBANDWIDTHMIN = 20000; + static const uint32_t RXBANDWIDTHMAX = 450000; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + orxProfile); + + ADI_NULL_PTR_RETURN(&device->common, + orxHsDigClk_kHz); + + ADRV9025_BUGINFO(__FUNCTION__); + + *orxHsDigClk_kHz = 0; + + /********************************/ + /* Check for a valid ORx profile */ + /********************************/ + if ((orxProfile->rxOutputRate_kHz < RXOUTPUTRATEMIN) || + (orxProfile->rxOutputRate_kHz > RXOUTPUTRATEMAX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "ORx Profile IQRate is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((orxProfile->rfBandwidth_kHz < RXBANDWIDTHMIN) || + (orxProfile->rfBandwidth_kHz > RXBANDWIDTHMAX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "ORx Profile RF bandwidth is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((orxProfile->rhb1Decimation != 1) && + (orxProfile->rhb1Decimation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "ORx Profile halfband 1 FIR filter decimation out of range(1, 2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((orxProfile->rhb2Decimation != 1) && + (orxProfile->rhb2Decimation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "ORx Profile halfband 2 FIR filter decimation out of range(1, 2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((orxProfile->rhb3Decimation != 1) && + (orxProfile->rhb3Decimation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "ORx Profile halfband 3 FIR filter decimation out of range(1, 2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((orxProfile->rxDec5Decimation != 1) && + (orxProfile->rxDec5Decimation != 5)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "ORx Profile Dec5 FIR filter decimation out of range(1,5)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((orxProfile->rxFirDecimation != 1) && + (orxProfile->rxFirDecimation != 2) && + (orxProfile->rxFirDecimation != 4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "ORx Profile programmable FIR decimation out of range (1,2,4)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((orxProfile->rxFir1Decimation != 1) && + (orxProfile->rxFir1Decimation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "ORx Profile FIR 1 decimation out of range (1,2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((orxProfile->rxFir.numFirCoefs == 0) && + (orxProfile->rxFirDecimation != 1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "ORx Profile PFIR coefficient array is NULL and filter is not bypassed"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (orxProfile->tiaPowerMode > 4) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "ORx Profile TIA Power mode is out of range (0 - 4)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + switch (orxProfile->rxDdcMode) + { + case ADI_ADRV9025_RXDDC_BYPASS_REALIF: + case ADI_ADRV9025_RXDDC_BYPASS: + ddcMultiply = 1; + ddcDivide = 1; + break; + case ADI_ADRV9025_RXDDC_DEC2_REALIF: + case ADI_ADRV9025_RXDDC_DEC2: + ddcMultiply = 2; + ddcDivide = 1; + break; + case ADI_ADRV9025_RXDDC_INT2_REALIF: + case ADI_ADRV9025_RXDDC_INT2: + ddcMultiply = 1; + ddcDivide = 2; + break; + case ADI_ADRV9025_RXDDC_FILTERONLY_REALIF: + case ADI_ADRV9025_RXDDC_FILTERONLY: + ddcMultiply = 1; + ddcDivide = 1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "ORx Profile DDC mode is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + uint32_t HsDigClk_kHz = (orxProfile->rxOutputRate_kHz * orxProfile->rxFirDecimation * + orxProfile->rxFir1Decimation * + orxProfile->rhb1Decimation * orxProfile->rhb2Decimation * orxProfile->rhb3Decimation * + orxProfile->rxDec5Decimation * ddcMultiply) / ddcDivide; + + if (orxProfile->rxDec5Decimation == 5) + { + HsDigClk_kHz /= 5; + } + else + { + HsDigClk_kHz /= 4; + } + + *orxHsDigClk_kHz = HsDigClk_kHz; + + return (device->common.error.newAction); +} + +/** +* \brief Verifies the Loopback profile members are valid (in range) and calculates HS Dig Clock require for the Rx Profile +* +* Private helper function to verify the Loopback profile members are valid (in range) +* and calculates HS Dig Clock require for the Loopback Profile +* If the LB profile IQ data rate = 0, it is assumed that the LB profile is +* not used. If LB IQ data rate > 0, and LB profile members are out of range, +* the function stores the error code describing the error, and returns a +* Recovery action to check the configuration settings. +* +* \pre This function is private and is not called directly by the user. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to ADRV9025 device data structure +* \param lbProfile lbProfile settings to be verified +* \param lbHsDigClk_kHz Return value of the calculated HS Dig Clock required by the LB profile +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +static int32_t adrv9025_VerifyLbProfile(adi_adrv9025_Device_t* device, + adi_adrv9025_RxProfile_t* lbProfile, + uint32_t* lbHsDigClk_kHz) +{ + uint8_t ddcMultiply = 1; + uint8_t ddcDivide = 1; + + static const uint32_t RXOUTPUTRATEMIN = 61440; + static const uint32_t RXOUTPUTRATEMAX = 500000; + + static const uint32_t RXBANDWIDTHMIN = 20000; + static const uint32_t RXBANDWIDTHMAX = 455000; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + lbProfile); + + ADI_NULL_PTR_RETURN(&device->common, + lbHsDigClk_kHz); + + ADRV9025_BUGINFO(__FUNCTION__); + + *lbHsDigClk_kHz = 0; + + /********************************/ + /* Check for a valid ORx profile */ + /********************************/ + if ((lbProfile->rxOutputRate_kHz < RXOUTPUTRATEMIN) || + (lbProfile->rxOutputRate_kHz > RXOUTPUTRATEMAX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "LB Profile IQRate is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((lbProfile->rfBandwidth_kHz < RXBANDWIDTHMIN) || + (lbProfile->rfBandwidth_kHz > RXBANDWIDTHMAX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "LB Profile RF bandwidth is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((lbProfile->rhb1Decimation != 1) && + (lbProfile->rhb1Decimation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "LB Profile halfband 1 FIR filter decimation out of range(1, 2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((lbProfile->rhb2Decimation != 1) && + (lbProfile->rhb2Decimation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "LB Profile halfband 2 FIR filter decimation out of range(1, 2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((lbProfile->rhb3Decimation != 1) && + (lbProfile->rhb3Decimation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "LB Profile halfband 3 FIR filter decimation out of range(1, 2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((lbProfile->rxDec5Decimation != 1) && + (lbProfile->rxDec5Decimation != 5)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "LB Profile Dec5 FIR filter decimation out of range(1,5)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((lbProfile->rxFirDecimation != 1) && + (lbProfile->rxFirDecimation != 2) && + (lbProfile->rxFirDecimation != 4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "LB Profile programmable FIR decimation out of range (1,2,4)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((lbProfile->rxFir1Decimation != 1) && + (lbProfile->rxFir1Decimation != 2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "LB Profile FIR 1 decimation out of range (1,2)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((lbProfile->rxFir.numFirCoefs == 0) && + (lbProfile->rxFirDecimation != 1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "LB Profile PFIR coefficient array is NULL and filter is not bypassed"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + switch (lbProfile->rxDdcMode) + { + case ADI_ADRV9025_RXDDC_BYPASS_REALIF: + case ADI_ADRV9025_RXDDC_BYPASS: + ddcMultiply = 1; + ddcDivide = 1; + break; + case ADI_ADRV9025_RXDDC_DEC2_REALIF: + case ADI_ADRV9025_RXDDC_DEC2: + ddcMultiply = 2; + ddcDivide = 1; + break; + case ADI_ADRV9025_RXDDC_INT2_REALIF: + case ADI_ADRV9025_RXDDC_INT2: + ddcMultiply = 1; + ddcDivide = 2; + break; + case ADI_ADRV9025_RXDDC_FILTERONLY_REALIF: + case ADI_ADRV9025_RXDDC_FILTERONLY: + ddcMultiply = 1; + ddcDivide = 1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "LB Profile DDC mode is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + uint32_t HsDigClk_kHz = (lbProfile->rxOutputRate_kHz * lbProfile->rxFirDecimation * + lbProfile->rxFir1Decimation * + lbProfile->rhb1Decimation * lbProfile->rhb2Decimation * lbProfile->rhb3Decimation * + lbProfile->rxDec5Decimation * ddcMultiply) / ddcDivide; + + if (lbProfile->rxDec5Decimation == 5) + { + HsDigClk_kHz /= 5; + } + else + { + HsDigClk_kHz /= 4; + } + + *lbHsDigClk_kHz = HsDigClk_kHz; + + return (device->common.error.newAction); +} + +int32_t adrv9025_ProfilesVerify(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init) +{ + uint32_t rxHsDigClk_kHz = 0; + uint32_t orxHsDigClk_kHz = 0; + uint32_t txHsDigClk_kHz = 0; + uint32_t lbxHsDigClk_kHz = 0; + uint32_t hsDigClk_kHz = 0; + adi_adrv9025_RxProfile_t* rxProfile = NULL; + adi_adrv9025_TxProfile_t* txProfile = NULL; + int i = 0; + uint32_t maskBit = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + init); + + ADRV9025_BUGINFO(__FUNCTION__); + + device->devStateInfo.profilesValid = 0; + + hsDigClk_kHz = 0; + if (init->tx.txInitChannelMask != ADI_ADRV9025_TXOFF) + { + for (i = 0; i < ADI_ADRV9025_MAX_TXCHANNELS; i++) + { + maskBit = (1 << i); + if (ADRV9025_BF_EQUAL(init->tx.txInitChannelMask, + maskBit)) + { + txProfile = &init->tx.txChannelCfg[i].profile; + adrv9025_VerifyTxProfile(device, + txProfile, + &txHsDigClk_kHz, + i); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (hsDigClk_kHz == 0) + { + hsDigClk_kHz = txHsDigClk_kHz; + } + + if (hsDigClk_kHz != txHsDigClk_kHz) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txHsDigClk_kHz, + "Tx Profile IQrate and filter settings are not possible with current CLKPLL frequency"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + } + + hsDigClk_kHz = 0; + if (init->rx.rxInitChannelMask != ADI_ADRV9025_RXOFF) + { + for (i = 0; i < ADI_ADRV9025_MAX_RX_ONLY; i++) + { + maskBit = (1 << i); + if (ADRV9025_BF_EQUAL(init->rx.rxInitChannelMask, + maskBit)) + { + rxProfile = &init->rx.rxChannelCfg[i].profile; + adrv9025_VerifyRxProfile(device, + rxProfile, + &rxHsDigClk_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (hsDigClk_kHz == 0) + { + hsDigClk_kHz = rxHsDigClk_kHz; + } + + if (hsDigClk_kHz != rxHsDigClk_kHz) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxHsDigClk_kHz, + "Rx Profile IQrate and filter settings are not possible with current CLKPLL frequency"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + } + + hsDigClk_kHz = 0; + if (init->rx.rxInitChannelMask != ADI_ADRV9025_RXOFF) + { + for (i = ADI_ADRV9025_MAX_RX_ONLY; i < ADI_ADRV9025_MAX_LB_CHANNEL_START; i++) + { + maskBit = (1 << i); + if (ADRV9025_BF_EQUAL(init->rx.rxInitChannelMask, + maskBit)) + { + rxProfile = &init->rx.rxChannelCfg[i].profile; + adrv9025_VerifyOrxProfile(device, + rxProfile, + &orxHsDigClk_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (hsDigClk_kHz == 0) + { + hsDigClk_kHz = orxHsDigClk_kHz; + } + + if (hsDigClk_kHz != orxHsDigClk_kHz) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + orxHsDigClk_kHz, + "ORx Profile IQrate and filter settings are not possible with current CLKPLL frequency"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + } + + hsDigClk_kHz = 0; + if (init->rx.rxInitChannelMask != ADI_ADRV9025_RXOFF) + { + for (i = ADI_ADRV9025_MAX_LB_CHANNEL_START; i < ADI_ADRV9025_MAX_RXCHANNELS; i++) + { + maskBit = (1 << i); + if (ADRV9025_BF_EQUAL(init->rx.rxInitChannelMask, + maskBit)) + { + rxProfile = &init->rx.rxChannelCfg[i].profile; + adrv9025_VerifyLbProfile(device, + rxProfile, + &lbxHsDigClk_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (hsDigClk_kHz == 0) + { + hsDigClk_kHz = lbxHsDigClk_kHz; + } + + if (hsDigClk_kHz != lbxHsDigClk_kHz) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + orxHsDigClk_kHz, + "LBx Profile IQrate and filter settings are not possible with current CLKPLL frequency"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + } + + if ((init->clocks.rfPllPhaseSyncMode != ADI_ADRV9025_RFPLLMCS_NOSYNC) + && (init->clocks.rfPllPhaseSyncMode != ADI_ADRV9025_RFPLLMCS_INIT_AND_SYNC) + && (init->clocks.rfPllPhaseSyncMode != ADI_ADRV9025_RFPLLMCS_INIT_AND_CONTTRACK)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "init->clocks.rfPllPhaseSyncMode structure member has invalid option for RFPLL phase sync mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Set the maximum hsDigClk_kHz */ + if (txHsDigClk_kHz > 0) + { + device->devStateInfo.profilesValid |= ADI_ADRV9025_TX_PROFILE_VALID; + device->devStateInfo.hsDigClk_kHz = txHsDigClk_kHz; + } + + /* Verify Rx profile is valid */ + if (rxHsDigClk_kHz > 0) + { + device->devStateInfo.profilesValid |= ADI_ADRV9025_RX_PROFILE_VALID; + if (device->devStateInfo.hsDigClk_kHz < rxHsDigClk_kHz) + { + device->devStateInfo.hsDigClk_kHz = rxHsDigClk_kHz; + } + } + + /* Verify ORx profile is valid */ + if (orxHsDigClk_kHz > 0) + { + device->devStateInfo.profilesValid |= ADI_ADRV9025_ORX_PROFILE_VALID; + if (device->devStateInfo.hsDigClk_kHz < orxHsDigClk_kHz) + { + device->devStateInfo.hsDigClk_kHz = orxHsDigClk_kHz; + } + } + + /* Verify LBx profile is valid */ + if ((lbxHsDigClk_kHz > 0) && (txHsDigClk_kHz > 0)) + { + device->devStateInfo.profilesValid |= ADI_ADRV9025_LB_PROFILE_VALID; + } + + return (device->common.error.newAction); +} + +int32_t adrv9025_RxOverloadProtectionSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel) +{ + static const uint8_t ALL_RX_MASK = (uint32_t)(ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4); + static const uint8_t ALL_ORX_MASK = (uint32_t)(ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2 | ADI_ADRV9025_ORX3 | ADI_ADRV9025_ORX4); + static const uint8_t MANUAL_GAIN_CTRL_CONFIG_REG_VAL = 0x02; + static const uint16_t MANUAL_GAIN_CTRL_CONFIG_REG_RX_OFFSET = 0x52; + static const uint16_t MANUAL_GAIN_CTRL_CONFIG_REG_ORX_OFFSET = 0x74; + static const uint8_t ULB_THRESHOLD_EXCEEDED_CNTR_REG_VAL = 0x03; + static const uint16_t ULB_THRESHOLD_EXCEEDED_CNTR_REG_RX_OFFSET = 0x6E; + static const uint16_t ULB_THRESHOLD_EXCEEDED_CNTR_REG_ORX_OFFSET = 0x8B; + static const uint8_t AGC_ADC_HIGH_OVRG_EXCEEDED_CNTR_REG_VAL = 0x03; + static const uint16_t AGC_ADC_HIGH_OVRG_EXCEEDED_CNTR_REG_RX_OFFSET = 0x70; + static const uint16_t AGC_ADC_HIGH_OVRG_EXCEEDED_CNTR_REG_ORX_OFFSET = 0x8D; + static const uint64_t AGC_GAIN_UPDATE_CNTR_uS = 500; + static const uint32_t MAX_AGC_GAIN_UPDATE_CNTR_REG_VAL = 0x03FFFFFF; + static const uint16_t AGC_GAIN_UPDATE_CNTR1_RX_OFFSET = 0x77; + static const uint16_t AGC_GAIN_UPDATE_CNTR2_RX_OFFSET = 0x78; + static const uint16_t AGC_GAIN_UPDATE_CNTR3_RX_OFFSET = 0x79; + static const uint16_t AGC_GAIN_UPDATE_CNTR1_ORX_OFFSET = 0x94; + static const uint16_t AGC_GAIN_UPDATE_CNTR2_ORX_OFFSET = 0x95; + static const uint16_t AGC_GAIN_UPDATE_CNTR3_ORX_OFFSET = 0x96; + static const uint8_t AGC_SLOWLOOP_SETTLING_DELAY_REG_VAL = 0x10; + static const uint16_t AGC_SLOWLOOP_SETTLING_DELAY_REG_RX_OFFSET = 0x7B; + static const uint16_t AGC_SLOWLOOP_SETTLING_DELAY_REG_ORX_OFFSET = 0x9B; + static const uint8_t DEC_OVERLOAD_CONFIG1_REG_VAL = 0xA1; + static const uint16_t DEC_OVERLOAD_CONFIG1_REG_RX_OFFSET = 0xF4; + static const uint16_t DEC_OVERLOAD_CONFIG1_REG_ORX_OFFSET = 0xC0; + static const uint8_t DEC_OVERLOAD_CONFIG2_REG_VAL = 0x07; + static const uint16_t DEC_OVERLOAD_CONFIG2_REG_RX_OFFSET = 0xF5; + static const uint16_t DEC_OVERLOAD_CONFIG2_REG_ORX_OFFSET = 0xC1; + static const uint8_t DEC_OVERLOAD_UPPER_THRESHOLD1_REG_VAL = 0x94; + static const uint16_t DEC_OVERLOAD_UPPER_THRESHOLD1_REG_RX_OFFSET = 0xF6; + static const uint16_t DEC_OVERLOAD_UPPER_THRESHOLD1_REG_ORX_OFFSET = 0xC2; + static const uint8_t DEC_OVERLOAD_UPPER_THRESHOLD2_REG_VAL = 0x28; + static const uint16_t DEC_OVERLOAD_UPPER_THRESHOLD2_REG_RX_OFFSET = 0xF7; + static const uint16_t DEC_OVERLOAD_UPPER_THRESHOLD2_REG_ORX_OFFSET = 0xC3; + static const uint8_t ANALOG_RX_BLOCK_DET_ULBTH_REG_VAL = 0x2A; /*-2dBFS Threshold, Assuming FS of ADC is 0.85V*/ + static const uint8_t ANALOG_RX_BLOCK_DET_LLBTH_REG_VAL = 0x1E; /*-5dBFS Threshold, Assuming FS of ADC is 0.85V*/ + static const uint16_t ANALOG_RX_BLOCK_DET_ULBTH_REG_RX_OFFSET = 0x65; + static const uint16_t ANALOG_RX_BLOCK_DET_LLBTH_REG_RX_OFFSET = 0x63; + static const uint16_t ANALOG_RX_BLOCK_DET_ULBTH_REG_ORX_OFFSET = 0x9E; + static const uint16_t ANALOG_RX_BLOCK_DET_LLBTH_REG_ORX_OFFSET = 0x9A; + static const uint16_t RX_BLOCK_TIA_VALID_OVERRIDE_OFFSET = 0x5A; + static const uint16_t ORX_BLOCK_TIA_VALID_OVERRIDE_OFFSET = 0x7C; + static const uint8_t SLOWLOOP_CONFIG_REG_VAL = 0x3C; + static const uint16_t SLOWLOOP_CONFIG_REG_RX_OFFSET = 0x7A; + static const uint16_t SLOWLOOP_CONFIG_REG_ORX_OFFSET = 0x9A; + static const uint8_t TIA_VALID_OVERRIDE_MASK = 0x02; + static const uint8_t TIA_VALID_OVERRIDE_SHIFT = 0x01; + + uint32_t agcClkRate_kHz = (device->devStateInfo.hsDigClk_kHz >> device->devStateInfo.clkDivideRatios.agcClkDivideRatio); + uint64_t agcGainUpdateCounter = ((AGC_GAIN_UPDATE_CNTR_uS * agcClkRate_kHz) / 1000); + uint8_t agcGainUpdateCntr1RegVal = (uint8_t)(agcGainUpdateCounter & (uint32_t)0x000000FF); + uint8_t agcGainUpdateCntr2RegVal = (uint8_t)((uint32_t)(agcGainUpdateCounter & (uint32_t)0x0000FF00) >> 8); + uint8_t agcGainUpdateCntr3RegVal = (uint8_t)((uint32_t)(agcGainUpdateCounter & (uint32_t)0x00FF0000) >> 16); + uint16_t manualGainConfigRegAddr = 0; + uint16_t ulbThresholdExceededCntrRegAddr = 0; + uint16_t adcHighOvrgExceededCntrRegAddr = 0; + uint16_t agcGainUpdateCntr1RegAddr = 0; + uint16_t agcGainUpdateCntr2RegAddr = 0; + uint16_t agcGainUpdateCntr3RegAddr = 0; + uint16_t agcSlowLoopSettlingDelayRegAddr = 0; + uint16_t decOverloadConfig1RegAddr = 0; + uint16_t decOverloadConfig2RegAddr = 0; + uint16_t decOverloadUpperThresh1RegAddr = 0; + uint16_t decOverloadUpperThresh2RegAddr = 0; + uint16_t analogRxBlockDetUlbthRegAddr = 0; + uint16_t analogRxBlockDetLlbthRegAddr = 0; + uint16_t slowLoopConfigRegAddr = 0; + uint16_t tiaValidOverrideRegAddr = 0; + adrv9025_BfRxChanAddr_e rxChannelBitfieldBaseAddr = (adrv9025_BfRxChanAddr_e)0; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldBaseAddr = (adrv9025_BfOrxChanAddr_e)0; + adrv9025_BfAnalogRxMemMapChanAddr_e rxChannelAnalogBitfieldBaseAddr = (adrv9025_BfAnalogRxMemMapChanAddr_e)0; + adrv9025_BfAnalogOrxMemMapChanAddr_e orxChannelAnalogBitfieldBaseAddr = (adrv9025_BfAnalogOrxMemMapChanAddr_e)0; + + /*Check that the requested rxChannel is valid*/ + if ((rxChannel != ADI_ADRV9025_RX1) && + (rxChannel != ADI_ADRV9025_RX2) && + (rxChannel != ADI_ADRV9025_RX3) && + (rxChannel != ADI_ADRV9025_RX4) && + (rxChannel != ADI_ADRV9025_ORX1) && + (rxChannel != ADI_ADRV9025_ORX2) && + (rxChannel != ADI_ADRV9025_ORX3) && + (rxChannel != ADI_ADRV9025_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel Requested for Rx Overload Protection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Range check that gain update counter is less than pow(2,22)-1 since the reg is 22 bits wide*/ + if (agcGainUpdateCounter > MAX_AGC_GAIN_UPDATE_CNTR_REG_VAL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + AGC_GAIN_UPDATE_CNTR_uS, + "AGC Gain Update counter interval too large for the given agc clk rate. Max allowed value = 0x03FFFFFF."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((ALL_RX_MASK & (uint32_t)rxChannel) > 0) + { + adrv9025_RxBitfieldAddressGet(device, + rxChannel, + &rxChannelBitfieldBaseAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAnalogBitfieldAddressGet(device, + rxChannel, + &rxChannelAnalogBitfieldBaseAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + manualGainConfigRegAddr = ((uint16_t)rxChannelBitfieldBaseAddr + MANUAL_GAIN_CTRL_CONFIG_REG_RX_OFFSET); + ulbThresholdExceededCntrRegAddr = ((uint16_t)rxChannelBitfieldBaseAddr + ULB_THRESHOLD_EXCEEDED_CNTR_REG_RX_OFFSET); + adcHighOvrgExceededCntrRegAddr = ((uint16_t)rxChannelBitfieldBaseAddr + AGC_ADC_HIGH_OVRG_EXCEEDED_CNTR_REG_RX_OFFSET); + agcGainUpdateCntr1RegAddr = ((uint16_t)rxChannelBitfieldBaseAddr + AGC_GAIN_UPDATE_CNTR1_RX_OFFSET); + agcGainUpdateCntr2RegAddr = ((uint16_t)rxChannelBitfieldBaseAddr + AGC_GAIN_UPDATE_CNTR2_RX_OFFSET); + agcGainUpdateCntr3RegAddr = ((uint16_t)rxChannelBitfieldBaseAddr + AGC_GAIN_UPDATE_CNTR3_RX_OFFSET); + agcSlowLoopSettlingDelayRegAddr = ((uint16_t)rxChannelBitfieldBaseAddr + AGC_SLOWLOOP_SETTLING_DELAY_REG_RX_OFFSET); + decOverloadConfig1RegAddr = ((uint16_t)rxChannelBitfieldBaseAddr + DEC_OVERLOAD_CONFIG1_REG_RX_OFFSET); + decOverloadConfig2RegAddr = ((uint16_t)rxChannelBitfieldBaseAddr + DEC_OVERLOAD_CONFIG2_REG_RX_OFFSET); + decOverloadUpperThresh1RegAddr = ((uint16_t)rxChannelBitfieldBaseAddr + DEC_OVERLOAD_UPPER_THRESHOLD1_REG_RX_OFFSET); + decOverloadUpperThresh2RegAddr = ((uint16_t)rxChannelBitfieldBaseAddr + DEC_OVERLOAD_UPPER_THRESHOLD2_REG_RX_OFFSET); + analogRxBlockDetUlbthRegAddr = ((uint16_t)rxChannelAnalogBitfieldBaseAddr + ANALOG_RX_BLOCK_DET_ULBTH_REG_RX_OFFSET); + analogRxBlockDetLlbthRegAddr = ((uint16_t)rxChannelAnalogBitfieldBaseAddr + ANALOG_RX_BLOCK_DET_LLBTH_REG_RX_OFFSET); + slowLoopConfigRegAddr = ((uint16_t)rxChannelBitfieldBaseAddr + SLOWLOOP_CONFIG_REG_RX_OFFSET); + tiaValidOverrideRegAddr = (uint16_t)rxChannelBitfieldBaseAddr + RX_BLOCK_TIA_VALID_OVERRIDE_OFFSET; + } + else if ((ALL_ORX_MASK & (uint32_t)rxChannel) > 0) + { + adrv9025_OrxBitfieldAddressGet(device, + rxChannel, + &orxChannelBitfieldBaseAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_OrxAnalogBitfieldAddressGet(device, + rxChannel, + &orxChannelAnalogBitfieldBaseAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + manualGainConfigRegAddr = ((uint16_t)orxChannelBitfieldBaseAddr + MANUAL_GAIN_CTRL_CONFIG_REG_ORX_OFFSET); + ulbThresholdExceededCntrRegAddr = ((uint16_t)orxChannelBitfieldBaseAddr + ULB_THRESHOLD_EXCEEDED_CNTR_REG_ORX_OFFSET); + adcHighOvrgExceededCntrRegAddr = ((uint16_t)orxChannelBitfieldBaseAddr + AGC_ADC_HIGH_OVRG_EXCEEDED_CNTR_REG_ORX_OFFSET); + agcGainUpdateCntr1RegAddr = ((uint16_t)orxChannelBitfieldBaseAddr + AGC_GAIN_UPDATE_CNTR1_ORX_OFFSET); + agcGainUpdateCntr2RegAddr = ((uint16_t)orxChannelBitfieldBaseAddr + AGC_GAIN_UPDATE_CNTR2_ORX_OFFSET); + agcGainUpdateCntr3RegAddr = ((uint16_t)orxChannelBitfieldBaseAddr + AGC_GAIN_UPDATE_CNTR3_ORX_OFFSET); + agcSlowLoopSettlingDelayRegAddr = ((uint16_t)orxChannelBitfieldBaseAddr + AGC_SLOWLOOP_SETTLING_DELAY_REG_ORX_OFFSET); + decOverloadConfig1RegAddr = ((uint16_t)orxChannelBitfieldBaseAddr + DEC_OVERLOAD_CONFIG1_REG_ORX_OFFSET); + decOverloadConfig2RegAddr = ((uint16_t)orxChannelBitfieldBaseAddr + DEC_OVERLOAD_CONFIG2_REG_ORX_OFFSET); + decOverloadUpperThresh1RegAddr = ((uint16_t)orxChannelBitfieldBaseAddr + DEC_OVERLOAD_UPPER_THRESHOLD1_REG_ORX_OFFSET); + decOverloadUpperThresh2RegAddr = ((uint16_t)orxChannelBitfieldBaseAddr + DEC_OVERLOAD_UPPER_THRESHOLD2_REG_ORX_OFFSET); + analogRxBlockDetLlbthRegAddr = ((uint16_t)orxChannelAnalogBitfieldBaseAddr + ANALOG_RX_BLOCK_DET_LLBTH_REG_ORX_OFFSET); + analogRxBlockDetUlbthRegAddr = ((uint16_t)orxChannelAnalogBitfieldBaseAddr + ANALOG_RX_BLOCK_DET_ULBTH_REG_ORX_OFFSET); + slowLoopConfigRegAddr = ((uint16_t)orxChannelBitfieldBaseAddr + SLOWLOOP_CONFIG_REG_ORX_OFFSET); + tiaValidOverrideRegAddr = (uint16_t)orxChannelBitfieldBaseAddr + ORX_BLOCK_TIA_VALID_OVERRIDE_OFFSET; + } + + ADRV9025_SPIWRITEBYTE("MANUAL_GAIN_CTRL_CONFIG_REG", + manualGainConfigRegAddr, + MANUAL_GAIN_CTRL_CONFIG_REG_VAL); + ADRV9025_SPIWRITEBYTE("ULB_THRESHOLD_EXCEEDED_CNTR_REG", + ulbThresholdExceededCntrRegAddr, + ULB_THRESHOLD_EXCEEDED_CNTR_REG_VAL); + ADRV9025_SPIWRITEBYTE("AGC_ADC_HIGH_OVRG_EXCEEDED_CNTR_REG", + adcHighOvrgExceededCntrRegAddr, + AGC_ADC_HIGH_OVRG_EXCEEDED_CNTR_REG_VAL); + ADRV9025_SPIWRITEBYTE("AGC_GAIN_UPDATE_CNTR", + agcGainUpdateCntr1RegAddr, + agcGainUpdateCntr1RegVal); + ADRV9025_SPIWRITEBYTE("AGC_GAIN_UPDATE_CNTR", + agcGainUpdateCntr2RegAddr, + agcGainUpdateCntr2RegVal); + ADRV9025_SPIWRITEBYTE("AGC_GAIN_UPDATE_CNTR", + agcGainUpdateCntr3RegAddr, + agcGainUpdateCntr3RegVal); + ADRV9025_SPIWRITEBYTE("AGC_SLOWLOOP_SETTLING_DELAY_REG", + agcSlowLoopSettlingDelayRegAddr, + AGC_SLOWLOOP_SETTLING_DELAY_REG_VAL); + ADRV9025_SPIWRITEBYTE("DEC_OVERLOAD_CONFIG1_REG", + decOverloadConfig1RegAddr, + DEC_OVERLOAD_CONFIG1_REG_VAL); + ADRV9025_SPIWRITEBYTE("DEC_OVERLOAD_CONFIG2_REG", + decOverloadConfig2RegAddr, + DEC_OVERLOAD_CONFIG2_REG_VAL); + ADRV9025_SPIWRITEBYTE("DEC_OVERLOAD_UPPER_THRESHOLD1_REG", + decOverloadUpperThresh1RegAddr, + DEC_OVERLOAD_UPPER_THRESHOLD1_REG_VAL); + ADRV9025_SPIWRITEBYTE("DEC_OVERLOAD_UPPER_THRESHOLD2_REG", + decOverloadUpperThresh2RegAddr, + DEC_OVERLOAD_UPPER_THRESHOLD2_REG_VAL); + ADRV9025_SPIWRITEBYTE("ANALOG_RX_BLOCK_DET_ULBTH_REG", + analogRxBlockDetUlbthRegAddr, + ANALOG_RX_BLOCK_DET_ULBTH_REG_VAL); + ADRV9025_SPIWRITEBYTE("ANALOG_RX_BLOCK_DET_LLBTH_REG", + analogRxBlockDetLlbthRegAddr, + ANALOG_RX_BLOCK_DET_LLBTH_REG_VAL); + ADRV9025_SPIWRITEBYTE("SLOWLOOP_CONFIG_REG", + slowLoopConfigRegAddr, + SLOWLOOP_CONFIG_REG_VAL); /* Disables fast loop recovery so that the threshold exceeded cntr updates correctly */ + ADRV9025_SPIFIELDWRITE(device, + tiaValidOverrideRegAddr, + ADI_TRUE, + TIA_VALID_OVERRIDE_MASK, + TIA_VALID_OVERRIDE_SHIFT, + "TIA_VALID_OVERWRITE"); /* Set this bit to latch new threshold values */ + ADRV9025_SPIFIELDWRITE(device, + tiaValidOverrideRegAddr, + ADI_FALSE, + TIA_VALID_OVERRIDE_MASK, + TIA_VALID_OVERRIDE_SHIFT, + "TIA_VALID_OVERWRITE"); /* Clear this bit to latch new threshold values */ + + return (device->common.error.newAction); +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_radioctrl.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_radioctrl.c new file mode 100644 index 0000000..266853d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_radioctrl.c @@ -0,0 +1,2558 @@ +/** + * \file adrv9025_radioctrl.c + * \brief Contains ADRV9025 radio control related private function implementations + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "../devices/adrv9025/private/include/adrv9025_radioctrl.h" +#include "../devices/adrv9025/private/include/adrv9025_tx.h" +#include "../devices/adrv9025/private/include/adrv9025_rx.h" +#include "../devices/adrv9025/private/include/adrv9025_bf_tx.h" +#include "../devices/adrv9025/private/include/adrv9025_bf_rx.h" +#include "../devices/adrv9025/private/include/adrv9025_bf_core.h" +#include "../devices/adrv9025/private/include/adrv9025_cpu.h" +#include "../devices/adrv9025/private/include/adrv9025_cpu_macros.h" +#include "../../private/include/adrv9025_shared_resource_manager.h" +#include "adi_adrv9025_error.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_cpu.h" +#include "adi_adrv9025_gpio.h" + +int32_t adrv9025_TxEnableSet(adi_adrv9025_Device_t* device, + uint32_t txChannelMask) +{ + static const uint8_t TX_ENABLE = 1; + static const uint8_t TX_DISABLE = 0; + static const adi_adrv9025_TxChannels_e txChannelsArr[] = {ADI_ADRV9025_TX1, ADI_ADRV9025_TX2, ADI_ADRV9025_TX3, ADI_ADRV9025_TX4}; + static const uint32_t ALL_TX_CHANNELS = (uint32_t)(ADI_ADRV9025_TXALL); + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t channelIndex = 0; + uint8_t txEnable = 0; + adrv9025_BfTxChanAddr_e txChannelBitfieldAddr = (adrv9025_BfTxChanAddr_e)ADRV9025_ADDR_CH0_TX; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + if ((txChannelMask & ~ALL_TX_CHANNELS) != 0) + { + /* Tx channel selection is not valid */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannelMask, + "Invalid Tx channel selection, any combination of TxOff/Tx1/2/3/4 channels are valid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (channelIndex = 0; channelIndex < (sizeof(txChannelsArr) / sizeof(txChannelsArr[0])); channelIndex++) + { + if (((device->devStateInfo.initializedChannels >> ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET) & (uint32_t)txChannelsArr[channelIndex]) == 0) + { + continue; + } + + txChannelBitfieldAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + txChannelsArr[channelIndex]); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((txChannelMask & (uint32_t)txChannelsArr[channelIndex]) == (uint32_t)txChannelsArr[channelIndex]) + { + txEnable = TX_ENABLE; + } + else + { + txEnable = TX_DISABLE; + } + + recoveryAction = adrv9025_TxTxEnableBfSet(device, + txChannelBitfieldAddr, + txEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_RxEnableSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask) +{ + static const uint8_t RX_ENABLE = 1; + static const uint8_t RX_DISABLE = 0; + static const adi_adrv9025_RxChannels_e rxChannelsArr[] = {ADI_ADRV9025_RX1, ADI_ADRV9025_RX2, ADI_ADRV9025_RX3, ADI_ADRV9025_RX4}; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t channelIndex = 0; + uint8_t rxEnable = 0; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_RX_CH0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + for (channelIndex = 0; channelIndex < (sizeof(rxChannelsArr) / sizeof(rxChannelsArr[0])); channelIndex++) + { + if ((device->devStateInfo.initializedChannels & (uint32_t)rxChannelsArr[channelIndex]) != (uint32_t)rxChannelsArr[channelIndex]) + { + continue; + } + + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + rxChannelsArr[channelIndex], + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((rxChannelMask & (uint32_t)rxChannelsArr[channelIndex]) == (uint32_t)rxChannelsArr[channelIndex]) + { + rxEnable = RX_ENABLE; + } + else + { + rxEnable = RX_DISABLE; + } + + recoveryAction = adrv9025_RxRxEnableBfSet(device, + rxChannelBitfieldAddr, + rxEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_OrxEnableSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask) +{ + static const uint8_t ORX1_ENABLE = 0x01; + static const uint8_t ORX2_ENABLE = 0x02; + static const uint8_t ORX3_ENABLE = 0x04; + static const uint8_t ORX4_ENABLE = 0x08; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t orxEnable = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + if ((rxChannelMask & ADI_ADRV9025_ORX1) == ADI_ADRV9025_ORX1) + { + orxEnable |= ORX1_ENABLE; + } + + if ((rxChannelMask & ADI_ADRV9025_ORX2) == ADI_ADRV9025_ORX2) + { + orxEnable |= ORX2_ENABLE; + } + + if ((rxChannelMask & ADI_ADRV9025_ORX3) == ADI_ADRV9025_ORX3) + { + orxEnable |= ORX3_ENABLE; + } + + if ((rxChannelMask & ADI_ADRV9025_ORX4) == ADI_ADRV9025_ORX4) + { + orxEnable |= ORX4_ENABLE; + } + + recoveryAction = adrv9025_CoreOrxEnableBfSet(device, + ADRV9025_BF_CORE, + orxEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_TxEnableGet(adi_adrv9025_Device_t* device, + uint32_t* txChannelMask) +{ + static const adi_adrv9025_TxChannels_e txChannelsArr[] = {ADI_ADRV9025_TX1, ADI_ADRV9025_TX2, ADI_ADRV9025_TX3, ADI_ADRV9025_TX4}; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t channelIndex = 0; + uint8_t txEnable = 0; + adrv9025_BfTxChanAddr_e txChannelBitfieldAddr = (adrv9025_BfTxChanAddr_e)ADRV9025_ADDR_CH0_TX; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + txChannelMask); + + for (channelIndex = 0; channelIndex < (sizeof(txChannelsArr) / sizeof(txChannelsArr[0])); channelIndex++) + { + if (((device->devStateInfo.initializedChannels >> ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET) & (uint32_t)txChannelsArr[channelIndex]) != (uint32_t) + txChannelsArr[channelIndex]) + { + continue; + } + + txChannelBitfieldAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + (uint32_t)txChannelsArr[channelIndex]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxTxEnableBfGet(device, + txChannelBitfieldAddr, + &txEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (txEnable > 0) + { + *txChannelMask |= (uint32_t)txChannelsArr[channelIndex]; + } + else + { + *txChannelMask &= ~(uint32_t)txChannelsArr[channelIndex]; + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxEnableGet(adi_adrv9025_Device_t* device, + uint32_t* rxChannelMask) +{ + static const adi_adrv9025_RxChannels_e rxChannelsArr[] = {ADI_ADRV9025_RX1, ADI_ADRV9025_RX2, ADI_ADRV9025_RX3, ADI_ADRV9025_RX4}; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t channelIndex = 0; + uint8_t rxEnable = 0; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_RX_CH0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + for (channelIndex = 0; channelIndex < (sizeof(rxChannelsArr) / sizeof(rxChannelsArr[0])); channelIndex++) + { + if ((device->devStateInfo.initializedChannels & (uint32_t)rxChannelsArr[channelIndex]) == 0) + { + continue; + } + + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + rxChannelsArr[channelIndex], + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxRxEnableBfGet(device, + rxChannelBitfieldAddr, + &rxEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (rxEnable > 0) + { + *rxChannelMask |= (uint32_t)rxChannelsArr[channelIndex]; + } + else + { + *rxChannelMask &= ~(uint32_t)rxChannelsArr[channelIndex]; + } + } + + return recoveryAction; +} + +int32_t adrv9025_OrxEnableGet(adi_adrv9025_Device_t* device, + uint32_t* rxChannelMask) +{ + static const uint8_t ORX1_ENABLE = 0x01; + static const uint8_t ORX2_ENABLE = 0x02; + static const uint8_t ORX3_ENABLE = 0x04; + static const uint8_t ORX4_ENABLE = 0x08; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t orxEnable = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + recoveryAction = adrv9025_CoreOrxEnableBfGet(device, + ADRV9025_BF_CORE, + &orxEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + + //Update enable status of ORx1 + if ((orxEnable & ORX1_ENABLE) == ORX1_ENABLE) + { + *rxChannelMask |= ADI_ADRV9025_ORX1; + } + else + { + *rxChannelMask &= ~ADI_ADRV9025_ORX1; + } + + //Update enable status of ORx2 + if ((orxEnable & ORX2_ENABLE) == ORX2_ENABLE) + { + *rxChannelMask |= ADI_ADRV9025_ORX2; + } + else + { + *rxChannelMask &= ~ADI_ADRV9025_ORX2; + } + + //Update enable status of ORx3 + if ((orxEnable & ORX3_ENABLE) == ORX3_ENABLE) + { + *rxChannelMask |= ADI_ADRV9025_ORX3; + } + else + { + *rxChannelMask &= ~ADI_ADRV9025_ORX3; + } + + //Update enable status of ORx4 + if ((orxEnable & ORX4_ENABLE) == ORX4_ENABLE) + { + *rxChannelMask |= ADI_ADRV9025_ORX4; + } + else + { + *rxChannelMask &= ~ADI_ADRV9025_ORX4; + } + + return recoveryAction; +} + +int32_t adrv9025_PllUnlockGpInterruptMaskGet(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + uint8_t* pllGpInterruptPin0Mask, + uint8_t* pllGpInterruptPin1Mask) +{ + static const uint8_t PLL_LO1_GP_INTERRUPT_MASK = 0x80; + static const uint8_t PLL_LO2_GP_INTERRUPT_MASK = 0x40; + static const uint8_t PLL_AUX_GP_INTERRUPT_MASK = 0x20; + static const uint8_t PLL_LO1_GP_INTERRUPT_SHIFT = 7; + static const uint8_t PLL_LO2_GP_INTERRUPT_SHIFT = 6; + static const uint8_t PLL_AUX_GP_INTERRUPT_SHIFT = 5; + static const uint64_t PLL_GP_INTERRUPT_BYTE_MASK = 0x0000FF0000000000; + static const uint8_t PLL_GP_INTERRUPT_BYTE_SHIFT = 40; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint64_t gpInterruptPin0Mask = 0; + uint64_t gpInterruptPin1Mask = 0; + uint8_t pllGpInterruptPin0MaskByte = 0; + uint8_t pllGpInterruptPin1MaskByte = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + pllGpInterruptPin0Mask); + + ADI_NULL_PTR_RETURN(&device->common, + pllGpInterruptPin1Mask); + + /*Read GP Interrupt Pin0 and Pin1 mask*/ + recoveryAction = adrv9025_CoreGpInterruptsMaskPin0BfGet(device, + ADRV9025_BF_CORE, + &gpInterruptPin0Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpInterruptsMaskPin1BfGet(device, + ADRV9025_BF_CORE, + &gpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*PLL mask status is the 5th Byte*/ + pllGpInterruptPin0MaskByte = (uint8_t)((gpInterruptPin0Mask & PLL_GP_INTERRUPT_BYTE_MASK) >> PLL_GP_INTERRUPT_BYTE_SHIFT); + pllGpInterruptPin1MaskByte = (uint8_t)((gpInterruptPin1Mask & PLL_GP_INTERRUPT_BYTE_MASK) >> PLL_GP_INTERRUPT_BYTE_SHIFT); + + switch (pllName) + { + case(ADI_ADRV9025_LO1_PLL): + { + *pllGpInterruptPin0Mask = (pllGpInterruptPin0MaskByte & PLL_LO1_GP_INTERRUPT_MASK) >> PLL_LO1_GP_INTERRUPT_SHIFT; + *pllGpInterruptPin1Mask = (pllGpInterruptPin1MaskByte & PLL_LO1_GP_INTERRUPT_MASK) >> PLL_LO1_GP_INTERRUPT_SHIFT; + break; + } + case(ADI_ADRV9025_LO2_PLL): + { + *pllGpInterruptPin0Mask = (pllGpInterruptPin0MaskByte & PLL_LO2_GP_INTERRUPT_MASK) >> PLL_LO2_GP_INTERRUPT_SHIFT; + *pllGpInterruptPin1Mask = (pllGpInterruptPin1MaskByte & PLL_LO2_GP_INTERRUPT_MASK) >> PLL_LO2_GP_INTERRUPT_SHIFT; + break; + } + case(ADI_ADRV9025_AUX_PLL): + { + *pllGpInterruptPin0Mask = (pllGpInterruptPin0MaskByte & PLL_AUX_GP_INTERRUPT_MASK) >> PLL_AUX_GP_INTERRUPT_SHIFT; + *pllGpInterruptPin1Mask = (pllGpInterruptPin1MaskByte & PLL_AUX_GP_INTERRUPT_MASK) >> PLL_AUX_GP_INTERRUPT_SHIFT; + break; + } + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pllName, + "Invalid PLL encountered while attempting to retrieve PLL GP Interrupt mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_PllUnlockGpInterruptMaskSet(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + uint8_t pllGpInterruptPin0Mask, + uint8_t pllGpInterruptPin1Mask) +{ + static const uint8_t PLL_LO1_GP_INTERRUPT_MASK = 0x80; + static const uint8_t PLL_LO2_GP_INTERRUPT_MASK = 0x40; + static const uint8_t PLL_AUX_GP_INTERRUPT_MASK = 0x20; + static const uint8_t PLL_LO1_GP_INTERRUPT_SHIFT = 7; + static const uint8_t PLL_LO2_GP_INTERRUPT_SHIFT = 6; + static const uint8_t PLL_AUX_GP_INTERRUPT_SHIFT = 5; + static const uint64_t PLL_GP_INTERRUPT_BYTE_MASK = 0x0000FF0000000000; + static const uint8_t PLL_GP_INTERRUPT_BYTE_SHIFT = 40; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint64_t gpInterruptPin0Mask = 0; + uint64_t gpInterruptPin1Mask = 0; + uint8_t pllGpInterruptPin0MaskByte = 0; + uint8_t pllGpInterruptPin1MaskByte = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /*Read GP Interrupt Pin0 and Pin1 mask*/ + recoveryAction = adrv9025_CoreGpInterruptsMaskPin0BfGet(device, + ADRV9025_BF_CORE, + &gpInterruptPin0Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpInterruptsMaskPin1BfGet(device, + ADRV9025_BF_CORE, + &gpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*PLL mask status is the 5th Byte*/ + pllGpInterruptPin0MaskByte = (uint8_t)((gpInterruptPin0Mask & PLL_GP_INTERRUPT_BYTE_MASK) >> PLL_GP_INTERRUPT_BYTE_SHIFT); + pllGpInterruptPin1MaskByte = (uint8_t)((gpInterruptPin1Mask & PLL_GP_INTERRUPT_BYTE_MASK) >> PLL_GP_INTERRUPT_BYTE_SHIFT); + + /*Clear Byte 5 of the GP Interrupt Mask*/ + gpInterruptPin0Mask &= ~PLL_GP_INTERRUPT_BYTE_MASK; + gpInterruptPin1Mask &= ~PLL_GP_INTERRUPT_BYTE_MASK; + + switch (pllName) + { + case(ADI_ADRV9025_LO1_PLL): + { + /*Clear LO1 Interrupt Mask bit in GP Interrupt byte5*/ + pllGpInterruptPin0MaskByte &= ~PLL_LO1_GP_INTERRUPT_MASK; + pllGpInterruptPin1MaskByte &= ~PLL_LO1_GP_INTERRUPT_MASK; + + /*Update PLL GP Interrupt Byte*/ + pllGpInterruptPin0MaskByte |= (pllGpInterruptPin0Mask << PLL_LO1_GP_INTERRUPT_SHIFT); + pllGpInterruptPin1MaskByte |= (pllGpInterruptPin1Mask << PLL_LO1_GP_INTERRUPT_SHIFT); + + break; + } + case(ADI_ADRV9025_LO2_PLL): + { + /*Clear LO2 Interrupt Mask bit in GP Interrupt byte5*/ + pllGpInterruptPin0MaskByte &= ~PLL_LO2_GP_INTERRUPT_MASK; + pllGpInterruptPin1MaskByte &= ~PLL_LO2_GP_INTERRUPT_MASK; + + /*Update PLL GP Interrupt Byte*/ + pllGpInterruptPin0MaskByte |= (pllGpInterruptPin0Mask << PLL_LO2_GP_INTERRUPT_SHIFT); + pllGpInterruptPin1MaskByte |= (pllGpInterruptPin1Mask << PLL_LO2_GP_INTERRUPT_SHIFT); + + break; + } + case(ADI_ADRV9025_AUX_PLL): + { + /*Clear Aux PLL Interrupt Mask bit in GP Interrupt byte5*/ + pllGpInterruptPin0MaskByte &= ~PLL_AUX_GP_INTERRUPT_MASK; + pllGpInterruptPin1MaskByte &= ~PLL_AUX_GP_INTERRUPT_MASK; + + /*Update PLL GP Interrupt Byte*/ + pllGpInterruptPin0MaskByte |= (pllGpInterruptPin0Mask << PLL_AUX_GP_INTERRUPT_SHIFT); + pllGpInterruptPin1MaskByte |= (pllGpInterruptPin1Mask << PLL_AUX_GP_INTERRUPT_SHIFT); + + break; + } + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pllName, + "Invalid PLL encountered while attempting to set PLL GP Interrupt mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Update GP Interrupt Mask Byte 5*/ + gpInterruptPin0Mask |= ((uint64_t)pllGpInterruptPin0MaskByte << PLL_GP_INTERRUPT_BYTE_SHIFT); + gpInterruptPin1Mask |= ((uint64_t)pllGpInterruptPin1MaskByte << PLL_GP_INTERRUPT_BYTE_SHIFT); + + /*Write GP Interrupt Pin0 and Pin1 mask*/ + recoveryAction = adrv9025_CoreGpInterruptsMaskPin0BfSet(device, + ADRV9025_BF_CORE, + gpInterruptPin0Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpInterruptsMaskPin1BfSet(device, + ADRV9025_BF_CORE, + gpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_PllOverrangeGpInterruptMaskGet(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + uint8_t* pllGpInterruptPin0Mask, + uint8_t* pllGpInterruptPin1Mask) +{ + static const uint8_t PLL_LO1_GP_INTERRUPT_MASK = 0x08; + static const uint8_t PLL_LO2_GP_INTERRUPT_MASK = 0x04; + static const uint8_t PLL_AUX_GP_INTERRUPT_MASK = 0x02; + static const uint8_t PLL_LO1_GP_INTERRUPT_SHIFT = 3; + static const uint8_t PLL_LO2_GP_INTERRUPT_SHIFT = 2; + static const uint8_t PLL_AUX_GP_INTERRUPT_SHIFT = 1; + static const uint64_t PLL_GP_INTERRUPT_BYTE_MASK = 0x0000FF0000000000; + static const uint8_t PLL_GP_INTERRUPT_BYTE_SHIFT = 40; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint64_t gpInterruptPin0Mask = 0; + uint64_t gpInterruptPin1Mask = 0; + uint8_t pllGpInterruptPin0MaskByte = 0; + uint8_t pllGpInterruptPin1MaskByte = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + pllGpInterruptPin0Mask); + + ADI_NULL_PTR_RETURN(&device->common, + pllGpInterruptPin1Mask); + + /*Read GP Interrupt Pin0 and Pin1 mask*/ + recoveryAction = adrv9025_CoreGpInterruptsMaskPin0BfGet(device, + ADRV9025_BF_CORE, + &gpInterruptPin0Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpInterruptsMaskPin1BfGet(device, + ADRV9025_BF_CORE, + &gpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*PLL mask status is the 5th Byte*/ + pllGpInterruptPin0MaskByte = (uint8_t)((gpInterruptPin0Mask & PLL_GP_INTERRUPT_BYTE_MASK) >> PLL_GP_INTERRUPT_BYTE_SHIFT); + pllGpInterruptPin1MaskByte = (uint8_t)((gpInterruptPin1Mask & PLL_GP_INTERRUPT_BYTE_MASK) >> PLL_GP_INTERRUPT_BYTE_SHIFT); + + switch (pllName) + { + case(ADI_ADRV9025_LO1_PLL): + { + *pllGpInterruptPin0Mask = (pllGpInterruptPin0MaskByte & PLL_LO1_GP_INTERRUPT_MASK) >> PLL_LO1_GP_INTERRUPT_SHIFT; + *pllGpInterruptPin1Mask = (pllGpInterruptPin1MaskByte & PLL_LO1_GP_INTERRUPT_MASK) >> PLL_LO1_GP_INTERRUPT_SHIFT; + break; + } + case(ADI_ADRV9025_LO2_PLL): + { + *pllGpInterruptPin0Mask = (pllGpInterruptPin0MaskByte & PLL_LO2_GP_INTERRUPT_MASK) >> PLL_LO2_GP_INTERRUPT_SHIFT; + *pllGpInterruptPin1Mask = (pllGpInterruptPin1MaskByte & PLL_LO2_GP_INTERRUPT_MASK) >> PLL_LO2_GP_INTERRUPT_SHIFT; + break; + } + case(ADI_ADRV9025_AUX_PLL): + { + *pllGpInterruptPin0Mask = (pllGpInterruptPin0MaskByte & PLL_AUX_GP_INTERRUPT_MASK) >> PLL_AUX_GP_INTERRUPT_SHIFT; + *pllGpInterruptPin1Mask = (pllGpInterruptPin1MaskByte & PLL_AUX_GP_INTERRUPT_MASK) >> PLL_AUX_GP_INTERRUPT_SHIFT; + break; + } + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pllName, + "Invalid PLL encountered while attempting to retrieve PLL overrange GP Interrupt mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_PllOverrangeGpInterruptMaskSet(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + uint8_t pllGpInterruptPin0Mask, + uint8_t pllGpInterruptPin1Mask) +{ + static const uint8_t PLL_LO1_GP_INTERRUPT_MASK = 0x08; + static const uint8_t PLL_LO2_GP_INTERRUPT_MASK = 0x04; + static const uint8_t PLL_AUX_GP_INTERRUPT_MASK = 0x02; + static const uint8_t PLL_LO1_GP_INTERRUPT_SHIFT = 3; + static const uint8_t PLL_LO2_GP_INTERRUPT_SHIFT = 2; + static const uint8_t PLL_AUX_GP_INTERRUPT_SHIFT = 1; + static const uint64_t PLL_GP_INTERRUPT_BYTE_MASK = 0x0000FF0000000000; + static const uint8_t PLL_GP_INTERRUPT_BYTE_SHIFT = 40; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint64_t gpInterruptPin0Mask = 0; + uint64_t gpInterruptPin1Mask = 0; + uint8_t pllGpInterruptPin0MaskByte = 0; + uint8_t pllGpInterruptPin1MaskByte = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /*Read GP Interrupt Pin0 and Pin1 mask*/ + recoveryAction = adrv9025_CoreGpInterruptsMaskPin0BfGet(device, + ADRV9025_BF_CORE, + &gpInterruptPin0Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpInterruptsMaskPin1BfGet(device, + ADRV9025_BF_CORE, + &gpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*PLL mask status is the 5th Byte*/ + pllGpInterruptPin0MaskByte = (uint8_t)((gpInterruptPin0Mask & PLL_GP_INTERRUPT_BYTE_MASK) >> PLL_GP_INTERRUPT_BYTE_SHIFT); + pllGpInterruptPin1MaskByte = (uint8_t)((gpInterruptPin1Mask & PLL_GP_INTERRUPT_BYTE_MASK) >> PLL_GP_INTERRUPT_BYTE_SHIFT); + + /*Clear Byte 5 of the GP Interrupt Mask*/ + gpInterruptPin0Mask &= ~PLL_GP_INTERRUPT_BYTE_MASK; + gpInterruptPin1Mask &= ~PLL_GP_INTERRUPT_BYTE_MASK; + + switch (pllName) + { + case(ADI_ADRV9025_LO1_PLL): + { + /*Clear LO1 Interrupt Mask bit in GP Interrupt byte5*/ + pllGpInterruptPin0MaskByte &= ~PLL_LO1_GP_INTERRUPT_MASK; + pllGpInterruptPin1MaskByte &= ~PLL_LO1_GP_INTERRUPT_MASK; + + /*Update PLL GP Interrupt Byte*/ + pllGpInterruptPin0MaskByte |= (pllGpInterruptPin0Mask << PLL_LO1_GP_INTERRUPT_SHIFT); + pllGpInterruptPin1MaskByte |= (pllGpInterruptPin1Mask << PLL_LO1_GP_INTERRUPT_SHIFT); + + break; + } + case(ADI_ADRV9025_LO2_PLL): + { + /*Clear LO2 Interrupt Mask bit in GP Interrupt byte5*/ + pllGpInterruptPin0MaskByte &= ~PLL_LO2_GP_INTERRUPT_MASK; + pllGpInterruptPin1MaskByte &= ~PLL_LO2_GP_INTERRUPT_MASK; + + /*Update PLL GP Interrupt Byte*/ + pllGpInterruptPin0MaskByte |= (pllGpInterruptPin0Mask << PLL_LO2_GP_INTERRUPT_SHIFT); + pllGpInterruptPin1MaskByte |= (pllGpInterruptPin1Mask << PLL_LO2_GP_INTERRUPT_SHIFT); + + break; + } + case(ADI_ADRV9025_AUX_PLL): + { + /*Clear Aux PLL Interrupt Mask bit in GP Interrupt byte5*/ + pllGpInterruptPin0MaskByte &= ~PLL_AUX_GP_INTERRUPT_MASK; + pllGpInterruptPin1MaskByte &= ~PLL_AUX_GP_INTERRUPT_MASK; + + /*Update PLL GP Interrupt Byte*/ + pllGpInterruptPin0MaskByte |= (pllGpInterruptPin0Mask << PLL_AUX_GP_INTERRUPT_SHIFT); + pllGpInterruptPin1MaskByte |= (pllGpInterruptPin1Mask << PLL_AUX_GP_INTERRUPT_SHIFT); + + break; + } + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pllName, + "Invalid PLL encountered while attempting to set PLL overrange GP Interrupt mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Update GP Interrupt Mask Byte 5*/ + gpInterruptPin0Mask |= ((uint64_t)pllGpInterruptPin0MaskByte << PLL_GP_INTERRUPT_BYTE_SHIFT); + gpInterruptPin1Mask |= ((uint64_t)pllGpInterruptPin1MaskByte << PLL_GP_INTERRUPT_BYTE_SHIFT); + + /*Write GP Interrupt Pin0 and Pin1 mask*/ + recoveryAction = adrv9025_CoreGpInterruptsMaskPin0BfSet(device, + ADRV9025_BF_CORE, + gpInterruptPin0Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpInterruptsMaskPin1BfSet(device, + ADRV9025_BF_CORE, + gpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_RxRadioCtrlCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxRadioCtrlModeCfg_t* rxRadioCtrlModeCfg) +{ + static const uint8_t RX_PIN_MODE_ENABLE = 1; + static const uint8_t RX_PIN_MODE_DISABLE = 0; + static const uint8_t ARM_OVERRIDE_CTRL_DISABLE = 0; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxChannelIndex = 0; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_RX_CH0; + adi_adrv9025_RxChannels_e rxChannelArr[] = {ADI_ADRV9025_RX1, ADI_ADRV9025_RX2, ADI_ADRV9025_RX3, ADI_ADRV9025_RX4}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + rxRadioCtrlModeCfg); + + for (rxChannelIndex = 0; rxChannelIndex < (sizeof(rxChannelArr) / sizeof(rxChannelArr[0])); rxChannelIndex++) + { + if ((rxRadioCtrlModeCfg->rxChannelMask & rxChannelArr[rxChannelIndex]) == rxChannelArr[rxChannelIndex]) + { + /*Retrieve Rx Channel Bitfield Address*/ + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + rxChannelArr[rxChannelIndex], + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*For Non-pin mode set Pin Mode bitfield to 0 and for pin mode set the Pin mode bitfield to 1*/ + if (rxRadioCtrlModeCfg->rxEnableMode == ADI_ADRV9025_RX_EN_SPI_MODE) + { + /* Disable ARM override ctrl for Rx ctrl configuration */ + recoveryAction = adrv9025_RxArmOverrideControlBfSet(device, + rxChannelBitfieldAddr, + ARM_OVERRIDE_CTRL_DISABLE); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Disable Pin ctrl mode */ + recoveryAction = adrv9025_RxRxPinModeBfSet(device, + rxChannelBitfieldAddr, + RX_PIN_MODE_DISABLE); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (rxRadioCtrlModeCfg->rxEnableMode == ADI_ADRV9025_RX_EN_PIN_MODE) + { + /* Disable ARM override ctrl for Rx ctrl configuration */ + recoveryAction = adrv9025_RxArmOverrideControlBfSet(device, + rxChannelBitfieldAddr, + ARM_OVERRIDE_CTRL_DISABLE); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Enable Pin ctrl mode */ + recoveryAction = adrv9025_RxRxPinModeBfSet(device, + rxChannelBitfieldAddr, + RX_PIN_MODE_ENABLE); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxRadioCtrlModeCfg->rxEnableMode, + "Invalid Rx Enable Mode encountered while attempting to configure Rx radio ctrl configuration settings"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return recoveryAction; +} + +int32_t adrv9025_TxRadioCtrlCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxRadioCtrlModeCfg_t* txRadioCtrlModeCfg) +{ + static const uint8_t TX_PIN_MODE_ENABLE = 1; + static const uint8_t TX_PIN_MODE_DISABLE = 0; + static const uint8_t ARM_OVERRIDE_CTRL_DISABLE = 0; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t txChannelIndex = 0; + adrv9025_BfTxChanAddr_e txChannelBitfieldAddr = ADRV9025_BF_TX_CH0; + adi_adrv9025_TxChannels_e txChannelArr[] = {ADI_ADRV9025_TX1, ADI_ADRV9025_TX2, ADI_ADRV9025_TX3, ADI_ADRV9025_TX4}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + txRadioCtrlModeCfg); + + for (txChannelIndex = 0; txChannelIndex < (sizeof(txChannelArr) / sizeof(txChannelArr[0])); txChannelIndex++) + { + if ((txRadioCtrlModeCfg->txChannelMask & txChannelArr[txChannelIndex]) == txChannelArr[txChannelIndex]) + { + /*Retrieve Tx Channel Bitfield Address*/ + txChannelBitfieldAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + (uint32_t)txChannelArr[txChannelIndex]); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*For Non-pin mode set Pin Mode bitfield to 0 and for pin mode set the Pin mode bitfield to 1*/ + if (txRadioCtrlModeCfg->txEnableMode == ADI_ADRV9025_TX_EN_SPI_MODE) + { + /* Disable ARM override ctrl for Tx ctrl configuration */ + recoveryAction = adrv9025_TxArmOverrideControlBfSet(device, + txChannelBitfieldAddr, + ARM_OVERRIDE_CTRL_DISABLE); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Disable Pin Mode ctrl */ + recoveryAction = adrv9025_TxTxPinModeBfSet(device, + txChannelBitfieldAddr, + TX_PIN_MODE_DISABLE); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (txRadioCtrlModeCfg->txEnableMode == ADI_ADRV9025_TX_EN_PIN_MODE) + { + /* Disable ARM override ctrl for Tx ctrl configuration */ + recoveryAction = adrv9025_TxArmOverrideControlBfSet(device, + txChannelBitfieldAddr, + ARM_OVERRIDE_CTRL_DISABLE); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Enable pin mode ctrl */ + recoveryAction = adrv9025_TxTxPinModeBfSet(device, + txChannelBitfieldAddr, + TX_PIN_MODE_ENABLE); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txRadioCtrlModeCfg->txEnableMode, + "Invalid Tx Enable Mode encountered while attempting to configure Tx radio ctrl configuration settings"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return recoveryAction; +} + +int32_t adrv9025_OrxRadioCtrlCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_ORxRadioCtrlModeCfg_t* orxRadioCtrlModeCfg) +{ + static const uint8_t ORX_PIN_MODE_ENABLE = 1; + static const uint8_t ORX_PIN_MODE_DISABLE = 0; + static const uint8_t ORX_SINGLE_CH_PIN_MODE_ENABLE = 1; + static const uint8_t ORX_SINGLE_CH_PIN_MODE_DISABLE = 0; + static const uint8_t ORX_SINGLE_CH_PIN_MODE1A_ENABLE = 1; + static const uint8_t ORX_SINGLE_CH_PIN_MODE1A_DISABLE = 0; + static const uint8_t ORX_PIN_MODE_USING_SPI_SELECT_ENABLE = 1; + static const uint8_t ORX_PIN_MODE_USING_SPI_SELECT_DISABLE = 0; + static const uint8_t ARM_OVERRIDE_CTRL_DISABLE = 0; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + orxRadioCtrlModeCfg); + + if (orxRadioCtrlModeCfg->orxEnableMode == ADI_ADRV9025_ORX_EN_SPI_MODE) + { + recoveryAction = adrv9025_CoreArmOverrideControlBfSet(device, + ADRV9025_BF_CORE, + ARM_OVERRIDE_CTRL_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxPinModeEnableBfSet(device, + ADRV9025_BF_CORE, + ORX_PIN_MODE_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (orxRadioCtrlModeCfg->orxEnableMode == ADI_ADRV9025_ORX_EN_SINGLE_CH_3PIN_MODE) + { + recoveryAction = adrv9025_CoreArmOverrideControlBfSet(device, + ADRV9025_BF_CORE, + ARM_OVERRIDE_CTRL_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxPinModeEnableBfSet(device, + ADRV9025_BF_CORE, + ORX_PIN_MODE_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSingleChannelMode1aBfSet(device, + ADRV9025_BF_CORE, + ORX_SINGLE_CH_PIN_MODE1A_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSingleChannelModeBfSet(device, + ADRV9025_BF_CORE, + ORX_SINGLE_CH_PIN_MODE_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxPinModeUsingSpiSelectBfSet(device, + ADRV9025_BF_CORE, + ORX_PIN_MODE_USING_SPI_SELECT_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CorePinSelectSettlingDelayBfSet(device, + ADRV9025_BF_CORE, + orxRadioCtrlModeCfg->orxPinSelectSettlingDelay_armClkCycles); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (orxRadioCtrlModeCfg->orxEnableMode == ADI_ADRV9025_ORX_EN_SINGLE_CH_2PIN_MODE) + { + recoveryAction = adrv9025_CoreArmOverrideControlBfSet(device, + ADRV9025_BF_CORE, + ARM_OVERRIDE_CTRL_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxPinModeEnableBfSet(device, + ADRV9025_BF_CORE, + ORX_PIN_MODE_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSingleChannelMode1aBfSet(device, + ADRV9025_BF_CORE, + ORX_SINGLE_CH_PIN_MODE1A_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSingleChannelModeBfSet(device, + ADRV9025_BF_CORE, + ORX_SINGLE_CH_PIN_MODE_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxPinModeUsingSpiSelectBfSet(device, + ADRV9025_BF_CORE, + ORX_PIN_MODE_USING_SPI_SELECT_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSingleChannelMode1aLowChannelEnableBfSet(device, + ADRV9025_BF_CORE, + (uint8_t)orxRadioCtrlModeCfg->singleChannel2PinModeLowOrxSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSingleChannelMode1aHighChannelEnableBfSet(device, + ADRV9025_BF_CORE, + (uint8_t)orxRadioCtrlModeCfg->singleChannel2PinModeHighOrxSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CorePinSelectSettlingDelayBfSet(device, + ADRV9025_BF_CORE, + orxRadioCtrlModeCfg->orxPinSelectSettlingDelay_armClkCycles); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (orxRadioCtrlModeCfg->orxEnableMode == ADI_ADRV9025_ORX_EN_SINGLE_CH_1PIN_MODE) + { + recoveryAction = adrv9025_CoreArmOverrideControlBfSet(device, + ADRV9025_BF_CORE, + ARM_OVERRIDE_CTRL_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxPinModeEnableBfSet(device, + ADRV9025_BF_CORE, + ORX_PIN_MODE_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSingleChannelMode1aBfSet(device, + ADRV9025_BF_CORE, + ORX_SINGLE_CH_PIN_MODE1A_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSingleChannelModeBfSet(device, + ADRV9025_BF_CORE, + ORX_SINGLE_CH_PIN_MODE_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxPinModeUsingSpiSelectBfSet(device, + ADRV9025_BF_CORE, + ORX_PIN_MODE_USING_SPI_SELECT_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSelectInPinModeBfSet(device, + ADRV9025_BF_CORE, + (uint8_t)orxRadioCtrlModeCfg->singleChannel1PinModeOrxSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CorePinSelectSettlingDelayBfSet(device, + ADRV9025_BF_CORE, + orxRadioCtrlModeCfg->orxPinSelectSettlingDelay_armClkCycles); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (orxRadioCtrlModeCfg->orxEnableMode == ADI_ADRV9025_ORX_EN_DUAL_CH_4PIN_MODE) + { + recoveryAction = adrv9025_CoreArmOverrideControlBfSet(device, + ADRV9025_BF_CORE, + ARM_OVERRIDE_CTRL_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxPinModeEnableBfSet(device, + ADRV9025_BF_CORE, + ORX_PIN_MODE_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSingleChannelMode1aBfSet(device, + ADRV9025_BF_CORE, + ORX_SINGLE_CH_PIN_MODE1A_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSingleChannelModeBfSet(device, + ADRV9025_BF_CORE, + ORX_SINGLE_CH_PIN_MODE_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxPinModeUsingSpiSelectBfSet(device, + ADRV9025_BF_CORE, + ORX_PIN_MODE_USING_SPI_SELECT_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CorePinSelectSettlingDelayBfSet(device, + ADRV9025_BF_CORE, + orxRadioCtrlModeCfg->orxPinSelectSettlingDelay_armClkCycles); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (orxRadioCtrlModeCfg->orxEnableMode == ADI_ADRV9025_ORX_EN_DUAL_CH_2PIN_MODE) + { + recoveryAction = adrv9025_CoreArmOverrideControlBfSet(device, + ADRV9025_BF_CORE, + ARM_OVERRIDE_CTRL_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxPinModeEnableBfSet(device, + ADRV9025_BF_CORE, + ORX_PIN_MODE_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSingleChannelMode1aBfSet(device, + ADRV9025_BF_CORE, + ORX_SINGLE_CH_PIN_MODE1A_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSingleChannelModeBfSet(device, + ADRV9025_BF_CORE, + ORX_SINGLE_CH_PIN_MODE_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxPinModeUsingSpiSelectBfSet(device, + ADRV9025_BF_CORE, + ORX_PIN_MODE_USING_SPI_SELECT_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSelectInPinModeBfSet(device, + ADRV9025_BF_CORE, + (uint8_t)orxRadioCtrlModeCfg->dualChannel2PinModeOrxSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CorePinSelectSettlingDelayBfSet(device, + ADRV9025_BF_CORE, + orxRadioCtrlModeCfg->orxPinSelectSettlingDelay_armClkCycles); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + orxRadioCtrlModeCfg->orxEnableMode, + "Invalid ORx Enable Mode encountered while attempting to configure ORx radio ctrl configuration settings"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_RxRadioCtrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxRadioCtrlModeCfg_t* rxRadioCtrlModeCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxChannelIndex = 0; + uint8_t rxEnableMode = (uint8_t)ADI_ADRV9025_RX_EN_INVALID_MODE; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_RX_CH0; + uint8_t armOverrideCtrl = 0; + adi_adrv9025_RxChannels_e rxChannelArr[] = {ADI_ADRV9025_RX1, ADI_ADRV9025_RX2, ADI_ADRV9025_RX3, ADI_ADRV9025_RX4}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + rxRadioCtrlModeCfg); + + rxRadioCtrlModeCfg->rxChannelMask = 0; + + for (rxChannelIndex = 0; rxChannelIndex < (sizeof(rxChannelArr) / sizeof(rxChannelArr[0])); rxChannelIndex++) + { + if ((rxChannel & rxChannelArr[rxChannelIndex]) == rxChannelArr[rxChannelIndex]) + { + /*Retrieve Rx Channel Bitfield Address*/ + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + rxChannelArr[rxChannelIndex], + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Read ARM Override ctrl bitfield*/ + recoveryAction = adrv9025_RxArmOverrideControlBfGet(device, + rxChannelBitfieldAddr, + &armOverrideCtrl); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* The pin mode bitfield is only valid if ARM override ctrl is not set to 1 */ + if (armOverrideCtrl == 0) + { + /*For Non-pin mode Pin Mode bitfield is set to 0 and for pin mode the 'Pin mode' bitfield is set to 1*/ + recoveryAction = adrv9025_RxRxPinModeBfGet(device, + rxChannelBitfieldAddr, + &rxEnableMode); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Update the Rx channel mask*/ + rxRadioCtrlModeCfg->rxChannelMask |= rxChannel; + + break; + } + } + + /*Update the enable mode struct member*/ + rxRadioCtrlModeCfg->rxEnableMode = (adi_adrv9025_RxEnableMode_e)rxEnableMode; + + return recoveryAction; +} + +int32_t adrv9025_TxRadioCtrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxRadioCtrlModeCfg_t* txRadioCtrlModeCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t txChannelIndex = 0; + uint8_t armOverrideCtrl = 0; + uint8_t txEnableMode = (uint8_t)ADI_ADRV9025_TX_EN_INVALID_MODE; + adrv9025_BfTxChanAddr_e txChannelBitfieldAddr = ADRV9025_BF_TX_CH0; + adi_adrv9025_TxChannels_e txChannelArr[] = {ADI_ADRV9025_TX1, ADI_ADRV9025_TX2, ADI_ADRV9025_TX3, ADI_ADRV9025_TX4}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + txRadioCtrlModeCfg); + + txRadioCtrlModeCfg->txChannelMask = 0; + + for (txChannelIndex = 0; txChannelIndex < (sizeof(txChannelArr) / sizeof(txChannelArr[0])); txChannelIndex++) + { + if ((txChannel & txChannelArr[txChannelIndex]) == txChannelArr[txChannelIndex]) + { + /*Retrieve Tx Channel Bitfield Address*/ + txChannelBitfieldAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + (uint32_t)txChannelArr[txChannelIndex]); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Read ARM Override ctrl bitfield*/ + recoveryAction = adrv9025_TxArmOverrideControlBfGet(device, + txChannelBitfieldAddr, + &armOverrideCtrl); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* The pin mode bitfield is only valid if ARM override ctrl is not set to 1 */ + if (armOverrideCtrl == 0) + { + /*For Non-pin mode Pin Mode bitfield is set to 0 and for pin mode the 'Pin mode' bitfield is set to 1*/ + recoveryAction = adrv9025_TxTxPinModeBfGet(device, + txChannelBitfieldAddr, + &txEnableMode); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Update the Rx channel mask*/ + txRadioCtrlModeCfg->txChannelMask |= txChannel; + + break; + } + } + + /*Update the enable mode struct member*/ + txRadioCtrlModeCfg->txEnableMode = (adi_adrv9025_TxEnableMode_e)txEnableMode; + + return recoveryAction; +} + +int32_t adrv9025_OrxRadioCtrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_ORxRadioCtrlModeCfg_t* orxRadioCtrlModeCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t singleChannelPinModeSel = 0; + uint8_t singleChannelPinMode1aSel = 0; + uint8_t orxPinModeSel = 0; + uint8_t armOverrideCtrl = 0; + uint8_t orxPinModeUsingSpiSelect = 0; + uint8_t singleChannel1PinModeOrxSel = (uint8_t)ADI_ADRV9025_SINGLE_CH_PIN_MODE_INVALID_ORX_SEL; + uint8_t singleChannel2PinModeHighOrxSel = (uint8_t)ADI_ADRV9025_SINGLE_CH_PIN_MODE_INVALID_ORX_SEL; + uint8_t singleChannel2PinModeLowOrxSel = (uint8_t)ADI_ADRV9025_SINGLE_CH_PIN_MODE_INVALID_ORX_SEL; + uint8_t dualChannel2PinModeOrxSel = (uint8_t)ADI_ADRV9025_DUAL_CH_PIN_MODE_INVALID_ORX_SEL; + adi_adrv9025_ORxEnableMode_e orxEnableMode = ADI_ADRV9025_ORX_EN_INVALID_MODE; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + orxRadioCtrlModeCfg); + + recoveryAction = adrv9025_CoreArmOverrideControlBfGet(device, + ADRV9025_BF_CORE, + &armOverrideCtrl); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxPinModeEnableBfGet(device, + ADRV9025_BF_CORE, + &orxPinModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSingleChannelModeBfGet(device, + ADRV9025_BF_CORE, + &singleChannelPinModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSingleChannelMode1aBfGet(device, + ADRV9025_BF_CORE, + &singleChannelPinMode1aSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxPinModeUsingSpiSelectBfGet(device, + ADRV9025_BF_CORE, + &orxPinModeUsingSpiSelect); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (armOverrideCtrl == 1) + { + orxEnableMode = ADI_ADRV9025_ORX_EN_INVALID_MODE; + } + else + { + if (orxPinModeSel == 0) + { + orxEnableMode = ADI_ADRV9025_ORX_EN_SPI_MODE; + } + else + { + if ((singleChannelPinModeSel == 1) && + (singleChannelPinMode1aSel == 0) && + (orxPinModeUsingSpiSelect == 0)) + { + orxEnableMode = ADI_ADRV9025_ORX_EN_SINGLE_CH_3PIN_MODE; + } + else if ((singleChannelPinModeSel == 1) && + (singleChannelPinMode1aSel == 0) && + (orxPinModeUsingSpiSelect == 1)) + { + orxEnableMode = ADI_ADRV9025_ORX_EN_SINGLE_CH_1PIN_MODE; + + recoveryAction = adrv9025_CoreOrxSelectInPinModeBfGet(device, + ADRV9025_BF_CORE, + &singleChannel1PinModeOrxSel); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if ((singleChannelPinModeSel == 1) && + (singleChannelPinMode1aSel == 1) && + (orxPinModeUsingSpiSelect == 0)) + { + orxEnableMode = ADI_ADRV9025_ORX_EN_SINGLE_CH_2PIN_MODE; + + recoveryAction = adrv9025_CoreOrxSingleChannelMode1aHighChannelEnableBfGet(device, + ADRV9025_BF_CORE, + &singleChannel2PinModeHighOrxSel); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreOrxSingleChannelMode1aLowChannelEnableBfGet(device, + ADRV9025_BF_CORE, + &singleChannel2PinModeLowOrxSel); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if ((singleChannelPinModeSel == 0) && + (singleChannelPinMode1aSel == 0) && + (orxPinModeUsingSpiSelect == 1)) + { + orxEnableMode = ADI_ADRV9025_ORX_EN_DUAL_CH_2PIN_MODE; + + recoveryAction = adrv9025_CoreOrxSelectInPinModeBfGet(device, + ADRV9025_BF_CORE, + &dualChannel2PinModeOrxSel); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if ((singleChannelPinModeSel == 0) && + (singleChannelPinMode1aSel == 0) && + (orxPinModeUsingSpiSelect == 0)) + { + orxEnableMode = ADI_ADRV9025_ORX_EN_DUAL_CH_4PIN_MODE; + } + } + } + + /* Update the orxRadioCtrlModeCfg structure members with readback/decoded values */ + recoveryAction = adrv9025_CorePinSelectSettlingDelayBfGet(device, + ADRV9025_BF_CORE, + &orxRadioCtrlModeCfg->orxPinSelectSettlingDelay_armClkCycles); + ADI_ERROR_RETURN(device->common.error.newAction); + + orxRadioCtrlModeCfg->orxEnableMode = orxEnableMode; + orxRadioCtrlModeCfg->singleChannel1PinModeOrxSel = (adi_adrv9025_SingleChannelPinModeOrxSel_e)singleChannel1PinModeOrxSel; + orxRadioCtrlModeCfg->singleChannel2PinModeHighOrxSel = (adi_adrv9025_SingleChannelPinModeOrxSel_e)singleChannel2PinModeHighOrxSel; + orxRadioCtrlModeCfg->singleChannel2PinModeLowOrxSel = (adi_adrv9025_SingleChannelPinModeOrxSel_e)singleChannel2PinModeLowOrxSel; + orxRadioCtrlModeCfg->dualChannel2PinModeOrxSel = (adi_adrv9025_DualChannelPinModeOrxSel_e)dualChannel2PinModeOrxSel; + + return recoveryAction; +} + +int32_t adrv9025_ArmGpioPinSet(adi_adrv9025_Device_t* device, + uint8_t signalId, + adi_adrv9025_ArmGpioPinCfg_t* armGpioPin) +{ +#define NUM_GPIOS_PER_CMD 1U + static const uint8_t GPIO_ENABLE = 0x80; + static const uint8_t GPIO_DISABLE = 0x00; + static const uint8_t GPIO_POLARITY_NORMAL = 0x00; + static const uint8_t GPIO_POLARITY_INVERTED = 0x20; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t resourceAcqReleaseStatus = ADI_FAILURE; + adi_adrv9025_GpioPinSel_e currentGpioPinSel = ADI_ADRV9025_GPIO_INVALID; + int32_t sharedResourceArr[NUM_GPIOS_PER_CMD] = {0}; + uint32_t gpioPinMask = 0; + uint8_t extData[3] = {0}; + uint8_t cmdStatusByte = 0; + int32_t errHdl = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + armGpioPin); + + /* Retrieve the currently assigned GPIO */ + recoveryAction = adrv9025_ArmGpioPinGet(device, + signalId, + ¤tGpioPinSel); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Disassociate currently assigned GPIO to the signal and release the shared resource */ + if (currentGpioPinSel < ADI_ADRV9025_GPIO_INVALID) + { + /* Command ARM to disassociate the currently assigned GPIO for the requested signal ID */ + extData[0] = ADRV9025_CPU_OBJECTID_GPIO_CTRL; + extData[1] = signalId; + extData[2] = ((uint8_t)currentGpioPinSel | GPIO_POLARITY_NORMAL | GPIO_DISABLE); + recoveryAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_SET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_SET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_SETARMGPIO_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_SETARMGPIO_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte >> 1) > 0) + { + recoveryAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Release the shared GPIO resource */ + sharedResourceArr[0] = (int32_t)currentGpioPinSel; + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + NUM_GPIOS_PER_CMD, + ADRV9025_FEATURE_ARM_GPIO_PIN, + &resourceAcqReleaseStatus); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + currentGpioPinSel, + "Unable to release GPIO pin currently assigned to requested signal ID. Please check if it is in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set the direction of Released GPIO to input */ + gpioPinMask = ((uint32_t)0x00000001 << (uint8_t)currentGpioPinSel); + recoveryAction = adi_adrv9025_GpioInputDirSet(device, + gpioPinMask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Associate requested signal ID with the GPIO pin selected and acquire the shared GPIO resource */ + if ((armGpioPin->enable > 0) && + (armGpioPin->gpioPinSel < ADI_ADRV9025_GPIO_INVALID)) + { + /* Acquire shared GPIO resource */ + sharedResourceArr[0] = (int32_t)armGpioPin->gpioPinSel; + recoveryAction = adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + NUM_GPIOS_PER_CMD, + ADRV9025_FEATURE_ARM_GPIO_PIN, + &resourceAcqReleaseStatus); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armGpioPin->gpioPinSel, + "Unable to acquire GPIO pin currently assigned to requested signal ID. Please check if it is in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set the direction of Acquired GPIO to input */ + gpioPinMask = ((uint32_t)0x00000001 << (uint8_t)armGpioPin->gpioPinSel); + recoveryAction = adi_adrv9025_GpioInputDirSet(device, + gpioPinMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Command ARM to associate the currently assigned GPIO for the requested signal ID */ + extData[0] = ADRV9025_CPU_OBJECTID_GPIO_CTRL; + extData[1] = signalId; + extData[2] = ((uint8_t)armGpioPin->gpioPinSel | GPIO_ENABLE); + + if (armGpioPin->polarity > 0) + { + extData[2] |= GPIO_POLARITY_INVERTED; + } + else + { + extData[2] &= ~GPIO_POLARITY_INVERTED; + } + + recoveryAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_SET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_SET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_SETARMGPIO_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_SETARMGPIO_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error and release the acquired shared resource */ + if ((cmdStatusByte >> 1) > 0) + { + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + NUM_GPIOS_PER_CMD, + ADRV9025_FEATURE_ARM_GPIO_PIN, + &resourceAcqReleaseStatus); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_ADRV9025_ACT_ERR_RESET_CPU, + armGpioPin->gpioPinSel, + "Unable to release currently acquired GPIO shared resource for ARM GPIO functionality due to an ARM error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set the direction of Released GPIO to input */ + gpioPinMask = ((uint32_t)0x00000001 << (uint8_t)armGpioPin->gpioPinSel); + recoveryAction = adi_adrv9025_GpioInputDirSet(device, + gpioPinMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_ArmGpioPinGet(adi_adrv9025_Device_t* device, + uint8_t signalId, + adi_adrv9025_GpioPinSel_e* gpioPinSel) +{ + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + static const uint8_t ARM_GPIO_MASK = 0x1F; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t extData[2] = {0}; + uint8_t armData[1] = {0}; + uint8_t cmdStatusByte = 0; + int32_t errHdl = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + gpioPinSel); + + /* Command ARM to return the currently assigned GPIO for the requested signal ID */ + extData[0] = ADRV9025_CPU_OBJECTID_GPIO_CTRL; + extData[1] = signalId; + recoveryAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_GET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_GETARMGPIO_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_GETARMGPIO_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte >> 1) > 0) + { + recoveryAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read GPIO Pin sel from ARM mailbox */ + recoveryAction = adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Return the GPIO data read back from ARM mailbox */ + *gpioPinSel = (adi_adrv9025_GpioPinSel_e)(armData[0] & ARM_GPIO_MASK); + + return recoveryAction; +} + +int32_t adrv9025_StreamTrigger(adi_adrv9025_Device_t* device, + uint8_t streamId) +{ + static const uint8_t CMD_STATUS_BYTE_ERROR = 0x0E; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t extData[1] = {0}; + uint8_t cmdStatusByte = 0; + int32_t errHdl = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Command ARM to execute the stream */ + extData[0] = streamId; + recoveryAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_STREAM_TRIGGER_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_STREAM_TRIGGER_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_SETTXTOORXMAP_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_SETTXTOORXMAP_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte & CMD_STATUS_BYTE_ERROR) > 0) + { + recoveryAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_STREAM_TRIGGER_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_StreamGpioPinSet(adi_adrv9025_Device_t* device, + uint8_t signalId, + adi_adrv9025_GpioPinSel_e streamTriggerGpio) +{ +#define NUM_ADRV9025_STREAM_GPIOS_PER_CMD 1 + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t resourceAcqReleaseStatus = ADI_FAILURE; + uint16_t streamTriggerPinMaskRegVal = 0; + uint16_t streamTriggerPinMask = 0; + adi_adrv9025_GpioPinSel_e activeStreamTriggerGpio = ADI_ADRV9025_GPIO_INVALID; + uint32_t gpioInputMask = 0; + int32_t sharedResourceArr[NUM_ADRV9025_STREAM_GPIOS_PER_CMD] = {0}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Range check on signalId */ + if (signalId > (uint8_t)ADI_ADRV9025_GPIO_15) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + signalId, + "SignalId provided has invalid range. Must be within [0-15]"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Retrieve the current GPIO pins programmed to be stream triggers */ + recoveryAction = adrv9025_StreamGpioPinGet(device, + signalId, + &activeStreamTriggerGpio); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (activeStreamTriggerGpio != ADI_ADRV9025_GPIO_INVALID) + { + /* The GPIO identified by signalId is to be masked from auto-trigggering streams */ + + /* Release the shared GPIO resource */ + sharedResourceArr[0] = (int32_t)signalId; + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + NUM_ADRV9025_STREAM_GPIOS_PER_CMD, + ADRV9025_FEATURE_GPIO_STREAM_TRIGGER, + &resourceAcqReleaseStatus); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_ADRV9025_ERR_SHARED_RESOURCE_RELEASE, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + signalId, + "Error while attempting to release the active stream trigger GPIO. Please check if the GPIO is in use by another feature."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Retrieve the current Stream Processor GPIO trigger mask */ + recoveryAction = adrv9025_CoreStreamProcGpioPinMaskBfGet(device, + ADRV9025_BF_CORE, + &streamTriggerPinMaskRegVal); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* At this point GPIO pin shared resource released, mask it from triggering streams. Setting to 1 masks the pin. */ + streamTriggerPinMaskRegVal |= ((uint16_t)1 << (uint8_t)activeStreamTriggerGpio); + recoveryAction = adrv9025_CoreStreamProcGpioPinMaskBfSet(device, + ADRV9025_BF_CORE, + streamTriggerPinMaskRegVal); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (streamTriggerGpio != ADI_ADRV9025_GPIO_INVALID) + { + /* Pin is currently masked */ + + /* Acquire shared resource first to make sure this GPio pin isn't being used for anything else */ + sharedResourceArr[0] = (int32_t)signalId; + recoveryAction = adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + NUM_ADRV9025_STREAM_GPIOS_PER_CMD, + ADRV9025_FEATURE_GPIO_STREAM_TRIGGER, + &resourceAcqReleaseStatus); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_ADRV9025_ERR_SHARED_RESOURCE_RELEASE, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + signalId, + "Error while attempting to acquire the req stream trigger GPIO. Please check if the GPIO is in use by another feature."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Read the current stream trigger pin mask value in the device */ + recoveryAction = adrv9025_CoreStreamProcGpioPinMaskBfGet(device, + ADRV9025_BF_CORE, + &streamTriggerPinMaskRegVal); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* At this point GPIO pin shared resource acquired, unmask it. Setting to 0 unmasks the pin. */ + streamTriggerPinMask = ((uint16_t)1 << (uint8_t)signalId); + streamTriggerPinMaskRegVal &= ~streamTriggerPinMask; + recoveryAction = adrv9025_CoreStreamProcGpioPinMaskBfSet(device, + ADRV9025_BF_CORE, + streamTriggerPinMaskRegVal); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set the GPIO direction to input */ + gpioInputMask = ((uint32_t)1 << (uint32_t)signalId); + recoveryAction = adi_adrv9025_GpioInputDirSet(device, + gpioInputMask); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_StreamGpioPinGet(adi_adrv9025_Device_t* device, + uint8_t signalId, + adi_adrv9025_GpioPinSel_e* streamTriggerGpio) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint16_t streamTriggerPinMask = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + streamTriggerGpio); + + /* Retrieve the current GPIO pins programmed to be stream triggers */ + recoveryAction = adrv9025_CoreStreamProcGpioPinMaskBfGet(device, + ADRV9025_BF_CORE, + &streamTriggerPinMask); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (ADRV9025_BF_EQUAL(streamTriggerPinMask, + ((uint16_t)1 << (uint16_t)signalId))) + { + /* corresponding pin in streamTriggerPinMask is equal to 1. Means it is masked, return ADI_ADRV9025_GPIO_INVALID */ + *streamTriggerGpio = ADI_ADRV9025_GPIO_INVALID; + } + else + { + /* corresponding pin in streamTriggerPinMAsk is not 1 (i.e. zero). Means it is unmasked, return the same pin code to indicate it is active.*/ + *streamTriggerGpio = (adi_adrv9025_GpioPinSel_e)signalId; + } + + return recoveryAction; +} + +int32_t adrv9025_StreamGpioConfigSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_StreamGpioPinCfg_t* streamGpioPinCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + streamGpioPinCfg); + + if ((streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_INVALID) && + (streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_00) && + (streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_01) && + (streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_02) && + (streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_03) && + (streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_04) && + (streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_05) && + (streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_06) && + (streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_07) && + (streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_08) && + (streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_09) && + (streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_10) && + (streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_11) && + (streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_12) && + (streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_13) && + (streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_14) && + (streamGpioPinCfg->streamGpInput0 != ADI_ADRV9025_GPIO_15)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + streamGpioPinCfg->streamGpInput0, + "Invalid stream trigger GPIO pin selected for stream GP0 input. GPIO00-GPIO15 are the valid values. To disable, please select GPIO_INVALID"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_INVALID) && + (streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_00) && + (streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_01) && + (streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_02) && + (streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_03) && + (streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_04) && + (streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_05) && + (streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_06) && + (streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_07) && + (streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_08) && + (streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_09) && + (streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_10) && + (streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_11) && + (streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_12) && + (streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_13) && + (streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_14) && + (streamGpioPinCfg->streamGpInput1 != ADI_ADRV9025_GPIO_15)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + streamGpioPinCfg->streamGpInput1, + "Invalid stream trigger GPIO pin selected for stream GP1 input. GPIO00-GPIO15 are valid values. To disable, please select GPIO_INVALID"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_INVALID) && + (streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_00) && + (streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_01) && + (streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_02) && + (streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_03) && + (streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_04) && + (streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_05) && + (streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_06) && + (streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_07) && + (streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_08) && + (streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_09) && + (streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_10) && + (streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_11) && + (streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_12) && + (streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_13) && + (streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_14) && + (streamGpioPinCfg->streamGpInput2 != ADI_ADRV9025_GPIO_15)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + streamGpioPinCfg->streamGpInput2, + "Invalid stream trigger GPIO pin selected for stream GP2 input. GPIO00-GPIO15 are valid values. To disable, please select GPIO_INVALID"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_INVALID) && + (streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_00) && + (streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_01) && + (streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_02) && + (streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_03) && + (streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_04) && + (streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_05) && + (streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_06) && + (streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_07) && + (streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_08) && + (streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_09) && + (streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_10) && + (streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_11) && + (streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_12) && + (streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_13) && + (streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_14) && + (streamGpioPinCfg->streamGpInput3 != ADI_ADRV9025_GPIO_15)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + streamGpioPinCfg->streamGpInput3, + "Invalid stream trigger GPIO pin selected for stream GP3 input. GPIO00-GPIO15 are valid values. To disable, please select GPIO_INVALID"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_TxToOrxMappingSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e orxChannel, + adi_adrv9025_TxChannels_e txChannel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + if (device->devStateInfo.devState < ADI_ADRV9025_STATE_CPULOADED) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + orxChannel, + "Tx-ORx mapping requires that the Stream and ARM binaries have been loaded"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((orxChannel != ADI_ADRV9025_ORX1) && + (orxChannel != ADI_ADRV9025_ORX2) && + (orxChannel != ADI_ADRV9025_ORX3) && + (orxChannel != ADI_ADRV9025_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + orxChannel, + "Invalid ORx Front end selected for Tx-ORx mapping. Valid ORx Front ends are ORx1-ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txChannel != ADI_ADRV9025_TX1) && + (txChannel != ADI_ADRV9025_TX2) && + (txChannel != ADI_ADRV9025_TX3) && + (txChannel != ADI_ADRV9025_TX4) && + (txChannel != ADI_ADRV9025_TXOFF)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid Tx channel selected for Tx-ORx mapping. Valid Tx channels are Tx1-Tx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((orxChannel == ADI_ADRV9025_ORX1) || (orxChannel == ADI_ADRV9025_ORX2)) + { + if ((txChannel != ADI_ADRV9025_TX1) && + (txChannel != ADI_ADRV9025_TX2) && + (txChannel != ADI_ADRV9025_TXOFF)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + orxChannel, + "Invalid Tx channel selected for Tx-ORx mapping on ORx1/2 Front End. Valid Tx channels are Tx1 and Tx2. To disable Tx-ORx mapping select TXOFF"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if ((orxChannel == ADI_ADRV9025_ORX3) || (orxChannel == ADI_ADRV9025_ORX4)) + { + if ((txChannel != ADI_ADRV9025_TX3) && + (txChannel != ADI_ADRV9025_TX4) && + (txChannel != ADI_ADRV9025_TXOFF)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + orxChannel, + "Invalid Tx channel selected for Tx-ORx mapping on ORx3/4 Front End. Valid Tx channels are Tx3 and Tx4. To disable Tx-ORx mapping select TXOFF"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_OrxMapDecode(adi_adrv9025_Device_t* device, + uint16_t encodedTxToORxMapping, + adi_adrv9025_RxChannels_e orxChannel, + adi_adrv9025_TxChannels_e* txChannel) +{ + static const uint16_t TXMAP_ORX1_ENA_MASK = 0x0002; + static const uint16_t TXMAP_ORX1_SEL_MASK = 0x0001; + static const uint16_t TXMAP_ORX2_ENA_MASK = 0x0020; + static const uint16_t TXMAP_ORX2_SEL_MASK = 0x0010; + static const uint16_t TXMAP_ORX3_ENA_MASK = 0x0200; + static const uint16_t TXMAP_ORX3_SEL_MASK = 0x0100; + static const uint16_t TXMAP_ORX4_ENA_MASK = 0x2000; + static const uint16_t TXMAP_ORX4_SEL_MASK = 0x1000; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + switch (orxChannel) + { + case(ADI_ADRV9025_ORX1): + { + if ((encodedTxToORxMapping & TXMAP_ORX1_ENA_MASK) == 0) + { + *txChannel = ADI_ADRV9025_TXOFF; + } + else + { + if ((encodedTxToORxMapping & TXMAP_ORX1_SEL_MASK) == 0) + { + *txChannel = ADI_ADRV9025_TX1; + } + else + { + *txChannel = ADI_ADRV9025_TX2; + } + } + + break; + } + case(ADI_ADRV9025_ORX2): + { + if ((encodedTxToORxMapping & TXMAP_ORX2_ENA_MASK) == 0) + { + *txChannel = ADI_ADRV9025_TXOFF; + } + else + { + if ((encodedTxToORxMapping & TXMAP_ORX2_SEL_MASK) == 0) + { + *txChannel = ADI_ADRV9025_TX1; + } + else + { + *txChannel = ADI_ADRV9025_TX2; + } + } + + break; + } + case(ADI_ADRV9025_ORX3): + { + if ((encodedTxToORxMapping & TXMAP_ORX3_ENA_MASK) == 0) + { + *txChannel = ADI_ADRV9025_TXOFF; + } + else + { + if ((encodedTxToORxMapping & TXMAP_ORX3_SEL_MASK) == 0) + { + *txChannel = ADI_ADRV9025_TX3; + } + else + { + *txChannel = ADI_ADRV9025_TX4; + } + } + + break; + } + case(ADI_ADRV9025_ORX4): + { + if ((encodedTxToORxMapping & TXMAP_ORX4_ENA_MASK) == 0) + { + *txChannel = ADI_ADRV9025_TXOFF; + } + else + { + if ((encodedTxToORxMapping & TXMAP_ORX4_SEL_MASK) == 0) + { + *txChannel = ADI_ADRV9025_TX3; + } + else + { + *txChannel = ADI_ADRV9025_TX4; + } + } + + break; + } + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + orxChannel, + "Invalid ORx channel selected for Tx-ORx mapping get."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_rx.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_rx.c new file mode 100644 index 0000000..8382601 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_rx.c @@ -0,0 +1,6283 @@ +/** + * \file adrv9025_rx.c + * \brief Contains ADRV9025 Rx related private function implementations + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "../../private/include/adrv9025_rx.h" +#include "../../private/include/adrv9025_tx.h" +#include "../../private/include/adrv9025_bf_core.h" +#include "../../private/include/adrv9025_bf_pll_mem_map.h" +#include "../../private/include/adrv9025_bf_analog_orx_mem_map.h" +#include "adi_adrv9025_error.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_gpio.h" +#include "../../private/include/adrv9025_shared_resource_manager.h" +#include "../../private/include/adrv9025_init.h" + +#define ADI_ADRV9025_NUM_GPIOS_RX_INT_SLICER_CTRL_OUT_FEATURE 4 +#define ADI_ADRV9025_NUM_GPIOS_RX_EXT_SLICER_CTRL_WORD_FEATURE 3 + +int32_t adrv9025_RxGainTableFormat(adi_adrv9025_Device_t* device, + adi_adrv9025_RxGainTableRow_t* gainTablePtr, + uint8_t* formattedGainTablePtr, + uint16_t numGainIndicesInTable) +{ + static const uint32_t NUM_BYTES_PER_GAIN_TABLE_ENTRY = 8; + static const uint16_t DIG_GAIN_LSB_MASK = 0x00FF; + static const uint16_t DIG_GAIN_MSB_MASK = 0x0300; + static const uint8_t DIG_GAIN_MSB_SHIFT = 8; + static const uint16_t DIG_GAIN_SIGN_MASK = 0x0400; + static const uint8_t DIG_GAIN_SIGN_SHIFT = 8; + static const uint8_t RXFE_GAIN_LSB_MASK = 0x1F; + static const uint8_t RXFE_GAIN_LSB_SHIFT = 3; + static const uint8_t RXFE_GAIN_MSB_MASK = 0xE0; + static const uint8_t RXFE_GAIN_MSB_SHIFT = 5; + static const uint16_t PHASE_OFFSET_LSB_MASK = 0x00FF; + static const uint16_t PHASE_OFFSET_MSB_MASK = 0xFF00; + static const uint8_t PHASE_OFFSET_MSB_SHIFT = 8; + static const uint8_t EXT_CTRL_MASK = 0x03; + static const uint8_t ADC_TIA_GAIN_MASK = 0x03; + static const uint8_t ADC_TIA_GAIN_SHIFT = 2; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t gainIndex = 0; + uint32_t formattedGainIndex = 0; + uint16_t sign = 0; + uint16_t magnitude = 0; + + /*Perform NULL checks on pointers*/ + if (gainTablePtr == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_NULL_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gainTablePtr, + "Null gainTablePtr encountered"); + return device->common.error.newAction; + } + + if (formattedGainTablePtr == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_NULL_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + formattedGainTablePtr, + "Null formattedGainTablePtr encountered"); + return device->common.error.newAction; + } + + /*Format gain table*/ + for (gainIndex = 0; gainIndex < numGainIndicesInTable; gainIndex++) + { + /*Format Gain Table Data as follows : + No. of Bytes per Gain Table Entry = 8 + @Addr 8 x gainIndex : {13'b0 , rx_fe_gain[7:0], dig_gain[10:0]} + @Addr 8 x gainIndex + 4 : {12'b0, tia_control, adc_control, ext_control[1:0], phase_offset[15:0]} + */ + formattedGainIndex = (gainIndex * NUM_BYTES_PER_GAIN_TABLE_ENTRY); + + if (gainTablePtr[gainIndex].digGain < 0) + { + sign = DIG_GAIN_SIGN_MASK; /* set bit 11 */ + magnitude = (((~(uint16_t)gainTablePtr[gainIndex].digGain) + 1) & 0x3FF); + } + else + { + sign = 0; + magnitude = gainTablePtr[gainIndex].digGain & 0x3FF; + } + + formattedGainTablePtr[formattedGainIndex] = (uint8_t)(magnitude & DIG_GAIN_LSB_MASK); + formattedGainTablePtr[formattedGainIndex + 1] = (uint8_t)((sign & DIG_GAIN_SIGN_MASK) >> DIG_GAIN_SIGN_SHIFT) | + (uint8_t)((magnitude & DIG_GAIN_MSB_MASK) >> DIG_GAIN_MSB_SHIFT) | + (uint8_t)((gainTablePtr[gainIndex].rxFeGain & RXFE_GAIN_LSB_MASK) << RXFE_GAIN_LSB_SHIFT); + formattedGainTablePtr[formattedGainIndex + 2] = (uint8_t)((gainTablePtr[gainIndex].rxFeGain & RXFE_GAIN_MSB_MASK) >> RXFE_GAIN_MSB_SHIFT); + formattedGainTablePtr[formattedGainIndex + 3] = 0; + formattedGainTablePtr[formattedGainIndex + 4] = (uint8_t)(gainTablePtr[gainIndex].phaseOffset & PHASE_OFFSET_LSB_MASK); + formattedGainTablePtr[formattedGainIndex + 5] = (uint8_t)((gainTablePtr[gainIndex].phaseOffset & PHASE_OFFSET_MSB_MASK) >> PHASE_OFFSET_MSB_SHIFT); + formattedGainTablePtr[formattedGainIndex + 6] = (uint8_t)(gainTablePtr[gainIndex].extControl & EXT_CTRL_MASK) | + (uint8_t)((gainTablePtr[gainIndex].adcTiaGain & ADC_TIA_GAIN_MASK) << ADC_TIA_GAIN_SHIFT); + formattedGainTablePtr[formattedGainIndex + 7] = 0; + } + + return recoveryAction; +} + +int32_t adrv9025_RxGainTableParse(adi_adrv9025_Device_t* device, + adi_adrv9025_RxGainTableRow_t* gainTablePtr, + uint8_t* armDmaDataGainTablePtr, + uint16_t numGainIndicesInTable) +{ + static const uint32_t NUM_BYTES_PER_GAIN_TABLE_ENTRY = 8; + static const uint16_t DIG_GAIN_MSB_MASK = 0x0003; + static const uint8_t DIG_GAIN_MSB_SHIFT = 8; + static const uint8_t RXFE_GAIN_LSB_MASK = 0xF8; + static const uint8_t RXFE_GAIN_LSB_SHIFT = 3; + static const uint8_t RXFE_GAIN_MSB_MASK = 0x07; + static const uint8_t RXFE_GAIN_MSB_SHIFT = 5; + static const uint8_t PHASE_OFFSET_MSB_SHIFT = 8; + static const uint8_t EXT_CTRL_MASK = 0x03; + static const uint8_t ADC_TIA_GAIN_MASK = 0x0C; + static const uint8_t ADC_TIA_GAIN_SHIFT = 2; + /*11th bit for digital gain is the sign bit*/ + static const uint8_t DIG_GAIN_SIGN_MASK = 0x04; + static const int16_t DIG_GAIN_SIGN_EXT = 0xFC00; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t gainIndex = 0; + uint32_t armDmaDataGainIndex = 0; + int16_t digGain = 0; + uint16_t magnitude = 0; + + /*Perform NULL checks on pointers*/ + if (gainTablePtr == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_NULL_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gainTablePtr, + "Null gainTablePtr encountered"); + return device->common.error.newAction; + } + + if (armDmaDataGainTablePtr == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_NULL_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armDmaDataGainTablePtr, + "Null armDmaDataGainTablePtr encountered"); + return device->common.error.newAction; + } + + /*Parse Gain Table Data in ARM DMA format and store it in gain table row struct*/ + for (gainIndex = 0; gainIndex < numGainIndicesInTable; gainIndex++) + { + /*Parse Gain Table Data : + No. of Bytes per Gain Table Entry = 8 + @armDmaDataGainIndex[8 x gainIndex] : {13'b0 , rx_fe_gain[7:0], dig_gain[10:0]} + @armDmaDataGainIndex[8 x gainIndex + 4]: {12'b0, tia_control, adc_control, ext_control[1:0], phase_offset[15:0]} + */ + armDmaDataGainIndex = (gainIndex * NUM_BYTES_PER_GAIN_TABLE_ENTRY); + + magnitude = ((uint16_t)armDmaDataGainTablePtr[armDmaDataGainIndex] | + (((uint16_t)armDmaDataGainTablePtr[armDmaDataGainIndex + 1] & DIG_GAIN_MSB_MASK) << DIG_GAIN_MSB_SHIFT)); + if ((armDmaDataGainTablePtr[armDmaDataGainIndex + 1] & DIG_GAIN_SIGN_MASK) == DIG_GAIN_SIGN_MASK) + { + /*Since digGain is a 11bit no. for ARM, 11th bit is the signed bit. However since it is of signed half word type for API use, hence has to be sign extended*/ + digGain = (int16_t)(~(uint16_t)(magnitude - 1)); + digGain |= DIG_GAIN_SIGN_EXT; + } + else + { + digGain = (int16_t)magnitude; + } + + gainTablePtr[gainIndex].digGain = digGain; + gainTablePtr[gainIndex].rxFeGain = (((uint8_t)armDmaDataGainTablePtr[armDmaDataGainIndex + 1] & RXFE_GAIN_LSB_MASK) >> RXFE_GAIN_LSB_SHIFT) | + (((uint8_t)armDmaDataGainTablePtr[armDmaDataGainIndex + 2] & RXFE_GAIN_MSB_MASK) << RXFE_GAIN_MSB_SHIFT); + gainTablePtr[gainIndex].phaseOffset = (uint16_t)armDmaDataGainTablePtr[armDmaDataGainIndex + 4] | + ((uint16_t)armDmaDataGainTablePtr[armDmaDataGainIndex + 5] << PHASE_OFFSET_MSB_SHIFT); + gainTablePtr[gainIndex].extControl = (uint8_t)armDmaDataGainTablePtr[armDmaDataGainIndex + 6] & EXT_CTRL_MASK; + gainTablePtr[gainIndex].adcTiaGain = ((uint8_t)armDmaDataGainTablePtr[armDmaDataGainIndex + 6] & ADC_TIA_GAIN_MASK) >> ADC_TIA_GAIN_SHIFT; + } + + return recoveryAction; +} + +int32_t adrv9025_RxGainTableReadParamsCompute(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint16_t maxReadGainIndices, + uint8_t gainIndexOffset, + uint16_t* numGainIndicesToRead, + uint32_t* baseAddr) +{ + static const uint32_t NUM_BYTES_PER_RX_GAIN_INDEX = 8; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint16_t maxGainIndices = 0; + uint32_t baseIndex = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /*Check that numGainIndicesToRead is not null*/ + ADI_NULL_PTR_RETURN(&device->common, + numGainIndicesToRead); + + /*Check that baseAddr is not null*/ + ADI_NULL_PTR_RETURN(&device->common, + baseAddr); + + /*Calculate base index for the config*/ + switch (rxChannel) + { + case ADI_ADRV9025_RX1: + { + maxGainIndices = (gainIndexOffset - device->devStateInfo.gainIndexes.rx1MinGainIndex) + 1; + + if (maxReadGainIndices >= maxGainIndices) + { + *numGainIndicesToRead = maxGainIndices; + } + else + { + *numGainIndicesToRead = maxReadGainIndices; + } + + baseIndex = (gainIndexOffset - (*numGainIndicesToRead - 1)); + *baseAddr = (uint32_t)ADI_ADRV9025_RX1_GAIN_TABLE_BASEADDR + (baseIndex * NUM_BYTES_PER_RX_GAIN_INDEX); + break; + } + + case ADI_ADRV9025_RX2: + { + maxGainIndices = (gainIndexOffset - device->devStateInfo.gainIndexes.rx2MinGainIndex) + 1; + + if (maxReadGainIndices >= maxGainIndices) + { + *numGainIndicesToRead = maxGainIndices; + } + else + { + *numGainIndicesToRead = maxReadGainIndices; + } + + baseIndex = (gainIndexOffset - (*numGainIndicesToRead - 1)); + *baseAddr = (uint32_t)ADI_ADRV9025_RX2_GAIN_TABLE_BASEADDR + (baseIndex * NUM_BYTES_PER_RX_GAIN_INDEX); + break; + } + + case ADI_ADRV9025_RX3: + { + maxGainIndices = (gainIndexOffset - device->devStateInfo.gainIndexes.rx3MinGainIndex) + 1; + + if (maxReadGainIndices >= maxGainIndices) + { + *numGainIndicesToRead = maxGainIndices; + } + else + { + *numGainIndicesToRead = maxReadGainIndices; + } + + baseIndex = (gainIndexOffset - (*numGainIndicesToRead - 1)); + *baseAddr = (uint32_t)ADI_ADRV9025_RX3_GAIN_TABLE_BASEADDR + (baseIndex * NUM_BYTES_PER_RX_GAIN_INDEX); + break; + } + + case ADI_ADRV9025_RX4: + { + maxGainIndices = (gainIndexOffset - device->devStateInfo.gainIndexes.rx4MinGainIndex) + 1; + + if (maxReadGainIndices >= maxGainIndices) + { + *numGainIndicesToRead = maxGainIndices; + } + else + { + *numGainIndicesToRead = maxReadGainIndices; + } + + baseIndex = (gainIndexOffset - (*numGainIndicesToRead - 1)); + *baseAddr = (uint32_t)ADI_ADRV9025_RX4_GAIN_TABLE_BASEADDR + (baseIndex * NUM_BYTES_PER_RX_GAIN_INDEX); + break; + } + + case ADI_ADRV9025_ORX1: /*Fall Through*/ + case ADI_ADRV9025_ORX2: + { + maxGainIndices = (gainIndexOffset - device->devStateInfo.gainIndexes.orx1orx2MinGainIndex) + 1; + + if (maxReadGainIndices >= maxGainIndices) + { + *numGainIndicesToRead = maxGainIndices; + } + else + { + *numGainIndicesToRead = maxReadGainIndices; + } + + baseIndex = (gainIndexOffset - (*numGainIndicesToRead - 1)); + *baseAddr = (uint32_t)ADI_ADRV9025_ORX1_ORX2_GAIN_TABLE_BASEADDR + (baseIndex * NUM_BYTES_PER_RX_GAIN_INDEX); + break; + } + + case ADI_ADRV9025_ORX3: /*Fall Through*/ + case ADI_ADRV9025_ORX4: + { + maxGainIndices = (gainIndexOffset - device->devStateInfo.gainIndexes.orx3orx4MinGainIndex) + 1; + + if (maxReadGainIndices >= maxGainIndices) + { + *numGainIndicesToRead = maxGainIndices; + } + else + { + *numGainIndicesToRead = maxReadGainIndices; + } + + baseIndex = (gainIndexOffset - (*numGainIndicesToRead - 1)); + *baseAddr = (uint32_t)ADI_ADRV9025_ORX3_ORX4_GAIN_TABLE_BASEADDR + (baseIndex * NUM_BYTES_PER_RX_GAIN_INDEX); + break; + } + + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel Requested for gain table read. Valid Rx channels include Rx1-Rx4, ORx1-ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxGainCtrlPinReportError(adi_adrv9025_Device_t* device, + int32_t sharedResourceArr[], + int32_t recoveryAction, + const char* customError) +{ + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_RX_GAIN_CTRL_PIN; + static const uint32_t NUM_GPIOS_IN_RX_GAIN_CTRL_PIN_FEATURE = 2U; + + int32_t recAct = ADI_COMMON_ACT_NO_ACTION; + uint8_t resourceReleaseStatus = ADI_FAILURE; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check rx bitfield channel address pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + sharedResourceArr); + + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + /*Clear the error so that clean up functions execute*/ + recAct = adi_common_ErrorClear(&device->common); + ADI_ERROR_RETURN(device->common.error.newAction); + + recAct = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + NUM_GPIOS_IN_RX_GAIN_CTRL_PIN_FEATURE, + THIS_FEATURE_ID, + &resourceReleaseStatus); + + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceReleaseStatus, + "Error while attempting to release GPIO shared resouce for GPIO gain ctrl Increment/Decrement Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + customError); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recAct; +} + +int32_t adrv9025_RxExtCtrlPinReportError(adi_adrv9025_Device_t* device, + int32_t sharedResourceArr[], + uint8_t numSharedResources, + int32_t recoveryAction, + const char* customError) +{ + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_RX_EXT_CTRL_WORD_OUTPUT; + + int32_t recAct = ADI_COMMON_ACT_NO_ACTION; + uint8_t resourceReleaseStatus = ADI_FAILURE; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check rx bitfield channel address pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + sharedResourceArr); + + /*If error encountered at any point during API execution, release acquired shared resource*/ + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + /*Clear the error so that clean up functions execute*/ + recAct = adi_common_ErrorClear(&device->common); + ADI_ERROR_RETURN(device->common.error.newAction); + + recAct = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + numSharedResources, + THIS_FEATURE_ID, + &resourceReleaseStatus); + + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceReleaseStatus, + "Error while attempting to release shared Analog GPIO during enabling of Rx ext ctrl output. Please Check if the GPIOs in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + customError); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recAct; +} + +int32_t adrv9025_RxDualbandLnaCtrlPinReportError(adi_adrv9025_Device_t* device, + int32_t sharedResourceArr[], + uint8_t numSharedResources, + int32_t recoveryAction, + const char* customError) +{ + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_RX_DUALBAND_LNA_CTRL_WORD_OUTPUT; + + int32_t recAct = ADI_COMMON_ACT_NO_ACTION; + uint8_t resourceReleaseStatus = ADI_FAILURE; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check rx bitfield channel address pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + sharedResourceArr); + + /*If error encountered at any point during API execution, release acquired shared resource*/ + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + /*Clear the error so that clean up functions execute*/ + recAct = adi_common_ErrorClear(&device->common); + ADI_ERROR_RETURN(device->common.error.newAction); + + recAct = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + numSharedResources, + THIS_FEATURE_ID, + &resourceReleaseStatus); + + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceReleaseStatus, + "Error while attempting to release shared Analog GPIO during enabling of Rx dualband ctrl output. Please Check if the GPIOs are in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + customError); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recAct; +} + +int32_t adrv9025_RxBitfieldAddressGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adrv9025_BfRxChanAddr_e* rxChannelBitfieldAddr) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check rx bitfield channel address pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + rxChannelBitfieldAddr); + + if ((device->devStateInfo.initializedChannels & (uint32_t)rxChannel) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Channel not in device initializedChannels for adrv9025_RxBitfieldAddressGet() function"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + switch (rxChannel) + { + case ADI_ADRV9025_RX1: + *rxChannelBitfieldAddr = ADRV9025_BF_RX_CH0; + break; + + case ADI_ADRV9025_RX2: + *rxChannelBitfieldAddr = ADRV9025_BF_RX_CH1; + break; + + case ADI_ADRV9025_RX3: + *rxChannelBitfieldAddr = ADRV9025_BF_RX_CH2; + break; + + case ADI_ADRV9025_RX4: + *rxChannelBitfieldAddr = ADRV9025_BF_RX_CH3; + break; + + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid rxChannel parameter for adrv9025_RxBitfieldAddressGet() function"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + } + + return recoveryAction; +} + +int32_t adrv9025_OrxBitfieldAddressGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e orxChannel, + adrv9025_BfOrxChanAddr_e* orxChannelBitfieldAddr) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check rx bitfield channel address pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + orxChannelBitfieldAddr); + + if ((device->devStateInfo.initializedChannels & (uint32_t)orxChannel) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + orxChannel, + "Channel not in device initializedChannels for adrv9025_OrxBitfieldAddressGet() function"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + switch (orxChannel) + { + case ADI_ADRV9025_ORX1: /*Fall Through*/ + case ADI_ADRV9025_ORX2: + *orxChannelBitfieldAddr = ADRV9025_BF_ORX_CH0; + break; + + case ADI_ADRV9025_ORX3: /*Fall Through*/ + case ADI_ADRV9025_ORX4: + *orxChannelBitfieldAddr = ADRV9025_BF_ORX_CH1; + break; + + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + orxChannel, + "Invalid orxChannel parameter for adrv9025_OrxBitfieldAddressGet() function"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxAnalogBitfieldAddressGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adrv9025_BfAnalogRxMemMapChanAddr_e* rxChannelAnalogBitfieldAddr) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check rx bitfield channel address pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + rxChannelAnalogBitfieldAddr); + + switch (rxChannel) + { + case ADI_ADRV9025_RX1: + *rxChannelAnalogBitfieldAddr = ADRV9025_BF_ANALOG_RX_CH0; + break; + + case ADI_ADRV9025_RX2: + *rxChannelAnalogBitfieldAddr = ADRV9025_BF_ANALOG_RX_CH1; + break; + + case ADI_ADRV9025_RX3: + *rxChannelAnalogBitfieldAddr = ADRV9025_BF_ANALOG_RX_CH2; + break; + + case ADI_ADRV9025_RX4: + *rxChannelAnalogBitfieldAddr = ADRV9025_BF_ANALOG_RX_CH3; + break; + + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid rxChannel parameter for adrv9025_RxAnalogBitfieldAddressGet() function"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + } + + return recoveryAction; +} + +int32_t adrv9025_OrxAnalogBitfieldAddressGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e orxChannel, + adrv9025_BfAnalogOrxMemMapChanAddr_e* orxChannelAnalogBitfieldAddr) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check rx bitfield channel address pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + orxChannelAnalogBitfieldAddr); + + switch (orxChannel) + { + case ADI_ADRV9025_ORX1: /*Fall Through*/ + case ADI_ADRV9025_ORX2: + *orxChannelAnalogBitfieldAddr = ADRV9025_BF_ANALOG_ORX_CH0; + break; + + case ADI_ADRV9025_ORX3: /*Fall Through*/ + case ADI_ADRV9025_ORX4: + *orxChannelAnalogBitfieldAddr = ADRV9025_BF_ANALOG_ORX_CH1; + break; + + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + orxChannel, + "Invalid orxChannel parameter for adrv9025_OrxAnalogBitfieldAddressGet() function"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + } + + return recoveryAction; +} + +uint16_t adrv9025_RxAddrDecode(adi_adrv9025_Device_t* device, + uint32_t channelMask) +{ + if (device == NULL) + { + return 0; + } + + if ((device->devStateInfo.initializedChannels & channelMask) != channelMask) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelMask, + "Channel not in device initializedChannels for adrv9025_RxAddrDecode() function"); + return (0); + } + + switch (channelMask) + { + case ADI_ADRV9025_RX1: + return ADRV9025_ADDR_CH0_RX; + case ADI_ADRV9025_RX2: + return ADRV9025_ADDR_CH1_RX; + case ADI_ADRV9025_RX3: + return ADRV9025_ADDR_CH2_RX; + case ADI_ADRV9025_RX4: + return ADRV9025_ADDR_CH3_RX; + case (ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4): + return ADRV9025_ADDR_ALL_RX; + case ADI_ADRV9025_ORX1: + return ADRV9025_ADDR_CH0_ORX; + case ADI_ADRV9025_ORX2: + return ADRV9025_ADDR_CH0_ORX; + case ADI_ADRV9025_ORX3: + return ADRV9025_ADDR_CH1_ORX; + case ADI_ADRV9025_ORX4: + return ADRV9025_ADDR_CH1_ORX; + case ADI_ADRV9025_LB12: + return ADRV9025_ADDR_CH0_ORX; + case ADI_ADRV9025_LB34: + return ADRV9025_ADDR_CH1_ORX; + default: + return (0); + } +} + +int32_t adrv9025_RxFirWrite(adi_adrv9025_Device_t* device, + uint32_t rxChanMask, + int8_t gain_dB, + uint8_t numFirCoefs, + int16_t coefs[], + uint8_t arraySize) +{ + uint8_t firBankSel = 0; + uint8_t i = 0; + uint8_t j = 0; + uint8_t numTapsReg = 0; + uint8_t nTapMul = 1; + uint8_t maxNumTaps = 0; + uint8_t filterGain = 0; + uint8_t pfirCoeffCtl = 0; + uint16_t baseaddr = 0; + uint8_t filterConfig = 0; + uint8_t rxPfirBankSel = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + coefs); + + ADRV9025_BUGINFO(__FUNCTION__); + + static const uint8_t autoInc = ADI_ADRV9025_PFIR_COEFF_AUTO_INCR; + static const uint8_t RXFIR_BANKA = 0x01; + static const uint8_t ORXFIR_BANKA = 0x02; + static const uint8_t ORXFIR_BANKB = 0x04; + static const uint8_t ORXFIR_BANKC = 0x08; + + static const uint8_t BANKA = 0; + static const uint8_t BANKB = 1; + static const uint8_t BANKC = 2; + + static const uint8_t RXFIR_MAXTAPS = 72; + static const uint8_t RXFIR_MULTAPS = 24; + + if (adrv9025_RxAddrDecode(device, + rxChanMask) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChanMask, + "Invalid RxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Error checking, #taps less than max number of taps allowed.*/ + if (numFirCoefs == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + numFirCoefs, + "NumFirCoef is zero"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (arraySize == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + arraySize, + "arraySize is zero"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* firBankSelect and assignment of maxNumTaps, nTapMul and address firAddr.*/ + switch (rxChanMask) + { + case ADI_ADRV9025_RX1: /* fall through */ + case ADI_ADRV9025_RX2: /* fall through */ + case ADI_ADRV9025_RX3: /* fall through */ + case ADI_ADRV9025_RX4: /* fall through */ + case (ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4): + maxNumTaps = RXFIR_MAXTAPS; + firBankSel = RXFIR_BANKA; + nTapMul = RXFIR_MULTAPS; + break; + + case ADI_ADRV9025_ORX1: /* fall through */ + case ADI_ADRV9025_ORX3: /* fall through */ + maxNumTaps = RXFIR_MAXTAPS; + firBankSel = ORXFIR_BANKA; + nTapMul = RXFIR_MULTAPS; + break; + + case ADI_ADRV9025_ORX2: /* fall through */ + case ADI_ADRV9025_ORX4: /* fall through */ + maxNumTaps = RXFIR_MAXTAPS; + firBankSel = ORXFIR_BANKB; + nTapMul = RXFIR_MULTAPS; + break; + + case ADI_ADRV9025_LB12: /* fall through */ + case ADI_ADRV9025_LB34: /* fall through */ + maxNumTaps = RXFIR_MAXTAPS; + firBankSel = ORXFIR_BANKC; + nTapMul = RXFIR_MULTAPS; + break; + + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChanMask, + "Undefined Rx ChannelMask"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Verification for the structure numFirCoefs */ + if (numFirCoefs > maxNumTaps) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + numFirCoefs, + "NumFirCoef is too large"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (numFirCoefs > arraySize) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + numFirCoefs, + "NumFirCoef is larger than arraySize"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Calculate register value for number of Taps */ + if (((numFirCoefs % nTapMul) == 0) && (numFirCoefs > 0)) + { + numTapsReg = (numFirCoefs / nTapMul) - 1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + numFirCoefs, + "Invalid numFirCoefs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (firBankSel == RXFIR_BANKA) + { + pfirCoeffCtl = ADRV9025_PFIR_COEFF_PROG_CLK_EN | ADRV9025_PFIR_COEFF_WR_ENABLE; + if (autoInc != 0) + { + pfirCoeffCtl |= ADRV9025_PFIR_COEFF_AUTO_INCR; + } + + baseaddr = adrv9025_RxAddrDecode(device, + rxChanMask); + ADRV9025_SPIWRITEBYTE("RX_PFIR_COEFF_CTL", + (baseaddr + ADRV9025_ADDR_RX_PFIR_COEFF_CTL_OFFSET), + pfirCoeffCtl); + + /* pfir_coeff_addr */ + j = 0; + ADRV9025_SPIWRITEBYTE("RX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_RX_PFIR_COEFF_ADDR_OFFSET), + j); + + for (i = 0; i < numFirCoefs; i++) + { + /* pfir_coeff_data LSB */ + ADRV9025_SPIWRITEBYTE("RX_PFIR_COEFF_DATA_LSB", + (baseaddr + ADRV9025_ADDR_RX_PFIR_COEFF_DATA_OFFSET), + (uint8_t)(coefs[i])); + if (autoInc == 0) + { + j++; + ADRV9025_SPIWRITEBYTE("RX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_RX_PFIR_COEFF_ADDR_OFFSET), + j); + } + /* pfir_coeff_data MSB */ + ADRV9025_SPIWRITEBYTE("RX_PFIR_COEFF_DATA_MSB", + (baseaddr + ADRV9025_ADDR_RX_PFIR_COEFF_DATA_OFFSET), + (uint8_t)(coefs[i] >> 8)); + if (autoInc == 0) + { + j++; + ADRV9025_SPIWRITEBYTE("RX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_RX_PFIR_COEFF_ADDR_OFFSET), + j); + } + } + + /* disable pfir_coeff_prog_clk_en */ + /* disable pfir_coeff_wr_enable */ + + pfirCoeffCtl = 0; + ADRV9025_SPIWRITEBYTE("RX_PFIR_COEFF_CTL", + (baseaddr + ADRV9025_ADDR_RX_PFIR_COEFF_CTL_OFFSET), + pfirCoeffCtl); + + /* Set filter gain to be used */ + switch (gain_dB) + { + case ADRV9025_FIR_GAIN_NEG12_DB: + filterGain = 0x00; + break; + case ADRV9025_FIR_GAIN_NEG6_DB: + filterGain = 0x01; + break; + case ADRV9025_FIR_GAIN_0_DB: + filterGain = 0x02; + break; + case ADRV9025_FIR_GAIN_POS6_DB: + filterGain = 0x03; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gain_dB, + "Invalid FirGain"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + filterConfig = 0; + /* rx_pfir_Taps */ + filterConfig |= ADRV9025_BF_ENCODE(numTapsReg, + ADRV9025_RX_PFIR_TAPS_MASK, + ADRV9025_RX_PFIR_TAPS_SHIFT); + + /* rx_pfir_gain */ + filterConfig |= ADRV9025_BF_ENCODE(filterGain, + ADRV9025_RX_PFIR_GAIN_MASK, + ADRV9025_RX_PFIR_GAIN_SHIFT); + + ADRV9025_SPIWRITEBYTE("RX_PFIR_SETTINGS", + (baseaddr + ADRV9025_ADDR_RX_PFIR_SETTINGS_OFFSET), + filterConfig); + } + + if (firBankSel & (ORXFIR_BANKA | ORXFIR_BANKB | ORXFIR_BANKC)) + { + pfirCoeffCtl = ADRV9025_PFIR_COEFF_PROG_CLK_EN | ADRV9025_PFIR_COEFF_WR_ENABLE; + if (autoInc != 0) + { + pfirCoeffCtl |= ADRV9025_PFIR_COEFF_AUTO_INCR; + } + /*pfir_coeff_rx_b_sel */ + + if (firBankSel & ORXFIR_BANKA) + { + pfirCoeffCtl |= ADRV9025_PFIR_COEFF_RX_A_SEL; + } + + if (firBankSel & ORXFIR_BANKB) + { + pfirCoeffCtl |= ADRV9025_PFIR_COEFF_RX_B_SEL; + } + + if (firBankSel & ORXFIR_BANKC) + { + pfirCoeffCtl |= ADRV9025_PFIR_COEFF_RX_C_SEL; + } + + baseaddr = adrv9025_RxAddrDecode(device, + rxChanMask); + ADRV9025_SPIWRITEBYTE("ORX_PFIR_COEFF_CTL", + (baseaddr + ADRV9025_ADDR_ORX_PFIR_COEFF_CTL_OFFSET), + pfirCoeffCtl); + + /* pfir_coeff_addr */ + j = 0; + ADRV9025_SPIWRITEBYTE("ORX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_ORX_PFIR_COEFF_ADDR_OFFSET), + j); + + for (i = 0; i < numFirCoefs; i++) + { + /* pfir_coeff_data LSB */ + ADRV9025_SPIWRITEBYTE("ORX_PFIR_COEFF_DATA_LSB", + (baseaddr + ADRV9025_ADDR_ORX_PFIR_COEFF_DATA_OFFSET), + (uint8_t)(coefs[i])); + if (autoInc == 0) + { + j++; + ADRV9025_SPIWRITEBYTE("ORX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_ORX_PFIR_COEFF_ADDR_OFFSET), + j); + } + + /* pfir_coeff_data MSB */ + ADRV9025_SPIWRITEBYTE("ORX_PFIR_COEFF_DATA_MSB", + (baseaddr + ADRV9025_ADDR_ORX_PFIR_COEFF_DATA_OFFSET), + (uint8_t)(coefs[i] >> 8)); + if (autoInc == 0) + { + j++; + ADRV9025_SPIWRITEBYTE("ORX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_ORX_PFIR_COEFF_ADDR_OFFSET), + j); + } + } + + /* disable pfir_coeff_prog_clk_en */ + /* disable pfir_coeff_wr_enable */ + pfirCoeffCtl = 0; + ADRV9025_SPIWRITEBYTE("ORX_PFIR_COEFF_CTL", + (baseaddr + ADRV9025_ADDR_ORX_PFIR_COEFF_CTL_OFFSET), + pfirCoeffCtl); + + /* Set filter gain to be used */ + switch (gain_dB) + { + case ADRV9025_FIR_GAIN_NEG12_DB: + filterGain = 0x00; + break; + case ADRV9025_FIR_GAIN_NEG6_DB: + filterGain = 0x01; + break; + case ADRV9025_FIR_GAIN_0_DB: + filterGain = 0x02; + break; + case ADRV9025_FIR_GAIN_POS6_DB: + filterGain = 0x03; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gain_dB, + "Invalid FirGain"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + filterConfig = 0; + + /* Write FIR #taps and gain */ + /* orx_pfir_Taps */ + /* rx_pfir_Taps */ + filterConfig |= ADRV9025_BF_ENCODE(numTapsReg, + ADRV9025_RX_PFIR_TAPS_MASK, + ADRV9025_RX_PFIR_TAPS_SHIFT); + + /* rx_pfir_gain */ + filterConfig |= ADRV9025_BF_ENCODE(filterGain, + ADRV9025_RX_PFIR_GAIN_MASK, + ADRV9025_RX_PFIR_GAIN_SHIFT); + + /* pfir_coeff_rx_b_sel */ + if (firBankSel & ORXFIR_BANKA) + { + ADRV9025_SPIWRITEBYTE("ORX_PFIR_CONFIG_SETTING_BANK_A", + (baseaddr + ADRV9025_ADDR_RX_PFIR_CONFIG_SETTINGSN_OFFSET + BANKA), + filterConfig); + } + + /* pfir_coeff_rx_b_sel */ + if (firBankSel & ORXFIR_BANKB) + { + ADRV9025_SPIWRITEBYTE("ORX_PFIR_CONFIG_SETTING_BANK_B", + (baseaddr + ADRV9025_ADDR_RX_PFIR_CONFIG_SETTINGSN_OFFSET + BANKB), + filterConfig); + } + + if (firBankSel & ORXFIR_BANKC) + { + ADRV9025_SPIWRITEBYTE("ORX_PFIR_CONFIG_SETTING_BANK_C", + (baseaddr + ADRV9025_ADDR_RX_PFIR_CONFIG_SETTINGSN_OFFSET + BANKC), + filterConfig); + } + + /* Set Mode mapping for Obs Rx1 FIR Bank A */ + rxPfirBankSel = ADRV9025_BF_ENCODE(BANKA, + ADRV9025_PFIR_CONFIG_FOR_ORX_1_MASK, + ADRV9025_PFIR_CONFIG_FOR_ORX_1_SHIFT); + /* Set Mode mapping for Obs Rx2 FIR Bank B */ + rxPfirBankSel |= ADRV9025_BF_ENCODE(BANKB, + ADRV9025_PFIR_CONFIG_FOR_ORX_2_MASK, + ADRV9025_PFIR_CONFIG_FOR_ORX_2_SHIFT); + /* Set Mode mapping for Loopback Bank C */ + rxPfirBankSel |= ADRV9025_BF_ENCODE(BANKC, + ADRV9025_PFIR_CONFIG_FOR_LOOPBACK_1_MASK, + ADRV9025_PFIR_CONFIG_FOR_LOOPBACK_1_SHIFT); + rxPfirBankSel |= ADRV9025_BF_ENCODE(BANKC, + ADRV9025_PFIR_CONFIG_FOR_LOOPBACK_2_MASK, + ADRV9025_PFIR_CONFIG_FOR_LOOPBACK_2_SHIFT); + + ADRV9025_SPIWRITEBYTE("ORX_PFIR_BANK_SEL", + (baseaddr + ADRV9025_ADDR_RX_PFIR_BANK_SEL_OFFSET), + rxPfirBankSel); + } + + return (device->common.error.newAction); +} + +int32_t adrv9025_RxDataFormatSetFloatingPointRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_FloatingPointConfigSettings_t* floatingPointConfig) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check rx bitfield channel address pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + floatingPointConfig); + + /* Check floating point format selected is valid */ + if ((floatingPointConfig->fpDataFormat != ADI_ADRV9025_FP_FORMAT_SIGN_SIGNIFICAND_EXP) && + (floatingPointConfig->fpDataFormat != ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + floatingPointConfig->fpDataFormat, + "Invalid floating point data format selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check floating point round mode is valid */ + if ((floatingPointConfig->fpRoundMode != ADI_ADRV9025_ROUND_TO_EVEN) && + (floatingPointConfig->fpRoundMode != ADI_ADRV9025_ROUNDTOWARDS_POSITIVE) && + (floatingPointConfig->fpRoundMode != ADI_ADRV9025_ROUNDTOWARDS_NEGATIVE) && + (floatingPointConfig->fpRoundMode != ADI_ADRV9025_ROUNDTOWARDS_ZERO) && + (floatingPointConfig->fpRoundMode != ADI_ADRV9025_ROUND_FROM_EVEN)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + floatingPointConfig->fpRoundMode, + "Invalid floating point round mode selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check floating point no. of exponent bits is valid */ + if ((floatingPointConfig->fpNumExpBits != ADI_ADRV9025_2_EXPONENTBITS) && + (floatingPointConfig->fpNumExpBits != ADI_ADRV9025_3_EXPONENTBITS) && + (floatingPointConfig->fpNumExpBits != ADI_ADRV9025_4_EXPONENTBITS) && + (floatingPointConfig->fpNumExpBits != ADI_ADRV9025_5_EXPONENTBITS)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + floatingPointConfig->fpNumExpBits, + "Invalid no. of floating point exponent bits selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check floating point attenuation steps are valid */ + if ((floatingPointConfig->fpAttenSteps != ADI_ADRV9025_FPATTEN_24DB) && + (floatingPointConfig->fpAttenSteps != ADI_ADRV9025_FPATTEN_18DB) && + (floatingPointConfig->fpAttenSteps != ADI_ADRV9025_FPATTEN_12DB) && + (floatingPointConfig->fpAttenSteps != ADI_ADRV9025_FPATTEN_6DB) && + (floatingPointConfig->fpAttenSteps != ADI_ADRV9025_FPATTEN_0DB) && + (floatingPointConfig->fpAttenSteps != ADI_ADRV9025_FPATTEN_MINUS6DB) && + (floatingPointConfig->fpAttenSteps != ADI_ADRV9025_FPATTEN_MINUS12DB) && + (floatingPointConfig->fpAttenSteps != ADI_ADRV9025_FPATTEN_MINUS18DB)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + floatingPointConfig->fpAttenSteps, + "Invalid floating point attenuation step selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check floating point encoded NaN selection is valid*/ + if ((floatingPointConfig->fpEncodeNan != ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE) && + (floatingPointConfig->fpEncodeNan != ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_ENABLE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + floatingPointConfig->fpEncodeNan, + "Invalid floating point encode NaN selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check floating point encoded NaN selection is valid*/ + if ((floatingPointConfig->fpHideLeadingOne != ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE) && + (floatingPointConfig->fpHideLeadingOne != ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_ENABLE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + floatingPointConfig->fpHideLeadingOne, + "Invalid floating point hide leading one selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_RxDataFormatSetIntegerRangeCheck(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + adi_adrv9025_RxDataFormatModes_e formatSelect, + adi_adrv9025_IntegerConfigSettings_t* integerConfigSettings, + adi_adrv9025_SlicerConfigSettings_t* slicerConfigSettings) +{ + static const uint8_t SOURCE_CTRL_RX_SLICER_POSN_4PIN_MODE = 0x0A; + static const uint8_t SOURCE_CTRL_RX_SLICER_POSN_3PIN_MODE = 0x0B; + static const uint8_t SOURCE_CTRL_UNUSED = 0x00; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t gpioSourceCtrl = 0; + uint8_t gpioSourceCtrl2 = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check integer format configuration struct is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + integerConfigSettings); + + /* Check slicer configuration struct is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + slicerConfigSettings); + + /* Check that internal slicer step sizes are correct */ + if ((formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) || + (formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) || + (formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO)) + { + /* Check that selected integer formatter internal slicer embedded bits mode is valid */ + if ((integerConfigSettings->intEmbeddedBits != ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS) && + (integerConfigSettings->intEmbeddedBits != ADI_ADRV9025_EMBED_1_SLICERBIT_AT_MSB) && + (integerConfigSettings->intEmbeddedBits != ADI_ADRV9025_EMBED_1_SLICERBIT_AT_LSB) && + (integerConfigSettings->intEmbeddedBits != ADI_ADRV9025_EMBED_2_SLICERBITS_AT_MSB_3_BIT_SLICER) && + (integerConfigSettings->intEmbeddedBits != ADI_ADRV9025_EMBED_2_SLICERBITS_AT_LSB_3_BIT_SLICER) && + (integerConfigSettings->intEmbeddedBits != ADI_ADRV9025_EMBED_2_SLICERBITS_AT_MSB_4_BIT_SLICER) && + (integerConfigSettings->intEmbeddedBits != ADI_ADRV9025_EMBED_2_SLICERBITS_AT_LSB_4_BIT_SLICER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + integerConfigSettings->intEmbeddedBits, + "Invalid integer formatter internal slicer embedded bits selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check that integer format resolution is valid */ + if ((integerConfigSettings->intSampleResolution != ADI_ADRV9025_INTEGER_12BIT_2SCOMP) && + (integerConfigSettings->intSampleResolution != ADI_ADRV9025_INTEGER_12BIT_SIGNED) && + (integerConfigSettings->intSampleResolution != ADI_ADRV9025_INTEGER_16BIT_2SCOMP) && + (integerConfigSettings->intSampleResolution != ADI_ADRV9025_INTEGER_16BIT_SIGNED) && + (integerConfigSettings->intSampleResolution != ADI_ADRV9025_INTEGER_24BIT_2SCOMP) && + (integerConfigSettings->intSampleResolution != ADI_ADRV9025_INTEGER_24BIT_SIGNED)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + integerConfigSettings->intSampleResolution, + "Invalid integer formatter sample resolution selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Embedding 1 bit slicer at MSB only supports 12 bit/16 bit/24 bit signed integer sample resolution */ + if ((integerConfigSettings->intEmbeddedBits == ADI_ADRV9025_EMBED_1_SLICERBIT_AT_MSB) && + (integerConfigSettings->intSampleResolution != ADI_ADRV9025_INTEGER_12BIT_SIGNED) && + (integerConfigSettings->intSampleResolution != ADI_ADRV9025_INTEGER_16BIT_SIGNED) && + (integerConfigSettings->intSampleResolution != ADI_ADRV9025_INTEGER_24BIT_SIGNED)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + integerConfigSettings->intSampleResolution, + "Invalid integer formatter sample resolution. Valid sample resolution is 12-bit signed for embedding 1 slicer bit at MSB"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Embedding 2 bit slicer at MSB for a 3-bit slicer mode only supports Signed representation in 16/24 bits */ + if (integerConfigSettings->intEmbeddedBits == ADI_ADRV9025_EMBED_2_SLICERBITS_AT_MSB_3_BIT_SLICER) + { + if ((integerConfigSettings->intSampleResolution != ADI_ADRV9025_INTEGER_16BIT_SIGNED) && + (integerConfigSettings->intSampleResolution != ADI_ADRV9025_INTEGER_24BIT_SIGNED)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + integerConfigSettings->intSampleResolution, + "Invalid integer formatter sample resolution. Valid sample resolution is 16/24-bit signed for embedding 2 slicer bits at MSB for a 3-bit slicer mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Embedding 2 bit slicer at MSB for a 4-bit slicer mode only supports Signed representation in 16/24 bits */ + if (integerConfigSettings->intEmbeddedBits == ADI_ADRV9025_EMBED_2_SLICERBITS_AT_MSB_4_BIT_SLICER) + { + if ((integerConfigSettings->intSampleResolution != ADI_ADRV9025_INTEGER_16BIT_SIGNED) && + (integerConfigSettings->intSampleResolution != ADI_ADRV9025_INTEGER_24BIT_SIGNED)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + integerConfigSettings->intSampleResolution, + "Invalid integer formatter sample resolution. Valid sample resolution is 16/24-bit signed for embedding 2 slicer bits at MSB for a 4-bit slicer mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Check that integer format parity is valid */ + if ((integerConfigSettings->intParity != ADI_ADRV9025_3BIT_SLICER_EVEN_PARITY) && + (integerConfigSettings->intParity != ADI_ADRV9025_3BIT_SLICER_ODD_PARITY) && + (integerConfigSettings->intParity != ADI_ADRV9025_NO_PARITY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + integerConfigSettings->intParity, + "Invalid integer formatter parity option selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check that the use case is valid for embedding parity bit */ + if ((integerConfigSettings->intParity == ADI_ADRV9025_3BIT_SLICER_EVEN_PARITY) || (integerConfigSettings->intParity == + ADI_ADRV9025_3BIT_SLICER_ODD_PARITY)) + { + /* Parity is valid only in 3 bit internal embedded slicer mode */ + if (formatSelect != ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + formatSelect, + "Invalid integer formatter mode selected for parity support. Parity is supported only in 3 bit internal slicer modes"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Parity is valid only in 3 bit slicer mode */ + if ((integerConfigSettings->intEmbeddedBits != ADI_ADRV9025_EMBED_2_SLICERBITS_AT_MSB_3_BIT_SLICER) && + (integerConfigSettings->intEmbeddedBits != ADI_ADRV9025_EMBED_2_SLICERBITS_AT_LSB_3_BIT_SLICER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + formatSelect, + "Invalid integer formatter mode selected for parity support. Parity is supported only in 3 bit internal slicer modes"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Parity is valid only in 3 bit embedded slicer mode. 12 bit resolution does not support 3 bit parity */ + if ((integerConfigSettings->intSampleResolution == ADI_ADRV9025_INTEGER_12BIT_2SCOMP) || + (integerConfigSettings->intSampleResolution == ADI_ADRV9025_INTEGER_12BIT_SIGNED)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + integerConfigSettings->intSampleResolution, + "Invalid integer formatter sampling resolution mode for parity config. Parity is supported only for 16 and 24 bit resolutions"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if ((slicerConfigSettings->intSlicerStepSize != ADI_ADRV9025_INTSLICER_STEPSIZE_1DB) && + (slicerConfigSettings->intSlicerStepSize != ADI_ADRV9025_INTSLICER_STEPSIZE_2DB) && + (slicerConfigSettings->intSlicerStepSize != ADI_ADRV9025_INTSLICER_STEPSIZE_3DB) && + (slicerConfigSettings->intSlicerStepSize != ADI_ADRV9025_INTSLICER_STEPSIZE_4DB) && + (slicerConfigSettings->intSlicerStepSize != ADI_ADRV9025_INTSLICER_STEPSIZE_6DB) && + (slicerConfigSettings->intSlicerStepSize != ADI_ADRV9025_INTSLICER_STEPSIZE_8DB)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + slicerConfigSettings->intSlicerStepSize, + "Invalid internal slicer step size selected for integer format internal slicer mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check the source ctrl on Rx Slicer Posn observation GPIOs for 4 Pin mode */ + if (formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + if (((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX1) == (uint32_t)ADI_ADRV9025_ORX1) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX2) == (uint32_t)ADI_ADRV9025_ORX2) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX3) == (uint32_t)ADI_ADRV9025_ORX3) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX4) == (uint32_t)ADI_ADRV9025_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "ORx channel is only supported for ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that Rx1 slicer position GPIO source ctrl is not set to another feature*/ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX1) == (uint32_t)ADI_ADRV9025_RX1) + { + recoveryAction = adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &gpioSourceCtrl); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((gpioSourceCtrl != SOURCE_CTRL_UNUSED) && + (gpioSourceCtrl != SOURCE_CTRL_RX_SLICER_POSN_4PIN_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioSourceCtrl, + "GPIO for Rx1 slicer position output in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Check that Rx2 slicer position GPIO source ctrl is not set to another feature*/ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX2) == (uint32_t)ADI_ADRV9025_RX2) + { + recoveryAction = adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &gpioSourceCtrl); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((gpioSourceCtrl != SOURCE_CTRL_UNUSED) && + (gpioSourceCtrl != SOURCE_CTRL_RX_SLICER_POSN_4PIN_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioSourceCtrl, + "GPIO for Rx2 slicer position output in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Check that Rx3 slicer position GPIO source ctrl is not set to another feature*/ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX3) == (uint32_t)ADI_ADRV9025_RX3) + { + recoveryAction = adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &gpioSourceCtrl); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((gpioSourceCtrl != SOURCE_CTRL_UNUSED) && + (gpioSourceCtrl != SOURCE_CTRL_RX_SLICER_POSN_4PIN_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioSourceCtrl, + "GPIO for Rx3 slicer position output in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Check that Rx4 slicer position GPIO source ctrl is not set to another feature*/ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX4) == (uint32_t)ADI_ADRV9025_RX4) + { + recoveryAction = adrv9025_CoreGpioLowerByteLowerNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &gpioSourceCtrl); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((gpioSourceCtrl != SOURCE_CTRL_UNUSED) && + (gpioSourceCtrl != SOURCE_CTRL_RX_SLICER_POSN_4PIN_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioSourceCtrl, + "GPIO for Rx4 slicer position output in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + /*Check the source ctrl on Rx Slicer Posn observation GPIOs for 3 Pin mode*/ + if (formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + if (((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX1) == (uint32_t)ADI_ADRV9025_ORX1) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX2) == (uint32_t)ADI_ADRV9025_ORX2) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX3) == (uint32_t)ADI_ADRV9025_ORX3) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX4) == (uint32_t)ADI_ADRV9025_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "ORx channel is only supported for ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that Rx1 slicer position GPIO source ctrl is not set to another feature*/ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX1) == (uint32_t)ADI_ADRV9025_RX1) + { + recoveryAction = adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &gpioSourceCtrl); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &gpioSourceCtrl2); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((gpioSourceCtrl != SOURCE_CTRL_UNUSED) && + (gpioSourceCtrl != SOURCE_CTRL_RX_SLICER_POSN_3PIN_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioSourceCtrl, + "GPIO for Rx1 slicer position output in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((gpioSourceCtrl2 != SOURCE_CTRL_UNUSED) && + (gpioSourceCtrl2 != SOURCE_CTRL_RX_SLICER_POSN_3PIN_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioSourceCtrl2, + "GPIO for Rx1 slicer position output in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Check that Rx2 slicer position GPIO source ctrl is not set to another feature*/ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX2) == (uint32_t)ADI_ADRV9025_RX2) + { + recoveryAction = adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &gpioSourceCtrl); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((gpioSourceCtrl != SOURCE_CTRL_UNUSED) && + (gpioSourceCtrl != SOURCE_CTRL_RX_SLICER_POSN_3PIN_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioSourceCtrl, + "GPIO for Rx2 slicer position output in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Check that Rx3 slicer position GPIO source ctrl is not set to another feature*/ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX3) == (uint32_t)ADI_ADRV9025_RX3) + { + recoveryAction = adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &gpioSourceCtrl); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((gpioSourceCtrl != SOURCE_CTRL_UNUSED) && + (gpioSourceCtrl != SOURCE_CTRL_RX_SLICER_POSN_3PIN_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioSourceCtrl, + "GPIO for Rx3 slicer position output in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Check that Rx4 slicer position GPIO source ctrl is not set to another feature*/ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX4) == (uint32_t)ADI_ADRV9025_RX4) + { + recoveryAction = adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &gpioSourceCtrl); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpioExtraBitsSourceControlBfGet(device, + ADRV9025_BF_CORE, + &gpioSourceCtrl2); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((gpioSourceCtrl != SOURCE_CTRL_UNUSED) && + (gpioSourceCtrl != SOURCE_CTRL_RX_SLICER_POSN_3PIN_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioSourceCtrl, + "GPIO for Rx4 slicer position output in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((gpioSourceCtrl2 != SOURCE_CTRL_UNUSED) && + (gpioSourceCtrl2 != SOURCE_CTRL_RX_SLICER_POSN_3PIN_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioSourceCtrl, + "GPIO for Rx4 slicer position output in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + } + + else if (formatSelect == ADI_ADRV9025_GAIN_WITH_EXTERNAL_SLICER) + { + if (((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX1) == (uint32_t)ADI_ADRV9025_ORX1) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX2) == (uint32_t)ADI_ADRV9025_ORX2) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX3) == (uint32_t)ADI_ADRV9025_ORX3) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX4) == (uint32_t)ADI_ADRV9025_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "ORx channel is only supported for ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check that if the format selected is external slicer, external slicer step sizes are valid */ + if ((slicerConfigSettings->extSlicerStepSize != ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB) && + (slicerConfigSettings->extSlicerStepSize != ADI_ADRV9025_EXTSLICER_STEPSIZE_2DB) && + (slicerConfigSettings->extSlicerStepSize != ADI_ADRV9025_EXTSLICER_STEPSIZE_3DB) && + (slicerConfigSettings->extSlicerStepSize != ADI_ADRV9025_EXTSLICER_STEPSIZE_4DB) && + (slicerConfigSettings->extSlicerStepSize != ADI_ADRV9025_EXTSLICER_STEPSIZE_6DB)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + slicerConfigSettings->extSlicerStepSize, + "Invalid external slicer step size selected for integer format external slicer mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that if an external slicer mode for Rx1 is selected, the corresponding external slicer GPIO is valid */ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX1) == (uint32_t)ADI_ADRV9025_RX1) + { + if (slicerConfigSettings->rx1ExtSlicerGpioSelect >= ADI_ADRV9025_EXTSLICER_RX_GPIO_INVALID) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + slicerConfigSettings->rx1ExtSlicerGpioSelect, + "Invalid external slicer GPIO pins selected for Rx1 integer format external slicer mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Check that if an external slicer mode for Rx2 is selected, the corresponding external slicer GPIO is valid */ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX2) == (uint32_t)ADI_ADRV9025_RX2) + { + if (slicerConfigSettings->rx2ExtSlicerGpioSelect >= ADI_ADRV9025_EXTSLICER_RX_GPIO_INVALID) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + slicerConfigSettings->rx2ExtSlicerGpioSelect, + "Invalid external slicer GPIO pins selected for Rx2 integer format external slicer mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Check that if an external slicer mode for Rx3 is selected, the corresponding external slicer GPIO is valid */ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX3) == (uint32_t)ADI_ADRV9025_RX3) + { + if (slicerConfigSettings->rx3ExtSlicerGpioSelect >= ADI_ADRV9025_EXTSLICER_RX_GPIO_INVALID) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + slicerConfigSettings->rx3ExtSlicerGpioSelect, + "Invalid external slicer GPIO pins selected for Rx3 integer format external slicer mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Check that if an external slicer mode for Rx4 is selected, the corresponding external slicer GPIO is valid */ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX4) == (uint32_t)ADI_ADRV9025_RX4) + { + if (slicerConfigSettings->rx4ExtSlicerGpioSelect >= ADI_ADRV9025_EXTSLICER_RX_GPIO_INVALID) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + slicerConfigSettings->rx4ExtSlicerGpioSelect, + "Invalid external slicer GPIO pins selected for Rx4 integer format external slicer mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxDataFormatSetEmbOvldMonitorRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_EmbOverloadMonitorConfigSettings_t* embOvldConfigSettings, + adi_adrv9025_RxIntSampleResolution_e intSampleResolution) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check embedded overload monitor configuration struct is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + embOvldConfigSettings); + + if (intSampleResolution != ADI_ADRV9025_INTEGER_16BIT_2SCOMP) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + intSampleResolution, + "Embedded overload monitoring Rx data format is only supported with integer 16Bit - 2s Complement format"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((embOvldConfigSettings->embeddedMonitorSrcLsbI != ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED) && + (embOvldConfigSettings->embeddedMonitorSrcLsbI != ADI_ADRV9025_RX_EMB_MON_SRC_APD_HIGH_THRESH) && + (embOvldConfigSettings->embeddedMonitorSrcLsbI != ADI_ADRV9025_RX_EMB_MON_SRC_APD_LOW_THRESH) && + (embOvldConfigSettings->embeddedMonitorSrcLsbI != ADI_ADRV9025_RX_EMB_MON_SRC_HB2_HIGH_THRESH) && + (embOvldConfigSettings->embeddedMonitorSrcLsbI != ADI_ADRV9025_RX_EMB_MON_SRC_HB2_LOW_THRESH)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + embOvldConfigSettings->embeddedMonitorSrcLsbI, + "Invalid embedded monitor source selected to be embedded at LSB posn - I sample"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneI != ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED) && + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneI != ADI_ADRV9025_RX_EMB_MON_SRC_APD_HIGH_THRESH) && + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneI != ADI_ADRV9025_RX_EMB_MON_SRC_APD_LOW_THRESH) && + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneI != ADI_ADRV9025_RX_EMB_MON_SRC_HB2_HIGH_THRESH) && + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneI != ADI_ADRV9025_RX_EMB_MON_SRC_HB2_LOW_THRESH)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneI, + "Invalid embedded monitor source selected to be embedded at LSB + 1 posn - I sample"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((embOvldConfigSettings->embeddedMonitorSrcLsbQ != ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED) && + (embOvldConfigSettings->embeddedMonitorSrcLsbQ != ADI_ADRV9025_RX_EMB_MON_SRC_APD_HIGH_THRESH) && + (embOvldConfigSettings->embeddedMonitorSrcLsbQ != ADI_ADRV9025_RX_EMB_MON_SRC_APD_LOW_THRESH) && + (embOvldConfigSettings->embeddedMonitorSrcLsbQ != ADI_ADRV9025_RX_EMB_MON_SRC_HB2_HIGH_THRESH) && + (embOvldConfigSettings->embeddedMonitorSrcLsbQ != ADI_ADRV9025_RX_EMB_MON_SRC_HB2_LOW_THRESH)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + embOvldConfigSettings->embeddedMonitorSrcLsbQ, + "Invalid embedded monitor source selected to be embedded at LSB posn - Q sample"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneQ != ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED) && + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneQ != ADI_ADRV9025_RX_EMB_MON_SRC_APD_HIGH_THRESH) && + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneQ != ADI_ADRV9025_RX_EMB_MON_SRC_APD_LOW_THRESH) && + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneQ != ADI_ADRV9025_RX_EMB_MON_SRC_HB2_HIGH_THRESH) && + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneQ != ADI_ADRV9025_RX_EMB_MON_SRC_HB2_LOW_THRESH)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneQ, + "Invalid embedded monitor source selected to be embedded at LSB + 1 posn - Q sample"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((embOvldConfigSettings->embeddedMonitorSrcLsbI == ADI_ADRV9025_RX_EMB_MON_SRC_APD_HIGH_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbQ == ADI_ADRV9025_RX_EMB_MON_SRC_APD_HIGH_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneI == ADI_ADRV9025_RX_EMB_MON_SRC_APD_HIGH_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneQ == ADI_ADRV9025_RX_EMB_MON_SRC_APD_HIGH_THRESH)) + { + if ((embOvldConfigSettings->embeddedMonitorApdHighSrcSel != ADI_ADRV9025_APD_HIGH_SRC_UPPER_LEVEL_BLOCKER_EXCEEDED) && + (embOvldConfigSettings->embeddedMonitorApdHighSrcSel != ADI_ADRV9025_APD_HIGH_SRC_UPPER_LEVEL_BLOCKER_CNTR_EXCEEDED)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + embOvldConfigSettings->embeddedMonitorApdHighSrcSel, + "Analog Peak Detector high thresh selected for embedded monitoring but APD high source is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if ((embOvldConfigSettings->embeddedMonitorSrcLsbI == ADI_ADRV9025_RX_EMB_MON_SRC_APD_LOW_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbQ == ADI_ADRV9025_RX_EMB_MON_SRC_APD_LOW_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneI == ADI_ADRV9025_RX_EMB_MON_SRC_APD_LOW_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneQ == ADI_ADRV9025_RX_EMB_MON_SRC_APD_LOW_THRESH)) + { + if ((embOvldConfigSettings->embeddedMonitorApdLowSrcSel != ADI_ADRV9025_APD_LOW_SRC_LOWER_LEVEL_BLOCKER_EXCEEDED) && + (embOvldConfigSettings->embeddedMonitorApdLowSrcSel != ADI_ADRV9025_APD_LOW_SRC_LOWER_LEVEL_BLOCKER_CNTR_EXCEEDED)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + embOvldConfigSettings->embeddedMonitorApdLowSrcSel, + "Analog Peak Detector low thresh selected for embedded monitoring but APD low source is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if ((embOvldConfigSettings->embeddedMonitorSrcLsbI == ADI_ADRV9025_RX_EMB_MON_SRC_HB2_HIGH_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbQ == ADI_ADRV9025_RX_EMB_MON_SRC_HB2_HIGH_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneI == ADI_ADRV9025_RX_EMB_MON_SRC_HB2_HIGH_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneQ == ADI_ADRV9025_RX_EMB_MON_SRC_HB2_HIGH_THRESH)) + { + if ((embOvldConfigSettings->embeddedMonitorHb2HighSrcSel != ADI_ADRV9025_HB2_HIGH_SRC_OVRG_HIGH) && + (embOvldConfigSettings->embeddedMonitorHb2HighSrcSel != ADI_ADRV9025_HB2_HIGH_SRC_OVRG_HIGH_CNTR_EXCEEDED)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + embOvldConfigSettings->embeddedMonitorHb2HighSrcSel, + "Digital HB2 Peak Detector high thresh selected for embedded monitoring but HB2 high source is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if ((embOvldConfigSettings->embeddedMonitorSrcLsbI == ADI_ADRV9025_RX_EMB_MON_SRC_HB2_LOW_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbQ == ADI_ADRV9025_RX_EMB_MON_SRC_HB2_LOW_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneI == ADI_ADRV9025_RX_EMB_MON_SRC_HB2_LOW_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneQ == ADI_ADRV9025_RX_EMB_MON_SRC_HB2_LOW_THRESH)) + { + if ((embOvldConfigSettings->embeddedMonitorHb2LowSrcSel != ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW) && + (embOvldConfigSettings->embeddedMonitorHb2LowSrcSel != ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT0) && + (embOvldConfigSettings->embeddedMonitorHb2LowSrcSel != ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1) && + (embOvldConfigSettings->embeddedMonitorHb2LowSrcSel != ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_THRESH_CNTR_EXCEEDED) && + (embOvldConfigSettings->embeddedMonitorHb2LowSrcSel != ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT0_THRESH_CNTR_EXCEEDED) && + (embOvldConfigSettings->embeddedMonitorHb2LowSrcSel != ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + embOvldConfigSettings->embeddedMonitorHb2LowSrcSel, + "Digital HB2 Peak Detector low thresh selected for embedded monitoring but HB2 low source is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxDataFormatSelectGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxDataFormatModes_e* rxDataFormat) +{ + static const uint8_t ENABLE_FLOATING_POINT_FORMAT = 1; + static const uint8_t ENABLE_GAIN_COMPENSATION = 1; + static const uint8_t ENABLE_RX_EXT_SLICER = 1; + static const uint8_t ENABLE_RX_INT_EMBEDDED_SLICER = 1; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t gainCompEn = 0; + uint8_t floatingPointEn = 0; + uint8_t rxExtSlicerModeEn = 0; + uint8_t intEmbedSlicer = 0; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_RX_CH0; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddr = ADRV9025_BF_ORX_CH0; + adi_adrv9025_EmbOverloadMonitorConfigSettings_t embOvldMonitorSettings = {ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check floating point configuration struct is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + rxDataFormat); + + if ((rxChannel == ADI_ADRV9025_RX1) || + (rxChannel == ADI_ADRV9025_RX2) || + (rxChannel == ADI_ADRV9025_RX3) || + (rxChannel == ADI_ADRV9025_RX4)) + { + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + rxChannel, + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxGainCompEnableBfGet(device, + rxChannelBitfieldAddr, + &gainCompEn); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (gainCompEn != ENABLE_GAIN_COMPENSATION) + { + recoveryAction = adrv9025_RxDataFormatEmbOvldMonitorGet(device, + rxChannel, + &embOvldMonitorSettings); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((embOvldMonitorSettings.embeddedMonitorSrcLsbI == ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED) && + (embOvldMonitorSettings.embeddedMonitorSrcLsbQ == ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED) && + (embOvldMonitorSettings.embeddedMonitorSrcLsbPlusOneI == ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED) && + (embOvldMonitorSettings.embeddedMonitorSrcLsbPlusOneQ == ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED)) + { + *rxDataFormat = ADI_ADRV9025_GAIN_COMPENSATION_DISABLED; + } + else + { + *rxDataFormat = ADI_ADRV9025_EMBED_OVERLOAD_MONITOR_DATA; + } + } + else + { + recoveryAction = adrv9025_RxFpEnBfGet(device, + rxChannelBitfieldAddr, + &floatingPointEn); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (floatingPointEn == ENABLE_FLOATING_POINT_FORMAT) + { + *rxDataFormat = ADI_ADRV9025_GAIN_WITH_FLOATING_POINT; + } + else + { + recoveryAction = adrv9025_RxSlicerPinControlModeBfGet(device, + rxChannelBitfieldAddr, + &rxExtSlicerModeEn); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (rxExtSlicerModeEn == ENABLE_RX_EXT_SLICER) + { + *rxDataFormat = ADI_ADRV9025_GAIN_WITH_EXTERNAL_SLICER; + } + else + { + recoveryAction = adrv9025_RxIntEmbedSlicerBfGet(device, + rxChannelBitfieldAddr, + &intEmbedSlicer); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (intEmbedSlicer == ENABLE_RX_INT_EMBEDDED_SLICER) + { + *rxDataFormat = ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO; + } + else + { + recoveryAction = adrv9025_RxInternalSlicerGpioEnableGet(device, + rxChannel, + rxDataFormat, + NULL); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + } + } + else if ((rxChannel == ADI_ADRV9025_ORX1) || + (rxChannel == ADI_ADRV9025_ORX2) || + (rxChannel == ADI_ADRV9025_ORX3) || + (rxChannel == ADI_ADRV9025_ORX4)) + { + recoveryAction = adrv9025_OrxBitfieldAddressGet(device, + rxChannel, + &orxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxGainCompEnableBfGet(device, + orxChannelBitfieldAddr, + &gainCompEn); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (gainCompEn != ENABLE_GAIN_COMPENSATION) + { + *rxDataFormat = ADI_ADRV9025_GAIN_COMPENSATION_DISABLED; + } + else + { + recoveryAction = adrv9025_OrxFpEnBfGet(device, + orxChannelBitfieldAddr, + &floatingPointEn); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (floatingPointEn == ENABLE_FLOATING_POINT_FORMAT) + { + *rxDataFormat = ADI_ADRV9025_GAIN_WITH_FLOATING_POINT; + } + else + { + recoveryAction = adrv9025_OrxIntEmbedSlicerBfGet(device, + orxChannelBitfieldAddr, + &intEmbedSlicer); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (intEmbedSlicer == ENABLE_RX_INT_EMBEDDED_SLICER) + { + *rxDataFormat = ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO; + } + else + { + *rxDataFormat = ADI_ADRV9025_GAIN_COMPENSATION_DISABLED; + } + } + } + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, rxChannel, + "rxChannel input parameter is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + + } + + + return recoveryAction; +} + +int32_t adrv9025_RxDataFormatFloatingPointSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + adi_adrv9025_FloatingPointConfigSettings_t* floatingPointConfig) +{ + static const adi_adrv9025_RxChannels_e RX_CHANNEL_ARR[] = {ADI_ADRV9025_RX1, ADI_ADRV9025_RX2, ADI_ADRV9025_RX3, ADI_ADRV9025_RX4}; + static const adi_adrv9025_RxChannels_e ORX_CHANNEL_ARR[] = {ADI_ADRV9025_ORX1, ADI_ADRV9025_ORX2, ADI_ADRV9025_ORX3, ADI_ADRV9025_ORX4}; + static const uint32_t RX_CHANNEL_ARR_SIZE = sizeof(RX_CHANNEL_ARR) / sizeof(RX_CHANNEL_ARR[0]); + static const uint32_t ORX_CHANNEL_ARR_SIZE = sizeof(ORX_CHANNEL_ARR) / sizeof(ORX_CHANNEL_ARR[0]); + static const uint8_t ENABLE_FLOATING_POINT_FORMAT = 1; + static const uint8_t ENABLE_GAIN_COMPENSATION = 1; + static const uint8_t DEFAULT_INT_DATA_FORMAT = 0; + static const uint8_t DEFAULT_INT_DATA_RESOLUTION = 1; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxChannelArrIndex = 0; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_RX_CH0; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddr = ADRV9025_BF_ORX_CH0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check floating point configuration struct is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + floatingPointConfig); + + /*Disable gain compensation and set integer format register to default*/ + recoveryAction = adrv9025_RxDataFormatGainCompDisable(device, + rxChannelMask, + DEFAULT_INT_DATA_FORMAT, + DEFAULT_INT_DATA_RESOLUTION); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Iterate through channel mask and if set configure the corresponding Rx floating point formatter*/ + for (rxChannelArrIndex = 0; rxChannelArrIndex < RX_CHANNEL_ARR_SIZE; rxChannelArrIndex++) + { + if ((rxChannelMask & (uint32_t)RX_CHANNEL_ARR[rxChannelArrIndex]) == (uint32_t)RX_CHANNEL_ARR[rxChannelArrIndex]) + { + /*If an Rx channel mask is set, resolve the corresponding Rx Bitfield Address*/ + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + RX_CHANNEL_ARR[rxChannelArrIndex], + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Floating Point Configs*/ + recoveryAction = adrv9025_RxFpRoundModeBfSet(device, + rxChannelBitfieldAddr, + (adrv9025_BfRxFpRoundMode_e)floatingPointConfig->fpRoundMode); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxFpFloatDataFormatBfSet(device, + rxChannelBitfieldAddr, + (uint8_t)floatingPointConfig->fpDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxFpNanEncEnBfSet(device, + rxChannelBitfieldAddr, + (uint8_t)floatingPointConfig->fpEncodeNan); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxFpExponentBitsBfSet(device, + rxChannelBitfieldAddr, + (adrv9025_BfRxFpExponentBits_e)floatingPointConfig->fpNumExpBits); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxFpHideLeadingOnesBfSet(device, + rxChannelBitfieldAddr, + (uint8_t)floatingPointConfig->fpHideLeadingOne); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Floating point attenuation*/ + recoveryAction = adrv9025_RxFpIntDataAttenBfSet(device, + rxChannelBitfieldAddr, + (uint8_t)floatingPointConfig->fpAttenSteps); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Enable Floating Point Format on the requested channel*/ + recoveryAction = adrv9025_RxFpEnBfSet(device, + rxChannelBitfieldAddr, + ENABLE_FLOATING_POINT_FORMAT); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Enable Gain Compensation*/ + recoveryAction = adrv9025_RxGainCompEnableBfSet(device, + rxChannelBitfieldAddr, + ENABLE_GAIN_COMPENSATION); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Iterate through channel mask and if set configure the corresponding ORx floating point formatter*/ + for (rxChannelArrIndex = 0; rxChannelArrIndex < ORX_CHANNEL_ARR_SIZE; rxChannelArrIndex++) + { + if ((rxChannelMask & (uint32_t)ORX_CHANNEL_ARR[rxChannelArrIndex]) == (uint32_t)ORX_CHANNEL_ARR[rxChannelArrIndex]) + { + /*If an Rx channel mask is set, resolve the corresponding Rx Bitfield Address*/ + recoveryAction = adrv9025_OrxBitfieldAddressGet(device, + ORX_CHANNEL_ARR[rxChannelArrIndex], + &orxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Floating Point Configs*/ + recoveryAction = adrv9025_OrxFpRoundModeBfSet(device, + orxChannelBitfieldAddr, + (adrv9025_BfOrxFpRoundMode_e)floatingPointConfig->fpRoundMode); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxFpFloatDataFormatBfSet(device, + orxChannelBitfieldAddr, + (uint8_t)floatingPointConfig->fpDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxFpNanEncEnBfSet(device, + orxChannelBitfieldAddr, + (uint8_t)floatingPointConfig->fpEncodeNan); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxFpExponentBitsBfSet(device, + orxChannelBitfieldAddr, + (adrv9025_BfOrxFpExponentBits_e)floatingPointConfig->fpNumExpBits); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxFpHideLeadingOnesBfSet(device, + orxChannelBitfieldAddr, + (uint8_t)floatingPointConfig->fpHideLeadingOne); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Floating point attenuation*/ + recoveryAction = adrv9025_OrxFpIntDataAttenBfSet(device, + orxChannelBitfieldAddr, + (uint8_t)floatingPointConfig->fpAttenSteps); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Enable Floating Point Format on the requested channel*/ + recoveryAction = adrv9025_OrxFpEnBfSet(device, + orxChannelBitfieldAddr, + ENABLE_FLOATING_POINT_FORMAT); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Enable Gain Compensation*/ + recoveryAction = adrv9025_OrxGainCompEnableBfSet(device, + orxChannelBitfieldAddr, + ENABLE_GAIN_COMPENSATION); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxDataFormatFloatingPointGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_FloatingPointConfigSettings_t* floatingPointConfig) + +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_ALL_RX_CHANNELS; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddr = ADRV9025_BF_ALL_ORX_CHANNELS; + adrv9025_BfRxFpRoundMode_e fpRoundModeBf = ADRV9025_BF_RX_ROUNDTIESTOEVEN; + uint8_t fpDataFormatBf = 0; + uint8_t fpEncodeNanBf = 0; + adrv9025_BfRxFpExponentBits_e fpNumExpBitsBf = ADRV9025_BF_RX_RX1_EXP_2; + uint8_t fpHideLeadingOneBf = 0; + uint8_t fpAttenStepsBf = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check rx bitfield channel address pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + floatingPointConfig); + + if ((rxChannel == ADI_ADRV9025_RX1) || + (rxChannel == ADI_ADRV9025_RX2) || + (rxChannel == ADI_ADRV9025_RX3) || + (rxChannel == ADI_ADRV9025_RX4)) + { + /*Resolve bit field base address for the channel*/ + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + rxChannel, + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Get Floating Point Configs*/ + /*Not sending references of struct members directly to the Get function as it updates only LSB (1byte) + of the members where as struct members are 4 bytes wide by default unless compiler settings are changed*/ + recoveryAction = adrv9025_RxFpRoundModeBfGet(device, + rxChannelBitfieldAddr, + &fpRoundModeBf); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxFpFloatDataFormatBfGet(device, + rxChannelBitfieldAddr, + &fpDataFormatBf); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxFpNanEncEnBfGet(device, + rxChannelBitfieldAddr, + &fpEncodeNanBf); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxFpExponentBitsBfGet(device, + rxChannelBitfieldAddr, + &fpNumExpBitsBf); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxFpHideLeadingOnesBfGet(device, + rxChannelBitfieldAddr, + &fpHideLeadingOneBf); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Get Floating point attenuation*/ + recoveryAction = adrv9025_RxFpIntDataAttenBfGet(device, + rxChannelBitfieldAddr, + &fpAttenStepsBf); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if ((rxChannel == ADI_ADRV9025_ORX1) || + (rxChannel == ADI_ADRV9025_ORX2) || + (rxChannel == ADI_ADRV9025_ORX3) || + (rxChannel == ADI_ADRV9025_ORX4)) + { + /*Resolve bit field base address for the channel*/ + recoveryAction = adrv9025_OrxBitfieldAddressGet(device, + rxChannel, + &orxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Get Floating Point Configs*/ + /*Not sending references of struct members directly to the Get function as it updates only LSB (1byte) + of the members where as struct members are 4 bytes wide by default unless compiler settings are changed*/ + recoveryAction = adrv9025_OrxFpRoundModeBfGet(device, + orxChannelBitfieldAddr, + (adrv9025_BfOrxFpRoundMode_e*)&fpRoundModeBf); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxFpFloatDataFormatBfGet(device, + orxChannelBitfieldAddr, + &fpDataFormatBf); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxFpNanEncEnBfGet(device, + orxChannelBitfieldAddr, + &fpEncodeNanBf); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxFpExponentBitsBfGet(device, + orxChannelBitfieldAddr, + (adrv9025_BfOrxFpExponentBits_e*)&fpNumExpBitsBf); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxFpHideLeadingOnesBfGet(device, + orxChannelBitfieldAddr, + &fpHideLeadingOneBf); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Get Floating point attenuation*/ + recoveryAction = adrv9025_OrxFpIntDataAttenBfGet(device, + orxChannelBitfieldAddr, + &fpAttenStepsBf); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Update the structure with read back data*/ + floatingPointConfig->fpRoundMode = (adi_adrv9025_FpRoundModes_e)fpRoundModeBf; + floatingPointConfig->fpDataFormat = (adi_adrv9025_FpFloatDataFormat_e)fpDataFormatBf; + floatingPointConfig->fpEncodeNan = (adi_adrv9025_FpNanEncode_e)fpEncodeNanBf; + floatingPointConfig->fpNumExpBits = (adi_adrv9025_FpExponentModes_e)fpNumExpBitsBf; + floatingPointConfig->fpHideLeadingOne = (adi_adrv9025_FpHideLeadingOne_e)fpHideLeadingOneBf; + floatingPointConfig->fpAttenSteps = (adi_adrv9025_FpAttenSteps_e)fpAttenStepsBf; + + return recoveryAction; +} + +int32_t adrv9025_RxDataFormatIntegerSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + adi_adrv9025_RxDataFormatModes_e formatSelect, + adi_adrv9025_IntegerConfigSettings_t* integerConfigSettings, + adi_adrv9025_SlicerConfigSettings_t* slicerConfigSettings) + +{ + static const adi_adrv9025_RxChannels_e RX_CHANNEL_ARR[] = {ADI_ADRV9025_RX1, ADI_ADRV9025_RX2, ADI_ADRV9025_RX3, ADI_ADRV9025_RX4}; + static const adi_adrv9025_RxChannels_e ORX_CHANNEL_ARR[] = {ADI_ADRV9025_ORX1, ADI_ADRV9025_ORX2, ADI_ADRV9025_ORX3, ADI_ADRV9025_ORX4}; + static const uint32_t RX_CHANNEL_ARR_SIZE = sizeof(RX_CHANNEL_ARR) / sizeof(RX_CHANNEL_ARR[0]); + static const uint32_t ORX_CHANNEL_ARR_SIZE = sizeof(ORX_CHANNEL_ARR) / sizeof(ORX_CHANNEL_ARR[0]); + static const uint8_t INT_DATA_FORMAT_2S_COMPLEMENT = 0; + static const uint8_t INT_DATA_RESOLUTION_16BITS = 1; + static const uint8_t INT_EMBED_SLICER_DISABLE = 0; + static const uint8_t INT_EMBED_SLICER_POS_MSB = 0; + static const uint8_t INT_EMBED_SLICER_2_BITS = 0; + static const uint8_t INT_PARTIY_SUPPORT_DISABLE = 0; + static const uint8_t INT_PARITY_EVEN = 0; + static const uint8_t ENABLE_GAIN_COMPENSATION = 1; + static const uint8_t SLICER_PIN_CTRL_MODE_INTERNAL = 0; + static const uint8_t SLICER_PIN_CTRL_MODE_EXTERNAL = 1; + static const uint8_t DEFAULT_INT_DATA_FORMAT = 0; + static const uint8_t DEFAULT_INT_DATA_RESOLUTION = 1; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxChannelArrIndex = 0; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_ALL_RX_CHANNELS; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddr = ADRV9025_BF_ALL_ORX_CHANNELS; + uint8_t intEvenParity = INT_PARITY_EVEN; + uint8_t intParitySupport = INT_PARTIY_SUPPORT_DISABLE; + uint8_t intEmbedSlicerNumber = INT_EMBED_SLICER_2_BITS; + uint8_t intEmbedSlicerPos = INT_EMBED_SLICER_POS_MSB; + uint8_t intEmbedSlicer = INT_EMBED_SLICER_DISABLE; + uint8_t intDataResolution = INT_DATA_RESOLUTION_16BITS; + uint8_t intDataFormat = INT_DATA_FORMAT_2S_COMPLEMENT; + uint8_t slicerPinCtrlMode = SLICER_PIN_CTRL_MODE_INTERNAL; + uint8_t slicer3bitModeEn = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check integer format configuration struct is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + integerConfigSettings); + + /* Check slicer configuration struct is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + slicerConfigSettings); + + /*Disable Gain Compensation and formatter settings for requested channels*/ + recoveryAction = adrv9025_RxDataFormatGainCompDisable(device, + rxChannelMask, + DEFAULT_INT_DATA_FORMAT, + DEFAULT_INT_DATA_RESOLUTION); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Iterate through channel mask and if set configure integer formatter settings on the corresponding Rx channel*/ + for (rxChannelArrIndex = 0; rxChannelArrIndex < RX_CHANNEL_ARR_SIZE; rxChannelArrIndex++) + { + if ((rxChannelMask & (uint32_t)RX_CHANNEL_ARR[rxChannelArrIndex]) == (uint32_t)RX_CHANNEL_ARR[rxChannelArrIndex]) + { + /*If an Rx channel mask bit is set, resolve the corresponding Rx Bitfield Address*/ + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + RX_CHANNEL_ARR[rxChannelArrIndex], + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* If external slicer selected, resolve GPIOs and ensure that GPIOs are not already in use */ + if (formatSelect == ADI_ADRV9025_GAIN_WITH_EXTERNAL_SLICER) + { + recoveryAction = adrv9025_RxExternalSlicerGpioEnable(device, + RX_CHANNEL_ARR[rxChannelArrIndex], + slicerConfigSettings); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxExternalSlicerPinControlStepBfSet(device, + rxChannelBitfieldAddr, + (uint8_t)slicerConfigSettings->extSlicerStepSize); + ADI_ERROR_RETURN(device->common.error.newAction); + + slicerPinCtrlMode = SLICER_PIN_CTRL_MODE_EXTERNAL; + } + /* If internal slicer with GPIOs selected, configure GPIO output source ctrl */ + else if ((formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) || + (formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE)) + { + recoveryAction = adrv9025_RxInternalSlicerGpioEnable(device, + formatSelect, + RX_CHANNEL_ARR[rxChannelArrIndex]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Resolve slicer and slicer position configs */ + recoveryAction = adrv9025_RxIntEmbSlicerConfigResolve(device, + formatSelect, + integerConfigSettings->intEmbeddedBits, + &intEmbedSlicer, + &intEmbedSlicerPos, + &intEmbedSlicerNumber, + &slicer3bitModeEn); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Resolve Sample Resolution*/ + recoveryAction = adrv9025_RxIntSampleResFormatResolve(device, + integerConfigSettings, + &intDataResolution, + &intDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Resolve Parity selection */ + recoveryAction = adrv9025_RxIntParitySupportResolve(device, + integerConfigSettings, + &intParitySupport, + &intEvenParity); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Enable Rx Gain Compensation for the requested Rx channel*/ + recoveryAction = adrv9025_RxGainCompEnableBfSet(device, + rxChannelBitfieldAddr, + ENABLE_GAIN_COMPENSATION); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntDataFormatBfSet(device, + rxChannelBitfieldAddr, + intDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntDataResolutionBfSet(device, + rxChannelBitfieldAddr, + intDataResolution); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntEmbedSlicerBfSet(device, + rxChannelBitfieldAddr, + intEmbedSlicer); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntEmbedSlicerPosBfSet(device, + rxChannelBitfieldAddr, + intEmbedSlicerPos); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntEmbedSlicerNumberBfSet(device, + rxChannelBitfieldAddr, + intEmbedSlicerNumber); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntParitySupportBfSet(device, + rxChannelBitfieldAddr, + intParitySupport); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntEvenParityBfSet(device, + rxChannelBitfieldAddr, + intEvenParity); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxSlicerPinControlModeBfSet(device, + rxChannelBitfieldAddr, + slicerPinCtrlMode); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntSlicerLsbOnQBfSet(device, + rxChannelBitfieldAddr, + (uint8_t)integerConfigSettings->intEmbeddedPos); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxStatic3bitSlicerModeEnBfSet(device, + rxChannelBitfieldAddr, + slicer3bitModeEn); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (formatSelect != ADI_ADRV9025_GAIN_WITH_EXTERNAL_SLICER) + { + recoveryAction = adrv9025_RxSlicerPinControlStepBfSet(device, + rxChannelBitfieldAddr, + (uint8_t)slicerConfigSettings->intSlicerStepSize); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO) + { + if ((integerConfigSettings->intEmbeddedBits == ADI_ADRV9025_EMBED_2_SLICERBITS_AT_MSB_3_BIT_SLICER) || + (integerConfigSettings->intEmbeddedBits == ADI_ADRV9025_EMBED_2_SLICERBITS_AT_LSB_3_BIT_SLICER)) + { + device->devStateInfo.rxChannel3bitSlicerMode |= (uint8_t)RX_CHANNEL_ARR[rxChannelArrIndex]; + } + else + { + device->devStateInfo.rxChannel3bitSlicerMode &= ~(uint8_t)RX_CHANNEL_ARR[rxChannelArrIndex]; + } + } + else + { + device->devStateInfo.rxChannel3bitSlicerMode &= ~(uint8_t)RX_CHANNEL_ARR[rxChannelArrIndex]; + } + } + } + + /*Iterate through channel mask and if set configure integer formatter settings on the corresponding ORx channel*/ + for (rxChannelArrIndex = 0; rxChannelArrIndex < ORX_CHANNEL_ARR_SIZE; rxChannelArrIndex++) + { + if ((rxChannelMask & (uint32_t)ORX_CHANNEL_ARR[rxChannelArrIndex]) == (uint32_t)ORX_CHANNEL_ARR[rxChannelArrIndex]) + { + /*If an Rx channel mask bit is set, resolve the corresponding Rx Bitfield Address*/ + recoveryAction = adrv9025_OrxBitfieldAddressGet(device, + ORX_CHANNEL_ARR[rxChannelArrIndex], + &orxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* External Slicer mode is invalid for ORx channel */ + if (formatSelect == ADI_ADRV9025_GAIN_WITH_EXTERNAL_SLICER) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + formatSelect, + "External slicer mode not supported for ORx channels"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* If internal slicer with GPIOs selected, configure GPIO output source ctrl */ + else if ((formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) || + (formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + formatSelect, + "Internal slicer mode not supported for ORx channels"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Resolve slicer and slicer position configs */ + recoveryAction = adrv9025_RxIntEmbSlicerConfigResolve(device, + formatSelect, + integerConfigSettings->intEmbeddedBits, + &intEmbedSlicer, + &intEmbedSlicerPos, + &intEmbedSlicerNumber, + &slicer3bitModeEn); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Resolve Sample Resolution*/ + recoveryAction = adrv9025_RxIntSampleResFormatResolve(device, + integerConfigSettings, + &intDataResolution, + &intDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Resolve Parity selection */ + recoveryAction = adrv9025_RxIntParitySupportResolve(device, + integerConfigSettings, + &intParitySupport, + &intEvenParity); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Enable Rx Gain Compensation for the requested ORx channel*/ + recoveryAction = adrv9025_OrxGainCompEnableBfSet(device, + orxChannelBitfieldAddr, + ENABLE_GAIN_COMPENSATION); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntDataFormatBfSet(device, + orxChannelBitfieldAddr, + intDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntDataResolutionBfSet(device, + orxChannelBitfieldAddr, + intDataResolution); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntEmbedSlicerBfSet(device, + orxChannelBitfieldAddr, + intEmbedSlicer); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntEmbedSlicerPosBfSet(device, + orxChannelBitfieldAddr, + intEmbedSlicerPos); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntEmbedSlicerNumberBfSet(device, + orxChannelBitfieldAddr, + intEmbedSlicerNumber); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntParitySupportBfSet(device, + orxChannelBitfieldAddr, + intParitySupport); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntEvenParityBfSet(device, + orxChannelBitfieldAddr, + intEvenParity); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntSlicerLsbOnQBfSet(device, + orxChannelBitfieldAddr, + (uint8_t)integerConfigSettings->intEmbeddedPos); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxSlicerPinControlStepBfSet(device, + orxChannelBitfieldAddr, + (uint8_t)slicerConfigSettings->intSlicerStepSize); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxStatic3bitSlicerModeEnBfSet(device, + orxChannelBitfieldAddr, + slicer3bitModeEn); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO) + { + if ((integerConfigSettings->intEmbeddedBits == ADI_ADRV9025_EMBED_2_SLICERBITS_AT_MSB_3_BIT_SLICER) || + (integerConfigSettings->intEmbeddedBits == ADI_ADRV9025_EMBED_2_SLICERBITS_AT_LSB_3_BIT_SLICER)) + { + device->devStateInfo.rxChannel3bitSlicerMode |= (uint8_t)ORX_CHANNEL_ARR[rxChannelArrIndex]; + } + else + { + device->devStateInfo.rxChannel3bitSlicerMode &= ~(uint8_t)ORX_CHANNEL_ARR[rxChannelArrIndex]; + } + } + else + { + device->devStateInfo.rxChannel3bitSlicerMode &= ~(uint8_t)ORX_CHANNEL_ARR[rxChannelArrIndex]; + } + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxDataFormatIntegerGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_IntegerConfigSettings_t* integerConfigSettings, + adi_adrv9025_SlicerConfigSettings_t* slicerConfigSettings) +{ + static const uint8_t INT_DATA_FORMAT_2S_COMPLEMENT = 0; + static const uint8_t INT_DATA_RESOLUTION_16BITS = 1; + static const uint8_t INT_EMBED_SLICER_DISABLE = 0; + static const uint8_t INT_EMBED_SLICER_POS_MSB = 0; + static const uint8_t INT_EMBED_SLICER_2_BITS = 0; + static const uint8_t INT_PARTIY_SUPPORT_DISABLE = 0; + static const uint8_t INT_PARITY_EVEN = 0; + static const uint8_t SLICER_PIN_CTRL_MODE_INTERNAL = 0; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_ALL_RX_CHANNELS; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddr = ADRV9025_BF_ALL_ORX_CHANNELS; + uint8_t intEvenParity = INT_PARITY_EVEN; + uint8_t intParitySupport = INT_PARTIY_SUPPORT_DISABLE; + uint8_t intEmbedSlicerNumber = INT_EMBED_SLICER_2_BITS; + uint8_t intEmbedSlicerPos = INT_EMBED_SLICER_POS_MSB; + uint8_t intEmbedSlicer = INT_EMBED_SLICER_DISABLE; + uint8_t intDataResolution = INT_DATA_RESOLUTION_16BITS; + uint8_t intDataFormat = INT_DATA_FORMAT_2S_COMPLEMENT; + uint8_t slicerPinCtrlMode = SLICER_PIN_CTRL_MODE_INTERNAL; + uint8_t extSlicerStepSize = 0; + uint8_t intSlicerStepSize = 0; + uint8_t rxExtSlicerGpioSel = 0; + uint8_t intSlicerLsbOnQ = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check integer format configuration struct is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + integerConfigSettings); + + /* Check slicer configuration struct is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + slicerConfigSettings); + + if ((rxChannel == ADI_ADRV9025_RX1) || + (rxChannel == ADI_ADRV9025_RX2) || + (rxChannel == ADI_ADRV9025_RX3) || + (rxChannel == ADI_ADRV9025_RX4)) + { + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + rxChannel, + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntDataFormatBfGet(device, + rxChannelBitfieldAddr, + &intDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntDataResolutionBfGet(device, + rxChannelBitfieldAddr, + &intDataResolution); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntEmbedSlicerBfGet(device, + rxChannelBitfieldAddr, + &intEmbedSlicer); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntEmbedSlicerPosBfGet(device, + rxChannelBitfieldAddr, + &intEmbedSlicerPos); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntEmbedSlicerNumberBfGet(device, + rxChannelBitfieldAddr, + &intEmbedSlicerNumber); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntParitySupportBfGet(device, + rxChannelBitfieldAddr, + &intParitySupport); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntEvenParityBfGet(device, + rxChannelBitfieldAddr, + &intEvenParity); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxSlicerPinControlModeBfGet(device, + rxChannelBitfieldAddr, + &slicerPinCtrlMode); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxExternalSlicerPinControlStepBfGet(device, + rxChannelBitfieldAddr, + &extSlicerStepSize); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxSlicerPinControlStepBfGet(device, + rxChannelBitfieldAddr, + &intSlicerStepSize); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxRxdpSlicerPinCntrlGpioSelectBfGet(device, + rxChannelBitfieldAddr, + &rxExtSlicerGpioSel); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntSlicerLsbOnQBfGet(device, + rxChannelBitfieldAddr, + &intSlicerLsbOnQ); + ADI_ERROR_RETURN(device->common.error.newAction); + + switch (rxChannel) + { + case(ADI_ADRV9025_RX1): + slicerConfigSettings->rx1ExtSlicerGpioSelect = (adi_adrv9025_RxExtSlicerGpioSel_e)rxExtSlicerGpioSel; + break; + case(ADI_ADRV9025_RX2): + slicerConfigSettings->rx2ExtSlicerGpioSelect = (adi_adrv9025_RxExtSlicerGpioSel_e)rxExtSlicerGpioSel; + break; + case(ADI_ADRV9025_RX3): + slicerConfigSettings->rx3ExtSlicerGpioSelect = (adi_adrv9025_RxExtSlicerGpioSel_e)rxExtSlicerGpioSel; + break; + case(ADI_ADRV9025_RX4): + slicerConfigSettings->rx4ExtSlicerGpioSelect = (adi_adrv9025_RxExtSlicerGpioSel_e)rxExtSlicerGpioSel; + break; + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel encountered while attempting to encode Rx Integer settings. Valid Rx Channels Rx1-Rx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + slicerConfigSettings->extSlicerStepSize = (adi_adrv9025_ExtSlicerStepSizes_e)extSlicerStepSize; + } + else if ((rxChannel == ADI_ADRV9025_ORX1) || + (rxChannel == ADI_ADRV9025_ORX2) || + (rxChannel == ADI_ADRV9025_ORX3) || + (rxChannel == ADI_ADRV9025_ORX4)) + { + recoveryAction = adrv9025_OrxBitfieldAddressGet(device, + rxChannel, + &orxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntDataFormatBfGet(device, + orxChannelBitfieldAddr, + &intDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntDataResolutionBfGet(device, + orxChannelBitfieldAddr, + &intDataResolution); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntEmbedSlicerBfGet(device, + orxChannelBitfieldAddr, + &intEmbedSlicer); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntEmbedSlicerPosBfGet(device, + orxChannelBitfieldAddr, + &intEmbedSlicerPos); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntEmbedSlicerNumberBfGet(device, + orxChannelBitfieldAddr, + &intEmbedSlicerNumber); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntParitySupportBfGet(device, + orxChannelBitfieldAddr, + &intParitySupport); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntEvenParityBfGet(device, + orxChannelBitfieldAddr, + &intEvenParity); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxSlicerPinControlStepBfGet(device, + orxChannelBitfieldAddr, + &intSlicerStepSize); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntSlicerLsbOnQBfGet(device, + orxChannelBitfieldAddr, + &intSlicerLsbOnQ); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel parameter encountered for Integer Format settings read back. Valid Rx channels are Rx1-Rx4, ORx1-ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_RxIntEmbSlicerConfigEncode(device, + rxChannel, + intEmbedSlicer, + intEmbedSlicerPos, + intEmbedSlicerNumber, + &integerConfigSettings->intEmbeddedBits); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntSampleResFormatEncode(device, + intDataResolution, + intDataFormat, + &integerConfigSettings->intSampleResolution); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntParitySupportEncode(device, + rxChannel, + intParitySupport, + intEvenParity, + &integerConfigSettings->intParity); + ADI_ERROR_RETURN(device->common.error.newAction); + + slicerConfigSettings->intSlicerStepSize = (adi_adrv9025_IntSlicerStepSizes_e)intSlicerStepSize; + integerConfigSettings->intEmbeddedPos = (adi_adrv9025_RxSlicerEmbeddedPos_e)intSlicerLsbOnQ; + + return recoveryAction; +} + +int32_t adrv9025_RxDataFormatEmbOvldMonitorSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + adi_adrv9025_EmbOverloadMonitorConfigSettings_t* embOvldConfigSettings) +{ + static const adi_adrv9025_RxChannels_e RX_CHANNEL_ARR[] = {ADI_ADRV9025_RX1, ADI_ADRV9025_RX2, ADI_ADRV9025_RX3, ADI_ADRV9025_RX4}; + static const uint32_t RX_CHANNEL_ARR_SIZE = sizeof(RX_CHANNEL_ARR) / sizeof(RX_CHANNEL_ARR[0]); + static const uint8_t DEFAULT_INT_DATA_FORMAT = 0; /* Int data format - 2s complement */ + static const uint8_t DEFAULT_INT_DATA_RESOLUTION = 1; /* Int sample resolution - 16 bit */ + static const uint8_t LSB_POS_I_CHANNEL_ID = 0; + static const uint8_t LSB_PLUS_ONE_POS_I_CHANNEL_ID = 1; + static const uint8_t LSB_POS_Q_CHANNEL_ID = 0; + static const uint8_t LSB_PLUS_ONE_POS_Q_CHANNEL_ID = 1; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxChannelArrIndex = 0; + uint8_t enable = 0; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_RX_CH0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check that embedded overload configuration struct is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + embOvldConfigSettings); + + /*Disable gain compensation and set integer format register to default*/ + recoveryAction = adrv9025_RxDataFormatGainCompDisable(device, + rxChannelMask, + DEFAULT_INT_DATA_FORMAT, + DEFAULT_INT_DATA_RESOLUTION); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Iterate through channel mask and if set configure the corresponding Rx embedded overload indicator formatter*/ + for (rxChannelArrIndex = 0; rxChannelArrIndex < RX_CHANNEL_ARR_SIZE; rxChannelArrIndex++) + { + if ((rxChannelMask & (uint32_t)RX_CHANNEL_ARR[rxChannelArrIndex]) == (uint32_t)RX_CHANNEL_ARR[rxChannelArrIndex]) + { + /* If an Rx channel mask is set, resolve the corresponding Rx Bitfield Address */ + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + RX_CHANNEL_ARR[rxChannelArrIndex], + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((embOvldConfigSettings->embeddedMonitorSrcLsbI == ADI_ADRV9025_RX_EMB_MON_SRC_APD_HIGH_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbQ == ADI_ADRV9025_RX_EMB_MON_SRC_APD_HIGH_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneI == ADI_ADRV9025_RX_EMB_MON_SRC_APD_HIGH_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneQ == ADI_ADRV9025_RX_EMB_MON_SRC_APD_HIGH_THRESH)) + { + /* Set the APD High Threshold exceeded indicator source */ + recoveryAction = adrv9025_RxApdHighSrcSelectBfSet(device, + rxChannelBitfieldAddr, + (uint8_t)embOvldConfigSettings->embeddedMonitorApdHighSrcSel); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((embOvldConfigSettings->embeddedMonitorSrcLsbI == ADI_ADRV9025_RX_EMB_MON_SRC_APD_LOW_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbQ == ADI_ADRV9025_RX_EMB_MON_SRC_APD_LOW_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneI == ADI_ADRV9025_RX_EMB_MON_SRC_APD_LOW_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneQ == ADI_ADRV9025_RX_EMB_MON_SRC_APD_LOW_THRESH)) + { + /* Set the APD Low Threshold exceeded indicator source */ + recoveryAction = adrv9025_RxApdLowSrcSelectBfSet(device, + rxChannelBitfieldAddr, + (uint8_t)embOvldConfigSettings->embeddedMonitorApdLowSrcSel); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((embOvldConfigSettings->embeddedMonitorSrcLsbI == ADI_ADRV9025_RX_EMB_MON_SRC_HB2_HIGH_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbQ == ADI_ADRV9025_RX_EMB_MON_SRC_HB2_HIGH_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneI == ADI_ADRV9025_RX_EMB_MON_SRC_HB2_HIGH_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneQ == ADI_ADRV9025_RX_EMB_MON_SRC_HB2_HIGH_THRESH)) + { + /* Set the HB2 High Threshold exceeded indicator source */ + recoveryAction = adrv9025_RxHb2HighSrcSelectBfSet(device, + rxChannelBitfieldAddr, + (uint8_t)embOvldConfigSettings->embeddedMonitorHb2HighSrcSel); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((embOvldConfigSettings->embeddedMonitorSrcLsbI == ADI_ADRV9025_RX_EMB_MON_SRC_HB2_LOW_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbQ == ADI_ADRV9025_RX_EMB_MON_SRC_HB2_LOW_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneI == ADI_ADRV9025_RX_EMB_MON_SRC_HB2_LOW_THRESH) || + (embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneQ == ADI_ADRV9025_RX_EMB_MON_SRC_HB2_LOW_THRESH)) + { + /* Set the HB2 Low Threshold exceeded indicator source */ + recoveryAction = adrv9025_RxHb2LowSrcSelectBfSet(device, + rxChannelBitfieldAddr, + (uint8_t)embOvldConfigSettings->embeddedMonitorHb2LowSrcSel); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* I Sample LSB Posn Embedded overload indicator config */ + recoveryAction = adrv9025_RxRxMonFormatIBfSet(device, + rxChannelBitfieldAddr, + LSB_POS_I_CHANNEL_ID, + (uint8_t)embOvldConfigSettings->embeddedMonitorSrcLsbQ); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* I Sample LSB + 1 Posn Embedded overload indicator config */ + recoveryAction = adrv9025_RxRxMonFormatIBfSet(device, + rxChannelBitfieldAddr, + LSB_PLUS_ONE_POS_I_CHANNEL_ID, + (uint8_t)embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneQ); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Q Sample LSB Posn Embedded overload indicator config */ + recoveryAction = adrv9025_RxRxMonFormatQBfSet(device, + rxChannelBitfieldAddr, + LSB_POS_Q_CHANNEL_ID, + (uint8_t)embOvldConfigSettings->embeddedMonitorSrcLsbI); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Q Sample LSB + 1 Posn Embedded overload indicator config */ + recoveryAction = adrv9025_RxRxMonFormatQBfSet(device, + rxChannelBitfieldAddr, + LSB_PLUS_ONE_POS_Q_CHANNEL_ID, + (uint8_t)embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneI); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set invert Hb2 flag config */ + enable = (embOvldConfigSettings->invertHb2Flag == 0) ? 0 : 1; + recoveryAction = adrv9025_RxInvertHb2LowBfSet(device, + rxChannelBitfieldAddr, + enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while writing invert Hb2 Flag configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set invert Apd2 flag config */ + enable = (embOvldConfigSettings->invertApdFlag == 0) ? 0 : 1; + recoveryAction = adrv9025_RxInvertApdLowBfSet(device, + rxChannelBitfieldAddr, + enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while writing invert Apd Flag configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxDataFormatEmbOvldMonitorGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_EmbOverloadMonitorConfigSettings_t* embOvldConfigSettings) +{ + static const uint8_t LSB_POS_I_CHANNEL_ID = 0; + static const uint8_t LSB_PLUS_ONE_POS_I_CHANNEL_ID = 1; + static const uint8_t LSB_POS_Q_CHANNEL_ID = 0; + static const uint8_t LSB_PLUS_ONE_POS_Q_CHANNEL_ID = 1; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_RX_CH0; + uint8_t apdHighSrcRegVal = 0; + uint8_t apdLowSrcRegVal = 0; + uint8_t hb2HighSrcRegVal = 0; + uint8_t hb2LowSrcRegVal = 0; + uint8_t lsbIMonSrcRegVal = 0; + uint8_t lsbQMonSrcRegVal = 0; + uint8_t lsbPlusOneIMonSrcRegVal = 0; + uint8_t lsbPlusOneQMonSrcRegVal = 0; + uint8_t invertHb2Flag = 0; + uint8_t invertApdFlag = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check that embedded overload configuration struct is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + embOvldConfigSettings); + + /* If the target Rx channel is not an ORx channel, retrieve the embedded overload indicator config */ + if ((rxChannel == ADI_ADRV9025_RX1) || + (rxChannel == ADI_ADRV9025_RX2) || + (rxChannel == ADI_ADRV9025_RX3) || + (rxChannel == ADI_ADRV9025_RX4)) + { + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + rxChannel, + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get the APD High Threshold exceeded indicator source */ + recoveryAction = adrv9025_RxApdHighSrcSelectBfGet(device, + rxChannelBitfieldAddr, + &apdHighSrcRegVal); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get the APD Low Threshold exceeded indicator source */ + recoveryAction = adrv9025_RxApdLowSrcSelectBfGet(device, + rxChannelBitfieldAddr, + &apdLowSrcRegVal); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get the HB2 High Threshold exceeded indicator source */ + recoveryAction = adrv9025_RxHb2HighSrcSelectBfGet(device, + rxChannelBitfieldAddr, + &hb2HighSrcRegVal); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get the HB2 Low Threshold exceeded indicator source */ + recoveryAction = adrv9025_RxHb2LowSrcSelectBfGet(device, + rxChannelBitfieldAddr, + &hb2LowSrcRegVal); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get I Sample LSB Posn Embedded overload indicator config */ + recoveryAction = adrv9025_RxRxMonFormatIBfGet(device, + rxChannelBitfieldAddr, + LSB_POS_I_CHANNEL_ID, + &lsbQMonSrcRegVal); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get I Sample LSB + 1 Posn Embedded overload indicator config */ + recoveryAction = adrv9025_RxRxMonFormatIBfGet(device, + rxChannelBitfieldAddr, + LSB_PLUS_ONE_POS_I_CHANNEL_ID, + &lsbPlusOneQMonSrcRegVal); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Q Sample LSB Posn Embedded overload indicator config */ + recoveryAction = adrv9025_RxRxMonFormatQBfGet(device, + rxChannelBitfieldAddr, + LSB_POS_Q_CHANNEL_ID, + &lsbIMonSrcRegVal); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Q Sample LSB + 1 Posn Embedded overload indicator config */ + recoveryAction = adrv9025_RxRxMonFormatQBfGet(device, + rxChannelBitfieldAddr, + LSB_PLUS_ONE_POS_Q_CHANNEL_ID, + &lsbPlusOneIMonSrcRegVal); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get invert Hb2 flag config */ + recoveryAction = adrv9025_RxInvertHb2LowBfGet(device, + rxChannelBitfieldAddr, + &invertHb2Flag); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while reading invert Hb2 Flag configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get invert Apd flag config */ + recoveryAction = adrv9025_RxInvertApdLowBfGet(device, + rxChannelBitfieldAddr, + &invertApdFlag); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while reading invert Apd Flag configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Update the pointer to embOvldConfigSettings with data retrieved from the device */ + embOvldConfigSettings->embeddedMonitorApdHighSrcSel = (adi_adrv9025_RxApdHighEmbeddedMonitorSrc_e)apdHighSrcRegVal; + embOvldConfigSettings->embeddedMonitorApdLowSrcSel = (adi_adrv9025_RxApdLowEmbeddedMonitorSrc_e)apdLowSrcRegVal; + embOvldConfigSettings->embeddedMonitorHb2HighSrcSel = (adi_adrv9025_RxHb2HighEmbeddedMonitorSrc_e)hb2HighSrcRegVal; + embOvldConfigSettings->embeddedMonitorHb2LowSrcSel = (adi_adrv9025_RxHb2LowEmbeddedMonitorSrc_e)hb2LowSrcRegVal; + embOvldConfigSettings->embeddedMonitorSrcLsbI = (adi_adrv9025_RxEmbeddedMonitorSrc_e)lsbIMonSrcRegVal; + embOvldConfigSettings->embeddedMonitorSrcLsbQ = (adi_adrv9025_RxEmbeddedMonitorSrc_e)lsbQMonSrcRegVal; + embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneI = (adi_adrv9025_RxEmbeddedMonitorSrc_e)lsbPlusOneIMonSrcRegVal; + embOvldConfigSettings->embeddedMonitorSrcLsbPlusOneQ = (adi_adrv9025_RxEmbeddedMonitorSrc_e)lsbPlusOneQMonSrcRegVal; + embOvldConfigSettings->invertHb2Flag = invertHb2Flag; + embOvldConfigSettings->invertApdFlag = invertApdFlag; + } + + return recoveryAction; +} + +int32_t adrv9025_RxIntEmbSlicerConfigResolve(adi_adrv9025_Device_t* device, + adi_adrv9025_RxDataFormatModes_e formatSelect, + adi_adrv9025_RxSlicerEmbeddedBits_e intEmbeddedBits, + uint8_t* intEmbedSlicer, + uint8_t* intEmbedSlicerPos, + uint8_t* intEmbedSlicerNumber, + uint8_t* staticSlicer3bitModeEn) +{ + static const uint8_t INT_EMBED_SLICER_ENABLE = 1; + static const uint8_t INT_EMBED_SLICER_DISABLE = 0; + static const uint8_t INT_EMBED_SLICER_POS_MSB = 0; + static const uint8_t INT_EMBED_SLICER_POS_LSB = 1; + static const uint8_t INT_EMBED_SLICER_1_BIT = 1; + static const uint8_t INT_EMBED_SLICER_2_BITS = 0; + static const uint8_t INT_SLICER_3_BIT_MODE_ENABLE = 1; + static const uint8_t INT_SLICER_3_BIT_MODE_DISABLE = 0; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check that write back pointers are not nullptrs */ + ADI_NULL_PTR_RETURN(&device->common, + intEmbedSlicer); + ADI_NULL_PTR_RETURN(&device->common, + intEmbedSlicerPos); + ADI_NULL_PTR_RETURN(&device->common, + intEmbedSlicerNumber); + + if (formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO) + { + /* Resolve slicer and slicer position configs */ + switch (intEmbeddedBits) + { + case ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS: + { + *intEmbedSlicer = INT_EMBED_SLICER_DISABLE; + *intEmbedSlicerPos = INT_EMBED_SLICER_POS_MSB; + *intEmbedSlicerNumber = INT_EMBED_SLICER_2_BITS; + *staticSlicer3bitModeEn = INT_SLICER_3_BIT_MODE_DISABLE; + break; + } + + case ADI_ADRV9025_EMBED_1_SLICERBIT_AT_LSB: + { + *intEmbedSlicer = INT_EMBED_SLICER_ENABLE; + *intEmbedSlicerPos = INT_EMBED_SLICER_POS_LSB; + *intEmbedSlicerNumber = INT_EMBED_SLICER_1_BIT; + *staticSlicer3bitModeEn = INT_SLICER_3_BIT_MODE_DISABLE; + break; + } + + case ADI_ADRV9025_EMBED_1_SLICERBIT_AT_MSB: + { + *intEmbedSlicer = INT_EMBED_SLICER_ENABLE; + *intEmbedSlicerPos = INT_EMBED_SLICER_POS_MSB; + *intEmbedSlicerNumber = INT_EMBED_SLICER_1_BIT; + *staticSlicer3bitModeEn = INT_SLICER_3_BIT_MODE_DISABLE; + break; + } + + case ADI_ADRV9025_EMBED_2_SLICERBITS_AT_MSB_3_BIT_SLICER: + { + *intEmbedSlicer = INT_EMBED_SLICER_ENABLE; + *intEmbedSlicerPos = INT_EMBED_SLICER_POS_MSB; + *intEmbedSlicerNumber = INT_EMBED_SLICER_2_BITS; + *staticSlicer3bitModeEn = INT_SLICER_3_BIT_MODE_ENABLE; + break; + } + + case ADI_ADRV9025_EMBED_2_SLICERBITS_AT_LSB_3_BIT_SLICER: + { + *intEmbedSlicer = INT_EMBED_SLICER_ENABLE; + *intEmbedSlicerPos = INT_EMBED_SLICER_POS_LSB; + *intEmbedSlicerNumber = INT_EMBED_SLICER_2_BITS; + *staticSlicer3bitModeEn = INT_SLICER_3_BIT_MODE_ENABLE; + break; + } + + case ADI_ADRV9025_EMBED_2_SLICERBITS_AT_MSB_4_BIT_SLICER: + { + *intEmbedSlicer = INT_EMBED_SLICER_ENABLE; + *intEmbedSlicerPos = INT_EMBED_SLICER_POS_MSB; + *intEmbedSlicerNumber = INT_EMBED_SLICER_2_BITS; + *staticSlicer3bitModeEn = INT_SLICER_3_BIT_MODE_DISABLE; + break; + } + + case ADI_ADRV9025_EMBED_2_SLICERBITS_AT_LSB_4_BIT_SLICER: + { + *intEmbedSlicer = INT_EMBED_SLICER_ENABLE; + *intEmbedSlicerPos = INT_EMBED_SLICER_POS_LSB; + *intEmbedSlicerNumber = INT_EMBED_SLICER_2_BITS; + *staticSlicer3bitModeEn = INT_SLICER_3_BIT_MODE_DISABLE; + break; + } + + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + integerConfigSettings->intEmbeddedBits, + "Invalid integer formatter embedded slicer mode config selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + else + { + /*For other data format modes set int embedded slicer config to default*/ + *intEmbedSlicer = INT_EMBED_SLICER_DISABLE; + *intEmbedSlicerPos = INT_EMBED_SLICER_POS_MSB; + *intEmbedSlicerNumber = INT_EMBED_SLICER_2_BITS; + + /*For a 3 pin internal slicer mode - enable the 3 pin slicer mode, for other modes, disable it*/ + if (formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + *staticSlicer3bitModeEn = INT_SLICER_3_BIT_MODE_ENABLE; + } + else + { + *staticSlicer3bitModeEn = INT_SLICER_3_BIT_MODE_DISABLE; + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxIntEmbSlicerConfigEncode(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint8_t intEmbedSlicer, + uint8_t intEmbedSlicerPos, + uint8_t intEmbedSlicerNumber, + adi_adrv9025_RxSlicerEmbeddedBits_e* integerConfigSettingsEmbSlicer) +{ + static const uint8_t INT_EMBED_SLICER_DISABLE = 0; + static const uint8_t INT_EMBED_SLICER_POS_MSB = 0; + static const uint8_t INT_EMBED_SLICER_POS_LSB = 1; + static const uint8_t INT_EMBED_SLICER_1_BIT = 1; + static const uint8_t INT_EMBED_SLICER_2_BITS = 0; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check integer format configuration for Embedded Slicer setting enum is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + integerConfigSettingsEmbSlicer); + + if (intEmbedSlicer == INT_EMBED_SLICER_DISABLE) + { + *integerConfigSettingsEmbSlicer = ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS; + } + else + { + if ((intEmbedSlicerPos == INT_EMBED_SLICER_POS_LSB) && + (intEmbedSlicerNumber == INT_EMBED_SLICER_1_BIT)) + { + *integerConfigSettingsEmbSlicer = ADI_ADRV9025_EMBED_1_SLICERBIT_AT_LSB; + } + else if ((intEmbedSlicerPos == INT_EMBED_SLICER_POS_MSB) && + (intEmbedSlicerNumber == INT_EMBED_SLICER_1_BIT)) + { + *integerConfigSettingsEmbSlicer = ADI_ADRV9025_EMBED_1_SLICERBIT_AT_MSB; + } + else if ((intEmbedSlicerPos == INT_EMBED_SLICER_POS_LSB) && + (intEmbedSlicerNumber == INT_EMBED_SLICER_2_BITS)) + { + if ((device->devStateInfo.rxChannel3bitSlicerMode & (uint8_t)rxChannel) == (uint8_t)rxChannel) + { + *integerConfigSettingsEmbSlicer = ADI_ADRV9025_EMBED_2_SLICERBITS_AT_LSB_3_BIT_SLICER; + } + else + { + *integerConfigSettingsEmbSlicer = ADI_ADRV9025_EMBED_2_SLICERBITS_AT_LSB_4_BIT_SLICER; + } + } + else if ((intEmbedSlicerPos == INT_EMBED_SLICER_POS_MSB) && + (intEmbedSlicerNumber == INT_EMBED_SLICER_2_BITS)) + { + if ((device->devStateInfo.rxChannel3bitSlicerMode & (uint8_t)rxChannel) == (uint8_t)rxChannel) + { + *integerConfigSettingsEmbSlicer = ADI_ADRV9025_EMBED_2_SLICERBITS_AT_MSB_3_BIT_SLICER; + } + else + { + *integerConfigSettingsEmbSlicer = ADI_ADRV9025_EMBED_2_SLICERBITS_AT_MSB_4_BIT_SLICER; + } + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + intEmbedSlicer, + "Invalid combination of embed slicer,pos,number combination encountered while attempting to encode integer embed slicer settings"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxIntSampleResFormatResolve(adi_adrv9025_Device_t* device, + const adi_adrv9025_IntegerConfigSettings_t* integerConfigSettings, + uint8_t* intDataResolution, + uint8_t* intDataFormat) + +{ + static const uint8_t INT_DATA_FORMAT_2S_COMPLEMENT = 0; + static const uint8_t INT_DATA_FORMAT_SIGNED_MAGNITUDE = 1; + static const uint8_t INT_DATA_RESOLUTION_12BITS = 0; + static const uint8_t INT_DATA_RESOLUTION_16BITS = 1; + static const uint8_t INT_DATA_RESOLUTION_24BITS = 2; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check integer format configuration struct is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + integerConfigSettings); + + /* Check that write back pointers are not nullptrs */ + ADI_NULL_PTR_RETURN(&device->common, + intDataResolution); + ADI_NULL_PTR_RETURN(&device->common, + intDataFormat); + + /*Resolve Sample Resolution*/ + switch (integerConfigSettings->intSampleResolution) + { + case ADI_ADRV9025_INTEGER_12BIT_2SCOMP: + { + *intDataResolution = INT_DATA_RESOLUTION_12BITS; + *intDataFormat = INT_DATA_FORMAT_2S_COMPLEMENT; + break; + } + + case ADI_ADRV9025_INTEGER_12BIT_SIGNED: + { + *intDataResolution = INT_DATA_RESOLUTION_12BITS; + *intDataFormat = INT_DATA_FORMAT_SIGNED_MAGNITUDE; + break; + } + + case ADI_ADRV9025_INTEGER_16BIT_2SCOMP: + { + *intDataResolution = INT_DATA_RESOLUTION_16BITS; + *intDataFormat = INT_DATA_FORMAT_2S_COMPLEMENT; + break; + } + + case ADI_ADRV9025_INTEGER_16BIT_SIGNED: + { + *intDataResolution = INT_DATA_RESOLUTION_16BITS; + *intDataFormat = INT_DATA_FORMAT_SIGNED_MAGNITUDE; + break; + } + + case ADI_ADRV9025_INTEGER_24BIT_2SCOMP: + { + *intDataResolution = INT_DATA_RESOLUTION_24BITS; + *intDataFormat = INT_DATA_FORMAT_2S_COMPLEMENT; + break; + } + + case ADI_ADRV9025_INTEGER_24BIT_SIGNED: + { + *intDataResolution = INT_DATA_RESOLUTION_24BITS; + *intDataFormat = INT_DATA_FORMAT_SIGNED_MAGNITUDE; + break; + } + + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + integerConfigSettings->intSampleResolution, + "Invalid integer formatter data resolution selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxIntSampleResFormatEncode(adi_adrv9025_Device_t* device, + uint8_t intDataResolution, + uint8_t intDataFormat, + adi_adrv9025_RxIntSampleResolution_e* intSampleResolution) +{ + static const uint8_t INT_DATA_FORMAT_2S_COMPLEMENT = 0; + static const uint8_t INT_DATA_FORMAT_SIGNED_MAGNITUDE = 1; + static const uint8_t INT_DATA_RESOLUTION_12BITS = 0; + static const uint8_t INT_DATA_RESOLUTION_16BITS = 1; + static const uint8_t INT_DATA_RESOLUTION_24BITS = 2; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check integer format resolution enum is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + intSampleResolution); + + if ((intDataResolution == INT_DATA_RESOLUTION_12BITS) && + (intDataFormat == INT_DATA_FORMAT_2S_COMPLEMENT)) + { + *intSampleResolution = ADI_ADRV9025_INTEGER_12BIT_2SCOMP; + } + else if ((intDataResolution == INT_DATA_RESOLUTION_12BITS) && + (intDataFormat == INT_DATA_FORMAT_SIGNED_MAGNITUDE)) + { + *intSampleResolution = ADI_ADRV9025_INTEGER_12BIT_SIGNED; + } + else if ((intDataResolution == INT_DATA_RESOLUTION_16BITS) && + (intDataFormat == INT_DATA_FORMAT_2S_COMPLEMENT)) + { + *intSampleResolution = ADI_ADRV9025_INTEGER_16BIT_2SCOMP; + } + else if ((intDataResolution == INT_DATA_RESOLUTION_16BITS) && + (intDataFormat == INT_DATA_FORMAT_SIGNED_MAGNITUDE)) + { + *intSampleResolution = ADI_ADRV9025_INTEGER_16BIT_SIGNED; + } + else if ((intDataResolution == INT_DATA_RESOLUTION_24BITS) && + (intDataFormat == INT_DATA_FORMAT_2S_COMPLEMENT)) + { + *intSampleResolution = ADI_ADRV9025_INTEGER_24BIT_2SCOMP; + } + else if ((intDataResolution == INT_DATA_RESOLUTION_24BITS) && + (intDataFormat == INT_DATA_FORMAT_SIGNED_MAGNITUDE)) + { + *intSampleResolution = ADI_ADRV9025_INTEGER_24BIT_SIGNED; + } + + return recoveryAction; +} + +int32_t adrv9025_RxIntParitySupportResolve(adi_adrv9025_Device_t* device, + const adi_adrv9025_IntegerConfigSettings_t* integerConfigSettings, + uint8_t* intParitySupport, + uint8_t* intEvenParity) + +{ + static const uint8_t INT_PARTIY_SUPPORT_ENABLE = 1; + static const uint8_t INT_PARTIY_SUPPORT_DISABLE = 0; + static const uint8_t INT_PARITY_EVEN = 0; + static const uint8_t INT_PARITY_ODD = 1; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check integer format configuration struct is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + integerConfigSettings); + + /* Check that write back pointers are not nullptrs */ + ADI_NULL_PTR_RETURN(&device->common, + intParitySupport); + ADI_NULL_PTR_RETURN(&device->common, + intEvenParity); + + switch (integerConfigSettings->intParity) + { + case ADI_ADRV9025_3BIT_SLICER_ODD_PARITY: + { + *intParitySupport = INT_PARTIY_SUPPORT_ENABLE; + *intEvenParity = INT_PARITY_ODD; + break; + } + + case ADI_ADRV9025_3BIT_SLICER_EVEN_PARITY: + { + *intParitySupport = INT_PARTIY_SUPPORT_ENABLE; + *intEvenParity = INT_PARITY_EVEN; + break; + } + + case ADI_ADRV9025_NO_PARITY: + { + *intParitySupport = INT_PARTIY_SUPPORT_DISABLE; + *intEvenParity = INT_PARITY_EVEN; + break; + } + + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + integerConfigSettings->intParity, + "Invalid integer formatter parity selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxIntParitySupportEncode(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint8_t intParitySupport, + uint8_t intEvenParity, + adi_adrv9025_RxIntParity_e* integerParity) +{ + static const uint8_t INT_PARTIY_SUPPORT_ENABLE = 1; + static const uint8_t INT_PARITY_EVEN = 0; + static const uint8_t INT_PARITY_ODD = 1; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check integer format configuration struct is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + integerParity); + + if ((intParitySupport == INT_PARTIY_SUPPORT_ENABLE) && + (intEvenParity == INT_PARITY_ODD) && + ((device->devStateInfo.rxChannel3bitSlicerMode & (uint8_t)rxChannel) == (uint8_t)rxChannel)) + { + *integerParity = ADI_ADRV9025_3BIT_SLICER_ODD_PARITY; + } + else if ((intParitySupport == INT_PARTIY_SUPPORT_ENABLE) && + (intEvenParity == INT_PARITY_EVEN) && + ((device->devStateInfo.rxChannel3bitSlicerMode & (uint8_t)rxChannel) == (uint8_t)rxChannel)) + { + *integerParity = ADI_ADRV9025_3BIT_SLICER_EVEN_PARITY; + } + else + { + *integerParity = ADI_ADRV9025_NO_PARITY; + } + + return recoveryAction; +} + +int32_t adrv9025_RxInternalSlicerGpioEnable(adi_adrv9025_Device_t* device, + adi_adrv9025_RxDataFormatModes_e intSlicerFormatSel, + adi_adrv9025_RxChannels_e rxChannel) +{ + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_RX_INT_SLICER_CTRL_OUT; + static const uint32_t NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_4PIN_MODE = 4; + static const uint32_t NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_3PIN_MODE = 3; + static const uint8_t SOURCE_CTRL_RX_SLICER_POSN_4PIN_MODE = 0x0A; + static const uint8_t SOURCE_CTRL_RX_SLICER_POSN_3PIN_MODE = 0x0B; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t sharedResourceArr[ADI_ADRV9025_NUM_GPIOS_RX_INT_SLICER_CTRL_OUT_FEATURE] = {0}; + uint8_t resourceAcqReleaseStatus = ADI_FAILURE; + uint32_t gpioOutputDirMask = 0; + uint32_t numberOfGpioPerChannel = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + switch (rxChannel) + { + case ADI_ADRV9025_RX1: + { + if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_11; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_10; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_09; + sharedResourceArr[3] = ADI_ADRV9025_GPIO_08; + gpioOutputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_11) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_10) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_09) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_08); + + numberOfGpioPerChannel = NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_4PIN_MODE; + } + else if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_06; /* RX1_slicer[0] */ + sharedResourceArr[1] = ADI_ADRV9025_GPIO_07; /* RX1_slicer[1] */ + sharedResourceArr[2] = ADI_ADRV9025_GPIO_08; /* RX1_slicer[2] */ + gpioOutputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_06) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_07) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_08); + + numberOfGpioPerChannel = NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_3PIN_MODE; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + intSlicerFormatSel, + "Invalid Rx data format mode selected for enabling internal slicer GPIOs."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + case ADI_ADRV9025_RX2: + { + if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_15; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_14; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_13; + sharedResourceArr[3] = ADI_ADRV9025_GPIO_12; + gpioOutputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_15) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_14) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_13) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_12); + + numberOfGpioPerChannel = NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_4PIN_MODE; + } + else if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_09; /* RX2_slicer[0] */ + sharedResourceArr[1] = ADI_ADRV9025_GPIO_10; /* RX2_slicer[1] */ + sharedResourceArr[2] = ADI_ADRV9025_GPIO_11; /* RX2_slicer[2] */ + gpioOutputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_09) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_10) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_11); + + numberOfGpioPerChannel = NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_3PIN_MODE; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + intSlicerFormatSel, + "Invalid Rx data format mode selected for enabling internal slicer GPIOs."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + case ADI_ADRV9025_RX3: + { + if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_07; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_06; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_05; + sharedResourceArr[3] = ADI_ADRV9025_GPIO_04; + gpioOutputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_07) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_06) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_05) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_04); + + numberOfGpioPerChannel = NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_4PIN_MODE; + } + else if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_12; /* RX3_slicer[0] */ + sharedResourceArr[1] = ADI_ADRV9025_GPIO_13; /* RX3_slicer[1] */ + sharedResourceArr[2] = ADI_ADRV9025_GPIO_14; /* RX3_slicer[2] */ + gpioOutputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_12) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_13) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_14); + + numberOfGpioPerChannel = NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_3PIN_MODE; + } + break; + } + + case ADI_ADRV9025_RX4: + { + if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_03; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_02; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_01; + sharedResourceArr[3] = ADI_ADRV9025_GPIO_00; + gpioOutputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_03) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_02) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_01) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_00); + + numberOfGpioPerChannel = NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_4PIN_MODE; + } + else if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_15; /* RX4_slicer[0] */ + sharedResourceArr[1] = ADI_ADRV9025_GPIO_16; /* RX4_slicer[1] */ + sharedResourceArr[2] = ADI_ADRV9025_GPIO_17; /* RX4_slicer[2] */ + gpioOutputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_15) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_16) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_17); + + numberOfGpioPerChannel = NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_3PIN_MODE; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + intSlicerFormatSel, + "Invalid Rx data format mode selected for enabling internal slicer GPIOs."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel selected for internal slicer ctrl word observation GPIO output"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Acquire Shared GPIOs to ensure that they are not in use by another feature*/ + recoveryAction = adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + numberOfGpioPerChannel, + THIS_FEATURE_ID, + &resourceAcqReleaseStatus); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Unable to acquire GPIOs for internal slicer ctrl word observation use. Please check if the GPIOs are already in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*If GPIOs are available set the source ctrl to observe Rx slicer position*/ + switch (rxChannel) + { + case ADI_ADRV9025_RX1: + { + if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + recoveryAction = adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_RX_SLICER_POSN_4PIN_MODE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx1 slicer position GPIO[11:8] - 4pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + recoveryAction = adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_RX_SLICER_POSN_3PIN_MODE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx1 slicer position GPIO[6] - 3pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_RX_SLICER_POSN_3PIN_MODE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx1 slicer position GPIO[8:7] - 3pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + case ADI_ADRV9025_RX2: + { + if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + recoveryAction = adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_RX_SLICER_POSN_4PIN_MODE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx2 slicer position GPIO[15:12] - 4pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + recoveryAction = adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_RX_SLICER_POSN_3PIN_MODE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx2 slicer position GPIO[11:9] - 3pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + case ADI_ADRV9025_RX3: + { + if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + recoveryAction = adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_RX_SLICER_POSN_4PIN_MODE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx3 slicer position GPIO[7:4] - 4pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + recoveryAction = adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_RX_SLICER_POSN_3PIN_MODE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx3 slicer position GPIO[14:12] - 3pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + case ADI_ADRV9025_RX4: + { + if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + recoveryAction = adrv9025_CoreGpioLowerByteLowerNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_RX_SLICER_POSN_4PIN_MODE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx4 slicer position GPIO[3:0] - 4pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + recoveryAction = adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_RX_SLICER_POSN_3PIN_MODE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx4 slicer position GPIO[16:15] - 3pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpioExtraBitsSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_RX_SLICER_POSN_3PIN_MODE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx4 slicer position GPIO[17] - 3pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel selected for internal slicer ctrl word observation GPIO output"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Set the direction as output for selected Rx channel Slicer Position observation*/ + if ((recoveryAction = adi_adrv9025_GpioOutputDirSet(device, + gpioOutputDirMask)) != ADI_COMMON_ACT_NO_ACTION) + { + /*Clear the error so that clean up functions execute*/ + recoveryAction = adi_common_ErrorClear(&device->common); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Release Shared GPIOs if setting of GPIO Input Dir is unsuccessful*/ + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + numberOfGpioPerChannel, + THIS_FEATURE_ID, + &resourceAcqReleaseStatus); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Unable to release GPIOs for internal slicer observation while attempting to exit the function due to GPIO dir set error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxInternalSlicerGpioDisable(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxDataFormatModes_e intSlicerFormatSel) +{ + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_RX_INT_SLICER_CTRL_OUT; + static const uint32_t NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_4PIN_MODE = 4; + static const uint32_t NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_3PIN_MODE = 3; + static const uint8_t SOURCE_CTRL_DEFAULT = 0x00; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t sharedResourceArr[ADI_ADRV9025_NUM_GPIOS_RX_INT_SLICER_CTRL_OUT_FEATURE] = {0}; + uint8_t resourceAcqReleaseStatus = ADI_FAILURE; + uint32_t gpioInputDirMask = 0; + uint32_t numberOfGpioPerChannel = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + switch (rxChannel) + { + case ADI_ADRV9025_RX1: + { + if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_11; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_10; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_09; + sharedResourceArr[3] = ADI_ADRV9025_GPIO_08; + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_11) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_10) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_09) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_08); + + numberOfGpioPerChannel = NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_4PIN_MODE; + } + else if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_06; /* RX1_slicer[0] */ + sharedResourceArr[1] = ADI_ADRV9025_GPIO_07; /* RX1_slicer[1] */ + sharedResourceArr[2] = ADI_ADRV9025_GPIO_08; /* RX1_slicer[2] */ + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_06) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_07) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_08); + + numberOfGpioPerChannel = NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_3PIN_MODE; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + intSlicerFormatSel, + "Invalid Rx data format mode selected for disabling internal slicer GPIOs."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + case ADI_ADRV9025_RX2: + { + if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_15; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_14; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_13; + sharedResourceArr[3] = ADI_ADRV9025_GPIO_12; + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_15) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_14) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_13) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_12); + + numberOfGpioPerChannel = NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_4PIN_MODE; + } + else if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_09; /* RX2_slicer[0] */ + sharedResourceArr[1] = ADI_ADRV9025_GPIO_10; /* RX2_slicer[1] */ + sharedResourceArr[2] = ADI_ADRV9025_GPIO_11; /* RX2_slicer[2] */ + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_09) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_10) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_11); + + numberOfGpioPerChannel = NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_3PIN_MODE; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + intSlicerFormatSel, + "Invalid Rx data format mode selected for disabling internal slicer GPIOs."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + case ADI_ADRV9025_RX3: + { + if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_07; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_06; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_05; + sharedResourceArr[3] = ADI_ADRV9025_GPIO_04; + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_07) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_06) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_05) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_04); + + numberOfGpioPerChannel = NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_4PIN_MODE; + } + else if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_12; /* RX3_slicer[0] */ + sharedResourceArr[1] = ADI_ADRV9025_GPIO_13; /* RX3_slicer[1] */ + sharedResourceArr[2] = ADI_ADRV9025_GPIO_14; /* RX3_slicer[2] */ + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_12) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_13) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_14); + + numberOfGpioPerChannel = NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_3PIN_MODE; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + intSlicerFormatSel, + "Invalid Rx data format mode selected for disabling internal slicer GPIOs."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + case ADI_ADRV9025_RX4: + { + if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_03; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_02; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_01; + sharedResourceArr[3] = ADI_ADRV9025_GPIO_00; + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_03) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_02) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_01) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_00); + + numberOfGpioPerChannel = NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_4PIN_MODE; + } + else if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_15; /* RX4_slicer[0] */ + sharedResourceArr[1] = ADI_ADRV9025_GPIO_16; /* RX4_slicer[1] */ + sharedResourceArr[2] = ADI_ADRV9025_GPIO_17; /* RX4_slicer[2] */ + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_15) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_16) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_17); + + numberOfGpioPerChannel = NUM_SHARED_INT_OBS_GPIOS_PER_CHANNEL_3PIN_MODE; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + intSlicerFormatSel, + "Invalid Rx data format mode selected for disabling internal slicer GPIOs."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel selected for internal slicer ctrl word observation GPIO output disable"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Acquire Shared GPIOs to ensure that they are not in use by another feature*/ + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + numberOfGpioPerChannel, + THIS_FEATURE_ID, + &resourceAcqReleaseStatus); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Unable to release requested GPIOs for internal slicer ctrl word observation use. Please check if the GPIOs are in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*If GPIOs are available clear the source ctrl for observe Rx slicer position*/ + switch (rxChannel) + { + case ADI_ADRV9025_RX1: + { + if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + recoveryAction = adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_DEFAULT); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to clear source ctrl of Rx1 slicer position GPIO[11:8] - 4 Pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + recoveryAction = adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_DEFAULT); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx1 slicer position GPIO[6] - 3pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_DEFAULT); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx1 slicer position GPIO[7:8] - 3pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + case ADI_ADRV9025_RX2: + { + if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + recoveryAction = adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_DEFAULT); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx2 slicer position GPIO[15:12] - 4pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + recoveryAction = adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_DEFAULT); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx2 slicer position GPIO[11:9] - 3pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + case ADI_ADRV9025_RX3: + { + if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + recoveryAction = adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_DEFAULT); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx3 slicer position GPIO[7:4] - 4pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + recoveryAction = adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_DEFAULT); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx3 slicer position GPIO[14:12] - 3pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + case ADI_ADRV9025_RX4: + { + if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) + { + recoveryAction = adrv9025_CoreGpioLowerByteLowerNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_DEFAULT); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx4 slicer position GPIO[3:0] - 4pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (intSlicerFormatSel == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) + { + recoveryAction = adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_DEFAULT); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx4 slicer position GPIO[16:15] - 3pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpioExtraBitsSourceControlBfSet(device, + ADRV9025_BF_CORE, + SOURCE_CTRL_DEFAULT); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx4 slicer position GPIO[17] - 3pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel selected for internal slicer ctrl word observation GPIO output disable"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + } + + /*Set the direction as input for selected Rx channel Slicer Position observation on release*/ + if ((recoveryAction = adi_adrv9025_GpioInputDirSet(device, + gpioInputDirMask)) != ADI_COMMON_ACT_NO_ACTION) + { + /*Clear the error so that clean up functions execute*/ + recoveryAction = adi_common_ErrorClear(&device->common); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Re-Acquire Shared GPIOs if setting of GPIO Input Dir is unsuccessful*/ + recoveryAction = adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + numberOfGpioPerChannel, + THIS_FEATURE_ID, + &resourceAcqReleaseStatus); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Unable to re-acquire GPIOs for internal slicer observation while attempting to exit the function due to GPIO dir set error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxInternalSlicerGpioEnableGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxDataFormatModes_e* intSlicerFormatSel, + uint8_t* enableStatus) +{ + static const uint8_t SOURCE_CTRL_RX_SLICER_POSN_4BIT_MODE = 0x0A; + static const uint8_t SOURCE_CTRL_RX_SLICER_POSN_3BIT_MODE = 0x0B; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t sourceCtrlGet4PinMode = 0; + uint8_t sourceCtrlGet3PinMode1 = 0; + uint8_t sourceCtrlGet3PinMode2 = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + switch (rxChannel) + { + case ADI_ADRV9025_RX1: + { + recoveryAction = adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &sourceCtrlGet4PinMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to get source ctrl of Rx1 slicer position GPIO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &sourceCtrlGet3PinMode1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to get source ctrl for Rx1 slicer position GPIO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &sourceCtrlGet3PinMode2); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to get source ctrl for Rx1 slicer position GPIO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + break; + } + + case ADI_ADRV9025_RX2: + { + recoveryAction = adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &sourceCtrlGet4PinMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to get source ctrl of Rx2 slicer position GPIO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &sourceCtrlGet3PinMode1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to get source ctrl for Rx2 slicer position GPIO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + break; + } + + case ADI_ADRV9025_RX3: + { + recoveryAction = adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &sourceCtrlGet4PinMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to get source ctrl of Rx3 slicer position GPIO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &sourceCtrlGet3PinMode1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to get source ctrl for Rx3 slicer position GPIO"); + ADI_ERROR_RETURN(device->common.error.newAction) + + break; + } + + case ADI_ADRV9025_RX4: + { + recoveryAction = adrv9025_CoreGpioLowerByteLowerNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &sourceCtrlGet4PinMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to get source ctrl of Rx4 slicer position GPIO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &sourceCtrlGet3PinMode1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx4 slicer position GPIO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpioExtraBitsSourceControlBfGet(device, + ADRV9025_BF_CORE, + &sourceCtrlGet3PinMode2); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set source ctrl for Rx4 slicer position GPIO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + break; + } + + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel selected for internal slicer ctrl word observation GPIO output status get"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + } + + if (sourceCtrlGet4PinMode == SOURCE_CTRL_RX_SLICER_POSN_4BIT_MODE) + { + if (intSlicerFormatSel != NULL) + { + *intSlicerFormatSel = ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE; + } + if (enableStatus != NULL) + { + *enableStatus = 1; + } + } + else if ((sourceCtrlGet3PinMode1 == SOURCE_CTRL_RX_SLICER_POSN_3BIT_MODE) || + (sourceCtrlGet3PinMode2 == SOURCE_CTRL_RX_SLICER_POSN_3BIT_MODE)) + { + if (intSlicerFormatSel != NULL) + { + *intSlicerFormatSel = ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE; + } + if (enableStatus != NULL) + { + *enableStatus = 1; + } + } + else + { + if (intSlicerFormatSel != NULL) + { + *intSlicerFormatSel = ADI_ADRV9025_GAIN_COMPENSATION_DISABLED; + } + if (enableStatus != NULL) + { + *enableStatus = 0; + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxExternalSlicerGpioEnable(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + const adi_adrv9025_SlicerConfigSettings_t* slicerConfigSettings) + +{ + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_RX_EXT_SLICER_CTRL; + static const uint32_t NUM_SHARED_EXT_CTRL_GPIOS_PER_CHANNEL = 3; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t sharedResourceArr[ADI_ADRV9025_NUM_GPIOS_RX_EXT_SLICER_CTRL_WORD_FEATURE] = {0}; + adi_adrv9025_RxExtSlicerGpioSel_e rxExtSlicerGpioSel = ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_ALL_RX_CHANNELS; + //adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddr = ADRV9025_BF_ALL_ORX_CHANNELS; + uint8_t resourceAcqReleaseStatus = ADI_FAILURE; + uint32_t gpioInputDirMask = 0; + uint8_t isOrxChannel = (uint8_t)ADI_FALSE; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check slicer configuration struct is not a nullptr */ + ADI_NULL_PTR_RETURN(&device->common, + slicerConfigSettings); + + /*Resolve External Slicer Ctrl GPIO sel*/ + if (rxChannel == ADI_ADRV9025_RX1) + { + rxExtSlicerGpioSel = slicerConfigSettings->rx1ExtSlicerGpioSelect; + } + else if (rxChannel == ADI_ADRV9025_RX2) + { + rxExtSlicerGpioSel = slicerConfigSettings->rx2ExtSlicerGpioSelect; + } + else if (rxChannel == ADI_ADRV9025_RX3) + { + rxExtSlicerGpioSel = slicerConfigSettings->rx3ExtSlicerGpioSelect; + } + else if (rxChannel == ADI_ADRV9025_RX4) + { + rxExtSlicerGpioSel = slicerConfigSettings->rx4ExtSlicerGpioSelect; + } + //else if (rxChannel == ADI_ADRV9025_ORX1) + //{ + // rxExtSlicerGpioSel = slicerConfigSettings->orx1ExtSlicerGpioSelect; + // isOrxChannel = ADI_TRUE; + //} + //else if (rxChannel == ADI_ADRV9025_ORX2) + //{ + // rxExtSlicerGpioSel = slicerConfigSettings->orx2ExtSlicerGpioSelect; + // isOrxChannel = ADI_TRUE; + //} + //else if (rxChannel == ADI_ADRV9025_ORX3) + //{ + // rxExtSlicerGpioSel = slicerConfigSettings->orx3ExtSlicerGpioSelect; + // isOrxChannel = ADI_TRUE; + //} + //else if (rxChannel == ADI_ADRV9025_ORX4) + //{ + // rxExtSlicerGpioSel = slicerConfigSettings->orx4ExtSlicerGpioSelect; + // isOrxChannel = ADI_TRUE; + //} + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxExtSlicerGpioSel, + "Invalid Rx Channel encountered while attempting to configure External slicer for Rx Data Formatter. Valid channels include Rx1-Rx4, ORx1-ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + switch (rxExtSlicerGpioSel) + { + case ADI_ADRV9025_EXTSLICER_RX_GPIO_2_DOWNTO_0: + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_00; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_01; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_02; + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_00) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_01) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_02); + break; + } + + case ADI_ADRV9025_EXTSLICER_RX_GPIO_5_DOWNTO_3: + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_03; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_04; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_05; + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_03) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_04) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_05); + break; + } + + case ADI_ADRV9025_EXTSLICER_RX_GPIO_8_DOWNTO_6: + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_06; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_07; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_08; + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_06) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_07) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_08); + break; + } + + case ADI_ADRV9025_EXTSLICER_RX_GPIO_11_DOWNTO_9: + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_09; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_10; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_11; + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_09) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_10) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_11); + break; + } + + case ADI_ADRV9025_EXTSLICER_RX_GPIO_14_DOWNTO_12: + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_12; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_13; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_14; + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_12) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_13) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_14); + break; + } + + case ADI_ADRV9025_EXTSLICER_RX_GPIO_17_DOWNTO_15: + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_15; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_16; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_17; + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_15) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_16) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_17); + break; + } + + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxExtSlicerGpioSel, + "Invalid integer formatter External ctrl GPIO selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Acquire Shared GPIOs to ensure that they are not in use by another feature*/ + recoveryAction = adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + NUM_SHARED_EXT_CTRL_GPIOS_PER_CHANNEL, + THIS_FEATURE_ID, + &resourceAcqReleaseStatus); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Unable to acquire GPIOs for external slicer ctrl word input use. Please check if the GPIOs are already in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Set the direction of external ctrl GPIOs as input*/ + if ((recoveryAction = adi_adrv9025_GpioInputDirSet(device, + gpioInputDirMask)) != ADI_COMMON_ACT_NO_ACTION) + { + /*Clear the error so that clean up functions execute*/ + recoveryAction = adi_common_ErrorClear(&device->common); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Release Shared GPIOs if setting of GPIO Input Dir is unsuccessful*/ + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + NUM_SHARED_EXT_CTRL_GPIOS_PER_CHANNEL, + THIS_FEATURE_ID, + &resourceAcqReleaseStatus); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Unable to release GPIOs for external slicer ctrl word input use while attempting to exit the function due to GPIO dir set error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + rxChannel, + "Error while attempting to set GPIO input direction while attempting to enable external slicer GPIO"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (isOrxChannel == (uint8_t)ADI_FALSE) + { + /*Resolve the corresponding Rx Bitfield Address*/ + if ((recoveryAction = adrv9025_RxBitfieldAddressGet(device, + rxChannel, + &rxChannelBitfieldAddr)) != ADI_COMMON_ACT_NO_ACTION) + { + /*Clear the error so that clean up functions execute*/ + recoveryAction = adi_common_ErrorClear(&device->common); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Release Shared GPIOs if decoding of Rx bitfield address is unsuccessful*/ + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + NUM_SHARED_EXT_CTRL_GPIOS_PER_CHANNEL, + THIS_FEATURE_ID, + &resourceAcqReleaseStatus); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Unable to release GPIOs for external slicer ctrl word input use while attempting to exit the function due to Rx bitfield addr decoding error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel encountered while attempting to decode Rx bitfield address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Set the external ctrl GPIO select*/ + if ((recoveryAction = adrv9025_RxRxdpSlicerPinCntrlGpioSelectBfSet(device, + rxChannelBitfieldAddr, + (uint8_t)rxExtSlicerGpioSel)) != ADI_COMMON_ACT_NO_ACTION) + { + /*Clear the error so that clean up functions execute*/ + recoveryAction = adi_common_ErrorClear(&device->common); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Release Shared GPIOs if setting of Rx slicer pin ctrl GPIO bitfield is unsuccessful*/ + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + NUM_SHARED_EXT_CTRL_GPIOS_PER_CHANNEL, + THIS_FEATURE_ID, + &resourceAcqReleaseStatus); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Unable to release GPIOs for external slicer ctrl word input use while attempting to exit the function due to slicer pin ctrl bitfield set error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Error while attempting to set Rx slicer pin ctrl bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + //else + //{ + // /*Resolve the corresponding ORx Bitfield Address*/ + // if ((recoveryAction = adrv9025_OrxBitfieldAddressGet(device, rxChannel, &orxChannelBitfieldAddr)) != ADI_COMMON_ACT_NO_ACTION) + // { + // /*Release Shared GPIOs if decoding of ORx bitfield address is unsuccessful*/ + // recoveryAction = adrv9025_SharedResourcesRelease(device, ADRV9025_SHARED_RESOURCE_GPIO, &sharedResourceArr[0], NUM_SHARED_EXT_CTRL_GPIOS_PER_CHANNEL, + // THIS_FEATURE_ID, &resourceAcqReleaseStatus); + // ADI_ERROR_RETURN(device->common.error.newAction); + + // if (resourceAcqReleaseStatus == ADI_FAILURE) + // { + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ACT_ERR_CHECK_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, rxChannel, + // "Unable to release GPIOs for external slicer ctrl word input use while attempting to exit the function due to ORx bitfield addr decoding error"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + + // /*Set the external ctrl GPIO select*/ + // if ((recoveryAction = adrv9025_OrxRxdpSlicerPinCntrlGpioSelectBfSet(device, orxChannelBitfieldAddr, (uint8_t)rxExtSlicerGpioSel)) != ADI_COMMON_ACT_NO_ACTION) + // { + // /*Release Shared GPIOs if setting of ORx slicer pin ctrl GPIO bitfield is unsuccessful*/ + // recoveryAction = adrv9025_SharedResourcesRelease(device, ADRV9025_SHARED_RESOURCE_GPIO, &sharedResourceArr[0], NUM_SHARED_EXT_CTRL_GPIOS_PER_CHANNEL, + // THIS_FEATURE_ID, &resourceAcqReleaseStatus); + // ADI_ERROR_RETURN(device->common.error.newAction); + + // if (resourceAcqReleaseStatus == ADI_FAILURE) + // { + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ACT_ERR_CHECK_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, rxChannel, + // "Unable to release GPIOs for external slicer ctrl word input use while attempting to exit the function due to slicer pin ctrl bitfield set error"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + //} + + return recoveryAction; +} + +int32_t adrv9025_RxExternalSlicerGpioDisable(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel) +{ + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_RX_EXT_SLICER_CTRL; + static const uint32_t NUM_SHARED_EXT_CTRL_GPIOS_PER_CHANNEL = 3; + static const uint8_t DEFAULT_GPIO_SELECT_VALUE = 0; + static const uint32_t ALL_RX_MASK = (uint32_t)(ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | + ADI_ADRV9025_RX4); + static const uint32_t ALL_ORX_MASK = (uint32_t)(ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2 | ADI_ADRV9025_ORX3 | + ADI_ADRV9025_ORX4); + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t sharedResourceArr[ADI_ADRV9025_NUM_GPIOS_RX_EXT_SLICER_CTRL_WORD_FEATURE] = {0}; + uint8_t rxExtSlicerGpioSelBf = 0; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_ALL_RX_CHANNELS; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddr = ADRV9025_BF_ALL_ORX_CHANNELS; + uint8_t resourceAcqReleaseStatus = ADI_FAILURE; + uint32_t gpioInputDirMask = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /*Check that the requested rxChannel is exactly 1 valid channel*/ + if ((rxChannel != ADI_ADRV9025_RX1) && + (rxChannel != ADI_ADRV9025_RX2) && + (rxChannel != ADI_ADRV9025_RX3) && + (rxChannel != ADI_ADRV9025_RX4) && + (rxChannel != ADI_ADRV9025_ORX1) && + (rxChannel != ADI_ADRV9025_ORX2) && + (rxChannel != ADI_ADRV9025_ORX3) && + (rxChannel != ADI_ADRV9025_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx channel encountered while attempting to disable External ctrl slicer GPIOs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)rxChannel & ALL_RX_MASK) > 0) + { + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + rxChannel, + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxRxdpSlicerPinCntrlGpioSelectBfGet(device, + rxChannelBitfieldAddr, + &rxExtSlicerGpioSelBf); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (((uint32_t)rxChannel & ALL_ORX_MASK) > 0) + { + recoveryAction = adrv9025_OrxBitfieldAddressGet(device, + rxChannel, + &orxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxRxdpSlicerPinCntrlGpioSelectBfGet(device, + orxChannelBitfieldAddr, + &rxExtSlicerGpioSelBf); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx channel encountered while attempting to disable External ctrl slicer GPIOs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + switch (rxExtSlicerGpioSelBf) + { + case ADI_ADRV9025_EXTSLICER_RX_GPIO_2_DOWNTO_0: + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_00; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_01; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_02; + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_00) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_01) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_02); + break; + } + + case ADI_ADRV9025_EXTSLICER_RX_GPIO_5_DOWNTO_3: + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_03; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_04; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_05; + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_03) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_04) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_05); + break; + } + + case ADI_ADRV9025_EXTSLICER_RX_GPIO_8_DOWNTO_6: + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_06; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_07; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_08; + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_06) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_07) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_08); + break; + } + + case ADI_ADRV9025_EXTSLICER_RX_GPIO_11_DOWNTO_9: + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_09; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_10; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_11; + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_09) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_10) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_11); + break; + } + + case ADI_ADRV9025_EXTSLICER_RX_GPIO_14_DOWNTO_12: + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_12; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_13; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_14; + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_12) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_13) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_14); + break; + } + + case ADI_ADRV9025_EXTSLICER_RX_GPIO_17_DOWNTO_15: + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_15; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_16; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_17; + gpioInputDirMask = ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_15) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_16) | + ((uint32_t)0x00000001 << ADI_ADRV9025_GPIO_17); + break; + } + + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxExtSlicerGpioSel, + "Invalid integer formatter External ctrl GPIO selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Release Shared GPIOs to ensure that they are not in use by another feature*/ + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + NUM_SHARED_EXT_CTRL_GPIOS_PER_CHANNEL, + THIS_FEATURE_ID, + &resourceAcqReleaseStatus); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Unable to release GPIOs for external slicer ctrl word input use. Please check if the GPIOs are already in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Set the External Ctrl GPIO select register to default*/ + if (((uint32_t)rxChannel & ALL_RX_MASK) > 0) + { + /*Set the external ctrl GPIO select to default */ + if ((recoveryAction = adrv9025_RxRxdpSlicerPinCntrlGpioSelectBfSet(device, + rxChannelBitfieldAddr, + DEFAULT_GPIO_SELECT_VALUE)) != ADI_COMMON_ACT_NO_ACTION) + { + /*Clear the error so that clean up functions execute*/ + recoveryAction = adi_common_ErrorClear(&device->common); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Release Shared GPIOs if setting of Rx slicer pin ctrl GPIO bitfield is unsuccessful*/ + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + NUM_SHARED_EXT_CTRL_GPIOS_PER_CHANNEL, + THIS_FEATURE_ID, + &resourceAcqReleaseStatus); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Unable to re-acquire GPIOs for external slicer ctrl word input use while attempting to exit the function due to slicer pin ctrl bitfield set error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Error while attempting to write to Rx slicer ctrl bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else + { + /*Set the external ctrl GPIO select to default */ + // if ((recoveryAction = adrv9025_OrxRxdpSlicerPinCntrlGpioSelectBfSet(device, orxChannelBitfieldAddr, DEFAULT_GPIO_SELECT_VALUE)) != ADI_COMMON_ACT_NO_ACTION) + // { + ///*Clear the error so that clean up functions execute*/ + //recoveryAction = adi_common_ErrorClear(&device->common); + //ADI_ERROR_RETURN(device->common.error.newAction); + + // /*Release Shared GPIOs if setting of ORx slicer pin ctrl GPIO bitfield is unsuccessful*/ + // recoveryAction = adrv9025_SharedResourcesRelease(device, ADRV9025_SHARED_RESOURCE_GPIO, &sharedResourceArr[0], NUM_SHARED_EXT_CTRL_GPIOS_PER_CHANNEL, + // THIS_FEATURE_ID, &resourceAcqReleaseStatus); + // ADI_ERROR_RETURN(device->common.error.newAction); + + // if (resourceAcqReleaseStatus == ADI_FAILURE) + // { + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, rxChannel, + // "Unable to re-acquire GPIOs for external slicer ctrl word input use while attempting to exit the function due to slicer pin ctrl bitfield set error"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + + //ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, rxChannel, + // "Error while attempting to write to ORx slicer ctrl bitfield"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + } + + /*Set the direction of external ctrl GPIOs as input*/ + if ((recoveryAction = adi_adrv9025_GpioInputDirSet(device, + gpioInputDirMask)) != ADI_COMMON_ACT_NO_ACTION) + { + /*Clear the error so that clean up functions execute*/ + recoveryAction = adi_common_ErrorClear(&device->common); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Re-acquire Shared GPIOs if setting of GPIO Input Dir is unsuccessful*/ + recoveryAction = adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + NUM_SHARED_EXT_CTRL_GPIOS_PER_CHANNEL, + THIS_FEATURE_ID, + &resourceAcqReleaseStatus); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Unable to re-acquire GPIOs for external slicer ctrl word input use while attempting to exit the function due to GPIO dir set error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Error while attempting to set GPIO direction to input in adrv9025_RxExternalSlicerGpioDisable function"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_RxDataFormatGainCompDisable(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint8_t intDataFormat, + uint8_t intDataResolution) +{ + static const adi_adrv9025_RxChannels_e RX_CHANNEL_ARR[] = {ADI_ADRV9025_RX1, ADI_ADRV9025_RX2, ADI_ADRV9025_RX3, ADI_ADRV9025_RX4}; + static const adi_adrv9025_RxChannels_e ORX_CHANNEL_ARR[] = {ADI_ADRV9025_ORX1, ADI_ADRV9025_ORX2, ADI_ADRV9025_ORX3, ADI_ADRV9025_ORX4}; + static const uint32_t RX_CHANNEL_ARR_SIZE = sizeof(RX_CHANNEL_ARR) / sizeof(RX_CHANNEL_ARR[0]); + static const uint32_t ORX_CHANNEL_ARR_SIZE = sizeof(ORX_CHANNEL_ARR) / sizeof(ORX_CHANNEL_ARR[0]); + static const uint8_t DISABLE_GAIN_COMPENSATION = 0; + static const uint8_t DISABLE_FLOATING_POINT = 0; + static const uint8_t DISABLE_INT_SLICER_EXT_PIN_CTRL = 0; + static const uint8_t DEFAULT_INT_EMBED_SLICER = 0; + static const uint8_t DEFAULT_INT_EMBED_SLICER_POS = 0; + static const uint8_t DEFAULT_INT_EMBED_SLICER_NUM = 0; + static const uint8_t DEFAULT_INT_PARITY_SUPPORT = 0; + static const uint8_t DEFAULT_INT_EVEN_PARITY = 0; + static const uint8_t LSB_POS_I_CHANNEL_ID = 0; + static const uint8_t LSB_PLUS_ONE_POS_I_CHANNEL_ID = 1; + static const uint8_t LSB_POS_Q_CHANNEL_ID = 0; + static const uint8_t LSB_PLUS_ONE_POS_Q_CHANNEL_ID = 1; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxChannelArrIndex = 0; + uint8_t gainCompEnStatus = 0; + uint8_t extPinCtrlStatus = 0; + uint8_t intEmbedStatus = 0; + uint8_t floatingPointEnStatus = 0; + uint8_t internalSlicerGpioEnableStatus = 0; + adi_adrv9025_RxDataFormatModes_e internalSlicerMode = ADI_ADRV9025_GAIN_COMPENSATION_DISABLED; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_RX_CH0; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddr = ADRV9025_BF_ORX_CH0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /*Iterate through channel mask and if set disable gain compensation on the corresponding channel*/ + for (rxChannelArrIndex = 0; rxChannelArrIndex < RX_CHANNEL_ARR_SIZE; rxChannelArrIndex++) + { + if ((rxChannelMask & (uint32_t)RX_CHANNEL_ARR[rxChannelArrIndex]) == (uint32_t)RX_CHANNEL_ARR[rxChannelArrIndex]) + { + /*If an Rx channel mask is set, resolve the corresponding Rx Bitfield Address*/ + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + RX_CHANNEL_ARR[rxChannelArrIndex], + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Please note that even though gain compensation is disabled, + the embedded slicer bits have to be explicitly set to 0 failing + which the received data will contain slicer bits if it was previously + enabled */ + + recoveryAction = adrv9025_RxIntDataFormatBfSet(device, + rxChannelBitfieldAddr, + intDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntDataResolutionBfSet(device, + rxChannelBitfieldAddr, + intDataResolution); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxGainCompEnableBfGet(device, + rxChannelBitfieldAddr, + &gainCompEnStatus); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Disable I Sample LSB Posn Embedded overload indicator config */ + recoveryAction = adrv9025_RxRxMonFormatIBfSet(device, + rxChannelBitfieldAddr, + LSB_POS_I_CHANNEL_ID, + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Disable I Sample LSB + 1 Posn Embedded overload indicator config */ + recoveryAction = adrv9025_RxRxMonFormatIBfSet(device, + rxChannelBitfieldAddr, + LSB_PLUS_ONE_POS_I_CHANNEL_ID, + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Disable Q Sample LSB Posn Embedded overload indicator config */ + recoveryAction = adrv9025_RxRxMonFormatQBfSet(device, + rxChannelBitfieldAddr, + LSB_POS_Q_CHANNEL_ID, + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Disable Q Sample LSB + 1 Posn Embedded overload indicator config */ + recoveryAction = adrv9025_RxRxMonFormatQBfSet(device, + rxChannelBitfieldAddr, + LSB_PLUS_ONE_POS_Q_CHANNEL_ID, + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (gainCompEnStatus > 0) + { + recoveryAction = adrv9025_RxFpEnBfGet(device, + rxChannelBitfieldAddr, + &floatingPointEnStatus); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (floatingPointEnStatus > 0) + { + /*Disable floating point formatter*/ + recoveryAction = adrv9025_RxFpEnBfSet(device, + rxChannelBitfieldAddr, + DISABLE_FLOATING_POINT); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_RxSlicerPinControlModeBfGet(device, + rxChannelBitfieldAddr, + &extPinCtrlStatus); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (extPinCtrlStatus > 0) + { + /*Unassign and release shared GPIOs*/ + recoveryAction = adrv9025_RxExternalSlicerGpioDisable(device, + RX_CHANNEL_ARR[rxChannelArrIndex]); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Disable Ext Slicer Pin Ctrl*/ + recoveryAction = adrv9025_RxSlicerPinControlModeBfSet(device, + rxChannelBitfieldAddr, + DISABLE_INT_SLICER_EXT_PIN_CTRL); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_RxIntEmbedSlicerBfGet(device, + rxChannelBitfieldAddr, + &intEmbedStatus); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxInternalSlicerGpioEnableGet(device, + RX_CHANNEL_ARR[rxChannelArrIndex], + &internalSlicerMode, + &internalSlicerGpioEnableStatus); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((intEmbedStatus == 0) && (internalSlicerGpioEnableStatus > 0)) + { + recoveryAction = adrv9025_RxInternalSlicerGpioDisable(device, + RX_CHANNEL_ARR[rxChannelArrIndex], + internalSlicerMode); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Set Slicer format configs to default*/ + recoveryAction = adrv9025_RxIntEmbedSlicerBfSet(device, + rxChannelBitfieldAddr, + DEFAULT_INT_EMBED_SLICER); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntEmbedSlicerPosBfSet(device, + rxChannelBitfieldAddr, + DEFAULT_INT_EMBED_SLICER_POS); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntEmbedSlicerNumberBfSet(device, + rxChannelBitfieldAddr, + DEFAULT_INT_EMBED_SLICER_NUM); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntParitySupportBfSet(device, + rxChannelBitfieldAddr, + DEFAULT_INT_PARITY_SUPPORT); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxIntEvenParityBfSet(device, + rxChannelBitfieldAddr, + DEFAULT_INT_EVEN_PARITY); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Disable Gain Compensation*/ + recoveryAction = adrv9025_RxGainCompEnableBfSet(device, + rxChannelBitfieldAddr, + DISABLE_GAIN_COMPENSATION); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + /* Disable ORx channel settings if selected */ + for (rxChannelArrIndex = 0; rxChannelArrIndex < ORX_CHANNEL_ARR_SIZE; rxChannelArrIndex++) + { + if ((rxChannelMask & (uint32_t)ORX_CHANNEL_ARR[rxChannelArrIndex]) == (uint32_t)ORX_CHANNEL_ARR[rxChannelArrIndex]) + { + /*If an Rx channel mask is set, resolve the corresponding Rx Bitfield Address*/ + recoveryAction = adrv9025_OrxBitfieldAddressGet(device, + ORX_CHANNEL_ARR[rxChannelArrIndex], + &orxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Please note that even though gain compensation is disabled, + the embedded slicer bits have to be explicitly set to 0 failing + which the received data will contain slicer bits if it was previously + enabled */ + + recoveryAction = adrv9025_OrxIntDataFormatBfSet(device, + orxChannelBitfieldAddr, + intDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntDataResolutionBfSet(device, + orxChannelBitfieldAddr, + intDataResolution); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxGainCompEnableBfGet(device, + orxChannelBitfieldAddr, + &gainCompEnStatus); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (gainCompEnStatus > 0) + { + recoveryAction = adrv9025_OrxFpEnBfGet(device, + orxChannelBitfieldAddr, + &floatingPointEnStatus); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (floatingPointEnStatus > 0) + { + /*Disable floating point formatter*/ + recoveryAction = adrv9025_OrxFpEnBfSet(device, + orxChannelBitfieldAddr, + DISABLE_FLOATING_POINT); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /*Set Slicer format configs to default*/ + recoveryAction = adrv9025_OrxIntEmbedSlicerBfSet(device, + orxChannelBitfieldAddr, + DEFAULT_INT_EMBED_SLICER); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntEmbedSlicerPosBfSet(device, + orxChannelBitfieldAddr, + DEFAULT_INT_EMBED_SLICER_POS); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntEmbedSlicerNumberBfSet(device, + orxChannelBitfieldAddr, + DEFAULT_INT_EMBED_SLICER_NUM); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntParitySupportBfSet(device, + orxChannelBitfieldAddr, + DEFAULT_INT_PARITY_SUPPORT); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxIntEvenParityBfSet(device, + orxChannelBitfieldAddr, + DEFAULT_INT_EVEN_PARITY); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Disable Gain Compensation*/ + recoveryAction = adrv9025_OrxGainCompEnableBfSet(device, + orxChannelBitfieldAddr, + DISABLE_GAIN_COMPENSATION); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxGainCompExtLnaSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint8_t externalLnaGain) +{ + static const adi_adrv9025_RxChannels_e RX_CHANNEL_ARR[] = {ADI_ADRV9025_RX1, ADI_ADRV9025_RX2, ADI_ADRV9025_RX3, ADI_ADRV9025_RX4}; + static const adi_adrv9025_RxChannels_e ORX_CHANNEL_ARR[] = {ADI_ADRV9025_ORX1, ADI_ADRV9025_ORX2, ADI_ADRV9025_ORX3, ADI_ADRV9025_ORX4}; + static const uint32_t RX_CHANNEL_ARR_SIZE = sizeof(RX_CHANNEL_ARR) / sizeof(RX_CHANNEL_ARR[0]); + static const uint32_t ORX_CHANNEL_ARR_SIZE = sizeof(ORX_CHANNEL_ARR) / sizeof(ORX_CHANNEL_ARR[0]); + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxChannelArrIndex = 0; + uint8_t externalLnaGainEn = 0; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_RX_CH0; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddr = ADRV9025_BF_ORX_CH0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + externalLnaGainEn = (externalLnaGain > 0) ? 1 : 0; + + /*Iterate through channel mask and if set write the ext gain bitfield of the corresponding Rx channel*/ + for (rxChannelArrIndex = 0; rxChannelArrIndex < RX_CHANNEL_ARR_SIZE; rxChannelArrIndex++) + { + if ((rxChannelMask & (uint32_t)RX_CHANNEL_ARR[rxChannelArrIndex]) == (uint32_t)RX_CHANNEL_ARR[rxChannelArrIndex]) + { + /*If an Rx channel mask is set, resolve the corresponding Rx Bitfield Address*/ + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + RX_CHANNEL_ARR[rxChannelArrIndex], + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxGainCompForExtGainBfSet(device, + rxChannelBitfieldAddr, + externalLnaGainEn); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Iterate through channel mask and if set write the ext gain bitfield of the corresponding ORx channel*/ + for (rxChannelArrIndex = 0; rxChannelArrIndex < ORX_CHANNEL_ARR_SIZE; rxChannelArrIndex++) + { + if ((rxChannelMask & (uint32_t)ORX_CHANNEL_ARR[rxChannelArrIndex]) == (uint32_t)ORX_CHANNEL_ARR[rxChannelArrIndex]) + { + /*If an Rx channel mask is set, resolve the corresponding Rx Bitfield Address*/ + recoveryAction = adrv9025_OrxBitfieldAddressGet(device, + ORX_CHANNEL_ARR[rxChannelArrIndex], + &orxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxGainCompForExtGainBfSet(device, + orxChannelBitfieldAddr, + externalLnaGainEn); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxGainCompExtLnaGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint8_t* externalLnaGain) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_RX_CH0; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddr = ADRV9025_BF_ORX_CH0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + externalLnaGain); + + if ((rxChannel == ADI_ADRV9025_RX1) || + (rxChannel == ADI_ADRV9025_RX2) || + (rxChannel == ADI_ADRV9025_RX3) || + (rxChannel == ADI_ADRV9025_RX4)) + { + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + rxChannel, + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxGainCompForExtGainBfGet(device, + rxChannelBitfieldAddr, + externalLnaGain); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if ((rxChannel == ADI_ADRV9025_ORX1) || + (rxChannel == ADI_ADRV9025_ORX2) || + (rxChannel == ADI_ADRV9025_ORX3) || + (rxChannel == ADI_ADRV9025_ORX4)) + { + recoveryAction = adrv9025_OrxBitfieldAddressGet(device, + rxChannel, + &orxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxGainCompForExtGainBfGet(device, + orxChannelBitfieldAddr, + externalLnaGain); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx channel encountered while attempting to retrieve Ext LNA gain Enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_RxGainCompTempEnableSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint8_t tempCompensationEnable) +{ + static const adi_adrv9025_RxChannels_e RX_CHANNEL_ARR[] = {ADI_ADRV9025_RX1, ADI_ADRV9025_RX2, ADI_ADRV9025_RX3, ADI_ADRV9025_RX4}; + static const adi_adrv9025_RxChannels_e ORX_CHANNEL_ARR[] = {ADI_ADRV9025_ORX1, ADI_ADRV9025_ORX2, ADI_ADRV9025_ORX3, ADI_ADRV9025_ORX4}; + static const uint32_t RX_CHANNEL_ARR_SIZE = sizeof(RX_CHANNEL_ARR) / sizeof(RX_CHANNEL_ARR[0]); + static const uint32_t ORX_CHANNEL_ARR_SIZE = sizeof(ORX_CHANNEL_ARR) / sizeof(ORX_CHANNEL_ARR[0]); + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxChannelArrIndex = 0; + uint8_t tempCompensationEn = 0; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_RX_CH0; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddr = ADRV9025_BF_ORX_CH0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + tempCompensationEn = (tempCompensationEnable > 0) ? 1 : 0; + + /*Iterate through channel mask and if set write the ext gain bitfield of the corresponding Rx channel*/ + for (rxChannelArrIndex = 0; rxChannelArrIndex < RX_CHANNEL_ARR_SIZE; rxChannelArrIndex++) + { + if ((rxChannelMask & (uint32_t)RX_CHANNEL_ARR[rxChannelArrIndex]) == (uint32_t)RX_CHANNEL_ARR[rxChannelArrIndex]) + { + /*If an Rx channel mask is set, resolve the corresponding Rx Bitfield Address*/ + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + RX_CHANNEL_ARR[rxChannelArrIndex], + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxGainCompForTempGainBfSet(device, + rxChannelBitfieldAddr, + tempCompensationEn); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Iterate through channel mask and if set write the ext gain bitfield of the corresponding ORx channel*/ + for (rxChannelArrIndex = 0; rxChannelArrIndex < ORX_CHANNEL_ARR_SIZE; rxChannelArrIndex++) + { + if ((rxChannelMask & (uint32_t)ORX_CHANNEL_ARR[rxChannelArrIndex]) == (uint32_t)ORX_CHANNEL_ARR[rxChannelArrIndex]) + { + /*If an Rx channel mask is set, resolve the corresponding Rx Bitfield Address*/ + recoveryAction = adrv9025_OrxBitfieldAddressGet(device, + ORX_CHANNEL_ARR[rxChannelArrIndex], + &orxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxGainCompForTempGainBfSet(device, + orxChannelBitfieldAddr, + tempCompensationEn); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxGainCompTempEnableGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint8_t* tempCompensationEnable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_RX_CH0; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddr = ADRV9025_BF_ORX_CH0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + tempCompensationEnable); + + if ((rxChannel == ADI_ADRV9025_RX1) || + (rxChannel == ADI_ADRV9025_RX2) || + (rxChannel == ADI_ADRV9025_RX3) || + (rxChannel == ADI_ADRV9025_RX4)) + { + recoveryAction = adrv9025_RxBitfieldAddressGet(device, + rxChannel, + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_RxGainCompForTempGainBfGet(device, + rxChannelBitfieldAddr, + tempCompensationEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if ((rxChannel == ADI_ADRV9025_ORX1) || + (rxChannel == ADI_ADRV9025_ORX2) || + (rxChannel == ADI_ADRV9025_ORX3) || + (rxChannel == ADI_ADRV9025_ORX4)) + { + recoveryAction = adrv9025_OrxBitfieldAddressGet(device, + rxChannel, + &orxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_OrxGainCompForTempGainBfGet(device, + orxChannelBitfieldAddr, + tempCompensationEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx channel encountered while attempting to retrieve temparature gain compensation Enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_RxDecPowerGetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel) +{ + static const uint32_t ALL_RX_MASK = (uint32_t)(ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4); + static const uint32_t ORX12_MASK = (uint32_t)(ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2); + static const uint32_t ORX34_MASK = (uint32_t)(ADI_ADRV9025_ORX3 | ADI_ADRV9025_ORX4); + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /*Check that the requested rxChannel is valid*/ + if ((rxChannel != ADI_ADRV9025_RX1) && + (rxChannel != ADI_ADRV9025_RX2) && + (rxChannel != ADI_ADRV9025_RX3) && + (rxChannel != ADI_ADRV9025_RX4) && + (rxChannel != ADI_ADRV9025_ORX1) && + (rxChannel != ADI_ADRV9025_ORX2) && + (rxChannel != ADI_ADRV9025_ORX3) && + (rxChannel != ADI_ADRV9025_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel Requested for manual rx dec power read"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that rx profile is valid in current config*/ + if (((uint32_t)rxChannel & ALL_RX_MASK) > 0) + { + if (((device->devStateInfo.profilesValid & ADI_ADRV9025_RX_PROFILE_VALID) == 0) + || (device->devStateInfo.initializedChannels & (uint32_t)rxChannel) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Dec Power read requested for an Rx channel but Rx profile is invalid or channel not initialized in device structure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Check that orx profile is valid in current config*/ + if (((uint32_t)rxChannel & (ORX12_MASK | ORX34_MASK)) > 0) + { + if (((device->devStateInfo.profilesValid & ADI_ADRV9025_ORX_PROFILE_VALID) == 0) + || (device->devStateInfo.initializedChannels & (uint32_t)rxChannel) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Dec Power read requested for an ORx channel but ORx profile is invalid or channel not initialized in device structure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxLoSourceGetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_LoSel_e* rxLoSource) +{ + static const uint32_t ALL_RX_MASK = (uint32_t)(ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4); + static const uint32_t ORX12_MASK = (uint32_t)(ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2); + static const uint32_t ORX34_MASK = (uint32_t)(ADI_ADRV9025_ORX3 | ADI_ADRV9025_ORX4); + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + rxLoSource); + + /*Check that the requested rxChannel is valid*/ + if ((rxChannel != ADI_ADRV9025_RX1) && + (rxChannel != ADI_ADRV9025_RX2) && + (rxChannel != ADI_ADRV9025_RX3) && + (rxChannel != ADI_ADRV9025_RX4) && + (rxChannel != ADI_ADRV9025_ORX1) && + (rxChannel != ADI_ADRV9025_ORX2) && + (rxChannel != ADI_ADRV9025_ORX3) && + (rxChannel != ADI_ADRV9025_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx channel selected for LO source mapping read back. Valid Rx channels are Rx1-Rx4, ORx1-ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that rx profile is valid in current config*/ + if (((uint32_t)rxChannel & ALL_RX_MASK) > 0) + { + if (((device->devStateInfo.profilesValid & ADI_ADRV9025_RX_PROFILE_VALID) == 0) + || (device->devStateInfo.initializedChannels & (uint32_t)rxChannel) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "LO source read back requested for an Rx channel but Rx profile is invalid or channel not initialized in the device structure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Check that orx profile is valid in current config*/ + if (((uint32_t)rxChannel & (ORX12_MASK | ORX34_MASK)) > 0) + { + if (((device->devStateInfo.profilesValid & ADI_ADRV9025_ORX_PROFILE_VALID) == 0) + || (device->devStateInfo.initializedChannels & (uint32_t)rxChannel) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "LO source read back requested for an ORx channel but ORx profile is invalid or channel not initialized in the device structure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxLoSourceGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_LoSel_e* rxLoSource) +{ + static const uint8_t RX_LO2_MASK = 0x01; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxtxLoMuxReg = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + rxLoSource); + + if ((rxChannel == ADI_ADRV9025_RX1) || + (rxChannel == ADI_ADRV9025_RX2)) + { + /*Read the Rx Tx Lo Mux reg from the west side of the chip (Aux PLL regs)*/ + recoveryAction = adrv9025_PllMemMapRx12SelLo2BfGet(device, + ADRV9025_BF_AUX_PLL, + &rxtxLoMuxReg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if ((rxChannel == ADI_ADRV9025_RX3) || + (rxChannel == ADI_ADRV9025_RX4)) + { + /*Read the Rx Tx Lo Mux reg from the west side of the chip (Aux PLL regs)*/ + recoveryAction = adrv9025_PllMemMapRx34SelLo2BfGet(device, + ADRV9025_BF_AUX_PLL, + &rxtxLoMuxReg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxtxLoMuxReg & RX_LO2_MASK) == 1) + { + *rxLoSource = ADI_ADRV9025_LOSEL_LO2; + } + else + { + *rxLoSource = ADI_ADRV9025_LOSEL_LO1; + } + + return recoveryAction; +} + +int32_t adrv9025_OrxLoSourceGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_LoSel_e* rxLoSource) +{ + static const uint32_t ORX_LOMUX_SEL_MASK = 0x01; + static const uint32_t ORX12_MASK = (uint32_t)(ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2); + static const uint32_t ORX34_MASK = (uint32_t)(ADI_ADRV9025_ORX3 | ADI_ADRV9025_ORX4); + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t orxLomuxReg = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + rxLoSource); + + if (((uint32_t)rxChannel & ORX12_MASK) > 0) + { + recoveryAction = adrv9025_AnalogOrxMemMapLomuxSelBfGet(device, + ADRV9025_BF_ANALOG_ORX_CH0, + &orxLomuxReg); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((orxLomuxReg & ORX_LOMUX_SEL_MASK) == ORX_LOMUX_SEL_MASK) + { + *rxLoSource = ADI_ADRV9025_LOSEL_AUXLO; + } + else + { + recoveryAction = adrv9025_TxLoSourceGet(device, + ADI_ADRV9025_TX1, + rxLoSource); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else if (((uint32_t)rxChannel & ORX34_MASK) > 0) + { + recoveryAction = adrv9025_AnalogOrxMemMapLomuxSelBfGet(device, + ADRV9025_BF_ANALOG_ORX_CH1, + &orxLomuxReg); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((orxLomuxReg & ORX_LOMUX_SEL_MASK) == ORX_LOMUX_SEL_MASK) + { + *rxLoSource = ADI_ADRV9025_LOSEL_AUXLO; + } + else + { + recoveryAction = adrv9025_TxLoSourceGet(device, + ADI_ADRV9025_TX3, + rxLoSource); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adrv9025_RxAgcEnableGainIndexUpdateLatch(adi_adrv9025_Device_t* device, + adrv9025_BfRxChanAddr_e rxChannelBitFieldAddr) +{ + static const uint32_t AGC_GAIN_INDEX_OFFSET = 0x9E; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t dummyValue = 0xFF; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + recoveryAction = adi_adrv9025_SpiByteWrite(device, + rxChannelBitFieldAddr + AGC_GAIN_INDEX_OFFSET, + dummyValue); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + + return recoveryAction; +} + +int32_t adrv9025_OrxOrx1AgcEnableGainIndexUpdateLatch(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e orxChannelBitFieldAddr) +{ + static const uint32_t AGC_GAIN_INDEX_OFFSET_ORX1 = 0xBB; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t dummyValue = 0xFF; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + recoveryAction = adi_adrv9025_SpiByteWrite(device, + orxChannelBitFieldAddr + AGC_GAIN_INDEX_OFFSET_ORX1, + dummyValue); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + + return recoveryAction; +} + +int32_t adrv9025_OrxOrx2AgcEnableGainIndexUpdateLatch(adi_adrv9025_Device_t* device, + adrv9025_BfOrxChanAddr_e orxChannelBitFieldAddr) +{ + static const uint32_t AGC_GAIN_INDEX_OFFSET_ORX2 = 0xBC; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t dummyValue = 0xFF; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + recoveryAction = adi_adrv9025_SpiByteWrite(device, + orxChannelBitFieldAddr + AGC_GAIN_INDEX_OFFSET_ORX2, + dummyValue); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_shared_resource_manager.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_shared_resource_manager.c new file mode 100644 index 0000000..9a3e032 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_shared_resource_manager.c @@ -0,0 +1,689 @@ +/** + * \file adrv9025_shared_resource_manager.c + * \brief Contains ADRV9025 shared resource related private function implementations + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "../../private/include/adrv9025_shared_resource_manager.h" +#include "adi_common_error_types.h" +#include "adi_adrv9025_gpio_types.h" +#include "adi_adrv9025_error.h" +#include "adi_adrv9025_hal.h" +#include "adi_common_macros.h" + +/******************************************** User Functions ********************************************************************/ + +int32_t adrv9025_SharedResourceMgrReset(adi_adrv9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t sharedResourceIndex = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + for (sharedResourceIndex = 0; sharedResourceIndex < ADRV9025_NUM_SHARED_RESOURCES; sharedResourceIndex++) + { + device->devStateInfo.sharedResourcePool[sharedResourceIndex].featureID = ADRV9025_FEATURE_UNUSED; + device->devStateInfo.sharedResourcePool[sharedResourceIndex].semaphoreCount = 0; + } + + return recoveryAction; +} + +int32_t adrv9025_SharedResourcesAcquire(adi_adrv9025_Device_t* device, + adrv9025_SharedResourceType_e sharedResourceType, + int32_t sharedResourceArr[], + uint32_t numSharedResources, + adrv9025_FeatureID_e featureID, + uint8_t* resourceAcquistionStatus) +{ + uint32_t sharedResourceIndex = 0; + adrv9025_SharedResourceID_e sharedResourceID = ADRV9025_SHARED_RESOURCE_INVALID; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check resourceAcquistionStatus pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + resourceAcquistionStatus); + + /*Range check that featureID is valid*/ + if (featureID >= ADRV9025_NUM_FEATURES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + featureID, + "featureID is not valid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Range Check that shared resource type is valid*/ + if (sharedResourceType >= ADRV9025_NUM_SHARED_RESOURCE_TYPES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + sharedResourceType, + "Invalid sharedResourceType encountered in adrv9025_SharedResourcesAcquire function"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Loop through each shared resource. + 1) Get Shared Resource unique ID + 2) Acquire Shared Resource + 3) If the resource is in use by another feature than the one which requested return a failed status*/ + for (sharedResourceIndex = 0; sharedResourceIndex < numSharedResources; sharedResourceIndex++) + { + adrv9025_SharedResourceIdGet(device, + sharedResourceType, + sharedResourceArr[sharedResourceIndex], + &sharedResourceID); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to resolve shared resource ID for the requested share resource"); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_SharedResourceAcquire(device, + sharedResourceID, + featureID, + resourceAcquistionStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to acquire requested share resource"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (*resourceAcquistionStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceAcquistionStatus, + "Error acquiring requested shared resource. Please check if the resource is already in use by another feature."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + } + + return device->common.error.newAction; +} + +int32_t adrv9025_SharedResourcesRelease(adi_adrv9025_Device_t* device, + adrv9025_SharedResourceType_e sharedResourceType, + int32_t sharedResourceArr[], + uint32_t numSharedResources, + adrv9025_FeatureID_e featureID, + uint8_t* resourceReleaseStatus) +{ + uint32_t sharedResourceIndex = 0; + adrv9025_SharedResourceID_e sharedResourceID = ADRV9025_SHARED_RESOURCE_INVALID; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check resourceReleaseStatus pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + resourceReleaseStatus); + + /*Range check that featureID is valid*/ + if (featureID >= ADRV9025_NUM_FEATURES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + featureID, + "featureID is not valid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Range Check that shared resource type is valid*/ + if (sharedResourceType >= ADRV9025_NUM_SHARED_RESOURCE_TYPES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + sharedResourceType, + "Invalid sharedResourceType encountered in adrv9025_SharedResourcesAcquire function"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Loop through each shared resource. + 1) Get Shared Resource unique ID + 2) Release Shared Resource + 3) If the resource is in use by another feature than the one which requested return a failed status*/ + for (sharedResourceIndex = 0; sharedResourceIndex < numSharedResources; sharedResourceIndex++) + { + adrv9025_SharedResourceIdGet(device, + sharedResourceType, + sharedResourceArr[sharedResourceIndex], + &sharedResourceID); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to resolve shared resource ID for the requested share resource"); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_SharedResourceRelease(device, + sharedResourceID, + featureID, + resourceReleaseStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to release requested share resource"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (*resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceReleaseStatus, + "Error releasing requested shared resource. Please check if the resource is already in use by another feature."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + } + + return device->common.error.newAction; +} + +/******************************************** Helper/Debug Functions ********************************************************************/ + +int32_t adrv9025_SharedResourceAvailabilityCheck(adi_adrv9025_Device_t* device, + adrv9025_SharedResourceID_e sharedResourceID, + uint8_t* sharedResourceAvailable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /*Range Check that shared resource ID is valid*/ + if (sharedResourceID >= ADRV9025_NUM_SHARED_RESOURCES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + sharedResourceID, + "sharedResourceID is not valid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Return success if shared resource pool index of shared resource ID has a feature other than UNUSED associated with it*/ + if (device->devStateInfo.sharedResourcePool[sharedResourceID].featureID == ADRV9025_FEATURE_UNUSED) + { + *sharedResourceAvailable = (uint8_t)ADI_TRUE; + } + else + { + *sharedResourceAvailable = (uint8_t)ADI_FALSE; + } + + return recoveryAction; +} + +int32_t adrv9025_SharedResourceIdGet(adi_adrv9025_Device_t* device, + adrv9025_SharedResourceType_e sharedResourceType, + int32_t sharedResource, + adrv9025_SharedResourceID_e* sharedResourceID) +{ + static const adrv9025_SharedResourceLut_t sharedResourceLut[] = { + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_00, ADRV9025_GPIO_00}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_01, ADRV9025_GPIO_01}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_02, ADRV9025_GPIO_02}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_03, ADRV9025_GPIO_03}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_04, ADRV9025_GPIO_04}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_05, ADRV9025_GPIO_05}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_06, ADRV9025_GPIO_06}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_07, ADRV9025_GPIO_07}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_08, ADRV9025_GPIO_08}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_09, ADRV9025_GPIO_09}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_10, ADRV9025_GPIO_10}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_11, ADRV9025_GPIO_11}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_12, ADRV9025_GPIO_12}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_13, ADRV9025_GPIO_13}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_14, ADRV9025_GPIO_14}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_15, ADRV9025_GPIO_15}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_16, ADRV9025_GPIO_16}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_17, ADRV9025_GPIO_17}, + {ADRV9025_SHARED_RESOURCE_GPIO, ADI_ADRV9025_GPIO_18, ADRV9025_GPIO_18}, + {ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, ADI_ADRV9025_GPIO_ANA_00, ADRV9025_GPIO_ANA_00}, + {ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, ADI_ADRV9025_GPIO_ANA_01, ADRV9025_GPIO_ANA_01}, + {ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, ADI_ADRV9025_GPIO_ANA_02, ADRV9025_GPIO_ANA_02}, + {ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, ADI_ADRV9025_GPIO_ANA_03, ADRV9025_GPIO_ANA_03}, + {ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, ADI_ADRV9025_GPIO_ANA_04, ADRV9025_GPIO_ANA_04}, + {ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, ADI_ADRV9025_GPIO_ANA_05, ADRV9025_GPIO_ANA_05}, + {ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, ADI_ADRV9025_GPIO_ANA_06, ADRV9025_GPIO_ANA_06}, + {ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, ADI_ADRV9025_GPIO_ANA_07, ADRV9025_GPIO_ANA_07} + }; + /*****************Please add lut val for shared resources above this line*******************/ + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t sharedResourceIndex = 0; + uint8_t validSharedResourceTypeFlag = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + sharedResourceID); + + /*Range Check that shared resource type is valid*/ + if (sharedResourceType >= ADRV9025_NUM_SHARED_RESOURCE_TYPES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + sharedResourceType, + "Invalid sharedResourceType encountered in adrv9025_SharedResourcesAcquire function"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (sharedResourceIndex = 0; sharedResourceIndex < ADRV9025_NUM_SHARED_RESOURCES; sharedResourceIndex++) + { + if (sharedResourceLut[sharedResourceIndex].sharedResourceType == sharedResourceType) + { + if (sharedResourceLut[sharedResourceIndex].sharedResource == sharedResource) + { + *sharedResourceID = sharedResourceLut[sharedResourceIndex].sharedResourceId; + validSharedResourceTypeFlag = 1; + break; + } + } + } + + /* Check not a valid shared resource ID found */ + if (validSharedResourceTypeFlag == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + sharedResourceType, + "Requested Shared Resource is not valid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_SharedResourceFeatureGet(adi_adrv9025_Device_t* device, + adrv9025_SharedResourceID_e sharedResourceID, + adrv9025_FeatureID_e* featureID) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /*Range check that featureID is not null*/ + ADI_NULL_PTR_RETURN(&device->common, + featureID); + + /*Range Check that shared resource ID is valid*/ + if (sharedResourceID >= ADRV9025_NUM_SHARED_RESOURCES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + sharedResourceID, + "sharedResourceID is not valid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Return the feature associated with shared resource pool*/ + *featureID = device->devStateInfo.sharedResourcePool[sharedResourceID].featureID; + + return recoveryAction; +} + +int32_t adrv9025_SharedResourceFeatureMaxSemaphoreCntGet(adi_adrv9025_Device_t* device, + adrv9025_FeatureID_e featureID, + uint8_t* maxSemaphoreCount) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /*Range check that the maximum semaphore count pointer is not null*/ + ADI_NULL_PTR_RETURN(&device->common, + maxSemaphoreCount); + + /*Range Check that feature ID is valid*/ + if (featureID >= ADRV9025_NUM_FEATURES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + featureID, + "The feature ID requested for retrieving maximum semaphore count is not valid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + switch (featureID) + { + case(ADRV9025_FEATURE_RX_GAIN_CTRL_PIN): + { + *maxSemaphoreCount = (uint8_t)ADRV9025_FEATURE_RX_GAIN_CTRL_PIN_MAX_SEMAPHORE_COUNT; + break; + } + case(ADRV9025_FEATURE_RX_PIN_CTRL_ATTN): + { + *maxSemaphoreCount = (uint8_t)ADRV9025_FEATURE_RX_PIN_CTRL_ATTN_MAX_SEMAPHORE_COUNT; + break; + } + case(ADRV9025_FEATURE_RX_EXT_CTRL_WORD_OUTPUT): + { + *maxSemaphoreCount = (uint8_t)ADRV9025_FEATURE_RX_GAIN_CTRL_PIN_MAX_SEMAPHORE_COUNT; + break; + } + case(ADRV9025_FEATURE_RX_DUALBAND_LNA_CTRL_WORD_OUTPUT): + { + *maxSemaphoreCount = (uint8_t)ADRV9025_FEATURE_RX_EXT_CTRL_WORD_OUTPUT_MAX_SEMAPHORE_COUNT; + break; + } + case(ADRV9025_FEATURE_TX_ATTEN_CTRL_PIN): + { + *maxSemaphoreCount = (uint8_t)ADRV9025_FEATURE_TX_ATTEN_CTRL_PIN_MAX_SEMAPHORE_COUNT; + break; + } + case(ADRV9025_FEATURE_SPI2_CTRL_PIN): + { + *maxSemaphoreCount = (uint8_t)ADRV9025_FEATURE_SPI2_CTRL_PIN_MAX_SEMAPHORE_COUNT; + break; + } + case(ADRV9025_FEATURE_ARM_GPIO_PIN): + { + *maxSemaphoreCount = (uint8_t)ADRV9025_FEATURE_ARM_GPIO_PIN_MAX_SEMAPHORE_COUNT; + break; + } + case(ADRV9025_FEATURE_RX_EXT_SLICER_CTRL): + { + *maxSemaphoreCount = (uint8_t)ADRV9025_FEATURE_RX_EXT_SLICER_CTRL_MAX_SEMAPHORE_COUNT; + break; + } + case(ADRV9025_FEATURE_RX_INT_SLICER_CTRL_OUT): + { + *maxSemaphoreCount = (uint8_t)ADRV9025_FEATURE_RX_INT_SLICER_CTRL_OUT_MAX_SEMAPHORE_COUNT; + break; + } + case(ADRV9025_FEATURE_AUX_DAC_OUT): + { + *maxSemaphoreCount = (uint8_t)ADRV9025_FEATURE_AUX_DAC_OUT_MAX_SEMAPHORE_COUNT; + break; + } + case(ADRV9025_FEATURE_GPIO_STREAM_TRIGGER): + { + *maxSemaphoreCount = (uint8_t)ADRV9025_FEATURE_GPIO_STREAM_TRIGGER_MAX_SEMAPHORE_COUNT; + break; + } + case(ADRV9025_FEATURE_FOVR): + { + *maxSemaphoreCount = (uint8_t)ADRV9025_FEATURE_FOVR_MAX_SEMAPHORE_COUNT; + break; + } + case(ADRV9025_FEATURE_PCA): + { + *maxSemaphoreCount = (uint8_t)ADRV9025_FEATURE_PCA_MAX_SEMAPHORE_COUNT; + break; + } + case(ADRV9025_FEATURE_TX_ATTEN_UPDATE_PIN): + { + *maxSemaphoreCount = (uint8_t)ADRV9025_FEATURE_TX_ATTEN_UPDATE_PIN_MAX_SEMAPHORE_COUNT; + break; + } + case(ADRV9025_FEATURE_EXT_DPD_CAPTURE_DONE_PIN): + { + *maxSemaphoreCount = (uint8_t)ADRV9025_FEATURE_EXT_DPD_CAPTURE_DONE_PIN_MAX_SEMAPHORE_COUNT; + break; + } + default: + { + *maxSemaphoreCount = 1; + break; + } + } + + return recoveryAction; +} + +int32_t adrv9025_SharedResourceAcquire(adi_adrv9025_Device_t* device, + adrv9025_SharedResourceID_e sharedResourceID, + adrv9025_FeatureID_e featureID, + uint8_t* resourceAcquistionStatus) +{ + uint8_t sharedResourceAvailable = (uint8_t)ADI_FALSE; + adrv9025_FeatureID_e currentFeatureID = ADRV9025_FEATURE_UNUSED; + uint8_t maxSemaphoreCount = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check resourceAcquistionStatus pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + resourceAcquistionStatus); + + /*Range check that featureID is valid*/ + if (featureID >= ADRV9025_NUM_FEATURES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + featureID, + "featureID is not valid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Range check that sharedResourceID is valid*/ + if (sharedResourceID >= ADRV9025_NUM_SHARED_RESOURCES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + sharedResourceID, + "sharedResourceID is not valid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Initialize resourceAcquistionStatus to false and set to true only if shared resource available*/ + *resourceAcquistionStatus = ADI_FAILURE; + + /*sharedResourceID check is done in Shared Resource Available function*/ + /*Acquire resource if it is not already acquired by another feature or already acquired by the requesting feature*/ + adrv9025_SharedResourceAvailabilityCheck(device, + sharedResourceID, + &sharedResourceAvailable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while checking for shared resource availability"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (sharedResourceAvailable == ADI_TRUE) + { + device->devStateInfo.sharedResourcePool[sharedResourceID].featureID = featureID; + device->devStateInfo.sharedResourcePool[sharedResourceID].semaphoreCount++; + *resourceAcquistionStatus = ADI_SUCCESS; + } + else + { + adrv9025_SharedResourceFeatureGet(device, + sharedResourceID, + ¤tFeatureID); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while acquiring shared resource feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (currentFeatureID == featureID) + { + adrv9025_SharedResourceFeatureMaxSemaphoreCntGet(device, + featureID, + &maxSemaphoreCount); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (device->devStateInfo.sharedResourcePool[sharedResourceID].semaphoreCount < maxSemaphoreCount) + { + device->devStateInfo.sharedResourcePool[sharedResourceID].semaphoreCount++; + *resourceAcquistionStatus = ADI_SUCCESS; + } + } + } + + return device->common.error.newAction; +} + +int32_t adrv9025_SharedResourceRelease(adi_adrv9025_Device_t* device, + adrv9025_SharedResourceID_e sharedResourceID, + adrv9025_FeatureID_e featureID, + uint8_t* resourceReleaseStatus) +{ + uint8_t sharedResourceAvailable = ADI_FALSE; + adrv9025_FeatureID_e currentFeatureID = ADRV9025_FEATURE_UNUSED; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check resourceReleaseStatus pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + resourceReleaseStatus); + + /*Range check that featureID is valid*/ + if (featureID >= ADRV9025_NUM_FEATURES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + featureID, + "featureID is not valid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Range check that sharedResourceID is valid*/ + if (sharedResourceID >= ADRV9025_NUM_SHARED_RESOURCES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + sharedResourceID, + "sharedResourceID is not valid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Initialize resourceReleaseStatus to false and set to true only if shared resource is released successfully*/ + *resourceReleaseStatus = ADI_FAILURE; + + /*sharedResourceID check is done in Shared Resource Available function*/ + /*Release the shared resource only if the requested feature ID matches the current feature ID or is not in use currently*/ + adrv9025_SharedResourceAvailabilityCheck(device, + sharedResourceID, + &sharedResourceAvailable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while checking for shared resource availability"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (sharedResourceAvailable == ADI_TRUE) + { + *resourceReleaseStatus = ADI_SUCCESS; + } + else + { + adrv9025_SharedResourceFeatureGet(device, + sharedResourceID, + ¤tFeatureID); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while acquiring shared resource feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (currentFeatureID == featureID) + { + if (device->devStateInfo.sharedResourcePool[sharedResourceID].semaphoreCount > 0) + { + device->devStateInfo.sharedResourcePool[sharedResourceID].semaphoreCount--; + } + + if (device->devStateInfo.sharedResourcePool[sharedResourceID].semaphoreCount == 0) + { + device->devStateInfo.sharedResourcePool[sharedResourceID].featureID = ADRV9025_FEATURE_UNUSED; + } + + *resourceReleaseStatus = ADI_SUCCESS; + } + } + + return device->common.error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_tx.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_tx.c new file mode 100644 index 0000000..9afa499 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_tx.c @@ -0,0 +1,1568 @@ +/** +* \file adrv9025_tx.c +* \brief Contains ADRV9025 transmit related function implementations +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "../../private/include/adrv9025_init.h" +#include "../../private/include/adrv9025_tx.h" +#include "../../private/include/adrv9025_bf_core.h" +#include "../../private/include/adrv9025_bf_txdac_mem_map.h" +#include "../../private/include/adrv9025_bf_pll_mem_map.h" +#include "adi_adrv9025_error.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_gpio.h" +#include "../../private/include/adrv9025_shared_resource_manager.h" +#include "../../private/include/adrv9025_bf_txdac_mem_map_types.h" + +#define IF_INVALID_TX_CHANNEL_RETURN(txChannel); \ +{\ + if ((txChannel != ADI_ADRV9025_TX1) && \ + (txChannel != ADI_ADRV9025_TX2) && \ + (txChannel != ADI_ADRV9025_TX3) && \ + (txChannel != ADI_ADRV9025_TX4) && \ + (txChannel != ADI_ADRV9025_TXALL) && \ + (txChannel > ADI_ADRV9025_TXALL)) \ + { \ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, txChannel, \ + "Invalid Tx Channel Parameter encountered"); \ + ADI_ERROR_RETURN(device->common.error.newAction); \ + } \ +} + +#define ADI_ADRV9025_NUM_GPIOS_IN_TX_ATTEN_UPDATE_PIN_FEATURE 1 +#define ADI_ADRV9025_NUM_GPIOS_IN_TX_ATTEN_CTRL_PIN_FEATURE 2 + +uint16_t adrv9025_TxDacAddrDecode(adi_adrv9025_Device_t* device, + uint32_t channelMask) +{ + if (device == NULL) + { + return 0; + } + + if (((device->devStateInfo.initializedChannels >> ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET) & channelMask) != channelMask) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelMask, + "Tx channel not in device initializedChannels"); + return 0; + } + + switch (channelMask) + { + case ADI_ADRV9025_TX1: + return ADRV9025_BF_TXDAC_CH0; + case ADI_ADRV9025_TX2: + return ADRV9025_BF_TXDAC_CH1; + case ADI_ADRV9025_TX3: + return ADRV9025_BF_TXDAC_CH2; + case ADI_ADRV9025_TX4: + return ADRV9025_BF_TXDAC_CH3; + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelMask, + "Tx channel is invalid"); + return (0); + } + } +} + +uint16_t adrv9025_TxAddrDecode(adi_adrv9025_Device_t* device, + uint32_t channelMask) +{ + if (device == NULL) + { + return 0; + } + + if (((device->devStateInfo.initializedChannels >> ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET) & channelMask) != channelMask) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelMask, + "TX channel not in device initializedChannels"); + return 0; + } + + switch (channelMask) + { + case ADI_ADRV9025_TX1: + return ADRV9025_ADDR_CH0_TX; + case ADI_ADRV9025_TX2: + return ADRV9025_ADDR_CH1_TX; + case ADI_ADRV9025_TX3: + return ADRV9025_ADDR_CH2_TX; + case ADI_ADRV9025_TX4: + return ADRV9025_ADDR_CH3_TX; + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelMask, + "Tx channel is invalid"); + return (0); + } + } +} + +int32_t adrv9025_TxAttenCtrlPinReportError(adi_adrv9025_Device_t* device, + int32_t sharedResourceArr[], + int32_t recoveryAction, + const char* customError) +{ + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_TX_ATTEN_CTRL_PIN; + static const uint32_t NUM_GPIOS_IN_TX_ATTEN_CTRL_PIN_FEATURE = 2U; + + int32_t recAct = ADI_COMMON_ACT_NO_ACTION; + uint8_t resourceReleaseStatus = ADI_FAILURE; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /* Check rx bitfield channel address pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + sharedResourceArr); + + if (recoveryAction > ADI_COMMON_ACT_NO_ACTION) + { + recAct = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + NUM_GPIOS_IN_TX_ATTEN_CTRL_PIN_FEATURE, + THIS_FEATURE_ID, + &resourceReleaseStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recAct, + NULL, + "Error while attempting to release GPIO shared resouce for GPIO Tx attenuation ctrl Increment/Decrement Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recAct, + resourceReleaseStatus, + "Error while attempting to release GPIO shared resouce for GPIO Tx attenutaion ctrl Increment/Decrement Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + customError); + + return recoveryAction; +} + +int32_t adrv9025_TxAttenSpi2CtrlPinReportError(adi_adrv9025_Device_t* device, + int32_t sharedResourceArr[], + int32_t recoveryAction, + const char* customError) +{ + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_TX_ATTEN_CTRL_PIN; + static const uint32_t NUM_GPIOS_IN_TX_SPI2_PIN_FEATURE = 1U; + + int32_t recAct = ADI_COMMON_ACT_NO_ACTION; + uint8_t resourceReleaseStatus = ADI_FAILURE; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check rx bitfield channel address pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(sharedResourceArr); + + if (recoveryAction > ADI_COMMON_ACT_NO_ACTION) + { + recAct = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + NUM_GPIOS_IN_TX_SPI2_PIN_FEATURE, + THIS_FEATURE_ID, + &resourceReleaseStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to release GPIO shared resouce for GPIO Tx attenuation ctrl Spi2 Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceReleaseStatus, + "Error while attempting to release GPIO shared resouce for GPIO Tx attenutaion ctrl Spi2 Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + customError); + + return recAct; +} + +int32_t adrv9025_TxAttenPinCtrlCfgSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_TxAttenPinCfg_t* txAttenPinCtrlCfg) +{ + static const uint8_t MAX_ATTEN_STEP = 31; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /*Check rxGainPinCtrlCfg pointer is not null*/ + ADI_NULL_PTR_RETURN(&device->common, + txAttenPinCtrlCfg); + + /*Check that gain increment step is between 0-31*/ + if (txAttenPinCtrlCfg->stepSize > MAX_ATTEN_STEP) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenPinCtrlCfg->stepSize, + "Attenuation step exceeds limit for GPIO gain control config. Valid range 0-31"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*GPIOs 0-15 are valid for GPIO gain control*/ + if (txAttenPinCtrlCfg->txAttenIncPin > ADI_ADRV9025_GPIO_15) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenPinCtrlCfg->txAttenIncPin, + "Attenuation Increment pin for GPIO ctrl is out of range. Valid values GPIO_0 - GPIO_15"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*GPIOs 0-15 are valid for GPIO gain control*/ + if (txAttenPinCtrlCfg->txAttenDecPin > ADI_ADRV9025_GPIO_15) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenPinCtrlCfg->txAttenDecPin, + "Attenuation Decrement pin for GPIO ctrl is out of range. Valid values GPIO_0 - GPIO_15"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that attenuation increment and decrement GPIO pins are not the same*/ + if (txAttenPinCtrlCfg->txAttenDecPin == txAttenPinCtrlCfg->txAttenIncPin) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenPinCtrlCfg, + "Attenuation Decrement pin cannot be same as attenuation Increment pin for GPIO attenuation ctrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_TxAttenModeSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_TxAttenMode_e txAttenMode, + adi_adrv9025_TxAttenSimultUpdateCfg_t simultaneousUpdateCfg, + adi_adrv9025_TxAttenPinCfg_t gpioModePinCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /*Check that attenuation mode is in range */ + if (txAttenMode > ADI_ADRV9025_TXATTEN_SPI2_MODE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenMode, + "Selected Tx attenuation mode is invalid, Valid Values BYPASS/SPI/GPIO/SPI2"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((simultaneousUpdateCfg.simultaneousUpdate != ADI_ADRV9025_TXATTEN_SIMULTAN_UPDATE_DISABLED) && (txAttenMode != ADI_ADRV9025_TXATTEN_SPI_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + simultaneousUpdate, + "Tx attenuation simultaneous update feature can only be used on Tx attenuation Spi mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((simultaneousUpdateCfg.simultaneousUpdate == ADI_ADRV9025_TXATTEN_SIMULTAN_UPDATE_DISABLED) && (simultaneousUpdateCfg.gpioUpdatePin != + ADI_ADRV9025_GPIO_INVALID)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + simultaneousUpdate, + "GPIO selection should be invalid, when Tx atteunation simultaneous update feature is not being used."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txAttenMode != ADI_ADRV9025_TXATTEN_GPIO_MODE) && ((gpioModePinCfg.txAttenIncPin != ADI_ADRV9025_GPIO_INVALID) || (gpioModePinCfg.txAttenDecPin != + ADI_ADRV9025_GPIO_INVALID))) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioModePinCfg, + "Inc/Dec pins should be selected INVALID when GPIO mode is not being used"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txAttenMode == ADI_ADRV9025_TXATTEN_GPIO_MODE) && ((gpioModePinCfg.txAttenIncPin == ADI_ADRV9025_GPIO_INVALID) || (gpioModePinCfg.txAttenDecPin == + ADI_ADRV9025_GPIO_INVALID))) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioModePinCfg, + "Inc/Dec pins shouldn't be invalid when Tx attenution mode is GPIO"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_TxAttenCfgSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_TxAttenCfg_t* txAttenCfg) +{ + static const uint8_t MAX_ATTEN_STEP = 0x03; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /*Check rxGainPinCtrlCfg pointer is not null*/ + ADI_NULL_PTR_RETURN(&device->common, + txAttenCfg); + + /*Check that the requested rxChannel is valid*/ + IF_INVALID_TX_CHANNEL_RETURN(txAttenCfg->txChannelMask); + + /*Check that gain increment step is between 0-7*/ + if (txAttenCfg->txAttenStepSize > MAX_ATTEN_STEP) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenCfg->txAttenStepSize, + "Attenuation step exceeds limit for GPIO gain control config. Valid range 0-3"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_TxTestToneCfgSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_TxTestToneCfg_t* txToneCfg) +{ + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + /*Check rxGainPinCtrlCfg pointer is not null*/ + ADI_NULL_PTR_RETURN(&device->common, + txToneCfg); + + /*Check that the requested rxChannel is valid*/ + IF_INVALID_TX_CHANNEL_RETURN(txToneCfg->txChannelMask); + + /*Check that gain increment step is between 0-7*/ + /* TODO: Is this range check already covered in the bitfield write function? */ + if (txToneCfg->txToneGain > 3) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txToneCfg->txToneGain, + "Tone gain is invalid, valid range 0-3"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Tone Frequency is checked in top level function because it needs to be checked per channel, since + * each channel can have a different Tx Sample rate */ + + return device->common.error.newAction; +} + +int32_t adrv9025_TxFirWrite(adi_adrv9025_Device_t* device, + uint32_t txChanMask, + int8_t gain_dB, + uint8_t numFirCoefs, + int16_t coefs[], + uint8_t arraySize) +{ + uint8_t i = 0; + uint8_t j = 0; + uint8_t numTapsReg = 0; + uint8_t nTapMul = 0; + uint8_t maxNumTaps = 0; + uint8_t filterGain = 0; + uint8_t pfirCoeffCtl = 0; + uint16_t baseaddr = 0; + uint8_t filterConfig = 0; + static const uint8_t autoInc = ADI_ADRV9025_PFIR_COEFF_AUTO_INCR; + static const uint8_t TXFIR_MAXTAPS = 80; + static const uint8_t TXFIR_MULTAPS = 20; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + coefs); + + ADRV9025_BUGINFO(__FUNCTION__); + + if (adrv9025_TxAddrDecode(device, + txChanMask) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChanMask, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Error checking, #taps less than max number of taps allowed.*/ + if (numFirCoefs == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + numFirCoefs, + "NumFirCoef is zero"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (arraySize == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + arraySize, + "arraySize is zero"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + maxNumTaps = TXFIR_MAXTAPS; + nTapMul = TXFIR_MULTAPS; + + /* Verification for the structure numFirCoefs */ + if (numFirCoefs > maxNumTaps) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + numFirCoefs, + "NumFirCoef is too large"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (numFirCoefs > arraySize) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + numFirCoefs, + "NumFirCoef is larger than arraySize"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Calculate register value for number of Taps */ + if (((numFirCoefs % nTapMul) == 0) && + (numFirCoefs > 0)) + { + numTapsReg = (numFirCoefs / nTapMul) - 1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + numFirCoefs, + "Invalid numFirCoefs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + pfirCoeffCtl |= ADRV9025_PFIR_COEFF_PROG_CLK_EN | ADRV9025_PFIR_COEFF_WR_ENABLE; + if (autoInc != 0) + { + pfirCoeffCtl |= ADRV9025_PFIR_COEFF_AUTO_INCR; + } + + baseaddr = adrv9025_TxAddrDecode(device, + txChanMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + ADRV9025_SPIWRITEBYTE("TX_PFIR_COEFF_CTL", + (baseaddr + ADRV9025_ADDR_TX_PFIR_COEFF_CTL_OFFSET), + pfirCoeffCtl); + + j = 0; + ADRV9025_SPIWRITEBYTE("TX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_TX_PFIR_COEFF_ADDR_OFFSET), + j); + + for (i = 0; i < numFirCoefs; i++) + { + //pfir_coeff_data LSB + ADRV9025_SPIWRITEBYTE("TX_PFIR_COEFF_DATA_LSB", + (baseaddr + ADRV9025_ADDR_TX_PFIR_COEFF_DATA_OFFSET), + (uint8_t)(coefs[i])); + if (autoInc == 0) + { + j++; + ADRV9025_SPIWRITEBYTE("TX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_TX_PFIR_COEFF_ADDR_OFFSET), + j); + } + //pfir_coeff_data MSB + ADRV9025_SPIWRITEBYTE("TX_PFIR_COEFF_DATA_MSB", + (baseaddr + ADRV9025_ADDR_TX_PFIR_COEFF_DATA_OFFSET), + (uint8_t)(coefs[i] >> 8)); + if (autoInc == 0) + { + j++; + ADRV9025_SPIWRITEBYTE("TX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_TX_PFIR_COEFF_ADDR_OFFSET), + j); + } + } + + /* disable pfir_coeff_prog_clk_en */ + /* disable pfir_coeff_wr_enable */ + pfirCoeffCtl = 0; + + ADRV9025_SPIWRITEBYTE("TX_PFIR_COEFF_CTL", + (baseaddr + ADRV9025_ADDR_TX_PFIR_COEFF_CTL_OFFSET), + pfirCoeffCtl); + + /* Set filter gain to be used */ + switch (gain_dB) + { + case ADRV9025_FIR_GAIN_NEG12_DB: + filterGain = 0x00; + break; + case ADRV9025_FIR_GAIN_NEG6_DB: + filterGain = 0x01; + break; + case ADRV9025_FIR_GAIN_0_DB: + filterGain = 0x02; + break; + case ADRV9025_FIR_GAIN_POS6_DB: + filterGain = 0x03; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gain_dB, + "Invalid FirGain"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + filterConfig = 0; + /* write filter gain and #taps if TX, else is RX */ + /* tx_pfir_Taps */ + filterConfig |= ADRV9025_BF_ENCODE(numTapsReg, + ADRV9025_TX_PFIR_TAPS_MASK, + ADRV9025_TX_PFIR_TAPS_SHIFT); + + /* tx_pfir_gain */ + filterConfig |= ADRV9025_BF_ENCODE(filterGain, + ADRV9025_TX_PFIR_GAIN_MASK, + ADRV9025_TX_PFIR_GAIN_SHIFT); + + ADRV9025_SPIWRITEBYTE("TX_FILTER_CONFIG", + (baseaddr + ADRV9025_ADDR_TX_FILTER_CONFIG_OFFSET), + filterConfig); + + return (device->common.error.newAction); +} + +uint32_t adrv9025_txAttenAddrLookup(adi_adrv9025_Device_t* device, + uint32_t channelMask) +{ + if (((device->devStateInfo.initializedChannels >> ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET) & channelMask) != channelMask) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + ChannelMask, + "Channel not in device initializedChannels for adrv9025_txAttenAddrLookup() function"); + return 0; + } + + switch (channelMask) + { + case ADI_ADRV9025_TX1: + return ADRV9025_ADDR_TX1_ATTEN_TABLE; + case ADI_ADRV9025_TX2: + return ADRV9025_ADDR_TX2_ATTEN_TABLE; + case ADI_ADRV9025_TX3: + return ADRV9025_ADDR_TX3_ATTEN_TABLE; + case ADI_ADRV9025_TX4: + return ADRV9025_ADDR_TX4_ATTEN_TABLE; + default: + return 0; + } +} + +int32_t adrv9025_TxAttenTableWriteRangeCheck(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + uint32_t txAttenIndexOffset, + adi_adrv9025_TxAttenTableRow_t txAttenTableRows[], + uint32_t numTxAttenEntries) +{ + static const uint8_t TX_ATTEN_HP_MIN = 0; + static const uint8_t TX_ATTEN_HP_MAX = 63; + static const uint16_t TX_ATTEN_MULT_MIN = 0; + static const uint16_t TX_ATTEN_MULT_MAX = 4095; + + uint32_t j = 0; + uint32_t maxAttenIndex = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + txAttenTableRows); + + ADRV9025_BUGINFO(__FUNCTION__); + + maxAttenIndex = ADRV9025_TX_ATTEN_TABLE_MAX; + + if ((txChannelMask < 1) || (txChannelMask > 0xF)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid TxChannelMask"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((numTxAttenEntries < 1) || (numTxAttenEntries > maxAttenIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid numTxAttenEntries"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (txAttenIndexOffset + numTxAttenEntries > maxAttenIndex) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid txAttenIndexOffset + numTxAttenEntries"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (j = 0; j < numTxAttenEntries; j++) + { + if ((txAttenTableRows[j].txAttenHp < TX_ATTEN_HP_MIN) || + (txAttenTableRows[j].txAttenHp > TX_ATTEN_HP_MAX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid txAttenHp"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txAttenTableRows[j].txAttenMult < TX_ATTEN_MULT_MIN) || + (txAttenTableRows[j].txAttenMult > TX_ATTEN_MULT_MAX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid txAttenMult"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adrv9025_TxPaProtectCfgRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_TxPaProtectCfg_t* txPaProtectCfg) +{ + /* Valid ranges for the pa protection configuration values */ + static const uint8_t AVG_DURATION_MAX = 0x0F; + static const uint8_t PEAK_DURATION_MAX = 0x0F; + static const uint16_t POWER_THRESH_MAX = 0x1FFF; + static const uint16_t PEAK_THRESH_MAX = 0x1FFF; + static const uint8_t PEAK_COUNT_MAX = 0x1F; + static const uint8_t SINGLE_BIT_MAX = 0x01; + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + if (txPaProtectCfg->avgDuration > AVG_DURATION_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txPaProtectCfg->avgDuration, + "Average duration exceeds maximum limit. Valid range 0-15"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (txPaProtectCfg->peakDuration > PEAK_DURATION_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txPaProtectCfg->peakDuration, + "Peak duration exceeds maximum limit. Valid range 0-15"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (txPaProtectCfg->powerThreshold > POWER_THRESH_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txPaProtectCfg->powerThreshold, + "Power Threshold exceeds maximum limit. Valid range 0-8191, [0:12] bits"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (txPaProtectCfg->peakThreshold > PEAK_THRESH_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txPaProtectCfg->peakThreshold, + "Peak threshold exceeds maximum limit. Valid range 0-8191 for Silicon B"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if (txPaProtectCfg->peakCount > PEAK_COUNT_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txPaProtectCfg->peakCount, + "Peak count exceeds maximum limit. Valid range 0-31 / Silicon B"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (txPaProtectCfg->avgPowerEnable > SINGLE_BIT_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txPaProtectCfg->avgPowerEnable, + "Avg power enable value is invalid. Valid values 0-1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (txPaProtectCfg->peakPowerEnable > SINGLE_BIT_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txPaProtectCfg->peakPowerEnable, + "Peak power enable value is invalid. Valid values 0-1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (txPaProtectCfg->avgPeakRatioEnable > SINGLE_BIT_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txPaProtectCfg->avgPeakRatioEnable, + "Avg Peak power ratio enable value is invalid. Valid values 0-1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txPaProtectCfg->inputSel != ADI_ADRV9025_COMPLEX_MULT_OUTPUT) && (txPaProtectCfg->inputSel != ADI_ADRV9025_TXQEC_ACTUATOR_OUTPUT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txPaProtectCfg->inputSel, + "Pa protection input selection is invalid. COMPLEX_MULT_OUTPUT and TXQEC_ACTUATOR_OUTPUT"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adrv9025_TxLoSourceGetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_LoSel_e* txLoSource) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + txLoSource); + + /*Check that the requested txChannel is valid*/ + if ((txChannel != ADI_ADRV9025_TX1) && + (txChannel != ADI_ADRV9025_TX2) && + (txChannel != ADI_ADRV9025_TX3) && + (txChannel != ADI_ADRV9025_TX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid Tx channel selected for LO source mapping read back. Valid Tx channels are Tx1-Tx4."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that tx profile is valid in current config*/ + if (((device->devStateInfo.profilesValid & ADI_ADRV9025_TX_PROFILE_VALID) == 0) + || ((device->devStateInfo.initializedChannels >> ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET) & (uint32_t)txChannel) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "LO source read back requested for Tx channel but Tx profile is invalid or channel not initialized in the device structure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_TxLoSourceGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_LoSel_e* txLoSource) +{ + static const uint8_t TX_LO2_MASK = 0x01; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxtxLoMuxReg = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + txLoSource); + + if ((txChannel == ADI_ADRV9025_TX1) || + (txChannel == ADI_ADRV9025_TX2)) + { + /*Read the Rx Tx Lo Mux reg from the west side of the chip (Aux PLL regs)*/ + recoveryAction = adrv9025_PllMemMapTx12SelLo2BfGet(device, + ADRV9025_BF_AUX_PLL, + &rxtxLoMuxReg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if ((txChannel == ADI_ADRV9025_TX3) || + (txChannel == ADI_ADRV9025_TX4)) + { + /*Read the Rx Tx Lo Mux reg from the west side of the chip (Aux PLL regs)*/ + recoveryAction = adrv9025_PllMemMapTx34SelLo2BfGet(device, + ADRV9025_BF_AUX_PLL, + &rxtxLoMuxReg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxtxLoMuxReg & TX_LO2_MASK) == 1) + { + *txLoSource = ADI_ADRV9025_LOSEL_LO2; + } + else + { + *txLoSource = ADI_ADRV9025_LOSEL_LO1; + } + + return recoveryAction; +} + +int32_t adrv9025_TxAttenPinCtrlCfgSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e txChannelBaseAddr, + adi_adrv9025_TxAttenPinCfg_t txAttenPinCfg, + uint8_t releaseCurrentPins, + uint8_t acquireNewPins) +{ + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_TX_ATTEN_CTRL_PIN; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t TX_GAIN_CTRL_INC_PIN_INDEX = 0; + uint32_t TX_GAIN_CTRL_DEC_PIN_INDEX = 1; + int32_t sharedResourceArr[ADI_ADRV9025_NUM_GPIOS_IN_TX_ATTEN_CTRL_PIN_FEATURE] = {0}; + uint8_t resourceAcquisitionStatus = ADI_FAILURE; + uint8_t resourceReleaseStatus = ADI_FAILURE; + uint8_t currentTxAttenCtrlIncPin = 0; + uint8_t currentTxAttenCtrlDecPin = 0; + uint32_t incGpioPinMask = 0; + uint32_t decGpioPinMask = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if (releaseCurrentPins != ADI_FALSE) + { + /*Read Tx Attenuation Decrement GPIO select */ + recoveryAction = adrv9025_TxTpcDecrAttenGpioSelectBfGet(device, + txChannelBaseAddr, + ¤tTxAttenCtrlDecPin); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read Attenuation decrement GPIO select register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Read Rx Attenuation Increment GPIO select*/ + recoveryAction = adrv9025_TxTpcIncrAttenGpioSelectBfGet(device, + txChannelBaseAddr, + ¤tTxAttenCtrlIncPin); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read Attenuation increment GPIO select register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Attempt to Release Attenuation Ctrl GPIO Pins */ + sharedResourceArr[TX_GAIN_CTRL_INC_PIN_INDEX] = currentTxAttenCtrlIncPin; + sharedResourceArr[TX_GAIN_CTRL_DEC_PIN_INDEX] = currentTxAttenCtrlDecPin; + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + ADI_ADRV9025_NUM_GPIOS_IN_TX_ATTEN_CTRL_PIN_FEATURE, + THIS_FEATURE_ID, + &resourceReleaseStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to release GPIO shared resouce for GPIO attenuation Increment/Decrement Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceReleaseStatus, + "Error while attempting to release GPIO shared resouce for GPIO gain ctrl Increment/Decrement Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Set released GPIO pins as inputs since unused pins are supposed to be inputs*/ + incGpioPinMask = ((uint32_t)0x00000001 << (uint8_t)currentTxAttenCtrlIncPin); + decGpioPinMask = ((uint32_t)0x00000001 << (uint8_t)currentTxAttenCtrlDecPin); + recoveryAction = adi_adrv9025_GpioInputDirSet(device, + (incGpioPinMask | decGpioPinMask)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while attempting to set GPIO Increment/Decrement Pin inputs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (acquireNewPins != ADI_FALSE) + { +#if ADI_ADRV9025_TX_RANGE_CHECK > 0 + recoveryAction = adrv9025_TxAttenPinCtrlCfgSetRangeCheck(device, + &txAttenPinCfg); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + txAttenPinCfg, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /* Attempt to Acquire Gain Ctrl Increment GPIO pins */ + sharedResourceArr[TX_GAIN_CTRL_INC_PIN_INDEX] = (int32_t)txAttenPinCfg.txAttenIncPin; + sharedResourceArr[TX_GAIN_CTRL_DEC_PIN_INDEX] = (int32_t)txAttenPinCfg.txAttenDecPin; + recoveryAction = adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + ADI_ADRV9025_NUM_GPIOS_IN_TX_ATTEN_CTRL_PIN_FEATURE, + THIS_FEATURE_ID, + &resourceAcquisitionStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to acquire GPIO shared resouce for GPIO Attenaution Increment/Decrement Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceAcquisitionStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceAcquisitionStatus, + "Error while attempting to acquire GPIO shared resouce for GPIO Attenuation ctrl Increment/Decrement Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Set ADRV9025 GPIO Directions for Gain ctrl GPIO Increment and Decrement pins*/ + incGpioPinMask = ((uint32_t)0x00000001 << (uint8_t)txAttenPinCfg.txAttenIncPin); + decGpioPinMask = ((uint32_t)0x00000001 << (uint8_t)txAttenPinCfg.txAttenDecPin); + + if ((recoveryAction = adi_adrv9025_GpioInputDirSet(device, + (incGpioPinMask | decGpioPinMask))) != ADI_COMMON_ACT_NO_ACTION) + { + /*Clear the error so that clean up functions execute */ + recoveryAction = adi_common_ErrorClear(&device->common); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while clearing error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Release Shared GPIOs if setting of GPIO Output Dir is unsuccessful */ + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + ADI_ADRV9025_NUM_GPIOS_IN_TX_ATTEN_CTRL_PIN_FEATURE, + THIS_FEATURE_ID, + &resourceReleaseStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while releasing shared GPIO pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_ADRV9025_ERR_SHARED_RESOURCE_RELEASE, + ADI_ADRV9025_ACT_ERR_RESET_GPIO, + resourceReleaseStatus, + "Unable to release GPIOs for Tx attenuation pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_ADRV9025_ACT_ERR_RESET_SPI, + gpioAnalogInputOutputMask, + "Unable to set GPIOs input direction for Tx attenuation pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Configure GPIO Attenuation step size */ + recoveryAction = adrv9025_TxTxIncrDecrWordBfSet(device, + txChannelBaseAddr, + txAttenPinCfg.stepSize); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txAttenPinCfg.stepSize, + "Error while attempting to set GPIO Attenaution step size"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Tx attenuation Ctrl Decrement GPIO select */ + recoveryAction = adrv9025_TxTpcDecrAttenGpioSelectBfSet(device, + txChannelBaseAddr, + txAttenPinCfg.txAttenDecPin); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txAttenPinCfg, + "Error while attempting to set GPIO Tx attenuation decrement pin control"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Tx attenuation Ctrl Increment GPIO select*/ + recoveryAction = adrv9025_TxTpcIncrAttenGpioSelectBfSet(device, + txChannelBaseAddr, + txAttenPinCfg.txAttenIncPin); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txAttenPinCfg, + "Error while attempting to set GPIO Tx attenuation increment pin control"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_TxAttenUpdateGpioPinCtrlCfgSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_GpioPinSel_e gpioSelection) +{ + if ((gpioSelection != ADI_ADRV9025_GPIO_00) && (gpioSelection != ADI_ADRV9025_GPIO_01) && + (gpioSelection != ADI_ADRV9025_GPIO_02) && (gpioSelection != ADI_ADRV9025_GPIO_03) && + (gpioSelection != ADI_ADRV9025_GPIO_04) && (gpioSelection != ADI_ADRV9025_GPIO_05) && + (gpioSelection != ADI_ADRV9025_GPIO_06) && (gpioSelection != ADI_ADRV9025_GPIO_07) && + (gpioSelection != ADI_ADRV9025_GPIO_08) && (gpioSelection != ADI_ADRV9025_GPIO_09) && + (gpioSelection != ADI_ADRV9025_GPIO_10) && (gpioSelection != ADI_ADRV9025_GPIO_11) && + (gpioSelection != ADI_ADRV9025_GPIO_12) && (gpioSelection != ADI_ADRV9025_GPIO_13) && + (gpioSelection != ADI_ADRV9025_GPIO_14) && (gpioSelection != ADI_ADRV9025_GPIO_15)) + { + /* Gpio selection is not valid */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioSelection, + "Invalid GPIO selection, Valid range(GPIO_00-GPIO_15)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adrv9025_TxAttenUpdateGpioPinCtrlCfgSet(adi_adrv9025_Device_t* device, + adrv9025_BfTxChanAddr_e txChannelBaseAddr, + adi_adrv9025_GpioPinSel_e gpioSelection, + uint8_t releaseCurrentPin, + uint8_t acquireNewPin) +{ + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_TX_ATTEN_UPDATE_PIN; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t sharedResourceArr[ADI_ADRV9025_NUM_GPIOS_IN_TX_ATTEN_UPDATE_PIN_FEATURE] = {0}; + uint8_t resourceAcquisitionStatus = ADI_FAILURE; + uint8_t resourceReleaseStatus = ADI_FAILURE; + uint8_t currentTxAttenUpdatePin = 0; + uint32_t updateGpioPinMask = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if (releaseCurrentPin != ADI_FALSE) + { + /*Read Tx Attenuation Update PIN GPIO select */ + recoveryAction = adrv9025_TxTxAttenUpdGpioSelectBfGet(device, + txChannelBaseAddr, + ¤tTxAttenUpdatePin); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read Tx attenuation update GPIO selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Attempt to Release Attenuation Update GPIO since it is a shared resource. */ + sharedResourceArr[0] = (int32_t)currentTxAttenUpdatePin; + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + ADI_ADRV9025_NUM_GPIOS_IN_TX_ATTEN_UPDATE_PIN_FEATURE, + THIS_FEATURE_ID, + &resourceReleaseStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to release GPIO shared resource for Tx attenuation update Pin"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceReleaseStatus, + "Error while attempting to release GPIO shared resource for Tx attenuation update Pin"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Set released GPIO pins as inputs since unused pins are supposed to be inputs*/ + updateGpioPinMask = ((uint32_t)0x00000001 << currentTxAttenUpdatePin); + recoveryAction = adi_adrv9025_GpioInputDirSet(device, + updateGpioPinMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while attempting to set Tx attenuation update GPIO pin as input"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (acquireNewPin != ADI_FALSE) + { + recoveryAction = adrv9025_TxAttenUpdateGpioPinCtrlCfgSetRangeCheck(device, + gpioSelection); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Invalid GPIO selection. Valid values GPIO00-GPIO15"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Attempt to Acquire Tx attenuation update GPIO since it is a shared resource. */ + sharedResourceArr[0] = (int32_t)gpioSelection; + + recoveryAction = adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + ADI_ADRV9025_NUM_GPIOS_IN_TX_ATTEN_UPDATE_PIN_FEATURE, + THIS_FEATURE_ID, + &resourceAcquisitionStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to acquire GPIO shared resouce for Tx attenuation update GPIO pin"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceAcquisitionStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceAcquisitionStatus, + "Error while attempting to acquire GPIO shared resouce for Tx attenuation update GPIO pin"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Set ADRV9025 GPIO Direction for attenuation update pin*/ + updateGpioPinMask = ((uint32_t)0x00000001 << (uint8_t)gpioSelection); + + /* Set GPIO analog pins as output */ + if ((recoveryAction = adi_adrv9025_GpioInputDirSet(device, + updateGpioPinMask)) != ADI_COMMON_ACT_NO_ACTION) + { + /*Clear the error so that clean up functions execute */ + recoveryAction = adi_common_ErrorClear(&device->common); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while clearing error "); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Release Shared GPIOs if setting of GPIO Output Dir is unsuccessful */ + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + ADI_ADRV9025_NUM_GPIOS_IN_TX_ATTEN_UPDATE_PIN_FEATURE, + THIS_FEATURE_ID, + &resourceReleaseStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while releasing shared GPIO pins "); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_ADRV9025_ERR_SHARED_RESOURCE_RELEASE, + ADI_ADRV9025_ACT_ERR_RESET_GPIO, + resourceReleaseStatus, + "Unable to release GPIO for Tx attenuation pin"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_ADRV9025_ACT_ERR_RESET_SPI, + gpioAnalogInputOutputMask, + "Unable to set GPIO output direction for Tx attenuation pin"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Set Tx attenuation Update GPIO select */ + recoveryAction = adrv9025_TxTxAttenUpdGpioSelectBfSet(device, + txChannelBaseAddr, + (uint8_t)gpioSelection); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txAttenPinCfg, + "Error while attempting to set GPIO Tx attenuation update pin"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adrv9025_TxRampDownInit(adi_adrv9025_Device_t* device, + adi_adrv9025_TxRampDownInitCfg_t* txRampDownInitCfg) +{ + static const uint32_t TX_RAMPDOWN_ALL_MASK = 0x00FF; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxChanAddr_e baseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + uint32_t rampDownMask = TX_RAMPDOWN_ALL_MASK; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txRampDownInitCfg); + + if ((baseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + (uint32_t)txRampDownInitCfg->txChannel)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Mask All ramp down events by default */ + recoveryAction = adi_adrv9025_PaPllDfrmEventRampDownEnableSet(device, + (uint32_t)txRampDownInitCfg->txChannel, + rampDownMask, + ADI_FALSE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to set Tx ramp down masks during initialization"); + ADI_ERROR_RETURN(device->common.error.newAction); + + rampDownMask = 0; + if (ADRV9025_BF_EQUAL(txRampDownInitCfg->txRampDownEvents, + (uint32_t)ADI_ADRV9025_TX_RAMP_DOWN_AUTOSELECT)) + { + if (txRampDownInitCfg->txLoSel == ADI_ADRV9025_LOSEL_LO1) + { + rampDownMask |= ADI_ADRV9025_RAMP_DOWN_ON_RF1PLLUNLOCK; + } + else if (txRampDownInitCfg->txLoSel == ADI_ADRV9025_LOSEL_LO2) + { + rampDownMask |= ADI_ADRV9025_RAMP_DOWN_ON_RF2PLLUNLOCK; + } + + if (txRampDownInitCfg->deserializerLanesEnabledDfrm0 > 0) + { + rampDownMask |= ADI_ADRV9025_RAMP_DOWN_ON_DFRMIRQ0; + } + + if (txRampDownInitCfg->deserializerLanesEnabledDfrm1 > 0) + { + rampDownMask |= ADI_ADRV9025_RAMP_DOWN_ON_DFRMIRQ1; + } + + /* Unmask Serdes(if it's being used) and Clk Pll unlock events in auto mode */ + if (txRampDownInitCfg->serdesPllVcoFreq_kHz != 0) + { + rampDownMask |= ADI_ADRV9025_RAMP_DOWN_ON_SERDESPLLUNLOCK; + } + rampDownMask |= ADI_ADRV9025_RAMP_DOWN_ON_CLKPLLUNLOCK; + } + else + { + if (!(ADRV9025_BF_EQUAL(txRampDownInitCfg->txRampDownEvents, + (uint32_t)ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_DFRMIRQ0))) + { + rampDownMask |= ADI_ADRV9025_RAMP_DOWN_ON_DFRMIRQ0; + } + if (!(ADRV9025_BF_EQUAL(txRampDownInitCfg->txRampDownEvents, + (uint32_t)ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_DFRMIRQ1))) + { + rampDownMask |= ADI_ADRV9025_RAMP_DOWN_ON_DFRMIRQ1; + } + if (!(ADRV9025_BF_EQUAL(txRampDownInitCfg->txRampDownEvents, + (uint32_t)ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_RF1PLLUNLOCK))) + { + rampDownMask |= ADI_ADRV9025_RAMP_DOWN_ON_RF1PLLUNLOCK; + } + if (!(ADRV9025_BF_EQUAL(txRampDownInitCfg->txRampDownEvents, + (uint32_t)ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_RF2PLLUNLOCK))) + { + rampDownMask |= ADI_ADRV9025_RAMP_DOWN_ON_RF2PLLUNLOCK; + } + if (!(ADRV9025_BF_EQUAL(txRampDownInitCfg->txRampDownEvents, + (uint32_t)ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_SERDESPLLUNLOCK))) + { + rampDownMask |= ADI_ADRV9025_RAMP_DOWN_ON_SERDESPLLUNLOCK; + } + if (!(ADRV9025_BF_EQUAL(txRampDownInitCfg->txRampDownEvents, + (uint32_t)ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_CLKPLLUNLOCK))) + { + rampDownMask |= ADI_ADRV9025_RAMP_DOWN_ON_CLKPLLUNLOCK; + } + } + + if (rampDownMask != 0) + { + /* Unmask selected Tx power ramp down events */ + recoveryAction = adi_adrv9025_PaPllDfrmEventRampDownEnableSet(device, + (uint32_t)txRampDownInitCfg->txChannel, + rampDownMask, + ADI_TRUE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to set Tx ramp down masks during initialization"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Enable Tx ramp down on Pll unlock */ + recoveryAction = adrv9025_TxTxDataRampDownOnPllUnlockBfSet(device, + baseAddr, + ADI_TRUE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Error while setting ramp down enable on Pll Unlock Event bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Enable Tx ramp down on Jesd Irq */ + recoveryAction = adrv9025_TxTxDataRampDownOnJesdDfrmIrqBfSet(device, + baseAddr, + ADI_TRUE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Error while setting ramp down enable on Jesd Irq Event bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_utilities.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_utilities.c new file mode 100644 index 0000000..3ee9b68 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/private/src/adrv9025_utilities.c @@ -0,0 +1,4557 @@ +/** +* \file adrv9025_utilities.c +* \brief Contains Utility features related private function implementations +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "../include/adrv9025_utilities.h" +#include "adi_adrv9025_error.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_cpu.h" +#include "adi_adrv9025_rx.h" +#include "adi_adrv9025_tx.h" +#include "adi_adrv9025_radioctrl.h" +#include "adi_adrv9025_cals.h" +#include "adi_adrv9025_gpio.h" +#include "adi_adrv9025.h" + +static const char* objectNameExceededMsg = "Object name string exceeds the maximum allowed length of 48"; + +int32_t adrv9025_RadioctrlInit(adi_adrv9025_Device_t* device, + adi_adrv9025_RadioctrlInit_t* radioCtrlInit) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Sets up Radio Ctrl mode for Rx/ORx/Tx signal chains (SPI vs Pin mode) */ + recoveryAction = adi_adrv9025_RadioCtrlCfgSet(device, + &radioCtrlInit->radioCtrlModeCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set Frequency for LO1 PLL */ + if (radioCtrlInit->lo1PllFreq_Hz != 0) + { + recoveryAction = adi_adrv9025_PllFrequencySet(device, + ADI_ADRV9025_LO1_PLL, + radioCtrlInit->lo1PllFreq_Hz); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Set Frequency for LO2 PLL */ + if (radioCtrlInit->lo2PllFreq_Hz != 0) + { + recoveryAction = adi_adrv9025_PllFrequencySet(device, + ADI_ADRV9025_LO2_PLL, + radioCtrlInit->lo2PllFreq_Hz); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Set Frequency for Aux PLL */ + if (radioCtrlInit->auxPllFreq_Hz != 0) + { + recoveryAction = adi_adrv9025_PllFrequencySet(device, + ADI_ADRV9025_AUX_PLL, + radioCtrlInit->auxPllFreq_Hz); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Sets up Tx to ORx mapping. Required to run external LOL cals. Valid only in non-pin Mode */ + if (radioCtrlInit->txToOrxMapping.orx1Map == ADI_ADRV9025_MAP_NONE_ORX1) + { + recoveryAction = adi_adrv9025_TxToOrxMappingSet(device, + ADI_ADRV9025_ORX1, + ADI_ADRV9025_TXOFF); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (radioCtrlInit->txToOrxMapping.orx1Map == ADI_ADRV9025_MAP_TX1_ORX1) + { + recoveryAction = adi_adrv9025_TxToOrxMappingSet(device, + ADI_ADRV9025_ORX1, + ADI_ADRV9025_TX1); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (radioCtrlInit->txToOrxMapping.orx1Map == ADI_ADRV9025_MAP_TX2_ORX1) + { + recoveryAction = adi_adrv9025_TxToOrxMappingSet(device, + ADI_ADRV9025_ORX1, + ADI_ADRV9025_TX2); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + radioCtrlInit->txToOrxMapping.orx1Map, + "Invalid Tx-ORx1 map encountered in post mcs init. Valid map values are MAP_TX1,MAP_Tx2 and MAP_NONE"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (radioCtrlInit->txToOrxMapping.orx2Map == ADI_ADRV9025_MAP_NONE_ORX2) + { + recoveryAction = adi_adrv9025_TxToOrxMappingSet(device, + ADI_ADRV9025_ORX2, + ADI_ADRV9025_TXOFF); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (radioCtrlInit->txToOrxMapping.orx2Map == ADI_ADRV9025_MAP_TX1_ORX2) + { + recoveryAction = adi_adrv9025_TxToOrxMappingSet(device, + ADI_ADRV9025_ORX2, + ADI_ADRV9025_TX1); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (radioCtrlInit->txToOrxMapping.orx2Map == ADI_ADRV9025_MAP_TX2_ORX2) + { + recoveryAction = adi_adrv9025_TxToOrxMappingSet(device, + ADI_ADRV9025_ORX2, + ADI_ADRV9025_TX2); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + radioCtrlInit->txToOrxMapping.orx1Map, + "Invalid Tx-ORx2 map encountered in post mcs init. Valid map values are MAP_TX1,MAP_Tx2 and MAP_NONE"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (radioCtrlInit->txToOrxMapping.orx3Map == ADI_ADRV9025_MAP_NONE_ORX3) + { + recoveryAction = adi_adrv9025_TxToOrxMappingSet(device, + ADI_ADRV9025_ORX3, + ADI_ADRV9025_TXOFF); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (radioCtrlInit->txToOrxMapping.orx3Map == ADI_ADRV9025_MAP_TX3_ORX3) + { + recoveryAction = adi_adrv9025_TxToOrxMappingSet(device, + ADI_ADRV9025_ORX3, + ADI_ADRV9025_TX3); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (radioCtrlInit->txToOrxMapping.orx3Map == ADI_ADRV9025_MAP_TX4_ORX3) + { + recoveryAction = adi_adrv9025_TxToOrxMappingSet(device, + ADI_ADRV9025_ORX3, + ADI_ADRV9025_TX4); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + radioCtrlInit->txToOrxMapping.orx1Map, + "Invalid Tx-ORx3 map encountered in post mcs init. Valid map values are MAP_TX3,MAP_Tx4 and MAP_NONE"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (radioCtrlInit->txToOrxMapping.orx4Map == ADI_ADRV9025_MAP_NONE_ORX4) + { + recoveryAction = adi_adrv9025_TxToOrxMappingSet(device, + ADI_ADRV9025_ORX4, + ADI_ADRV9025_TXOFF); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (radioCtrlInit->txToOrxMapping.orx4Map == ADI_ADRV9025_MAP_TX3_ORX4) + { + recoveryAction = adi_adrv9025_TxToOrxMappingSet(device, + ADI_ADRV9025_ORX4, + ADI_ADRV9025_TX3); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (radioCtrlInit->txToOrxMapping.orx4Map == ADI_ADRV9025_MAP_TX4_ORX4) + { + recoveryAction = adi_adrv9025_TxToOrxMappingSet(device, + ADI_ADRV9025_ORX4, + ADI_ADRV9025_TX4); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + radioCtrlInit->txToOrxMapping.orx1Map, + "Invalid Tx-ORx4 map encountered in post mcs init. Valid map values are MAP_TX3,MAP_TX4 and MAP_NONE"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Sets up the GPIO pin mapping to the 4 stream trigger inputs to ADRV9025 */ + recoveryAction = adi_adrv9025_StreamGpioConfigSet(device, + &radioCtrlInit->streamGpioCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_CalsInit(adi_adrv9025_Device_t* device, + adi_adrv9025_InitCals_t* initCals) +{ + //TODO : Minimize timeout after lab eval + static const uint32_t INIT_CALS_TIMEOUT_MS = 60000; /*60 seconds timeout*/ + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t initCalsError = 0; + + /* Run Init Cals */ + recoveryAction = adi_adrv9025_InitCalsRun(device, + initCals); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_adrv9025_InitCalsWait(device, + INIT_CALS_TIMEOUT_MS, + &initCalsError); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_DdcMultDivGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxDdc_e rxDdcMode, + uint8_t* ddcMultiply, + uint8_t* ddcDivide) +{ + switch (rxDdcMode) + { + case ADI_ADRV9025_RXDDC_BYPASS_REALIF: + case ADI_ADRV9025_RXDDC_BYPASS: + *ddcMultiply = 1; + *ddcDivide = 1; + break; + case ADI_ADRV9025_RXDDC_DEC2_REALIF: + case ADI_ADRV9025_RXDDC_DEC2: + *ddcMultiply = 2; + *ddcDivide = 1; + break; + case ADI_ADRV9025_RXDDC_INT2_REALIF: + case ADI_ADRV9025_RXDDC_INT2: + *ddcMultiply = 1; + *ddcDivide = 2; + break; + case ADI_ADRV9025_RXDDC_FILTERONLY_REALIF: + case ADI_ADRV9025_RXDDC_FILTERONLY: + *ddcMultiply = 1; + *ddcDivide = 1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxProfile, + "Rx Profile DDC mode is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adrv9025_AdcProfilesInit(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init, + adi_adrv9025_AdcProfiles_t* adcProfile) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t ddcMultiply = 1; + uint8_t ddcDivide = 1; + uint8_t i = 0; + uint8_t j = 0; + uint32_t adcClk_MHz = 0; + uint8_t profileIndex = 0; + uint32_t maskBit = 0; + adi_adrv9025_RxProfile_t* rxProfile = NULL; + adi_adrv9025_RxProfile_t* orxProfile = NULL; + uint32_t rxMaskArray[ADI_ADRV9025_MAX_RXCHANNELS] = { + ADI_ADRV9025_RX1, + ADI_ADRV9025_RX2, + ADI_ADRV9025_RX3, + ADI_ADRV9025_RX4, + ADI_ADRV9025_ORX1, + ADI_ADRV9025_ORX2, + ADI_ADRV9025_ORX3, + ADI_ADRV9025_ORX4, + ADI_ADRV9025_LB12, + ADI_ADRV9025_LB34 + }; + + const uint8_t NUM_ADC_PROFILES = 26; + uint8_t numAdcProfilesCoef = 41; + static const uint16_t adcProfileLutIndex[26][2] = + { + {20, 1228}, + {30, 1228}, + {37, 1474}, + {10, 1966}, + {50, 1966}, + {60, 1966}, + {100, 1966}, + {50, 2457}, + {62, 2457}, + {50, 2949}, + {75, 2949}, + {62, 3072}, + {70, 3072}, + {140, 3072}, + {75, 3686}, + {84, 3686}, + {150, 3686}, + {168, 3686}, + {100, 3932}, + {225, 3932}, + {100, 4915}, + {112, 4915}, + {140, 4915}, + {225, 4915}, + {101, 5000}, + {228, 5000} + }; + + static const uint16_t adcProfileLut[26 * 41] = + { + 386, 273, 500, 154, 7, 1185, 619, 116, 12, 197, 132, 1, 10, 48, 0, 0, 32, 0, 0, 0, 12, 128, 3, 0, 15, 5, 0, 0, 3, 0, 13, 2, 0, 0, 14, 14, 0, 14, 0, 12, 0, + 386, 273, 506, 153, 15, 1182, 617, 116, 12, 198, 132, 1, 10, 48, 0, 0, 32, 0, 0, 0, 12, 128, 3, 0, 15, 5, 0, 0, 3, 0, 13, 2, 0, 0, 14, 14, 0, 14, 0, 12, 0, + 386, 273, 507, 192, 16, 984, 513, 121, 15, 206, 132, 1, 10, 48, 0, 0, 32, 0, 0, 0, 12, 128, 3, 0, 15, 5, 0, 0, 3, 0, 13, 2, 0, 0, 14, 14, 0, 14, 0, 12, 0, + 386, 273, 500, 256, 7, 739, 386, 120, 20, 205, 132, 1, 10, 48, 0, 0, 32, 0, 0, 0, 12, 128, 3, 0, 15, 5, 0, 0, 3, 0, 13, 2, 0, 0, 14, 14, 0, 14, 0, 12, 0, + 386, 273, 508, 255, 16, 738, 385, 121, 20, 206, 132, 1, 10, 48, 0, 0, 32, 0, 0, 0, 12, 128, 3, 7, 15, 5, 0, 0, 3, 7, 13, 2, 0, 0, 14, 14, 0, 14, 0, 12, 0, + 386, 273, 511, 255, 20, 737, 384, 122, 20, 206, 132, 1, 10, 48, 0, 0, 32, 0, 0, 0, 12, 128, 3, 7, 15, 5, 0, 0, 3, 7, 13, 2, 0, 0, 14, 14, 0, 14, 0, 12, 0, + 386, 273, 542, 240, 57, 730, 380, 120, 19, 199, 132, 1, 10, 48, 0, 0, 32, 0, 0, 0, 12, 128, 3, 7, 15, 5, 0, 0, 3, 7, 13, 2, 0, 0, 14, 14, 0, 14, 0, 12, 0, + 386, 273, 503, 320, 10, 590, 308, 121, 25, 211, 132, 1, 10, 48, 0, 0, 32, 0, 0, 0, 13, 128, 7, 7, 0, 5, 0, 7, 7, 7, 7, 7, 0, 7, 13, 13, 0, 13, 0, 12, 0, + 386, 273, 508, 319, 16, 590, 307, 121, 25, 211, 132, 1, 10, 48, 0, 0, 32, 0, 0, 0, 13, 128, 7, 7, 0, 5, 0, 7, 7, 7, 7, 7, 0, 7, 13, 13, 0, 13, 0, 12, 0, + 386, 273, 501, 384, 7, 492, 256, 120, 30, 210, 132, 1, 10, 48, 0, 0, 32, 0, 0, 0, 13, 128, 7, 7, 0, 5, 0, 7, 7, 7, 7, 7, 0, 7, 13, 13, 0, 13, 0, 12, 0, + 386, 273, 509, 383, 16, 491, 256, 121, 30, 211, 132, 1, 10, 48, 0, 0, 32, 0, 0, 0, 13, 128, 7, 7, 0, 5, 0, 7, 7, 7, 7, 7, 0, 7, 13, 13, 0, 13, 0, 12, 0, + 386, 273, 504, 396, 10, 472, 246, 120, 31, 204, 132, 1, 10, 32, 0, 0, 24, 0, 0, 0, 14, 128, 7, 7, 15, 5, 0, 7, 7, 7, 13, 2, 0, 7, 14, 14, 0, 14, 0, 12, 0, + 386, 273, 506, 396, 13, 471, 246, 120, 31, 204, 132, 1, 10, 32, 0, 0, 24, 0, 0, 0, 14, 128, 7, 7, 15, 5, 0, 7, 7, 7, 13, 2, 0, 7, 14, 14, 0, 14, 0, 12, 0, + 386, 273, 535, 381, 46, 467, 244, 120, 30, 200, 132, 1, 10, 32, 0, 0, 24, 0, 0, 0, 14, 128, 7, 7, 15, 5, 0, 7, 7, 7, 13, 2, 0, 7, 14, 14, 0, 14, 0, 12, 0, + 386, 273, 504, 486, 10, 393, 204, 122, 38, 208, 132, 1, 10, 32, 0, 0, 24, 0, 0, 0, 14, 128, 7, 7, 15, 5, 0, 7, 7, 7, 13, 2, 0, 7, 14, 14, 0, 14, 0, 12, 0, + 386, 273, 506, 486, 13, 392, 204, 123, 38, 209, 132, 1, 10, 32, 0, 0, 24, 0, 0, 0, 14, 128, 7, 7, 15, 5, 0, 7, 7, 7, 13, 2, 0, 7, 14, 14, 0, 14, 0, 12, 0, + 386, 273, 528, 470, 36, 390, 204, 122, 37, 205, 132, 1, 10, 32, 0, 0, 24, 0, 0, 0, 14, 128, 7, 7, 15, 5, 0, 7, 7, 7, 13, 2, 0, 7, 14, 14, 0, 14, 0, 12, 0, + 386, 273, 537, 469, 46, 389, 204, 123, 37, 206, 132, 1, 10, 32, 0, 0, 24, 0, 0, 0, 14, 128, 7, 7, 15, 5, 0, 7, 7, 7, 13, 2, 0, 7, 14, 14, 0, 14, 0, 12, 0, + 386, 273, 510, 511, 16, 367, 191, 121, 40, 206, 132, 1, 10, 32, 0, 0, 24, 0, 0, 0, 14, 128, 7, 7, 15, 5, 0, 7, 7, 7, 13, 2, 0, 7, 14, 14, 0, 14, 0, 12, 0, + 386, 273, 564, 479, 74, 362, 191, 121, 38, 200, 132, 1, 10, 32, 0, 0, 24, 0, 0, 0, 14, 128, 7, 7, 15, 5, 0, 7, 7, 7, 13, 2, 0, 7, 14, 14, 0, 14, 0, 12, 0, + 386, 273, 505, 512, 10, 294, 153, 96, 40, 148, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, + 386, 273, 507, 511, 13, 294, 153, 96, 40, 148, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, + 386, 273, 512, 511, 18, 293, 153, 97, 40, 149, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, + 386, 273, 541, 507, 47, 291, 153, 99, 40, 150, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, + 386, 273, 505, 512, 10, 289, 150, 94, 40, 146, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0, + 386, 273, 541, 507, 47, 286, 150, 98, 40, 148, 132, 1, 10, 16, 0, 0, 16, 0, 0, 0, 0, 128, 7, 7, 0, 5, 0, 7, 7, 7, 1, 2, 0, 7, 4, 0, 0, 4, 0, 12, 0 + }; + + if (device->devStateInfo.profilesValid & ADI_ADRV9025_RX_PROFILE_VALID) + { + for (i = 0; i < ADI_ADRV9025_MAX_RX_ONLY; i++) + { + maskBit = rxMaskArray[i]; + if ((device->devStateInfo.initializedChannels & maskBit) == maskBit) + { + rxProfile = &init->rx.rxChannelCfg[i].profile; + recoveryAction = adrv9025_DdcMultDivGet(device, + rxProfile->rxDdcMode, + &ddcMultiply, + &ddcDivide); + ADI_ERROR_RETURN(device->common.error.newAction); + + adcClk_MHz = (rxProfile->rxOutputRate_kHz * rxProfile->rxFirDecimation * + rxProfile->rxFir1Decimation * rxProfile->rxFir2Decimation * + rxProfile->rhb1Decimation * rxProfile->rhb2Decimation * rxProfile->rhb3Decimation * + rxProfile->rxDec5Decimation * ddcMultiply / ddcDivide) / 1000; + + /* find correct ADC profile in the LUT */ + profileIndex = NUM_ADC_PROFILES; + for (j = 0; j < NUM_ADC_PROFILES; j++) + { + /* Find a row in the LUT that matches the ADC clock frequency */ + if ((adcProfileLutIndex[j][1] == adcClk_MHz) && (adcProfileLutIndex[j][0] >= (rxProfile->rxAdcBandWidth_kHz / 1000))) + { + profileIndex = j; + break; + } + } + + /* Verify that a profile was found in the LUT, if not return error */ + if (profileIndex >= NUM_ADC_PROFILES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + profileIndex, + "Invalid Rx profileIndex in adrv9025_AdcProfilesLoad"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (maskBit == ADI_ADRV9025_RX1) + { + for (j = 0; j < numAdcProfilesCoef; j++) + { + adcProfile->RxChannel1[j] = adcProfileLut[profileIndex * numAdcProfilesCoef + j]; + } + } + else if (maskBit == ADI_ADRV9025_RX2) + { + for (j = 0; j < numAdcProfilesCoef; j++) + { + adcProfile->RxChannel2[j] = adcProfileLut[profileIndex * numAdcProfilesCoef + j]; + } + } + else if (maskBit == ADI_ADRV9025_RX3) + { + for (j = 0; j < numAdcProfilesCoef; j++) + { + adcProfile->RxChannel3[j] = adcProfileLut[profileIndex * numAdcProfilesCoef + j]; + } + } + else if (maskBit == ADI_ADRV9025_RX4) + { + for (j = 0; j < numAdcProfilesCoef; j++) + { + adcProfile->RxChannel4[j] = adcProfileLut[profileIndex * numAdcProfilesCoef + j]; + } + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + profileIndex, + "Invalid Rx channel in adrv9025_AdcProfilesLoad"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + } + + if (device->devStateInfo.profilesValid & ADI_ADRV9025_ORX_PROFILE_VALID) + { + adcProfile->OrxChannel1Index = 0; + adcProfile->OrxChannel2Index = 0; + + for (i = ADI_ADRV9025_MAX_RX_ONLY; i < ADI_ADRV9025_MAX_LB_CHANNEL_START; i++) + { + maskBit = rxMaskArray[i]; + if ((device->devStateInfo.initializedChannels & maskBit) == maskBit) + { + orxProfile = &init->rx.rxChannelCfg[i].profile; + recoveryAction = adrv9025_DdcMultDivGet(device, + orxProfile->rxDdcMode, + &ddcMultiply, + &ddcDivide); + ADI_ERROR_RETURN(device->common.error.newAction); + + adcClk_MHz = (orxProfile->rxOutputRate_kHz * orxProfile->rxFirDecimation * + orxProfile->rxFir1Decimation * + orxProfile->rhb1Decimation * orxProfile->rhb2Decimation * orxProfile->rhb3Decimation * + orxProfile->rxDec5Decimation * ddcMultiply / ddcDivide) / 1000; + + /* find correct ADC profile in the LUT */ + profileIndex = NUM_ADC_PROFILES; + for (j = 0; j < NUM_ADC_PROFILES; j++) + { + /* Find a row in the LUT that matches the ADC clock frequency */ + if ((adcProfileLutIndex[j][1] == adcClk_MHz) && (adcProfileLutIndex[j][0] >= (orxProfile->rxAdcBandWidth_kHz / 1000))) + { + profileIndex = j; + break; + } + } + + /* Verify that a profile was found in the LUT, if not return error */ + if (profileIndex >= NUM_ADC_PROFILES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + profileIndex, + "Invalid Orx profileIndex in adrv9025_AdcProfilesLoad"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (maskBit == ADI_ADRV9025_ORX1) + { + for (j = 0; j < numAdcProfilesCoef; j++) + { + adcProfile->OrxChannel1Profile0[j] = adcProfileLut[profileIndex * numAdcProfilesCoef + j]; + } + } + else if (maskBit == ADI_ADRV9025_ORX2) + { + for (j = 0; j < numAdcProfilesCoef; j++) + { + adcProfile->OrxChannel1Profile1[j] = adcProfileLut[profileIndex * numAdcProfilesCoef + j]; + } + } + else if (maskBit == ADI_ADRV9025_ORX3) + { + for (j = 0; j < numAdcProfilesCoef; j++) + { + adcProfile->OrxChannel2Profile0[j] = adcProfileLut[profileIndex * numAdcProfilesCoef + j]; + } + } + else if (maskBit == ADI_ADRV9025_ORX4) + { + for (j = 0; j < numAdcProfilesCoef; j++) + { + adcProfile->OrxChannel2Profile1[j] = adcProfileLut[profileIndex * numAdcProfilesCoef + j]; + } + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + profileIndex, + "Invalid ORx ADC Profile channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + } + + if (device->devStateInfo.profilesValid & ADI_ADRV9025_TX_PROFILE_VALID) + { + for (i = ADI_ADRV9025_MAX_LB_CHANNEL_START; i <= ADI_ADRV9025_MAX_LB_CHANNEL_END; i++) + { + maskBit = rxMaskArray[i]; + if ((device->devStateInfo.initializedChannels & maskBit) == maskBit) + { + orxProfile = &init->rx.rxChannelCfg[i].profile; + recoveryAction = adrv9025_DdcMultDivGet(device, + orxProfile->rxDdcMode, + &ddcMultiply, + &ddcDivide); + ADI_ERROR_RETURN(device->common.error.newAction); + + adcClk_MHz = (orxProfile->rxOutputRate_kHz * orxProfile->rxFirDecimation * + orxProfile->rxFir1Decimation * + orxProfile->rhb1Decimation * orxProfile->rhb2Decimation * orxProfile->rhb3Decimation * + orxProfile->rxDec5Decimation * ddcMultiply / ddcDivide) / 1000; + + /* find correct ADC profile in the LUT */ + profileIndex = NUM_ADC_PROFILES; + for (j = 0; j < NUM_ADC_PROFILES; j++) + { + /* Find a row in the LUT that matches the ADC clock frequency */ + if ((adcProfileLutIndex[j][1] == adcClk_MHz) && (adcProfileLutIndex[j][0] >= (orxProfile->rxAdcBandWidth_kHz / 1000))) + { + profileIndex = j; + break; + } + } + + /* Verify that a profile was found in the LUT, if not return error */ + if (profileIndex >= NUM_ADC_PROFILES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + profileIndex, + "Invalid Loopback ADC profileIndex "); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (maskBit == ADI_ADRV9025_LB12) + { + for (j = 0; j < numAdcProfilesCoef; j++) + { + adcProfile->OrxChannel1Profile2[j] = adcProfileLut[profileIndex * numAdcProfilesCoef + j]; + adcProfile->OrxChannel1Profile3[j] = adcProfileLut[profileIndex * numAdcProfilesCoef + j]; + } + } + else if (maskBit == ADI_ADRV9025_LB34) + { + for (j = 0; j < numAdcProfilesCoef; j++) + { + adcProfile->OrxChannel2Profile2[j] = adcProfileLut[profileIndex * numAdcProfilesCoef + j]; + adcProfile->OrxChannel2Profile3[j] = adcProfileLut[profileIndex * numAdcProfilesCoef + j]; + } + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + profileIndex, + "Invalid Loopback ADC Profile channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + } + + return recoveryAction; +} + +static void RemoveWhiteSpace(char* strUntrimmed) +{ + char* strTrimmed = strUntrimmed; + + while (*strUntrimmed != '\0') + { + if (!isspace(*strUntrimmed)) + { + *strTrimmed = *strUntrimmed; + strTrimmed++; + } + + strUntrimmed++; + } + + /* Null terminate the trimmed character array */ + *strTrimmed = '\0'; +} + +int32_t adrv9025_JsonFindStartOfFile(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar) +{ + char* fileRead = NULL; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + objNameStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + + if (fileRead != NULL) + { + RemoveWhiteSpace(fullStr); + if (strstr(&fullStr[*currChar], + "{") == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fullStr, + "Could not find the start of JSON file"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_JsonFindEndOfFile(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar) +{ + char* fileRead = NULL; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + objNameStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (strstr(&fullStr[*currChar], + "}") == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fullStr, + "Could not find the end of JSON file"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_JsonFindStartOfObject(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar) +{ + char* fileRead = NULL; + char matchStr[53] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + objNameStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + /* going to be adding 5 additional characters to the string to be searched + * including the null terminator */ + if (strlen(objNameStr) + 5 > sizeof(matchStr)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + objectNameExceededMsg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + strncat(matchStr, + "\"", + 2); + strncat(matchStr, + objNameStr, + strlen(objNameStr)); + strncat(matchStr, + "\":{", + 4); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (strstr(&fullStr[*currChar], + matchStr) == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + "Could not find JSON object"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_JsonFindEndOfObject(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar) +{ + char* fileRead = NULL; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + objNameStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (strstr(&fullStr[*currChar], + "}") == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + "Could not find end of JSON object"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_JsonFindStartOfArray(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar) +{ + char* fileRead = NULL; + char matchStr[53] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + objNameStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + /* going to be adding 5 additional characters to the string to be searched + * including the null terminator */ + if (strlen(objNameStr) + 5 > sizeof(matchStr)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + objectNameExceededMsg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + strncat(matchStr, + "\"", + 2); + strncat(matchStr, + objNameStr, + strlen(objNameStr)); + strncat(matchStr, + "\":[", + 4); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (strstr(&fullStr[*currChar], + matchStr) == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + "Could not find end of JSON array"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_JsonFindEndOfArray(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar) +{ + char* fileRead = NULL; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + objNameStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (strstr(&fullStr[*currChar], + "]") == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + "Could not find end of JSON array"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_JsonFindOpenCurlBrace(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar) +{ + char* fileRead = NULL; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (strstr(&fullStr[*currChar], + "{") == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + "Could not find the open curled brace"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_JsonFindClosedCurlBrace(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar) +{ + char* fileRead = NULL; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (strstr(&fullStr[*currChar], + "}") == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + "Could not find closed curled brace"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_JsonPeekNextKeyword(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* keyword) +{ + char* fileRead = NULL; + int32_t matched = 0; + long fileMarker = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + ADI_NULL_PTR_RETURN(&device->common, + fp); + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + ADI_NULL_PTR_RETURN(&device->common, + keyword); + + fileMarker = ftell(fp); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (strstr(fullStr, + keyword)) + { + matched = 1; + } + /* reset the file marker back to where it was */ + fseek(fp, + fileMarker, + SEEK_SET); + } + + return (matched); +} +int32_t adrv9025_JsonParseU64(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar, + uint64_t* value) +{ + char* fileRead = NULL; + char matchStr[48] = {0}; + uint64_t val = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + objNameStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + ADI_NULL_PTR_RETURN(&device->common, + value); + + if (strlen(objNameStr) > sizeof(matchStr)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + "Object name string exceeds the maximum allowed length of 48"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + strcat(matchStr, + "\""); + strcat(matchStr, + objNameStr); + strcat(matchStr, + "\":%llu"); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (sscanf(&fullStr[*currChar], + matchStr, + &val) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + "Could not parse UInt64 value of the object"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + *value = val; + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} +int32_t adrv9025_JsonParseCalRsltFileStr(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + int32_t* currChar) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + fgets(fullStr, ADRV9025_MAX_FILE_BUFFER, fp); + RemoveWhiteSpace(fullStr); + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_JsonParseI32(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar, + int32_t* value) +{ + char* fileRead = NULL; + char matchStr[54] = {0}; + int32_t val = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + objNameStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + ADI_NULL_PTR_RETURN(&device->common, + value); + + /* going to be adding 6 additional characters to the string to be searched + * including the null terminator */ + if (strlen(objNameStr) + 6 > sizeof(matchStr)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + objectNameExceededMsg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + strncat(matchStr, + "\"", + 2); + strncat(matchStr, + objNameStr, + strlen(objNameStr)); + strncat(matchStr, + "\":%d", + 5); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (sscanf(&fullStr[*currChar], + matchStr, + &val) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + "Could not parse Int32 value of the object"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + *value = val; + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_JsonParseU32(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar, + uint32_t* value) +{ + char* fileRead = NULL; + char matchStr[54] = {0}; + uint32_t val = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + objNameStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + ADI_NULL_PTR_RETURN(&device->common, + value); + + /* going to be adding 6 additional characters to the string to be searched + * including the null terminator */ + if (strlen(objNameStr) + 6 > sizeof(matchStr)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + objectNameExceededMsg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + strncat(matchStr, + "\"", + 2); + strncat(matchStr, + objNameStr, + strlen(objNameStr)); + strncat(matchStr, + "\":%u", + 5); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (sscanf(&fullStr[*currChar], + matchStr, + &val) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + "Could not parse UInt32 value of the object"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + *value = val; + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_JsonParseU16(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar, + uint16_t* value) +{ + char* fileRead = NULL; + char matchStr[55] = {0}; + uint16_t val = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + objNameStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + ADI_NULL_PTR_RETURN(&device->common, + value); + + /* going to be adding 7 additional characters to the string to be searched + * including the null terminator */ + if (strlen(objNameStr) + 7 > sizeof(matchStr)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + objectNameExceededMsg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + strncat(matchStr, + "\"", + 2); + strncat(matchStr, + objNameStr, + strlen(objNameStr)); + strncat(matchStr, + "\":%hu", + 6); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (sscanf(&fullStr[*currChar], + matchStr, + &val) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + "Could not parse UInt16 value of the object"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + *value = val; + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_JsonParseU8(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar, + uint8_t* value) +{ + char* fileRead = NULL; + char matchStr[56] = {0}; + uint8_t val = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + objNameStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + ADI_NULL_PTR_RETURN(&device->common, + value); + + /* going to be adding 8 additional characters to the string to be searched + * including the null terminator */ + if (strlen(objNameStr) + 8 > sizeof(matchStr)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + objectNameExceededMsg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + strncat(matchStr, + "\"", + 2); + strncat(matchStr, + objNameStr, + strlen(objNameStr)); + strncat(matchStr, + "\":%hhu", + 7); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (sscanf(&fullStr[*currChar], + matchStr, + &val) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + "Could not parse UInt8 value of the object"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + *value = val; + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_JsonParseI8(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar, + int8_t* value) +{ + char* fileRead = NULL; + char matchStr[56] = { 0 }; + int8_t val = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + objNameStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + ADI_NULL_PTR_RETURN(&device->common, + value); + + /* going to be adding 8 additional characters to the string to be searched + * including the null terminator */ + if (strlen(objNameStr) + 8 > sizeof(matchStr)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + objectNameExceededMsg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + strncat(matchStr, + "\"", + 2); + strncat(matchStr, + objNameStr, + strlen(objNameStr)); + strncat(matchStr, + "\":%hhd", + 7); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (sscanf(&fullStr[*currChar], + matchStr, + &val) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + "Could not parse Int8 value of the object"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + *value = val; + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_JsonParseUI8(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + const char* objNameStr, + int32_t* currChar, + uint8_t* value) +{ + char* fileRead = NULL; + char matchStr[56] = { 0 }; + int8_t val = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + objNameStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + ADI_NULL_PTR_RETURN(&device->common, + value); + + /* going to be adding 8 additional characters to the string to be searched + * including the null terminator */ + if (strlen(objNameStr) + 8 > sizeof(matchStr)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + objectNameExceededMsg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + strncat(matchStr, + "\"", + 2); + strncat(matchStr, + objNameStr, + strlen(objNameStr)); + strncat(matchStr, + "\":%hhd", + 7); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (sscanf(&fullStr[*currChar], + matchStr, + &val) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + "Could not parse Uint8 value of the object"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + *value = val; + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_JsonParseArrayElementI16(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + int* currChar, + int16_t* value) +{ + char* fileRead = NULL; + int16_t val = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + ADI_NULL_PTR_RETURN(&device->common, + value); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (sscanf(&fullStr[*currChar], + "%hd", + &val) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + "Could not parse Int16 array element value of the object"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + *value = val; + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} +uint32_t adrv9025_JsonParseArrayElementU16(adi_adrv9025_Device_t* device, + FILE* fp, + char* fullStr, + int* currChar, + uint16_t* value) +{ + char* fileRead = NULL; + uint16_t val = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + fullStr); + + ADI_NULL_PTR_RETURN(&device->common, + currChar); + + ADI_NULL_PTR_RETURN(&device->common, + value); + + fileRead = fgets(fullStr, + ADRV9025_MAX_FILE_BUFFER, + fp); + RemoveWhiteSpace(fullStr); + + if (fileRead != NULL) + { + if (sscanf(&fullStr[*currChar], + "%hd", + &val) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + objNameStr, + "Could not parse UInt16 array element value of the object"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + *value = val; + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t adrv9025_JsonParseInitSpiSettings(adi_adrv9025_Device_t* device, + adi_adrv9025_SpiSettings_t* spiSettings, + FILE* fp) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t currChar = 0; + char lineStr[ADRV9025_MAX_FILE_BUFFER + 1] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + spiSettings); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "spiSettings", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "msbFirst", + &currChar, + &spiSettings->msbFirst); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "enSpiStreaming", + &currChar, + &spiSettings->enSpiStreaming); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "autoIncAddrUp", + &currChar, + &spiSettings->autoIncAddrUp); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "fourWireMode", + &currChar, + &spiSettings->fourWireMode); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "cmosPadDrvStrength", + &currChar, + (uint32_t*)&spiSettings->cmosPadDrvStrength); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "spiSettings", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_JsonParseInitClockSettings(adi_adrv9025_Device_t* device, + adi_adrv9025_ClockSettings_t* clockSettings, + FILE* fp) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t currChar = 0; + char lineStr[ADRV9025_MAX_FILE_BUFFER + 1] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + clockSettings); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "clocks", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "deviceClock_kHz", + &currChar, + &clockSettings->deviceClock_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "clkPllVcoFreq_kHz", + &currChar, + &clockSettings->clkPllVcoFreq_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "serdesPllVcoFreq_kHz", + &currChar, + &clockSettings->serdesPllVcoFreq_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "ldoSelect", + &currChar, + &clockSettings->ldoSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "extLoFreq1_kHz", + &currChar, + &clockSettings->extLoFreq1_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "extLoFreq2_kHz", + &currChar, + &clockSettings->extLoFreq2_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rfPll1LoMode", + &currChar, + (uint32_t*)&clockSettings->rfPll1LoMode); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rfPll2LoMode", + &currChar, + (uint32_t*)&clockSettings->rfPll2LoMode); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "rfPll1LoOutDivider", + &currChar, + &clockSettings->rfPll1LoOutDivider); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "rfPll2LoOutDivider", + &currChar, + &clockSettings->rfPll2LoOutDivider); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rfPllPhaseSyncMode", + &currChar, + (uint32_t*)&clockSettings->rfPllPhaseSyncMode); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rx12LoSelect", + &currChar, + (uint32_t*)&clockSettings->rx12LoSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rx34LoSelect", + &currChar, + (uint32_t*)&clockSettings->rx34LoSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "tx12LoSelect", + &currChar, + (uint32_t*)&clockSettings->tx12LoSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "tx34LoSelect", + &currChar, + (uint32_t*)&clockSettings->tx34LoSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "orx12LoSelect", + &currChar, + (uint32_t*)&clockSettings->orx12LoSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "orx34LoSelect", + &currChar, + (uint32_t*)&clockSettings->orx34LoSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "clocks", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_JsonParseInitRxSettings(adi_adrv9025_Device_t* device, + adi_adrv9025_RxSettings_t* rxSettings, + FILE* fp) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t currChar = 0; + char lineStr[ADRV9025_MAX_FILE_BUFFER + 1] = {0}; + uint32_t i = 0; + uint32_t j = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + rxSettings); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "rx", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rxInitChannelMask", + &currChar, + &rxSettings->rxInitChannelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "rxChannelCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_ADRV9025_MAX_RXCHANNELS; i++) + { + recoveryAction = adrv9025_JsonFindOpenCurlBrace(device, + fp, + &lineStr[0], + NULL, + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "profile", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "channelType", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.channelType); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "rxFirDecimation", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxFirDecimation); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "rxDec5Decimation", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxDec5Decimation); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "rhb1Decimation", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rhb1Decimation); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "rhb1WideBandMode", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rhb1WideBandMode); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "rhb2Decimation", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rhb2Decimation); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "rhb3Decimation", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rhb3Decimation); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "rxFir1Decimation", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxFir1Decimation); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "rxFir2Decimation", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxFir2Decimation); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rxOutputRate_kHz", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxOutputRate_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rfBandwidth_kHz", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rfBandwidth_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rxBbf3dBCorner_kHz", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxBbf3dBCorner_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rxAdcBandWidth_kHz", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxAdcBandWidth_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "rxFir", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseI8(device, + fp, + &lineStr[0], + "gain_dB", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxFir.gain_dB); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "numFirCoefs", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxFir.numFirCoefs); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Find Start of Rx PFIR Array */ + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "coefs", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (j = 0; j < ADI_ADRV9025_MAX_RXPFIR_COEFS; j++) + { + recoveryAction = adrv9025_JsonParseArrayElementI16(device, + fp, + &lineStr[0], + &currChar, + &(rxSettings->rxChannelCfg[i].profile.rxFir.coefs[j])); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find End of Rx PFIR Array */ + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "coefs", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "rxFir", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rxDdcMode", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDdcMode); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "rxNcoShifterCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "bandAInputBandWidth_kHz", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxNcoShifterCfg.bandAInputBandWidth_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseI32(device, + fp, + &lineStr[0], + "bandAInputCenterFreq_kHz", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxNcoShifterCfg.bandAInputCenterFreq_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseI32(device, + fp, + &lineStr[0], + "bandANco1Freq_kHz", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxNcoShifterCfg.bandANco1Freq_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseI32(device, + fp, + &lineStr[0], + "bandANco2Freq_kHz", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxNcoShifterCfg.bandANco2Freq_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "bandBInputBandWidth_kHz", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxNcoShifterCfg.bandBInputBandWidth_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseI32(device, + fp, + &lineStr[0], + "bandBInputCenterFreq_kHz", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxNcoShifterCfg.bandBInputCenterFreq_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseI32(device, + fp, + &lineStr[0], + "bandBNco1Freq_kHz", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxNcoShifterCfg.bandBNco1Freq_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseI32(device, + fp, + &lineStr[0], + "bandBNco2Freq_kHz", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxNcoShifterCfg.bandBNco2Freq_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseI32(device, + fp, + &lineStr[0], + "bandAbCombinedEnable", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxNcoShifterCfg.bandAbCombinedEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "rxNcoShifterCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "tiaPowerMode", + &currChar, + &rxSettings->rxChannelCfg[i].profile.tiaPowerMode); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "rxDataFormat", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rxChannelMask", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.rxChannelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "formatSelect", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.formatSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "floatingPointConfig", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "fpDataFormat", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.floatingPointConfig.fpDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "fpRoundMode", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.floatingPointConfig.fpRoundMode); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "fpNumExpBits", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.floatingPointConfig.fpNumExpBits); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "fpAttenSteps", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.floatingPointConfig.fpAttenSteps); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "fpHideLeadingOne", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.floatingPointConfig.fpHideLeadingOne); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "fpEncodeNan", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.floatingPointConfig.fpEncodeNan); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "floatingPointConfig", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "integerConfigSettings", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "intEmbeddedBits", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.integerConfigSettings.intEmbeddedBits); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "intSampleResolution", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.integerConfigSettings.intSampleResolution); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "intParity", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.integerConfigSettings.intParity); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "intEmbeddedPos", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.integerConfigSettings.intEmbeddedPos); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "integerConfigSettings", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "slicerConfigSettings", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "extSlicerStepSize", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.slicerConfigSettings.extSlicerStepSize); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "intSlicerStepSize", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.slicerConfigSettings.intSlicerStepSize); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rx1ExtSlicerGpioSelect", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.slicerConfigSettings.rx1ExtSlicerGpioSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rx2ExtSlicerGpioSelect", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.slicerConfigSettings.rx2ExtSlicerGpioSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rx3ExtSlicerGpioSelect", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.slicerConfigSettings.rx3ExtSlicerGpioSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rx4ExtSlicerGpioSelect", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.slicerConfigSettings.rx4ExtSlicerGpioSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "slicerConfigSettings", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "embOvldMonitorSettings", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "embeddedMonitorSrcLsbI", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.embOvldMonitorSettings.embeddedMonitorSrcLsbI); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "embeddedMonitorSrcLsbQ", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.embOvldMonitorSettings.embeddedMonitorSrcLsbQ); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "embeddedMonitorSrcLsbPlusOneI", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i] + .profile.rxDataFormat.embOvldMonitorSettings.embeddedMonitorSrcLsbPlusOneI); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "embeddedMonitorSrcLsbPlusOneQ", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i] + .profile.rxDataFormat.embOvldMonitorSettings.embeddedMonitorSrcLsbPlusOneQ); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "embeddedMonitorHb2LowSrcSel", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.embOvldMonitorSettings.embeddedMonitorHb2LowSrcSel); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "embeddedMonitorHb2HighSrcSel", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i] + .profile.rxDataFormat.embOvldMonitorSettings.embeddedMonitorHb2HighSrcSel); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "embeddedMonitorApdLowSrcSel", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i].profile.rxDataFormat.embOvldMonitorSettings.embeddedMonitorApdLowSrcSel); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "embeddedMonitorApdHighSrcSel", + &currChar, + (uint32_t*)&rxSettings->rxChannelCfg[i] + .profile.rxDataFormat.embOvldMonitorSettings.embeddedMonitorApdHighSrcSel); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "invertHb2Flag", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxDataFormat.embOvldMonitorSettings.invertHb2Flag); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "invertApdFlag", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxDataFormat.embOvldMonitorSettings.invertApdFlag); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "embOvldMonitorSettings", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "externalLnaGain", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxDataFormat.externalLnaGain); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "tempCompensationEnable", + &currChar, + &rxSettings->rxChannelCfg[i].profile.rxDataFormat.tempCompensationEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "rxDataFormat", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "profile", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindClosedCurlBrace(device, + fp, + &lineStr[0], + NULL, + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "rxChannelCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "rx", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} +int32_t adrv9025_JsonParseInitAdcProfileSettings(adi_adrv9025_Device_t* device, + adi_adrv9025_AdcProfiles_t* adcProfiles, + FILE* fp) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t currChar = 0; + char lineStr[ADRV9025_MAX_FILE_BUFFER + 1] = { 0 }; + uint32_t j = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + adcProfiles); + + /* Find Start of Rx ADC Profiles Object*/ + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "adcProfiles", + &currChar); + if (recoveryAction == ADI_COMMON_ACT_ERR_CHECK_PARAM) + { + /* if not found then set the inti struct ADC profiles to 0, clear the error and return no error + * this is to keep backwards compatibility*/ + memset(adcProfiles->RxChannel1, 0, ADC_PROFILE_MAX*sizeof(uint16_t)); + memset(adcProfiles->RxChannel2, 0, ADC_PROFILE_MAX*sizeof(uint16_t)); + memset(adcProfiles->RxChannel3, 0, ADC_PROFILE_MAX*sizeof(uint16_t)); + memset(adcProfiles->RxChannel4, 0, ADC_PROFILE_MAX*sizeof(uint16_t)); + memset(adcProfiles->OrxChannel1Profile0, 0, ADC_PROFILE_MAX*sizeof(uint16_t)); + memset(adcProfiles->OrxChannel1Profile1, 0, ADC_PROFILE_MAX*sizeof(uint16_t)); + memset(adcProfiles->OrxChannel1Profile2, 0, ADC_PROFILE_MAX*sizeof(uint16_t)); + memset(adcProfiles->OrxChannel1Profile3, 0, ADC_PROFILE_MAX*sizeof(uint16_t)); + memset(adcProfiles->OrxChannel2Profile0, 0, ADC_PROFILE_MAX*sizeof(uint16_t)); + memset(adcProfiles->OrxChannel2Profile1, 0, ADC_PROFILE_MAX*sizeof(uint16_t)); + memset(adcProfiles->OrxChannel2Profile2, 0, ADC_PROFILE_MAX*sizeof(uint16_t)); + memset(adcProfiles->OrxChannel2Profile3, 0, ADC_PROFILE_MAX*sizeof(uint16_t)); + adcProfiles->OrxChannel1Index = 0; + adcProfiles->OrxChannel2Index = 0; + recoveryAction = adi_common_ErrorClear(&device->common); + return recoveryAction; + } + else + { + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find Start of RxChannel1 ADC profile*/ + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "RxChannel1", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (j = 0; j < ADC_PROFILE_MAX; j++) + { + recoveryAction = adrv9025_JsonParseArrayElementU16(device, + fp, + &lineStr[0], + &currChar, + &(adcProfiles->RxChannel1[j])); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find End of RxChannel1 ADC profile array*/ + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "RxChannel1", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Find Start of RxChannel2 array*/ + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "RxChannel2", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (j = 0; j < ADC_PROFILE_MAX; j++) + { + recoveryAction = adrv9025_JsonParseArrayElementU16(device, + fp, + &lineStr[0], + &currChar, + &(adcProfiles->RxChannel2[j])); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find End of RxChannel2 array*/ + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "RxChannel2", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Find Start of RxChannel3 array*/ + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "RxChannel3", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (j = 0; j < ADC_PROFILE_MAX; j++) + { + recoveryAction = adrv9025_JsonParseArrayElementU16(device, + fp, + &lineStr[0], + &currChar, + &(adcProfiles->RxChannel3[j])); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find End of RxChannel3 array*/ + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "RxChannel3", + &currChar); + + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Find Start of RxChannel4 array*/ + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "RxChannel4", + &currChar); + + for (j = 0; j < ADC_PROFILE_MAX; j++) + { + recoveryAction = adrv9025_JsonParseArrayElementU16(device, + fp, + &lineStr[0], + &currChar, + &(adcProfiles->RxChannel4[j])); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find End of RxChannel4 array*/ + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "RxChannel4", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Find Start of OrxChannel1Profile0 array*/ + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "OrxChannel1Profile0", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (j = 0; j < ADC_PROFILE_MAX; j++) + { + recoveryAction = adrv9025_JsonParseArrayElementU16(device, + fp, + &lineStr[0], + &currChar, + &(adcProfiles->OrxChannel1Profile0[j])); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find End of OrxChannel1Profile0 array*/ + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "OrxChannel1Profile0", + &currChar); + + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Find Start of OrxChannel1Profile1 array*/ + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "OrxChannel1Profile1", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (j = 0; j < ADC_PROFILE_MAX; j++) + { + recoveryAction = adrv9025_JsonParseArrayElementU16(device, + fp, + &lineStr[0], + &currChar, + &(adcProfiles->OrxChannel1Profile1[j])); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find End of OrxChannel1Profile1 array*/ + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "OrxChannel1Profile1", + &currChar); + + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Find Start of OrxChannel1Profile2 array*/ + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "OrxChannel1Profile2", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (j = 0; j < ADC_PROFILE_MAX; j++) + { + recoveryAction = adrv9025_JsonParseArrayElementU16(device, + fp, + &lineStr[0], + &currChar, + &(adcProfiles->OrxChannel1Profile2[j])); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find End of OrxChannel1Profile2 array*/ + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "OrxChannel1Profile2", + &currChar); + + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Find Start of OrxChannel1Profile3 array*/ + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "OrxChannel1Profile3", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (j = 0; j < ADC_PROFILE_MAX; j++) + { + recoveryAction = adrv9025_JsonParseArrayElementU16(device, + fp, + &lineStr[0], + &currChar, + &(adcProfiles->OrxChannel1Profile3[j])); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find End of OrxChannel1Profile3 array*/ + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "OrxChannel1Profile3", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Find Start of OrxChannel2Profile0 array*/ + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "OrxChannel2Profile0", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (j = 0; j < ADC_PROFILE_MAX; j++) + { + recoveryAction = adrv9025_JsonParseArrayElementU16(device, + fp, + &lineStr[0], + &currChar, + &(adcProfiles->OrxChannel2Profile0[j])); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find End of OrxChannel2Profile0 array*/ + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "OrxChannel2Profile0", + &currChar); + + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Find Start of OrxChannel2Profile1 array*/ + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "OrxChannel2Profile1", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (j = 0; j < ADC_PROFILE_MAX; j++) + { + recoveryAction = adrv9025_JsonParseArrayElementU16(device, + fp, + &lineStr[0], + &currChar, + &(adcProfiles->OrxChannel2Profile1[j])); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find End of OrxChannel2Profile1 array*/ + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "OrxChannel2Profile1", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Find Start of OrxChannel2Profile2 array*/ + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "OrxChannel2Profile2", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (j = 0; j < ADC_PROFILE_MAX; j++) + { + recoveryAction = adrv9025_JsonParseArrayElementU16(device, + fp, + &lineStr[0], + &currChar, + &(adcProfiles->OrxChannel2Profile2[j])); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find End of OrxChannel2Profile2 array*/ + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "OrxChannel2Profile2", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Find Start of OrxChannel2Profile3 array*/ + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "OrxChannel2Profile3", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (j = 0; j < ADC_PROFILE_MAX; j++) + { + recoveryAction = adrv9025_JsonParseArrayElementU16(device, + fp, + &lineStr[0], + &currChar, + &(adcProfiles->OrxChannel2Profile3[j])); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find End of OrxChannel2Profile3 array*/ + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "OrxChannel2Profile3", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + + recoveryAction = adrv9025_JsonParseUI8(device, + fp, + &lineStr[0], + "OrxChannel1Index", + &currChar, + &(adcProfiles->OrxChannel1Index)); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseUI8(device, + fp, + &lineStr[0], + "OrxChannel2Index", + &currChar, + &(adcProfiles->OrxChannel2Index)); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Find End of ADC profiles */ + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "rxadcprofiles", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_JsonParseInitTxSettings(adi_adrv9025_Device_t* device, + adi_adrv9025_TxSettings_t* txSettings, + FILE* fp) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t currChar = 0; + char lineStr[ADRV9025_MAX_FILE_BUFFER + 1] = {0}; + uint32_t i = 0; + uint32_t j = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + txSettings); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "tx", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "txInitChannelMask", + &currChar, + &txSettings->txInitChannelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "txChannelCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_ADRV9025_MAX_TXCHANNELS; i++) + { + recoveryAction = adrv9025_JsonFindOpenCurlBrace(device, + fp, + &lineStr[0], + NULL, + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "profile", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "txInputRate_kHz", + &currChar, + &txSettings->txChannelCfg[i].profile.txInputRate_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "primarySigBandwidth_kHz", + &currChar, + &txSettings->txChannelCfg[i].profile.primarySigBandwidth_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "rfBandwidth_kHz", + &currChar, + &txSettings->txChannelCfg[i].profile.rfBandwidth_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "txDac3dBCorner_kHz", + &currChar, + &txSettings->txChannelCfg[i].profile.txDac3dBCorner_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "txBbf3dBCorner_kHz", + &currChar, + &txSettings->txChannelCfg[i].profile.txBbf3dBCorner_kHz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "dpdHb1Interpolation", + &currChar, + &txSettings->txChannelCfg[i].profile.dpdHb1Interpolation); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "dpdHb2Interpolation", + &currChar, + &txSettings->txChannelCfg[i].profile.dpdHb2Interpolation); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "txFirInterpolation", + &currChar, + &txSettings->txChannelCfg[i].profile.txFirInterpolation); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "thb1Interpolation", + &currChar, + &txSettings->txChannelCfg[i].profile.thb1Interpolation); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "thb2Interpolation", + &currChar, + &txSettings->txChannelCfg[i].profile.thb2Interpolation); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "thb3Interpolation", + &currChar, + &txSettings->txChannelCfg[i].profile.thb3Interpolation); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "txInt5Interpolation", + &currChar, + &txSettings->txChannelCfg[i].profile.txInt5Interpolation); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "txFir", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseI8(device, + fp, + &lineStr[0], + "gain_dB", + &currChar, + &txSettings->txChannelCfg[i].profile.txFir.gain_dB); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "numFirCoefs", + &currChar, + &txSettings->txChannelCfg[i].profile.txFir.numFirCoefs); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Find Start of Tx PFIR Array */ + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "coefs", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (j = 0; j < ADI_ADRV9025_MAX_TXPFIR_COEFS; j++) + { + recoveryAction = adrv9025_JsonParseArrayElementI16(device, + fp, + &lineStr[0], + &currChar, + &(txSettings->txChannelCfg[i].profile.txFir.coefs[j])); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find End of Tx PFIR Array */ + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "coefs", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "txFir", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "txBbfPowerMode", + &currChar, + &txSettings->txChannelCfg[i].profile.txBbfPowerMode); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Find End of Tx Profile Array */ + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "profile", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "txAttenCtrl", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "txAttenStepSize", + &currChar, + (uint32_t*)&txSettings->txChannelCfg[i].txAttenCtrl.txAttenStepSize); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "txRampDownEvents", + &currChar, + (uint32_t*)&txSettings->txChannelCfg[i].txAttenCtrl.txRampDownEvents); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "reserved", + &currChar, + (uint32_t*)&txSettings->txChannelCfg[i].txAttenCtrl.reserved); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "attenMode", + &currChar, + (uint32_t*)&txSettings->txChannelCfg[i].txAttenCtrl.attenMode); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* The "dacFUllScale" was moved out of the block but some profiles still have it to maintain init structure */ + if ((recoveryAction = adrv9025_JsonPeekNextKeyword(device, + fp, + &lineStr[0], + "dacFullScale")) > 0) + { + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "dacFullScale", + &currChar, + (uint32_t*)&txSettings->txChannelCfg[i].txAttenCtrl.dacFullScale); + //reserved field to maintain init structure (not used) + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_JsonParseU16(device, + fp, + &lineStr[0], + "txAttenInit_mdB", + &currChar, + &txSettings->txChannelCfg[i].txAttenCtrl.txAttenInit_mdB); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "txAttenCtrl", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "dacFullScale", + &currChar, + (uint32_t*)&txSettings->txChannelCfg[i].dacFullScale); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindClosedCurlBrace(device, + fp, + &lineStr[0], + NULL, + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "txChannelCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "tx", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_JsonParseInitDataInterfaceSettings(adi_adrv9025_Device_t* device, + adi_adrv9025_DataInterfaceCfg_t* dataInterfaceSettings, + FILE* fp) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t currChar = 0; + char lineStr[ADRV9025_MAX_FILE_BUFFER + 1] = {0}; + uint32_t i = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + dataInterfaceSettings); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "dataInterface", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "framer", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_ADRV9025_NUM_FRAMERS; i++) + { + recoveryAction = adrv9025_JsonFindOpenCurlBrace(device, + fp, + &lineStr[0], + NULL, + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "serializerLaneCrossbar", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "lane0FramerOutSel", + &currChar, + &dataInterfaceSettings->framer[i].serializerLaneCrossbar.lane0FramerOutSel); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "lane1FramerOutSel", + &currChar, + &dataInterfaceSettings->framer[i].serializerLaneCrossbar.lane1FramerOutSel); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "lane2FramerOutSel", + &currChar, + &dataInterfaceSettings->framer[i].serializerLaneCrossbar.lane2FramerOutSel); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "lane3FramerOutSel", + &currChar, + &dataInterfaceSettings->framer[i].serializerLaneCrossbar.lane3FramerOutSel); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "serializerLaneCrossbar", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "adcCrossbar", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv0", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv1", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv2", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv3", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv4", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv5", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv6", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv6); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv7", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv7); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv8", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv9", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv10", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv11", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv12", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv12); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv13", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv13); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv14", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv15", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv15); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv16", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv16); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv17", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv17); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv18", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv19", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv20", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv20); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv21", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv21); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv22", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv22); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv23", + &currChar, + (uint32_t*)&dataInterfaceSettings->framer[i].adcCrossbar.conv23); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "adcCrossbar", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "enableJesd204C", + &currChar, + &dataInterfaceSettings->framer[i].enableJesd204C); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "bankId", + &currChar, + &dataInterfaceSettings->framer[i].bankId); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "deviceId", + &currChar, + &dataInterfaceSettings->framer[i].deviceId); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "lane0Id", + &currChar, + &dataInterfaceSettings->framer[i].lane0Id); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "jesd204M", + &currChar, + &dataInterfaceSettings->framer[i].jesd204M); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU16(device, + fp, + &lineStr[0], + "jesd204K", + &currChar, + &dataInterfaceSettings->framer[i].jesd204K); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "jesd204F", + &currChar, + &dataInterfaceSettings->framer[i].jesd204F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "jesd204Np", + &currChar, + &dataInterfaceSettings->framer[i].jesd204Np); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "jesd204E", + &currChar, + &dataInterfaceSettings->framer[i].jesd204E); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "scramble", + &currChar, + &dataInterfaceSettings->framer[i].scramble); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "serializerLanesEnabled", + &currChar, + &dataInterfaceSettings->framer[i].serializerLanesEnabled); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU16(device, + fp, + &lineStr[0], + "lmfcOffset", + &currChar, + &dataInterfaceSettings->framer[i].lmfcOffset); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "syncbInSelect", + &currChar, + &dataInterfaceSettings->framer[i].syncbInSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "overSample", + &currChar, + &dataInterfaceSettings->framer[i].overSample); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "syncbInLvdsMode", + &currChar, + &dataInterfaceSettings->framer[i].syncbInLvdsMode); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "syncbInLvdsPnInvert", + &currChar, + &dataInterfaceSettings->framer[i].syncbInLvdsPnInvert); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "newSysrefOnRelink", + &currChar, + &dataInterfaceSettings->framer[i].newSysrefOnRelink); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "sysrefForStartup", + &currChar, + &dataInterfaceSettings->framer[i].sysrefForStartup); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "sysrefNShotEnable", + &currChar, + &dataInterfaceSettings->framer[i].sysrefNShotEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "sysrefNShotCount", + &currChar, + &dataInterfaceSettings->framer[i].sysrefNShotCount); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "sysrefIgnoreWhenLinked", + &currChar, + &dataInterfaceSettings->framer[i].sysrefIgnoreWhenLinked); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindClosedCurlBrace(device, + fp, + &lineStr[0], + NULL, + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "framer", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "deframer", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_ADRV9025_NUM_DEFRAMERS; i++) + { + recoveryAction = adrv9025_JsonFindOpenCurlBrace(device, + fp, + &lineStr[0], + NULL, + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "deserializerLaneCrossbar", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "deframerInput0LaneSel", + &currChar, + &dataInterfaceSettings->deframer[i].deserializerLaneCrossbar.deframerInput0LaneSel); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "deframerInput1LaneSel", + &currChar, + &dataInterfaceSettings->deframer[i].deserializerLaneCrossbar.deframerInput1LaneSel); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "deframerInput2LaneSel", + &currChar, + &dataInterfaceSettings->deframer[i].deserializerLaneCrossbar.deframerInput2LaneSel); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "deframerInput3LaneSel", + &currChar, + &dataInterfaceSettings->deframer[i].deserializerLaneCrossbar.deframerInput3LaneSel); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "deserializerLaneCrossbar", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "enableJesd204C", + &currChar, + &dataInterfaceSettings->deframer[i].enableJesd204C); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "bankId", + &currChar, + &dataInterfaceSettings->deframer[i].bankId); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "deviceId", + &currChar, + &dataInterfaceSettings->deframer[i].deviceId); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "lane0Id", + &currChar, + &dataInterfaceSettings->deframer[i].lane0Id); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "jesd204M", + &currChar, + &dataInterfaceSettings->deframer[i].jesd204M); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU16(device, + fp, + &lineStr[0], + "jesd204K", + &currChar, + &dataInterfaceSettings->deframer[i].jesd204K); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "jesd204F", + &currChar, + &dataInterfaceSettings->deframer[i].jesd204F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "jesd204Np", + &currChar, + &dataInterfaceSettings->deframer[i].jesd204Np); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "jesd204E", + &currChar, + &dataInterfaceSettings->deframer[i].jesd204E); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "scramble", + &currChar, + &dataInterfaceSettings->deframer[i].scramble); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "deserializerLanesEnabled", + &currChar, + &dataInterfaceSettings->deframer[i].deserializerLanesEnabled); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU16(device, + fp, + &lineStr[0], + "lmfcOffset", + &currChar, + &dataInterfaceSettings->deframer[i].lmfcOffset); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "syncbOutSelect", + &currChar, + &dataInterfaceSettings->deframer[i].syncbOutSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "syncbOutLvdsMode", + &currChar, + &dataInterfaceSettings->deframer[i].syncbOutLvdsMode); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "syncbOutLvdsPnInvert", + &currChar, + &dataInterfaceSettings->deframer[i].syncbOutLvdsPnInvert); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "syncbOutCmosSlewRate", + &currChar, + &dataInterfaceSettings->deframer[i].syncbOutCmosSlewRate); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "syncbOutCmosDriveLevel", + &currChar, + &dataInterfaceSettings->deframer[i].syncbOutCmosDriveLevel); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "dacCrossbar", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "tx1DacChanI", + &currChar, + (uint32_t*)&dataInterfaceSettings->deframer[i].dacCrossbar.tx1DacChanI); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "tx1DacChanQ", + &currChar, + (uint32_t*)&dataInterfaceSettings->deframer[i].dacCrossbar.tx1DacChanQ); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "tx2DacChanI", + &currChar, + (uint32_t*)&dataInterfaceSettings->deframer[i].dacCrossbar.tx2DacChanI); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "tx2DacChanQ", + &currChar, + (uint32_t*)&dataInterfaceSettings->deframer[i].dacCrossbar.tx2DacChanQ); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "tx3DacChanI", + &currChar, + (uint32_t*)&dataInterfaceSettings->deframer[i].dacCrossbar.tx3DacChanI); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "tx3DacChanQ", + &currChar, + (uint32_t*)&dataInterfaceSettings->deframer[i].dacCrossbar.tx3DacChanQ); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "tx4DacChanI", + &currChar, + (uint32_t*)&dataInterfaceSettings->deframer[i].dacCrossbar.tx4DacChanI); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "tx4DacChanQ", + &currChar, + (uint32_t*)&dataInterfaceSettings->deframer[i].dacCrossbar.tx4DacChanQ); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "dacCrossbar", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "newSysrefOnRelink", + &currChar, + &dataInterfaceSettings->deframer[i].newSysrefOnRelink); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "sysrefForStartup", + &currChar, + &dataInterfaceSettings->deframer[i].sysrefForStartup); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "sysrefNShotEnable", + &currChar, + &dataInterfaceSettings->deframer[i].sysrefNShotEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "sysrefNShotCount", + &currChar, + &dataInterfaceSettings->deframer[i].sysrefNShotCount); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "sysrefIgnoreWhenLinked", + &currChar, + &dataInterfaceSettings->deframer[i].sysrefIgnoreWhenLinked); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindClosedCurlBrace(device, + fp, + &lineStr[0], + NULL, + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "deframer", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "serCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_ADRV9025_NUM_LANES; i++) + { + recoveryAction = adrv9025_JsonFindOpenCurlBrace(device, + fp, + &lineStr[0], + NULL, + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "serAmplitude", + &currChar, + &dataInterfaceSettings->serCfg[i].serAmplitude); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "serPreEmphasis", + &currChar, + &dataInterfaceSettings->serCfg[i].serPreEmphasis); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "serPostEmphasis", + &currChar, + &dataInterfaceSettings->serCfg[i].serPostEmphasis); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "serInvertLanePolarity", + &currChar, + &dataInterfaceSettings->serCfg[i].serInvertLanePolarity); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindClosedCurlBrace(device, + fp, + &lineStr[0], + NULL, + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "serCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfArray(device, + fp, + &lineStr[0], + "desCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_ADRV9025_NUM_LANES; i++) + { + recoveryAction = adrv9025_JsonFindOpenCurlBrace(device, + fp, + &lineStr[0], + NULL, + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "highBoost", + &currChar, + &dataInterfaceSettings->desCfg[i].highBoost); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "configOption1", + &currChar, + &dataInterfaceSettings->desCfg[i].configOption1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "configOption2", + &currChar, + &dataInterfaceSettings->desCfg[i].configOption2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "configOption3", + &currChar, + &dataInterfaceSettings->desCfg[i].configOption3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "configOption4", + &currChar, + &dataInterfaceSettings->desCfg[i].configOption4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "configOption5", + &currChar, + &dataInterfaceSettings->desCfg[i].configOption5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "configOption6", + &currChar, + &dataInterfaceSettings->desCfg[i].configOption6); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "configOption7", + &currChar, + &dataInterfaceSettings->desCfg[i].configOption7); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "configOption8", + &currChar, + &dataInterfaceSettings->desCfg[i].configOption8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "configOption9", + &currChar, + &dataInterfaceSettings->desCfg[i].configOption9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "configOption10", + &currChar, + &dataInterfaceSettings->desCfg[i].configOption10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "desInvertLanePolarity", + &currChar, + &dataInterfaceSettings->desCfg[i].desInvertLanePolarity); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindClosedCurlBrace(device, + fp, + &lineStr[0], + NULL, + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_JsonFindEndOfArray(device, + fp, + &lineStr[0], + "desCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "linkSharingCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "linkSharingEnabled", + &currChar, + &dataInterfaceSettings->linkSharingCfg.linkSharingEnabled); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "linkSharingM", + &currChar, + &dataInterfaceSettings->linkSharingCfg.linkSharingM); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "linkSharingS", + &currChar, + &dataInterfaceSettings->linkSharingCfg.linkSharingS); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "linkSharingNp", + &currChar, + &dataInterfaceSettings->linkSharingCfg.linkSharingNp); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "linkSharingAdcCrossbar", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv0", + &currChar, + (uint32_t*)&dataInterfaceSettings->linkSharingCfg.linkSharingAdcCrossbar.conv0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv1", + &currChar, + (uint32_t*)&dataInterfaceSettings->linkSharingCfg.linkSharingAdcCrossbar.conv1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv2", + &currChar, + (uint32_t*)&dataInterfaceSettings->linkSharingCfg.linkSharingAdcCrossbar.conv2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv3", + &currChar, + (uint32_t*)&dataInterfaceSettings->linkSharingCfg.linkSharingAdcCrossbar.conv3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv4", + &currChar, + (uint32_t*)&dataInterfaceSettings->linkSharingCfg.linkSharingAdcCrossbar.conv4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv5", + &currChar, + (uint32_t*)&dataInterfaceSettings->linkSharingCfg.linkSharingAdcCrossbar.conv5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv6", + &currChar, + (uint32_t*)&dataInterfaceSettings->linkSharingCfg.linkSharingAdcCrossbar.conv6); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv7", + &currChar, + (uint32_t*)&dataInterfaceSettings->linkSharingCfg.linkSharingAdcCrossbar.conv7); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv8", + &currChar, + (uint32_t*)&dataInterfaceSettings->linkSharingCfg.linkSharingAdcCrossbar.conv8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv9", + &currChar, + (uint32_t*)&dataInterfaceSettings->linkSharingCfg.linkSharingAdcCrossbar.conv9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv10", + &currChar, + (uint32_t*)&dataInterfaceSettings->linkSharingCfg.linkSharingAdcCrossbar.conv10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv11", + &currChar, + (uint32_t*)&dataInterfaceSettings->linkSharingCfg.linkSharingAdcCrossbar.conv11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv12", + &currChar, + (uint32_t*)&dataInterfaceSettings->linkSharingCfg.linkSharingAdcCrossbar.conv12); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv13", + &currChar, + (uint32_t*)&dataInterfaceSettings->linkSharingCfg.linkSharingAdcCrossbar.conv13); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv14", + &currChar, + (uint32_t*)&dataInterfaceSettings->linkSharingCfg.linkSharingAdcCrossbar.conv14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + fp, + &lineStr[0], + "conv15", + &currChar, + (uint32_t*)&dataInterfaceSettings->linkSharingCfg.linkSharingAdcCrossbar.conv15); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "linkSharingAdcCrossbar", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "linkSharingCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "dataCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "enable", + &currChar, + &dataInterfaceSettings->dataCfg.enable); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "configOption1", + &currChar, + &dataInterfaceSettings->dataCfg.configOption1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "configOption2", + &currChar, + &dataInterfaceSettings->dataCfg.configOption2); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "dataCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "channelSelect", + &currChar, + &dataInterfaceSettings->channelSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + fp, + &lineStr[0], + "channelMode", + &currChar, + &dataInterfaceSettings->channelMode); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "datapath", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adrv9025_JsonParseUtilRadioctrlInit(adi_adrv9025_Device_t* device, + adi_adrv9025_RadioctrlInit_t* radioCtrlInit, + FILE* fp) +{ + UNUSED_PARA(device); + UNUSED_PARA(radioCtrlInit); + UNUSED_PARA(fp); + /* TODO */ + return 0; +} + +int32_t adrv9025_JsonParseUtilInitCals(adi_adrv9025_Device_t* device, + adi_adrv9025_InitCals_t* initCals, + FILE* fp) +{ + UNUSED_PARA(device); + UNUSED_PARA(initCals); + UNUSED_PARA(fp); + /* TODO */ + return 0; +} + +int32_t adrv9025_JsonParseInitGpInterruptSettings(adi_adrv9025_Device_t* device, + adi_adrv9025_GpInterruptSettings_t* gpInterruptSettings, + FILE* fp) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t currChar = 0; + char lineStr[ADRV9025_MAX_FILE_BUFFER + 1] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + fp); + + ADI_NULL_PTR_RETURN(&device->common, + gpInterruptSettings); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + fp, + &lineStr[0], + "gpInterrupts", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU64(device, + fp, + &lineStr[0], + "gpIntMaskPin0", + &currChar, + &gpInterruptSettings->gpIntMaskPin0); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU64(device, + fp, + &lineStr[0], + "gpIntMaskPin1", + &currChar, + &gpInterruptSettings->gpIntMaskPin1); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + fp, + &lineStr[0], + "gpInterrupts", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025.h new file mode 100644 index 0000000..867f0e7 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025.h @@ -0,0 +1,433 @@ +/** +* \file adi_adrv9025.h +* \brief Contains top level Adrv9025 related function prototypes for +* adi_adrv9025.c +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_H_ +#define _ADI_ADRV9025_H_ + +#include "adi_adrv9025_types.h" +#include "adi_common_macros.h" +#include "adi_adrv9025_user.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Performs a Hardware Initialization for ADRV9025 Device. +* +* This API shall call the ADI HAL function adi_hal_HwOpen for +* ADRV9025 Hardware initialization. This HAL function initializes all the external +* hardware blocks required in the operation of the Adrv9025 device. +* This API will also set the HAL timeout limit for the HAL driver as per API +* requirements. +* +* \pre This function may be called after device->common.devHalInfo has been initialized with +* user values +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to ADRV9025 device data structure. Adrv9025Device_t member +* devHalInfo shall be initialized with all the required information to initialize +* external Hardware required for ADRV9025 operation for example +* power, pull ups, SPI master etc +* \param spiSettings Pointer to adi_adrv9025_SpiSettings_t structure that contains SPI +* configuration parameters. These settings get copied into the device structure. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_ERR_RESET_FEATURE Recovery action for user GPIO reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_HwOpen(adi_adrv9025_Device_t* device, + adi_adrv9025_SpiSettings_t* spiSettings); + +/** +* \brief Performs a hardware shutdown for ADRV9025 Device. +* +* This API shall call the ADI HAL function adi_hal_HwClose for +* ADRV9025 Hardware shutdown. This HAL function shuts down all the external +* hardware blocks required in the operation of the Adrv9025 device. +* +* \pre This function may be called any time after device->common.devHalInfo has been +* initialized with user values +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to ADRV9025 device data structure. Adrv9025Device_t member +* devHalInfo shall be initialized with all the required information to initialize +* supporting Hardware for ADRV9025 operation for example +* power, pull ups, SPI master etc +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_ERR_RESET_FEATURE Recovery action for user GPIO reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_HwClose(adi_adrv9025_Device_t* device); + +/** +* \brief Performs a hard reset on the ADRV9025 DUT (Toggles RESETB pin on device) +* +* Toggles the ADRV9025 devices RESETB pin. Only resets the device with +* the SPI chip select indicated in the device->spiSettings structure. +* +* \pre This function may be called any time after device->common.devHalInfo has been +* initialized with user values +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to ADRV9025 device data structure containing settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_WARN_RESET_GPIO Recovery action to warn user a GPIO reset may be required +* \retval ADI_COMMON_ACT_ERR_RESET_FEATURE Recovery action for user GPIO reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_HwReset(adi_adrv9025_Device_t* device); + +/** +* \brief Initializes the ADRV9025 device based on the desired device settings. +* +* This function initializes the ADRV9025 device, digital clocks, +* JESD204b settings, FIR Filters, digital filtering. It does not load the ARM +* or perform any of the ARM init calibrations. It leaves the +* ADRV9025 in a state ready for multichip sync (which can bring up the JESD204 links), the +* ARM to be loaded, and the init calibrations run. +* +* \pre This function is the very first API to be called by the user to configure the device +* after all dependent data structures have been initialized +* +* \dep_begin +* \dep{device (all members)} +* \dep{init (all members)} +* \dep_end +* +* \param device Pointer to ADRV9025 device data structure +* \param init Pointer to ADRV9025 initialization settings structures +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_Initialize(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init); + +/** +* \brief API To safely Shutdown Adrv9025 +* +* The User should call this function to safely shutdown ADRV9025 Device. +* The function performs a hardware reset to reset the ADRV9025 Device into a safe +* state for shutdown or re-initialization. +* +* \pre This function may be called at any time but not before device->common.devHalInfo +* has been configured with user device settings +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_Shutdown(adi_adrv9025_Device_t* device); + +/** +* \brief Sets up the transceiver to listen for incoming SYSREF pulses to synchronize the internal clock tree. +* +* When working with multiple transceivers or even only one transceiver that +* requires deterministic latency between the Tx and observation and or main +* Rx JESD204B data path, Multichip sync is necessary. This function should +* be run after all transceivers have finished the Adrv9025_initialize(), +* and after Adrv9025_ArmStart(). +* +* This function will reset the MCS state +* machine in the ADRV9025 device. Calling the function again, will reset +* the state machine and expect the MCS sequence to start over. Since clocks +* will be adjusted, the transceiver should not be transmitting or receiving +* when this function is called. +* +* Typical sequence: +* 1) Initialize all ADRV9025 devices in system using Adrv9025_initialize() +* 2) Run adi_adrv9025_MultichipSyncSet(). Make sure enableSync is 1. +* 3) Send at least 4 SYSREF pulses, and verify mcsStatus is set for each +* MCS step +* 4) Use adi_adrv9025_MultichipSyncStatusGet() to verify MCS. +* 4) Run adi_adrv9025_MultichipSyncSet(). Make sure enableSync is 0 +* to indicate end of MCS sequence. +* 5) Continue with init sequnece ... int cals, etc +* +* \pre This function is called after the device has been initialized and PLL lock status has +* been verified. ARM must be running before calling this function. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device is a pointer to the device settings structure +* \param enableSync is a 0/1 variable used to indicate MultiChipSync start/stop. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_MultichipSyncSet(adi_adrv9025_Device_t* device, + uint8_t enableSync); + +/** +* \brief Reads back the multi-chip sync status +* +* After running adi_adrv9025_MultichipSyncSet(), this function can be used +* to verify that all the SYSREF pulses were received by the transceiver. +* +* Typical sequence: +* 1) Initialize all ADRV9025 devices in system using adi_adrv9025_initialize() +* 2) Run adi_adrv9025_MultichipSyncSet() +* 3) Send at least 4 SYSREF pulses, and verify mcsStatus is set for each +* MCS step +* 4) Run adi_adrv9025_MultichipSyncStatusGet() verify mcsStatus +* 5) Continue with init sequnece ... int cals, etc +* +* mcsStatus | bit Description +* -----------|-------------------------------------------------------- +* [0] | MCS JESD SYSREF Status (1 = sync occurred) +* [1] | MCS Digital Clocks Sync Status (1 = sync occurred) +* [2] | MCS Clock Gen Sync Status (1 = sync occurred) +* [3] | MCS CLKPLL SDM Sync Status (1 = sync occurred) +* [4] | MCS Device Clock divider Sync Status (1 = sync occurred) +* +* \pre This function is called after the device has been initialized and PLL lock status has +* been verified. ARM must be running before using the MCS functions. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device A pointer to the device settings structure +* \param mcsStatus Returns the mcsStatus word described in the table above. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_MultichipSyncStatusGet(adi_adrv9025_Device_t* device, + uint32_t* mcsStatus); + +/** +* \brief Verifies the init structure profiles are valid combinations +* +* This function checks that the Rx/Tx/ORx profiles have valid clock rates in +* order to operate together. Rx/Tx and ORx share a common high speed digital +* clock. If an invalid combination of profiles is detected, an error will be +* returned. If a profile in the init structure is unused, the user should zero +* out all members of that particular profile structure. If a Rx/Tx/ORx profile +* has an IQ rate = 0, it is assumed that the profile is disabled. +* +* \pre This function is private and is not called directly by the user. +* +* This function uses Adrv9025_TxProfileVerify(), Adrv9025_RxProfileVerify(), and +* Adrv9025_OrxProfileVerify() as helper functions. +* +* \dep_begin +* \dep{device->devStateInfo} +* \dep{init-> (most members)} +* \dep_end +* +* \param device Structure pointer to ADRV9025 device data structure +* \param init Pointer to ADRV9025 initialization settings structures +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_ProfilesVerify(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init); + +/** +* \brief Sets the ADRV9025 device SPI settings (3wire/4wire, msbFirst, etc). +* +* This function will use the settings in the passed spi structure parameter +* to set SPI stream mode, address auto increment direction, msbFirst/lsbfirst, +* and 3wire/4wire mode for the ADRV9025 SPI controller. The ADRV9025 device +* always uses SPI MODE 0 (CPHA=0, CPOL=0) and a 16-bit instruction word. +* +* \pre This function is a helper function and does not need to be called +* directly by the user. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{init->spiSettings->MSBFirst} +* \dep{init->spiSettings->enSpiStreaming} +* \dep{init->spiSettings->autoIncAddrUp} +* \dep{init->spiSettings->fourWireMode} +* \dep{init->spiSettings->cmosPadDrvStrength} +* \dep_end +* +* \param device Structure pointer to ADRV9025 device data structure +* \param spi Pointer to ADRV9025 SPI controller settings - not platform hardware SPI settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_SpiCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_SpiSettings_t* spi); + +/** +* \brief Gets the ADRV9025 device SPI settings (3wire/4wire, msbFirst, etc). +* +* This function will use the settings in the passed spi structure parameter +* to get SPI stream mode, address auto increment direction, msbFirst/lsbfirst, +* and 3wire/4wire mode for the ADRV9025 SPI controller. The ADRV9025 device +* always uses SPI MODE 0 (CPHA=0, CPOL=0) and a 16-bit instruction word. +* +* \pre This function is a helper function and does not need to be called +* directly by the user. +* \pre Can only call this function if config has been set or SpiVerify +* returns with no errors +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{init->spiSettings->MSBFirst} +* \dep{init->spiSettings->enSpiStreaming} +* \dep{init->spiSettings->autoIncAddrUp} +* \dep{init->spiSettings->fourWireMode} +* \dep{init->spiSettings->cmosPadDrvStrength} +* \dep_end +* +* \param device Structure pointer to ADRV9025 device data structure +* \param spi Pointer to ADRV9025 SPI controller settings - not platform hardware SPI settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_SpiCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_SpiSettings_t* spi); + +/** +* \brief Verifies whether the existing SPI settings work. +* +* This function checks the SPI settings set through adi_adrv9025_setSpiSettings for +* correct functionality. The function performs the following function: +* +* 1. Reads readonly register to check SPI read operation. +* 2. Writes scratchpad register with 10110110, reads back the data +* 3. Writes scratchpad register with 01001001, reads back the data +* +* The function performs the above operation on registers at the lower end of +* the register address space, and on the upper end of the register address +* space. +* +* \pre This function is a helper function and does not need to be called +* directly by the user. +* +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to ADRV9025 device data structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_ERR_RESET_FULL Recovery action for full chip reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_SpiVerify(adi_adrv9025_Device_t* device); + +/** +* \brief Get API version number +* +* This function reads back the version number of the API +* +* \param device Pointer to the ADRV9025 data structure +* \param apiVersion Pointer to structure where API version information is returned +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION function completed successfully, no action required * +*/ +int32_t adi_adrv9025_ApiVersionGet(adi_adrv9025_Device_t* device, + adi_adrv9025_ApiVersion_t* apiVersion); + +/** +* \brief Reads back the silicon revision for the ADRV9025 Device +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param siRevision Return value of the ADRV9025 silicon revision +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION function completed successfully, no action required * +*/ +int32_t adi_adrv9025_DeviceRevGet(adi_adrv9025_Device_t* device, + uint8_t* siRevision); + +/** +* \brief Reads back the Product ID for the ADRV9025 Device +* +* productId | Description +* ------------|--------------- +* 1 | ... +* +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param productId Return value of the ADRV9025 product Id +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION function completed successfully, no action required * +*/ +int32_t adi_adrv9025_ProductIdGet(adi_adrv9025_Device_t* device, + uint8_t* productId); + +/** +* \brief Reads back the device hardware capability +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param devCapability Structure pointer to return device hardware capability +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION function completed successfully, no action required +*/ +int32_t adi_adrv9025_DeviceCapabilityGet(adi_adrv9025_Device_t* device, + adi_adrv9025_CapabilityModel_t* devCapability); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_agc.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_agc.h new file mode 100644 index 0000000..31033cc --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_agc.h @@ -0,0 +1,327 @@ +/** + * \file adi_adrv9025_agc.h + * \brief Contains ADRV9025 API AGC function prototypes for adi_adrv9025_agc.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_AGC_H_ +#define _ADI_ADRV9025_AGC_H_ + +#include "adi_adrv9025_types.h" +#include "adi_adrv9025_agc_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Sets up the device Rx Automatic Gain Control (AGC) registers +* +* The instantiated AGC setting structure (adi_adrv9025_AgcCfg_t) must be initialized with +* valid settings before this function may be used due to the dependencies +* +* This function can be called by the user to load a AGC Config or +* to reconfigure the AGC Config. The AGC config for a receiver type is set with the +* parameters passed by adi_adrv9025_AgcCfg_t agcConfig array. +* The arraySize conveyed the number of agcConfig passed in. +* +* The AGC configs can be broadcast / multicast based on the channel mask +* parameter in adi_adrv9025_AgcCfg_t structure. +* +* rxChannelMask | Rx Channels Programmed +* ---------------------------------|-------------------------------------- +* bit[0] = 1 | Enables Rx1 gain table programming +* ---------------------------------|-------------------------------------- +* bit[1] = 1 | Enables Rx2 gain table programming +* ---------------------------------|-------------------------------------- +* bit[2] = 1 | Enables Rx3 gain table programming +* ---------------------------------|-------------------------------------- +* bit[3] = 1 | Enables Rx4 gain table programming +* +* Eg: To program the same gain table to channels and Rx1, the rxChannelMask +* should be set to 0x00000001 +* +* Eg: To program a single gain table to all channels, the rxChannelMask +* should be set to 0x0000000F +* +* \pre This function is called only if AGC will be used, and only after the +* initialization process (ADI_ADRV9025_Initialize). +* The API function that sets the Rx gain control mode adi_adrv9025_RxGainCtrlModeSet +* needs to be called after setup to switch between MGC and AGCSLOW. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{agcConfig} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure containing settings +* \param agcConfig Array contain AgcCfg data structure containing settings +* \param arraySize Size of agcConfig Array. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_ERR_RESET_FEATURE Recovery action for user GPIO reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AgcCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AgcCfg_t agcConfig[], + uint8_t arraySize); + +/** +* \brief Checks the Range for the device Rx Automatic Gain Control (AGC) registers +* +* The instantiated AGC setting structure (adi_adrv9025_AgcCfg_t) must be initialized with +* valid settings before this function may be used due to the dependencies * +* +* This function called automatically as part of adi_adrv9025_AgcCfgSet() API +* if ADI_ADRV9025_AGC_RANGE_CHECK is set to 1. This function can be called independently +* for standalone range checking of Rx AGC Config Set functionality. +* +* +* \pre This function is called only if AGC will be used, and only after the +* initialization process (ADI_ADRV9025_Initialize) +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{agcConfig} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure containing settings +* \param agcConfig Array contain AgcCfg data structure containing settings +* \param arraySize Size of agcConfig Array. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_ERR_RESET_FEATURE Recovery action for user GPIO reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AgcCfgSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_AgcCfg_t agcConfig[], + uint8_t arraySize); + +/** +* \brief Gets the value of the AGC related registers from the ADRV9025 device. +* +* This function is used to get value of the AGC registers. +* +* \pre This function may be used only if AGC is active +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{agcConfig (most members)} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param rxChannel adi_adrv9025_RxChannels_e enum type to select Rx Channel. +* \param agcConfig Pointer to the agcCfg structure. Function will update values in the structure to return the current setup. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_ERR_RESET_FEATURE Recovery action for user GPIO reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AgcCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_AgcCfg_t* agcConfig); + +/** +* \brief This function will setup the AGC for the dualband mode. +* \brief Not currently implemented +* +* This function compliments the adi_adrv9025_AgcCfgSet() function to set up the +* AGC for the dualband mode. The function also sets up the GPIO's, +* to enable the device to control external LNA's. +* +* \pre This function may be used only if AGC is active. This function can be +* used in radio off state. Device must be initialized to dual band mode as +* a part of adi_adrv9025_Initialize() +* +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxAgcCtrlDualBand Pointer to the ADRV9025 AGC dualband settings data +* structure +* \param arraySize Size of Array. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_ERR_RESET_FEATURE Recovery action for user GPIO reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AgcDualBandCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AgcDualBandCfg_t rxAgcCtrlDualBand[], + uint8_t arraySize); + +/** +* \brief This function will get the AGC for the dualband mode. +* \brief Not currently implemented +* +* This function compliments the adi_adrv9025_AgcCfgGet() function to set up the +* AGC for the dualband mode. The function also sets up the GPIO's, +* to enable the device to control external LNA's. +* +* \pre This function may be used only if AGC is active. This function can be +* used in radio off state. Device must be initialized to dual band mode as +* a part of adi_adrv9025_Initialize() +* +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxChannel adi_adrv9025_RxChannels_e enum type to select either Rx1, Rx2, +* Rx1 + Rx2 for programming the dualband AGC. +* \param rxAgcCtrlDualBand Pointer to the ADRV9025 AGC dualband settings data +* structure +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_ERR_RESET_FEATURE Recovery action for user GPIO reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AgcDualBandCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_AgcDualBandCfg_t* rxAgcCtrlDualBand); + +/** +* \brief This function returns the current values of the LNA controls for the +* dualband mode. +* \brief Not currently implemented +* +* This function can be used if the user is not controlling the external LNA's +* through the 3.3V GPIO pins of the device. The LNA controls are programmed by +* the user in the dualband LNA gain table. The AGC then indexes to one of the +* entries in the table based on its algorithm. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxChannel adi_adrv9025_RxChannels_e enum type to select either Rx1 or Rx2 +* \param rxDualBandLnaControls Pointer to the AGC dualband LNA settings data +* structure +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_ERR_RESET_FEATURE Recovery action for user GPIO reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AgcDualBandLnaGpioOutGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_DualBandLnaCfg_t* rxDualBandLnaControls); + +/** +* \brief This function sets the min/max gain indexes for AGC for the specified channel. +* +* This function can be used to set the min/max gains of RX channel in runtime. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param agcGainRange Pointer to the ADRV9025 AGC dualband settings data +* structure +* \param arraySize Size of Array. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_ERR_RESET_FEATURE Recovery action for user GPIO reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AgcGainIndexRangeSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AgcGainRange_t agcGainRange[], + uint8_t arraySize); + +/** +* \brief This function sets the min/max gain indexes for AGC for the specified channel. +* +* This function can be used to set the min/max gains of RX channel in runtime. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxChannel adi_adrv9025_RxChannels_e enum type to select Rx for programming the dualband AGC. +* \param agcGainRange Pointer to the ADRV9025 AGC dualband settings data +* structure +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_ERR_RESET_FEATURE Recovery action for user GPIO reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AgcGainIndexRangeGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_AgcGainRange_t* agcGainRange); + +/** +* \brief This function resets all the state machines in the Gain Control Block. +* +* resets all state machines within the gain control block to state 0 +* and maximum gain (for slow, fast attack, and hybrid AGC loops) +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxChannelMask Maskbits from adi_adrv9025_RxChannels_e +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_ERR_RESET_FEATURE Recovery action for user GPIO reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AgcReset(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask); + +/** +* \brief This function will enable or disable the AGC Overload GPIO output +* +* Prerequisite: The AGC clock needs to be set to Slow Loop AGC Mode before adi_adrv9025_AgcOverloadIndicatorGpioSet is invoked +* +* The function will Iterate through GPIO pins 6 - 17 and acquire the shared resource +* Sets the direction of the pins to output +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param overloadEnable > 0 will enable the overload or to Disable Overload overloadEnable = 0 +* +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_ERR_RESET_FULL Recovery action for GPIO output, shared resource release or AGC mode failure +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AgcOverloadIndicatorGpioSet(adi_adrv9025_Device_t* device, + uint8_t overloadEnable); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_AGC_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_agc_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_agc_types.h new file mode 100644 index 0000000..ca73fa1 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_agc_types.h @@ -0,0 +1,166 @@ +/** +* \file adi_adrv9025_agc_types.h +* \brief Contains ADRV9025 API AGC data types +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_AGC_TYPES_H_ +#define _ADI_ADRV9025_AGC_TYPES_H_ + +#ifdef __cplusplus +extern +"C" + { +#endif + +#include + +/** +* \brief Data structure to hold AGC peak settings +* The evaluation software GUI for the product can be used to generate a structure with suggested settings. +*/ +typedef struct adi_adrv9025_AgcPeak +{ + uint16_t agcUnderRangeLowInterval; /*!< Update interval for AGC loop mode in AGC clock cycles. Valid range is 0 to 65535 */ + uint8_t agcUnderRangeMidInterval; /*!< 2nd update interval for multiple time constant AGC mode. Calculated as (agcUnderRangeMidInterval+1)*agcUnderRangeLowInterval_ns. Valid range is 0 to 63 */ + uint8_t agcUnderRangeHighInterval; /*!< 3rd update interval for multiple time constant AGC mode. Calculated as (agcUnderRangeHighInterval+1)*2nd update interval. Valid range is 0 to 63 */ + uint8_t apdHighThresh; /*!< AGC APD high threshold. Valid range is 0 to 63 */ + uint8_t apdLowGainModeHighThresh; /*!< AGC APD high threshold in low gain mode. Valid range is 0 to 63. Recommended to be 3dB above apdHighThresh */ + uint8_t apdLowThresh; /*!< AGC APD low threshold. Valid range is 0 to 63. Recommended to be 3dB below apdHighThresh */ + uint8_t apdLowGainModeLowThresh; /*!< AGC APD low threshold in low gain mode. Valid range is 0 to 63. Recommended to be 3dB above apdLowThresh */ + uint8_t apdUpperThreshPeakExceededCnt; /*!< AGC APD peak detect upper threshold count. Valid range is 0 to 255 */ + uint8_t apdLowerThreshPeakExceededCnt; /*!< AGC APD peak detect lower threshold count. Valid range is 0 to 255 */ + uint8_t apdGainStepAttack; /*!< AGC APD peak detect attack gain step. Valid range is 0 to 31 */ + uint8_t apdGainStepRecovery; /*!< AGC APD gain index step size for recovery. Valid range is 0 to 31 */ + uint8_t enableHb2Overload; /*!< Enable or disables the HB2 overload detector. */ + uint8_t hb2OverloadDurationCnt; /*!< Sets the window of clock cycles (at the HB2 output rate) to meet the overload count. (0 = 2 cycles, 1 = 4 cycles, 2 = 8 cycles, 3 = 12 cycles, 4 = 16 cycles, 5 = 24 cycles, 6 = 32 cycles) */ + uint8_t hb2OverloadThreshCnt; /*!< Sets the number of actual overloads required to trigger the overload signal. Valid range from 1 to 15 */ + uint16_t hb2HighThresh; /*!< AGC HB2 output high threshold. Valid range from 0 to 16383 */ + uint16_t hb2UnderRangeLowThresh; /*!< AGC HB2 output low threshold. Valid range from 0 to 16383 */ + uint16_t hb2UnderRangeMidThresh; /*!< AGC HB2 output low threshold for 2nd interval for multiple time constant AGC mode. Valid range from 0 to 16383 */ + uint16_t hb2UnderRangeHighThresh; /*!< AGC HB2 output low threshold for 3rd interval for multiple time constant AGC mode. Valid range from 0 to 16383 */ + uint8_t hb2UpperThreshPeakExceededCnt; /*!< AGC HB2 output upper threshold count. Valid range from 0 to 255 */ + uint8_t hb2UnderRangeHighThreshExceededCnt; /*!< AGC HB2 output lower threshold count. Valid range from 0 to 255 */ + uint8_t hb2GainStepHighRecovery; /*!< AGC HB2 gain index step size. Valid range from 0 to 31 */ + uint8_t hb2GainStepLowRecovery; /*!< AGC HB2 gain index step size, when the HB2 Low Overrange interval 2 triggers. Valid range from 0 to 31 */ + uint8_t hb2GainStepMidRecovery; /*!< AGC HB2 gain index step size, when the HB2 Low Overrange interval 3 triggers. Valid range from 0 to 31 */ + uint8_t hb2GainStepAttack; /*!< AGC HB2 output attack gain step. Valid range from 0 to 31 */ + uint8_t hb2OverloadPowerMode; /*!< When this bit is set, the dynamic range of the power measurement increases from -40dB to ~-60dB (that is, all signal levels from 0dBFS to -60dBFS are accurately detected */ + uint8_t hb2ThreshConfig; /*!< Not User Modifiable Initialized to 0x03 */ + uint8_t hb2UnderRangeMidThreshExceededCnt; /*!< AGC HB2 output upper threshold count. Valid range from 0 to 255 */ + uint8_t hb2UnderRangeLowThreshExceededCnt; /*!< AGC HB2 output lower threshold count. Valid range from 0 to 255 */ +} adi_adrv9025_AgcPeak_t; + +/** +* \brief Data structure to hold AGC power settings +* The evaluation software GUI for the product can be used to generate a structure with suggested settings. +*/ +typedef struct adi_adrv9025_AgcPower +{ + uint8_t powerEnableMeasurement; /*!< Enable the Rx power measurement block. (0/1) */ + uint8_t powerInputSelect; /*!< Use output of Rx for power measurement. 0: RFIR, 1: HB1, 2: HB2, 3:HB2. Valid Range from 0 to 3) */ + uint8_t underRangeHighPowerThresh; /*!< AGC power measurement detect lower 0 threshold. Valid Range from 0 to 127. */ + uint8_t underRangeLowPowerThresh; /*!< AGC power measurement detect lower 1 threshold. Valid offset from 0 to 31 */ + uint8_t underRangeHighPowerGainStepRecovery; /*!< AGC power measurement detect lower 0 recovery gain step. Valid range from 0 to 31 */ + uint8_t underRangeLowPowerGainStepRecovery; /*!< AGC power measurement detect lower 1 recovery gain step. Valid range from 0 to 31 */ + uint8_t powerMeasurementDuration; /*!< Average power measurement duration = 8*2^powerMeasurementDuration. Valid range from 0 to 31 */ + uint16_t rxTddPowerMeasDuration; /*!< Measurement duration to detect power for specific slice of the gain update counter. */ + uint16_t rxTddPowerMeasDelay; /*!< Measurement delay to detect power for specific slice of the gain update counter. */ + uint8_t overRangeHighPowerThresh; /*!< AGC upper 0 (overRangeHighPowerThreshold) threshold for power measurement. Valid Range from 0 to 127.*/ + uint8_t overRangeLowPowerThresh; /*!< AGC upper 1 (overRangeLowPowerThreshold) threshold for power measurement. Valid offset from 0 to 15 */ + uint8_t powerLogShift; /*!< Not User Modifiable Initialized to 0x01. Enable Increase in dynamic range of the power measurement from 40dB to ~60dB. Provides higher accuracy. */ + + uint8_t overRangeHighPowerGainStepAttack; /*!< AGC power measurement detect lower 0 attack gain step. Valid range from 0 to 31 */ + uint8_t overRangeLowPowerGainStepAttack; /*!< AGC power measurement detect lower 1 attack gain step. Valid range from 0 to 31 */ +} adi_adrv9025_AgcPower_t; + +/** +* \brief Data structure to hold all AGC configuration settings for initialization +* The evaluation software GUI for the product can be used to generate a structure with suggested settings. +*/ +typedef struct adi_adrv9025_AgcCfg +{ + uint32_t rxChannelMask; /*!< Channel mask of Rx channels to apply these settings to, or that settings were read from */ + uint8_t agcPeakWaitTime; /*!< AGC peak wait time. Valid range is from 0 to 31 */ + uint8_t agcRxMaxGainIndex; /*!< AGC Rx max gain index. Valid range is from 0 to 255 */ + uint8_t agcRxMinGainIndex; /*!< AGC Rx min gain index. Valid range is from 0 to 255 */ + uint32_t agcGainUpdateCounter; /*!< AGC gain update time in AGC clock cycles. Valid range is from 0 to 4194303*/ + uint8_t agcRxAttackDelay; /*!< On entering Rx, the Rx AGC is kept inactive for a period = agcRxAttackDelay*1us */ + uint8_t agcSlowLoopSettlingDelay; /*!< On any gain change, the AGC waits for the time (range 0 to 127) specified in AGC clock cycles to allow gain transients to flow through the Rx path before starting any measurements. */ + uint8_t agcLowThreshPreventGainInc; /*!< Prevent gain index from incrementing if peak thresholds are being exceeded */ + uint8_t agcChangeGainIfThreshHigh; /*!< Enable immediate gain change if high threshold counter is exceeded. Bit 0 enables ULB high threshold, Bit 1 enables HB2 high threshold */ + uint8_t agcPeakThreshGainControlMode; /*!< Enable gain change based only on the signal peak threshold over-ranges. Power based AGC changes are disabled in this mode. */ + uint8_t agcResetOnRxon; /*!< Reset the AGC slow loop state machine to max gain when the Rx Enable is taken low */ + uint8_t agcEnableSyncPulseForGainCounter; /*!< Enable the AGC gain update counter to be sync'ed to a time-slot boundary. */ + uint8_t agcEnableFastRecoveryLoop; /*!< Enable multiple time constants in AGC loop for fast attack and fast recovery. */ + uint8_t agcAdcResetGainStep; /*!< Indicates how much gain steps to reduce when a reset happens in the ADC. Typically larger (1-2dB) than the agc_ovrg_gain_step */ + uint8_t agcSlowloopFastGainChangeBlockEnable; /*!< Block change_gain_immediately for settling_delay cycles amount of time before gainupdate counter expired */ + adi_adrv9025_AgcPower_t agcPower; + adi_adrv9025_AgcPeak_t agcPeak; +} adi_adrv9025_AgcCfg_t; + +/** +* \brief Data structure to hold all AGC Dualband configuration. +* Used along with adi_adrv9025_RxChannels_e structure to setup AGC for Rx1 and/or Rx2 +*/ +typedef struct adi_adrv9025_AgcDualBandCfg +{ + uint32_t rxChannelMask; /*!< Channel mask of Rx channels to apply these settings to, or that settings were read from */ + uint8_t agcDualBandEnable; /*!< Enable AGC operation for dualband receiver */ + uint8_t agcRxDualbandExtTableUpperIndex; /*!< Rx1/2 AGC dual band operation - Indicates the gain table index below which the AGC prioritizes + decreasing gain through external LNA control over the Front-end gain */ + uint8_t agcRxDualbandExtTableLowerIndex; /*!< Rx1/2 AGC dual band operation - Indicates the gain table index above which the AGC prioritizes + increasing gain through external LNA control over the Front-end gain */ + uint8_t agcDualbandPwrMargin; /*!< Margin for comparing total power against power of individual bands. If + Total power > Upper Band Power + Lower Band Power +margin, the signal contains other components + than the two bands, and AGC should behave like a single band system. Margin is in 0.5db steps. */ + uint8_t agcDualbandLnaStep; /*!< Margin to compare Upper band power versus Lower band power + (for Upper Band Power > Lower Band Power + margin, and Lower Band Power > Upper Band Power + margin checks). + The margin compares the powers of the bands to change the LNA of one band so that powers of the bands match. + Value is in 0.5db resolution */ + uint8_t agcDualbandHighLnaThreshold; /*!< High threshold for Upper band or Lower band power above which the LNA index is decreased. + Value is in 0.5db */ + uint8_t agcDualbandLowLnaThreshold; /*!< Low threshold for Upper band or Lower band power below which the LNA index is increased. + Value is in 0.5db */ + uint8_t dualBandGpioEnable; /*!< Enable the 3.3V GPIO's that would be used to drive the external LNA's. + Rx1 : GPIO3.3[1:0] controls Lower band LNA, GPIO3.3[3:2] controls Upper band LNA + Rx2 : GPIO3.3[5:4] controls Lower band LNA, GPIO3.3[7:6] controls Upper band LNA + If disabled, user needs to use API function to read back the LNA control + value through the SPI. */ + uint8_t decPowerDdcMeasurementDuration; /*!< Power measurement duration for measuring the power of the individual bands. This variable has + a range of 0 to 31. The sampling period is calculated as = 8 x 2^decPowerDdcMeasurementDuration. */ +} adi_adrv9025_AgcDualBandCfg_t; + +/** +* \brief Data structure to hold AGC Dualband LNA controls for the external LNA's. +* Used along with adi_adrv9025_RxChannels_e structure to read back LNA controls for Rx1 or Rx2 +*/ +typedef struct adi_adrv9025_DualBandLnaCfg +{ + uint32_t rxChannelMask; /*!< Rx Channel that these settings were read from */ + uint8_t rxLowerBandLnaControl; /* The control value for the Rx1/2 Lower band LNA (Values 0-3) */ + uint8_t rxUpperBandLnaControl; /* The control value for the Rx1/2 Upper band LNA (Values 0-3) */ +} adi_adrv9025_DualBandLnaCfg_t; + +/** +* \brief Data structure to set/get the AGC min/max gain index for one or more Rx channels. +*/ +typedef struct adi_adrv9025_AgcGainRange +{ + uint32_t rxChannelMask; /*!< Channel mask of Rx channels to apply these settings to, or that settings were read from */ + uint8_t maxGainIndex; /*!< Max gain index the AGC can use */ + uint8_t minGainIndex; /*!< Min gain index the AGC can use */ +} adi_adrv9025_AgcGainRange_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_AGC_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_arm.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_arm.h new file mode 100644 index 0000000..6e64bdf --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_arm.h @@ -0,0 +1,501 @@ +/** + * \file adi_adrv9025_arm.h + * \brief Contains ADRV9025 ARM related function prototypes for adi_adrv9025_arm.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_ARM_H_ +#define _ADI_ADRV9025_ARM_H_ + +#include "adi_adrv9025_arm_types.h" +#include "adi_adrv9025_types.h" +#include "adi_common_error_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************** + * Initialization functions + **************************************************************************** + */ + +/** + * \brief Start the ARM processor + * + * Sets ARM Run = 1. Then wait and check for ARM FW Status. + * + * + * \pre This function is called after the device has been initialized and before multichip-sync + * (MCS) has been completed + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep{init-> (most members)} + * \dep_end + * + * \param device Pointer to the ADRV9025 device settings data structure + * \param init Pointer to the ADRV9025 initialization setting data structure + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_ArmStart(adi_adrv9025_Device_t* device, + const adi_adrv9025_Init_t* init); + +/** + * \brief Check the ARM processor Firmware Status. + * + * After ARM Run = 1, then wait and check for ARM FW Status. This function use a SPI read, + * and can not be use in a SPI write only (Broadcasting) mode. + * + * \pre This function is called after the device has been initialized and before multichip-sync + * (MCS) has been completed + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 device settings data structure + * \param timeout_us Timeout to stop waiting for ARM to boot up. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_ArmStartStatusCheck(adi_adrv9025_Device_t* device, + uint32_t timeout_us); + +/** + * \brief Writes the ADRV9025 ARM configuration settings + * + * \pre This function is called automatically during adi_adrv9025_ArmStart(), and + * this function must be called after loading the ARM firmware. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep{init-> (most members)} + * \dep_end + * + * \param device Pointer to the ADRV9025 device settings data structure + * \param init Pointer to the ADRV9025 initialization settings data structure + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_ArmProfileWrite(adi_adrv9025_Device_t* device, + const adi_adrv9025_Init_t* init); + +/** + * \brief Loads binary array into ARM program memory + * + * This function sets the ARM DMA control register bits for an ARM memory write, auto-incrementing + * the address. Valid memory addresses are: Program Memory (0x01018000 - 0x0104FFFF) + * + * The top level application reads the binary file, parsing it into any array, starting at the first data byte + * on the first line of the file. The array is passed to this function and writes it to ARM program memory. Any non-data + * bytes should be excluded from the binary array when parsing. + * + * \pre This function is called after the device has been initialized, PLL lock status has been verified, and + * the stream binary has been loaded + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 device data structure containing settings + * \param byteOffset Offset (starting from 0) of where to place the binary + * array in ARM memory (if loaded in multiple function + calls) + * \param binary Byte array containing all valid ARM file data bytes + * \param byteCount The number of bytes in the binary array + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_ArmImageWrite(adi_adrv9025_Device_t* device, + uint32_t byteOffset, + const uint8_t binary[], + uint32_t byteCount); + +/** + * \brief Loads the ADC profile data into ARM memory + * + * This function writes ADC profile into the ARM data memory before + * loading the ARM firmware. When the ARM firmware is loaded and begins + * to initialize, the ARM init sequence copies the ADC profiles from ARM + * memory and loads them into the ARM firmware internal data strucutures. + * + * \pre This function is called during device initialization after the ARM binary is loaded + * \pre adcProfiles should be initialized using adi_adrv9025_AdcProfilesInit, prior to this function being invoked + * + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 device settings data structure + * \param adcProfiles Pointer to the ADRV9025 ADC profile data structure + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_AdcProfilesWrite(adi_adrv9025_Device_t* device, + const adi_adrv9025_AdcProfiles_t* adcProfiles); + +/**************************************************************************** + * Runtime functions + **************************************************************************** + */ + +/**************************************************************************** + * Helper functions + **************************************************************************** + */ + +/** + * \brief Read from the ADRV9025 ARM program or data memory + * + * Valid memory addresses are: Program Memory (0x01018000 - 0x0104FFFF), + * Data Memory (0x20028000 - 0x2004FFFF). + * + * \pre This function is private and is not called directly by the user. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Structure pointer to the ADRV9025 data structure containing settings + * \param address The 32bit ARM address to read from. + * \param returnData Byte(uint8_t) array containing the data read from the ARM memory. + * \param byteCount Number of bytes in the returnData array. + * \param autoIncrement is boolean flag to enable or disable auto-increment of ARM register address + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_ArmMemRead(adi_adrv9025_Device_t* device, + uint32_t address, + uint8_t returnData[], + uint32_t byteCount, + uint8_t autoIncrement); + +/** + * \brief Write to the ADRV9025 ARM program or data memory + * + * Valid memory addresses are: Program Memory (0x01018000 - 0x0104FFFF), + * Data Memory (0x20028000 - 0x2004FFFF). + * + * \pre This function is private and is not called directly by the user. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Structure pointer to the ADRV9025 data structure containing settings + * \param address The 32-bit ARM address to write + * \param data Byte array (uint8_t) containing data to be written to ARM memory + * \param byteCount Number of bytes in the data array to be written + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_ArmMemWrite(adi_adrv9025_Device_t* device, + uint32_t address, + const uint8_t data[], + uint32_t byteCount); + +/** + * \brief Low level helper function used by ADRV9025 API to write the ARM memory config structures + * + * Normally this function should not be required to be used directly by the BBIC. This is a helper + * function used by other ADRV9025 API commands to write settings into the ARM memory. + * + * \pre This function is private and is not called directly by the user. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Structure pointer to the ADRV9025 data structure containing settings + * \param objectId ARM id of a particular structure or setting in ARM memory + * \param byteOffset Byte offset from the start of the objectId's memory location in ARM memory + * \param data A byte array containing data to write to the ARM memory buffer. + * \param byteCount Number of bytes in the data array (Valid size = 1-255 bytes) + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_ARM Recovery action for ARM reset required + * \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_ArmConfigWrite(adi_adrv9025_Device_t* device, + uint8_t objectId, + uint16_t byteOffset, + const uint8_t data[], + uint8_t byteCount); + +/** + * \brief Low level helper function used by ADRV9025 API to read the ARM memory config structures + * + * Normally this function should not be required to be used directly by the BBIC. This is a helper + * function used by other ADRV9025 API commands to read settings from the ARM memory. + * + * \pre This function is private and is not called directly by the user + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Structure pointer to the ADRV9025 data structure containing settings + * \param objectId ARM id of a particular structure or setting in ARM memory + * \param byteOffset Byte offset from the start of the objectId's memory location in ARM memory + * \param returnData A byte array containing data read back from the ARM memory buffer + * \param byteCount Number of bytes in the data array (Valid size = 1-255 bytes) + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required + * \retval ADI_ADRV9025_ACT_ERR_RESET_ARM Recovery action for ARM reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_ArmConfigRead(adi_adrv9025_Device_t* device, + uint8_t objectId, + uint16_t byteOffset, + uint8_t returnData[], + uint8_t byteCount); + +/** + * \brief Reads the ADRV9025 ARM 64-bit command status register and returns an error and status word + * + * A 64-bit status register consisting of a pending bit and three-bit error type is read one byte at + * a time for the first 16 even-numbered opcodes. The function parses the pending bits and error bits into + * two (2) separate 16-bit words. statusWord contains the status pending bits. errorWord contains + * a single error bit if the error type > 0 for any three-bit code. + * Each word is weighted according to the first 16 even-numbered opcodes where, + * 0x0001 = opcode '0', 0x0002 = opcode '2', 0x0004 = opcode '4', 0x0008 = opcode '6' and so on. + * + * \pre This function is private and is not called directly by the user. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Structure pointer to the ADRV9025 data structure containing settings + * \param errorWord 16-bit error word comprised of weighted bits according to first 16 even-numbered opcodes + * The weighted bit is set if any three-bit error type > 0, where '0' = OK + * \param statusWord 16-bit pending bits word comprised of weighted bits according to first 16 even-numbered opcodes + * The weighted bit is set if an opcode is pending, where '0' = no pending opcode + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + * + * TODO: Need to review number of error and status bits in SPI regs */ +int32_t adi_adrv9025_ArmCmdStatusGet(adi_adrv9025_Device_t* device, + uint16_t* errorWord, + uint16_t* statusWord); + +/** + * \brief Isolated byte read of the ADRV9025 ARM 64-bit command status register based on the opcode + * + * A single byte read is performed on the 64-bit command status register according to + * the opcode of interest. The pending bit and the error type are extracted from the status + * register and returned as a single byte in the lower nibble. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Structure pointer to the ADRV9025 data structure containing settings + * \param opCode Opcode of interest where only the first 16 even-numbered integers are valid + * \param cmdStatByte Comprised of cmdStatByte[3:1] = error type, cmdStatByte[0] = pending flag for opCode of interest + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + * + * TODO: Need to review number of bits SPI regs per opcode */ +int32_t adi_adrv9025_ArmCmdStatusOpcodeGet(adi_adrv9025_Device_t* device, + uint8_t opCode, + uint8_t* cmdStatByte); + +/** + * \brief ADRV9025 ARM command status wait function polls command status register until opcode of interest completes + * + * \pre ARM firmware load and initialization must take place first before attempting to use this function + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Structure pointer to the ADRV9025 data structure containing settings + * \param opCode Opcode of interest where only the first 16 even-numbered integers are valid + * \param cmdStatusByte Comprised of cmdStatByte[3:1] = error type, cmdStatByte[0] = pending flag for opCode of interest + * \param timeout_us Command time-out period in microseconds + * \param waitInterval_us Wait interval time to thread sleep between each check of the ARM command status to prevent SPI read thrashing + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_ARM Recovery action for ARM reset required + * \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + * + * TODO: Need to review number of bits SPI regs per opcode */ +int32_t adi_adrv9025_ArmCmdStatusWait(adi_adrv9025_Device_t* device, + uint8_t opCode, + uint8_t* cmdStatusByte, + uint32_t timeout_us, + uint32_t waitInterval_us); + +/** + * \brief Sends a command to the ADRV9025 ARM processor interface + * + * \pre This function can be called after initializing the ARM processor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Structure pointer to the ADRV9025 data structure containing settings + * \param opCode Opcode of interest where only the first 16 even-numbered integers are valid + * \param extendedData A byte array containing extended data to write to the ARM command interface + * \param byteCount Number of bytes in the extendedData array (Valid size = 0-4 bytes) + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_ARM Recovery action for ARM reset required + * \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_ArmCmdWrite(adi_adrv9025_Device_t* device, + uint8_t opCode, + const uint8_t extendedData[], + uint8_t byteCount); + +/**************************************************************************** + * Debug functions + **************************************************************************** + */ + +/** +* \brief Reads back the version of the ARM binary loaded into the ADRV9025 ARM memory +* +* This function reads the ARM memory to read back the major.minor.releaseCandidate +* version for the ARM binary loaded into ARM memory. +* +* Dependencies +* - device->spiSettings->chipSelectIndex +* +* \param device is structure pointer to the ADRV9025 data structure containing settings +* \param armVersion Arm version will be populated here, it is of struct type adi_adrv9025_ArmVersion_t. +* +* \retval ADRV9025_ERR_OK Function completed successfully +* \retval ADRV9025_ERR_GETARMVER_NULL_PARM One of the function parameters has a NULL pointer +*/ +int32_t adi_adrv9025_ArmVersionGet(adi_adrv9025_Device_t* device, + adi_adrv9025_ArmVersion_t* armVersion); + +/** + * \brief Verifies the ARM checksum value + * + * The checksum which is written into the binary file is verified with the calculated + * checksum in the ADRV9025 ARM after the binary file has been loaded. This function + * will wait for a timeout period for the checksum calculation to occur. The + * user can adjust the timeout period and SPI read interval in adi_adrv9025_user.c by + * adjusting the macros VERIFY_ARM_CHKSUM_TIMEOUTUS and + * VERIFY_ARM_CHKSUM_INTERVALUS. + * + * \pre This function is called after the ARM binary file has been loaded to verify it's + * checksum in ARM memory + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device is structure pointer to the ADRV9025 data structure containing settings + * \param checksum Pointer to adi_adrv9025_ChecksumTable_t data structure containing settings + * \param checksumValid Indicate if a valid checksum + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_ARM Recovery action for ARM reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_ArmChecksumTableGet(adi_adrv9025_Device_t* device, + adi_adrv9025_ChecksumTable_t* checksum, + uint8_t* checksumValid); + +/** + * \brief Reads Arm Mailbox Command Status + * + * This function reads Arm Mailbox Command Status from 'arm_command_busy' bit + * located in 'arm_command' register (0x00c3) + * + * \pre This function may be called any time after device initialization + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device is structure pointer to the ADRV9025 data structure containing settings + * \param mailboxBusy Pointer to byte containing mailbox busy status, 0:Arm is ready to accept a new command, 1:Arm is busy and cannot accept a new command + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_ArmMailboxBusyGet(adi_adrv9025_Device_t* device, + uint8_t* mailboxBusy); + +/** +* \brief Reads Arm System error message from ARM-C. +* +* \pre This function may be called any time after device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device is structure pointer to the ADRV9025 data structure containing settings +* \param errorMessage Pointer to character array containing the error message +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_ArmSystemErrorGet(adi_adrv9025_Device_t* device, + const char** errorMessage); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_ARM_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_arm_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_arm_types.h new file mode 100644 index 0000000..a07092a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_arm_types.h @@ -0,0 +1,73 @@ +/** + * \file adi_adrv9025_arm_types.h + * \brief Contains ADRV9025 ARM data types + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_ARM_TYPES_H_ +#define _ADI_ADRV9025_ARM_TYPES_H_ + +#include + +#ifdef __cplusplus +extern +"C" + { +#endif + +/** +* \brief Enumerated list of ARM bootup states. +*/ +typedef enum adi_adrv9025_ArmBootStates +{ + ADI_ADRV9025_ARMERR_BOOTUP_TIMEOUT_ERROR, /*!< Timed out waiting for ARM bootup to happen*/ + ADI_ADRV9025_ARMERR_BOOTUP_IDLE, /*!< ARM in IDLE mode after bootup*/ + ADI_ADRV9025_ARMERR_BOOTUP_RADIO_ON, /*!< ARM in RADIO_ON mode after bootup*/ + ADI_ADRV9025_ARMERR_BOOTUP_PROFILE_ERROR, /*!< ARM Profile error during bootup*/ + ADI_ADRV9025_ARMERR_BOOTUP_UNKNOWN_ERROR /*!< ARM unknown error during bootup*/ +} adi_adrv9025_ArmBootStates_e; + +/** +* \brief Enumerated list of ARM image build options. +*/ +typedef enum adi_adrv9025_ArmBuildType +{ + ADI_ADRV9025_ARMBUILD_RELEASE = 0, + ADI_ADRV9025_ARMBUILD_DEBUG = 1, + ADI_ADRV9025_ARMBUILD_TESTOBJ = 2 +} adi_adrv9025_ArmBuildType_e; + +/** +* \brief Data structure to ARM version information +*/ +typedef struct adi_adrv9025_ArmVersion +{ + uint8_t majorVer; + uint8_t minorVer; + uint8_t maintVer; + uint16_t rcVer; + adi_adrv9025_ArmBuildType_e armBuildType; +} adi_adrv9025_ArmVersion_t; + +/** +* \brief Data structure to hold ARM image build and runtime calculated checksums. +*/ +typedef struct adi_adrv9025_CpuChecksum adi_adrv9025_Checksum_t; + +/** +* \brief Data structure to hold a table of additional ARM checksums +*/ +typedef struct adi_adrv9025_CpuChecksumTable adi_adrv9025_ChecksumTable_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_ARM_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_cals.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_cals.h new file mode 100644 index 0000000..f0aff37 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_cals.h @@ -0,0 +1,898 @@ +/** + * \file adi_adrv9025_cals.h + * \brief Contains ADRV9025 calibration related function prototypes for + * adi_adrv9025_cals.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_CALS_H_ +#define _ADI_ADRV9025_CALS_H_ + +#include "adi_adrv9025_types.h" +#include "adi_adrv9025_cals_types.h" +#include "adi_adrv9025_tx_types.h" +#include "adi_adrv9025_rx_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************** + * Initialization functions + **************************************************************************** + */ + +/** + * \brief Runs the ADRV9025 initialization calibrations + * + * \pre This function is called after the device has been initialized, and the RF PLL has been + * verified to be locked + * + * calMask Bit | Calibration + * ------------|---------------------- + * 0 | Tx BB Filter + * 1 | ADC Tuner + * 2 | Rx TIA 3dB Corner + * 3 | Orx TIA 3dB Corner + * 4 | Loopback Rx TIA 3dB Corner + * 5 | Rx DC Offset + * 6 | Orx DC Offset + * 7 | Loopback Rx DC Offset + * 8 | Flash converter comparator + * 9 | Path delay equalization + * 10 | Internal Tx LO leakage + * 11 | External Tx LO leakage + * 12 | Tx quadrature error correction + * 13 | Loopback Rx LO delay path + * 14 | Loopback Rx quadrature error correction + * 15 | Rx LO delay path + * 16 | Rx quadrature error correction + * 17 | ORx LO delay path + * 18 | ORx quadrature error correction + * 19 | Tx DAC passband + * 20 | Digital Pre Distortion + * 21 | Closed Loop Gain Control + * 22 | Closed Loop Gain Control + * 23 | Harmonic Distortion + * 24 | Tx attenuation delay + * 25 | Tx Attenuation + * 26 | Rx gain delay + * 27 | Rx Gain and Phase + * [28-31] | Reserved + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + + * \param device A pointer to the device settings structure + * \param initCals A pointer to the InitCals structure which calibrations to run + * + * \retval ADI_ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADI_COMMON_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required + * \retval ADI_ADI_COMMON_ACT_ERR_RESET_ARM Recovery action for ARM reset required + * \retval ADI_ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_InitCalsRun(adi_adrv9025_Device_t* device, + adi_adrv9025_InitCals_t* initCals); + +/** + * \brief Blocking waits for the ADRV9025 initialization calibrations to complete + * + * \pre This function is called after adi_adrv9025_runInitCals to wait for them to finish + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device A pointer to the device settings structure + * \param timeoutMs A timeout value in milliseconds to wait for the calibrations to complete + * \param errorFlag A 3-bit error flag that helps identify any errors during Initial calibrations. + * A value of 0 indicates that there was no error. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset + * \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action for ARM reset required + * \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required + * \retval ADI_COMMON_ACT_ERR_RERUN_INIT_CALS Recovery action to re-run initialization calibrations + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_InitCalsWait(adi_adrv9025_Device_t* device, + uint32_t timeoutMs, + uint8_t* errorFlag); + +/** + * \brief Immediate initialization calibration completion check + * + * This function is similar to adi_adrv9025_waitInitCals except it does + * not block the thread waiting for the enabled init calibrations to complete. + * This function returns the initialization calibration status immediately + * allowing the application layer to do other work while the calibrations are + * running. + * + * The *errorFlag parameter is optional. If not used, pass a NULL parameter + * + * \pre This function is called after the initialization calibrations have been + * started + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device A pointer to the device settings structure + * + * \param areCalsRunning A pointer to a uint8_t return variable: Returns 1 if + * init cals are running, 0 = init cals are not running (either complete + * or have not started) + * + * \param errorFlag (Optional, pass NULL if unused) A pointer to a uint8_t + * return variable: 3-bit value which is the initialization + * calibration error code where 0 = No Error + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_ERR_RERUN_INIT_CALS Recovery action to re-run initialization calibrations + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_InitCalsCheckCompleteGet(adi_adrv9025_Device_t* device, + uint8_t* areCalsRunning, + uint8_t* errorFlag); + +/** + * \brief Aborts an on-going ARM initialization calibration sequence + * + * The ARM init calibrations can take several seconds. This function is called when + * the BBIC needs to intercede and stop the current initialization calibration sequence. + * The *calsCompleted uint32_t parameter is optional and will return the completed initialization calibration + * bit-mask before the abort command was received. If *calsCompleted is passed as a null pointer + * no value will be returned. + * + * \pre This function is called any time during the initialization calibration process + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device A pointer to the device settings structure + * \param calsCompleted A uint32_t pointer which is passed to obtain a bitmask + * which describes the initialization calibrations completed during the previous + * adi_adrv9025_runInitCals() function call + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required + * \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action for ARM reset required + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_InitCalsAbort(adi_adrv9025_Device_t* device, + uint32_t* calsCompleted); + +/** + * \brief Gets the device initialization calibration status + * + * This function provides updates to represent the status of the initialization calibrations + * calsSincePowerUp, calsLastRun are bit wise representations of calibration status. + * Each bit represents a calibration. adi_adrv9025_InitCalibrations_e defines the unique initialization + * calibration bit masks + * + * \pre This function may be called any time after the device has been initialized, and + * initialization calibrations have taken place + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device A pointer to the device settings structure + * \param initStatus Pointer passed to obtain init calibrations values. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required + * \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action for ARM reset required + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_InitCalsDetailedStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_InitCalStatus_t* initStatus); + +/**************************************************************************** + * Runtime functions + **************************************************************************** + */ + +/** + * \brief Enables or Disables Calibration Tracking. + * This API expects a 64 bit-mask, each bit in the mask controls one of the calibrations. + * The corresponding calibrations for the bits that are set to 1 will be enabled or disabled. + * 0s in the mask are ignored. enableDisableFlag parameter indicates the enable/disable operation. + * + * Example : To ENABLE TRACKING_CAL_RX1_QEC and TRACKING_CAL_TX1_QEC + * This API should be called with + * mask = 0x0101, enableDisableFlag = ADI_ADRV9025_TRACKING_CAL_ENABLE + * To DISABLE TRACKING_CAL_RX1_QEC and TRACKING_CAL_TX1_QEC + * This API should be called with + * mask = 0x0101, enableDisableFlag = ADI_ADRV9025_TRACKING_CAL_DISABLE + * + * Note: Observe that the mask can be same to enable and disable calibrations, + * the enableDisableFlag should be used to indicate whether user wants to enable or disable. + * + * + * Bits | Corresponding Calibration + * [64 bits] | + * ---------------------------------------- + * 0 | TRACKING_CAL_RX1_QEC + * 1 | TRACKING_CAL_RX2_QEC + * 2 | TRACKING_CAL_RX3_QEC + * 3 | TRACKING_CAL_RX4_QEC + * 4 | TRACKING_CAL_ORX1_QEC + * 5 | TRACKING_CAL_ORX2_QEC + * 6 | TRACKING_CAL_ORX3_QEC + * 7 | TRACKING_CAL_ORX4_QEC + * 8 | TRACKING_CAL_TX1_LOL + * 9 | TRACKING_CAL_TX2_LOL + * 10 | TRACKING_CAL_TX3_LOL + * 11 | TRACKING_CAL_TX4_LOL + * 12 | TRACKING_CAL_TX1_QEC + * 13 | TRACKING_CAL_TX2_QEC + * 14 | TRACKING_CAL_TX3_QEC + * 15 | TRACKING_CAL_TX4_QEC + * 16 | TRACKING_CAL_TX1_DPD + * 17 | TRACKING_CAL_TX2_DPD + * 18 | TRACKING_CAL_TX3_DPD + * 19 | TRACKING_CAL_TX4_DPD + * 20 | TRACKING_CAL_TX1_CLGC + * 21 | TRACKING_CAL_TX2_CLGC + * 22 | TRACKING_CAL_TX3_CLGC + * 23 | TRACKING_CAL_TX4_CLGC + * 24 | TRACKING_CAL_TX1_VSWR + * 25 | TRACKING_CAL_TX2_VSWR + * 26 | TRACKING_CAL_TX3_VSWR + * 27 | TRACKING_CAL_TX4_VSWR + * 28 | TRACKING_CAL_RX1_HD2 + * 29 | TRACKING_CAL_RX2_HD2 + * 30 | TRACKING_CAL_RX3_HD2 + * 31 | TRACKING_CAL_RX4_HD2 + * 32 | TRACKING_CAL_SERDES + * 33-64 | Reserved + * + * If the cal mask corresponding to an uninitialized Tx/Rx/ORx channel is set, this function automatically + * clears the cal mask before commanding the ARM to enable/disable the requested cals + * + * \pre This command must be called after a full device initialization + * has taken place, all PLLs are configured and locked, Multi-Chip Sync (MCS) has taken place, and the JESD204B + * links are configured and operational. + * + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the device settings structure + * \param enableMask The 64 bit-mask to enable/ disable calibration. + * \param enableDisableFlag to indicate whether the mask is to be used to enable or disable. + * Possible values are ADI_ADRV9025_TRACKING_CAL_ENABLE or ADI_ADRV9025_TRACKING_CAL_DISABLE + * from adi_adrv9025_TrackingCalEnableDisable_e + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action for user ARM reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_TrackingCalsEnableSet(adi_adrv9025_Device_t* device, + uint64_t enableMask, + adi_adrv9025_TrackingCalEnableDisable_e enableDisableFlag); + +/** +* \brief Reads back which ARM tracking cals are enabled. +* In the returned 64 bit-mask, each bit represents enable/disable state of one of the calibrations. +* state can be interpreted as 1 = enabled and 0 = disabled. +* +* \pre This command is called after a full device initialization to determine +* which tracking cals are enabled. The ARM must be loaded and init cals +* run before this command can be called. +* +* Bits | Corresponding Calibration +* [32 bits] | +* ---------------------------------------- +* 0 | TRACKING_CAL_RX1_QEC +* 1 | TRACKING_CAL_RX2_QEC +* 2 | TRACKING_CAL_RX3_QEC +* 3 | TRACKING_CAL_RX4_QEC +* 4 | TRACKING_CAL_ORX1_QEC +* 5 | TRACKING_CAL_ORX2_QEC +* 6 | TRACKING_CAL_ORX3_QEC +* 7 | TRACKING_CAL_ORX4_QEC +* 8 | TRACKING_CAL_TX1_LOL +* 9 | TRACKING_CAL_TX2_LOL +* 10 | TRACKING_CAL_TX3_LOL +* 11 | TRACKING_CAL_TX4_LOL +* 12 | TRACKING_CAL_TX1_QEC +* 13 | TRACKING_CAL_TX2_QEC +* 14 | TRACKING_CAL_TX3_QEC +* 15 | TRACKING_CAL_TX4_QEC +* 16 | TRACKING_CAL_TX1_DPD +* 17 | TRACKING_CAL_TX2_DPD +* 18 | TRACKING_CAL_TX3_DPD +* 19 | TRACKING_CAL_TX4_DPD +* 20 | TRACKING_CAL_TX1_CLGC +* 21 | TRACKING_CAL_TX2_CLGC +* 22 | TRACKING_CAL_TX3_CLGC +* 23 | TRACKING_CAL_TX4_CLGC +* 24 | TRACKING_CAL_TX1_VSWR +* 25 | TRACKING_CAL_TX2_VSWR +* 26 | TRACKING_CAL_TX3_VSWR +* 27 | TRACKING_CAL_TX4_VSWR +* 28 | TRACKING_CAL_RX1_HD2 +* 29 | TRACKING_CAL_RX2_HD2 +* 30 | TRACKING_CAL_RX3_HD2 +* 31 | TRACKING_CAL_RX4_HD2 +* 32 | TRACKING_CAL_SERDES +* 33-64 | Reserved +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param enableMask Pointer to single uint64_t variable that returns a bitmask +* that shows which tracking cals are enabled. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action for user ARM reset required +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Check enableMask pointer for null value +*/ +int32_t adi_adrv9025_TrackingCalsEnableGet(adi_adrv9025_Device_t* device, + uint64_t* enableMask); + +/** +* \brief Returns the status of the Deserializer tracking calibration +* +* The function can be called to read back the status of the Deserializer +* calibration including metrics like error codes, percentage of data +* collected for current cal, the performance of the cal and the number of +* times the cal has run and updated the hardware. The varianceMetric is not currently +* applicable for this tracking cal. +* +* \pre Before the function is called, the device must be initialized, the ARM +* loaded, and init cals run. +* +* \param device Pointer to the device settings structure +* \param desLane The deserializer lane whose status is to be read back +* \param desStatus Status of the Deserializer tracking cal, as a structure +* of type adi_adrv9025_DesTrackingCalStatus_t is returned to this pointer address +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TrackingCalDeserializerStatusGet(adi_adrv9025_Device_t* device, + uint8_t desLane, + adi_adrv9025_DesTrackingCalStatus_t* desStatus); + +/** + * \brief Returns the status of the TxLOL external tracking calibration + * + * The function can be called to read back the status of the TxLOL external + * calibration including metrics like error codes, percentage of data + * collected for current cal, the performance of the cal and the number of + * times the cal has run and updated the hardware. + * + * \pre Before the function is called, the device must be initialized, the ARM + * loaded, and init cals run. + * + * \param device Pointer to the device settings structure + * \param txChannel The channel (Tx1/Tx2/Tx3/Tx4) whose status is to be read back + * \param txLolStatus Status of the TxLOL external calibration, as a structure + * of type adi_adrv9025_TxLolStatus_t is returned to this pointer address + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_TrackingCalTxLolStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxLolStatus_t* txLolStatus); + +/** + * \brief Returns the status of the TxQEC tracking calibration + * + * The function can be called to read back the status of the TxQEC + * calibration including metrics like error codes, percentage of data + * collected for current cal, the performance of the cal and the number of + * times the cal has run and updated the hardware. + * + * \pre Before the function is called, the device must be initialized, the ARM + * loaded, and init cals run. + * + * \param device Pointer to the device settings structure + * \param txChannel The channel (Tx1/Tx2) whose status is to be read back + * \param txQecStatus Status of the TxQEC external calibration, as a structure + * of type adi_adrv9025_TxQecStatus_t is returned to this pointer address + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_TrackingCalTxQecStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxQecStatus_t* txQecStatus); + +/** + * \brief Returns the status of the RxQEC tracking calibration + * + * The function can be called to read back the status of the RxQEC external + * calibration including metrics like error codes, percentage of data + * collected for current cal, the performance of the cal and the number of + * times the cal has run and updated the hardware. + * + * \pre Before the function is called, the device must be initialized, the ARM + * loaded, and init cals run. + * + * \param device Pointer to the device settings structure + * \param rxChannel The channel (Rx1/Rx2/Rx3/Rx4) whose status is to be read back + * \param rxQecStatus Status of the RxQEC calibration, as a structure + * of type adi_adrv9025_RxQecStatus_t is returned to this pointer address + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_TrackingCalRxQecStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxQecStatus_t* rxQecStatus); + +/** +* \brief Returns the status of the ORxQEC tracking calibration +* +* The function can be called to read back the status of the ORxQEC external +* calibration including metrics like error codes, percentage of data +* collected for current cal, the performance of the cal and the number of +* times the cal has run and updated the hardware. +* +* \pre Before the function is called, the device must be initialized, the ARM +* loaded, and init cals run. +* +* \param device Pointer to the device settings structure +* \param orxChannel The channel (Orx1/Orx2/Orx3/Orx4) whose status is to be read back +* \param orxQecStatus Status of the ORxQEC external calibration, as a structure +* of type adi_adrv9025_RxQecStatus_t is returned to this pointer address +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TrackingCalOrxQecStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e orxChannel, + adi_adrv9025_OrxQecStatus_t* orxQecStatus); + +/** +* \brief Returns the status of the CLGC tracking calibration +* +* The function can be called to read back the status of the CLGC tracking +* calibration including metrics like error codes, percentage of data +* collected for current cal, the performance of the cal and the number of +* times the cal has run and updated the hardware. +* +* \pre Before the function is called, the device must be initialized, the ARM +* loaded, and init cals run. +* +* \param device Pointer to the device settings structure +* \param txChannel The channel (Tx1/Tx2/Tx3/Tx4) whose status is to be read back +* \param clgcStatus Status of the CLGC tracking calibration, as a structure +* of type adi_adrv9025_ClgcStatus_t is returned to this pointer address +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TrackingCalClgcStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_ClgcTrackingCalStatus_t* clgcStatus); + +/** + * \brief Returns the status of the RxHd2 tracking calibration + * + * The function can be called to read back the status of the RxHd2 external + * calibration including metrics like error codes, percentage of data + * collected for current cal, Confidence level that cal has accurately identified + * the coefficient required to cancel HD2 and the number of times the cal has + * run and updated the hardware. + * + * \pre Before the function is called, the device must be initialized, the ARM + * loaded, and init cals run. + * + * \param device Pointer to the device settings structure + * \param rxChannel The channel (Rx1/Rx2/Rx3/Rx4) whose status is to be read back + * \param rxHd2Status Status of the RxHd2 calibration, as a structure + * of type adi_adrv9025_RxHd2Status_t is returned to this pointer address + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_TrackingCalRxHd2StatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxHd2Status_t* rxHd2Status); + +/** + * \brief Allows setting configuration options for ADRV9025 Rx HD2 tracking calibration + * + * Set hd2CalConfig->posSideBandSel to the side (negative - lower side band or + * positive - upper side band) that has the desired + * signal. Correction will be correcting the 2nd harmonic distortion on the + * same side of the spectrum. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 device data structure containing settings + * \param hd2CalConfig Pointer to HD2 calibration config structure with desired settings + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action if ARM is detected to be in wrong state + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_TrackingCalRxHd2CfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxHd2Config_t* hd2CalConfig); + +/** + * \brief Allows reading configuration options for ADRV9025 Rx HD2 tracking calibration from + * ADRV9025 ARM memory + * + * Config values are read from the ADRV9025 ARM memory and returned at the address of + * the hd2CalConfig function parameter. + * + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 device data structure containing settings + * \param hd2CalConfig Pointer to HD2 calibration config structure to return read settings + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action if ARM is detected to be in wrong state + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_TrackingCalRxHd2CfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxHd2Config_t* hd2CalConfig); + +/** +* \brief Allows reading the current state of all calibrations. +* The possible states for each calibration depending on the returned value are +* +* BIT Number | STATE | Description +* ------------------------------------------------------------------------------ +* 0 | SUSPENDED | Cal is temporarily suspended by the framework. +* 1 | RESUMED | Cal is resumed for running. +* 2 | INACTIVE | Cal's Main function is not executing +* 3 | RUNNING | Cal's Main function is executing +* 4 | ENABLED | Cal is enabled +* 5 | DISABLED | Cal is disabled +* 6 | ERROR | Cal has generated error. It may be suspended from running. +* | | BBIC should re-run the cal. +* +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param calState Pointer to Tracking calibration state structure to store the read values. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action if ARM is detected to be in wrong state +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TrackingCalAllStateGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TrackingCalState_t* calState); + +/** +* \brief Configures the Tx-ORx path delay used to align Tx and ORx samples +* +* This function allows the user to manually overwrite the Tx-ORx external path delay +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \pre This function may be called any time after device initialization. +* +* \note If the Tx-ORx external routing is not the same as default Tx-ORx mapping, then the user will have to +* call the API adi_adrv9025_TxToOrxMappingSet() in pin mode or switch the appropriate GPIO pins +* in a GPIO Tx to ORx mapping control mode before executing this API in order to convey the +* Tx-ORx mapping to the ADRV9025 firmware. +* +* \param device Pointer to the device settings structure +* \param txChannel Target Tx channel for which the Tx-ORx path delay is required to be configured +* \param externalPathDelay Structure consisting of the path delay settings to be configured +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADI_COMMON_ACT_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_ExternalPathDelaySet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_ExternalPathDelay_t* externalPathDelay); + +/** +* \brief Retrieves the current Tx-ORx path delay value used to align Tx and ORx samples +* +* This function returns the current Tx-ORx external path delay calibrated by the ARM or written manually by the user +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \pre This function may be called any time after device initialization and the path delay init cal has run. +* +* \param device Pointer to the device settings structure +* \param txChannel Target Tx channel for which the Tx-ORx path delay is required to be configured +* \param externalPathDelay Structure consisting of the path delay settings to be configured +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADI_COMMON_ACT_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_ExternalPathDelayGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_ExternalPathDelay_t* externalPathDelay); + +/** +* \brief Configures the supplied mShift value (0-31) to the supplied channel selection. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \pre This function may be called any time after device initialization. +* +* \param device Pointer to the device settings structure +* \param dcOffSetMShift structure containing mShift channel and value +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADI_COMMON_ACT_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DigDcOffsetMShiftSet(adi_adrv9025_Device_t* device, + adi_adrv9025_DcOffSet_t dcOffSetMShift); + +/** +* \brief Retrieves the mShift value for the supplied channel selection. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \pre This function may be called any time after device initialization. +* +* \param device Pointer to the device settings structure +* \param dcOffSetMShift pointer to the structure where the mShift value +* is returned for the supplied channel selection. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADI_COMMON_ACT_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DigDcOffsetMShiftGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DcOffSet_t* dcOffSetMShift); + +/** +* \brief Sets the Enable/Disable Digital DC Offset using the adi_adrv9025_DcOffsetChannels_e to +* construct as channel mask. +* The mask can be a combination of the following channel values ( ::adi_adrv9025_DcOffsetChannels_e ). +* +* Channel | Value | Channel description +* ----------------------------------------------|-----------|-------------------------- +* ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH0 | 0x0001 | MShift and DcOffset RX channel0 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH1 | 0x0002 | MShift and DcOffset RX channel1 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH2 | 0x0004 | MShift and DcOffset RX channel2 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH3 | 0x0008 | MShift and DcOffset RX channel3 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX_CH0 | 0x0010 | MShift and DcOffset ORX channel0 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX_CH1 | 0x0020 | MShift and DcOffset ORX channel1 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX2_CH0 | 0x0040 | MShift and DcOffset ORX2 mode channel0 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX2_CH1 | 0x0080 | MShift and DcOffset ORX2 mode channel1 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK1_CH0 | 0x0100 | MShift and DcOffset ORX LpBack1 channel0 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK1_CH1 | 0x0200 | MShift and DcOffset ORX LpBack1 channel1 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK2_CH0 | 0x0400 | MShift and DcOffset ORX LpBack2 channel0 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK2_CH1 | 0x0400 | MShift and DcOffset ORX LpBack2 channel0 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ALL_CHANNELS | 0x0FFF | MShift and DcOffset All Channels selected +* +* Dependencies +* - device->spiSettings->chipSelectIndex +* +* \param device Pointer to the device settings structure +* \param channelDisableEnableMask with bits of channels to be enabled if set and disabled if cleared. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADI_COMMON_ACT_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DigDcOffsetEnableSet(adi_adrv9025_Device_t* device, + uint16_t channelDisableEnableMask); + +/** +* \brief Returns Enable/Disable Digital DC Offset mask representing the enable/disable status of each +* digital DC Offset channel where a 0 is disabled and a 1 is disable using the following channel mapping: +* +* Channel | Value | Channel description +* ----------------------------------------------|-----------|-------------------------- +* ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH0 | 0x0001 | MShift and DcOffset RX channel0 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH1 | 0x0002 | MShift and DcOffset RX channel1 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH2 | 0x0004 | MShift and DcOffset RX channel2 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH3 | 0x0008 | MShift and DcOffset RX channel3 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX_CH0 | 0x0010 | MShift and DcOffset ORX channel0 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX_CH1 | 0x0020 | MShift and DcOffset ORX channel1 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX2_CH0 | 0x0040 | MShift and DcOffset ORX2 mode channel0 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX2_CH1 | 0x0080 | MShift and DcOffset ORX2 mode channel1 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK1_CH0 | 0x0100 | MShift and DcOffset ORX LpBack1 channel0 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK1_CH1 | 0x0200 | MShift and DcOffset ORX LpBack1 channel1 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK2_CH0 | 0x0400 | MShift and DcOffset ORX LpBack2 channel0 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK2_CH1 | 0x0400 | MShift and DcOffset ORX LpBack2 channel0 select +* ADI_ADRV9025_MSHIFT_DC_OFFSET_ALL_CHANNELS | 0x0FFF | MShift and DcOffset All Channels selected +* +* Dependencies +* - device->spiSettings->chipSelectIndex +* +* \param device Pointer to the device settings structure +* \param channelDisableEnableMask point with bits representing the enable/disable status of each channel. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADI_COMMON_ACT_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DigDcOffsetEnableGet(adi_adrv9025_Device_t* device, + uint16_t* channelDisableEnableMask); + +/** +* \brief Resets the External Tx LO Leakage estimate for the specified channel mask with two types of reset, +* Hard reset and Soft reset. +* +* Both reset types resets the perturbation scaler, clears accumulated RX and TX values, sets fast attack=1 to force a fast attack +* and applies the measurements more strongly. +* +* Hard reset erases the TxLOL look-up table. The look-up table keeps the correction values for all 64 attenuation values. +* Soft reset restarts the TxLOL estimation without erasing the TxLOL look-up table. +* +* \param device Pointer to the device settings structure +* \param txLolReset Pointer to structure containing channel mask and reset type +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADI_COMMON_ACT_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_ExtTxLolChannelReset(adi_adrv9025_Device_t* device, + adi_adrv9025_ExtTxLolChannelReset_t* txLolReset); + +/** +* \brief Sets the switching time between LO1/2 to auxLO, that occurs when dual band is enabled during tracking cals +* +* \param device Pointer to the device settings structure +* \param milliseconds variable which defines the new switching time in milliseconds +* +* Min and Max Values are defined in adi_adrv9025_cals_types.h as ADI_ADRV9025_SWITCH_TIME_MIN and ADI_ADRV9025_SWITCH_TIME_MAX +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADI_COMMON_ACT_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DualBandSwitchingTimeSet(adi_adrv9025_Device_t* device, + uint32_t milliseconds); + +/** +* \brief Gets the switching time between LO1/2 to auxLO, that occurs when dual band is enabled during tracking cals +* +* \param device Pointer to the device settings structure +* \param milliseconds pointer variable which we use to store the time read back from Firmware +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADI_COMMON_ACT_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DualBandSwitchingTimeGet(adi_adrv9025_Device_t* device, + uint32_t* milliseconds); + + + +/** +* \brief Configures the Tx-ORx path delay used to align Tx and ORx samples +* +* This function allows the user to manually overwrite the Tx-ORx external CLGC path delay +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \pre This function may be called any time after device initialization. +* +* \note If the Tx-ORx external routing is not the same as default Tx-ORx mapping, then the user will have to +* call the API adi_adrv9025_TxToOrxMappingSet() in pin mode or switch the appropriate GPIO pins +* in a GPIO Tx to ORx mapping control mode before executing this API in order to convey the +* Tx-ORx mapping to the ADRV9025 firmware. +* +* \param device Pointer to the device settings structure +* \param txChannel Target Tx channel for which the Tx-ORx external CLGC path delay is required to be configured +* \param externalPathDelay Structure consisting of the path delay settings to be configured +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADI_COMMON_ACT_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_ClgcExternalPathDelaySet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_ExternalPathDelay_t* externalPathDelay); + +/** +* \brief Retrieves the current Tx-ORx CLGC path delay value used to align Tx and ORx samples +* +* This function returns the current Tx-ORx external CLGC path delay calibrated by the ARM or written manually by the user +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \pre This function may be called any time after device initialization and the path delay init cal has run. +* +* \param device Pointer to the device settings structure +* \param txChannel Target Tx channel for which the Tx-ORx CLGC external path delay is required to be configured +* \param externalPathDelay Structure consisting of the path delay settings to be configured +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADI_COMMON_ACT_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_ClgcExternalPathDelayGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_ExternalPathDelay_t* externalPathDelay); +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_CALS_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_cals_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_cals_types.h new file mode 100644 index 0000000..f50a1af --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_cals_types.h @@ -0,0 +1,598 @@ +/** + * \file adi_adrv9025_cals_types.h + * \brief Contains ADRV9025 API Calibration data types + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_CALS_TYPES_H_ +#define _ADI_ADRV9025_CALS_TYPES_H_ + +#define ARMINITCAL_ERRCODE(armCalId, armCalErrCode) ((armCalId << 8) | armCalErrCode) + +#define ADI_ADRV9025_SWITCH_TIME_MIN 1000 +#define ADI_ADRV9025_SWITCH_TIME_MAX 3000 + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * \brief Enum to select desired InitCals select bits in the initCalMask. + */ +typedef enum adi_adrv9025_InitCalibrations +{ + ADI_ADRV9025_TX_BB_FILTER = 0x00000001U, /*!< Tx BB filter calibration */ + ADI_ADRV9025_ADC_TUNER = 0x00000002U, /*!< ADC tuner calibration */ + ADI_ADRV9025_RX_TIA = 0x00000004U, /*!< Rx TIA 3dB corner calibration */ + ADI_ADRV9025_ORX_TIA = 0x00000008U, /*!< ORx TIA 3dB corner calibration */ + ADI_ADRV9025_LBRX_TIA = 0x00000010U, /*!< Loopback Rx TIA 3dB corner calibration */ + ADI_ADRV9025_RX_DC_OFFSET = 0x00000020U, /*!< Rx DC offset calibration */ + ADI_ADRV9025_ORX_DC_OFFSET = 0x00000040U, /*!< ORx DC offset calibration */ + ADI_ADRV9025_LBRX_DC_OFFSET = 0x00000080U, /*!< LBRx DC offset calibration */ + ADI_ADRV9025_FLASH_CAL = 0x00000100U, /*!< Flash converter comparator calibration */ + ADI_ADRV9025_INTERNAL_PATH_DELAY = 0x00000200U, /*!< Internal Path Delay calibration */ + ADI_ADRV9025_TX_LO_LEAKAGE_INTERNAL = 0x00000400U, /*!< Internal Tx LO leakage calibration */ + ADI_ADRV9025_TX_LO_LEAKAGE_EXTERNAL = 0x00000800U, /*!< External Tx LO leakage calibration */ + ADI_ADRV9025_TX_QEC_INIT = 0x00001000U, /*!< Tx quadrature error correction calibration */ + ADI_ADRV9025_LOOPBACK_RX_LO_DELAY = 0x00002000U, /*!< Loopback Rx LO delay path calibration */ + ADI_ADRV9025_LOOPBACK_RX_RX_QEC_INIT = 0x00004000U, /*!< Loopback Rx quadrature error correction calibration */ + ADI_ADRV9025_RX_LO_DELAY = 0x00008000U, /*!< Rx LO delay path calibration */ + ADI_ADRV9025_RX_QEC_INIT = 0x00010000U, /*!< Rx quadrature error correction calibration */ + ADI_ADRV9025_ORX_LO_DELAY = 0x00020000U, /*!< ORx LO delay path calibration */ + ADI_ADRV9025_ORX_QEC_INIT = 0x00040000U, /*!< ORx quadrature error correction calibration */ + ADI_ADRV9025_TX_DAC = 0x00080000U, /*!< Tx DAC passband calibration */ + ADI_ADRV9025_DPD = 0x00100000U, /*!< Digital Pre Distortion init calibration */ + ADI_ADRV9025_EXTERNAL_PATH_DELAY = 0x00200000U, /*!< External Tx-ORx Path delay equalization calibration */ + ADI_ADRV9025_VSWR = 0x00400000U, /*!< Voltage Standing Wave Ratio calibration */ + ADI_ADRV9025_HD2 = 0x00800000U, /*!< Second Harmonic Distortion calibration */ + ADI_ADRV9025_TX_ATTENUATION_DELAY = 0x01000000U, /*!< Tx attenuation delay calibration */ + ADI_ADRV9025_TX_ATTEN_TABLE = 0x02000000U, /*!< Tx Attenuation Calibration */ + ADI_ADRV9025_RX_GAIN_DELAY = 0x04000000U, /*!< Rx gain delay calibration */ + ADI_ADRV9025_RX_GAIN_PHASE = 0x08000000U, /*!< Rx Gain and Phase calibration */ + ADI_ADRV9025_CFR_INIT = 0x20000000U, /*!< Crest Factor Reduction init calibration */ + ADI_ADRV9025_SERDES_INIT = 0x40000000U, /*!< SERDES init cal */ + ADI_ADRV9025_MAX_INIT_CAL_MASK = 0x6FFFFFFFU /*!< Maximum Value of initcal mask */ +} adi_adrv9025_InitCalibrations_e; + +/** + * \brief Constants to select desired TrackingCals select bits in the trackingCalMask. + */ + +#define ADI_ADRV9025_TRACK_NONE 0x0000000000000000 /*!< Disable all tracking calibrations */ +#define ADI_ADRV9025_TRACK_RX1_QEC 0x0000000000000001 /*!< Rx1 quadrature error correction tracking calibration */ +#define ADI_ADRV9025_TRACK_RX2_QEC 0x0000000000000002 /*!< Rx2 quadrature error correction tracking calibration */ +#define ADI_ADRV9025_TRACK_RX3_QEC 0x0000000000000004 /*!< Rx3 quadrature error correction tracking calibration */ +#define ADI_ADRV9025_TRACK_RX4_QEC 0x0000000000000008 /*!< Rx4 quadrature error correction tracking calibration */ +#define ADI_ADRV9025_TRACK_ORX1_QEC 0x0000000000000010 /*!< ORx1 quadrature error correction tracking calibration */ +#define ADI_ADRV9025_TRACK_ORX2_QEC 0x0000000000000020 /*!< ORx2 quadrature error correction tracking calibration */ +#define ADI_ADRV9025_TRACK_ORX3_QEC 0x0000000000000040 /*!< ORx3 quadrature error correction tracking calibration */ +#define ADI_ADRV9025_TRACK_ORX4_QEC 0x0000000000000080 /*!< ORx4 quadrature error correction tracking calibration */ +#define ADI_ADRV9025_TRACK_TX1_LOL 0x0000000000000100 /*!< Tx1 LO leakage tracking calibration */ +#define ADI_ADRV9025_TRACK_TX2_LOL 0x0000000000000200 /*!< Tx2 LO leakage tracking calibration */ +#define ADI_ADRV9025_TRACK_TX3_LOL 0x0000000000000400 /*!< Tx3 LO leakage tracking calibration */ +#define ADI_ADRV9025_TRACK_TX4_LOL 0x0000000000000800 /*!< Tx4 LO leakage tracking calibration */ +#define ADI_ADRV9025_TRACK_TX1_QEC 0x0000000000001000 /*!< Tx1 quadrature error correction tracking calibration */ +#define ADI_ADRV9025_TRACK_TX2_QEC 0x0000000000002000 /*!< Tx2 quadrature error correction tracking calibration */ +#define ADI_ADRV9025_TRACK_TX3_QEC 0x0000000000004000 /*!< Tx3 quadrature error correction tracking calibration */ +#define ADI_ADRV9025_TRACK_TX4_QEC 0x0000000000008000 /*!< Tx4 quadrature error correction tracking calibration */ +#define ADI_ADRV9025_TRACK_TX1_DPD 0x0000000000010000 /*!< Tx1 digital pre distortion tracking calibration */ +#define ADI_ADRV9025_TRACK_TX2_DPD 0x0000000000020000 /*!< Tx2 digital pre distortion tracking calibration */ +#define ADI_ADRV9025_TRACK_TX3_DPD 0x0000000000040000 /*!< Tx3 digital pre distortion tracking calibration */ +#define ADI_ADRV9025_TRACK_TX4_DPD 0x0000000000080000 /*!< Tx4 digital pre distortion tracking calibration */ +#define ADI_ADRV9025_TRACK_TX1_CLGC 0x0000000000100000 /*!< Tx1 closed loop gain control tracking calibration */ +#define ADI_ADRV9025_TRACK_TX2_CLGC 0x0000000000200000 /*!< Tx2 closed loop gain control tracking calibration */ +#define ADI_ADRV9025_TRACK_TX3_CLGC 0x0000000000400000 /*!< Tx3 closed loop gain control tracking calibration */ +#define ADI_ADRV9025_TRACK_TX4_CLGC 0x0000000000800000 /*!< Tx4 closed loop gain control tracking calibration */ +#define ADI_ADRV9025_TRACK_TX1_VSWR 0x0000000001000000 /*!< Tx1 voltage standing wave ratio tracking calibration */ +#define ADI_ADRV9025_TRACK_TX2_VSWR 0x0000000002000000 /*!< Tx2 voltage standing wave ratio tracking calibration */ +#define ADI_ADRV9025_TRACK_TX3_VSWR 0x0000000004000000 /*!< Tx3 voltage standing wave ratio tracking calibration */ +#define ADI_ADRV9025_TRACK_TX4_VSWR 0x0000000008000000 /*!< Tx4 voltage standing wave ratio tracking calibration */ +#define ADI_ADRV9025_TRACK_RX1_HD2 0x0000000010000000 /*!< Rx1 HD2 error correction tracking calibration */ +#define ADI_ADRV9025_TRACK_RX2_HD2 0x0000000020000000 /*!< Rx2 HD2 error correction tracking calibration */ +#define ADI_ADRV9025_TRACK_RX3_HD2 0x0000000040000000 /*!< Rx3 HD2 error correction tracking calibration */ +#define ADI_ADRV9025_TRACK_RX4_HD2 0x0000000080000000 /*!< Rx4 HD2 error correction tracking calibration */ +#define ADI_ADRV9025_TRACK_DESERIALIZER 0x0000000100000000 /*!< Deserializer tracking calibration */ + +/** + * \brief Enum of possible wait events + */ +typedef enum adi_adrv9025_WaitEvents +{ + ADI_ADRV9025_CLK_PLL_CP = 0, /*!< CLK PLL CP wait event */ + ADI_ADRV9025_CLK_PLL_LOCK, /*!< CLK PLL lock wait event */ + ADI_ADRV9025_LO1_PLL_CP, /*!< RF PLL CP wait event */ + ADI_ADRV9025_LO1_PLL_LOCK, /*!< RF PLL lock wait event */ + ADI_ADRV9025_LO2_PLL_CP, /*!< RF PLL CP wait event */ + ADI_ADRV9025_LO2_PLL_LOCK, /*!< RF PLL lock wait event */ + ADI_ADRV9025_AUX_PLL_CP, /*!< AUX PLL CP wait event */ + ADI_ADRV9025_AUX_PLL_LOCK, /*!< AUX PLL LOCK wait event */ + ADI_ADRV9025_ARMBUSY /*!< ARM busy wait event */ +} adi_adrv9025_WaitEvents_e; + +/** +* \brief Enum of Calibrations Tracking Enable/ Disable flags +*/ +typedef enum adi_adrv9025_TrackingCalEnableDisable +{ + ADI_ADRV9025_TRACKING_CAL_DISABLE = 0, /*!< Flag to indicate calibration is to disabled */ + ADI_ADRV9025_TRACKING_CAL_ENABLE = 1 /*!< Flag to indicate calibration is to be enabled */ +} adi_adrv9025_TrackingCalEnableDisable_e; + +/** + * \brief Enum of Calibration Errors + */ +typedef enum adi_adrv9025_TrackingCalError +{ + ADI_ADRV9025_TRACKINGCAL_RX1QEC_ERROR = 0x01, /*!< Error state of RX1 QEC */ + ADI_ADRV9025_TRACKINGCAL_RX2QEC_ERROR = 0x02, /*!< Error state of RX2 QEC */ + ADI_ADRV9025_TRACKINGCAL_RX3QEC_ERROR = 0x04, /*!< Error state of RX3 QEC */ + ADI_ADRV9025_TRACKINGCAL_RX4QEC_ERROR = 0x08, /*!< Error state of RX4 QEC */ + ADI_ADRV9025_TRACKINGCAL_ORX1QEC_ERROR = 0x10, /*!< Error state of ORX1 QEC */ + ADI_ADRV9025_TRACKINGCAL_ORX2QEC_ERROR = 0x20, /*!< Error state of ORX2 QEC */ + ADI_ADRV9025_TRACKINGCAL_ORX3QEC_ERROR = 0x40, /*!< Error state of ORX3 QEC */ + ADI_ADRV9025_TRACKINGCAL_ORX4QEC_ERROR = 0x80, /*!< Error state of ORX4 QEC */ + ADI_ADRV9025_TRACKINGCAL_TX1LOL_ERROR = 0x100, /*!< Error state of TX1 LOL */ + ADI_ADRV9025_TRACKINGCAL_TX2LOL_ERROR = 0x200, /*!< Error state of TX2 LOL */ + ADI_ADRV9025_TRACKINGCAL_TX3LOL_ERROR = 0x400, /*!< Error state of TX3 LOL */ + ADI_ADRV9025_TRACKINGCAL_TX4LOL_ERROR = 0x800, /*!< Error state of TX4 LOL */ + ADI_ADRV9025_TRACKINGCAL_TX1QEC_ERROR = 0x1000, /*!< Error state of TX1 QEC */ + ADI_ADRV9025_TRACKINGCAL_TX2QEC_ERROR = 0x2000, /*!< Error state of TX2 QEC */ + ADI_ADRV9025_TRACKINGCAL_TX3QEC_ERROR = 0x4000, /*!< Error state of TX3 QEC */ + ADI_ADRV9025_TRACKINGCAL_TX4QEC_ERROR = 0x8000, /*!< Error state of TX4 QEC */ + ADI_ADRV9025_TRACKINGCAL_TX1DPD_ERROR = 0x10000, /*!< Error state of TX1 DPD */ + ADI_ADRV9025_TRACKINGCAL_TX2DPD_ERROR = 0x20000, /*!< Error state of TX2 DPD */ + ADI_ADRV9025_TRACKINGCAL_TX3DPD_ERROR = 0x40000, /*!< Error state of TX3 DPD */ + ADI_ADRV9025_TRACKINGCAL_TX4DPD_ERROR = 0x80000, /*!< Error state of TX4 DPD */ + ADI_ADRV9025_TRACKINGCAL_TX1CLGC_ERROR = 0x100000, /*!< Error state of TX1 CLGC */ + ADI_ADRV9025_TRACKINGCAL_TX2CLGC_ERROR = 0x200000, /*!< Error state of TX2 CLGC */ + ADI_ADRV9025_TRACKINGCAL_TX3CLGC_ERROR = 0x400000, /*!< Error state of TX3 CLGC */ + ADI_ADRV9025_TRACKINGCAL_TX4CLGC_ERROR = 0x800000, /*!< Error state of TX4 CLGC */ + ADI_ADRV9025_TRACKINGCAL_TX1VSWR_ERROR = 0x1000000, /*!< Error state of TX1 VSWR */ + ADI_ADRV9025_TRACKINGCAL_TX2VSWR_ERROR = 0x2000000, /*!< Error state of TX2 VSWR */ + ADI_ADRV9025_TRACKINGCAL_TX3VSWR_ERROR = 0x4000000, /*!< Error state of TX3 VSWR */ + ADI_ADRV9025_TRACKINGCAL_TX4VSWR_ERROR = 0x8000000, /*!< Error state of TX4 VSWR */ + ADI_ADRV9025_TRACKINGCAL_RX1HD2_ERROR = 0x10000000, /*!< Error state of RX1 HD2 */ + ADI_ADRV9025_TRACKINGCAL_RX2HD2_ERROR = 0x20000000, /*!< Error state of RX2 HD2 */ + ADI_ADRV9025_TRACKINGCAL_RX3HD2_ERROR = 0x40000000, /*!< Error state of RX3 HD2 */ + ADI_ADRV9025_TRACKINGCAL_RX4HD2_ERROR = 0x80000000 /*!< Error state of RX4 HD2 */ +} adi_adrv9025_TrackingCalError_e; + +/** + * \brief Enum of Tracking Calibration States + */ +typedef enum adi_adrv9025_TrackingCalStateCode +{ + ADI_ADRV9025_TRACKINGCAL_SUSPENDED = 0x01, /*!< Cal is temporarily suspended by the framework. */ + ADI_ADRV9025_TRACKINGCAL_RESUMED = 0x02, /*!< Cal is resumed for running. */ + ADI_ADRV9025_TRACKINGCAL_INACTIVE = 0x04, /*!< Cal's Main function is not executing */ + ADI_ADRV9025_TRACKINGCAL_RUNNING = 0x08, /*!< Cal's Main function is executing */ + ADI_ADRV9025_TRACKINGCAL_ENABLED = 0x10, /*!< Cal is enabled */ + ADI_ADRV9025_TRACKINGCAL_DISABLED = 0x20, /*!< Cal is disabled */ + ADI_ADRV9025_TRACKINGCAL_ERROR = 0x40 /*!< Cal has generated error. It may be suspended + from running. BBIC should re-run the cal. */ +} adi_adrv9025_TrackingCalStateCode_e; + +/** +* \brief Enumerated list of Clgc tracking cal errors +*/ +typedef enum adi_adrv9025_ClgcTrackingCalError +{ + ADI_ADRV9025_CLGC_TRACKINGCAL_NO_ERROR = 0, + ADI_ADRV9025_CLGC_TRACKINGCAL_DATACAP_ERROR = 0x3501, /*!< Error code to convey that correlation capture error has occurred */ + ADI_ADRV9025_CLGC_TRACKINGCAL_DATACAP_ABORT_ERROR = 0x3502, /*!< Error code to convey that correlation capture abort error has occurred */ + ADI_ADRV9025_CLGC_TRACKINGCAL_NO_PATHDELAY_ERROR = 0x3503, /*!< Error code to convey that no path delay is found */ + ADI_ADRV9025_CLGC_TRACKINGCAL_TRACK_APPLY_TX_ATTEN_ERROR = 0x3504, /*!< Error code to convey that Tx attenuation was failed to be applied */ + ADI_ADRV9025_CLGC_TRACKINGCAL_TRACK_TX_ATTEN_LIMIT_ERROR = 0x3505, /*!< Error code to convey that Tx attenuation limit has been reached */ + ADI_ADRV9025_CLGC_TRACKINGCAL_TRACK_CONVERG_LIMIT_ERROR = 0x3506, /*!< Error code to convey that convergence limit has been reached */ + ADI_ADRV9025_CLGC_TRACKINGCAL_TRACK_PA_PROTECTION_ERROR = 0x3507, /*!< Error code to convey that PA protection error has occurred */ + ADI_ADRV9025_CLGC_TRACKINGCAL_TRACK_DPD_SYNC_ERROR = 0x3508, /*!< Error code to convey that CLGC-DPD synchronization error has occurred */ + ADI_ADRV9025_CLGC_TRACKINGCAL_TX_LEVEL_LOW_ERROR = 0x3509, /*!< Error code to convey that Tx power level is too low */ + ADI_ADRV9025_CLGC_TRACKINGCAL_ORX_LEVEL_LOW_ERROR = 0x350A, /*!< Error code to convey that ORx power level is too low */ + ADI_ADRV9025_CLGC_TRACKINGCAL_TX_MEAS_ERROR = 0x350B, /*!< Error code to convey that there is a Tx power measurement error */ + ADI_ADRV9025_CLGC_TRACKINGCAL_ORX_MEAS_ERROR = 0x350C, /*!< Error code to convey that there is an ORx power measurement error */ + ADI_ADRV9025_CLGC_TRACKINGCAL_DATACAP_TIMEOUT_ERROR = 0x350D /*!< Error code to convey that data capture is timed out caused by invalid Tx to Orx mapping */ +} adi_adrv9025_ClgcTrackingCalError_e; + +/** +* \brief Enumerated list of CLGC and DPD synchronization status +*/ +typedef enum adi_adrv9025_TrackingCalSyncStatus +{ + ADI_ADRV9025_TRACKINGCAL_SYNC_NA = 0, /*!< Cal sync not available since startup */ + ADI_ADRV9025_TRACKINGCAL_SYNC_OK = 1, /*!< Base and target cals are sync'ed */ + ADI_ADRV9025_TRACKINGCAL_SYNC_BASE_SYNC_NOT_ENABLED = 2, /*!< Sync not enabled in base cal task */ + ADI_ADRV9025_TRACKINGCAL_SYNC_TARG_SYNC_NOT_ENABLED = 3, /*!< Sync not enabled in target cal task */ + ADI_ADRV9025_TRACKINGCAL_SYNC_TARG_CAL_NOT_ENABLED = 4, /*!< Target cal task not enabled */ + ADI_ADRV9025_TRACKINGCAL_SYNC_SEM_CREATE_ERR = 5, /*!< Semaphore cannot be created */ + ADI_ADRV9025_TRACKINGCAL_SYNC_TARG_CAL_GET_STATUS_ERR = 6, /*!< Cannot get target cal's enable status */ + ADI_ADRV9025_TRACKINGCAL_SYNC_TARG_CAL_GET_TIMER_ERR = 7, /*!< Cannot get target cal's timer period */ + ADI_ADRV9025_TRACKINGCAL_SYNC_SEM_TAKE_WARN = 8, /*!< Fail to take a semaphore before timeout */ + ADI_ADRV9025_TRACKINGCAL_SYNC_SEM_GIVE_ERR = 9, /*!< Fail to give a semaphore */ + ADI_ADRV9025_TRACKINGCAL_SYNC_BASE_CAL_ABORT = 10 /*!< Base cal is aborted */ +} adi_adrv9025_TrackingCalSyncStatus_e; + +/** +* \brief Enum of Selecting the mShift channel +*/ +typedef enum adi_adrv9025_DcOffsetChannels +{ + ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH0 = 0x0001, /*!< MShift and DcOffset RX channel0 select */ + ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH1 = 0x0002, /*!< MShift and DcOffset RX channel1 select */ + ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH2 = 0x0004, /*!< MShift and DcOffset RX channel2 select */ + ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH3 = 0x0008, /*!< MShift and DcOffset RX channel3 select */ + ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX_CH0 = 0x0010, /*!< MShift and DcOffset ORX channel0 select */ + ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX_CH1 = 0x0020, /*!< MShift and DcOffset ORX channel1 select */ + ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX2_CH0 = 0x0040, /*!< MShift and DcOffset ORX2 mode channel0 select */ + ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX2_CH1 = 0x0080, /*!< MShift and DcOffset ORX2 mode channel1 select */ + ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK1_CH0 = 0x0100, /*!< MShift and DcOffset ORX LpBack channel0 select */ + ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK1_CH1 = 0x0200, /*!< MShift and DcOffset ORX LpBack channel1 select */ + ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK2_CH0 = 0x0400, /*!< MShift and DcOffset ORX LpBack channel0 select */ + ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK2_CH1 = 0x0800, /*!< MShift and DcOffset ORX LpBack channel1 select */ + ADI_ADRV9025_MSHIFT_DC_OFFSET_ALL_CHANNELS = 0x0FFF /*!< MShift and DcOffset All Channels selected */ +} adi_adrv9025_DcOffsetChannels_e; + +/** +* \brief Enum of Warmboot status +*/ +typedef enum adi_adrv9025_WarmbootStatus +{ + ADI_ADRV9025_WARMBOOT_OFF = 0x00U, /*!< Status indicating Warmboot off */ + ADI_ADRV9025_RUN_INIT_WARMBOOT_IND = 0x80U /*!< Status indicating Warmboot on */ +} adi_adrv9025_WarmbootStatus_e; + +/** +* \brief Enum of possible Cal channel masks +*/ +typedef enum adi_adrv9025_CalChannels +{ + ADI_ADRV9025_CAL_CH_1 = 0x1U, /*!< Channel 0 enabled */ + ADI_ADRV9025_CAL_CH_2 = 0x2U, /*!< Channel 1 enabled */ + ADI_ADRV9025_CAL_CH_3 = 0x4U, /*!< Channel 2 enabled */ + ADI_ADRV9025_CAL_CH_4 = 0x8U, /*!< Channel 3 enabled */ + ADI_ADRV9025_CAL_CH_ALL = 0x0F /*!< All channel mask */ +} adi_adrv9025_CalChannels_e; + +/** +* \brief Data structure to hold Deserializer Tracking Status +*/ +typedef struct adi_adrv9025_DesTrackingCalStatus +{ + uint32_t errorCode; /*!< error code from Serdes tracking */ + uint32_t percentComplete; /*!< percent of required data collected for the current cal. Range 0 to 100 */ + uint32_t varianceMetric; /*!< NOT APPLICABLE FOR SERDES */ + uint32_t iterCount; /*!< running counter that increments each time the cal runs to completion */ + uint32_t updateCount; /*!< running counter that increments each time the cal updates the correction/actuator hardware */ +} adi_adrv9025_DesTrackingCalStatus_t; + +/** + * \brief Data structure to hold Tx LOL Status + */ +typedef struct adi_adrv9025_TxLolStatus +{ + uint32_t errorCode; /*!< error code from Tx LOL */ + uint32_t percentComplete; /*!< percent of required data collected for the current cal. Range 0 to 100 */ + uint32_t varianceMetric; /*!< metric of how well the tracking cal is performing */ + uint32_t iterCount; /*!< running counter that increments each time the cal runs to completion */ + uint32_t updateCount; /*!< running counter that increments each time the cal updates the correction/actuator hardware */ +} adi_adrv9025_TxLolStatus_t; + +/** +* \brief Data structure to hold Tx CLGC Status +*/ +typedef struct adi_adrv9025_ClgcTrackingCalStatus +{ + adi_adrv9025_ClgcTrackingCalError_e errorCode; /*!< error code from Tx CLGC */ + uint32_t percentComplete; /*!< percent of required data collected for the current cal. Range 0 to 100 */ + uint32_t varianceMetric; /*!< metric of how well the tracking cal is performing */ + uint32_t iterCount; /*!< running counter that increments each time the cal runs to completion */ + uint32_t updateCount; /*!< running counter that increments each time the cal updates the correction/actuator hardware */ +} adi_adrv9025_ClgcTrackingCalStatus_t; + +/** + * \brief Data structure to hold Tx QEC Status + */ +typedef struct adi_adrv9025_TxQecStatus +{ + uint32_t errorCode; /*!< error code from Tx QEC */ + uint32_t percentComplete; /*!< percent of required data collected for the current cal. Range 0 to 100 */ + uint32_t correctionMetric; /*!< metric of how well the tracking cal is performing */ + uint32_t iterCount; /*!< running counter that increments each time the cal runs to completion */ + uint32_t updateCount; /*!< running counter that increments each time the cal updates the correction/actuator hardware */ +} adi_adrv9025_TxQecStatus_t; + +/** + * \brief Data structure to hold Rx QEC Status + */ +typedef struct adi_adrv9025_RxQecStatus +{ + uint32_t errorCode; /*!< error code from Rx QEC */ + uint32_t percentComplete; /*!< percent of required data collected for the current cal. Range 0 to 100 */ + uint32_t selfcheckIrrDb; /*!< Performance of the calibration */ + uint32_t iterCount; /*!< running counter that increments each time the cal runs to completion */ + uint32_t updateCount; /*!< running counter that increments each time the cal updates the correction/actuator hardware */ +} adi_adrv9025_RxQecStatus_t; + +/** + * \brief Data structure to hold Rx HD2 Status + */ +typedef struct adi_adrv9025_RxHd2Status +{ + uint32_t errorCode; /*!< error code from HD2 */ + uint32_t percentComplete; /*!< NOT APPLICABLE FOR HD2 Dynamic condition of this cal does not allow for convergence */ + uint32_t confidenceLevel; /*!< Confidence level that cal has accurately identified the coefficient required to cancel HD2 + 0 - No Observation, 1 - 7 indicates increasing confidence level */ + uint32_t iterCount; /*!< running counter that increments each time the cal runs to completion */ + uint32_t updateCount; /*!< running counter that increments each time the cal updates the correction/actuator hardware */ +} adi_adrv9025_RxHd2Status_t; + +/** +* \brief Data structure to hold Orx QEC Status +*/ +typedef struct adi_adrv9025_OrxQecStatus +{ + uint32_t errorCode; /*!< error code from Orx QEC */ + uint32_t percentComplete; /*!< percent of required data collected for the current cal. Range 0 to 100 */ + uint32_t selfcheckIrrDb; /*!< Performance of the calibration */ + uint32_t iterCount; /*!< running counter that increments each time the cal runs to completion */ + uint32_t updateCount; /*!< running counter that increments each time the cal updates the correction/actuator hardware */ +} adi_adrv9025_OrxQecStatus_t; + +/** +* \brief Data structure to hold Rx HD2 calibration config settings +* +* Note: Set posSideBandSel to the side (negative - lower side band or +* positive - upper side band) that has the desired +* signal. Correction will be correcting the 2nd harmonic distortion on the +* same side of the spectrum. +* +* The stop/start frequency specify the harmonic correction range. If not specified, firmware chooses +* a start frequency which is close to baseband DC (~0.12 x capture rate) and a stop frequency which +* matches the edge of used BW specified by the profile for the device. Attempts to extend start/stop +* outside the default range is clipped back to defaults. +* +* It is important for HD2 cancellation to be disabled where signal isn't passed by the PFIR. +* +* The control word is similar to specifying an HD2 control word using ARM control write, but being part of a +* configuration write, it influences HD2 cancellation for all Rx channels. +* Description for each bit of the control word is as follows: +* +* BIT Number | Name | Description +* ------------------------------------------------------------------------------ +* 0 | clear_trust | If set to 1: Clear trust in learned correction information +* 1 | clear_correction | If set to 1: Clears all learned correction information +* 2 | suspend_correction | While set to 1: Disables w/o clearing learned correction corefficient +* 3 | suspend_learning | While set to 1: Disables further learning of correction coefficient +* 4 | suspend_degrading | While set to 1: Disables degrading of trust of corrrection coefficient +* 5 | ignore_power | While set to 1: Ignore blocker power (merge all observations over power) +* 6 | eval_enable | While set to 1: Calculate evaluation data when HFIR is updated +* 7 | preserve_coef | While set to 1: Prevents stop/start from altering correction +* +*/ +typedef struct adi_adrv9025_RxHd2Config +{ + uint32_t posSideBandSel; /*!< 1 = Correct HD2 of desired signal on the positive (upper) side of the complex FFT, + 0 = correct HD2 in the negative (lower)side of the complex FFT */ + uint32_t control; /*!< Applies ARM control word to all channels */ + uint32_t correctStart; /*!< Adjusts start frequency of HD2 correction. Specifies harmonic correction range, not location of the blocker. Defaults to ~0.12 * capture rate. Can be specified anywhere between default range. LSB = 10kHz */ + uint32_t correctStop; /*!< Adjusts stop frequency of HD2 correction. Specifies harmonic correction range, not location of the blocker. Defaults to the edge of the current BW. Can be specified anywhere between default range. LSB = 10kHz */ +} adi_adrv9025_RxHd2Config_t; + +/** + * \brief Data structure to hold the InitCalStatus information for readback. + */ +typedef struct adi_adrv9025_InitCalStatus +{ + uint32_t initErrCode; /*!< ObjID and Error code reported by the initialization calibration. ObjId Bits [15:8], Error Bits [7:0] */ + uint32_t initErrCal; /*!< the object ID of the calibration reporting an error */ + uint32_t calsDurationUsec; /*!< Duration time in uSec of the last initial calibration run */ + uint32_t calsSincePowerUp[4]; /*!< Bitmask indicating calibrations run since power up for Channel 1/2/3/4 */ + uint32_t calsLastRun[4]; /*!< Bitmask indicating calibrations run in during the previous runInitCals() call for Channel 1/2/3/4 */ +} adi_adrv9025_InitCalStatus_t; + +/** +* \brief Data structure to hold Cals Init structures +* +* \param calMask Mask from adi_adrv9025_InitCalibrations_e to run on init. +* \param channelMask Mask to hold Channel to run on init +* Bit mask range, (valid 0x01-0x0F), 1 bit per channel. +* channelMask applies to the specific cals selected. +* If Tx cal, the channel mask refers to Tx channels, +* if Rx cals, channel mask refers to Rx channels, +* if ORx, channel mask refers to ORxchannels. +* If multiple selected, refers to all selected (Rx/Tx/ORx channels) for the cals selected. +* \param warmBoot Not supported. +*/ +typedef struct adi_adrv9025_InitCals +{ + uint32_t calMask; /*!< Mask adi_adrv9025_InitCalibrations_e to run on init */ + uint8_t channelMask; /*!< Mask to hold Channel to run on init */ + uint8_t warmBoot; /*!< (not supported) */ +} adi_adrv9025_InitCals_t; + +/** +* \brief Data structure to hold current state of all the calibrations. +* Description for each bit of the returned state for every calibration is as follows +* +* BIT Number | STATE | Description +* ------------------------------------------------------------------------------ +* 0 | SUSPENDED | Cal is temporarily suspended by the framework. +* 1 | RESUMED | Cal is resumed for running. +* 2 | INACTIVE | Cal's Main function is not executing +* 3 | RUNNING | Cal's Main function is executing +* 4 | ENABLED | Cal is enabled +* 5 | DISABLED | Cal is disabled +* 6 | ERROR | Cal has generated error. It may be suspended from running. +* | | BBIC should re-run the cal. + +* \param calError 4 bytes for Error codes Mask +* +* Bits | Corresponding error +* [4 bytes] | +* ---------------------------------------- +* 0 | Error state of RX1 QEC +* 1 | Error state of RX2 QEC +* 2 | Error state of RX3 QEC +* 3 | Error state of RX4 QEC +* 4 | Error state of ORX1 QEC +* 5 | Error state of ORX2 QEC +* 6 | Error state of ORX3 QEC +* 7 | Error state of ORX4 QEC +* 8 | Error state of TX1 LOL +* 9 | Error state of TX2 LOL +* 10 | Error state of TX3 LOL +* 11 | Error state of TX4 LOL +* 12 | Error state of TX1 QEC +* 13 | Error state of TX2 QEC +* 14 | Error state of TX3 QEC +* 15 | Error state of TX4 QEC +* 16 | Error state of TX1 DPD +* 17 | Error state of TX2 DPD +* 18 | Error state of TX3 DPD +* 19 | Error state of TX4 DPD +* 20 | Error state of TX1 CLGC +* 21 | Error state of TX2 CLGC +* 22 | Error state of TX3 CLGC +* 23 | Error state of TX4 CLGC +* 24 | Error state of TX1 VSWR +* 25 | Error state of TX2 VSWR +* 26 | Error state of TX3 VSWR +* 27 | Error state of TX4 VSWR +* 28 | Error state of RX1 HD2 +* 29 | Error state of RX2 HD2 +* 30 | Error state of RX3 HD2 +* 31 | Error state of RX4 HD2 +* +* \param rx1Qec Rx Qec Tracking Cal Status for Channel 1. +* \param rx2Qec Rx Qec Tracking Cal Status for Channel 2. +* \param rx3Qec Rx Qec Tracking Cal Status for Channel 3. +* \param rx4Qec Rx Qec Tracking Cal Status for Channel 4. +* +* \param orx1Qec Orx Qec Tracking Cal Status for Channel 1. +* \param orx2Qec Orx Qec Tracking Cal Status for Channel 2. +* \param orx3Qec Orx Qec Tracking Cal Status for Channel 3. +* \param orx4Qec Orx Qec Tracking Cal Status for Channel 4. +* +* \param tx1Lol Tx Lol Tracking Cal Status for Channel 1. +* \param tx2Lol Tx Lol Tracking Cal Status for Channel 2. +* \param tx3Lol Tx Lol Tracking Cal Status for Channel 3. +* \param tx4Lol Tx Lol Tracking Cal Status for Channel 4. +* +* \param tx1Qec Tx Qec Tracking Cal Status for Channel 1. +* \param tx2Qec Tx Qec Tracking Cal Status for Channel 2. +* \param tx3Qec Tx Qec Tracking Cal Status for Channel 3. +* \param tx4Qec Tx Qec Tracking Cal Status for Channel 4. +* +* \param tx1Dpd Tx Dpd Tracking Cal Status for Channel 1. +* \param tx2Dpd Tx Dpd Tracking Cal Status for Channel 2. +* \param tx3Dpd Tx Dpd Tracking Cal Status for Channel 3. +* \param tx4Dpd Tx Dpd Tracking Cal Status for Channel 4. +* +* \param tx1Clgc Tx Clgc Tracking Cal Status for Channel 1. +* \param tx2Clgc Tx Clgc Tracking Cal Status for Channel 2. +* \param tx3Clgc Tx Clgc Tracking Cal Status for Channel 3. +* \param tx4Clgc Tx Clgc Tracking Cal Status for Channel 4. +* +* \param tx1Vswr Tx vswr Tracking Cal Status for Channel 1. +* \param tx2Vswr Tx vswr Tracking Cal Status for Channel 2. +* \param tx3Vswr Tx vswr Tracking Cal Status for Channel 3. +* \param tx4Vswr Tx vswr Tracking Cal Status for Channel 4. +* +* \param rx1Hd2 Rx Hd2 Tracking Cal Status for Channel 1. +* \param rx2Hd2 Rx Hd2 Tracking Cal Status for Channel 2. +* \param rx3Hd2 Rx Hd2 Tracking Cal Status for Channel 3. +* \param rx4Hd2 Rx Hd2 Tracking Cal Status for Channel 4. +* +*/ +typedef struct adi_adrv9025_TrackingCalState +{ + uint64_t calError; /*!< 8 bytes for Error codes Mask */ + + uint8_t rx1Qec; /*!< Rx Qec Tracking Cal Status for Channel 1 */ + uint8_t rx2Qec; /*!< Rx Qec Tracking Cal Status for Channel 2 */ + uint8_t rx3Qec; /*!< Rx Qec Tracking Cal Status for Channel 3 */ + uint8_t rx4Qec; /*!< Rx Qec Tracking Cal Status for Channel 4 */ + + uint8_t orx1Qec; /*!< Orx Qec Tracking Cal Status for Channel 1 */ + uint8_t orx2Qec; /*!< Orx Qec Tracking Cal Status for Channel 2 */ + uint8_t orx3Qec; /*!< Orx Qec Tracking Cal Status for Channel 3 */ + uint8_t orx4Qec; /*!< Orx Qec Tracking Cal Status for Channel 4 */ + + uint8_t tx1Lol; /*!< Tx Lol Tracking Cal Status for Channel 1 */ + uint8_t tx2Lol; /*!< Tx Lol Tracking Cal Status for Channel 2 */ + uint8_t tx3Lol; /*!< Tx Lol Tracking Cal Status for Channel 3 */ + uint8_t tx4Lol; /*!< Tx Lol Tracking Cal Status for Channel 4 */ + + uint8_t tx1Qec; /*!< Tx Qec Tracking Cal Status for Channel 1 */ + uint8_t tx2Qec; /*!< Tx Qec Tracking Cal Status for Channel 2 */ + uint8_t tx3Qec; /*!< Tx Qec Tracking Cal Status for Channel 3 */ + uint8_t tx4Qec; /*!< Tx Qec Tracking Cal Status for Channel 4 */ + + uint8_t tx1Dpd; /*!< Tx Dpd Tracking Cal Status for Channel 1 */ + uint8_t tx2Dpd; /*!< Tx Dpd Tracking Cal Status for Channel 2 */ + uint8_t tx3Dpd; /*!< Tx Dpd Tracking Cal Status for Channel 3 */ + uint8_t tx4Dpd; /*!< Tx Dpd Tracking Cal Status for Channel 4 */ + + uint8_t tx1Clgc; /*!< Tx Clgc Tracking Cal Status for Channel 1 */ + uint8_t tx2Clgc; /*!< Tx Clgc Tracking Cal Status for Channel 2 */ + uint8_t tx3Clgc; /*!< Tx Clgc Tracking Cal Status for Channel 3 */ + uint8_t tx4Clgc; /*!< Tx Clgc Tracking Cal Status for Channel 4 */ + + uint8_t tx1Vswr; /*!< VSWR Tracking Cal Status for Channel 1 */ + uint8_t tx2Vswr; /*!< VSWR Tracking Cal Status for Channel 2 */ + uint8_t tx3Vswr; /*!< VSWR Tracking Cal Status for Channel 3 */ + uint8_t tx4Vswr; /*!< VSWR Tracking Cal Status for Channel 4 */ + + uint8_t rx1Hd2; /*!< Rx Hd2 Tracking Cal Status for Channel 1 */ + uint8_t rx2Hd2; /*!< Rx Hd2 Tracking Cal Status for Channel 2 */ + uint8_t rx3Hd2; /*!< Rx Hd2 Tracking Cal Status for Channel 3 */ + uint8_t rx4Hd2; /*!< Rx Hd2 Tracking Cal Status for Channel 4 */ + + uint8_t deserializer; /*!< Deserializer Tracking Cal Status */ +} adi_adrv9025_TrackingCalState_t; + +/** +* \brief Data structure to hold the external path delay settings +*/ +typedef struct adi_adrv9025_ExternalPathDelay +{ + uint8_t fifoDelay; /*!< External Tx-ORx data path delay for capturing samples */ + uint8_t interpolationIndex; /*!< Tx-ORx data path delay interpolation index aligned to 1/16th of a sample */ +} adi_adrv9025_ExternalPathDelay_t; + +/** +* \brief Data structure to hold the DC OffSet and MShift selections +*/ +typedef struct adi_adrv9025_DcOffSet +{ + adi_adrv9025_DcOffsetChannels_e dcChannelSelect; /*!< enum that select the channel type to apply the offset and shift */ + uint8_t mShift; /*!< mShift value between 0-31 */ +} adi_adrv9025_DcOffSet_t; + +/** +* \brief Data structure to hold the DC OffSet and MShift selections +* +* Both reset types resets the perturbation scaler, clears accumulated RX and TX values, sets fast attack=1 to force a fast attack +* and applies the measurements more strongly. +* +* Hard reset erases the TxLOL look-up table. The look-up table keeps the correction values for all 64 attenuation values. +* Soft reset restarts the TxLOL estimation without erasing the TxLOL look-up table. +*/ +typedef struct adi_adrv9025_ExtTxLolChannelReset_s +{ + adi_adrv9025_TxChannels_e channelSelect; /*!< enum that select the channels t0 reset */ + uint8_t resetType; /*!< 0-Soft Reset, 1-Hard Reset */ +} adi_adrv9025_ExtTxLolChannelReset_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_CALS_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_cpu.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_cpu.h new file mode 100644 index 0000000..95509a5 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_cpu.h @@ -0,0 +1,596 @@ +/** +* \file adi_adrv9025_cpu.h +* \brief Contains ADRV9025 processor function prototypes for +* adi_adrv9025_cpu.c +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.txt" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_CPU_H_ +#define _ADI_ADRV9025_CPU_H_ + +#include "adi_adrv9025_types.h" +#include "adi_common_error_types.h" +#include "adi_adrv9025_cpu_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************** +* Initialization functions +**************************************************************************** +*/ + +/** + * \brief Start the CPU(s) + * + * Sets run bit to 1. Then wait and check for FW Status. + * + * + * \pre This function is called after the device has been initialized and before multichip-sync + * (MCS) has been completed + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep{init-> (most members)} + * \dep_end + * + * \param device Pointer to the ADRV9025 device settings data structure + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_CpuStart( + adi_adrv9025_Device_t* device); + +/** +* \brief Loads binary array into CPU program memory +* +* This function sets the CPU DMA control register bits for an CPU memory write, auto-incrementing +* the address. Valid memory addresses are: Program Memory (0x01000000 - 0x0104FFFF) +* +* The top level application reads the binary file, parsing it into any array, starting at the first data byte +* on the first line of the file. The array is passed to this function and writes it to CPU program memory. Any non-data +* bytes should be excluded from the binary array when parsing. +* +* \pre This function is called after the device has been initialized, PLL lock status has been verified, and +* the stream binary has been loaded +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param cpuType type of cpu +* \param byteOffset Offset (starting from 0) of where to place the binary +* array in CPU memory (if loaded in multiple function +* calls) +* \param binary Byte array containing all valid FW file data bytes +* \param byteCount The number of bytes in the binary array +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_CpuImageWrite( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint32_t byteOffset, + const uint8_t binary[], + uint32_t byteCount); + +/** +* \brief Writes the ADRV9025 CPU configuration settings +* +* \pre This function is called automatically during adi_adrv9025_CpuStart(), and +* this function must be called after loading the firmware. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{init-> (most members)} +* \dep_end +* +* \param device Pointer to the ADRV9025 device settings data structure +* \param init Pointer to the ADRV9025 initialization settings data structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_CpuProfileWrite( + adi_adrv9025_Device_t* device, + const adi_adrv9025_Init_t* init); + +/** +* \brief Loads the ADC profile data into CPU memory +* +* This function writes ADC profile into the CPU data memory before +* loading the firmware. When the firmware is loaded and begins +* to initialize, the CPU init sequence copies the ADC profiles from CPU +* memory and loads them into the firmware internal data strucutures. +* +* \pre This function is called during device after downloading FW code +* +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device settings data structure +* \param adcProfiles Pointer to the ADRV9025 ADC profile data structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_CpuAdcProfilesWrite( + adi_adrv9025_Device_t* device, + const adi_adrv9025_AdcProfiles_t* adcProfiles); + +/** +* \brief Check the Firmware Status. +* +* After setting run bit to 1, then wait and check for FW Status. This function does a SPI read, +* and can not be use in a SPI write only (Broadcasting) mode. +* +* \pre This function is called after the device has been initialized and before multichip-sync +* (MCS) has been completed +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device settings data structure +* \param timeout_us Timeout to stop waiting for CPU to boot up. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_CpuStartStatusCheck( + adi_adrv9025_Device_t* device, + uint32_t timeout_us); + +/**************************************************************************** +* Runtime functions +**************************************************************************** +*/ + +/**************************************************************************** +* Helper functions +**************************************************************************** +*/ + +/** +* \brief Write to the ADRV9025 CPU program or data memory +* +* Valid memory addresses are: Program Memory (0x01000000 - 0x0104FFFF), +* Data Memory (0x20000000 - 0x2004FFFF). +* +* \pre This function is private and is not called directly by the user. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param address The 32-bit CPU memory address to write +* \param data Byte array (uint8_t) containing data to be written to CPU memory +* \param byteCount Number of bytes in the data array to be written +* \param autoIncrement is boolean flag to enable or disable auto-increment of CPU register address +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_CpuMemWrite( + adi_adrv9025_Device_t* device, + uint32_t address, + const uint8_t data[], + uint32_t byteCount, + uint8_t autoIncrement); + +/** +* \brief Read from the ADRV9025 CPU program or data memory +* +* Valid memory addresses are: Program Memory (0x01000000 - 0x0104FFFF), +* Data Memory (0x20000000 - 0x2004FFFF). +* +* \pre This function is private and is not called directly by the user. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param address The 32bit CPU memory address to read from. +* \param returnData Byte(uint8_t) array containing the data read from the CPU memory. +* \param byteCount Number of bytes in the returnData array. +* \param autoIncrement is boolean flag to enable or disable auto-increment of CPU register address +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_CpuMemRead( + adi_adrv9025_Device_t* device, + uint32_t address, + uint8_t returnData[], + uint32_t byteCount, + uint8_t autoIncrement); + +/** +* \brief Sends a command to the ADRV9025 CPU interface +* +* \pre This function can be called after initializing the CPU +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param cpuType type of cpu +* \param opCode Opcode of interest where only the first 16 even-numbered integers are valid +* \param extendedData A byte array containing extended data to write to the CPU command interface +* \param byteCount Number of bytes in the extendedData array (Valid size = 0-4 bytes) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action for CPU reset required +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_CpuCmdWrite( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint8_t opCode, + const uint8_t extendedData[], + uint8_t byteCount); + +/** +* \brief Isolated byte read of the ADRV9025 CPU 64-bit command status register based on the opcode +* +* A single byte read is performed on the 64-bit command status register according to +* the opcode of interest. The pending bit and the error type are extracted from the status +* register and returned as a single byte in the lower nibble. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param cpuType Type of cpu +* \param opCode Opcode of interest where only the first 16 even-numbered integers are valid +* \param cmdStatByte Comprised of cmdStatByte[3:1] = error type, cmdStatByte[0] = pending flag for opCode of interest +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +* TODO: Need to review number of bits SPI regs per opcode */ +int32_t adi_adrv9025_CpuCmdStatusOpcodeGet(adi_adrv9025_Device_t *device, + adi_adrv9025_CpuType_e cpuType, + uint8_t opCode, + uint8_t *cmdStatByte); + +/** +* \brief ADRV9025 CPU command status wait function polls command status register until opcode of interest completes +* +* \pre firmware load and initialization must take place first before attempting to use this function +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param cpuType Type of cpu +* \param opCode Opcode of interest where only the first 16 even-numbered integers are valid +* \param cmdStatusByte Comprised of cmdStatByte[3:1] = error type, cmdStatByte[0] = pending flag for opCode of interest +* \param timeout_us Command time-out period in microseconds +* \param waitInterval_us Wait interval time to thread sleep between each check of the CPU command status to prevent SPI read thrashing +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action for CPU reset required +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +* TODO: Need to review number of bits SPI regs per opcode */ +int32_t adi_adrv9025_CpuCmdStatusWait( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint8_t opCode, + uint8_t* cmdStatusByte, + uint32_t timeout_us, + uint32_t waitInterval_us); + +/** +* \brief Sends a command to the ADRV9025 CPU interface and polls command status register until opcode of interest completes +* +* \pre This function can be called after initializing the CPU +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param cpuType type of cpu +* \param armOpCode Opcode of interest where only the first 16 even-numbered integers are valid +* \param extendedData A byte array containing extended data to write to the CPU command interface +* \param byteCount Number of bytes in the extendedData array (Valid size = 0-4 bytes) +* \param waitTimeoutUs Command time-out period in microseconds +* \param waitIntervalUs Wait interval time to thread sleep between each check of the CPU command status to prevent SPI read thrashing +* \param armObjId The interest object ID +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action for CPU reset required +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_CpuCmdWriteWait( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint8_t armOpCode, + const uint8_t extendedData[], + uint8_t byteCount, + uint32_t waitTimeoutUs, + uint32_t waitIntervalUs, + uint8_t armObjId); + +/** +* \brief Low level helper function used by ADRV9025 API to read the CPU memory config structures +* +* Normally this function should not be required to be used directly by the BBIC. This is a helper +* function used by other ADRV9025 API commands to read settings from the CPU memory. +* +* \pre This function is private and is not called directly by the user +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param cpuType Type of cpu +* \param objectId CPU id of a particular structure or setting in CPU memory +* \param byteOffset Byte offset from the start of the objectId's memory location in CPU memory +* \param returnData A byte array containing data read back from the CPU memory buffer +* \param byteCount Number of bytes in the data array (Valid size = 1-255 bytes) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action for CPU reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_CpuConfigRead( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint8_t objectId, + uint16_t byteOffset, + uint8_t returnData[], + uint8_t byteCount); + +/** +* \brief Low level helper function used by ADRV9025 API to write the CPU memory config structures +* +* Normally this function should not be required to be used directly by the BBIC. This is a helper +* function used by other ADRV9025 API commands to write settings into the CPU memory. +* +* \pre This function is private and is not called directly by the user. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param cpuType Type of cpu +* \param objectId CPU id of a particular structure or setting in CPU memory +* \param byteOffset Byte offset from the start of the objectId's memory location in CPU memory +* \param data A byte array containing data to write to the CPU memory buffer. +* \param byteCount Number of bytes in the data array (Valid size = 1-255 bytes) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action for CPU reset required +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_CpuConfigWrite( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint8_t objectId, + uint16_t byteOffset, + const uint8_t data[], + uint8_t byteCount); + +/** +* \brief Reads the ADRV9025 CPU 64-bit command status register and returns an error and status word +* +* A 64-bit status register consisting of a pending bit and three-bit error type is read one byte at +* a time for the first 16 even-numbered opcodes. The function parses the pending bits and error bits into +* two (2) separate 16-bit words. statusWord contains the status pending bits. errorWord contains +* a single error bit if the error type > 0 for any three-bit code. +* Each word is weighted according to the first 16 even-numbered opcodes where, +* 0x0001 = opcode '0', 0x0002 = opcode '2', 0x0004 = opcode '4', 0x0008 = opcode '6' and so on. +* +* \pre This function is private and is not called directly by the user. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param cpuType Type of cpu +* \param errorWord 16-bit error word comprised of weighted bits according to first 16 even-numbered opcodes +* The weighted bit is set if any three-bit error type > 0, where '0' = OK +* \param statusWord 16-bit pending bits word comprised of weighted bits according to first 16 even-numbered opcodes +* The weighted bit is set if an opcode is pending, where '0' = no pending opcode +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +* TODO: Need to review number of error and status bits in SPI regs */ +int32_t adi_adrv9025_CpuCmdStatusGet(adi_adrv9025_Device_t *device, + adi_adrv9025_CpuType_e cpuType, + uint16_t *errorWord, + uint16_t *statusWord); + +/**************************************************************************** +* Debug functions +**************************************************************************** +*/ + +/** + * \brief Verifies the CPU checksum value + * + * The checksum which is written into the binary file is verified with the calculated + * checksum in the ADRV9025 CPU after the binary file has been loaded. This function + * will wait for a timeout period for the checksum calculation to occur. The + * user can adjust the timeout period and SPI read interval in adi_adrv9025_user.c by + * adjusting the macros VERIFY_CPU_CHKSUM_TIMEOUTUS and + * VERIFY_CPU_CHKSUM_INTERVALS. This function is only supported for CPU-C + * + * \pre This function is called after the CPU FW binary file has been loaded to verify it's + * checksum in CPU memory + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device is structure pointer to the ADRV9025 data structure containing settings + * \param cpuType Type of cpu - User can only select CPU-C. + * \param checksum Pointer to adi_adrv9025_ChecksumTable_t data structure containing settings + * \param checksumValid Indicate if a valid checksum + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action for CPU reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_CpuChecksumTableGet( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + adi_adrv9025_CpuChecksumTable_t* checksum, + uint8_t* checksumValid); + +/** +* \brief Reads back the version of the CPU binary loaded into the ADRV9025 CPU memory +* +* This function reads the CPU memory to read back the major.minor.releaseCandidate +* version for the CPU binary loaded into CPU memory. +* +* Dependencies +* - device->spiSettings->chipSelectIndex +* +* \param device is structure pointer to the ADRV9025 data structure containing settings +* \param cpuType Type of cpu +* \param fwVersion FW version will be populated here, it is of struct type adi_adrv9025_CpuVersion_t. +* +* \retval ADRV9025_ERR_OK Function completed successfully +*/ +int32_t adi_adrv9025_CpuFwVersionGet( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + adi_adrv9025_CpuFwVersion_t* fwVersion); + +/** +* \brief Reads CPU Mailbox Command Status +* +* This function reads CPU Mailbox Command Status from 'arm_command_busy' bit +* located in 'arm_command' register (0x00c3) +* +* \pre This function may be called any time after device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device is structure pointer to the ADRV9025 data structure containing settings +* \param mailboxBusy Pointer to byte containing mailbox busy status, 0:CPU is ready to accept a new command, 1:CPU is busy and cannot accept a new command +* \param cpuType Type of cpu +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_CpuMailboxBusyGet( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint8_t* mailboxBusy); + +/** + * \brief Reads CPU Exception Status + * + * This function reads Exception Status from arm memory +* +* \pre This function may be called any time after device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device is structure pointer to the ADRV9025 data structure containing settings +* \param cpuType Type of cpu +* \param exceptionValue Pointer to byte containing ARM exception error code +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_CpuExceptionGet( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint32_t* exceptionValue); + +/** + * \brief Reads Arm System error message. + * + * \pre This function may be called any time after device initialization + * + * \dep_begin + * \dep{ device->common.devHalInfo } + * \dep_end + * + * \param device is structure pointer to the ADRV9025 data structure containing settings + * \param cpuType Type of cpu + * \param errorMessage Pointer to character array containing the error message + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_CpuSystemErrorGet(adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + const char** errorMessage); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_CPU_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_cpu_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_cpu_types.h new file mode 100644 index 0000000..83a2ce9 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_cpu_types.h @@ -0,0 +1,120 @@ +/** +* \file adi_adrv9025_cpu_types.h +* \brief Contains ADRV9025 data types for on board cpus feature +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.txt" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_CPU_TYPES_H_ +#define _ADI_ADRV9025_CPU_TYPES_H_ + +#include +#include "../../private/include/adrv9025_cpu_macros.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum adi_adrv9025_CpuType +{ + ADI_ADRV9025_CPU_TYPE_UNKNOWN = -1, + ADI_ADRV9025_CPU_TYPE_C, + ADI_ADRV9025_CPU_TYPE_D, + ADI_ADRV9025_CPU_TYPE_MAX +} adi_adrv9025_CpuType_e; + +/** +* \brief Enumerated list of FW image build options. +*/ +typedef enum adi_adrv9025_CpuFwBuildType +{ + ADI_ADRV9025_CPU_FW_BUILD_RELEASE = 0, + ADI_ADRV9025_CPU_FW_BUILD_DEBUG = 1, + ADI_ADRV9025_CPU_FW_BUILD_TESTOBJ = 2 +} adi_adrv9025_CpuFwBuildType_e; + +/** +* \brief Data structure to FW version information +*/ +typedef struct adi_adrv9025_CpuFwVersion +{ + uint8_t majorVer; + uint8_t minorVer; + uint8_t maintVer; + uint16_t rcVer; + adi_adrv9025_CpuFwBuildType_e cpuFwBuildType; +} adi_adrv9025_CpuFwVersion_t; + +/* structure to hold memory map of a cpu */ +typedef struct adi_adrv9025_CpuAddr +{ + uint8_t enabled; + /* subsystem registers */ + uint16_t ctlAddr; /* control register */ + uint16_t bootAddr; /* boot address */ + uint16_t stackPtrAddr; /* stack pointer */ + + /* Mailbox registers */ + uint16_t cmdAddr; /* command. b7 = command_busy. b5:0 command */ + uint16_t extCmdAddr; /* command payload. 4 bytes */ + uint16_t cmdStatusAddr; /* command status. 16 bytes */ + + /* Program section */ + uint32_t progStartAddr; /* start address of program memory section */ + uint32_t progEndAddr; /* end address of program memory section */ + uint32_t versionAddr; /* 48-bytes set aside for FW Rev Info address */ + uint32_t structChecksumAddr; /* checksum structure address */ + uint32_t debugPointersAddr; /* Debug Pointers */ + uint32_t buildChecksumAddr; /* FW build time checksum address */ + + /* Data section */ + uint32_t dataStartAddr; /* start address of data memory section */ + uint32_t dataEndAddr; /* end address of data memory section */ + uint32_t cfrPulseAddr; /* */ + uint32_t mailboxSetAddr; /* Mailbox SET command buffer */ + uint32_t mailboxGetAddr; /* Mailbox GET command buffer */ + uint32_t mailboxRunInitAddr; /* Mailbox RUN_INIT command buffer */ + uint32_t mailboxFhmAddr; /* Mailbox Frequency Hopping Mode */ +} adi_adrv9025_CpuAddr_t; + +typedef struct adi_adrv9025_Cpu +{ + uint32_t devProfileAddr; /* Device Profile structure address */ + uint32_t adcProfileAddr; /* ADC Profile structure address */ + adi_adrv9025_CpuAddr_t cpuAddr[ADRV9025_MAX_CPUS]; +} adi_adrv9025_Cpu_t; + +/** +* \brief Data structure to hold ARM image build and runtime calculated checksums. +*/ +typedef struct adi_adrv9025_CpuChecksum +{ + uint32_t buildChecksum; + uint32_t runChecksum; +} adi_adrv9025_CpuChecksum_t; + +/** +* \brief Data structure to hold a table of additional ARM checksums +*/ +typedef struct adi_adrv9025_CpuChecksumTable +{ + adi_adrv9025_CpuChecksum_t fwCheckSums; + adi_adrv9025_CpuChecksum_t streamsCheckSum[ADRV9025_STREAM_MAX]; + adi_adrv9025_CpuChecksum_t deviceProfileCheckSum; + adi_adrv9025_CpuChecksum_t adcProfilefwCheckSum; + uint32_t fwError; + uint32_t fwErrorCode; +} adi_adrv9025_CpuChecksumTable_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_CPU_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_data_interface.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_data_interface.h new file mode 100644 index 0000000..85edfff --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_data_interface.h @@ -0,0 +1,1313 @@ +/** + * \file adi_adrv9025_data_interface.h + * \brief Contains ADRV9025 JESD204b data path related function prototypes for + * adi_adrv9025_jesd204.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_DATA_INTERFACE_H_ +#define _ADI_ADRV9025_DATA_INTERFACE_H_ + +#include "adi_adrv9025_types.h" +#include "adi_adrv9025_tx_types.h" +#include "adi_common_error_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************** + * Initialization functions + **************************************************************************** + */ + +/** +* \brief Gets the JESD204B Framer's configuration +* +* This function reads the JESD204B framer settings. +* +* \pre This function may be called any time after device initialization +* +* \dep_begin +* \dep{device->devHalInfo} +* \dep{init->rxChannels} +* \dep{init->jesd204Settings.framerA :All members} +* \dep{init->jesd204Settings.framerB :All members} +* \dep_end +* +* \param device Structure pointer to the device settings structure +* \param framerSel Select the framer to read +* \param framerCfg Structure pointer to return framer's configuration +* +* \retval ADI_ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_FramerCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_FramerSel_e framerSel, + adi_adrv9025_FrmCfg_t* framerCfg); + +/** + * \brief Reads Configuration of JESD204B Deframer * + * + * This function reads the JESD204B deframer settings. + * deframerCfg->bankId is returned zero, since Jrx doesn't support bank id. + * deframerCfg->externalSysref is not used, will be returned 0. + * deframerCfg->syncbOutCmosSlewRate is not used, will be returned 0. + * deframerCfg->enableManualLaneXbar is not used, will be returned 0. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep{init->jesd204Settings} + * \dep{init->tx} + * \dep_end + * + * \param device Structure pointer to device settings data structure + * \param deframerSel Desired deframer to read + * \param deframerCfg Structure pointer to read deframer configuration + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_DeframerCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSel, + adi_adrv9025_DfrmCfg_t* deframerCfg); + +/** + * \brief Enables/Disables the JESD204B/C Framer + * \brief Not currently implemented + * This function is normally not necessary. In the event that the link needs to be reset, this + * function allows a framer to be disabled and re-enabled, adi_adrv9025_FramerSel_e contains the links + * which OR'd together and passed as the selFramerMask parameter. + * + * framerSelMask | Description + * --------------|----------------------------------------------------------------------------- + * bit 2 | Select Framer 2 + * bit 1 | Select Framer 1 + * bit 0 | Select Framer 0 + * + * \pre This function may be called any time after device initialization + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device is a pointer to the device settings structure + * \param framerSelMask Desired framer(s) to set/reset. + * \param enable 0 = Disable the selected framers, 1 = enable the selected framer link + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_FramerLinkStateSet(adi_adrv9025_Device_t* device, + uint8_t framerSelMask, + uint8_t enable); + +/** +* \brief Get the JESD204B/C Framer Link enable values +* +* This allows reading which framers are enabled/disabled. +* +* enable | Description +* --------------|----------------------------------------------------------------------------- +* bit 1 | 1 = Deframer 1 Enabled, 0 = Deframer 1 Disabled +* bit 0 | 1 = Deframer 0 Enabled, 0 = Deframer 0 Disabled +* +* \pre This function may be called any time after device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device is a pointer to the device settings structure +* \param enable is a pointer to the value returned. Valid values are 0 to 7. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_FramerLinkStateGet(adi_adrv9025_Device_t* device, + uint8_t* enable); + +/** + * \brief Enables/Disables the JESD204B/C Deframer + * + * This function is normally not necessary. In the event that the link needs to be reset, this + * function allows a deframer to be disabled and re-enabled. During disable, the lane FIFOs + * for the selected deframer are also disabled. When the deframer link is enabled, the + * lane FIFOs for the selected deframer are re-enabled (reset). The BBIC should send valid + * serializer data before enabling the link so the ADRV9025 CDR (recovered clock) is locked. + * In the event that the deframer needs to be enabled or disabled, this + * function allows a framer to be disabled and re-enabled, adi_adrv9025_DeframerSel_e contains the links + * which OR'd together and passed as the selDeframerMask parameter. + * + * framerSelMask | Description + * --------------|----------------------------------------------------------------------------- + * bit 1 | Select Deframer 1 + * bit 0 | Select Deframer 0 + * + * \pre This function may be called any time after device initialization. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 device settings data structure + * \param deframerSelMask Desired deframer to reset, deframer 1 or deframer 2 + * \param enable 0 = Disable the selected deframer, 1 = enable the selected deframer link + * + \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_DfrmLinkStateSet(adi_adrv9025_Device_t* device, + uint8_t deframerSelMask, + uint8_t enable); + +/** +* \brief Get the JESD204B/C Deframer Link enable values +* +* This allows reading which deframers are enabled/disabled. +* +* \pre This function may be called any time after device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device is a pointer to the device settings structure +* \param enable is a pointer to the value returned. Valid values are 1 to 3. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DfrmLinkStateGet(adi_adrv9025_Device_t* device, + uint8_t* enable); + +/** + * \brief Enables or disables the external SYSREF JESD204b signal to the transceiver's framers + * + * For the framer to retime its LMFC (local multi frame clock), a SYSREF rising edge is required. + * The external SYSREF signal at the pin can be gated off internally so the framer does not see + * a potential invalid SYSREF pulse before it is configured correctly. + * + * By default ADRV9025 has the SYSREF signal ungated, however, the ADRV9025 Multichip Sync state machine + * still does not allow the external SYSREF to reach the framer until the other stages of multichip + * sync have completed. As long as the external SYSREF is correctly configured before performing MCS, + * this function may not be needed by the BBIC, since the MCS state machine gates the SYSREF to the + * framer. + * + * \pre This function is called after the device has been initialized and the JESD204B framer is enabled + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device is a pointer to the device settings structure + * \param framerSelMask Select framer to enable/disable SYSREF input for (Valid Any ORed combination of enums ADI_ADRV9025_FRAMER_0, ADI_ADRV9025_FRAMER_1, ADI_ADRV9025_FRAMER_1 or ADI_ADRV9025_ALL_FRAMERS) + * \param enable = '1' enables SYSREF to deframer, '0' disables SYSREF to deframer + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + * + * TODO: Could pass structure instead of just enable, allow to set sysref options */ +int32_t adi_adrv9025_FramerSysrefCtrlSet(adi_adrv9025_Device_t* device, + uint8_t framerSelMask, + uint8_t enable); + +/** +* \brief Reads the bit indicating external SYSREF JESD204b signal of the transceiver's framers. Only status for one channel +* \ at a time can be read. +* +* +* \pre This function is called after the device has been initialized and the JESD204B framer is enabled +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device is a pointer to the device settings structure +* \param framerSel Select framer to get SYSREF input for (Valid ADI_ADRV9025_FRAMER_0, ADI_ADRV9025_FRAMER_1, ADI_ADRV9025_FRAMER_2) +* \param enable is a pointer to the value returned. Valid values are 0 and 1. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_FramerSysrefCtrlGet(adi_adrv9025_Device_t* device, + adi_adrv9025_FramerSel_e framerSel, + uint8_t* enable); + +/** + * \brief Enables or disables the external SYSREF JESD204b signal to the transceiver's deframers + * + * \pre This function is called after the device has been initialized and the JESD204B deframer is enabled + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device is a pointer to the device settings structure + * \param deframerSel Select deframer to enable/disable SYSREF input for (Valid ADI_ADRV9025_DEFRAMER_0, ADI_ADRV9025_DEFRAMER_1 or ADI_ADRV9025_DEFRAMER_0_AND_1) + * \param enable = '1' enables SYSREF to deframer, '0' disables SYSREF to deframer + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + * + * TODO: Could pass structure instead of just enable, allow to set sysref options */ +int32_t adi_adrv9025_DeframerSysrefCtrlSet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSel, + uint8_t enable); + +/** +* \brief Reads the bit indicating external SYSREF JESD204b signal of the transceiver's deframers. Only status for one channel +* \ at a time can be read. +* +* +* \pre This function is called after the device has been initialized and the JESD204B framer is enabled +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device is a pointer to the device settings structure +* \param deframerSel Select deframer to get SYSREF input for (Valid ADI_ADRV9025_DEFRAMER_0, ADI_ADRV9025_DEFRAMER_1) +* \param enable enable is a pointer to the value returned. Valid values are 0 and 1. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DeframerSysrefCtrlGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSel, + uint8_t* enable); + +/** +* \brief Reads the ADRV9025 framer status for the framer selected by the framerSel input parameter +* +* \pre The Rx JESD204B/JESD204C link(s) needs to be configured and running to use this function +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* Status for JESD204B: +* framerStatus->status | Description +*----------------------|----------------------------------------------------------------------------- +* [7] | Reserved +* [6] | Reserved +* [5] | Reserved +* [4] | Reserved +* [3] |Current SYNCBIN level(1 = high, 0 = low) +* [2] |SYSREF phase error - a new SYSREF had different timing than the first that set the LMFC timing. +* [1] |SYSREF phase established by framer +* [0] |Flag indicating that configuration parameters are not supported when set(1) +* +* framerSynbcNeCount : 8 bit counter of negative edge Sync transitions +* +* qbfStateStatus | Description +*-----------------------|----------------------------------------------------------------------------- +* [7] | Reserved +* [6] | Reserved +* [5] | Reserved +* [4] | Reserved +* [3] | Reserved +* [2] | QBF bit 2 +* [1] | QBF bit 1 +* [0] | QBF bit 0 +* +* syncNSel | Description +*-----------------------|----------------------------------------------------------------------------- +* [7] | Reserved +* [6] | Reserved +* [5] | Reserved +* [4] | Reserved +* [3] | Reserved +* [2] | Syncb crossbar select +* [1] | Syncb crossbar select +* [0] | Syncb crossbar select +* +* Status for JESD204C: +* framerStatus->status | Description +*-----------------------|----------------------------------------------------------------------------- +* [0] | Sysref received bit +* +* \param device is a pointer to the device settings structure +* \param framerSel Read back the framer status of the selected framer (Framer0, Framer1 or Framer2) +* \param framerStatus is the RX framer status structure read +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_FramerStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_FramerSel_e framerSel, + adi_adrv9025_FramerStatus_t* framerStatus); + +/** + * \brief Reads the status of the requested deframer + * + * \pre The Tx JESD204B/JESD204C link(s) needs to be configured and running to use this function + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * Status for JESD204B: + * deframerStatus | Bit Name | Description + * ----------------|--------------------------|-------------------------------------------------- + * [7] | Valid checksum | 1 if the checksum calculated by the ADRV9025 matched the one sent in the ILAS data. + * [6] | EOF Event | This bit captures the internal status of the framer End of Frame event. Value =1 if framing error during ILAS + * [5] | EOMF Event | This bit captures the internal status of the framer End of Multi-Frame event. Value =1 if framing error during ILAS + * [4] | FS Lost | This bit captures the internal status of the framer Frame Symbol event. Value =1 if framing error during ILAS or user data (invalid replacement characters) + * [3] | Reserved | Reserved + * [2] | User Data Valid | =1 when in user data (deframer link is up and sending valid DAC data) + * [1] | SYSREF Received | Deframer has received the external SYSREF signal + * [0] | Syncb level | Current level of Syncb signal internal to deframer (=1 means link is up) + * + * Status for JESD204C: + * deframerStatus | Bit Name | Description + * ----------------|--------------------------|-------------------------------------------------- + * [2:0] | Current lock state | These 3 bits indicate state of JESD204C Lock + * + * An explanation of what each the value of the 3 bits relates to is below: + * value | Description + * ----------------|----------------------------------------------------------------------------- + * 0 | Reset + * 1 | Unlocked + * 2 | Block(Blocks aligned) + * 3 | M_Block(Lanes aligned) + * 4 | E_M_Block(Multiblock aligned) + * 5 | FEC_BUF + * 6 | FEC_READY (Good State!) + * 7 | Reserved + * + * \param device is a pointer to the device settings structure + * \param deframerSel Select the deframer to read back the status of + * \param deframerStatus 8bit deframer status word return value for each lane + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + * + * TODO: Update to return a structure with more detailed info? */ +int32_t adi_adrv9025_DeframerStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSel, + adi_adrv9025_DeframerStatus_t* deframerStatus); + +/**************************************************************************** + * Runtime functions + **************************************************************************** + */ + +/**************************************************************************** + * Helper functions + **************************************************************************** + */ + +/** + * \brief Sets the DAC sample crossbar for the specified ADRV9025 deframer + * + * \pre This function is called after JESD204B initialization + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to ADRV9025 device data structure containing settings + * \param deframerSel adi_adrv9025_DeframerSel_e enumerated data type for DAC crossbar link selection + * \param dacXbar Pointer to the adi_adrv9025_DacSampleXbarCfg_t enumerated data + * type used to map any deframer output to a specific DAC channel + * I or Q converter input for Tx + * + * Note: Outputs greater than the JESD204 M-1 value programmed at initialization for the selected deframer will be disabled. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_DacSampleXbarSet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSel, + adi_adrv9025_DacSampleXbarCfg_t* dacXbar); + +/** + * \brief Gets the DAC sample crossbar for the specified ADRV9025 deframer + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to ADRV9025 device data structure containing settings + * \param deframerSel adi_adrv9025_DeframerSel_e enumerated data type for DAC crossbar link selection + * \param dacXbar Pointer to the adi_adrv9025_DacSampleXbarCfg_t enumerated data + * type used to map any deframer output to a specific DAC + * channel I or Q converter input for Tx where read back + * values are returned. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_DacSampleXbarGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSel, + adi_adrv9025_DacSampleXbarCfg_t* dacXbar); + +/** + * \brief Sets the ADC sample crossbar to map Rx1/Rx2/Rx3/Rx4/ORx1/ORx2 'I/Q' data to + * the chosen JESD204B framer's converter inputs. During standard operation, ADC crossbar + * selection is being managed by streams. This function should be used for debug purposes. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to ADRV9025 device data structure containing settings + * \param framerSel Selects the JESD204 framer to set the ADC crossbar for. + * Only 1 framer may be selected at a time from the enum. + * + * \param adcXbar Pointer to structure containing ADC converter crossbar settings for the specified JESD204 framer. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_AdcSampleXbarSet(adi_adrv9025_Device_t* device, + adi_adrv9025_FramerSel_e framerSel, + adi_adrv9025_AdcSampleXbarCfg_t* adcXbar); + +/** + * \brief Gets the ADC sample crossbar converter configuration map for + * the chosen JESD204B framer converter + * + * \pre This function is called after JESD204B initialization + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to ADRV9025 device data structure containing settings + * \param framerSel Selects the JESD204 framer to get the ADC crossbar for. + * Only 1 framer may be selected at a time from the enum. + * + * \param adcXbar Pointer to structure containing ADC converter crossbar settings for the specified JESD204 framer. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_AdcSampleXbarGet(adi_adrv9025_Device_t* device, + adi_adrv9025_FramerSel_e framerSel, + adi_adrv9025_AdcSampleXbarCfg_t* adcXbar); + +/**************************************************************************** + * Debug functions + **************************************************************************** + */ + +/** + * \brief Selects the PRBS type and enables or disables RX Framer PRBS generation + * + * This is a debug function to be used for debug of the Rx JESD204B lanes. + * Rx data transmission on the JESD204B link(s) is not possible + * when the framer test data is activated. To disable PRBS call this function + * again with the framer data source set to FTD_ADC_DATA. + * + * \pre This function may be called any time after device initialization + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device is a pointer to the device settings structure + * \param frmTestDataCfg is a pointer to a structure which contains the framer(s) of interest, testDataSource and injectPoint + + * + *\retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_FramerTestDataSet(adi_adrv9025_Device_t* device, + adi_adrv9025_FrmTestDataCfg_t* frmTestDataCfg); + +/** +* \brief Gets the PRBS Framer Test Mode and Inject Points +* +* This is a debug function to be used for debug of the Rx JESD204B lanes. +* Rx data transmission on the JESD204B link(s) is not possible +* when the framer test data is activated. +* +* \pre This function may be called any time after device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device is a pointer to the device settings structure +* \param framerSelect contains the framer of interest +* \param frmTestDataCfg is a pointer to a structure which contains testDataSource and injectPoint +* +*\retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_FramerTestDataGet(adi_adrv9025_Device_t* device, + adi_adrv9025_FramerSel_e framerSelect, + adi_adrv9025_FrmTestDataCfg_t* frmTestDataCfg); + +/** + * \brief Injects an error into the Framer test data by inverting the data + * + * This is a debug function to be used for debug of the the Rx JESD204B lanes. + * Rx data transmission on the JESD204B link(s) is not possible + * when the framer test data is activated. + * + * \pre This function is called after the framer test data is enabled. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device is a pointer to the device settings structure + * \param framerSelect Select the desired framer ADI_ADRV9025_FRAMER_0, ADI_ADRV9025_FRAMER_1, ADI_ADRV9025_FRAMER_2 + * \param laneMask is an eight bit mask allowing selection of lanes 0-7 (at package balls) for the selected framer + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_FramerTestDataInjectError(adi_adrv9025_Device_t* device, + adi_adrv9025_FramerSel_e framerSelect, + uint8_t laneMask); + +/** + * \brief Configures and enables or disables the transceiver's lane/sample PRBS + * checker. + * + * This is a debug function to be used for debug of the Tx JESD204B lanes. + * The Tx link(s) need to be configured and on to use this function. If the + * checkerLocation is TAL_PRBSCHECK_LANEDATA, the PRBS is checked at the + * output of the deserializer. If the checkLocation is TAL_PRBSCHECK_SAMPLEDATA + * the PRBS data is expected to be framed JESD204b data and the PRBS is checked + * after the JESD204b data is deframed. For the sample data, there is only + * a PRBS checker on deframer output 0. The lane PRBS has a checker on each + * deserializer lane. + * + * \pre This function may be called any time after device initialization + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device is a pointer to the device settings structure + * \param dfrmPrbsCfg Pointer to adi_adrv9025_DfrmPrbsCfg_t data structure. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_DfrmPrbsCheckerStateSet(adi_adrv9025_Device_t* device, + adi_adrv9025_DfrmPrbsCfg_t* dfrmPrbsCfg); + +int32_t adi_adrv9025_DfrmPrbsCheckerStateGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DfrmPrbsCfg_t* dfrmPrbsCfg); + +/** +* \brief Clears the deserializer lane and deframer sample PRBS error counters +* +* \pre The device must be initialized to a profile, so that the CLKPLL and +* deserializer clock dividers are setup. If reading PRBS samples framed +* in the JESD204 data, the JESD204 deframer must be configured. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device is a pointer to the device settings structure + +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DfrmPrbsCountReset(adi_adrv9025_Device_t* device); + +/** + * \brief Clears the deserializer lane and deframer sample PRBS error counters + * + * In the case that the PRBS checker is set to check at the deframer output + * sample, there is only a checker on the Deframer Sample 0 output. In this + * case the lane function parameter is ignored and the sample 0 PRBS counter + * is returned. + * + * \pre The device must be initialized to a profile, so that the CLKPLL and + * deserializer clock dividers are setup. If reading PRBS samples framed + * in the JESD204 data, the JESD204 deframer must be configured. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the device settings structure + * \param counters Pointer to PRBS Error counter structure to be returned + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_DfrmPrbsErrCountGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DfrmPrbsErrCounters_t* counters); + +/** + * \brief Compares received Lane0 ILAS configuration to ADRV9025 deframer + * configuration and returns 32-bit mask indicating values that + * mismatched. Actual lane0 ILAS configuration and deframer + * configuration values can be obtained by passing a pointer to a + * structure of type adi_adrv9025_DfrmCompareData_t. + * + * \pre The Rx JESD204B link(s) needs to be configured and running to use + * this function + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * mismatch Mask| Description + * -------------|------------------------------------------ + * [14] | Lane0 Checksum, 0 = match, 1 = mismatch + * [13] | HD, 0 = match, 1 = mismatch + * [12] | CF, 0 = match, 1 = mismatch + * [11] | S, 0 = match, 1 = mismatch + * [10] | NP, 0 = match, 1 = mismatch + * [9] | CS, 0 = match, 1 = mismatch + * [8] | N, 0 = match, 1 = mismatch + * [7] | M, 0 = match, 1 = mismatch + * [6] | K, 0 = match, 1 = mismatch + * [5] | F, 0 = match, 1 = mismatch + * [4] | SCR, 0 = match, 1 = mismatch + * [3] | L, 0 = match, 1 = mismatch + * [2] | LID0, 0 = match, 1 = mismatch + * [1] | BID, 0 = match, 1 = mismatch + * [0] | DID, 0 = match, 1 = mismatch + * + * \param device Pointer to the device settings structure + * \param deframerSelect Enum indicating which deframer to address. + * \param dfrmData Pointer to a adi_adrv9025_DfrmCompareData_t structure that + * returns the deframer ILAS and configuration settings as well as the + * mismatch flag and zero data flag. If the zero flag is set to zero, + * then no valid ILAS data found indicating link is not enabled. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_DfrmIlasMismatchGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect, + adi_adrv9025_DfrmCompareData_t* dfrmData); + +/** + * \brief Reads the IRQ interrupt clear register of the specified deframer. + * This function reads the contents of the deframer IRQ clear register. Use this function whenever a general purpose (GP) + * deframer IRQ asserts to find the maskable deframer IRQ sources. Note: Deframer IRQ sources Elastic Buffer Error Flag, + * Sysref Buffer Error, and the four Lane FIFO Async Error IRQ sources are always enabled and can not be masked in the + * interrupt clear register. + * \brief Not currently implemented + * + * \pre This function may be called any time after JESD204B link initialization + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device is a pointer to the device settings structure + * \param deframerSelect selects the deframer to interrogate. + * \param irqMask is a pointer to the bit mask value containing the contents of the deframer IRQ Clear Register + * + * Bit | Description + * -------------|----------------------------------------------------------------------------- + * [15] | UnUsed + * [14] | UnUsed + * [13] | UnUsed + * [12] | UnUsed + * [11] | UnUsed + * [10] | UnUsed + * [9] | UnUsed + * [8] | CMM - Configuration mismatch for lane0 0 = No Interrupt, 1 = Interrupt Asserted + * [7] | BD - Bad Disparity error counter 0 = No Interrupt, 1 = Interrupt Asserted + * [6] | Not-In-Table error counter 0 = No Interrupt, 1 = Interrupt Asserted + * [5] | Unexpected K error counter 0 = No Interrupt, 1 = Interrupt Asserted + * [4] | ILD - Inter-lane De-skew 0 = No Interrupt, 1 = Interrupt Asserted + * [3] | ILS - Initial lane synce 0 = No Interrupt, 1 = Interrupt Asserted + * [2] | GCS - Good Check Sum 0 = No Interrupt, 1 = Interrupt Asserted + * [1] | FS - Frame Sync 0 = No Interrupt, 1 = Interrupt Asserted + * [0] | CSG - Code Group Sync 0 = No Interrupt, 1 = Interrupt Asserted + * + * + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_DfrmIrqMaskGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect, + adi_adrv9025_DeframerIrq_Mask_Vector_t* irqMask); + +/** + * \brief Writes the IRQ interrupt clear register of the specified deframer. + * This function writes the specified IRQ mask value to the deframer IRQ clear register. Use this function whenever a general purpose (GP) + * deframer IRQ asserts to clear the pending maskable deframer IRQ or to enable/disable deframer interrupt sources. Note: Deframer IRQ sources + * Elastic Buffer Error Flag, Sysref Buffer Error, and the four Lane FIFO Async Error IRQ sources are always enabled and can not be masked in the + * interrupt clear register. This function does not read-modify-write the interrupt clear register. To manually clear the interrupt, write + * a one (set) to disable or mask the bit of the interrupt followed by writing a zero (clear) to enable the bit of the interrupt. However, if the interrupt condition + * still exists after setting the mask bit, the corresponding IRQ vector bit will re-assert. + * \brief Not currently implemented + * + * \pre This function may be called any time after Jesd204B link initialization + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device is a pointer to the device settings structure + * \param deframerSelect selects the deframer to interrogate. + * \param irqMask is the bit mask value to be written to the deframer IRQ Clear Register (this is not a read-modify-write) + * + * Bit | Description + * -------------|----------------------------------------------------------------------------- + * [15] | UnUsed + * [14] | UnUsed + * [13] | UnUsed + * [12] | UnUsed + * [11] | UnUsed + * [10] | UnUsed + * [9] | UnUsed + * [8] | CMM - Configuration mismatch for lane0 0 = No Interrupt, 1 = Interrupt Asserted + * [7] | BD - Bad Disparity error counter 0 = No Interrupt, 1 = Interrupt Asserted + * [6] | Not-In-Table error counter 0 = No Interrupt, 1 = Interrupt Asserted + * [5] | Unexpected K error counter 0 = No Interrupt, 1 = Interrupt Asserted + * [4] | ILD - Inter-lane De-skew 0 = No Interrupt, 1 = Interrupt Asserted + * [3] | ILS - Initial lane synce 0 = No Interrupt, 1 = Interrupt Asserted + * [2] | GCS - Good Check Sum 0 = No Interrupt, 1 = Interrupt Asserted + * [1] | FS - Frame Sync 0 = No Interrupt, 1 = Interrupt Asserted + * [0] | CSG - Code Group Sync 0 = No Interrupt, 1 = Interrupt Asserted + * + * + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_DfrmIrqMaskSet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect, + adi_adrv9025_DeframerIrq_Mask_Vector_t irqMask); + +/** + * \brief Write the IRQ interrupt clear register for the specified deframer. + * This function clears all deframer IRQ sources. Use this function whenever a general purpose (GP) + * deframer IRQ asserts to clear the pending deframer IRQ. + * \brief Not currently implemented + * + * \pre This function may be called any time after JESD204 link initialization + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device is a pointer to the device settings structure + * \param deframerSelect selects the deframer to interrogate. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_DfrmIrqSourceReset(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect); + +/** + * \brief Read the IRQ interrupt source registers for the specified deframer. + * This function fetches the contents of the deframer IRQ Vector register and other IRQ sources. Use this function whenever + * a general purpose (GP) deframer IRQ asserts to determine the source of the deframer IRQ. Common IRQ sources are Bad Disparity (BD), + * Not-In-Table (NIT), and Unexpected K-char (UEK) counters greater than the specified error threshold count value. + * \brief Not currently implemented + * + * \pre This function may be called any time after JESD204 link initialization + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device is a pointer to the device settings structure + * \param deframerSelect selects the deframer to interrogate. + * \param irqSourceValue is a pointer to a bit mask containing the status of the IRQ Vector source register at read time. + * + * Bit | Description + * -------------|----------------------------------------------------------------------------- + * [15] | UnUsed + * [14] | UnUsed + * [13] | UnUsed + * [12] | UnUsed + * [11] | UnUsed + * [10] | UnUsed + * [9] | UnUsed + * [8] | CMM - Configuration mismatch for lane0 0 = No Interrupt, 1 = Interrupt Asserted + * [7] | BD - Bad Disparity error counter 0 = No Interrupt, 1 = Interrupt Asserted + * [6] | Not-In-Table error counter 0 = No Interrupt, 1 = Interrupt Asserted + * [5] | Unexpected K error counter 0 = No Interrupt, 1 = Interrupt Asserted + * [4] | ILD - Inter-lane De-skew 0 = No Interrupt, 1 = Interrupt Asserted + * [3] | ILS - Initial lane synce 0 = No Interrupt, 1 = Interrupt Asserted + * [2] | GCS - Good Check Sum 0 = No Interrupt, 1 = Interrupt Asserted + * [1] | FS - Frame Sync 0 = No Interrupt, 1 = Interrupt Asserted + * [0] | CSG - Code Group Sync 0 = No Interrupt, 1 = Interrupt Asserted + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_DfrmIrqSourceGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect, + adi_adrv9025_DeframerIrq_Mask_Vector_t* irqSourceValue); + +/** +* \brief Reset the serializer +* +* Used in the initialization sequence by passing the serdes PLL frequency. If a serdes PLL frequency is provided, it +* will be greater than zero in the init structure member. Otherwise, the init structure member will be initialized to +* a value of zero causing the CLK PLL to be the selected. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device is a pointer to the device settings structure +* \param pllClkSource is flag indicating which pll is the serializer clock source: >0 SERDES PLL, 0 = Clocking PLL. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_SerializerReset(adi_adrv9025_Device_t* device, + uint32_t pllClkSource); + +/** +* \brief Used to configure and reset the deframer error counters Bad Disparity Error (BD), +* Not-In-Table (NIT), Unexpected K-char (UEK). +* +* This function allows individual counter enable/disable, reset, and configuration control +* for all lanes of a single deframer. +* This function will set the error counter interrupt bits at deframer interrupt request mask according to interruptEnable input +* +* \pre This function may be called any time after Jesd link initialization +* +* \dep_begin +* \dep{device->devHalInfo} +* \dep_end +* +* \param device is a pointer to the device settings structure +* \param deframerSelect selects the deframer of interest, DEFRAMER_0, DEFRAMER_1 +* \param interruptEnable argument to enable/disable GPINT in case error counters overflow 255 +* \param laneNumber Enum selecting the lane number to set config. +* \param errCounterControl 8-bit mask for enabling/disabling and resetting individual counters. +* +* bit | Lane +* -----|------------------ +* 0 | Bad Disparity Error 0 = disable, 1 = enable +* 1 | Not-In-Table (NIT) 0 = disable, 1 = enable +* 2 | Unexpected K-char (UEK) 0 = disable, 1 = enable +* 3 | Reserved +* 4 | Bad Disparity Error 0 = Do not reset counter, 1 = Reset counter to zero +* 5 | Not-In-Table (NIT) 0 = Do not reset counter, 1 = Reset counter to zero +* 6 | Unexpected K-char (UEK) 0 = Do not reset counter, 1 = Reset counter to zero +* 7 | Reserved +* +* \param errCounterHoldCfg 8-bit mask for configuring the deframer error counters to stop counting +* on overflow from 0xFF or to reset and continue counting. +* +* bit | Lane +* -----|------------------ +* 0 | Bad Disparity Error 0 = Reset and continue counting, 1 = Stop counting at 0xFF overflow +* 1 | Not-In-Table (NIT) 0 = Reset and continue counting, 1 = Stop counting at 0xFF overflow +* 2 | Unexpected K-char (UEK) 0 = Reset and continue counting, 1 = Stop counting at 0xFF overflow +* 3 | Reserved +* 4 | Reserved +* 5 | Reserved +* 6 | Reserved +* 7 | Reserved +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DfrmErrCntrCntrlSet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect, + adi_adrv9025_DfrmErrCounterIrqSel_e interruptEnable, + uint8_t laneNumber, + uint8_t errCounterControl, + uint8_t errCounterHoldCfg); + +/** +* \brief Used to read the configuration for the deframer error counters Bad Disparity Error (BD), +* Not-In-Table (NIT), Unexpected K-char (UEK). +* +* \pre This function may be called any time after Jesd link initialization +* +* \dep_begin +* \dep{device->devHalInfo} +* \dep_end +* +* \param device is a pointer to the device settings structure +* \param deframerSelect selects the deframer of interest, DEFRAMER_A, DEFRAMER_B +* \param laneNumber Enum selecting the lane number to set config. +* \param errCounterControl Pointer to 8-bit variable containing individual counters enable bits. +* +* bit | Lane +* -----|------------------ +* 0 | Bad Disparity Error 0 = disable, 1 = enable +* 1 | Not-In-Table (NIT) 0 = disable, 1 = enable +* 2 | Unexpected K-char (UEK) 0 = disable, 1 = enable +* 3 | Reserved +* 4 | Reserved +* 5 | Reserved +* 6 | Reserved +* 7 | Reserved +* +* \param errCounterHoldCfg Pointer to 8-bit variable containing configuration for deframer error counters to stop counting +* on overflow from 0xFF or to reset and continue counting. +* +* bit | Lane +* -----|------------------ +* 0 | Bad Disparity Error 0 = Reset and continue counting, 1 = Stop counting at 0xFF overflow +* 1 | Not-In-Table (NIT) 0 = Reset and continue counting, 1 = Stop counting at 0xFF overflow +* 2 | Unexpected K-char (UEK) 0 = Reset and continue counting, 1 = Stop counting at 0xFF overflow +* 3 | Reserved +* 4 | Reserved +* 5 | Reserved +* 6 | Reserved +* 7 | Reserved +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DfrmErrCntrCntrlGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint8_t laneNumber, + uint8_t* errCounterControl, + uint8_t* errCounterHoldCfg); + +/** +* \brief Used to read the deframer lane status and error counter values. +* +* This function returns the status and error counter values for the selected deframer +* and lane. Returned counter values include UnExpected K-charactoer (UEK), +* Not-In-Table (NIT), Initial Lane Synchronization (ILS), Inter-Lane De-skew (ILD), +* Frame Sync (FS), Computed CheckSum (CCS), Code Group Sync (CGS), Bad Disparity (BD). +* +* Lane Status +* Bit | Description +*---------|------------------------------------------------------------- +* [7] | UEK Error, 0 = No Error, 1 = Error +* [6] | NIT Error, 0 = No Error, 1 = Error +* [5] | ILS Status, 0 = Not Completed, 1 = Completed Successfully +* [4] | ILD Status, 0 = Not Completed, 1 = Completed Successfully +* [3] | FS Status, 0 = Not Completed, 1 = Completed Successfully +* [2] | CCS Status, 0 = Not Completed, 1 = Completed Successfully +* [1] | CGS Status, 0 = Not Completed, 1 = Completed Successfully +* [0] | BD Error, 0 = No Error, 1 = Error +* +* \pre This function may be called any time after Jesd link initialization +* +* \dep_begin +* \dep{device->devHalInfo} +* \dep_end +* +* \param device is a pointer to the device settings structure +* \param deframerSelect selects the deframer of interest, DEFRAMER_A, DEFRAMER_B +* \param laneNumber selects the lane to read (values from 0 - 7) +* \param errCounterStatus structure for returning the lane status and error count values. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DfrmErrCounterStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint8_t laneNumber, + adi_adrv9025_DfrmErrCounterStatus_t* errCounterStatus); + +/** +* \brief Used to get a deframer link condition up or down +* +* This function is called to get a deframer User Data Ready state bit. +* +* \dep_begin +* \dep{device->devHalInfo} +* \dep_end +* +* \param device is a pointer to the device settings structure +* \param deframerSelect Enum indicating which deframer to address. +* \param dfrmLinkCondition pointer to a 8 bit value +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DfrmLinkConditionGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint8_t* dfrmLinkCondition); + +/** +* \brief For the lane selected, runs a Static Phase Offset sweep to measure the horizontal eye opening and stores results in +* the spoSweepResults struct +* +* The function assumes valid PRBS test is running for the selected lane +* +* \dep_begin +* \dep{device->devHalInfo} +* \dep_end +* +* \param device is a pointer to the device settings structure +* \param laneNumber selects the lane to read +* \param spoSweepResults pointer to an empty structure that will hold the results of the sweep +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_adrv9025_DesEyeSweep(adi_adrv9025_Device_t* device, + uint8_t laneNumber, + adi_adrv9025_DesEyeSweepResults_t* spoSweepResults); + +/** +* \brief Enable/Disable the automatic underflow protection for the buffer. +* By default the protection is enabled +* +* \pre This API must be called before the device is programmed +* +* \dep_begin +* \dep{device->devHalInfo} +* \dep_end +* +* \param device is a pointer to the device settings structure +* \param bufferProtectionSet Data to be configured, 0 = Disable, 1 = Enable +* \param deframerSelect selects the deframer of interest, DEFRAMER_A, DEFRAMER_B +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DfrmBufferProtectionSet(adi_adrv9025_Device_t *device, + uint8_t bufferProtectionSet, + adi_adrv9025_DeframerSel_e deframerSelect); + +/** +* \brief API will return the current state of the buffer protection status i.e. If buffer protection is enabled or disabled +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param deframerSelect Desired deframer to read +* \param bufferProtectionGet Pointer the will return the status. 0 = Disabled, 1 = Enabled +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +* +*/ +int32_t adi_adrv9025_DfrmBufferProtectionGet(adi_adrv9025_Device_t *device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint8_t *bufferProtectionGet); + +/** +* \brief This function will return the elastic FIFO depth +* +* \pre Buffer protection is enabled +* \pre Buffer protection is active +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param deframerSelect selects the deframer of interest, DEFRAMER_A, DEFRAMER_B +* \param channelId Register that will be read (0 = A, 1 = B, 2 = C, 3 = D) +* \param fifoDepth Pointer that will hold the elastic FIFO depth. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_adrv9025_DfrmFifoDepthGet(adi_adrv9025_Device_t *device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint8_t channelId, + uint8_t *fifoDepth); + +/** +* \brief Reads buffer protection active bit +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param deframerSelect selects the deframer of interest, DEFRAMER_A, DEFRAMER_B +* \param bufferProtectionStatus Pointer that will hold the current status of active bit. +* 0 = Buffer protection not active +* 1 = Buffer protection active. Buffer read and write pointers were too close with the chosen LMFC offset setting +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +* +*/ +int32_t adi_adrv9025_DfrmBufferProtectionStatusGet(adi_adrv9025_Device_t *device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint8_t *bufferProtectionStatus); + +/** +* \brief This API allows setting the LMFC offset value for the selected Deframer +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param deframerSelect selects the deframer of interest, DEFRAMER_0, DEFRAMER_1 or both +* \param lmfcOffset The LMFC offset value sets to the selected deframer, from 0-65535 +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_adrv9025_DfrmLmfcOffsetSet(adi_adrv9025_Device_t *device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint16_t lmfcOffset); + +/** +* \brief This API allows getting the LMFC offset value for the selected Deframer +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025s device data structure. +* \param deframerSelect selects the deframer of interest, DEFRAMER_0, DEFRAMER_1. DEFRAMER_0_AND_1 is invalid. +* \param lmfcOffset Pointer to LMFC offset value got from the selected deframer +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_adrv9025_DfrmLmfcOffsetGet(adi_adrv9025_Device_t *device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint16_t *lmfcOffset); + +/** +* \brief This function will return the phase difference from when the global LMFC is triggered +* to the point at which the received LMFC is flagged from the lane data. +* +* \pre Buffer protection is enabled +* \pre Buffer protection is active +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param deframerSelect selects the deframer of interest, DEFRAMER_A, DEFRAMER_B +* \param channelId Register that will be read (0 = A, 1 = B, 2 = C, 3 = D) +* \param phaseDiff Pointer that will hold the phase difference. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_adrv9025_DfrmPhaseDiffGet(adi_adrv9025_Device_t *device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint8_t channelId, + uint8_t *phaseDiff); + +/** +* \brief Generates eye diagram metrics for JESD profiles running in QR mode +* +* This function uses the ARM firmware to generate information about the signal eye related to a particular profile +* This method produces a multi level eye, this eye is generated using information based on intersymbol interference post cursors +* ADRV9025 uses a Baud Rate Phase detection method to determine signal eye layout this is to account for higher lane rates which are possible in madura +* This will produce eyediagram output which is reffered to as a 4 level eye. +* +* /pre Dependancies are as follows: +* - Device must be programmed prior to use +* - Requires the use of a profile that operates in Quarter Rate Mode (typically JESD204C Mode link speeds > 16Gbps) +* +* \param device is structure pointer to the ADRV9025 data structure containing settings +* \param lane is a variable which instructs the API with lane to test +* \param results an 2d array of adi_adrv9025_EyeDiagramResultsQR_t structures that will be populated with the results of the eye diagram for the given profile +* results[0][x] will contain members - will contain to positive eye data +* results[1][x] will contain members - will contain negative eye data +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_GenerateEyeDiagramQRMode(adi_adrv9025_Device_t *device, + uint8_t lane, + adi_adrv9025_EyeDiagramResultsQR_t **results); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_DATA_INTERFACE_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_data_interface_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_data_interface_types.h new file mode 100644 index 0000000..2b8322d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_data_interface_types.h @@ -0,0 +1,546 @@ +/** +* \file adi_adrv9025_data_interface_types.h +* \brief Contains ADRV9025 API data interface types +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_DATA_INTERFACE_TYPES_H_ +#define _ADI_ADRV9025_DATA_INTERFACE_TYPES_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define ADI_ADRV9025_NUM_LANES 4 +#define ADI_ADRV9025_FRMR_NUM_OF_CONVERTERS 24 +#define ADRV9025_QR_EYE_NUM_PHASES 36 +/** +* \brief Enum to select desired framer +*/ +typedef enum adi_adrv9025_FramerSel +{ + ADI_ADRV9025_FRAMER_0 = 1, /*!< Framer 0 selected */ + ADI_ADRV9025_FRAMER_1 = 2, /*!< Framer 1 selected */ + ADI_ADRV9025_FRAMER_2 = 4, /*!< Framer 2 selected */ + ADI_ADRV9025_ALL_FRAMERS = 7 /*!< All Framers selected */ + +} adi_adrv9025_FramerSel_e; + +/** +* \brief Enum to select desired deframer +*/ +typedef enum adi_adrv9025_DeframerSel +{ + ADI_ADRV9025_DEFRAMER_0 = 1, /*!< Deframer A selection */ + ADI_ADRV9025_DEFRAMER_1 = 2, /*!< Deframer B selection */ + ADI_ADRV9025_DEFRAMER_0_AND_1 = 3 /*!< Used for cases where Tx1 uses one deframer, Tx2 uses the second deframer */ +} adi_adrv9025_DeframerSel_e; + +/** +* \brief Enumerated list of DAC Sample Xbar options +*/ +typedef enum adi_adrv9025_DacSampleXbarSel +{ + ADI_ADRV9025_DEFRAMER_OUT0 = 0x1, /*!< Deframer out 0 */ + ADI_ADRV9025_DEFRAMER_OUT1 = 0x0, /*!< Deframer out 1 */ + ADI_ADRV9025_DEFRAMER_OUT2 = 0x3, /*!< Deframer out 2 */ + ADI_ADRV9025_DEFRAMER_OUT3 = 0x2, /*!< Deframer out 3 */ + ADI_ADRV9025_DEFRAMER_OUT4 = 0x5, /*!< Deframer out 4 */ + ADI_ADRV9025_DEFRAMER_OUT5 = 0x4, /*!< Deframer out 5 */ + ADI_ADRV9025_DEFRAMER_OUT6 = 0x7, /*!< Deframer out 6 */ + ADI_ADRV9025_DEFRAMER_OUT7 = 0x6, /*!< Deframer out 7 */ + ADI_ADRV9025_DEFRAMER_OUT_DISABLE = 0x7F /*!< Deframer out Disable Value */ +} adi_adrv9025_DacSampleXbarSel_e; + +/** +* \brief Enumerated list of ADC Sample Xbar options +*/ +/* TODO: Verify enum values */ +typedef enum adi_adrv9025_AdcSampleXbarSel +{ + ADI_ADRV9025_ADC_RX1_I = 0x1, /*!< Rx1 I data */ + ADI_ADRV9025_ADC_RX1_Q = 0x0, /*!< Rx1 Q data */ + ADI_ADRV9025_ADC_RX2_I = 0x3, /*!< Rx2 I data */ + ADI_ADRV9025_ADC_RX2_Q = 0x2, /*!< Rx2 Q data */ + ADI_ADRV9025_ADC_RX3_I = 0x5, /*!< Rx3 I data */ + ADI_ADRV9025_ADC_RX3_Q = 0x4, /*!< Rx3 Q data */ + ADI_ADRV9025_ADC_RX4_I = 0x7, /*!< Rx4 I data */ + ADI_ADRV9025_ADC_RX4_Q = 0x6, /*!< Rx4 Q data */ + + ADI_ADRV9025_ADC_DUALBAND_RX1_BAND_A_I = 0x1, /*!< Dualband Rx1 Band A I data */ + ADI_ADRV9025_ADC_DUALBAND_RX1_BAND_A_Q = 0x0, /*!< Dualband Rx1 Band A Q data */ + ADI_ADRV9025_ADC_DUALBAND_RX2_BAND_A_I = 0x3, /*!< Dualband Rx2 Band A I data */ + ADI_ADRV9025_ADC_DUALBAND_RX2_BAND_A_Q = 0x2, /*!< Dualband Rx2 Band A Q data */ + ADI_ADRV9025_ADC_DUALBAND_RX3_BAND_A_I = 0x5, /*!< Dualband Rx3 Band A I data */ + ADI_ADRV9025_ADC_DUALBAND_RX3_BAND_A_Q = 0x4, /*!< Dualband Rx3 Band A Q data */ + ADI_ADRV9025_ADC_DUALBAND_RX4_BAND_A_I = 0x7, /*!< Dualband Rx4 Band A I data */ + ADI_ADRV9025_ADC_DUALBAND_RX4_BAND_A_Q = 0x6, /*!< Dualband Rx4 Band A Q data */ + + ADI_ADRV9025_ADC_DUALBAND_RX1_BAND_B_I = 0x9, /*!< Dualband Rx1 Band B I data */ + ADI_ADRV9025_ADC_DUALBAND_RX1_BAND_B_Q = 0x8, /*!< Dualband Rx1 Band B Q data */ + ADI_ADRV9025_ADC_DUALBAND_RX2_BAND_B_I = 0xB, /*!< Dualband Rx2 Band B I data */ + ADI_ADRV9025_ADC_DUALBAND_RX2_BAND_B_Q = 0xA, /*!< Dualband Rx2 Band B Q data */ + ADI_ADRV9025_ADC_DUALBAND_RX3_BAND_B_I = 0xD, /*!< Dualband Rx3 Band B I data */ + ADI_ADRV9025_ADC_DUALBAND_RX3_BAND_B_Q = 0xC, /*!< Dualband Rx3 Band B Q data */ + ADI_ADRV9025_ADC_DUALBAND_RX4_BAND_B_I = 0xF, /*!< Dualband Rx4 Band B I data */ + ADI_ADRV9025_ADC_DUALBAND_RX4_BAND_B_Q = 0xE, /*!< Dualband Rx4 Band B Q data */ + + ADI_ADRV9025_ADC_ORX1_I = 0x11, + ADI_ADRV9025_ADC_ORX1_Q = 0x10, + ADI_ADRV9025_ADC_ORX2_I = 0x13, + ADI_ADRV9025_ADC_ORX2_Q = 0x12, + + ADI_ADRV9025_ADC_DISABLE = 0x7F + +} adi_adrv9025_AdcSampleXbarSel_e; + +/** +* \brief Enum of possible Framer Test Data sources +*/ +typedef enum adi_adrv9025_FramerDataSource +{ + ADI_ADRV9025_FTD_ADC_DATA = 0, /*!< Framer test data ADC data source */ + ADI_ADRV9025_FTD_CHECKERBOARD, /*!< Framer test data checkerboard data source */ + ADI_ADRV9025_FTD_TOGGLE0_1, /*!< Framer test data toggle 0 to 1 data source */ + ADI_ADRV9025_FTD_PRBS31, /*!< Framer test data PRBS31 data source */ + ADI_ADRV9025_FTD_PRBS23, /*!< Framer test data PRBS23 data source */ + ADI_ADRV9025_FTD_PRBS15, /*!< Framer test data PRBS15 data source */ + ADI_ADRV9025_FTD_PRBS9, /*!< Framer test data PRBS9 data source */ + ADI_ADRV9025_FTD_PRBS7, /*!< Framer test data PRBS7 data source */ + ADI_ADRV9025_FTD_RAMP, /*!< Framer test data ramp data source */ + ADI_ADRV9025_FTD_PATTERN_REPEAT = 14, /*!< Framer test data 16-bit programmed pattern repeat source */ + ADI_ADRV9025_FTD_PATTERN_ONCE = 15 /*!< Framer test data 16-bit programmed pattern executed once source */ + +} adi_adrv9025_FramerDataSource_e; + +/** +* \brief Enum of Framer test data injection points +*/ +typedef enum adi_adrv9025_FramerDataInjectPoint +{ + ADI_ADRV9025_FTD_FRAMERINPUT = 0, /*!< Framer test data injection point at framer input */ + ADI_ADRV9025_FTD_SERIALIZER, /*!< Framer test data injection point at serializer input */ + ADI_ADRV9025_FTD_POST_LANEMAP /*!< Framer test data injection point after lane mapping */ + +} adi_adrv9025_FramerDataInjectPoint_e; + +/** +* \brief Enum for JESD204B PRBS generated types +*/ +typedef enum adi_adrv9025_DeframerPrbsOrder +{ + ADI_ADRV9025_PRBS_DISABLE = 0, /*!< Deframer PRBS pattern disable */ + ADI_ADRV9025_PRBS7, /*!< Deframer PRBS7 pattern select */ + ADI_ADRV9025_PRBS9, /*!< Deframer PRBS9 pattern select */ + ADI_ADRV9025_PRBS15, /*!< Deframer PRBS15 pattern select */ + ADI_ADRV9025_PRBS31, /*!< Deframer PRBS31 pattern select */ + ADI_ADRV9025_USERDATA /*!< Deframer user supplied pattern select */ + +} adi_adrv9025_DeframerPrbsOrder_e; + +/** +* \brief Enum for JESD204B deserializer / deframer PRBS selection +*/ +typedef enum adi_adrv9025_DeframerPrbsCheckLoc +{ + ADI_ADRV9025_PRBSCHECK_LANEDATA = 0, /*!< Check PRBS at deserializer lane output (does not require JESD204b link) */ + ADI_ADRV9025_PRBSCHECK_SAMPLEDATA /*!< Check PRBS at output of deframer (JESD204b deframed sample) */ + +} adi_adrv9025_DeframerPrbsCheckLoc_e; + +/** +* \brief Enum to select GPINT enable/disable for deframer error counters +*/ +typedef enum adi_adrv9025_DfrmErrCounterIrqSel +{ + ADI_ADRV9025_DFRM_ERR_COUNT_DISABLE_IRQ = 0, /*!< Don't create GPINT when error counter overflows 255 */ + ADI_ADRV9025_DFRM_ERR_COUNT_ENABLE_IRQ /*!< Create GPINT when error counter overflows 255 */ +} adi_adrv9025_DfrmErrCounterIrqSel_e; + +/** +* \brief Data structure to hold the DAC sample crossbar information +*/ +typedef struct adi_adrv9025_DacSampleXbarCfg +{ + adi_adrv9025_DacSampleXbarSel_e tx1DacChanI; /*!< Sample Crossbar select for Tx1 I channel data*/ + adi_adrv9025_DacSampleXbarSel_e tx1DacChanQ; /*!< Sample Crossbar select for Tx1 Q channel data*/ + adi_adrv9025_DacSampleXbarSel_e tx2DacChanI; /*!< Sample Crossbar select for Tx2 I channel data*/ + adi_adrv9025_DacSampleXbarSel_e tx2DacChanQ; /*!< Sample Crossbar select for Tx2 Q channel data*/ + adi_adrv9025_DacSampleXbarSel_e tx3DacChanI; /*!< Sample Crossbar select for Tx3 I channel data*/ + adi_adrv9025_DacSampleXbarSel_e tx3DacChanQ; /*!< Sample Crossbar select for Tx3 Q channel data*/ + adi_adrv9025_DacSampleXbarSel_e tx4DacChanI; /*!< Sample Crossbar select for Tx4 I channel data*/ + adi_adrv9025_DacSampleXbarSel_e tx4DacChanQ; /*!< Sample Crossbar select for Tx4 Q channel data*/ +} adi_adrv9025_DacSampleXbarCfg_t; + +/** +* \brief Data structure to hold the ADC sample crossbar information +*/ +typedef struct adi_adrv9025_AdcSampleXbarCfg +{ + adi_adrv9025_AdcSampleXbarSel_e conv0; /*!< Sample Crossbar select for converter 0*/ + adi_adrv9025_AdcSampleXbarSel_e conv1; /*!< Sample Crossbar select for converter 1*/ + adi_adrv9025_AdcSampleXbarSel_e conv2; /*!< Sample Crossbar select for converter 2*/ + adi_adrv9025_AdcSampleXbarSel_e conv3; /*!< Sample Crossbar select for converter 3*/ + adi_adrv9025_AdcSampleXbarSel_e conv4; /*!< Sample Crossbar select for converter 4*/ + adi_adrv9025_AdcSampleXbarSel_e conv5; /*!< Sample Crossbar select for converter 5*/ + adi_adrv9025_AdcSampleXbarSel_e conv6; /*!< Sample Crossbar select for converter 6*/ + adi_adrv9025_AdcSampleXbarSel_e conv7; /*!< Sample Crossbar select for converter 7*/ + adi_adrv9025_AdcSampleXbarSel_e conv8; /*!< Sample Crossbar select for converter 8*/ + adi_adrv9025_AdcSampleXbarSel_e conv9; /*!< Sample Crossbar select for converter 9*/ + adi_adrv9025_AdcSampleXbarSel_e conv10; /*!< Sample Crossbar select for converter 10*/ + adi_adrv9025_AdcSampleXbarSel_e conv11; /*!< Sample Crossbar select for converter 11*/ + adi_adrv9025_AdcSampleXbarSel_e conv12; /*!< Sample Crossbar select for converter 12*/ + adi_adrv9025_AdcSampleXbarSel_e conv13; /*!< Sample Crossbar select for converter 13*/ + adi_adrv9025_AdcSampleXbarSel_e conv14; /*!< Sample Crossbar select for converter 14*/ + adi_adrv9025_AdcSampleXbarSel_e conv15; /*!< Sample Crossbar select for converter 15*/ + adi_adrv9025_AdcSampleXbarSel_e conv16; /*!< Sample Crossbar select for converter 15*/ + adi_adrv9025_AdcSampleXbarSel_e conv17; /*!< Sample Crossbar select for converter 15*/ + adi_adrv9025_AdcSampleXbarSel_e conv18; /*!< Sample Crossbar select for converter 15*/ + adi_adrv9025_AdcSampleXbarSel_e conv19; /*!< Sample Crossbar select for converter 15*/ + adi_adrv9025_AdcSampleXbarSel_e conv20; /*!< Sample Crossbar select for converter 15*/ + adi_adrv9025_AdcSampleXbarSel_e conv21; /*!< Sample Crossbar select for converter 15*/ + adi_adrv9025_AdcSampleXbarSel_e conv22; /*!< Sample Crossbar select for converter 15*/ + adi_adrv9025_AdcSampleXbarSel_e conv23; /*!< Sample Crossbar select for converter 15*/ +} adi_adrv9025_AdcSampleXbarCfg_t; + +/** +* \brief Data structure to hold the Framer output lane crossbar information +* +* Note that not all framers have 8 outputs. A physical lane can only be used +* on one framer at a time. +*/ +typedef struct adi_adrv9025_SerLaneXbar +{ + uint8_t lane0FramerOutSel; /*!< Framer output to route to Physical Lane 0 (valid 0-7) */ + uint8_t lane1FramerOutSel; /*!< Framer output to route to Physical Lane 1 (valid 0-7) */ + uint8_t lane2FramerOutSel; /*!< Framer output to route to Physical Lane 2 (valid 0-7) */ + uint8_t lane3FramerOutSel; /*!< Framer output to route to Physical Lane 3 (valid 0-7) */ +} adi_adrv9025_SerLaneXbar_t; + +/** +* \brief Data structure to hold the Deframer input lane crossbar information +* +* Note that not all deframers have 8 inputs. +*/ +typedef struct adi_adrv9025_DeserLaneXbar +{ + uint8_t deframerInput0LaneSel; /*!< Physical lane select for deframer input 0 (valid 0-7) */ + uint8_t deframerInput1LaneSel; /*!< Physical lane select for deframer input 1 (valid 0-7) */ + uint8_t deframerInput2LaneSel; /*!< Physical lane select for deframer input 2 (valid 0-7) */ + uint8_t deframerInput3LaneSel; /*!< Physical lane select for deframer input 3 (valid 0-7) */ +} adi_adrv9025_DeserLaneXbar_t; + +/** +* \brief Data structure to hold ADRV9025 JESD204b DeFramer ILAS configuration settings +*/ +typedef struct adi_adrv9025_DfrmLane0Cfg +{ + uint8_t dfrmDID; /*!< JESD204B Configuration Device ID for ILAS check */ + uint8_t dfrmBID; /*!< JESD204B Configuration Bank ID for ILAS check */ + uint8_t dfrmLID0; /*!< JESD204B Configuration starting Lane ID for ILAS check */ + uint8_t dfrmL; /*!< JESD204B Configuration L = lanes per data converter for ILAS check */ + uint8_t dfrmSCR; /*!< JESD204B Configuration scramble setting for ILAS check */ + uint8_t dfrmF; /*!< JESD204B Configuration F = octets per frame for ILAS check */ + uint8_t dfrmK; /*!< JESD204B Configuration K = frames per multiframe for ILAS check */ + uint8_t dfrmM; /*!< JESD204B Configuration M = number of data converters for ILAS check */ + uint8_t dfrmN; /*!< JESD204B Configuration N = data converter sample resolution for ILAS check */ + uint8_t dfrmCS; /*!< JESD204B Configuration CS = number of control bits transferred per sample per frame for ILAS check */ + uint8_t dfrmNP; /*!< JESD204B Configuration NP = JESD204B word size based on the highest resolution of the data converter for ILAS check */ + uint8_t dfrmS; /*!< JESD204B Configuration S = number of samples/data converter/frame for ILAS check */ + uint8_t dfrmCF; /*!< JESD204B Configuration CF = '0' = control bits appended to each sample, '1' = appended to end of frame for ILAS check */ + uint8_t dfrmHD; /*!< JESD204B Configuration HD = high density bit - samples are contained within lane (0) or divided over more than one lane (1) for ILAS check */ + uint8_t dfrmFCHK0; /*!< JESD204B Configuration checksum for ILAS check lane0 */ +} adi_adrv9025_DfrmLane0Cfg_t; + +/** +* \brief Data structure to hold ADRV9025 JESD204b Framer configuration settings +*/ +typedef struct adi_adrv9025_FrmCfg +{ + uint8_t enableJesd204C; /*!< 1= Enable JESD204C framer, 0 = use JESD204B framer */ + uint8_t bankId; /*!< JESD204B Configuration Bank ID extension to Device ID. Range is 0..15 */ + uint8_t deviceId; /*!< JESD204B Configuration Device ID link identification number. Range is 0..255 */ + uint8_t lane0Id; /*!< JESD204B Configuration starting Lane ID. If more than one lane is used, each lane will increment from the Lane0 ID. Range is 0..31 */ + uint8_t jesd204M; /*!< Number of ADCs (0, 2, or 4) where 2 ADCs are required per receive chain (I and Q). */ + uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K must be modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C). */ + uint8_t jesd204F; /*!< Number of bytes(octets) per frame (Valid 1, 2, 4, 8). */ + uint8_t jesd204Np; /*!< converter sample resolution (12, 16, 24). */ + uint8_t jesd204E; /*!< JESD204C E parameter */ + uint8_t scramble; /*!< Scrambling off if framerScramble = 0, if framerScramble > 0 scrambling is enabled */ + uint8_t serializerLanesEnabled; /*!< Serializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ + uint16_t lmfcOffset; /*!< LMFC offset value for deterministic latency setting. */ + uint8_t syncbInSelect; /*!< Selects SYNCb input source. Where, 0 = use SYNCBIN0 for this framer, 1 = use SYNCBIN1 for this framer, 2 = use SYNCBIN2 */ + uint8_t overSample; /*!< Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples) */ + uint8_t syncbInLvdsMode; /*!< 1 - enable LVDS input pad with 100ohm internal termination, 0 - enable CMOS input pad */ + uint8_t syncbInLvdsPnInvert; /*!< 0 - syncb LVDS PN not inverted, 1 - syncb LVDS PN inverted */ + adi_adrv9025_SerLaneXbar_t serializerLaneCrossbar; /*!< Lane crossbar to map framer lane outputs to physical lanes */ + adi_adrv9025_AdcSampleXbarCfg_t adcCrossbar; /*!< ADC converter to framer input mapping */ + uint8_t newSysrefOnRelink; /*!< Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, '0' = not set */ + uint8_t sysrefForStartup; /*!< 1 = Framer: Require a SYSREF before CGS will be output from serializer, 0: Allow CGS to output before SYSREF occurs (recommended on framer to allow deframer CDR to lock and EQ to train)*/ + uint8_t sysrefNShotEnable; /*!< 1 = Enable SYSREF NShot (ability to ignore first rising edge of SYSREF to ignore possible runt pulses.) */ + uint8_t sysrefNShotCount; /*!< Count value of which SYSREF edge to use to reset LMFC phase, valid range is 0 to 15 */ + uint8_t sysrefIgnoreWhenLinked; /*!< When JESD204 link is up and valid, 1= ignore any sysref pulses */ +} adi_adrv9025_FrmCfg_t; + +/** +* \brief Data structure to hold ADRV9025 JESD204b Link Sharing Framer configuration settings +*/ +typedef struct adi_adrv9025_LinkSharingCfg +{ + uint8_t linkSharingEnabled; /*!< 1 = link sharing enabled. This structure will hold ORx settings (typical); 0 = no link sharing. This structure unused */ + uint8_t linkSharingM; /*!< Number of ADCs (0, 2, or 4) where 2 ADCs are required per receive chain (I and Q). */ + uint8_t linkSharingS; /*!< number of samples per frame */ + uint8_t linkSharingNp; /*!< converter sample resolution (12, 16, 24). */ + adi_adrv9025_AdcSampleXbarCfg_t linkSharingAdcCrossbar; /*!< ADC converter to framer input mapping */ +} adi_adrv9025_LinkSharingCfg_t; + +/** +* \brief Data structure to hold the settings for the deframer configuration +*/ +typedef struct adi_adrv9025_DfrmCfg +{ + uint8_t enableJesd204C; /*!< 1= Enable JESD204C framer, 0 = use JESD204B framer */ + uint8_t bankId; /*!< Extension to Device ID. Range is 0..15 , bankId is not supported for Jrx, returns always 0*/ + uint8_t deviceId; /*!< Link identification number. Range is 0..255 */ + uint8_t lane0Id; /*!< Lane0 ID. Range is 0..31 */ + uint8_t jesd204M; /*!< Number of DACs (0, 2, or 4) - 2 DACs per transmit chain (I and Q) */ + uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K = modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C) */ + uint8_t jesd204F; /*!< Number of bytes(octets) per frame . */ + uint8_t jesd204Np; /*!< converter sample resolution (12, 16) */ + uint8_t jesd204E; /*!< JESD204C E parameter */ + uint8_t scramble; /*!< Scrambling off if scramble = 0, if framerScramble > 0 scrambling is enabled */ + uint8_t deserializerLanesEnabled; /*!< Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ + uint16_t lmfcOffset; /*!< LMFC offset value to adjust deterministic latency. */ + uint8_t syncbOutSelect; /*!< Selects deframer SYNCBOUT pin (0 = SYNCBOUT0, 1 = SYNCBOUT1, 2 = output SYNCB to SYNCBOUT0 and SYNCBOUT1) */ + uint8_t syncbOutLvdsMode; /*!< 1 - enable LVDS output pad, 0 - enable CMOS output pad */ + uint8_t syncbOutLvdsPnInvert; /*!< 0 - syncb LVDS PN not inverted, 1 - syncb LVDS PN inverted */ + uint8_t syncbOutCmosSlewRate; /*!< 0 - fastest rise/fall times, 3 - slowest rise/fall times(not used, always returns 0) */ + uint8_t syncbOutCmosDriveLevel; /*!< 0 - normal cmos drive level, 1 - double cmos drive level */ + adi_adrv9025_DeserLaneXbar_t deserializerLaneCrossbar; /*!< Lane crossbar to map physical lanes to deframer inputs */ + adi_adrv9025_DacSampleXbarCfg_t dacCrossbar; /*!< Deframer output to DAC mapping */ + uint8_t newSysrefOnRelink; /*!< Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, '0' = not set */ + uint8_t sysrefForStartup; /*!< Suggested to enable for deframer so deframer will not assert SYNCB to init the link until SYSREF has occurred, which resets LMFC phase */ + uint8_t sysrefNShotEnable; /*!< 1 = Enable SYSREF NShot (ability to ignore first rising edge of SYSREF to ignore possible runt pulses.) */ + uint8_t sysrefNShotCount; /*!< Count value of which SYSREF edge to use to reset LMFC phase, valid range is 0 to 15 */ + uint8_t sysrefIgnoreWhenLinked; /*!< When JESD204 link is up and valid, 1= ignore any sysref pulses */ +} adi_adrv9025_DfrmCfg_t; + +/** +* \brief Data structure to hold ADRV9025 JESD204b Serializer configuration information +*/ +typedef struct adi_adrv9025_SerCfg +{ + uint8_t serAmplitude; /*!< Serializer amplitude setting. Default = 1. (Range is 0..3) 0 = 1.0 * VTT, 1 = 0.85*VTT, 2 = 0.75*VTT, 3 = 0.5*VTT */ + uint8_t serPreEmphasis; /*!< Serializer pre-emphasis setting. Default = 0 (Range is 0..2) , 0=0dB, 1=3dB, 2=6dB*/ + uint8_t serPostEmphasis; /*!< Serializer Post-emphasis setting. (Valid 0,1,2,3,4) 0=0dB, 1=3dB, 2=6dB, 3=9dB, 4=12dB */ + uint8_t serInvertLanePolarity; /*!< Serializer Lane PN inversion select. Default = 0. Where, bit[0] = 1 will invert lane [0], bit[1] = 1 will invert lane 1, etc. */ +} adi_adrv9025_SerCfg_t; + +/** +* \brief Data structure to hold ADRV9025 JESD204b Deserializer configuration information +*/ +typedef struct adi_adrv9025_DesCfg +{ + uint8_t desInvertLanePolarity; /*!< Deserializer Lane PN inversion select. 1 = Invert PN, 0 = Do nothing */ + uint8_t highBoost; /*!< High Boost Lane enable select. 1 = High Boost enabled, 0 = High Boost disabled */ + uint32_t configOption1; /*!< SERDES init & tracking calibration algorithm parameter */ + uint32_t configOption2; /*!< SERDES init & tracking calibration algorithm parameter */ + uint32_t configOption3; /*!< SERDES init & tracking calibration algorithm parameter */ + uint32_t configOption4; /*!< SERDES init & tracking calibration algorithm parameter */ + uint32_t configOption5; /*!< SERDES init & tracking calibration algorithm parameter */ + uint32_t configOption6; /*!< SERDES init & tracking calibration algorithm parameter */ + uint32_t configOption7; /*!< SERDES init & tracking calibration algorithm parameter */ + uint32_t configOption8; /*!< SERDES init & tracking calibration algorithm parameter */ + uint32_t configOption9; /*!< SERDES init & tracking calibration algorithm parameter */ + uint32_t configOption10; /*!< SERDES init & tracking calibration algorithm parameter */ +} adi_adrv9025_DesCfg_t; + + +/** +* \brief Data structure to hold ADRV9025 Data Configuration controls +*/ +typedef struct adi_adrv9025_JesdDataConfigCtrl +{ + uint8_t enable; /*!< Enables data configuration feature */ + uint8_t configOption1; /*!< Data configuration option 1 */ + uint8_t configOption2; /*!< Data configuration option 2 */ +} adi_adrv9025_JesdDataConfigCtrl_t; + +/** +* \brief Data structure to hold ADRV9025 JESD204b Framer and Deframer configuration information +*/ +typedef struct adi_adrv9025_DataInterfaceCfg +{ + adi_adrv9025_FrmCfg_t framer[3]; /*!< Framer 0/1/2 configuration data structures */ + adi_adrv9025_DfrmCfg_t deframer[2]; /*!< Deframer 0/1 configuration data structures */ + adi_adrv9025_SerCfg_t serCfg[ADI_ADRV9025_NUM_LANES]; /*!< Serializer PHY layer settings */ + adi_adrv9025_DesCfg_t desCfg[ADI_ADRV9025_NUM_LANES]; /*!< Deserializer PHY layer settings */ + adi_adrv9025_LinkSharingCfg_t linkSharingCfg; /*!< Link Sharing configuration. Typically used to store ORx settings when Framer 0 stores Rx settings */ + adi_adrv9025_JesdDataConfigCtrl_t dataCfg; /*!< Data configuration control structure */ + uint8_t channelSelect; /*!< Allows use of control channel */ + uint8_t channelMode; /*!< Allows the LSB of JESD data to be used as control bits when JESD compression is disabled */ +} adi_adrv9025_DataInterfaceCfg_t; + +/** +* \brief Data structure to hold ADRV9025 JESD204b Framer Test data and debug configuration +*/ +typedef struct adi_adrv9025_FrmTestDataCfg +{ + uint8_t framerSelMask; + adi_adrv9025_FramerDataSource_e testDataSource; + adi_adrv9025_FramerDataInjectPoint_e injectPoint; +} adi_adrv9025_FrmTestDataCfg_t; + +/** +* \brief Data structure to hold ADRV9025 JESD204b Deframer PRBS test configuration +*/ +typedef struct adi_adrv9025_DfrmPrbsCfg +{ + adi_adrv9025_DeframerSel_e deframerSel; + adi_adrv9025_DeframerPrbsOrder_e polyOrder; + adi_adrv9025_DeframerPrbsCheckLoc_e checkerLocation; +} adi_adrv9025_DfrmPrbsCfg_t; + +/** +* \brief Data structure to hold ADRV9025 JESD204b Deframer PRBS Error Counter values on readback +*/ +typedef struct adi_adrv9025_DfrmPrbsErrCounters +{ + adi_adrv9025_DeframerPrbsCheckLoc_e sampleSource; /*! Sample or Lane mode. Mode error count and status use zeroth index for sample mode */ + uint8_t errorStatus[ADI_ADRV9025_NUM_LANES]; /*! Bit 0 = Lane inverted, bit 1 = invalid data flag, bit 2 = sample/lane error flag */ + uint32_t laneErrors[ADI_ADRV9025_NUM_LANES]; /*! Lane 0 contains error counters if in sample mode, otherwise errors are maintained per lane */ +} adi_adrv9025_DfrmPrbsErrCounters_t; + +/** +* \brief Data structure to hold ADRV9025 JESD204b Framer status information +*/ +typedef struct adi_adrv9025_FramerStatus +{ + uint8_t status; + uint8_t framerSyncNeCount; /*! Count of SYNCB falling edges */ + uint8_t qbfStateStatus; + uint8_t syncNSel; +} adi_adrv9025_FramerStatus_t; + +/** +* \brief Data structure to hold ADRV9025 JESD204b Deframer status information +*/ +typedef struct adi_adrv9025_DeframerStatus +{ + uint8_t status; + uint8_t reserved; +} adi_adrv9025_DeframerStatus_t; + +/** +* \brief Data structure to hold ADRV9025 JESD204b Deframer Mask and Source register bits +*/ +typedef struct adi_adrv9025_DeframerIrq_Mask_Vector +{ + uint16_t deframer0; + uint16_t deframer1; +} adi_adrv9025_DeframerIrq_Mask_Vector_t; + +/** +* \brief Data structure to hold ADRV9025 JESD204b DeFramer ILAS configuration settings +* for each deframer +*/ +typedef struct adi_adrv9025_DfrmCompareData +{ + uint32_t zeroCheckFlag; /*!< Link Valid Data Flag - if returned all zero then link is not active */ + uint32_t ilasMismatchDfrm; /*!< ILAS mismatch Flag - all set bits indicated mismatch and bit position indicates incorrect value */ + adi_adrv9025_DfrmLane0Cfg_t dfrmIlasData; /*!< Captured ILAS data */ + adi_adrv9025_DfrmLane0Cfg_t dfrmCfgData; /*!< Configured ILAS data */ +} adi_adrv9025_DfrmCompareData_t; +/** +* \brief Data structure to hold ADRV9025 JESD204b Deframer error counter status +*/ +typedef struct adi_adrv9025_DfrmErrCounterStatus +{ + uint8_t laneStatus; /*!< deframer status bits */ + uint8_t bdCntValue; /*!< Bad-Disparity error counter current value */ + uint8_t uekCntValue; /*!< UnExpected-K error counter current value */ + uint8_t nitCntValue; /*!< Not-In-Table error counter current value */ +} adi_adrv9025_DfrmErrCounterStatus_t; + +typedef struct adi_adrv9025_GpInterruptSettings +{ + uint64_t gpIntMaskPin0; /*!< Default setting for GP interrupt Pin 0 mask */ + uint64_t gpIntMaskPin1; /*!< Default setting for GP interrupt Pin 1 mask */ +} adi_adrv9025_GpInterruptSettings_t; + +typedef struct adi_adrv9025_FramerProfileSetting +{ + uint8_t enableJesd204C; /*!< 1= Enable JESD204C framer, 0 = use JESD204B framer */ + uint8_t lane0Id; /*!< JESD204B Configuration starting Lane ID. */ + uint8_t serializerLanesEnabled; /*!< Serializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ +} adi_adrv9025_FramerProfileSetting_t; + +typedef struct adi_adrv9025_DeframerProfileSetting +{ + uint8_t enableJesd204C; /*!< 1= Enable JESD204C framer, 0 = use JESD204B framer */ + uint8_t lane0Id; /*!< JESD204B Configuration starting Lane ID. */ + uint8_t deserializerLanesEnabled; /*!< Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ +} adi_adrv9025_DeframerProfileSetting_t; + +typedef struct adi_adrv9025_JesdDataProfileCfg +{ + adi_adrv9025_FramerProfileSetting_t framerCfg[3]; /*!< Framer 0/1/2 saved configuration */ + adi_adrv9025_DeframerProfileSetting_t deframerCfg[2]; /*!< Deframer 0/1 saved configuratio */ +} adi_adrv9025_JesdDataProfileCfg_t; + +/** +* \brief Enum to select desired deframer lane +*/ +typedef enum adi_adrv9025_LaneSel +{ + ADI_ADRV9025_LANE_0 = 0x01, /*!< LANE 0 selection */ + ADI_ADRV9025_LANE_1 = 0X02, /*!< LANE 1 selection */ + ADI_ADRV9025_LANE_2 = 0X04, /*!< LANE 2 selection */ + ADI_ADRV9025_LANE_3 = 0X08, /*!< LANE 3 selection */ + ADI_ADRV9025_ALL_LANES = 0x0F +} adi_adrv9025_LaneSel_e; + +/** +* \brief Structure to hold SPO settings +*/ +typedef struct adi_adrv9025_DesEyeSweepResults +{ + uint8_t goodSpoLeft; + uint8_t goodSpoRight; + uint8_t goodSpoTotal; +} adi_adrv9025_DesEyeSweepResults_t; + +typedef struct adi_adrv9025_EyeDiagramResultsQR +{ + uint8_t phase; /* phase point in time that reading occured, this will be between -16 and +16 as Unit Interval for signal on QR mode consists of 32 phases */ + uint8_t b1Threshold; /* Threshold of b1 value in DFE Core, this determines where a detection is approaching a 1 bit value or its inverse value approaching a 0 bit */ + int8_t eyeStepUp; /* position of eye top reading for a particular point in time */ + int8_t eyeStepDown; /* position of eye bottom reading for a particular point in time */ + +} adi_adrv9025_EyeDiagramResultsQR_t; + +typedef struct adi_adrv9025_VerticalISIConfig +{ + uint32_t error_threshold; /* Error Threshold */ + uint8_t start_eyemon_step; /* Eye monitor step interval */ + uint8_t num_flashes; /* Number of flashes to use */ + uint8_t c0_notc1; /* Flag indicating which comparitor to use (c0/c1) */ + uint8_t search_up_down; /* Directional flag either search up or down */ +} adi_adrv9025_VerticalISIConfig_t; + +#ifdef __cplusplus +} + + +#endif + +#endif /* _ADI_ADRV9025_DATA_INTERFACE_TYPES_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_dynamic_slicer.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_dynamic_slicer.h new file mode 100644 index 0000000..641cf74 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_dynamic_slicer.h @@ -0,0 +1,121 @@ +/** +* \file adi_adrv9025_dynamic_slicer.h +* \brief Contains ADRV9025 function prototypes for adi_adrv9025_dynamic_slicer.c +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_DYNAMIC_SLICER_H_ +#define _ADI_ADRV9025_DYNAMIC_SLICER_H_ + +#include "adi_adrv9025_dynamic_slicer_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Configures the dynamic slicer mode of operation for Rx data +* +* The slicer works in conjunction with the gain compensation module. +* The digital gain compensation module compensates for the front end attenuation +* thereby increasing the bit resolution of the Rx data word. The slicer is then +* applied to attenuate the data such that it can fit into the JESD data path resolution. +* +* Dynamic slicer configuration allows the receiver data to be sent on all bits of the 12-bit/16-bit +* JESD data unless there is a gain change. At every gain change, the new slicer configuration is +* transmitted. The dynamic slicer data is 56 bits long transmitted across 28 samples of I and Q JESD data +* which includes 32 bits of user programmable sync header for identification, +* 16 bits consisting of an AGC sync bit and the slicer control word followed by 8 CRC bits. +* The dynamic slicer data transmitted over the JESD I and Q lines are shown below +* +* I Data (consisting of odd bits of the 56 bit dynamic slicer data): +* S31,S29,S27,S25,S23,S21,S19,S17,S15,S13,S11,S9,S7,S5,S3,S1,SYNC,0,0,0,0,0,SL3,SL1,C7,C5,C3,C1 (LSB - Transmitted first) +* +* Q Data (consisting of the even bits of the 56 bit dynamic slicer data): +* S30,S28,S26,S24,S22,S20,S18,S16,S14,S12,S10,S8,S6,S4,S2,S0,0,0,0,0,0,0,SL2,SL0,C6,C4,C2,C0 (LSB - Transmitted first) +* +* Where S31-S0 are the user programmable sync header bits, SYNC - AGC sync bit, SL3-SL0 is the slicer control word +* and C7-C0 is the CRC generated by applying the the CRC generator polynomial x^8 + x^2 + x + 1 on the LSB 16 bits +* of the 56 bit dynamic slicer data which includes {SYNC,0,0,0,0,0,0,0,0,0,0,0,SL3,SL2,SL1,SL0}. +* +* Please note that enabling the dynamic slicer mode of operation enables the gain compensation on the device. +* +* Please note that while embedding 1 dynamic slicer data bit at LSB or MSB-1 posn is allowed for signed magnitude data, +* embedding of 1 dynamic slicer data bit at LSB is the only allowed option for 2s complement data. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param rxDynamicSlicerCfg Array of dynamic slicer configuration structures +* \param arraySize No. of elements in the rxDynamicSlicerCfg array +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxDynamicSlicerConfigSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxDynamicSlicerConfig_t rxDynamicSlicerCfg[], + uint8_t arraySize); + +/** +* \brief Retrieves the dynamic slicer configuration settings from the device +* +* Reads the current status of the dynamic slicer configuration from the device +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param rxChannel Target Rx channel whose dynamic slicer configuration is requested +* \param rxDynamicSlicerCfg Pointer to the dynamic slicer config which will be updated with the +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxDynamicSlicerConfigGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxDynamicSlicerConfig_t* rxDynamicSlicerCfg); + +/** +* \brief Commands the ADRV9025 to resend dynamic slicer data +* +* The 56 bit dynamic slicer data is transmitted via JESD data automatically when the Rx gain changes. +* The user can request the slicer to resend dynamic slicer data on demand through this API. +* +* \pre This function can be called only if the dynamic slicer config is enabled previously via +* adi_adrv9025_RxDynamicSlicerConfigSet() API. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param rxChannelMask A mask consisting of the 'OR'ed Rx channels for which the +* dynamic slicer data is required to be resent +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxDynamicSlicerDataResend(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_dynamic_slicer_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_dynamic_slicer_types.h new file mode 100644 index 0000000..ce0175b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_dynamic_slicer_types.h @@ -0,0 +1,44 @@ +/** +* \file adi_adrv9025_dynamic_slicer_types.h +* \brief Contains ADRV9025 dynamic slicer data types +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_DYNAMIC_SLICER_TYPES_H_ +#define _ADI_ADRV9025_DYNAMIC_SLICER_TYPES_H_ + +#include +#include "adi_adrv9025_types.h" +#include "adi_adrv9025_rx_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Data structure to hold ADRV9025 Rx dynamic slicer configuration. In the dynamic slicer mode +* the slicer control word is embedded in the JESD data only when there is a gain change / slicer control word update. +*/ +typedef struct adi_adrv9025_RxDynamicSlicerConfig +{ + uint32_t rxChannelMask; /*!< Mask consisting of ORed Rx Channels for which the dynamic slicer settings are applied */ + uint8_t dynamicSlicerEnable; /*!< Enables the dynamic slicer mode of operation. Slicer data is embedded in the JESD data whenever there is a gain change */ + uint8_t dynamicSlicerAgcSyncEnable; /*!< This enables a flag in the dynamic slicer data which goes high whenever there is a gain change */ + uint32_t dynamicSlicerSyncHeader; /*!< A 32 bit unique identification pattern preceding the slicer control word embedded in the JESD data */ + adi_adrv9025_RxIntSampleResolution_e intSampleResolution; /*!< Resolution of Rx Data */ + adi_adrv9025_RxSlicerEmbeddedBits_e intEmbeddedBits; /*!< No. of embedded slicer bits in Rx Data. For dynamic slicer operation embedding of 1 bit at LSB / embedding 1 bit at MSB are the only modes allowed */ + adi_adrv9025_IntSlicerStepSizes_e intSlicerStepSize; /*!< Step size to be used by the internal slicer module. Valid step sizes are 1dB, 2dB, 3dB, 4dB, 6dB, 8dB */ +} adi_adrv9025_RxDynamicSlicerConfig_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_DYNAMIC_SLICER_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_error.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_error.h new file mode 100644 index 0000000..19e82f6 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_error.h @@ -0,0 +1,70 @@ +/** +* \file adi_adrv9025_error.h +* \brief ADRV9025 ERROR header file +* +* Extension of adi_common_error +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_ERROR_H_ +#define _ADI_ADRV9025_ERROR_H_ + +#include "adi_common_error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Extending Common Errors for ADRV9025 */ +#define ADI_ADRV9025_ERR_INV_TX_ATTEN_MODE 0x1001 /*!< Invalid Tx attenuation control mode found */ +#define ADI_ADRV9025_ERR_GP_INTERRUPT 0x1002 /*!< GP interrupt error has been detected, more info can be found in adrv9025_GpIntHandler */ +#define ADI_ADRV9025_ERR_SHARED_RESOURCE_RELEASE 0x1003 /*!< Error while releasing shared source */ +#define ADI_ADRV9025_ERR_SHARED_RESOURCE_ACQUIRE 0x1004 /*!< Error while acquiring shared source */ +#define ADI_ADRV9025_ERR_NUMBER_OF_ERRORS 0x1005 /*!< End of Errors for ADRV9025 */ + +/* Extending Common Actions for ADRV9025 + * TODO remove once common actions are associated */ +#define ADI_ADRV9025_ACT_WARN_RERUN_TRCK_CAL (2) /*!< API NG - RESET SPEC TRACK CALS */ +#define ADI_ADRV9025_ACT_WARN_RESET_GPIO (3) /*!< API OK - GPIO Not working */ +#define ADI_ADRV9025_ACT_WARN_BBIC_LOGERROR (5) /*!< API OK - Recommend for BBIC to log and track error frequency */ +#define ADI_ADRV9025_ACT_WARN_CHECK_TX_DATA (6) /*!< API OK - Recommend for BBIC to check Tx data for SRL violations */ +#define ADI_ADRV9025_ACT_ERR_RESET_CPU (-2) /*!< API NG - RESET CPU ONLY */ +#define ADI_ADRV9025_ACT_ERR_RERUN_INIT_CALS (-3) /*!< API NG - RESET INIT CAL SEQ */ +#define ADI_ADRV9025_ACT_ERR_RESET_SPI (-4) /*!< API NG - SPI Not Working */ +#define ADI_ADRV9025_ACT_ERR_RESET_GPIO (-5) /*!< API NG - GPIO Not working */ +#define ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR (-12) /*!< API NG - USER Should log this error and decide recovery action */ +#define ADI_ADRV9025_ACT_ERR_RESET_CACHE (-14) /*!< API NG - SPI CACHE Requires reset */ +#define ADI_ADRV9025_ACT_ERR_FLUSH_CACHE (-15) /*!< API NG - Bitfield CACHE requires flushing */ + +/* Extending common error sources */ +#define ADI_ADRV9025_SRC_AGC 0x1001 /*!< Error detected in adi_adrv9025_agc.c */ +#define ADI_ADRV9025_SRC_CPU 0x1002 /*!< Error detected in adi_adrv9025_cpu.c */ +#define ADI_ADRV9025_SRC_CALS 0x1003 /*!< Error detected in adi_adrv9025_cals.c */ +#define ADI_ADRV9025_SRC_DATAINTERFACE 0x1004 /*!< Error detected in adi_adrv9025_data_interface.c */ +#define ADI_ADRV9025_SRC_DPD 0x1005 /*!< Error detected in adi_adrv9025_dpd.c */ +#define ADI_ADRV9025_SRC_GPIO 0x1006 /*!< Error detected in adi_adrv9025_gpio.c */ +#define ADI_ADRV9025_SRC_HAL 0x1007 /*!< Error detected in adi_adrv9025_hal.c */ +#define ADI_ADRV9025_SRC_PCA 0x1008 /*!< Error detected in adi_adrv9025_pca.c */ +#define ADI_ADRV9025_SRC_PHM 0x1009 /*!< Error detected in adi_adrv9025_phm.c */ +#define ADI_ADRV9025_SRC_RADIOCTRL 0x100a /*!< Error detected in adi_adrv9025_radioctrl.c */ +#define ADI_ADRV9025_SRC_RX 0x100b /*!< Error detected in adi_adrv9025_rx.c */ +#define ADI_ADRV9025_SRC_TX 0x100c /*!< Error detected in adi_adrv9025_tx.c */ +#define ADI_ADRV9025_SRC_UTILITIES 0x100d /*!< Error detected in adi_adrv9025_utilities.c */ + +/* Extending feature errors*/ +#define ADI_ADRV9025_SRC_CPUCMD 0x1102 /*!< Error detected in adi_adrv9025_cpu.c cpu cmd */ +#define ADI_ADRV9025_SRC_CPUFWSTATUS 0x1202 /*!< Error detected in adi_adrv9025_cpu.c cpu start status check */ +#define ADI_ADRV9025_SRC_CPUINITCALS 0x1103 /*!< Error detected in adi_adrv9025_cals.c cpu cmd init cals */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_ERROR_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_gpio.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_gpio.h new file mode 100644 index 0000000..2f68c94 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_gpio.h @@ -0,0 +1,1050 @@ +/** + * \file adi_adrv9025_gpio.h + * \brief ADRV9025 GPIO header file + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_GPIO_H_ +#define _ADI_ADRV9025_GPIO_H_ + +#include "adi_adrv9025_types.h" +#include "adi_adrv9025_gpio_types.h" +#include "adi_common_error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Sets the ADRV9025 low voltage GPIO pin directions + * \brief Not currently implemented + * + * This function will set the GPIO direction given by the passed parameter. + * The direction can be either output or input per pin. The gpioUsedMask + * parameter allows the function to only affect the GPIO pins of interest. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param gpioOutEn (valid range 0 - 0x07FFFF), bit per GPIO pin, the direction is + * + * gpioOutEn[bit] | GPIO direction + * ----------------|------------------- + * 0 | input + * 1 | output + * + * \param gpioUsedMask Mask used to control which Oe bits are set/cleared. If + * mask bit =1, that bit will be modified by gpioOutEn bit + * + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_GpioOeSet(adi_adrv9025_Device_t* device, + uint32_t gpioOutEn, + uint32_t gpioUsedMask); + +/** + * \brief Gets the ADRV9025 low voltage GPIO pin directions + * + * This function will get the GPIO direction currently set in the device. + * The direction can be either output or input per pin. The return gpioOutEn + * function parameter returns a bit per GPIO pin. 1 = output from the ADRV9025 + * Device, 0 = input into the ADRV9025 device. + * + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param gpioOutEn Pointer to a single uint32_t variable that returns the + * output enable reading per GPIO pin + * + * gpioOutEn[bit] | GPIO direction + * ----------------|------------------- + * 0 | input + * 1 | output + * + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_GpioOeGet(adi_adrv9025_Device_t* device, + uint32_t* gpioOutEn); + +/** +* \brief Sets the selected ADRV9025 low voltage GPIO pins I/O direction to Input +* +* This function will set the GPIO direction currently for the requested GPIOs to input. +* The direction can be either output or input per pin. The gpioInputMask +* determines the GPIO pins which can be set to input. +* +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param gpioInputMask ADRV9025 GPIO pins which are required to be set as input +* in the range 0x00000 - 0x7FFFF +* +* GPIO_0 corresponds to LSB of gpioInputMask where as GPIO_18 corresponds +* to MSB of gpioInputMask. For example, to set GPIO_0, GPIO_1, GPIO_17,GPIO_18 +* as inputs the gpioInputMask parameter would be equal to 0x60003. +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_GpioInputDirSet(adi_adrv9025_Device_t* device, + uint32_t gpioInputMask); + +/** +* \brief Sets the selected ADRV9025 low voltage GPIO pins I/O direction to Output +* +* This function will set the GPIO direction currently for the requested GPIOs to output. +* The direction can be either output or input per pin. The gpioOutputMask +* determines the GPIO pins which can be set to output. +* \brief Not currently implemented +* +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param gpioOutputMask ADRV9025 GPIO pins which are required to be set as output +* in the range 0x00000 - 0x7FFFF +* +* GPIO_0 corresponds to LSB of gpioOutputMask where as GPIO_18 corresponds +* to MSB of gpioOutputMask. For example, to set GPIO_0, GPIO_1, GPIO_17,GPIO_18 +* as outputs the gpioInputMask parameter would be equal to 0x60003. +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_GpioOutputDirSet(adi_adrv9025_Device_t* device, + uint32_t gpioOutputMask); + +/** +* \brief Sets the selected ADRV9025 analog GPIO pins I/O direction to Input +* +* This function will set the analog GPIO direction for the requested analog GPIO pins to input. +* The direction can be either output or input per pin. The gpioAnalogInputMask +* determines the GPIO pins which can be set to input. +* +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param gpioAnalogInputMask ADRV9025 analog GPIO pins which are required to be set as input +* in the range 0x00 - 0xFF +* +* GPIO_ANA_0 corresponds to LSB of gpioAnalogInputMask where as GPIO_ANA_7 corresponds +* to MSB of gpioAnalogInputMask. For example, to set GPIO_ANA_0, GPIO_ANA_1, GPIO_ANA_7,GPIO_ANA_6 +* as inputs the gpioAnalogInputMask parameter would be equal to 0xC3. +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_GpioAnalogInputDirSet(adi_adrv9025_Device_t* device, + uint8_t gpioAnalogInputMask); + +/** +* \brief Sets the selected ADRV9025 analog GPIO pins I/O direction to Output +* +* This function will set the analog GPIO direction for the requested analog GPIO pins to output. +* The direction can be either output or input per pin. The gpioAnalogInputMask +* determines the GPIO pins which can be set to input. +* +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param gpioAnalogOutputMask ADRV9025 analog GPIO pins which are required to be set as output +* in the range 0x00 - 0xFF +* +* GPIO_ANA_0 corresponds to LSB of gpioAnalogOutputMask where as GPIO_ANA_7 corresponds +* to MSB of gpioAnalogOutputMask. For example, to set GPIO_ANA_0, GPIO_ANA_1, GPIO_ANA_7,GPIO_ANA_6 +* as outputs the gpioAnalogOutputMask parameter would be equal to 0xC3. +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_GpioAnalogOutputDirSet(adi_adrv9025_Device_t* device, + uint8_t gpioAnalogOutputMask); + +/** + * \brief Sets the ADRV9025 GPIO output source for different GPIO functionality + * + * This function will only affect the GPIO pins that have their OE direction + * set to output. Each four GPIO pins can be assigned a GPIO source. Each + * GPIO nibble (4 pins) must share that same GPIO output source. ENUM + * adi_adrv9025_GpioOutputModes_e can be bitshifted and bitwise OR-ed together to create the + * value for the gpioSrcCtrl function parameter. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param gpioSrcCtrl Nibble based source control, this is a 32 bit value + * containing 5 nibbles that will set the output source + * control for each set of four GPIO pins. + * + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_GpioOutSourceCtrlSet(adi_adrv9025_Device_t* device, + uint32_t gpioSrcCtrl); + +/** + * \brief Reads the ADRV9025 GPIO output source for each set of four low voltage + * GPIO pins. + * + * See ENUM adi_adrv9025_GpioOutputModes_e for possible GPIO output sources. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param gpioSrcCtrl Pointer to a single uint32_t variable where nibble based + * GPIO source is returned. Each nibble of this return value describes + * the GPIO source for the GPIO output pins based on the table below + * gpioSrcCtrl[bits] | Description + * -------------------|--------------------- + * [3:0] | GPIO output source for GPIO[3:0] pins + * [7:4] | GPIO output source for GPIO[7:4] pins + * [11:8] | GPIO output source for GPIO[11:8] pins + * [15:12]| GPIO output source for GPIO[15:12] pins + * [19:16]| GPIO output source for GPIO[18:16] pins + * + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_GpioOutSourceCtrlGet(adi_adrv9025_Device_t* device, + uint32_t* gpioSrcCtrl); + +/** + * \brief Sets the ADRV9025 low voltage GPIO output pins level + * + * This function will only affect the GPIO pins that have their OE direction set to output and + * that have the correct source control for the nibbles in GPIO_BITBANG_MODE + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param gpioOutPinLevel Bit per GPIO pin, level to output for each GPIO pin. 0 = low output, 1 = high output + * + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_GpioOutPinLevelSet(adi_adrv9025_Device_t* device, + uint32_t gpioOutPinLevel); + +/** + * \brief Reads the ADRV9025 low voltage GPIO pin levels and returns their + * contents in a single 32-bit word + * + * The GPIO pins that are set to be inputs in BITBANG mode will read back and + * be returned in the gpioPinLevel parameter. The return value is a bit per + * pin. GPIO 0 returns on bit 0 of the gpioPinLevel parameter. A logic low + * level returns a 0, a logic high level returns a 1. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param gpioInPinLevel Pointer to a single uint32_t variable which returns the + * GPIO pin levels read back on the pins assigned as + * inputs (bit per pin) + * + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_GpioInputPinLevelGet(adi_adrv9025_Device_t* device, + uint32_t* gpioInPinLevel); + +/** + * \brief Reads the ADRV9025 GPIO pin output levels for BITBANG mode + * + * This function allows reading the value that the GPIO output pins are + * set to drive out the pins. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param gpioOutPinLevel Pointer to a single uint32_t variable which returns + * the level set to output of each output GPIO pin + * (bit per pin) + * + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + * + */ +int32_t adi_adrv9025_GpioOutPinLevelGet(adi_adrv9025_Device_t* device, + uint32_t* gpioOutPinLevel); + +/** + * \brief This API function configures the monitor output function for the GPIOs + * + * The monitor outputs allow visibility to some internal ADRV9025 signals. Each + * monitor index outputs a set of eight signals. To output these signals on + * the low voltage GPIO[18:0] pins, first set the desired GPIO[18:0] pin + * direction, then set the GPIO nibble source control to allow the monitor + * signals to route to a set of 4 GPIO pins. If GPIO[18:16] nibble source is + * set to monitor outs, monitor out[6:4] signals are routed to GPIO[18:16]. + * When the nibble source is set to monitor out for GPIO[15:0], monitorOut[7:0] + * is routed to GPIO[7:0] and monitorOut[7:0] is also routed to GPIO[15:8]. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param monitorIndex The index that outputs a set of 8 monitor outputs. See + * table in documentation for which signals output on each GPIO pins + * + * \param monitorMask which GPIO monitor outputs are going to active, bit 0 + * will represent monitor out 0 and bit 7 will represent monitor out 7. + * + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + * + */ +int32_t adi_adrv9025_GpioMonitorOutSrcSet(adi_adrv9025_Device_t* device, + uint8_t monitorIndex, + uint8_t monitorMask); + +/** + * \brief This API function reads the GPIO monitor index and mask from ADRV9025 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param monitorIndex Pointer to single uint8_t variable which returns the + * current monitor signal selection index + * + * \param monitorMask Pointer to single uint8_t variable which returns the + * monitor out signal masking. Bit per monitor out [7:0] + * signal. + * + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_GpioMonitorOutSrcGet(adi_adrv9025_Device_t* device, + uint8_t* monitorIndex, + uint8_t* monitorMask); + +/** + * \brief Sets the General Purpose (GP) interrupt register bit mask for either GP_INT0 ro GP_INT1 or both. + * + * \pre This function can be called any time after device initialization + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param maskSelect Enum indicating the which gp interrupt mask to write + * \param maskArray Data structure holding the gp interrupt masks to write + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_GpIntMaskSet(adi_adrv9025_Device_t* device, + adi_adrv9025_gpMaskSelect_e maskSelect, + adi_adrv9025_gp_MaskArray_t* maskArray); + +/** +* \brief Gets the General Purpose (GP) interrupt register bit mask for either GP_INT0 ro GP_INT1 or both. +* +* \pre This function can be called any time after device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param maskSelect Enum indicating the which gp interrupt mask to write +* \param maskArray Pointer to data structure holding the gp interrupt masks retrieved +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_GpIntMaskGet(adi_adrv9025_Device_t* device, + adi_adrv9025_gpMaskSelect_e maskSelect, + adi_adrv9025_gp_MaskArray_t* maskArray); + +/** + * \brief Reads the General Purpose (GP) interrupt status to determine what caused the GP Interrupt pin to assert. + * WARNING: Reading the GP Status will clear the status bits. DO NOT call this API before calling the API's adi_adrv9025_GpInt0Handler + of adi_adrv9025_GpInt1Handler. + * + * When the BBIC detects a rising edge on either General Purpose Interrupt pins GP_INT0 or GP_INT1, this function + * allows the BBIC to determine the source of the interrupt. The value returned in the status parameter + * will show one or more sources for the interrupt based on the following table. + * + * The status word read-back will show the current value for all interrupt sources, even if they are disabled by the masked. However, + * the GP Interrupt pin will only assert for the enabled sources. + * + * \pre This function can be called any time after device initialization and after the interrupt mask bits have been set + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param gpIntStatus Pointer to status read-back word + * + * bit[n] | GP Interrupt Mask Bit + * -------|----------------------- + * bit47 | RF1PLL_UNLOCK + * bit46 | RF2PLL_UNLOCK + * bit45 | AUXPLL_UNLOCK + * bit44 | CLKPLL_UNLOCK + * bit43 | RF1PLL_CP_OVR_RANGE + * bit42 | RF2PLL_CP_OVR_RANGE + * bit41 | AUXPLL_OVR_RANGE + * bit40 | CLKPLL_OVR_RANGE + * bit39 | SERDES_PLL_UNLOCK + * bit38 | DEFRAMER9_IRQ + * bit37 | DEFRAMER8_IRQ + * bit36 | DEFRAMER7_IRQ + * bit35 | DEFRAMER6_IRQ + * bit34 | DEFRAMER5_IRQ + * bit33 | DEFRAMER4_IRQ + * bit32 | DEFRAMER3_IRQ + * bit31 | DEFRAMER2_IRQ + * bit30 | DEFRAMER1_IRQ + * bit29 | DEFRAMER0_IRQ + * bit28 | FRAMER8_IRQ + * bit27 | FRAMER7_IRQ + * bit26 | FRAMER6_IRQ + * bit25 | FRAMER5_IRQ + * bit24 | FRAMER4_IRQ + * bit23 | FRAMER3_IRQ + * bit22 | FRAMER2_IRQ + * bit21 | FRAMER1_IRQ + * bit20 | FRAMER0_IRQ + * bit19 | PA_PROTECTION_TX4_ERROR + * bit18 | PA_PROTECTION_TX3_ERROR + * bit17 | PA_PROTECTION_TX2_ERROR + * bit16 | PA_PROTECTION_TX1_ERROR + * bit15 | ARM_FORCE_INTERRUPT + * bit14 | WATCHDOG_TIMEOUT + * bit13 | ARM_CALIBRATION_ERROR + * bit12 | ARM_SYSTEM_ERROR + * bit11 | ORX2_STREAM_ERROR + * bit10 | ORX1_STREAM_ERROR + * bit9 | TX4_STREAM_ERROR + * bit8 | TX3_STREAM_ERROR + * bit7 | TX2_STREAM_ERROR + * bit6 | TX1_STREAM_ERROR + * bit5 | RX4_STREAM_ERROR + * bit4 | RX3_STREAM_ERROR + * bit3 | RX2_STREAM_ERROR + * bit2 | RX1_STREAM_ERROR + * bit1 | CORE_STREAM_ERROR + * bit0 | Reserved + * + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_GpIntStatusGet(adi_adrv9025_Device_t* device, + uint64_t* gpIntStatus); + +/** + * \brief Sets the GPInt status register sticky bit mask. This mask is a B0 only feature and masks which events + * show up in the status register. This bit mapping is exactly the same as the status register. + * + * \pre This function can be called any time after device initialization + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param eventMask 64-bit unsigned integer mask representing which events to mask from the status register (1 = masked, 0 = active). + * + * \retval ADI_COMMON_ACT_ERR_RESET_FULL Recovery action when API has critical failure. + * \retval ADI_COMMON_ACT_WARN_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + */ +int32_t adi_adrv9025_GpIntStickyBitMaskSet(adi_adrv9025_Device_t* device, + uint64_t eventMask); + +/** + * \brief Gets the GPInt status register sticky bit mask. This mask is a B0 only feature and masks which events + * show up in the status register. This bit mapping is exactly the same as the status register. + * + * \pre This function can be called any time after device initialization + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param eventMask Pointer 64-bit unsigned integer mask representing which events are masked from the status register (1 = masked, 0 = active). + * + * \retval ADI_COMMON_ACT_ERR_RESET_FULL Recovery action when API has critical failure. + * \retval ADI_COMMON_ACT_WARN_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + */ +int32_t adi_adrv9025_GpIntStickyBitMaskGet(adi_adrv9025_Device_t* device, + uint64_t* eventMask); + +/** + * \brief Reads back the device temperature sensor + * + * This function reads the device's temperature sensor by requesting the latest + * temperature sensor value from the ARM processor. The temperature sensor + * value read back is scaled to return the temperature as degrees C. + * + * \pre This function may be called after the device has been fully initialized + * any time during run-time operation, but only after the ARM has been + * configured + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param temperatureDegC A pointer to a single uint16_t element that returns the + * current 12bit temperature sensor value in degrees C. + * + * \retval ADI_ADRV9025_WARN_RESET_LOG recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_RESET_SPI recovery action for SPI reset required + * \retval ADI_ADRV9025_NO_ACTION function completed successfully, no action required + */ +int32_t adi_adrv9025_TemperatureGet(adi_adrv9025_Device_t* device, + int16_t* temperatureDegC); + +/** + * \brief Configures the selected auxiliary ADC with the supplied configuration. + * + * Multiple ADCs can be configured in a single invocation + * of this function by supplying an array of adi_adrv9025_AuxAdcCfg_t structures. + * Note that each of the supplied structures must target a unique ADC. The user may + * not configure multiple ADCs using a single configuration structure because the + * ADC to target is specified as a field within the structure. The function will + * flag an error if this occurs. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param auxAdcConfig A pointer to the supplied ADC configuration structure(s) + * \param arraySize The number of supplied configuration structures + * +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for ARM/WATCHDOG errors +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_AuxAdcCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcCfg_t* auxAdcConfig, + uint8_t arraySize); + +/** + * \brief Reads back the configuration from the selected auxiliary ADC + * + * Only a single ADC configuration can be read with a single invocation of this function. + * The supplied auxAdcConfig structure is populated with the configuration which + * is based on the ADC's configuration registers. Note that supplied auxAdcConfig + * structure does not need to be initialized in any way. For example, the supplied + * auxAdcSelect argument is copied into auxAdcConfig by this function because + * it is a member of adi_adrv9025_AuxAdcCfg_t. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param auxAdcSelect Select which auxiliary ADC to read the configuration from + * \param auxAdcConfig A pointer to the supplied auxiliary ADC configuration + * structure to populate + * +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for ARM/WATCHDOG errors +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_AuxAdcCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcSelect_e auxAdcSelect, + adi_adrv9025_AuxAdcCfg_t* auxAdcConfig); + +/** + * \brief Reads the selected ADC's sample value. + * + * This function obtains the selected ADC's sample value and populates the + * supplied auxAdcValue structure with it. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \pre Before using this function to read back the sensor value: + * adi_Adrv9025_AuxAdcCfgSet() function is needed in order to set up the selected + * auxiliary ADC channel. The selected ADC will be started if a suitable configuration + * is written using the adi_Adrv9025_AuxAdcCfgSet() function and that the associated + * auxAdcConfig structure has its auxAdcEnable field set to ADI_ADRV9025_AUXADC_ENABLE. + * All ADC sample values need to be obtained using this function. + * + * \post The auxAdcvalue structure will be populated with the ADC sample data as well + * as an indication of the sample's validity and finally the ADC that the sample is from. + * The ADC's output is dependent on the device's power supplies. + * See the definition of the adi_adrv9025_AuxAdcCfg_t struct for the formula. + * The ADC's output is linear only to 10 bits and as such, the user should either + * round or truncate the output. + * + * \param device Pointer to the ADRV9025 data structure + * \param auxAdcSelect Select which auxiliary ADC to read a sample from + * \param auxAdcValue A pointer to the supplied auxiliary ADC value structure to + * populate + * +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for ARM/WATCHDOG errors +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_AuxAdcValueGet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcSelect_e auxAdcSelect, + adi_adrv9025_AuxAdcValue_t* auxAdcValue); + +/** +* \brief Starts AuxADC measurement. +* +* This function will start AuxADC measurement by toggling reset bit for selected AuxADC. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param auxAdcSelect Select which auxiliary ADC to start measurement +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for ARM/WATCHDOG errors +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AuxAdcMeasurementStart(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcSelect_e auxAdcSelect); + +/** + * \brief Enables/Disables SPI2 on ADRV9025 + * \brief Not currently implemented + * + * The ADRV9025 device can enable a second SPI port on the low voltage GPIO[3:0] + * pins. This SPI port allows read/write access to a limited set of + * TxAttenuation and Rx gain index registers. + * + * The SPI2 uses the same configuration that is programmed for SPI. This + * includes LSB/MSB first, 4 wire mode, streaming, and address increment. + * + * One unique feature about the TxAtten control is that the SPI register value + * can be set and does not update to the transmitter until a GPIO pin is + * toggled (See spi2TxAttenGpioSel function parameter). The GPIO pin is level + * sensitive, selecting the TxAtten programmed in either the + * tx(1/2)_attenuation_s1 or tx(1/2)_attenuation_s2 bitfields of the second SPI + * registers. The GPIO pin used to switch between the two TxAtten settings is + * user selectable using the ENUM in the function parameter. + * + * For readback of TxAttenuation SPI registers, first write the desired register + * to force the value to be updated, before reading it back across SPI. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param spi2Enable Enable(=1)/Disable(=0) SPI2 protocol on ADRV9025 + * + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_Spi2CfgSet(adi_adrv9025_Device_t* device, + uint8_t spi2Enable); + +/** + * \brief Get current status of SPI2 configuration on ADRV9025 + * \brief Not currently implemented *\ + * + * This function reads back whether the second SPI port on the low voltage + * GPIO[3:0] is enabled. It also reads back the GPIO pin selected for the + * TxAttenuation switch used when SPI2 is enabled. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param spi2Enable Indicates whether SPI2 protocol is Enabled(=1)/Disabled(=0) on ADRV9025 + * + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_Spi2CfgGet(adi_adrv9025_Device_t* device, + uint8_t* spi2Enable); + +/** + * \brief Clears GP Int status register + * + * \pre This function can be called any time after device initialization + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * + * \retval ADI_COMMON_ACT_ERR_RESET_FULL Recovery action when API has critical failure. + * \retval ADI_COMMON_ACT_WARN_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + */ +int32_t adi_adrv9025_GPIntClearStatusRegister(adi_adrv9025_Device_t* device); + +/** +* \brief Called whenever the BBIC detects a GP_INT1 assertion to find the source and clear it if possible. GP_INT1 is +* considered to be the HIGH priority interrupt service while GP_INT0 is considered the LOWER priority interrupt service. +* A mutex around the GP_INT1 service routine insures that a GP_INT0 service request will be ignored while a GP_INT1 service +* request is in process. This is accomplished by disabling all GP_INT0 interrupts during the GP_INT1 service request. +* +* When the BBIC detects a rising edge on the General Purpose Interrupt pin1, this function +* allows the BBIC an easy way to determine the GP_INT1 source, clear it if possible, and receive a recovery action. +* +* The GP Interrupt pin1 is the logical OR of all the sources and the gp_interrupts_mask_pin1. The gp_interrupts_mask_pin1 +* bit-field is used to control which of the 48 available interrupt sources can assert the GP_INT1 pin. To enable an +* available interrupt source for GP_INT1, write the corresponding bit in the gp_interrupts_mask0 bit-field to low. +* Writing an interrupt source bit in the gp_interrupts_mask0 bit-field to high will disable that interrupt source from +* asserting the GP_INT1 pin. The gp_interrupts_status_word read-back will show the current value for all interrupt sources, +* even if they are disabled by the masked. However, the GP Interrupt pin will only assert for the enabled sources. +* +* \pre This function can be called any time after device initialization and after the interrupt mask bits have been set +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param gpInt1Status Pointer to status read-back word containing the GP_INT1 source registers. Bit mapping is: +* +* bit[n] | GP Interrupt Mask +* -------|----------------------- +* bit47 | ADI_ADRV9025_GP_MASK_RF1PLL_UNLOCK +* bit46 | ADI_ADRV9025_GP_MASK_RF2PLL_UNLOCK +* bit45 | ADI_ADRV9025_GP_MASK_AUXPLL_UNLOCK +* bit44 | ADI_ADRV9025_GP_MASK_CLKPLL_UNLOCK +* bit43 | ADI_ADRV9025_GP_MASK_RF1PLL_CP_OVR_RANGE +* bit42 | ADI_ADRV9025_GP_MASK_RF2PLL_CP_OVR_RANGE +* bit41 | ADI_ADRV9025_GP_MASK_AUXPLL_OVR_RANGE +* bit40 | ADI_ADRV9025_GP_MASK_CLKPLL_OVR_RANGE +* bit39 | ADI_ADRV9025_GP_MASK_SERDES_PLL_UNLOCK +* bit38 | ADI_ADRV9025_GP_MASK_DEFRAMER9_IRQ 204C Link1 Loss of Sync +* bit37 | ADI_ADRV9025_GP_MASK_DEFRAMER8_IRQ 204B Link1 QBD IRQ +* bit36 | ADI_ADRV9025_GP_MASK_DEFRAMER7_IRQ Link1 Sysref Out of Phase +* bit35 | ADI_ADRV9025_GP_MASK_DEFRAMER6_IRQ Link1 Elastic Buffer Error +* bit34 | ADI_ADRV9025_GP_MASK_DEFRAMER5_IRQ Link1 Lane FIFO pointer error +* bit33 | ADI_ADRV9025_GP_MASK_DEFRAMER4_IRQ 204C Link0 Loss of Sync +* bit32 | ADI_ADRV9025_GP_MASK_DEFRAMER3_IRQ 204B Link0 QBD IRQ +* bit31 | ADI_ADRV9025_GP_MASK_DEFRAMER2_IRQ Link0 Sysref Out of Phase +* bit30 | ADI_ADRV9025_GP_MASK_DEFRAMER1_IRQ Link0 Elastic Buffer Error +* bit29 | ADI_ADRV9025_GP_MASK_DEFRAMER0_IRQ Link0 Lane FIFO pointer error +* bit28 | ADI_ADRV9025_GP_MASK_FRAMER8_IRQ Link2 Transport Not sending data +* bit27 | ADI_ADRV9025_GP_MASK_FRAMER7_IRQ Link2 Sysref out of Phase +* bit26 | ADI_ADRV9025_GP_MASK_FRAMER6_IRQ Link2 Lane FIFO pointer error +* bit25 | ADI_ADRV9025_GP_MASK_FRAMER5_IRQ Link1 Transport Not sending data +* bit24 | ADI_ADRV9025_GP_MASK_FRAMER4_IRQ Link1 Sysref out of Phase +* bit23 | ADI_ADRV9025_GP_MASK_FRAMER3_IRQ Link1 Lane FIFO pointer error +* bit22 | ADI_ADRV9025_GP_MASK_FRAMER2_IRQ Link0 Transport Not sending data +* bit21 | ADI_ADRV9025_GP_MASK_FRAMER1_IRQ Link0 Sysref out of Phase +* bit20 | ADI_ADRV9025_GP_MASK_FRAMER0_IRQ Link0 Lane FIFO pointer error +* bit19 | ADI_ADRV9025_GP_MASK_PA_PROTECTION_TX4_ERROR +* bit18 | ADI_ADRV9025_GP_MASK_PA_PROTECTION_TX3_ERROR +* bit17 | ADI_ADRV9025_GP_MASK_PA_PROTECTION_TX2_ERROR +* bit16 | ADI_ADRV9025_GP_MASK_PA_PROTECTION_TX1_ERROR +* bit15 | ADI_ADRV9025_GP_MASK_ARM_FORCE_INTERRUPT +* bit14 | ADI_ADRV9025_GP_MASK_WATCHDOG_TIMEOUT +* bit13 | ADI_ADRV9025_GP_MASK_ARM_CALIBRATION_ERROR +* bit12 | ADI_ADRV9025_GP_MASK_ARM_SYSTEM_ERROR +* bit11 | ADI_ADRV9025_GP_MASK_ORX2_STREAM_ERROR +* bit10 | ADI_ADRV9025_GP_MASK_ORX1_STREAM_ERROR +* bit9 | ADI_ADRV9025_GP_MASK_TX4_STREAM_ERROR +* bit8 | ADI_ADRV9025_GP_MASK_TX3_STREAM_ERROR +* bit7 | ADI_ADRV9025_GP_MASK_TX2_STREAM_ERROR +* bit6 | ADI_ADRV9025_GP_MASK_TX1_STREAM_ERROR +* bit5 | ADI_ADRV9025_GP_MASK_RX4_STREAM_ERROR +* bit4 | ADI_ADRV9025_GP_MASK_RX3_STREAM_ERROR +* bit3 | ADI_ADRV9025_GP_MASK_RX2_STREAM_ERROR +* bit2 | ADI_ADRV9025_GP_MASK_RX1_STREAM_ERROR +* bit1 | ADI_ADRV9025_GP_MASK_CORE_STREAM_ERROR +* bit0 | Reserved +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action for ARM/WATCHDOG errors +* \retval ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR Recovery action for errors the BBIC must track and decide +* if the interrupt is an error or not. +* \retval ADI_ADRV9025_ACT_WARN_RERUN_TRCK_CAL ARM signals tracking cals need to be restarted +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_GpInt1Handler(adi_adrv9025_Device_t* device, + adi_adrv9025_gpIntStatus_t* gpInt1Status); + +/** +* \brief Called whenever the BBIC detects a GP_INT0 assertion to find the source and clear it if possible. GP_INT1 is +* considered to be the HIGH priority interrupt service while GP_INT0 is considered the LOWER priority interrupt service. +* GP_INT1 are not disabled during a GP_INT0 interrupt service request. Thus, a GP_INT0 service request can be interrupted +* by a GP_INT1 interrupt service request. When the BBIC detects a rising edge on the General Purpose Interrupt pin0, this function +* allows the BBIC an easy way to determine the GP_INT0 source, clear it if possible, and receive a recovery action. +* +* The GP Interrupt pin0 is the logical OR of all the sources and the gp_interrupts_mask_pin0. The gp_interrupts_mask_pin0 +* bit-field is used to control which of the 48 available interrupt sources can assert the GP_INT0 pin. To enable an +* available interrupt source for GP_INT0, write the corresponding bit in the gp_interrupts_mask0 bit-field to low. +* Writing an interrupt source bit in the gp_interrupts_mask0 bit-field to high will disable that interrupt source from +* asserting the GP_INT0 pin. The gp_interrupts_status_word read-back will show the current value for all interrupt sources, +* even if they are disabled by the masked. However, the GP Interrupt pin will only assert for the enabled sources. +* +* \pre This function can be called any time after device initialization and after the interrupt mask bits have been set +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param gpInt0Status Pointer to status read-back word containing the GP_INT0 source registers. Bit mapping is: +* +* bit[n] | GP Interrupt Mask +* -------|----------------------- +* bit47 | GP_MASK_RF1PLL_UNLOCK +* bit46 | GP_MASK_RF2PLL_UNLOCK +* bit45 | GP_MASK_AUXPLL_UNLOCK +* bit44 | GP_MASK_CLKPLL_UNLOCK +* bit43 | GP_MASK_RF1PLL_CP_OVR_RANGE +* bit42 | GP_MASK_RF2PLL_CP_OVR_RANGE +* bit41 | GP_MASK_AUXPLL_OVR_RANGE +* bit40 | GP_MASK_CLKPLL_OVR_RANGE +* bit39 | GP_MASK_SERDES_PLL_UNLOCK +* bit38 | GP_MASK_DEFRAMER9_IRQ 204C Link1 Loss of Sync +* bit37 | GP_MASK_DEFRAMER8_IRQ 204B Link1 QBD IRQ +* bit36 | GP_MASK_DEFRAMER7_IRQ Link1 Sysref Out of Phase +* bit35 | GP_MASK_DEFRAMER6_IRQ Link1 Elastic Buffer Error +* bit34 | GP_MASK_DEFRAMER5_IRQ Link1 Lane FIFO pointer error +* bit33 | GP_MASK_DEFRAMER4_IRQ 204C Link0 Loss of Sync +* bit32 | GP_MASK_DEFRAMER3_IRQ 204B Link0 QBD IRQ +* bit31 | GP_MASK_DEFRAMER2_IRQ Link0 Sysref Out of Phase +* bit30 | GP_MASK_DEFRAMER1_IRQ Link0 Elastic Buffer Error +* bit29 | GP_MASK_DEFRAMER0_IRQ Link0 Lane FIFO pointer error +* bit28 | GP_MASK_FRAMER8_IRQ Link2 Transport Not sending data +* bit27 | GP_MASK_FRAMER7_IRQ Link2 Sysref out of Phase +* bit26 | GP_MASK_FRAMER6_IRQ Link2 Lane FIFO pointer error +* bit25 | GP_MASK_FRAMER5_IRQ Link1 Transport Not sending data +* bit24 | GP_MASK_FRAMER4_IRQ Link1 Sysref out of Phase +* bit23 | GP_MASK_FRAMER3_IRQ Link1 Lane FIFO pointer error +* bit22 | GP_MASK_FRAMER2_IRQ Link0 Transport Not sending data +* bit21 | GP_MASK_FRAMER1_IRQ Link0 Sysref out of Phase +* bit20 | GP_MASK_FRAMER0_IRQ Link0 Lane FIFO pointer error +* bit19 | GP_MASK_PA_PROTECTION_TX4_ERROR +* bit18 | GP_MASK_PA_PROTECTION_TX3_ERROR +* bit17 | GP_MASK_PA_PROTECTION_TX2_ERROR +* bit16 | GP_MASK_PA_PROTECTION_TX1_ERROR +* bit15 | GP_MASK_ARM_FORCE_INTERRUPT +* bit14 | GP_MASK_WATCHDOG_TIMEOUT +* bit13 | GP_MASK_ARM_CALIBRATION_ERROR +* bit12 | GP_MASK_ARM_SYSTEM_ERROR +* bit11 | GP_MASK_ORX2_STREAM_ERROR +* bit10 | GP_MASK_ORX1_STREAM_ERROR +* bit9 | GP_MASK_TX4_STREAM_ERROR +* bit8 | GP_MASK_TX3_STREAM_ERROR +* bit7 | GP_MASK_TX2_STREAM_ERROR +* bit6 | GP_MASK_TX1_STREAM_ERROR +* bit5 | GP_MASK_RX4_STREAM_ERROR +* bit4 | GP_MASK_RX3_STREAM_ERROR +* bit3 | GP_MASK_RX2_STREAM_ERROR +* bit2 | GP_MASK_RX1_STREAM_ERROR +* bit1 | GP_MASK_CORE_STREAM_ERROR +* bit0 | Reserved +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action for ARM/WATCHDOG errors +* \retval ADI_ADRV9025_ACT_ERR_BBIC_LOG_ERROR Recovery action for errors the BBIC must track and decide +* if the interrupt is an error or not. +* \retval ADI_ADRV9025_ACT_WARN_RERUN_TRCK_CAL ARM signals tracking cals need to be restarted +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_GpInt0Handler(adi_adrv9025_Device_t* device, + adi_adrv9025_gpIntStatus_t* gpInt0Status); + +/** +* \brief This function sets the configuration for AuxDACs. +* +* There are 8 AuxDACs at Adrv9025. AuxDAC0-7 outputs to GPIO Analog pin0-7 respectively. +* This function supports setting multiple configurations at the same call. +* +* AuxDAC[n] | GPIO_ANA_n +* ------- |----------------------- +* AuxDAC0 | GPIO_ANA_0 +* AuxDAC1 | GPIO_ANA_1 +* AuxDAC2 | GPIO_ANA_2 +* AuxDAC3 | GPIO_ANA_3 +* AuxDAC4 | GPIO_ANA_4 +* AuxDAC5 | GPIO_ANA_5 +* AuxDAC6 | GPIO_ANA_6 +* AuxDAC7 | GPIO_ANA_7 +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param auxDacConfig Array of AuxDAC configuration structures to be set. +* \param numberOfCfg Number of configurations at auxDacConfig array +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AuxDacCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxDacCfg_t auxDacConfig[], + uint8_t numberOfCfg); + +/** +* \brief This function gets the configuration of selected AuxDAC +* +* There are 8 AuxDACs at Adrv9025. AuxDAC0-7 outputs to GPIO Analog pin0-7 respectively. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param auxDacMask Enum to select AuxDAC +* \param auxDacConfig Pointer to AuxDAC configuration struct of selected AuxDAC +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AuxDacCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxDacs_e auxDacMask, + adi_adrv9025_AuxDacCfg_t* auxDacConfig); + +/** +* \brief This function sets 12 bit DAC word of selected AuxDAC. +* +* There are 8 AuxDACs at Adrv9025. AuxDAC0-7 outputs to GPIO Analog pin0-7 respectively. +* This function supports setting multiple AuxDAC values at the same call +* +* AuxDAC[n] | GPIO_ANA_n +* ------- |----------------------- +* AuxDAC0 | GPIO_ANA_0 +* AuxDAC1 | GPIO_ANA_1 +* AuxDAC2 | GPIO_ANA_2 +* AuxDAC3 | GPIO_ANA_3 +* AuxDAC4 | GPIO_ANA_4 +* AuxDAC5 | GPIO_ANA_5 +* AuxDAC6 | GPIO_ANA_6 +* AuxDAC7 | GPIO_ANA_7 +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param auxDacValues Array of DAC value structs to be set +* \param numberOfCfg Number of DAC words at auxDacValues array +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AuxDacValueSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxDacValue_t auxDacValues[], + uint8_t numberOfCfg); + +/** +* \brief This function reads the DAC word of selected AuxDAC. +* +* There are 8 AuxDACs at Adrv9025. AuxDAC0-7 uses a GPIO Analog pin0-7 respectively. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param auxDacMask AuxDAC selection to read DAC word +* \param auxDacValue Pointer to DAC value struct read from selected AuxDAC +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AuxDacValueGet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxDacs_e auxDacMask, + adi_adrv9025_AuxDacValue_t* auxDacValue); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_GPIO_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_gpio_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_gpio_types.h new file mode 100644 index 0000000..927a44a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_gpio_types.h @@ -0,0 +1,338 @@ +/** + * \file adi_adrv9025_gpio_types.h + * \brief Contains functions to allow control of the General Purpose IO functions on the ADRV9025 device + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_GPIO_TYPES_H_ +#define _ADI_ADRV9025_GPIO_TYPES_H_ + +#include "adi_adrv9025_data_interface_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * \brief Enum to select desired GPIO pin used by the API + */ +typedef enum adi_adrv9025_GpioPinSel +{ + ADI_ADRV9025_GPIO_00 = 0, /*!< Select GPIO_00*/ + ADI_ADRV9025_GPIO_01, /*!< Select GPIO_01*/ + ADI_ADRV9025_GPIO_02, /*!< Select GPIO_02*/ + ADI_ADRV9025_GPIO_03, /*!< Select GPIO_03*/ + ADI_ADRV9025_GPIO_04, /*!< Select GPIO_04*/ + ADI_ADRV9025_GPIO_05, /*!< Select GPIO_05*/ + ADI_ADRV9025_GPIO_06, /*!< Select GPIO_06*/ + ADI_ADRV9025_GPIO_07, /*!< Select GPIO_07*/ + ADI_ADRV9025_GPIO_08, /*!< Select GPIO_08*/ + ADI_ADRV9025_GPIO_09, /*!< Select GPIO_09*/ + ADI_ADRV9025_GPIO_10, /*!< Select GPIO_11*/ + ADI_ADRV9025_GPIO_11, /*!< Select GPIO_12*/ + ADI_ADRV9025_GPIO_12, /*!< Select GPIO_13*/ + ADI_ADRV9025_GPIO_13, /*!< Select GPIO_14*/ + ADI_ADRV9025_GPIO_14, /*!< Select GPIO_15*/ + ADI_ADRV9025_GPIO_15, /*!< Select GPIO_16*/ + ADI_ADRV9025_GPIO_16, /*!< Select GPIO_17*/ + ADI_ADRV9025_GPIO_17, /*!< Select GPIO_18*/ + ADI_ADRV9025_GPIO_18, /*!< Select GPIO_19*/ + ADI_ADRV9025_GPIO_INVALID /*!< Invalid GPIO*/ +} adi_adrv9025_GpioPinSel_e; + +/** +* \brief Enum to select desired Analog GPIO pins used by the API +*/ +typedef enum adi_adrv9025_Gpio3v3PinSel +{ + ADI_ADRV9025_GPIO_ANA_00 = 0, /*!< Select GPIO_ANA_00*/ + ADI_ADRV9025_GPIO_ANA_01, /*!< Select GPIO_ANA_01*/ + ADI_ADRV9025_GPIO_ANA_02, /*!< Select GPIO_ANA_02*/ + ADI_ADRV9025_GPIO_ANA_03, /*!< Select GPIO_ANA_03*/ + ADI_ADRV9025_GPIO_ANA_04, /*!< Select GPIO_ANA_04*/ + ADI_ADRV9025_GPIO_ANA_05, /*!< Select GPIO_ANA_05*/ + ADI_ADRV9025_GPIO_ANA_06, /*!< Select GPIO_ANA_06*/ + ADI_ADRV9025_GPIO_ANA_07, /*!< Select GPIO_ANA_07*/ + ADI_ADRV9025_GPIO_ANA_INVALID /*!< Invalid Analog Gpio*/ +} adi_adrv9025_Gpio3v3PinSel_e; + +/** + * \brief Enum to set the low voltage GPIO mode + */ +typedef enum adi_adrv9025_GpioOutputModes +{ + ADI_ADRV9025_GPIO_MONITOR_MODE = 0, /*!< Allows a choice of debug signals to output from ADRV9025 to monitor the state of the device */ + ADI_ADRV9025_GPIO_BITBANG_MODE = 3, /*!< Manual mode, API function sets output pin levels and reads input pin levels */ + ADI_ADRV9025_GPIO_ARM_OUT_MODE = 9, /*!< Allows internal ARM processor to output on GPIO pins */ + ADI_ADRV9025_GPIO_SLICER_OUT_MODE = 10 /*!< Allows Slicer active configuration to the GPIO output pins */ +} adi_adrv9025_GpioOutputModes_e; + +/** + * \brief Enum of unique error codes for the ADRV9025 GPIO API functions. + * Each error condition in the library should get its own enum value to allow + * easy debug of errors. + */ +typedef enum adi_adrv9025_GpioErrCodes +{ + ADI_ADRV9025_ERR_GPIO_OK = 0, + ADI_ADRV9025_ERR_MONITOR_OUT_INDEX_RANGE, + ADI_ADRV9025_ERR_GETGPIOMON_INDEX_NULL_PARM, + ADI_ADRV9025_ERR_GETGPIOMON_MONITORMASK_NULL_PARM, + ADI_ADRV9025_ERR_GETGPIO_OE_NULL_PARM, + ADI_ADRV9025_ERR_GPIO_OE_INV_PARM, + ADI_ADRV9025_ERR_GPIO_SRC_INV_PARM, + ADI_ADRV9025_ERR_GETGPIO_SRC_NULL_PARM, + ADI_ADRV9025_ERR_GPIO_LEVEL_INV_PARM, + ADI_ADRV9025_ERR_GETGPIO_LEVEL_NULL_PARM, + ADI_ADRV9025_ERR_GETGPIO_SETLEVEL_NULL_PARM, + ADI_ADRV9025_ERR_SETUPAUXDAC_NULL_PARM, + ADI_ADRV9025_ERR_SETUPAUXDAC_INV_10BIT_AUXDACCODE, + ADI_ADRV9025_ERR_SETUPAUXDAC_INV_12BIT_AUXDACCODE, + ADI_ADRV9025_ERR_WRITEAUXDAC_INV_10BIT_AUXDACCODE, + ADI_ADRV9025_ERR_WRITEAUXDAC_INV_12BIT_AUXDACCODE, + ADI_ADRV9025_ERR_WRITEAUXDAC_INV_AUXDACINDEX, + ADI_ADRV9025_ERR_SETUPAUXDAC_INV_RESOLUTION, + ADI_ADRV9025_ERR_GPIO3V3_OE_INV_PARM, + ADI_ADRV9025_ERR_GETGPIO3V3_OE_NULL_PARM, + ADI_ADRV9025_ERR_GPINT_OK, + ADI_ADRV9025_ERR_GPINT_STATUS_NULL_PARM, + ADI_ADRV9025_ERR_GPINT_GPINTDIAG_NULL_PARM, + ADI_ADRV9025_ERR_GPINT_NO_SOURCE_FOUND, + ADI_ADRV9025_ERR_GPINT_SOURCE_NOT_IMPLEMENTED, + ADI_ADRV9025_ERR_GPINT_CLKPLL_UNLOCKED, + ADI_ADRV9025_ERR_GPINT_RFPLL_UNLOCKED, + ADI_ADRV9025_ERR_GPINT_AUXPLL_UNLOCKED, + ADI_ADRV9025_ERR_GPINT_ARM_WATCHDOG_TIMEOUT, + ADI_ADRV9025_ERR_GPINT_ARM_FORCE_GPINT, + ADI_ADRV9025_ERR_GPINT_ARM_SYSTEM_ERROR, + ADI_ADRV9025_ERR_GPINT_ARM_DATA_PARITY_ERROR, + ADI_ADRV9025_ERR_GPINT_ARM_PROG_PARITY_ERROR, + ADI_ADRV9025_ERR_GPINT_ARM_CALIBRATION_ERROR, + ADI_ADRV9025_ERR_GPINT_FRAMERA, + ADI_ADRV9025_ERR_GPINT_DEFRAMERA, + ADI_ADRV9025_ERR_GPINT_FRAMERB, + ADI_ADRV9025_ERR_GPINT_DEFRAMERB, + ADI_ADRV9025_ERR_GPINT_PA_PROTECT_CH1, + ADI_ADRV9025_ERR_GPINT_PA_PROTECT_CH2, + ADI_ADRV9025_ERR_GPINT_STREAM_ERROR, + ADI_ADRV9025_ERR_GPIO_NUMBER_OF_ERRORS /* Keep this ENUM last as a reference to the total number of error enum values */ +} adi_adrv9025_GpioErrCodes_e; + +/** +* \brief Enum for selecting the GP_INT channel +*/ +typedef enum adi_adrv9025_gpMaskSelect +{ + ADI_ADRV9025_GPINT0, + ADI_ADRV9025_GPINT1, + ADI_ADRV9025_GPINTALL, + ADI_ADRV9025_GPINT_NUMBER_OF_CHANNELS /* Keep this ENUM last as a reference to the total number of gp channel enum values */ +} adi_adrv9025_gpMaskSelect_e; + +/** +* \brief data structure holding the gp interrupt mask values +*/ +typedef struct adi_adrv9025_gp_MaskArray +{ + uint64_t gpInt0Mask; + uint64_t gpInt1Mask; +} adi_adrv9025_gp_MaskArray_t; + +/** + * \brief GPIO settings for SPI2 TxAtten select + */ +typedef enum adi_adrv9025_Spi2TxAttenGpioSel +{ + ADI_ADRV9025_SPI2_TXATTEN_DISABLE = 0, /*!< Disable GPIO for SPI2 Tx Attenuation select */ + ADI_ADRV9025_SPI2_TXATTEN_GPIO4 = 1, /*!< Select GPIO4 for SPI2 Tx Attenuation select */ + ADI_ADRV9025_SPI2_TXATTEN_GPIO5 = 2, /*!< Select GPIO5 for SPI2 Tx Attenuation select */ + ADI_ADRV9025_SPI2_TXATTEN_GPIO6 = 3, /*!< Select GPIO6 for SPI2 Tx Attenuation select */ + ADI_ADRV9025_SPI2_TXATTEN_GPIO7 = 4, /*!< Select GPIO7 for SPI2 Tx Attenuation select */ + ADI_ADRV9025_SPI2_TXATTEN_GPIO8 = 5, /*!< Select GPIO8 for SPI2 Tx Attenuation select */ + ADI_ADRV9025_SPI2_TXATTEN_GPIO9 = 6, /*!< Select GPIO9 for SPI2 Tx Attenuation select */ + ADI_ADRV9025_SPI2_TXATTEN_GPIO10 = 7, /*!< Select GPIO10 for SPI2 Tx Attenuation select */ + ADI_ADRV9025_SPI2_TXATTEN_GPIO11 = 8, /*!< Select GPIO11 for SPI2 Tx Attenuation select */ + ADI_ADRV9025_SPI2_TXATTEN_GPIO12 = 9, /*!< Select GPIO12 for SPI2 Tx Attenuation select */ + ADI_ADRV9025_SPI2_TXATTEN_GPIO13 = 10, /*!< Select GPIO13 for SPI2 Tx Attenuation select */ + ADI_ADRV9025_SPI2_TXATTEN_GPIO14 = 11, /*!< Select GPIO14 for SPI2 Tx Attenuation select */ + ADI_ADRV9025_SPI2_TXATTEN_GPIO15 = 12, /*!< Select GPIO15 for SPI2 Tx Attenuation select */ + ADI_ADRV9025_SPI2_TXATTEN_GPIO16 = 13, /*!< Select GPIO16 for SPI2 Tx Attenuation select */ + ADI_ADRV9025_SPI2_TXATTEN_GPIO17 = 14, /*!< Select GPIO17 for SPI2 Tx Attenuation select */ + ADI_ADRV9025_SPI2_TXATTEN_GPIO18 = 15 /*!< Select GPIO18 for SPI2 Tx Attenuation select */ +} adi_adrv9025_Spi2TxAttenGpioSel_e; + +/** +* \brief GP_INT status general structure +*/ +typedef struct adi_adrv9025_gpIntStatus +{ + uint64_t gp_Interrupt_Status; + uint64_t gp_Int_Irq_Mask; + uint64_t gp_Int_Active_Sources; + uint64_t gp_Int_Save_Irq_Mask0; + uint64_t gp_Int_Save_Irq_Mask1; + uint64_t gp_Int_StickyBit_Mask; + int32_t gp_Int_Recovery_Action; + const char* gp_Int_Error_Message; +} adi_adrv9025_gpIntStatus_t; + +/** +* \brief Enum to select AuxDAC +* AuxDAC0-3 use AuxDACs located at Analog Tx1 +* AuxDAC4-7 use AuxDACs located at Analog Tx2 +*/ +typedef enum adi_adrv9025_AuxDacs +{ + ADI_ADRV9025_AUXDAC0 = 0x01, /*!< AuxDAC0 */ + ADI_ADRV9025_AUXDAC1 = 0x02, /*!< AuxDAC1 */ + ADI_ADRV9025_AUXDAC2 = 0x04, /*!< AuxDAC2 */ + ADI_ADRV9025_AUXDAC3 = 0x08, /*!< AuxDAC3 */ + ADI_ADRV9025_AUXDAC4 = 0x10, /*!< AuxDAC4 */ + ADI_ADRV9025_AUXDAC5 = 0x20, /*!< AuxDAC5 */ + ADI_ADRV9025_AUXDAC6 = 0x40, /*!< AuxDAC6 */ + ADI_ADRV9025_AUXDAC7 = 0x80 /*!< AuxDAC7 */ +} adi_adrv9025_AuxDacs_e; + +/** +* \brief Data structure to hold ADRV9025 AuxDAC Configuration +*/ +typedef struct adi_adrv9025_AuxDacCfg +{ + uint32_t auxDacMask; /*!< AuxDAC Selection - Bit0:AuxDAC0 | Bit1:AuxDAC1 | ... | Bit7:AuxDAC7 */ + uint8_t enable; /*!< 1:Enable selected AuxDAC, 0:Disable selected AuxDAC */ +} adi_adrv9025_AuxDacCfg_t; + +/** +* \brief Data structure to hold ADRV9025 AuxDAC Value +*/ +typedef struct adi_adrv9025_AuxDacValue +{ + uint32_t auxDacMask; /*!< AuxDAC Selection - Bit0:AuxDAC0 | Bit1:AuxDAC1 | ... | Bit7:AuxDAC7 */ + uint16_t dacWord; /*!< 12 bit AuxDAC word - 0-4095 maps to 0-1.8V*/ +} adi_adrv9025_AuxDacValue_t; + +/** +* \brief Data structure to hold ADRV9025 AuxDAC Value +*/ +typedef struct adi_adrv9025_AuxDacVoltage +{ + uint32_t auxDacMask; /*!< AuxDAC Selection - Bit0:AuxDAC0 | Bit1:AuxDAC1 | ... | Bit7:AuxDAC7 */ + uint16_t dacVoltage; /*!< AuxDAC voltage between 0-1800mV*/ +} adi_adrv9025_AuxDacVoltage_t; + +/** + * \brief Aux ADC input selection + * + * Two aux ADCs are available for use and both have two available inputs 0 + * and 1 which can be selected using a common set of enumerations. A specific + * ADC input is target by selecting both the desired ADC + * (see adi_adrv9025_AuxAdcSelect_e) and the desired input channel with this + * enumeration. + */ +typedef enum adi_adrv9025_AuxAdcInputSelect +{ + ADI_ADRV9025_AUXADC_INPUT_0 = 0x3, /*!< Aux ADC input 0 selection */ + ADI_ADRV9025_AUXADC_INPUT_1 = 0x2 /*!< Aux ADC input 1 selection */ +} adi_adrv9025_AuxAdcInputSelect_e; + +/** + * \brief Aux ADC selection + * + * Select which ADC to target for either configuration (see adi_adrv9025_AuxAdcCfg_t) + * or value reading (see adi_adrv9025_AuxAdcValue_t) + */ +typedef enum adi_adrv9025_AuxAdcSelect +{ + ADI_ADRV9025_AUXADC_A = 0x0, /*!< Aux ADC A selection */ + ADI_ADRV9025_AUXADC_B = 0x1, /*!< Aux ADC B selection */ + ADI_ADRV9025_AUXADC_NUM = 0x2 /*!< Number of aux ADCs */ +} adi_adrv9025_AuxAdcSelect_e; + +/** + * \brief Aux ADC clock divide control selection + * + * The aux ADC's input clock is sourced from the device clock. + * The ADC's input clock should be nominally set to 20 MHz. + */ +typedef enum adi_adrv9025_AuxAdcClkDivide +{ + ADI_ADRV9025_AUXADC_CLKDIVIDE_32 = 0, /*!< Input clock divide by 32 */ + ADI_ADRV9025_AUXADC_CLKDIVIDE_1, /*!< No clock divide */ + ADI_ADRV9025_AUXADC_CLKDIVIDE_2, /*!< Input clock divide by 2 */ + ADI_ADRV9025_AUXADC_CLKDIVIDE_3, /*!< Input clock divide by 3 */ + ADI_ADRV9025_AUXADC_CLKDIVIDE_4, /*!< Input clock divide by 4 */ + ADI_ADRV9025_AUXADC_CLKDIVIDE_5, /*!< Input clock divide by 5 */ + ADI_ADRV9025_AUXADC_CLKDIVIDE_6, /*!< Input clock divide by 6 */ + ADI_ADRV9025_AUXADC_CLKDIVIDE_7, /*!< Input clock divide by 7 */ + ADI_ADRV9025_AUXADC_CLKDIVIDE_8, /*!< Input clock divide by 8 */ + ADI_ADRV9025_AUXADC_CLKDIVIDE_9, /*!< Input clock divide by 9 */ + ADI_ADRV9025_AUXADC_CLKDIVIDE_10, /*!< Input clock divide by 10 */ + ADI_ADRV9025_AUXADC_CLKDIVIDE_11, /*!< Input clock divide by 11 */ + ADI_ADRV9025_AUXADC_CLKDIVIDE_12, /*!< Input clock divide by 12 */ + ADI_ADRV9025_AUXADC_CLKDIVIDE_13, /*!< Input clock divide by 13 */ + ADI_ADRV9025_AUXADC_CLKDIVIDE_14, /*!< Input clock divide by 14 */ + ADI_ADRV9025_AUXADC_CLKDIVIDE_15, /*!< Input clock divide by 15 */ + ADI_ADRV9025_AUXADC_CLKDIVIDE_NUM_DIVIDE /*!< Number of clock divide settings*/ +} adi_adrv9025_AuxAdcClkDivide_e; + +/** + * \brief Aux ADC Enable + */ +typedef enum adi_adrv9025_AuxAdcEnable +{ + ADI_ADRV9025_AUXADC_DISABLE = 0, /*!< Aux ADC disabled */ + ADI_ADRV9025_AUXADC_ENABLE, /*!< Aux ADC enabled */ + ADI_ADRV9025_AUXADC_ENABLE_NUM /*!< Number of enable enumerations*/ +} adi_adrv9025_AuxAdcEnable_e; + +/** + * \brief Aux ADC configuration + * + * Configuration structure used to configure the selected aux ADC. + * Note that a specific ADC input can be selected by selecting the + * appropriate ADC using auxAdcSelect and the ADC's input using auxAdcInputSelect. + * The current mapping of ADC inputs to physical input pins can be seen below. + * + * auxAdcSelect | auxAdcInputSelect | Device AUXADC pin + * ------------------------|------------------------------|-------------------- + * ADI_ADRV9025_AUXADC_A | ADI_ADRV9025_AUXADC_INPUT_0 | 0 + * ADI_ADRV9025_AUXADC_A | ADI_ADRV9025_AUXADC_INPUT_1 | 1 + * ADI_ADRV9025_AUXADC_B | ADI_ADRV9025_AUXADC_INPUT_0 | 2 + * ADI_ADRV9025_AUXADC_B | ADI_ADRV9025_AUXADC_INPUT_1 | 3 + * + * The ADC's output equation is the following: + * Dout = 4096*(Vin - 0.5v)/(Vdd - Vss) + 2048. + * Where Vdd in this case is the 1.0V domain: VCONV1_1P0 for Aux ADC A or + * VCONV2_1P0 for Aux ADC B. + * + */ +typedef struct adi_adrv9025_AuxAdcCfg +{ + adi_adrv9025_AuxAdcEnable_e auxAdcEnable; /*!< Enable or disable the selected ADC */ + adi_adrv9025_AuxAdcSelect_e auxAdcSelect; /*!< Select which ADC to configure */ + adi_adrv9025_AuxAdcInputSelect_e auxAdcInputSelect; /*!< Select which ADC input to use */ + adi_adrv9025_AuxAdcClkDivide_e auxAdcClkDivide; /*!< Clock divide setting */ +} adi_adrv9025_AuxAdcCfg_t; + +/** + * \brief Aux ADC sample + */ +typedef struct adi_adrv9025_AuxAdcValue +{ + adi_adrv9025_AuxAdcSelect_e auxAdcSelect; /*!< The ADC the sample originates from */ + uint16_t auxAdcValue; /*!< The 12 bit ADC sample */ +} adi_adrv9025_AuxAdcValue_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_GPIO_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_hal.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_hal.h new file mode 100644 index 0000000..0151fd3 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_hal.h @@ -0,0 +1,437 @@ +/** + * \file adi_adrv9025_hal.h + * \brief Contains prototypes and macro definitions for Private ADI HAL wrapper + * functions implemented in adi_adrv9025_hal.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_HAL_H_ +#define _ADI_ADRV9025_HAL_H_ + +#include "adi_adrv9025_hal_types.h" +#include "adi_platform.h" +#include "adi_adrv9025.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* TODO: Any user changeable #defines need to be moved to adi_adrv9025_user.h */ +#define HAL_TIMEOUT_DEFAULT 100 /* 100ms */ +#define HAL_TIMEOUT_NONE 0x0 /* Non-blocking */ +#define HAL_TIMEOUT_INFINITE 0xFFFFFFFF /* Blocking */ +#define HAL_TIMEOUT_MULT 2 /* HAL timeout worse-case factor */ + +#define MAXSPILOGMESSAGE 64 + +/* TODO: add #defines */ +#define ADRV9025_HW_RMW_LO_ADDR 0xFF /* Hardware Read Modify Write address */ +#define ADRV9025_HW_RMW_HI_ADDR 0x100 /* Hardware Read Modify Write address */ +#define ADRV9025_HW_RMW_MASK 0x101 /* Hardware Read Modify Write address */ +#define ADRV9025_HW_RMW_DATA 0x102 /* Hardware Read Modify Write address */ +#define ADRV9025_HW_RMW_BYTES 0xC /* Number of bytes required to use HW_RMW */ +#define ADRV9025_SPI_BYTES 0x3 /* Number of bytes required to use non HW_RMW */ +#define ADRV9025_SPI_WRITE_POLARITY 0x00 /* Write bit polarity for ADRV9025 */ + +/** +* \brief creates an array acceptable to the ADIHAL layer. +* SPI writes require 3 bytes two address and one data in order to change +* all 8 bits in register. if only a few bits are to be changed then a +* read Modify Write (RMW) operation is needed. +* The ADRV9025 provides a write only RMW which reduces spi transactions. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep{SPIARRAYTRIPSIZE} +* \dep{ADRV9025_HW_RMW_LO_ADDR} +* \dep{ADRV9025_HW_RMW_HI_ADDR} +* \dep{ADRV9025_HW_RMW_MASK} +* \dep{ADRV9025_HW_RMW_DATA} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param wrData the resulting array to be set to the HAL layer. +* \param numWrBytes The number of elements filled in the wrData array +* in a zero indexed array this points to the next empty location. +* \param addr The address to be added to wrData. +* \param mask The mask to be added to wrData, this will be 0 if packing a full byte. +* \param data The data to be added to wrData. +* \param writeFlag The value to be bitwise or'd into the MSB of the 16-bit address +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_adrv9025_SpiDataPack(adi_adrv9025_Device_t* device, + uint8_t* wrData, + uint16_t* numWrBytes, + uint16_t addr, + uint8_t mask, + uint8_t data, + uint8_t writeFlag); + +/** +* \brief writes a byte of data to the part. +* +* \dep_begin +* \dep{device->halInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param addr the address of the register to write to. +* \param data the value to write to the register. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_adrv9025_SpiByteWrite(adi_adrv9025_Device_t* device, + uint16_t addr, + uint8_t data); + +/** +* \brief Writes a full word to DMA registers . +* This function only supports B0 silicon +* +* \dep_begin +* \dep{device->halInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param data A full word to write. +* \param startAddress Address of most significant byte in full word +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_adrv9025_SpiDmaWordWrite(adi_adrv9025_Device_t* device, + const uint32_t data, + uint16_t startAddress); + +/** +* \brief Writes a data array with Spi streaming by using custom hal layer function (adi_hal_CustomSpiStreamWrite). +* To call this function, adi_hal_CustomSpiStreamWrite function pointer should point to custom spi stream write hal +* function which will transfer the "count" number of data bytes with A A D D D D packages. DMA Auto increment +* should be enabled to use this function. +* +* \dep_begin +* \dep{device->halInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param data Data array to write. +* \param count The number of bytes within data array. This must be multiple of 4. +* \param address Lowest address value for target DMA word +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_adrv9025_SpiWriteStreamWithCustomHalFunction(adi_adrv9025_Device_t* device, + const uint8_t data[], + uint32_t count, + uint16_t address); + +/** +* \brief Reads data array with Spi streaming by using custom hal layer function (adi_hal_CustomSpiStreamRead). +* To call this function, adi_hal_CustomSpiStreamRead function pointer should point to custom spi stream read hal +* function which will read the "count" number of data bytes with A A D D D D packages. DMA Auto increment +* should also be enabled to use this function. +* +* \dep_begin +* \dep{device->halInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param readData Data array to read. +* \param count The number of bytes within data array. This must be multiple of 4. +* \param address Lowest address value for target DMA word +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_adrv9025_SpiReadStreamWithCustomHalFunction(adi_adrv9025_Device_t* device, + uint8_t readData[], + uint32_t count, + uint16_t address); + +/** +* \brief Writes a data array with Spi streaming. +* This function allows reduction of API address overhead for writing consecutive DMA registers +* Streaming should have been enabled before calling this function. It only supports single/multiple full +* DMA word transfers. It holds spi CS low, transfer the data package and then pulls CS high to end SPI stream. +* Data package is transferred as => A A D D D D | A A D D D D | .... | A A D D D D | +* +* \dep_begin +* \dep{device->halInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param data Data array to write. +* \param count The number of bytes within data array. This must be multiple of 4. +* \param address Lowest address value for target DMA word +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_adrv9025_SpiDmaWordWriteStream(adi_adrv9025_Device_t* device, + const uint8_t data[], + uint32_t count, + uint16_t address); + +/** +* \brief Read a data array with Spi streaming . +* This function allows reduction of API address overhead for reading consecutive DMA registers +* Streaming should have been enabled before calling this function. It only supports single/multiple full +* DMA word transfers. It holds spi CS low, reads the data package and then pulls CS high to end SPI stream. +* Data package is transferred as => A A D D D D | A A D D D D | .... | A A D D D D | +* +* \dep_begin +* \dep{device->halInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param readData Read back data is returned in this array. +* \param count The number of bytes to read. This must be multiple of 4. +* \param address Lowest address value for target DMA word +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_adrv9025_SpiDmaWordReadStream(adi_adrv9025_Device_t* device, + uint8_t readData[], + uint32_t count, + uint16_t address); + +/** +* \brief Reads a full word from DMA registers . +* This function only supports B0 silicon +* +* \dep_begin +* \dep{device->halInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param data Pointer to memory location storing the word value read from memory. +* \param startAddress Address of most significant byte in full word +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_adrv9025_SpiDmaWordRead(adi_adrv9025_Device_t* device, + uint32_t* data, + uint16_t startAddress); + +/** +* \brief writes an array of bytes of data to the part. +* +* \dep_begin +* \dep{device->halInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param addr[] the addresses of the registers to write to. +* \param data[] the values to write to the registers. +* \param count the number of register addresses to write data to. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_adrv9025_SpiBytesWrite(adi_adrv9025_Device_t* device, + const uint16_t addr[], + const uint8_t data[], + uint32_t count); + +/** +* \brief reads a byte of data from the part. +* +* \dep_begin +* \dep{device->halInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param addr the address of the register to read from. +* \param readData a pointer to a location to write the register data to. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_adrv9025_SpiByteRead(adi_adrv9025_Device_t* device, + uint16_t addr, + uint8_t* readData); + +/** +* \brief reads an array of bytes of data from the part. +* +* \dep_begin +* \dep{device->halInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param addr[] the addresses of the registers to read from. +* \param readData[] the location to put the values to read from the registers. +* \param count the number of register addresses to read data from. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_adrv9025_SpiBytesRead(adi_adrv9025_Device_t* device, + const uint16_t addr[], + uint8_t readData[], + uint32_t count); + +/** +* \brief writes a field of data to the part. +* +* \dep_begin +* \dep{device->halInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param addr the address of the register to write to. +* \param fieldVal the value to write to the register. +* \param mask the mask to use when writing the value to the register. +* \param startBit the bit number where the field starts within the register. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_adrv9025_SpiFieldWrite(adi_adrv9025_Device_t* device, + uint16_t addr, + uint8_t fieldVal, + uint8_t mask, + uint8_t startBit); + +/** +* \brief reads a field of data from the part. +* +* \dep_begin +* \dep{device->halInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param addr the address of the register to read from. +* \param fieldVal pointer to a location to put the value read from the register. +* \param mask the mask to use when decoding the value to the register. +* \param startBit the bit number where the field starts within the register. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_adrv9025_SpiFieldRead(adi_adrv9025_Device_t* device, + uint16_t addr, + uint8_t* fieldVal, + uint8_t mask, + uint8_t startBit); + +/** +* \brief writes an array of bytes of data to the part. +* +* \dep_begin +* \dep{device->halInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param wrCache[] the values to write to the registers. +* \param count the number of register addresses to write data to. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_adrv9025_SpiCacheWrite(adi_adrv9025_Device_t* device, + const uint32_t wrCache[], + uint32_t count); + +/** +* \brief reads an array of bytes of data from the part. +* +* \dep_begin +* \dep{device->halInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param rdCache[] the addresses of the registers to read from. +* \param readData[] the location to put the values to read from the registers. +* \param count the number of register addresses to read data from. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_adrv9025_SpiCacheRead(adi_adrv9025_Device_t* device, + const uint32_t rdCache[], + uint8_t readData[], + uint32_t count); + +/** +* \brief verifies that hardware resources are available and have valid pointers allocated. +* +* \dep_begin +* \dep{device->halInfo} +* \dep_end +* +* \param device Pointer to the ADRV9010 device data structure. +* +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_adrv9025_HwVerify(adi_adrv9025_Device_t *device); + + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_HAL_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_hal_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_hal_types.h new file mode 100644 index 0000000..7c9ae19 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_hal_types.h @@ -0,0 +1,59 @@ +/** + * \file adi_adrv9025_hal_types.h + * \brief Contains prototypes and macro definitions for ADI HAL wrapper + * functions implemented in adi_adrv9025_hal.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef ADRV9025_HAL_TYPES_H_ +#define ADRV9025_HAL_TYPES_H_ + +#include +#include + +#include "adi_adrv9025.h" +#include "adi_common_hal.h" + +#ifdef __cplusplus +extern +"C" + { +#endif + +#define SPI_ADDR_SIZE 16 +#define SPI_DATA_SIZE 8 +#define SPI_MASK_SIZE 8 +#define HW_RMW_DATA_BYTES 12 + + +/** + * \brief Enum of possible HAL layer error codes. + */ +typedef enum adrv9025_Hal_Err +{ + ADRV9025HAL_OK = 0, /*!< HAL function successful. No error Detected */ + ADRV9025HAL_SPI_FAIL, /*!< HAL SPI operation failure. SPI controller Down */ + ADRV9025HAL_GPIO_FAIL, /*!< HAL GPIO function Failure */ + ADRV9025HAL_TIMER_FAIL, /*!< HAL Timer function Failure */ + ADRV9025HAL_WAIT_TIMEOUT, /*!< HAL function Timeout */ + ADRV9025HAL_LOG_FAIL, + ADRV9025HAL_LOG_LEVEL_FAIL, + ADRV9025HAL_HAL_MODE_FAIL, + ADRV9025HAL_GEN_SW, /*!< HAL function failed due to general invalid HAL data*/ + ADRV9025HAL_WARNING, /*!< HAL function warning that non critical error was detected*/ + ADRV9025HAL_BUFFER_OVERFLOW +} adrv9025_Hal_Err_e; + + +#ifdef __cplusplus +} +#endif + +#endif /* ADRV9025_HAL_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_radioctrl.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_radioctrl.h new file mode 100644 index 0000000..bd79e5a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_radioctrl.h @@ -0,0 +1,839 @@ +/** + * \file adi_adrv9025_radioctrl.h + * \brief Contains ADRV9025 related function prototypes for adi_adrv9025_radioctrl.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_RADIOCTRL_H_ +#define _ADI_ADRV9025_RADIOCTRL_H_ + +#include "adi_adrv9025_types.h" +#include "adi_adrv9025_radioctrl_types.h" +#include "adi_adrv9025_tx_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************** + * Initialization functions + **************************************************************************** + */ + +/** + * \brief Loads binary array into stream processor data memory + * + * A 20K element byte array is passed into this function. The byte array is + * obtained by reading the binary stream processor file provided by Analog + * Devices. The stream processor uses the information in the stream file to + * properly power up and down the various signal chains. + * + * \pre This function is called after after adi_adrv9025_Initialize, and before ARM is loaded. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 device data structure containing settings + * \param byteOffset Offset (starting from 0) of where to place the binary + * array (if loaded in multiple function calls) + * \param binary Byte array containing all valid ARM file data bytes + * \param byteCount The number of bytes in the binary arrayile + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_StreamImageWrite(adi_adrv9025_Device_t* device, + uint32_t byteOffset, + uint8_t binary[], + uint32_t byteCount); + +/** + * \brief Instructs the ADRV9025 ARM which GPIO pins are used for TDD pin control + * + * \brief Not currently implemented + * + * The ADRV9025 can control any of these related signals by sending an ARM command, or + * the ADRV9025 ARM signals can be routed to GPIO pins. Each signal in the armGpio + * structure has an enable member. If the enable member is set, the ADRV9025 ARM + * will expect the BBP to drive that signal on the specified GPIO pin. The + * signals can be intermixed - some on GPIO pins, and some set by ARM command. + * + * The BBP should call this function after loading the ARM processor via + * adi_adrv9025_ArmImageWrite() function call. If the BBP wishes to change the GPIO + * assignments this function can be called again to change the configuration while + * the ARM is in the radioOff state. This function also sets the ADRV9025 GPIO pin + * direction for any GPIO pins that are enabled in this function. + * + * \pre This function can be called after loading ADRV9025 ARM binary. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Structure pointer to the ADRV9025 data structure containing settings + * \param armGpio Pointer to structure that describes which GPIO pins/settings to use for each possible ARM GPIO signal + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_ArmGpioPinsSet(adi_adrv9025_Device_t* device, + adi_adrv9025_ArmGpioCfg_t* armGpio); + +/** +* \brief Commands the ADRV9025 ARM to retrieve the GPIO pins used for TDD control +* +* \brief Not currently implemented +* +* The GPIO pins not assigned to radio control are returned as INVALID +* +* The BBP should call this function after loading the ARM processor through +* adi_adrv9025_ArmImageWrite() function call. +* +* \pre This function can be called after loading ADRV9025 ARM binary. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 data structure containing settings +* \param armGpio Pointer to structure that describes which GPIO pins/settings to use for each possible ARM GPIO signal +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_ArmGpioPinsGet(adi_adrv9025_Device_t* device, + adi_adrv9025_ArmGpioCfg_t* armGpio); + +/** + * \brief This function sets up the mode (Pin Mode/Non-Pin Mode) through which the signal path is controlled + * + * The ADRV9025 device defaults to Non-pin mode on power up. This function is used to reconfigure + * the signal path control mode of Rx, ORx, Tx signal chains. Non-Pin mode signal chain control + * can be accomplished through adi_adrv9025_RxTxEnableSet() API. The pin mode signal chain control + * is accomplished through a combination of SPI registers dedicated input pins to ADRV9025 device. + * + * In Pin mode, the Tx and Rx signal chains are controlled using dedicated pins RX_ENABLE<3:0> and + * TX_ENABLE<3:0>. ORx enable in Pin mode is accomplished through a combination of dedicated ORX_ENABLE<3:0> + * pins alongwith SPI registers. The table below outlines the various ORx enable modes and corresponding ORx + * select mechanisms. + * + * ORx PIN Mode | ORx Select Mechanism + * -----------------------------|------------------------------------------------------------------------------------ + * Single Channel 3 Pin Mode | ORX_ENABLE[0] is enable/disable ctrl. ORx select is accomplished by ORX_ENABLE[2:1] + * Single Channel 2 Pin Mode | ORX_ENABLE[0] is enable/disable ctrl. ORx select is accomplished by SPI registers. + * | ORx select is multiplexed between 2 possible ORx channels depending on the level of ORx_ENABLE[1] pin + * Single Channel 1 Pin Mode | ORX_ENABLE[0] is enable/disable ctrl. ORx select is accomplished by SPI registers. + * Dual Channel 4 Pin Mode | ORX_ENABLE[1:0] pins are enable/disable ctrl. ORx select is accomplished by ORX_ENABLE[3:2] + * Dual Channel 2 Pin Mode | ORX_ENABLE[1:0] pins are enable/disable ctrl. ORx select is accomplished by SPI registers + * + * \pre This function may be called after the device has been fully initialized + * any time during run-time operation, but only after the ARM and GPIO + * have been configured + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param radioCtrlCfg is comprised of radio control mode configurations for Rx,ORx and Tx channels + * + * In Order to avoid configuration for a specific signal chain, set the respective enable mode to invalid. Eg: To avoid + * Tx configuration, set radioCtrlCfg->txRadioCtrlModeCfg.txEnableMode to ADI_ADRV9025_TX_EN_INVALID_MODE. Similarly + * to avoid Rx configuration set radioCtrlCfg->rxRadioCtrlModeCfg.rxEnableMode to ADI_ADRV9025_RX_EN_INVALID_MODE and + * to avoid ORx configuration set radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode to ADI_ADRV9025_ORX_EN_INVALID_MODE. + * + * Parameter radioCtrlCfg->singleChannel1PinModeOrxSel is ignored if radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode + * is not set to ADI_ADRV9025_ORX_EN_SINGLE_CH_1PIN_MODE + * + * Parameters radioCtrlCfg->singleChannel2PinModeLowOrxSel and radioCtrlCfg->singleChannel2PinModeHighOrxSel + * are ignored if radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode is not set to ADI_ADRV9025_ORX_EN_SINGLE_CH_2PIN_MODE + * + * Parameter radioCtrlCfg->dualChannel2PinModeOrxSel is ignored if radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode is + * not set to ADI_ADRV9025_ORX_EN_DUAL_CH_2PIN_MODE + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_RadioCtrlCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RadioCtrlModeCfg_t* radioCtrlCfg); + +/** +* \brief This function performs Range check on parameters passed to adi_adrv9025_RadioCtrlCfgSet() API +* +* This function is called automatically as part of adi_adrv9025_RadioCtrlCfgSet() if ADI_ADRV9025_RADIOCTRL_RANGE_CHECK +* is set to 1. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param radioCtrlCfg is comprised of radio control mode configurations for Rx,ORx and Tx channels +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RadioCtrlCfgSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RadioCtrlModeCfg_t* radioCtrlCfg); + +/** + * \brief Reads back the Tx, Rx, and ORx radio control mode configuration + * + * This function retrieves Pin mode / Non pin mode configuration of + * radio ctrl modes for Rx/Tx/ORx signal chains. For Rx and Tx signal chains, + * a SPI or Pin mode is returned. For the ORx signal chain, in addition to SPI vs + * Pin mode control, settling delay(in terms of arm clk cycles) alongwith Single + * channel 2 Pin and 1 Pin mode ORx channel selects, dual channel 2 pin mode ORx channel + * selects are returned. + * + * \pre This function may be called after the device has been fully initialized + * any time during run-time operation, but only after the ARM and GPIO + * have been configured + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 data structure + * \param rxChannel Receiver channel for which mode config readback is requested (valid channels Rx1-Rx4) + * \param txChannel Transmitter channel for which mode config readback is requested (valid channels Tx-Tx4) + * \param radioCtrlCfg Pointer to radio ctrl config data structure which will be updated with read back + * values for Rx,Tx and ORx signal chain control configs. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_RadioCtrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_RadioCtrlModeCfg_t* radioCtrlCfg); + +/**************************************************************************** + * Runtime functions + **************************************************************************** + */ + +/** + * \brief Reads the current ARM radio state + * + * Currently, *radioStatus only returns data in the lower 8 bits, but + * is defined as a 32-bit status word to permit future bitfield expansion. + * + * Bits | Bitfield + * ------------------------- + * 1:0 | State[1:0], 0 = POWERUP, 1 = READY, 2 = IDLE, 3 = RADIO ON + * 2 | Indicates invalid Rx/Tx/ORx profile information was loaded into ARM memory during init/ARM powerup + * 7:3 | unused + * + * \pre This function may be called any time after full device initialization + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the device settings structure + * \param radioStatus The current ARM radio state is returned in this parameter + * + * \retval TALACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval TALACT_ERR_RESET_SPI Recovery action for SPI reset required + * \retval TALACT_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_RadioStateGet(adi_adrv9025_Device_t* device, + uint32_t* radioStatus); + +/** +* \brief This API sets the Rx/ORx/Tx channels to be enabled or disabled in the +* transceiver if the signal chain control is configured to be in SPI mode +* +* For use cases where pin mode is not required, this function can be used to +* enable/disable the Rx/ORx/Tx signal paths. This +* function should be called after initialization and loading the stream +* processor. +* +* \pre This function should be called after initialization and loading the stream +* processor. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param rxChannelMask Desired Rx/ORx signal chain (channel) to power up +* \param txChannelMask Desired Tx signal chains (channel) to power up +* +* The following table lists the rxChannelMask bits and the corresponding channels +* that are enabled/disabled in SPI mode +* +* rxChannelMask | Channel Enable/Disable +* -----------------|------------------------------------ +* bit[0] | 1 = Rx1 Enable, 0 = Rx1 Disable +* bit[1] | 1 = Rx2 Enable, 0 = Rx2 Disable +* bit[2] | 1 = Rx3 Enable, 0 = Rx3 Disable +* bit[3] | 1 = Rx4 Enable, 0 = Rx4 Disable +* bit[4] | 1 = ORx1 Enable, 0 = ORx1 Disable +* bit[5] | 1 = ORx2 Enable, 0 = ORx2 Disable +* bit[6] | 1 = ORx3 Enable, 0 = ORx3 Disable +* bit[7] | 1 = ORx4 Enable, 0 = ORx4 Disable +* +* The following table lists the txChannelMask bits and the corresponding channels +* that are enabled/disabled in SPI mode +* +* txChannelMask | Channel Enable/Disable +* -----------------|------------------------------------ +* bit[0] | 1 = Tx1 Enable, 0 = Tx1 Disable +* bit[1] | 1 = Tx2 Enable, 0 = Tx2 Disable +* bit[2] | 1 = Tx3 Enable, 0 = Tx3 Disable +* bit[3] | 1 = Tx4 Enable, 0 = Tx4 Disable +* +* \retval ADI_ADRV9025_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxTxEnableSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint32_t txChannelMask); + +/** +* \brief This function performs range check for adi_adrv9025_RxTxEnableSet API +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param rxChannelMask Desired Rx/ORx signal chain (channel) to power up +* \param txChannelMask Desired Tx signal chains (channel) to power up +* +* \retval ADI_ADRV9025_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxTxEnableSetRangeCheck(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint32_t txChannelMask); + +/** +* \brief This API reads back the Rx/ORx/Tx channels that are powered up in the +* transceiver +* +* For use cases where pin mode is not required, this function can be used to +* read the current state of the Rx/ORx/Tx channel enable (power up) signals. +* This function should be called after initialization and loading the stream +* processor. +* +* \pre This function can be called after initialization. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param rxChannelMask Current Rx/ORx signal chains enabled returned to this pointer address +* \param txChannelMask Current Tx signal chains enabled returned to this pointer address +* +* The following table lists the rxChannelMask bits and the corresponding channels +* that will be enabled/disabled in SPI mode +* +* rxChannelMask | Channel Enable/Disable +* -----------------|------------------------------------ +* bit[0] | 1 = Rx1 Enabled, 0 = Rx1 Disabled +* bit[1] | 1 = Rx2 Enabled, 0 = Rx2 Disabled +* bit[2] | 1 = Rx3 Enabled, 0 = Rx3 Disabled +* bit[3] | 1 = Rx4 Enabled, 0 = Rx4 Disabled +* bit[4] | 1 = ORx1 Enabled, 0 = ORx1 Disabled +* bit[5] | 1 = ORx2 Enabled, 0 = ORx2 Disabled +* bit[6] | 1 = ORx3 Enabled, 0 = ORx3 Disabled +* bit[7] | 1 = ORx4 Enabled, 0 = ORx4 Disabled +* +* The following table lists the txChannelMask bits and the corresponding channels +* that will be enabled/disabled in SPI mode +* +* txChannelMask | Channel Enable/Disable +* -----------------|------------------------------------ +* bit[0] | 1 = Tx1 Enabled, 0 = Tx1 Disabled +* bit[1] | 1 = Tx2 Enabled, 0 = Tx2 Disabled +* bit[2] | 1 = Tx3 Enabled, 0 = Tx3 Disabled +* bit[3] | 1 = Tx4 Enabled, 0 = Tx4 Disabled +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxTxEnableGet(adi_adrv9025_Device_t* device, + uint32_t* rxChannelMask, + uint32_t* txChannelMask); + +/** +* \brief This function associates a GPIO pin with stream processor GP inputs and enables stream trigger +* functionality if a valid GPIO(GPIO0-GPIO15) is assigned to the streamGpInput pins. +* +* There are 16 GPIO inputs available to trigger streams. These GPIO pins can +* be mapped to one of GPIOs[0:15]. +* +* To unmap a GPIO association with a stream GP input, please set the GPIO input +* to ADI_ADRV9025_GPIO_INVALID. +* +* For B0 HW the GPIO pins are now hard coded to stream triggers as defined in the table below +* +* Stream | StreamNo +* --------------|--------- +* GPIO_0_FALL | 0x23 +* GPIO_1_FALL | 0x24 +* GPIO_2_FALL | 0x25 +* GPIO_3_FALL | 0x26 +* GPIO_4_FALL | 0x34 +* GPIO_5_FALL | 0x35 +* GPIO_6_FALL | 0x36 +* GPIO_7_FALL | 0x37 +* GPIO_8_FALL | 0x38 +* GPIO_9_FALL | 0x39 +* GPIO_10_FALL | 0x3A +* GPIO_11_FALL | 0x3B +* GPIO_12_FALL | 0x3C +* GPIO_13_FALL | 0x3D +* GPIO_14_FALL | 0x3E +* GPIO_15_FALL | 0x3F +* GPIO_0_HIGH | 0x27 +* GPIO_1_HIGH | 0x28 +* GPIO_2_HIGH | 0x29 +* GPIO_3_HIGH | 0x2A +* GPIO_4_HIGH | 0x40 +* GPIO_5_HIGH | 0x41 +* GPIO_6_HIGH | 0x42 +* GPIO_7_HIGH | 0x43 +* GPIO_8_HIGH | 0x44 +* GPIO_9_HIGH | 0x45 +* GPIO_10_HIGH | 0x46 +* GPIO_11_HIGH | 0x47 +* GPIO_12_HIGH | 0x48 +* GPIO_13_HIGH | 0x49 +* GPIO_14_HIGH | 0x4A +* GPIO_15_HIGH | 0x4B +* +* \pre This function requires ARM and Stream binaries to be loaded +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param streamGpioPinCfg Pointer to the structure holding GPIO pin to stream GP input mappings (Input) +* +* \retval ADI_ADRV9025_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_StreamGpioConfigSet(adi_adrv9025_Device_t* device, + adi_adrv9025_StreamGpioPinCfg_t* streamGpioPinCfg); + +/** +* \brief This function retrieves the current Tx-ORx mapping control GPIO pins +* +* This function retrieves the GPIOs assigned for Tx-ORx mapping stream triggering +* +* \pre This function can be called anytime after ADRV9025 device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param streamGpioPinCfg Pointer to the structure which will be updated with the +* active GPIO pin to stream GP input mappings (Output) +* +* \retval ADI_ADRV9025_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_StreamGpioConfigGet(adi_adrv9025_Device_t* device, + adi_adrv9025_StreamGpioPinCfg_t* streamGpioPinCfg); + +/** +* \brief Sets the Tx to ORx external signal routing for external LOL initialization calibrations and tracking calibrations +* +* This function invokes the streams required to setup a Tx to ORx mapping configuration. +* +* Shown below are the Tx channels that can be mapped to ORx Front End inputs. +* +* ORx Front End | Possible Tx channels that can be Mapped to ORx input +* -------------------------------|----------------------------------------------------- +* ADI_ADRV9025_ORX1 | ADI_ADRV9025_TX1, ADI_ADRV9025_TX2, ADI_ADRV9025_TXOFF(disables Tx-ORx1 mapping) +* ADI_ADRV9025_ORX2 | ADI_ADRV9025_TX1, ADI_ADRV9025_TX2, ADI_ADRV9025_TXOFF(disables Tx-ORx2 mapping) +* ADI_ADRV9025_ORX3 | ADI_ADRV9025_TX3, ADI_ADRV9025_TX4, ADI_ADRV9025_TXOFF(disables Tx-ORx3 mapping) +* ADI_ADRV9025_ORX4 | ADI_ADRV9025_TX3, ADI_ADRV9025_TX4, ADI_ADRV9025_TXOFF(disables Tx-ORx4 mapping) +* +* Please note that if ADI_ADRV9025_TXOFF is chosen as the tx channel to be mapped to ORx, then the Tx-ORx mapping +* for that ORx front end will be disabled. +* +* \pre This function may be called after the ARM has been initialized and loaded. But, before initialization +* calibrations are run because this is used for both the external LOL initialization and tracking calibrations. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param orxChannel Target ORx Front end for Tx-ORx mapping +* \param txChannel Target Tx channel that is routed back into the requested ORx channel +* +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_ERR_RESET_ARM Recovery action for user ARM reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxToOrxMappingSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e orxChannel, + adi_adrv9025_TxChannels_e txChannel); + +/** +* \brief Gets the Tx to ORx external signal routing for external LOL initialization calibrations and tracking calibrations +* +* This function commands the ARM to return the Tx channel mapped to the requested ORx channel +* +* \pre This function may be called after the ARM and Stream processors have been initialized and loaded. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param orxChannel The ORx channel for which Tx channel mapping is requested +* \param txChannel The Tx channel map to the ORx channel +* +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_ERR_RESET_ARM Recovery action for user ARM reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxToOrxMappingGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e orxChannel, + adi_adrv9025_TxChannels_e* txChannel); + +/** +* \brief Sets the RF PLL local oscillator (LO) frequency (RF carrier frequency). +* +* \pre This function can be called after the ARM has been initialized, and +* device must be in radioOff state. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param pllName Name of the PLL to configure based on the enumerated types in adi_adrv9025_RfPllName_e +* \param pllLoFrequency_Hz Desired RF LO frequency in Hz +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PllFrequencySet(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + uint64_t pllLoFrequency_Hz); + +/** +* \brief Sets the RF PLL settings for the desired LO +* +* \pre This function can be called after the ARM has been initialized, and +* device must be in radioOff state. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param pllConfig Pointer to the PLL config settings +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PllFrequencySet_v2(adi_adrv9025_Device_t* device, + adi_adrv9025_PllConfig_t* pllConfig); + +/** +* \brief Performs range check on parameters for adi_adrv9025_PllFrequencySet function +* +* This function is used to set a PLL's current frequency. An adi_adrv9025_RfPllName_e enumerated type is passed for +* the desired PLL frequency to set: LO1_PLL, LO2_PLL or AUX_PLL. +* +* \pre This function is automatically called as part of adi_adrv9025_PllFrequencySet if +* ADI_ADRV9025_RADIOCTRL_RANGE_CHECK is set to 1. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param pllName Name of the PLL to configure based on the enumerated types in adi_adrv9025_RfPllName_e +* \param pllLoFrequency_Hz Desired RF LO frequency in Hz +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PllFrequencySetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + uint64_t pllLoFrequency_Hz); + +/** +* \brief Performs range check on parameters for adi_adrv9025_PllFrequencySet_v2 function +* +* \pre This function is automatically called as part of adi_adrv9025_PllFrequencySet_v2 if +* ADI_ADRV9025_RADIOCTRL_RANGE_CHECK is set to 1. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param pllConfig Pointer to the PLL config settings +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PllFrequencySetRangeCheck_v2(adi_adrv9025_Device_t* device, + adi_adrv9025_PllConfig_t* pllConfig); + +/** +* \brief Gets a PLL Local Oscillator (LO) frequency (RF carrier frequency). +* +* This function is used to get a PLL's current frequency. A adi_adrv9025_RfPllName_e enumerated type is passed for +* the desired PLL frequency to read: LO1_PLL, LO2_PLL or AUX_PLL. +* +* \pre This function can be used after the device has been initialized, ARM firmware loaded and the +* PLLs configured. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param pllName Name of the desired PLL to read the frequency +* \param pllLoFrequency_Hz Current LO frequency for the PLL specified +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PllFrequencyGet(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + uint64_t* pllLoFrequency_Hz); + +/** + * \brief Checks if the PLLs are locked + * + * This function returns the status of the ADRV9025 PLLs via the pllLockStatus pointer. + * The 4 LSBs of the uint32_t value at pllLockStatus represent the lock status + * of the CLK PLL, RF PLL and AUX PLL. + * + * pllLockStatus bit 0 = CLK PLL Lock status + * pllLockStatus bit 1 = LO1 PLL Lock status + * pllLockStatus bit 2 = LO2 PLL Lock status + * pllLockStatus bit 3 = AUX(LO3) PLL Lock Status + * + * A bit value of 1 indicates the corresponding PLL is locked + * A bit value of 0 indicates the corresponding PLL is unlocked. + * + * \pre This may be called any time after the PLLs have been configured and + * are operational. This also requires the lockdet_mode<1:0> to have a value + * of either 1(Run Lock Detect once) or 2(Run Lock Detect Continuously) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 device data structure containing settings + * \param pllLockStatus PLLs lock status byte pointer to return the bit wise representation of + * the ADRV9025 PLLs lock status + * + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_PllStatusGet(adi_adrv9025_Device_t* device, + uint32_t* pllLockStatus); + +/** + * \brief Performs Range Check for adi_adrv9025_PllLoopFilterSet function + * + * \pre This function is called automatically as part of adi_adrv9025_PllLoopFilterSet + * API if ADI_ADRV9025_RADIOCTRL_RANGE_CHECK is set to 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 device data structure containing settings + * \param pllName selects the target PLL for loop filter configuration + * \param pllLoopFilterConfig pointer to the PLL loop filter configuration structure. + * Configuration includes the following 1) Phase margin (40 - 85 degrees), + * 2) Loop BW(50KHz - ) 3) Power Scale(0 - 10, default is 10) + * + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_CHECK_TIMER Recovery action for timer time-out check required + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_ERR_RESET_ARM Recovery action for ARM reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_PllLoopFilterSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + adi_adrv9025_PllLoopFilterCfg_t* pllLoopFilterConfig); + +/** +* \brief Sets the configuration for the PLL loop filter +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param pllName selects the target PLL for loop filter configuration +* \param pllLoopFilterConfig pointer to the PLL loop filter configuration structure. +* Configuration includes the following 1) Phase margin (40 - 85 degrees), +* 2) Loop BW(50KHz - ) 3) Power Scale(0 - 10, default is 10) +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PllLoopFilterSet(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + adi_adrv9025_PllLoopFilterCfg_t* pllLoopFilterConfig); + +/** + * \brief Gets the configuration for the RF PLL loop filter + * + * This function is used to get the current loop bandwidth, phase margin and the power scale + * factor for the PLL + * + * \pre This function can be used after the device has been initialized and the + * PLL configured. The ARM firmware must also be loaded and running. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 device data structure containing settings + * \param pllName selects the target PLL for loop filter configuration + * \param pllLoopFilterConfig pointer to the PLL loop filter configuration structure. + * + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_CHECK_TIMER Recovery action for timer time-out check required + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_ERR_RESET_ARM Recovery action for ARM reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_PllLoopFilterGet(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + adi_adrv9025_PllLoopFilterCfg_t* pllLoopFilterConfig); + +/** +* \brief Retrieves Current Dual Band status +* +* This function can be used to read back the current status of the dual band feature +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \pre This function may be called any time after device initialization +* +* \param device Pointer to the device settings structure +* \param status Pointer to variable which the dual band status value will be written +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ACT_ERR_RESET_CPU Recovery action for CPU reset required +* \retval ADI_ADRV9025_ACT_ERR_RERUN_INIT_CALS Recovery action rerun init cals required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DualBandStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DualbandStatus_e* status); + +/** +* \brief Reads back the version of the Stream binary loaded into the ADRV9025 ARM memory +* +* This function reads the ARM memory to read back the major.minor.maint.build releaseCandidate +* version for the Stream binary loaded into ARM memory. +* +* Dependencies +* - device->spiSettings->chipSelectIndex +* +* \param device is structure pointer to the ADRV9025 data structure containing settings +* \param streamVersion will be populated here, it is a pointer to struct type adi_adrv9025_StreamVersion_t. +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_ERR_RESET_ARM Recovery action for ARM reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_StreamVersionGet(adi_adrv9025_Device_t* device, + adi_adrv9025_StreamVersion_t* streamVersion); + +/**************************************************************************** +* Helper functions +**************************************************************************** +*/ + +/**************************************************************************** + * Debug functions + **************************************************************************** + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_RADIOCTRL_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_radioctrl_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_radioctrl_types.h new file mode 100644 index 0000000..987b78f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_radioctrl_types.h @@ -0,0 +1,352 @@ +/** + * \file adi_adrv9025_radioctrl_types.h + * \brief Contains ADRV9025 API Radio Control data types + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_RADIOCTRL_TYPES_H_ +#define _ADI_ADRV9025_RADIOCTRL_TYPES_H_ + +#include "adi_adrv9025_gpio_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * \brief Data structure to hold ARM GPIO pin assignments, polarity, and pin enable for the ADRV9025 ARM + */ +typedef struct adi_adrv9025_ArmGpioPinCfg +{ + adi_adrv9025_GpioPinSel_e gpioPinSel; /*!< Select desired GPIO pin to input into ADRV9025 (valid 0-15) */ + uint8_t polarity; /*!< Signal polarity (0 = Normal polarity, 1=ADRV9025 will invert the signal before using) */ + uint8_t enable; /*!< 1 = Enable ADRV9025 ARM use of GPIO signal, 0 = ADRV9025 ARM uses ARM command to set this signal value */ +} adi_adrv9025_ArmGpioPinCfg_t; + +/** + * \brief Data structure to hold ARM GPIO pin assignments for each ARM input/output pin. + */ +typedef struct adi_adrv9025_ArmGpioCfg +{ + /* ADRV9025 ARM input GPIO pins -- Only valid if orxPinMode = 1 */ + adi_adrv9025_ArmGpioPinCfg_t orx1TxSel0Pin; /*!< Select desired GPIO pin as input to ADRV9025(valid 0-18), polarity, enable */ + adi_adrv9025_ArmGpioPinCfg_t orx1TxSel1Pin; /*!< Select desired GPIO pin as input to ADRV9025(valid 0-18), polarity, enable */ + adi_adrv9025_ArmGpioPinCfg_t orx2TxSel0Pin; /*!< Select desired GPIO pin as input to ADRV9025(valid 0-18), polarity, enable */ + adi_adrv9025_ArmGpioPinCfg_t orx2TxSel1Pin; /*!< Select desired GPIO pin as input to ADRV9025(valid 0-18), polarity, enable */ + adi_adrv9025_ArmGpioPinCfg_t orx3TxSel0Pin; /*!< Select desired GPIO pin as input to ADRV9025(valid 0-18), polarity, enable */ + adi_adrv9025_ArmGpioPinCfg_t orx3TxSel1Pin; /*!< Select desired GPIO pin as input to ADRV9025(valid 0-18), polarity, enable */ + adi_adrv9025_ArmGpioPinCfg_t orx4TxSel0Pin; /*!< Select desired GPIO pin as input to ADRV9025(valid 0-18), polarity, enable */ + adi_adrv9025_ArmGpioPinCfg_t orx4TxSel1Pin; /*!< Select desired GPIO pin as input to ADRV9025(valid 0-18), polarity, enable */ + adi_adrv9025_ArmGpioPinCfg_t tx12CalEnPin; /*!< Select desired GPIO pin as input to ADRV9025(valid 0-18), polarity, enable */ + adi_adrv9025_ArmGpioPinCfg_t tx34CalEnPin; /*!< Select desired GPIO pin as input to ADRV9025(valid 0-18), polarity, enable */ + adi_adrv9025_ArmGpioPinCfg_t calUpdate0Pin; /*!< Select desired GPIO pin as input to ADRV9025(valid 0-18), polarity, enable */ + adi_adrv9025_ArmGpioPinCfg_t calUpdate1Pin; /*!< Select desired GPIO pin as input to ADRV9025(valid 0-18), polarity, enable */ + adi_adrv9025_ArmGpioPinCfg_t calUpdate2Pin; /*!< Select desired GPIO pin as input to ADRV9025(valid 0-18), polarity, enable */ + adi_adrv9025_ArmGpioPinCfg_t rfPllFreqHopPin; /*!< Select desired GPIO pin as input to ADRV9025(valid 0-18), polarity, enable */ +} adi_adrv9025_ArmGpioCfg_t; + +/** +* \brief Data structure to hold Stream trigger GPIO pin assignments that can be used to trigger streams. +*/ +typedef struct adi_adrv9025_StreamGpioPinCfg +{ + adi_adrv9025_GpioPinSel_e streamGpInput0; /*!< Select desired GPIO pin input to ADRV9025 stream processor GP input 0 (valid GPIO0-GPIO15). To disable select ADI_ADRV9025_GPIO_INVALID */ + adi_adrv9025_GpioPinSel_e streamGpInput1; /*!< Select desired GPIO pin input to ADRV9025 stream processor GP input 1 (valid GPIO0-GPIO15). To disable select ADI_ADRV9025_GPIO_INVALID */ + adi_adrv9025_GpioPinSel_e streamGpInput2; /*!< Select desired GPIO pin input to ADRV9025 stream processor GP input 2 (valid GPIO0-GPIO15). To disable select ADI_ADRV9025_GPIO_INVALID */ + adi_adrv9025_GpioPinSel_e streamGpInput3; /*!< Select desired GPIO pin input to ADRV9025 stream processor GP input 3 (valid GPIO0-GPIO15). To disable select ADI_ADRV9025_GPIO_INVALID */ + adi_adrv9025_GpioPinSel_e streamGpInput4; /*!< Select desired GPIO pin input to ADRV9025 stream processor GP input 4 (valid GPIO0-GPIO15). To disable select ADI_ADRV9025_GPIO_INVALID */ + adi_adrv9025_GpioPinSel_e streamGpInput5; /*!< Select desired GPIO pin input to ADRV9025 stream processor GP input 5 (valid GPIO0-GPIO15). To disable select ADI_ADRV9025_GPIO_INVALID */ + adi_adrv9025_GpioPinSel_e streamGpInput6; /*!< Select desired GPIO pin input to ADRV9025 stream processor GP input 6 (valid GPIO0-GPIO15). To disable select ADI_ADRV9025_GPIO_INVALID */ + adi_adrv9025_GpioPinSel_e streamGpInput7; /*!< Select desired GPIO pin input to ADRV9025 stream processor GP input 7 (valid GPIO0-GPIO15). To disable select ADI_ADRV9025_GPIO_INVALID */ + adi_adrv9025_GpioPinSel_e streamGpInput8; /*!< Select desired GPIO pin input to ADRV9025 stream processor GP input 8 (valid GPIO0-GPIO15). To disable select ADI_ADRV9025_GPIO_INVALID */ + adi_adrv9025_GpioPinSel_e streamGpInput9; /*!< Select desired GPIO pin input to ADRV9025 stream processor GP input 9 (valid GPIO0-GPIO15). To disable select ADI_ADRV9025_GPIO_INVALID */ + adi_adrv9025_GpioPinSel_e streamGpInput10; /*!< Select desired GPIO pin input to ADRV9025 stream processor GP input 10 (valid GPIO0-GPIO15). To disable select ADI_ADRV9025_GPIO_INVALID */ + adi_adrv9025_GpioPinSel_e streamGpInput11; /*!< Select desired GPIO pin input to ADRV9025 stream processor GP input 11 (valid GPIO0-GPIO15). To disable select ADI_ADRV9025_GPIO_INVALID */ + adi_adrv9025_GpioPinSel_e streamGpInput12; /*!< Select desired GPIO pin input to ADRV9025 stream processor GP input 12 (valid GPIO0-GPIO15). To disable select ADI_ADRV9025_GPIO_INVALID */ + adi_adrv9025_GpioPinSel_e streamGpInput13; /*!< Select desired GPIO pin input to ADRV9025 stream processor GP input 13 (valid GPIO0-GPIO15). To disable select ADI_ADRV9025_GPIO_INVALID */ + adi_adrv9025_GpioPinSel_e streamGpInput14; /*!< Select desired GPIO pin input to ADRV9025 stream processor GP input 14 (valid GPIO0-GPIO15). To disable select ADI_ADRV9025_GPIO_INVALID */ + adi_adrv9025_GpioPinSel_e streamGpInput15; /*!< Select desired GPIO pin input to ADRV9025 stream processor GP input 15 (valid GPIO0-GPIO15). To disable select ADI_ADRV9025_GPIO_INVALID */ +} adi_adrv9025_StreamGpioPinCfg_t; + +/** + * \brief Data structure to hold the radio state information. + */ +typedef enum adi_adrv9025_RadioState +{ + ADI_ADRV9025_RADIO_POWERUP = 0, + ADI_ADRV9025_RADIO_BOOTCOMPLETE, + ADI_ADRV9025_BOOTERROR +} adi_adrv9025_RadioState_e; + +/** + * \brief Enumerated list of Tx to ORx1/2 Front End mapping selections + */ +typedef enum adi_adrv9025_TxToOrx12Mapping +{ + ADI_ADRV9025_MAP_TX1_ORX12 = 0, /*!< Tx1 to ORx12 Front End mapping select */ + ADI_ADRV9025_MAP_TX2_ORX12 = 1 /*!< Tx2 to ORx12 Front End mapping select */ +} adi_adrv9025_TxToOrx12Mapping_e; + +/** +* \brief Enumerated list of Tx to ORx3/4 Front End mapping selections +*/ +typedef enum adi_adrv9025_TxToOrx34Mapping +{ + ADI_ADRV9025_MAP_TX3_ORX34 = 0, /*!< Tx3 to ORx3/4 Front End mapping select */ + ADI_ADRV9025_MAP_TX4_ORX34 = 1 /*!< Tx4 to ORx3/4 Front End mapping select */ +} adi_adrv9025_TxToOrx34Mapping_e; + +/** + * \brief Enum of PLL selections + */ +typedef enum adi_adrv9025_PllName +{ + ADI_ADRV9025_LO1_PLL = 0, /*!< Selects PLL LO1 for Rx and Tx */ + ADI_ADRV9025_LO2_PLL, /*!< Selects PLL LO2 for Rx and Tx */ + ADI_ADRV9025_AUX_PLL /*!< Selects AUX PLL for Rx and tx*/ +} adi_adrv9025_PllName_e; + +/** +* \brief Enum of PLL Mode selections +*/ +typedef enum adi_adrv9025_PllModeSel +{ + ADI_ADRV9025_PLL_SLOW_MODE = 0x00, /*!< Selects the PLL to be programmed to run in slow mode */ + ADI_ADRV9025_PLL_FAST_MODE = 0x00 /*!< Selects the PLL to be programmed to run in slow mode */ +} adi_adrv9025_PllModeSel_e; + +/** +* \brief Enum of PLL Aux LO resync selections +*/ +typedef enum adi_adrv9025_PllAuxLoResyncSel +{ + ADI_ADRV9025_PLL_AUX_LO_RESYNC_ENABLE = 0x00, /*!< Automatically resync AUX LO and TX LO (phase sync) */ + ADI_ADRV9025_PLL_AUX_LO_RESYNC_DISABLE = 0x20 /*!< Don't automatically resync AUX LO and TX LO (phase sync) */ +} adi_adrv9025_PllAuxLoResyncSel_e; + +/** +* \brief Enum of PLL Aux LO offset programming enable +*/ +typedef enum adi_adrv9025_PllAuxLoOffsetProgSel +{ + ADI_ADRV9025_PLL_AUX_LO_OFFSET_PROG_ENABLE = 0x00, /*!< Automatically program AUXPLL with offset LO when setting TX LO frequency */ + ADI_ADRV9025_PLL_AUX_LO_OFFSET_PROG_DISABLE = 0x40 /*!< Don't automatically program AUXPLL with offset LO when setting TX LO frequency */ +} adi_adrv9025_PllAuxLoOffsetProgSel_e; + +/** +* \brief Enum of Tx Enable Modes +*/ +typedef enum adi_adrv9025_TxEnableMode +{ + ADI_ADRV9025_TX_EN_SPI_MODE = 0, /*!< Selects SPI registers to control Tx signal path on/off */ + ADI_ADRV9025_TX_EN_PIN_MODE, /*!< Selects Pin mode to control Tx signal path on/off. Tx signal path is controlled by dedicated input pins to ARM */ + ADI_ADRV9025_TX_EN_INVALID_MODE +} adi_adrv9025_TxEnableMode_e; + +/** +* \brief Enum of Rx Enable Modes +*/ +typedef enum adi_adrv9025_RxEnableMode +{ + ADI_ADRV9025_RX_EN_SPI_MODE = 0, /*!< Selects SPI registers to control Rx signal path on/off */ + ADI_ADRV9025_RX_EN_PIN_MODE, /*!< Selects Pin mode to control Rx signal path on/off. Rx signal path is controlled by dedicated input pins to ARM */ + ADI_ADRV9025_RX_EN_INVALID_MODE +} adi_adrv9025_RxEnableMode_e; + +/** +* \brief Enum of ORx Enable Modes +*/ +typedef enum adi_adrv9025_ORxEnableMode +{ + ADI_ADRV9025_ORX_EN_SPI_MODE = 0, /*!< Selects SPI registers to control ORx signal path on/off */ + ADI_ADRV9025_ORX_EN_SINGLE_CH_3PIN_MODE, /*!< Selects Pin mode to control ORx signal path on/off. ORx_ENABLE[0] pin is the enable/disable select. ORx_ENABLE[1], ORx_ENABLE[2] pins can be used to select ORx channel*/ + ADI_ADRV9025_ORX_EN_SINGLE_CH_2PIN_MODE, /*!< Selects Pin mode to control ORx signal path on/off. ORx_ENABLE[0] pin is the enable/disable select. Channel select is accomplished by a combination of SPI reg and ORx_ENABLE[1] pin*/ + ADI_ADRV9025_ORX_EN_SINGLE_CH_1PIN_MODE, /*!< Selects Pin mode to control ORx signal path on/off. ORx_ENABLE[0] pin is the enable/disable select. Channel select is accomplished by SPI registers*/ + ADI_ADRV9025_ORX_EN_DUAL_CH_4PIN_MODE, /*!< Selects Pin mode to control ORx signal path on/off. ORx_ENABLE[0], ORx_ENABLE[1] pins are enable/disable switches. Channel select is accomplished by ORx_ENABLE[2] and ORx_ENABLE[3] pins*/ + ADI_ADRV9025_ORX_EN_DUAL_CH_2PIN_MODE, /*!< Selects Pin mode to control ORx signal path on/off. ORx_ENABLE[0], ORx_ENABLE[1] pins are enable/disable switches. Channel select is accomplished by SPI Registers*/ + ADI_ADRV9025_ORX_EN_INVALID_MODE +} adi_adrv9025_ORxEnableMode_e; + +/** +* \brief Enum of Single Channel ORx Pin Mode ORx select +*/ +typedef enum adi_adrv9025_SingleChannelPinModeOrxSel +{ + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX1_FE = 0, /*!< Selects ORx1 in single channel 2 pin / single channel 1 pin ORx pin mode */ + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE, /*!< Selects ORx2 in single channel 2 pin / single channel 1 pin ORx pin mode */ + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX3_FE, /*!< Selects ORx3 in single channel 2 pin / single channel 1 pin ORx pin mode */ + ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX4_FE, /*!< Selects ORx4 in single channel 2 pin / single channel 1 pin ORx pin mode */ + ADI_ADRV9025_SINGLE_CH_PIN_MODE_INVALID_ORX_SEL +} adi_adrv9025_SingleChannelPinModeOrxSel_e; + +/** +* \brief Enum of Dual Channel ORx Pin Mode ORx select +*/ +typedef enum adi_adrv9025_DualChannelPinModeOrxSel +{ + ADI_ADRV9025_DUAL_CH_PIN_MODE_ORX1_ORX3_SEL = 0, /*!< Selects ORx1 and ORx3 in dual channel 2 pin mode */ + ADI_ADRV9025_DUAL_CH_PIN_MODE_ORX2_ORX3_SEL, /*!< Selects ORx2 and ORx3 in dual channel 2 pin mode */ + ADI_ADRV9025_DUAL_CH_PIN_MODE_ORX1_ORX4_SEL, /*!< Selects ORx1 and ORx4 in dual channel 2 pin mode */ + ADI_ADRV9025_DUAL_CH_PIN_MODE_ORX2_ORX4_SEL, /*!< Selects ORx2 and ORx4 in dual channel 2 pin mode */ + ADI_ADRV9025_DUAL_CH_PIN_MODE_INVALID_ORX_SEL +} adi_adrv9025_DualChannelPinModeOrxSel_e; + +/** +* \brief Enumerated list of Tx to ORx1 mapping selections +*/ +typedef enum adi_adrv9025_TxToOrx1Mapping +{ + ADI_ADRV9025_MAP_NONE_ORX1 = 0, /*!< No Tx to ORx1 mapping select */ + ADI_ADRV9025_MAP_TX1_ORX1 = 2, /*!< Tx1 to ORx1 mapping select */ + ADI_ADRV9025_MAP_TX2_ORX1 = 3 /*!< Tx2 to ORx1 mapping select */ +} adi_adrv9025_TxToOrx1Mapping_e; + +/** +* \brief Enumerated list of Tx to ORx2 mapping selections +*/ +typedef enum adi_adrv9025_TxToOrx2Mapping +{ + ADI_ADRV9025_MAP_NONE_ORX2 = 0, /*!< No Tx to ORx2 mapping select */ + ADI_ADRV9025_MAP_TX1_ORX2 = 2, /*!< Tx1 to ORx2 mapping select */ + ADI_ADRV9025_MAP_TX2_ORX2 = 3 /*!< Tx2 to ORx2 mapping select */ +} adi_adrv9025_TxToOrx2Mapping_e; + +/** +* \brief Enumerated list of Tx to ORx3 mapping selections +*/ +typedef enum adi_adrv9025_TxToOrx3Mapping +{ + ADI_ADRV9025_MAP_NONE_ORX3 = 0, /*!< No Tx to ORx3 mapping select */ + ADI_ADRV9025_MAP_TX3_ORX3 = 2, /*!< Tx3 to ORx3 mapping select */ + ADI_ADRV9025_MAP_TX4_ORX3 = 3 /*!< Tx4 to ORx3 mapping select */ +} adi_adrv9025_TxToOrx3Mapping_e; + +/** +* \brief Enumerated list of Tx to ORx4 mapping selections +*/ +typedef enum adi_adrv9025_TxToOrx4Mapping +{ + ADI_ADRV9025_MAP_NONE_ORX4 = 0, /*!< No Tx to ORx4 mapping select */ + ADI_ADRV9025_MAP_TX3_ORX4 = 2, /*!< Tx3 to ORx4 mapping select */ + ADI_ADRV9025_MAP_TX4_ORX4 = 3 /*!< Tx4 to ORx4 mapping select */ +} adi_adrv9025_TxToOrx4Mapping_e; + +/** +* \brief Enum to describe dual band status +*/ +typedef enum adi_adrv9025_DualbandStatus +{ + ADI_ADRV9025_DUALBAND_SWITCHING_DISABLED = 0x00, + ADI_ADRV9025_DUALBAND_SWITCHING_ENABLED = 0x01 +} adi_adrv9025_DualbandStatus_e; + +/** +* \brief Data structure to hold Tx Signal Path Control configurations +*/ +typedef struct adi_adrv9025_TxRadioCtrlModeCfg +{ + adi_adrv9025_TxEnableMode_e txEnableMode; /*!< Configuration for Tx Channel Enable mode */ + uint32_t txChannelMask; /*!< Tx channels for which configuration is valid */ +} adi_adrv9025_TxRadioCtrlModeCfg_t; + +/** +* \brief Data structure to hold Rx Signal Path Control configurations +*/ +typedef struct adi_adrv9025_RxRadioCtrlModeCfg +{ + adi_adrv9025_RxEnableMode_e rxEnableMode; /*!< Configuration for Tx Channel Enable mode */ + uint32_t rxChannelMask; /*!< Tx channels for which configuration is valid */ +} adi_adrv9025_RxRadioCtrlModeCfg_t; + +/** +* \brief Data structure to hold ORx Signal Path Control configurations +*/ +typedef struct adi_adrv9025_ORxRadioCtrlModeCfg +{ + adi_adrv9025_ORxEnableMode_e orxEnableMode; /*!< Configuration for ORx Channel Enable mode */ + uint8_t orxPinSelectSettlingDelay_armClkCycles; /*!< Amount of time for the firmware to wait before sampling ORx Enable Pins */ + /* uint8_t enableOrxLowToHighStreams; */ /*!< 1 - Forces use of a specified ORx High and ORx Low streams, 0 - default channel streams are used */ + adi_adrv9025_SingleChannelPinModeOrxSel_e singleChannel1PinModeOrxSel; /*!< ORx channel select in single channel 1 pin ORx enable mode */ + adi_adrv9025_SingleChannelPinModeOrxSel_e singleChannel2PinModeLowOrxSel; /*!< ORx channel select when ORx_ENABLE[1] pin is low in single channel 2 pin ORx enable mode */ + adi_adrv9025_SingleChannelPinModeOrxSel_e singleChannel2PinModeHighOrxSel; /*!< ORx channel select when ORx_ENABLE[1] pin is high in single channel 2 pin ORx enable mode */ + adi_adrv9025_DualChannelPinModeOrxSel_e dualChannel2PinModeOrxSel; /*!< ORx channel select in dual channel 2 pin ORx enable mode */ +} adi_adrv9025_ORxRadioCtrlModeCfg_t; + +/** +* \brief Data structure to hold Signal Path Control configurations +*/ +typedef struct adi_adrv9025_RadioCtrlModeCfg +{ + adi_adrv9025_TxRadioCtrlModeCfg_t txRadioCtrlModeCfg; /*!< Tx signal path enable mode configuration */ + adi_adrv9025_RxRadioCtrlModeCfg_t rxRadioCtrlModeCfg; /*!< Rx signal path enable mode configuration */ + adi_adrv9025_ORxRadioCtrlModeCfg_t orxRadioCtrlModeCfg; /*!< ORx signal path enable mode configuration */ +} adi_adrv9025_RadioCtrlModeCfg_t; + +/** +* \brief Data structure to hold Tx to Orx mapping +*/ +typedef struct adi_adrv9025_TxToOrxMappingConfig +{ + adi_adrv9025_TxToOrx1Mapping_e orx1Map; /*!< Selects Tx feedback to ORx1 input */ + adi_adrv9025_TxToOrx2Mapping_e orx2Map; /*!< Selects Tx feedback to ORx2 input */ + adi_adrv9025_TxToOrx3Mapping_e orx3Map; /*!< Selects Tx feedback to ORx3 input */ + adi_adrv9025_TxToOrx4Mapping_e orx4Map; /*!< Selects Tx feedback to ORx4 input */ +} adi_adrv9025_TxToOrxMappingConfig_t; + +/** +* \brief Data structure to hold the PLL settings +*/ +typedef struct adi_adrv9025_PllConfig +{ + adi_adrv9025_PllName_e pllName; /*!< Select the target RF LO PLL source */ + adi_adrv9025_PllModeSel_e pllModeSel; /*!< PLL Mode select - Slow vs Fast mode */ + adi_adrv9025_PllAuxLoResyncSel_e pllAuxLoResyncSel; /* Aux LO Resync with Tx LO */ + adi_adrv9025_PllAuxLoOffsetProgSel_e pllAuxLoOffsetProgSel; /* Select if Aux LO is to be programmed with offset LO when programming Tx LO*/ + uint64_t pllLoFrequency_Hz; /*!< Desired RF LO frequency in Hz */ +} adi_adrv9025_PllConfig_t; + +/** +* \brief Data structure to hold Synthesizer PLL Loop filter settings +*/ +typedef struct adi_adrv9025_PllLoopFilterCfg +{ + uint16_t loopBandwidth_kHz; /*!< Synthesizer PLL Loop filter bandwidth. Range TBD */ + uint8_t phaseMargin_degrees; /*< Synthesizer PLL Loop filter phase margin in degrees. Range 40-85 */ + uint8_t powerScale; /*!< Synthesizer PLL Loop filter power scale. Range 0 - 10. Default is 10 */ +} adi_adrv9025_PllLoopFilterCfg_t; + +/** +*brief Data Structure to hold stream version settings +*/ +typedef struct adi_adrv9025_StreamVersion +{ + uint8_t majorVer; + uint8_t minorVer; + uint8_t mainVer; + uint8_t buildVer; +} adi_adrv9025_StreamVersion_t; + +#define ADRV9025_IMAGEINFOSIZE 4 +#define ADRV9025_MAINSTREAMSIZEMAX 4*1024 +#define ADRV9025_TXSTREAMSIZEMAX 1024 +#define ADRV9025_RXSTREAMSIZEMAX 1024 +#define ADRV9025_ORXSTREAMSIZEMAX 4*1024 +#define ADRV9025_MAINNUM 1 +#define ADRV9025_TXNUM 4 +#define ADRV9025_RXNUM 4 +#define ADRV9025_ORXNUM 2 +#define ADRV9025_STREAM_MAX 11 + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_RADIOCTRL_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_rx.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_rx.h new file mode 100644 index 0000000..9cad7d7 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_rx.h @@ -0,0 +1,1269 @@ +/** + * \file adi_adrv9025_rx.h + * \brief Contains ADRV9025 receive related function prototypes for + * adi_adrv9025_rx.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_RX_H_ +#define _ADI_ADRV9025_RX_H_ + +#include "adi_adrv9025_types.h" +#include "adi_adrv9025_rx_types.h" +#include "adi_common_error_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************** + * Initialization functions + **************************************************************************** + */ + +/** +* \brief Programs the gain table settings for Rx / ORx channels. +* +* This function can be called by the user to load a custom gain table or +* to reconfigure the gain table.The gain table for a receiver type is set with the +* parameters passed by adi_adrv9025_RxGainTableRow_t gainTablePtr array. +* The array length (n) is dependent upon receiver type. +* The (n) value is conveyed by numGainIndicesInTable. +* All gain tables have a maximum index and a minimum index specified by +* MAX_RX_GAIN_TABLE_NUMINDICES and MIN_RX_GAIN_TABLE_INDEX +* The minimum gain index is application dependent, this can be modified +* in the user space, the absolute maximum and minimum indices are specified +* by MAX_GAIN_TABLE_INDEX and MIN_GAIN_TABLE_INDEX +* +* The Rx max gain index is user configurable. A separate call has to be made +* to adi_adrv9025_RxMinMaxGainIndexSet() API to update the min and max gain +* indices for a given Rx Channel. Updating min and max gain indices are +* decoupled from the main gain table loading so that the user has flexibility +* to load multiple gain table regions and switch between them during runtime. +* +* The gain table configs can be broadcast / multicast based on the channel mask +* parameter in adi_adrv9025_RxGainTableCfg_t structure. +* +* rxChannelMask | Rx Channels Programmed +* ---------------------------------|-------------------------------------- +* bit[0] = 1 | Enables Rx1 gain table programming +* | +* bit[1] = 1 | Enables Rx2 gain table programming +* | +* bit[2] = 1 | Enables Rx3 gain table programming +* | +* bit[3] = 1 | Enables Rx4 gain table programming +* | +* bit[4] = 1 | Enables ORx1 gain table programming +* | +* bit[5] = 1 | Enables ORx2 gain table programming +* | +* bit[6] = 1 | Enables ORx3 gain table programming +* | +* bit[7] = 1 | Enables ORx4 gain table programming +* +* Eg: To program the same gain table to channels ORx1 and Rx1, the rxChannelMask +* should be set to 0x00000011 +* +* Eg: To program a single gain table to all channels, the rxChannelMask +* should be set to 0x0000003F +* +* Partial gain table loads can be done through this API in case of memory constraints / multiple region loading +* For example, consider a 256 row gain table which needs to be loaded in 4 consecutive calls. +* In this case the config parameters for partial loads would be +* Partial Load 1 : gainTableRow[] = gainTable[63:0], gainIndexOffset = 63, numGainIndicesInTable = 64 +* Partial Load 2 : gainTableRow[] = gainTable[127:64], gainIndexOffset = 127, numGainIndicesInTable = 64 +* Partial Load 3 : gainTableRow[] = gainTable[191:128], gainIndexOffset = 191, numGainIndicesInTable = 64 +* Partial Load 4 : gainTableRow[] = gainTable[255:192], gainIndexOffset = 255, numGainIndicesInTable = 64 +* +* Post this multiple partial gain table load, call the function adi_adrv9025_RxMinMaxGainIndexSet(minIndex = 0, maxIndex = 255). +* +* Please note that ORx1 and ORx2 are physically mapped to the same ORx channel and ORx3 and ORx4 are physically mapped +* to the same ORx channel. Selecting ORx1 / ORx2 writes the same ORx gain table SRAM and similarly selecting ORx3 or ORx4 +* writes to the same ORx gain table SRAM. +* +* \pre This function called automatically in adi_adrv9025_Initialize() to load +* the default gain table. If the BBIC desires to change or update the +* gain table, it may call this function after initialization but before +* running init cals. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannelMask is the set of channels for which current gain table settings are to be programmed. +* Valid Rx channels include Rx1-Rx4 and ORx1-ORx4 +* \param gainIndexOffset is the starting gain index from which gain table is programmed +* \param gainTableRow Array of gain table row entries for programming +* \param arraySize is the number of gain table rows to be programmed +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainTableWrite(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint8_t gainIndexOffset, + adi_adrv9025_RxGainTableRow_t gainTableRow[], + uint16_t arraySize); + +/** +* \brief Performs range check on the gain table settings for Rx / ORx channels. +* +* This function called automatically as part of adi_adrv9025_RxGainTableWrite() API +* if ADI_ADRV9025_RX_RANGE_CHECK is set to 1. This function can be called independently +* for standalone range checking of Rx Gain Table write functionality. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannelMask is the set of channels for which current gain table settings are to be programmed. +* Valid Rx channels include Rx1-Rx4 and ORx1-ORx4 +* \param gainIndexOffset is the starting gain index from which gain table is programmed +* \param gainTableRow Array of gain table row entries for programming +* \param arraySize is the number of gain table rows to be programmed +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainTableWriteRangeCheck(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint8_t gainIndexOffset, + adi_adrv9025_RxGainTableRow_t gainTableRow[], + uint16_t arraySize); + +/** +* \brief Reads the gain table entries for Rx / ORx channels requested. +* +* This function can be called by the user to read back the currently programmed gain table +* for a given channel. This function reads the current gain table settings from ADRV9025 gain table Static RAMs +* for the requested channel and stores it in the provided memory reference of type adi_adrv9025_RxGainTableCfg_t +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannel represents the channels for which gain table read back is requested. +* Valid Rx channels include Rx1-Rx4 and ORx1-ORx4 +* \param gainIndexOffset is the gain index from which gain table read back should start +* \param gainTableRow Read back array for gain table row entries which will be updated with the read back values +* \param arraySize is the size of gainTableRow array. It is also the upper limit for the no. of gain indices to read +* \param numGainIndicesRead is the actual no. of gain indices read from SRAM (output). A NULL can be passed +* if the value of no. of gain indices actually read is not required. +* +* \pre This function can be called by the user anytime after initialization. +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainTableRead(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint8_t gainIndexOffset, + adi_adrv9025_RxGainTableRow_t gainTableRow[], + uint16_t arraySize, + uint16_t* numGainIndicesRead); + +/** +* \brief Performs range check on adi_adrv9025_RxGainTableRead() function +* +* This function called automatically as part of adi_adrv9025_RxGainTableRead() API +* if ADI_ADRV9025_RX_RANGE_CHECK is set to 1. This function can be called independently +* for standalone range checking of Rx Gain Table read functionality. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannel represents the channels for which gain table read back is requested. +* Valid Rx channels include Rx1-Rx4 and ORx1-ORx4 +* \param gainIndexOffset is the gain index from which gain table read back should start +* \param gainTableRow Read back array for gain table row entries which will be updated with the read back values +* \param arraySize is the size of gainTableRow array. It is also the upper limit for the no. of gain indices to read +* \param numGainIndicesRead is the actual no. of gain indices read from SRAM (output). A NULL can be passed +* if the value of no. of gain indices actually read is not required. +* +* \pre This function can be called by the user anytime after initialization. +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainTableReadRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint8_t gainIndexOffset, + adi_adrv9025_RxGainTableRow_t gainTableRow[], + uint16_t arraySize, + uint16_t* numGainIndicesRead); + +/** +* \brief Updates the minimum and maximum gain indices for a requested Rx/ORx Channel +* in the device data structure +* +* This function is required to be called by the user right after loading the gain table. +* This function is decoupled from the gain table loading function so that a user has +* flexibility to load multiple gain table regions and switch between multiple gain table +* regions during runtime +* +* The gain table configs can be broadcast / multicast based on the channel mask +* parameter in adi_adrv9025_RxGainTableCfg_t structure. +* +* rxChannelMask | Rx Channel min & max gain indices updated +* ---------------------------------|-------------------------------------------- +* bit[0] = 1 | Updates Rx1 min & max gain indices +* ---------------------------------|-------------------------------------------- +* bit[1] = 1 | Updates Rx2 min & max gain indices +* ---------------------------------|-------------------------------------------- +* bit[2] = 1 | Updates Rx3 min & max gain indices +* ---------------------------------|-------------------------------------------- +* bit[3] = 1 | Updates Rx4 min & max gain indices +* ---------------------------------|-------------------------------------------- +* bit[4] = 1 | Updates ORx1 min & max gain indices +* ---------------------------------|-------------------------------------------- +* bit[5] = 1 | Updates ORx2 min & max gain indices +* ---------------------------------|-------------------------------------------- +* bit[6] = 1 | Updates ORx3 min & max gain indices +* ---------------------------------|-------------------------------------------- +* bit[7] = 1 | Updates ORx4 min & max gain indices +* +* Eg: To update min and max gain indices of channels ORx1 and Rx1, the rxChannelMask +* should be set to 0x00000011 +* +* Eg: To update min and max gain indices of all channels(Rx + ORx), the rxChannelMask +* should be set to 0x0000003F +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannelMask channel masks for which min and max gain indices are to be updated +* \param minGainIndex is the lower limit of the gain index for a given channel +* \param maxGainIndex is the upper limit of the gain index for a given channel +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxMinMaxGainIndexSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint8_t minGainIndex, + uint8_t maxGainIndex); + +/** +* \brief Performs range check on the Rx channel min and max gain indices to be updated +* +* This function is called automatically as part of adi_adrv9025_RxMinMaxGainIndexSet() +* if the ADI_ADRV9025_RX_RANGE_CHECK is set to 1. This function can be called independently +* to perform range checks only on parameters for adi_adrv9025_RxMinMaxGainIndexSet() API +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep{device->devStateInfo} +* \dep_end +* +* \param device Structure pointer to the ADRV9025 device data structure +* \param rxChannelMask channel masks for which min and max gain indices are to be updated +* \param minGainIndex is the lower limit of the gain index for a given channel +* \param maxGainIndex is the upper limit of the gain index for a given channel +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxMinMaxGainIndexSetRangeCheck(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint8_t minGainIndex, + uint8_t maxGainIndex); + +/** + * \brief Programs the Dualband external LNA control gain table settings for + * either Rx1, Rx2, Rx1 + Rx2 receiver types + * \brief Not currently implemented + * + * The gain table for a receiver type is set with the parameters passed by + * adi_adrv9025_DualBandLnaGtRow_t gainTablePtr array. The array length (n) is + * conveyed by numGainIndicesInTable. The table can have a maximum of 4 + * entries. The first entry in the array corresponds to entry 0, second to + * entry 1, and so on. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep{device->devStateInfo} + * \dep_end + * + * \param device Structure pointer to the ADRV9025 device data structure + * \param gainTableCfg[] Pointer to Dual Band LNA gain table array of adi_adrv9025_DualBandLnaGtRow_t structures + * \param arraySize is the size of gainTableCfg array. + * + * \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required + * \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required + */ +int32_t adi_adrv9025_RxGainTableDualBandLnaWrite(adi_adrv9025_Device_t* device, + adi_adrv9025_DualBandRxGainTableCfg_t gainTableCfg[], + uint8_t arraySize); + +/* TODO: Needs doxygen header */ +/*\brief Not currently implemented */ + +int32_t adi_adrv9025_RxGainTableDualBandLnaRead(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_DualBandRxGainTableCfg_t* gainTableCfg); + +/** +* \brief Configures one or more RX FIR filters in the device +* +* The device stores 1 RX FIR filter per channel. +* The device stores an independent filter for each ORx front end (ORx1, ORx2, ORx3, ORx4). +* Internal Loopback 1 and 2 share a FIR filter, and Internal loopback 3 and 4 share a FIR filter. +* Rx and ORx channel can have 24, 48, 72 taps. +* +* The function is not called directly. It is called as a part of the adi_adrv9025_initialize() function. +* The function could be used to change A FIR filter later, but would require calibrations to be rerun. +* +* \pre This function is called during device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* \param device Pointer to the ADRV9025 data structure +* \param rxChanMask One or more RX channel from adi_adrv9025_RxChannels_e. +* \param gain_dB The gain_dB value (-12, -6, 0, 6) +* \param numFirCoefs The number of Fir Coefs in coefs array (24, 48, 72) +* \param coefs[] Pointer to coefs array +* \param arraySize The size of coefs array +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* \ +*/ +int32_t adi_adrv9025_RxFirWrite(adi_adrv9025_Device_t* device, + uint32_t rxChanMask, + int8_t gain_dB, + uint8_t numFirCoefs, + int16_t coefs[], + uint8_t arraySize); + +/** +* \brief Get one RX FIR filters in the device +* +* The device stores up to 1 RX FIR filter banks. +* The device stores up to 3 FIR Filter banks A,B,or C for ORX and LOOPBACK +* Rx and ORx channel can have 24, 48, 72 taps. +* +* The function is not called directly. It is called as a part of the adi_adrv9025_initialize() function. +* The function could be used to change A FIR filter later, but would require calibrations to be rerun. +* +* \pre This function is called during device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* \param device Pointer to the ADRV9025 data structure +* \param rxChannel adi_adrv9025_RxChannels_e enum type to select. +* \param gain_dB Pointer to the gain_dB value read from device (output) +* \param numFirCoefs Pointer to the numFirCoefs value read from device (output) +* \param coefs[] Pointer to coefs array read from the device (output) +* \param arraySize The size of coefs array +* +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* \ +*/ +int32_t adi_adrv9025_RxFirRead(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + int8_t* gain_dB, + uint8_t* numFirCoefs, + int16_t coefs[], + uint8_t arraySize); + +/**************************************************************************** + * Runtime functions + **************************************************************************** + */ + +/** +* \brief Sets the Rx1 or Rx2 Manual Gain Index +* +* If the value passed in the gainIndex parameter is within range of the gain +* table minimum and maximum indices, the Rx channel gain index will be written +* to the transceiver. Else, an error will be returned. The maximum index is 255 +* and the minimum index is application specific. +* +* The default gain table can take values between 0xB7 and 0xFF, +* even though every index is accessible from 0x00 to 0xFF. +* +* \pre This function may be called any time after device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxGain is the channelized gain setting parameter +* \param arraySize Size of rxGain array representing no. of configs. +* +* The gain table configs can be broadcast / multicast based on the channel mask +* parameter in adi_adrv9025_RxGainTableCfg_t structure. +* +* rxGain[i]->rxChannelMask | Rx Channels to set manual gain +* ---------------------------------|-------------------------------------- +* bit[0] | 1 = Rx1 manual gain is updated +* | +* bit[1] | 1 = Rx2 manual gain is updated +* | +* bit[2] | 1 = Rx3 manual gain is updated +* | +* bit[3] | 1 = Rx4 manual gain is updated +* | +* bit[4] | 1 = ORx1 manual gain is updated +* | +* bit[5] | 1 = ORx2 manual gain is updated +* | +* bit[6] | 1 = ORx3 manual gain is updated +* | +* bit[7] | 1 = ORx4 manual gain is updated +* +* Eg: To update manual gain for channels Rx4 and Rx1, the rxGain[i]->rxChannelMask +* should be set to 0x00000009 +* +* Eg: To update manual gain for all Rx channels, the rxGain[i]->rxChannelMask +* should be set to 0x0000000F +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxGain_t rxGain[], + uint8_t arraySize); + +/** +* \brief Performs range check on rx gain index setting. +* +* \pre This function is called automatically as part of adi_adrv9025_RxGainSet() +* function if ADI_ADRV9025_RX_RANGE_CHECK > 0. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxGain is the channelized gain setting parameter +* \param arraySize Size of rxGain array representing no. of configs. +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxGain_t rxGain[], + uint8_t arraySize); + +/** +* \brief Reads the Rx MGC Gain Index for the requested Rx channel +* +* This function reads the gain index for the passed channel Rx1-Rx4, ORx1-ORx4 +* +* This function reads back the Manual gain index per channel, depending on the gain control mode. +* +* \pre This function may be called any time after device initialization. +* However, gain indices are tracked only after the device goes into a +* Receiver mode. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param rxChannel Channel selection to read back gain index for (Valid Rx1-Rx4, ORx1-ORx4 only) +* \param rxGain Pointer to the specified channel gain index value +* which will be updated by this function +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxMgcGainGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxGain_t* rxGain); + +/** +* \brief Reads the Rx AGC Gain Index for the requested Rx channel +* +* This function reads the gain index for the passed channel Rx1-Rx4, ORx1-ORx4 +* +* This function reads back the AGC gain index per channel, depending on the gain control mode. +* +* @note: That this function taps into the agc_gain_index register which operates in two modes +* depending on if agc_enable_gain_index_update is set to 0 or 1 +* if agc_enable_gain_index_update == 0: This register will latch to new gain index values +* automatically. +* if agc_enable_gain_index_update == 1: This register will require a dummy write in +* order to latch to the correct gain index. Furthermore in this mode, the +* corresponding Rx/ORx channels MUST be enabled for the register to latch to the +* correct gain index. +* +* \pre This function may be called any time after device initialization. +* However, gain indices are tracked only after the device goes into a +* Receiver mode. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param rxChannel Channel selection to read back gain index for (Valid Rx1-Rx4, ORx1-ORx4 only) +* \param rxGain Pointer to the specified channel gain index value +* which will be updated by this function +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxGain_t* rxGain); + +/** +* \brief Performs range check on AGC/MGC gain get API. +* +* \pre This function is called automatically as part of AGC/MGC gain get API. +* function if ADI_ADRV9025_RX_RANGE_CHECK > 0. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param rxChannel Channel selection to read back gain index for (Valid Rx1-Rx4, ORx1-ORx4 only) +* \param rxGain Pointer to the specified channel gain index value +* which will be updated by this function +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainGetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxGain_t* rxGain); + +/** +* \brief Configures the Rx gain control mode +* +* \brief The Gain Ctrl Mode for Rx signal can be set to Manual Gain Ctrl, Fast attack AGC, +* Slow Loop AGC, Hybrid mode for channels Rx1-Rx4, ORx1-ORx4. +* +* The ADRV9025 device defaults to Manual Gain Control (MGC) mode on power-up. +* This API is used to reconfigure the Rx Gain Control Mode. +* +* \pre This function should be called before Rx operation is initiated. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param gainMode Desired gain mode to be configured. Parameter is of enumerated type adi_adrv9025_RxAgcMode_e +* \param arraySize is the no. of elements in gainMode[] array +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainCtrlModeSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxAgcMode_t gainMode[], + uint8_t arraySize); + +/** +* \brief Retrieves the currently configured Rx gain control mode +* +* \brief The Gain Ctrl Mode for Rx signal can be set to Manual Gain Ctrl, Fast attack AGC, +* Slow Loop AGC, Hybrid mode for channels Rx1-Rx4, ORx1-ORx4. This API is used to +* read back the current Rx gain ctrl mode setting. +* +* \pre +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxChannel is the receiver for which gain ctrl mode read back is requested +* \param gainMode is the pointer to adi_adrv9025_RxAgcMode_t structure which will +* be updated with the read back config +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainCtrlModeGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxAgcMode_t* gainMode); + +/** +* \brief Range Check for adi_adrv9025_RxDataFormatSet function. +* +* The ADRV9025 data formatting should be used in conjunction with the +* gain compensation feature. This function is automatically called as +* part of adi_adrv9025_RxDataFormatSet() if ADI_ADRV9025_RX_RANGE_CHECK +* is set to 1 +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param rxDataFormat Pointer to the Rx data format configuration structure +* \param arraySize Size of rxDataFormat array representing no. of configs +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxDataFormatSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxDataFormat_t rxDataFormat[], + uint8_t arraySize); + +/** +* \brief Sets the Rx Data format to integer or floating point format. +* +* The slicer/formatter work in conjunction with the gain compensation module. +* The digital gain compensation module compensates for the front end attenuation +* thereby increasing the bit resolution of the Rx data word. The slicer is then +* applied to attenuate the data such that it can fit into the JESD data path resolution. +* +* The function allows selecting the Rx data format (integer or floating point) +* and allows configuring the various data formatting options.The ADRV9025 defaults +* to integer format. +* +* The floating point format can be set for one of several 16 bit floating +* point formats. The user can select the number of exponent and significand +* bits. It is not possible to represent every possible sample value with +* 16bit floating point format. When using integer formatting, the number of slicer +* bits as well as their position in the data word are selectable. The GPIO bits are +* also user selectable for external slicer control mode. +* +* The user can select the data format mode from one of the following +* +* rxDataFormat[i]->formatSelect | Description +* ---------------------------------------------|-------------------------------------- +* ADI_ADRV9025_GAIN_COMPENSATION_DISABLED | Disables gain compensation and Rx data formatting +* | +* ADI_ADRV9025_GAIN_WITH_FLOATING_POINT | Setup formatting for one of the following +* | floating point modes. 5/3/2 exp bits, 10/12/13 +* | significand bits and 1 sign bit. +* | +* ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO | Setup Rx data format to an integer format such +* | that the gain compensation data(slicer) is embedded +* | in the I and Q data. It is possible to embed 2/3/4 +* | slicer bits providing a dynamic gain compensation range +* | of 50dB. Applicable for 16-bit / 12-bit resolution +* | +* ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER | Setup Rx data format to an integer format such +* | that the gain compensation data(slicer) is encoded +* | in the GPIO output from ADRV9025. It is possible to encode 2/3/4 +* | slicer bits providing a dynamic gain compensation range +* | of 50dB. Applicable for 16-bit / 12-bit resolution +* | +* ADI_ADRV9025_GAIN_WITH_EXTERNAL_SLICER | Setup Rx data format to an integer format such +* | that the gain compensation data(slicer) is input +* | to ADRV9025 via GPIO pins. It is possible to encode 3 +* | slicer bits for 16 bit resolution and 2 slicer bits for +* | 12 bit resolution. +* | +* ADI_ADRV9025_EMBED_OVERLOAD_MONITOR_DATA | Setup overload indicators to be embedded in the 16 bit +* | 2s complement data. The overload indicators can be embedded +* | at LSB and/or LSB+1 positions of I and Q samples. +* +* The ADRV9025 data formatting should be used in conjunction with the +* gain compensation feature. +* +* Please note that for ORx channels ADI_ADRV9025_GAIN_WITH_FLOATING_POINT and ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO +* are the only valid modes +* +* Please note that while disabling gain compensation a valid data format represented by +* rxDataFormat[i].integerConfigSettings.intSampleResolution has to be set to a valid mode. Please refer to enum +* adi_adrv9025_RxIntSampleResolution_e for valid intSampleResolution modes +* +* It has to be ensured that the ADRV9025 JESD Framer Np for the selected Rx channel is at least equal to +* integer sample resolution size. +* +* In a 2 bit embedded slicer mode (ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO), slicer position bit 0 +* is embedded in Q data from JESD and slicer position bit 1 is embedded in I data from JESD. +* +* In a 4 bit embedded slicer mode (ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO), slicer position bit 0 +* and bit1 are embedded in Q data from JESD and slicer position bit 2 and bit 3 are embedded in I data from JESD. +* +* The slicer position can also be read back via adi_adrv9025_RxSlicerPositionGet() API +* +* The slicer position in the internal slicer mode (ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER) can be observed on +* the following GPIO lines which are configured as outputs from ADRV9025 +* +* rxChannel | ADRV9025 GPIOs set to internal slicer ctrl +* ---------------------|------------------------------------------------------------------------- +* ADI_ADRV9025_RX1 | ADRV9025_GPIO_06, ADRV9025_GPIO_07, ADRV9025_GPIO_08 (MSB) +* ADI_ADRV9025_RX2 | ADRV9025_GPIO_09, ADRV9025_GPIO_10, ADRV9025_GPIO_11 (MSB) +* ADI_ADRV9025_RX3 | ADRV9025_GPIO_12, ADRV9025_GPIO_13, ADRV9025_GPIO_14 (MSB) +* ADI_ADRV9025_RX4 | ADRV9025_GPIO_15, ADRV9025_GPIO_16, ADRV9025_GPIO_17 (MSB) +* +* Please note that only the least significant 3 bits of the slicer control word is output on the GPIOs. +* +* User needs to enable fast recovery and configure AGC block with adi_adrv9025_AgcCfgSet API before using +* HB2 int0/int1 threshold and counter exceeded embedded overload flags + +* \pre Slicer/Formatter operation requires that the device be loaded with a gain table that compensates +* for the analog front end attenuation applied. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param rxDataFormat Pointer to the Rx data format configuration structure +* \param arraySize Size of rxDataFormat array representing no. of configs +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxDataFormatSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxDataFormat_t rxDataFormat[], + uint8_t arraySize); + +/** +* \brief Retrieve the Rx data path format configuration. +* \brief Not currently implemented +* +* Use this command to retrieve the Rx data path data formatting configuration +* set by the adi_adrv9025__RxDataFormatSet function. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param rxChannel adi_adrv9025_RxChannels_e enum type to select channel for reading configuration from. +* \param rxDataFormat Pointer to the Rx data format configuration structure +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxDataFormatGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxDataFormat_t* rxDataFormat); + +/** +* \brief Get the gain slicer position bits for both Rx1 and Rx2. +* +* Before this information is valid, the Rx gain compensation feature should be enabled with +* the integer gain slicer sample format enabled. See the adi_adrv9025_RxDataFormatSet() function +* to enable gain compensation. This function is not useful in the case of using floating point +* as the gain slicer (data scaling) is applied in the floating point scaled sample. This function +* is also not valid if the selected data format is external slicer mode +* +* The slicer position is only needed for integer 12bit and 16bit formats. The 24bit sample format +* already applies scaling in the 24bit sample. The data can be scaled in steps of 1dB, 2dB, 4dB, +* 6dB, 8dB configured through the adi_adrv9025_RxDataFormatSet() function. +* +* Slicer Position[2:0] | Description +* ---------------------|--------------------------------------------- +* 0 | 0dB gain +* 1 | Rx Data samples should be scaled by 1 x step size(dB) +* 2 | Rx Data samples should be scaled by 2 x step size(dB) +* 3 | Rx Data samples should be scaled by 3 x step size(dB) +* 4 | Rx Data samples should be scaled by 4 x step size(dB) +* 5 | Rx Data samples should be scaled by 5 x step size(dB) +* 6 | Rx Data samples should be scaled by 6 x step size(dB) +* 7 | Rx Data samples should be scaled by 7 x step size(dB) +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param rxChannel adi_adrv9025_RxChannels_e enum type to select channel from. +* \param slicerPosition Pointer to byte which returns the slicer position bits for the requested channel. +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxSlicerPositionGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint8_t* slicerPosition); + +/** +* \brief Configures Gain steps and the GPIO inputs for Manual Rx gain control +* +* This API function configures the GPIO input pin and step size to allow the +* BBP to control gain changes in Rx signal chain. +* A high pulse on the 'rxGainIncPin' in pin control mode will increment the +* rx gain index by the value set in 'rxGainPinCtrlCfg.incStep' + 1. +* A high pulse on the 'rxGainDecPin' in pin control mode will decrement the +* rx gain index by the value set in 'rxGainPinCtrlCfg.decStep' + 1. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param rxChannel enum to select channel Rx channel for gpio gain ctrl config +* \param rxGainPinCtrlCfg Pointer to adi_adrv9025_RxGainPinCfg_t structure +* containing configuration values for Manual Rx gain pin control +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainPinCtrlCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxGainPinCfg_t* rxGainPinCtrlCfg); + +/** +* \brief Performs a range check on the GPIO mode gain control config +* +* This API function checks that the GPIO pins are in the range GPIO[15:0] +* This API also verifies that increment and decrement steps are in the range 0-7 +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param rxChannel enum to select channel Rx channel for gpio gain ctrl config +* \param rxGainPinCtrlCfg Pointer to adi_adrv9025_RxGainPinCfg_t structure +* containing configuration values for Manual Rx gain pin control +* on which range check will be performed +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainPinCtrlCfgSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxGainPinCfg_t* rxGainPinCtrlCfg); + +/** +* \brief This API function returns the configuration (Gain steps and the GPIO +* inputs) for Manual Rx gain control. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param rxChannel enum type to select Rx channel for reading configuration from. +* \param rxGainPinCtrlCfg Pointer to adi_adrv9025_RxGainPinCfg_t structure that +* would contain configuration values for Manual Rx gain pin control read back (Output). +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainPinCtrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxGainPinCfg_t* rxGainPinCtrlCfg); + +/** +* \brief This API function configures Analog GPIOs to output gain table external ctrl words +* on analog GPIOs +* +* extCtrlGpioChannelEn | Ext Ctrl Word Output GPIOs +* -------------------------------------------------|-------------------------------------------- +* ADI_ADRV9025_ENABLE_RX1_RX2_RX3_RX4_EXT_CTRL_GPIOS | GPIO_ANA[1:0] -> Rx1 Ext Ctrl Word Output +* | GPIO_ANA[3:2] -> Rx2 Ext Ctrl Word Output +* | GPIO_ANA[5:4] -> Rx3 Ext Ctrl Word Output +* | GPIO_ANA[7:6] -> Rx4 Ext Ctrl Word Output +* | +* ADI_ADRV9025_DISABLE_RX1_RX2_RX3_RX4_EXT_CTRL_GPIOS | GPIO_ANA[7:0] -> Default(Input) +* | +* ADI_ADRV9025_ENABLE_RX1_RX2_EXT_CTRL_GPIOS | GPIO_ANA[1:0] -> Rx1 Ext Ctrl Word Output +* | GPIO_ANA[3:2] -> Rx2 Ext Ctrl Word Output +* | +* ADI_ADRV9025_DISABLE_RX1_RX2_EXT_CTRL_GPIOS | GPIO_ANA[3:0] -> Default(Input) +* | +* ADI_ADRV9025_ENABLE_RX3_RX4_EXT_CTRL_GPIOS | GPIO_ANA[5:4] -> Rx3 Ext Ctrl Word Output +* | GPIO_ANA[7:6] -> Rx4 Ext Ctrl Word Output +* | +* ADI_ADRV9025_DISABLE_RX3_RX4_EXT_CTRL_GPIOS | GPIO_ANA[7:4] -> Default(Input) +* +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* +* \param extCtrlGpioChannelEn adi_adrv9025_RxChannels_e enum type to select which set of gain table +* external ctrl words to output on analog GPIOs as per the table shown above +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainTableExtCtrlPinsSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxExtCtrlPinOuputEnable_e extCtrlGpioChannelEn); + +/** +* \brief Range check for adi_adrv9025_RxGainTableExtCtrlPinsSet() function +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* +* \param extCtrlGpioChannelEnable adi_adrv9025_RxChannels_e enum type to select which set of gain table +* external ctrl words to output on analog GPIOs +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainTableExtCtrlPinsSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxExtCtrlPinOuputEnable_e extCtrlGpioChannelEnable); + +/** +* \brief This function gets the Dec Power for the specified channel. +* +* This function can be used to get the Dec Power of RX channel in runtime. +* +* Due to interdependencies between the AGC and power measurement the power measurement duration and +* where the measurement is taken is variable. +* The location of the power measurement is given by agcCfg->agcPower->powerInputSelect +* The number of samples the power measurement uses is given by 8*2^(agcCfg->agcPower->powerMeasurementDuration) at the IQ rate, +* if measured at RFIR output. This number of samples must be less than the agcCfg->agcGainUpdateCounter. +* If the receiver is disabled during the power measurement, this function returns a 0 value for rxDecPower_mdBFS +* +* The resolution of this function is 0.25dB. +* The dynamic range of this function is 60dB. Signals lower than 60dBFS may not be measured accurately. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxChannel adi_adrv9025_RxChannels_e enum type to select Rx Channel. +* \param rxDecPower_mdBFS Pointer to store the ADRV9025 Dec Power return. Value returned in mdBFS. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_ERR_RESET_FEATURE Recovery action for user GPIO reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxDecPowerGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint16_t* rxDecPower_mdBFS); + +/** +* \brief This function reads back the LO Source Mapping to the requested Rx channel. +* +* The LO source select for a given channel is configured during init time. This function +* can be used to read back the configuration during run time. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxChannel Enum to select Rx Channel. +* \param rxLoSource Pointer to store Rx channel LO source mapping read back (Output) +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_ERR_RESET_FEATURE Recovery action for user GPIO reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxLoSourceGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_LoSel_e* rxLoSource); + +/** +* \brief This function sets the temperature gain compensation parameter. +* +* This function can be called at any point. The gain can be configured +* from -6.3 dB to 6.3 dB in 0.1 dB increments. Hence allowable range is +* [-63 to +63] with 0 representing 0 dB. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxChannelMask Bit mask representing channels to be programmed (can be multiple channels). +* \param gainValue Gain value to set +* +* The following table lists the rxChannelMask bits and the corresponding channels +* that are enabled/disabled in SPI mode +* +* rxChannelMask | Channel Enable/Disable +* -----------------|------------------------------------ +* bit[0] | 1 = Rx1 Enable, 0 = Rx1 Disable +* bit[1] | 1 = Rx2 Enable, 0 = Rx2 Disable +* bit[2] | 1 = Rx3 Enable, 0 = Rx3 Disable +* bit[3] | 1 = Rx4 Enable, 0 = Rx4 Disable +* bit[4] | 1 = ORx1 Enable, 0 = ORx1 Disable +* bit[5] | 1 = ORx2 Enable, 0 = ORx2 Disable +* bit[6] | 1 = ORx3 Enable, 0 = ORx3 Disable +* bit[7] | 1 = ORx4 Enable, 0 = ORx4 Disable +* bit[8] | Reserved, do not use. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxTempGainCompSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + int8_t gainValue); + +/** +* \brief This function gets the temperature gain compensation parameter. Only one channel +* can be retrieved per call. +* +* This function can be called at any point. The gain returned is in the +* range -63 to 63 +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxChannel Bit mask representing which channel to retrieve (only one channel returned per call) +* \param gainValue Gain value retrieved (Output) +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxTempGainCompGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + int8_t* gainValue); + +/** +* \brief This API function configures Analog GPIOs to output Rx dualband external LNA ctrl signal +* when all 4 RX channels are enabled. +* +* This function configures the dualband A and B controls for all 4 Rx channels, therefore all 8 +* analog GPIO pins are consumed by this feature. The analog GPIO pin outputs from ADRV9025 are +* assigned as follows :- +* +* GPIO | Control Signal +* ----------------|---------------------- +* Analog GPIO[0] | Rx1 Dual band ctrl A +* Analog GPIO[1] | Rx1 Dual band ctrl B +* Analog GPIO[2] | Rx2 Dual band ctrl A +* Analog GPIO[3] | Rx2 Dual band ctrl B +* Analog GPIO[4] | Rx3 Dual band ctrl A +* Analog GPIO[5] | Rx3 Dual band ctrl B +* Analog GPIO[6] | Rx4 Dual band ctrl A +* Analog GPIO[7] | Rx4 Dual band ctrl B +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param enable Param to enable(1) or disable(0) Rx dualband LNA ctrl via Analog GPIOs. +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_GpioForAnalogDualBandOperationSet(adi_adrv9025_Device_t* device, + uint8_t enable); + +/** +* \brief This API function configures Rx NCO mixers in the Rx data path. +* This API can only be used at runtime after device initialization. +* +* Available configuration parameters are: +* bandAInputBandWidth_kHz is the bandwidth in kHz of the BandA input signal +* bandAInputCenterFreq_kHz is the center frequency in kHz of the BandA input signal +* bandANco1Freq_kHz is the BandA NCO1 Frequency shift in kHz +* bandANco2Freq_kHz is the BandA NCO2 Frequency shift in kHz +* bandBInputBandWidth_kHz is the bandwidth in kHz of the BandB input signal +* bandBInputCenterFreq_kHz is the center frequency in kHz of the BandB input signal +* bandBNco1Freq_kHz is the BandB NCO1 Frequency shift in kHz +* bandBNco2Freq_kHz is the BandB NCO2 Frequency shift in kHz +* bandAbCombinedEnable is the BandA and BandB Combined at output, 1 = Combine dualband AB, 0 disable combine dualband on AB +* +* Enable parameters: +* If ADI_ADRV9025_RX_GAIN_PHASE init cal is run ADI_ADRV9025_BAND_A_NCO_1 needs to be enabled all the time +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param rxChannelMask Channels to apply the supplied configuration +* \param rxShiftConfig Rx NCO configuration +* \param rxDdcMode DDC Half Band Filter configuration +* \param enableMask This is a mask composed of type adi_adrv9025_RxNcoEnable_e +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxNcoShifterSet(adi_adrv9025_Device_t *device, + adi_adrv9025_RxChannels_e rxChannelMask, + adi_adrv9025_RxNcoShifterCfg_t rxShiftConfig, + adi_adrv9025_RxDdc_e rxDdcMode, + uint32_t enableMask); + +/** +* \brief This API function retrieves the selected channel's Rx NCO mixer status. +* This API can only be used at runtime after device initialization. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param rxChannel Channel from which to get the configuration +* \param ncoBandSelect Signal Band A or B from which to get the configuration +* \param rxShiftConfigGet pointer to the configuration structure in which retrieved configuration is returned +* \param rxDdcMode DDC read back value +* \param enableMask pointer to read back NCO +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxNcoShifterGet(adi_adrv9025_Device_t *device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxNcoBandSelect_e ncoBandSelect, + adi_adrv9025_RxNcoShifterCfg_t *rxShiftConfigGet, + adi_adrv9025_RxDdc_e *rxDdcMode, + uint32_t *enableMask); + +/** +* \brief These bits configure the gain control mode that is used on RX channels. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param rxChannelMask Rx Channel(s) to be configured, Valid range (1-15) +* \param agcMode Data to be configured. Parameter is of type adi_adrv9025_RxAgcMode_e. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +* +*/ +int32_t adi_adrv9025_RxAgcClkModeSet(adi_adrv9025_Device_t *device, + uint32_t rxChannelMask, + adi_adrv9025_RxAgcMode_e agcMode); + +/** +* \brief This API function retrieves the selected channel's Rx AGC clock mode status. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param rxChannel Base Address of instance to be configured. +* \param agcMode value retrieved (output). Parameter is of type uint8_t. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +* +*/ +int32_t adi_adrv9025_RxAgcClkModeGet(adi_adrv9025_Device_t *device, + adi_adrv9025_RxChannels_e rxChannel, + uint8_t *agcMode); + + + + +/** +* \brief This function maps Rx channels to a GPIO to enable +* the gain counter sync pulse feature, as such the Gain Update Counter +* gets synchronized with the rising edge of the pulse. This function should +* be used if agcEnableSyncPulseForGainCounter is set. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param rxChannel Rx channel selection +* \param hybridSelPin1 Gpio to be mapped +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxAgcSyncGpioPinSet(adi_adrv9025_Device_t *device, + uint8_t rxChannel, + adi_adrv9025_GpioPinSel_e hybridSelPin1); + + + +/**************************************************************************** + * Helper functions + **************************************************************************** + */ + +/**************************************************************************** + * Debug functions + **************************************************************************** + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_RX_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_rx_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_rx_types.h new file mode 100644 index 0000000..3c8d487 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_rx_types.h @@ -0,0 +1,532 @@ +/** + * \file adi_adrv9025_rx_types.h + * \brief Contains ADRV9025 API Rx datapath data types + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_RX_TYPES_H_ +#define _ADI_ADRV9025_RX_TYPES_H_ + +#include "adi_adrv9025_radioctrl_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * \brief Enum of possible Rx gain table SRAM base addresses + */ +typedef enum adrv9025_RxChanGainTableBaseAddr_e +{ + ADI_ADRV9025_ALL_RX_CHANNELS_GAIN_TABLE_BASEADDR = 0xD0800000, /*!< Select gain table SRAM base address for all Rx Channels */ + ADI_ADRV9025_ALL_ORX_CHANNELS_GAIN_TABLE_BASEADDR = 0xE0800000, /*!< Select gain table SRAM base address for all ORx Channels */ + ADI_ADRV9025_RX1_GAIN_TABLE_BASEADDR = 0x80800000, /*!< Select gain table SRAM base address for Rx1 Channel */ + ADI_ADRV9025_RX2_GAIN_TABLE_BASEADDR = 0x88800000, /*!< Select gain table SRAM base address for Rx2 Channel */ + ADI_ADRV9025_RX3_GAIN_TABLE_BASEADDR = 0x90800000, /*!< Select gain table SRAM base address for Rx3 Channel */ + ADI_ADRV9025_RX4_GAIN_TABLE_BASEADDR = 0x98800000, /*!< Select gain table SRAM base address for Rx4 Channel */ + ADI_ADRV9025_ORX1_ORX2_GAIN_TABLE_BASEADDR = 0xC0800000, /*!< Select gain table SRAM base address for ORx1 Channel */ + ADI_ADRV9025_ORX3_ORX4_GAIN_TABLE_BASEADDR = 0xC8800000 /*!< Select gain table SRAM base address for ORx2 Channel */ +} adrv9025_RxChanGainTableBaseAddr_e; + +/** + * \brief Enum of possible Rx channel enables + */ +typedef enum adi_adrv9025_RxChannels +{ + ADI_ADRV9025_RXOFF = 0x00, /*!< No Rx/ORx channels are enabled */ + ADI_ADRV9025_RX1 = 0x01, /*!< Rx1 channel enabled */ + ADI_ADRV9025_RX2 = 0x02, /*!< Rx2 channel enabled */ + ADI_ADRV9025_RX3 = 0x04, /*!< Rx3 channel enabled */ + ADI_ADRV9025_RX4 = 0x08, /*!< Rx4 channel enabled */ + ADI_ADRV9025_ORX1 = 0x10, /*!< ORx1 channel enabled */ + ADI_ADRV9025_ORX2 = 0x20, /*!< ORx2 channel enabled */ + ADI_ADRV9025_ORX3 = 0x40, /*!< ORx3 channel enabled */ + ADI_ADRV9025_ORX4 = 0x80, /*!< ORx4 channel enabled */ + ADI_ADRV9025_LB12 = 0x100, /*!< Tx1 or Tx2 internal loopback into ORx1/2 channel enabled, NOT Used for RxDDC Mode settings */ + ADI_ADRV9025_LB34 = 0x200 /*!< Tx3 or Tx4 internal loopback into ORx3/4 channel enabled, NOT Used for RxDDC Mode settings */ +} adi_adrv9025_RxChannels_e; + +/** + * \brief Enum to set the Rx Gain control mode + */ +typedef enum +{ + ADI_ADRV9025_MGC = 0, /*!< Manual Gain Control */ + ADI_ADRV9025_AGCFAST = 1, /*!< Fast Attack AGC Mode */ + ADI_ADRV9025_AGCSLOW = 2, /*!< Slow Loop AGC */ + ADI_ADRV9025_HYBRID = 3 /*!< Hybrid AGC Gain Control */ +} adi_adrv9025_RxAgcMode_e; + +/** + * \brief Enum to hold ADRV9025 Floating Point Formatter format which indicates order of sign significand and exponent + */ +typedef enum adi_adrv9025_FpFloatDataFormat +{ + ADI_ADRV9025_FP_FORMAT_SIGN_EXP_SIGNIFICAND = 0, /*!< Floating point format of type {Sign, Significand, Exponent} */ + ADI_ADRV9025_FP_FORMAT_SIGN_SIGNIFICAND_EXP = 1 /*!< Floating point format of type {Sign, Exponent, Significand} */ +} adi_adrv9025_FpFloatDataFormat_e; + +/** + * \brief Enum to hold ADRV9025 Floating Point Formatter NaN encode enable + */ +typedef enum adi_adrv9025_FpNanEncode +{ + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_DISABLE = 0, /*!< Does not reserve highest value of exponent for NaN */ + ADI_ADRV9025_FP_FORMAT_NAN_ENCODE_ENABLE = 1 /*!< Eeserve highest value of exponent for NaN */ +} adi_adrv9025_FpNanEncode_e; + +/** + * \brief Enum to hold ADRV9025 Hide Leading One selection + */ +typedef enum adi_adrv9025_FpHideLeadingOne +{ + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_DISABLE = 0, /*!< Sets leading one to be at the MSB of the significand */ + ADI_ADRV9025_FP_FORMAT_HIDE_LEADING_ONE_ENABLE = 1 /*!< Hides the leading one in significand to be compatible to the IEEE754 specification */ +} adi_adrv9025_FpHideLeadingOne_e; + +/** + * \brief Enum to hold ADRV9025 Floating Point Formatter number of exponent bits + */ +typedef enum adi_adrv9025_FpExponentModes +{ + ADI_ADRV9025_2_EXPONENTBITS = 0, /*!< Floating point values have 2 exponent bits, 13 significand bits, 1 sign bit */ + ADI_ADRV9025_3_EXPONENTBITS = 1, /*!< Floating point values have 3 exponent bits, 12 significand bits, 1 sign bit */ + ADI_ADRV9025_4_EXPONENTBITS = 2, /*!< Floating point values have 4 exponent bits, 11 significand bits, 1 sign bit */ + ADI_ADRV9025_5_EXPONENTBITS = 3 /*!< Floating point values have 5 exponent bits, 10 significand bits, 1 sign bit */ +} adi_adrv9025_FpExponentModes_e; + +/** + * \brief Enum to hold ADRV9025 Floating Point Formatter rounding modes for the Rx data path + */ +typedef enum adi_adrv9025_FpRoundModes +{ + ADI_ADRV9025_ROUND_TO_EVEN = 0, /*!< Round floating point ties to an even value */ + ADI_ADRV9025_ROUNDTOWARDS_POSITIVE = 1, /*!< Round floating point toward the positive direction */ + ADI_ADRV9025_ROUNDTOWARDS_NEGATIVE = 2, /*!< Round floating point toward the negative direction */ + ADI_ADRV9025_ROUNDTOWARDS_ZERO = 3, /*!< Round floating point toward the zero direction */ + ADI_ADRV9025_ROUND_FROM_EVEN = 4 /*!< Round floating point ties away from even value */ +} adi_adrv9025_FpRoundModes_e; + +/** + * \brief Enum to hold ADRV9025 Rx attenuation values that are used when the + * floating point format is enabled + */ +typedef enum adi_adrv9025_FpAttenSteps +{ + ADI_ADRV9025_FPATTEN_24DB = 4, /*!< Set Rx attenuation to 24 dB when Rx Data format set to floating point mode */ + ADI_ADRV9025_FPATTEN_18DB = 5, /*!< Set Rx attenuation to 18 dB when Rx Data format set to floating point mode */ + ADI_ADRV9025_FPATTEN_12DB = 6, /*!< Set Rx attenuation to 12 dB when Rx Data format set to floating point mode */ + ADI_ADRV9025_FPATTEN_6DB = 7, /*!< Set Rx attenuation to 6 dB when Rx Data format set to floating point mode */ + ADI_ADRV9025_FPATTEN_0DB = 0, /*!< Set Rx attenuation to 0 dB when Rx Data format set to floating point mode */ + ADI_ADRV9025_FPATTEN_MINUS6DB = 1, /*!< Set Rx attenuation to -6 dB when Rx Data format set to floating point mode */ + ADI_ADRV9025_FPATTEN_MINUS12DB = 2, /*!< Set Rx attenuation to -12 dB when Rx Data format set to floating point mode */ + ADI_ADRV9025_FPATTEN_MINUS18DB = 3 /*!< Set Rx attenuation to -18 dB when Rx Data format set to floating point mode */ +} adi_adrv9025_FpAttenSteps_e; + +/** + * \brief Enum to select the four Data Formatting options + */ +typedef enum adi_adrv9025_RxDataFormatModes +{ + ADI_ADRV9025_GAIN_COMPENSATION_DISABLED = 0, /*!< Gain Compensation and Data Formatting are disabled */ + ADI_ADRV9025_GAIN_WITH_FLOATING_POINT, /*!< Gain Compensation enabled with floating point data formatting enabled and internal slicer enabled */ + ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO, /*!< Gain Compensation enabled with integer data formatting and internal slicer enabled with no GPIO Slicer Position output. The slicer position is embedded in the JESD data */ + ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE, /*!< Gain Compensation enabled with integer data formatting and internal slicer enabled with GPIO Slicer Position output. The least significant 3 bits of the slicer control word are output on the GPIO */ + ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE, /*!< Gain Compensation enabled with integer data formatting and internal slicer enabled with GPIO Slicer Position output. All 4 bits of the slicer control word are output on the GPIOs */ + ADI_ADRV9025_GAIN_WITH_EXTERNAL_SLICER, /*!< Gain Compensation enabled with integer data formatting and external slicer enabled */ + ADI_ADRV9025_EMBED_OVERLOAD_MONITOR_DATA /*!< Embed 1-bit/2 bit monitor data on the 2 least significant bits of a 16-bit 2's Complement JESD Rx data */ +} adi_adrv9025_RxDataFormatModes_e; + +/** + * \brief Enum to hold ADRV9025 Gain Slicer external pin gain step size. Slicer gain in this mode is determined by multiplying the step size by the step size selection from the base band processor. + */ +typedef enum adi_adrv9025_ExtSlicerStepSizes +{ + ADI_ADRV9025_EXTSLICER_STEPSIZE_1DB = 0, /*!< Set Gain Slicer External gain step size to 1dB */ + ADI_ADRV9025_EXTSLICER_STEPSIZE_2DB, /*!< Set Gain Slicer External gain step size to 2dB */ + ADI_ADRV9025_EXTSLICER_STEPSIZE_3DB, /*!< Set Gain Slicer External gain step size to 3dB */ + ADI_ADRV9025_EXTSLICER_STEPSIZE_4DB, /*!< Set Gain Slicer External gain step size to 4dB */ + ADI_ADRV9025_EXTSLICER_STEPSIZE_6DB /*!< Set Gain Slicer External gain step size to 6dB */ +} adi_adrv9025_ExtSlicerStepSizes_e; + +/** + * \brief Enum to hold ADRV9025 Internal Gain Slicer gain step size. Slicer gain in this mode is determined by multiplying the step size by the step size selection from the base band processor. + */ +typedef enum adi_adrv9025_IntSlicerStepSizes +{ + ADI_ADRV9025_INTSLICER_STEPSIZE_1DB = 0, /*!< Set Gain Slicer Internal gain step size to 1dB */ + ADI_ADRV9025_INTSLICER_STEPSIZE_2DB, /*!< Set Gain Slicer Internal gain step size to 2dB */ + ADI_ADRV9025_INTSLICER_STEPSIZE_3DB, /*!< Set Gain Slicer Internal gain step size to 3dB */ + ADI_ADRV9025_INTSLICER_STEPSIZE_4DB, /*!< Set Gain Slicer Internal gain step size to 4dB */ + ADI_ADRV9025_INTSLICER_STEPSIZE_6DB, /*!< Set Gain Slicer Internal gain step size to 6dB */ + ADI_ADRV9025_INTSLICER_STEPSIZE_8DB /*!< Set Gain Slicer Internal gain step size to 8dB */ +} adi_adrv9025_IntSlicerStepSizes_e; + +/** + * \brief Enum to hold ADRV9025 Rx Gain Slicer external pin GPIO selection options + */ +typedef enum adi_adrv9025_RxExtSlicerGpioSel_e +{ + ADI_ADRV9025_EXTSLICER_RX_GPIO_DISABLE = 0, /*!< No GPIO assigned to external slicer */ + ADI_ADRV9025_EXTSLICER_RX_GPIO_2_DOWNTO_0 = 1, /*!< Select Rx Gain Slicer External GPIO2, GPIO1, GPIO0 */ + ADI_ADRV9025_EXTSLICER_RX_GPIO_5_DOWNTO_3 = 2, /*!< Select Rx Gain Slicer External GPIO5, GPIO4, GPIO3 */ + ADI_ADRV9025_EXTSLICER_RX_GPIO_8_DOWNTO_6 = 3, /*!< Select Rx Gain Slicer External GPIO8, GPIO7, GPIO6 */ + ADI_ADRV9025_EXTSLICER_RX_GPIO_11_DOWNTO_9 = 4, /*!< Select Rx Gain Slicer External GPIO11, GPIO10, GPIO9 */ + ADI_ADRV9025_EXTSLICER_RX_GPIO_14_DOWNTO_12 = 5, /*!< Select Rx Gain Slicer External GPIO14, GPIO13, GPIO12 */ + ADI_ADRV9025_EXTSLICER_RX_GPIO_17_DOWNTO_15 = 6, /*!< Select Rx Gain Slicer External GPIO17, GPIO16, GPIO15 */ + ADI_ADRV9025_EXTSLICER_RX_GPIO_INVALID = 7 +} adi_adrv9025_RxExtSlicerGpioSel_e; + +/** + * \brief Enum to hold ADRV9025 Rx1 Gain Slicer external pin GPIO selection options + */ +typedef enum adi_adrv9025_Rx1ExtSlicerGpioSel +{ + ADI_ADRV9025_EXTSLICER_RX1_GPIO0_1_2 = 0, /*!< Select Rx1 Gain Slicer External GPIO0, GPIO1, GPIO2 */ + ADI_ADRV9025_EXTSLICER_RX1_GPIO5_6_7, /*!< Select Rx1 Gain Slicer External GPIO5, GPIO6, GPIO7 */ + ADI_ADRV9025_EXTSLICER_RX1_GPIO8_9_10, /*!< Select Rx1 Gain Slicer External GPIO8, GPIO9, GPIO10 */ + ADI_ADRV9025_EXTSLICER_RX1_GPIO_DISABLE /*!< Select Rx1 Disable Gain Slicer External GPIO */ +} adi_adrv9025_Rx1ExtSlicerGpioSel_e; + +/** + * \brief Enum to hold ADRV9025 integer mode parity selection for 3 bit slicer mode + */ +typedef enum adi_adrv9025_RxIntParity +{ + ADI_ADRV9025_3BIT_SLICER_EVEN_PARITY = 0, /*!< Even parity for the unused 4th bit in 3 bit slicer mode */ + ADI_ADRV9025_3BIT_SLICER_ODD_PARITY = 1, /*!< Odd parity for the unused 4th bit in 3 bit slicer mode */ + ADI_ADRV9025_NO_PARITY = 2 /*!< Disable parity */ +} adi_adrv9025_RxIntParity_e; + +/** + * \brief Enum to hold ADRV9025 Rx2 Gain Slicer external pin GPIO selection options + */ +typedef enum adi_adrv9025_Rx2ExtSlicerGpioSel +{ + ADI_ADRV9025_EXTSLICER_RX2_GPIO11_12_13 = 0, /*!< Select Rx2 Gain Slicer External GPIO11, GPIO12, GPIO13 */ + ADI_ADRV9025_EXTSLICER_RX2_GPIO5_6_7 = 1, /*!< Select Rx2 Gain Slicer External GPIO5, GPIO6, GPIO7 */ + ADI_ADRV9025_EXTSLICER_RX2_GPIO_DISABLE = 3 /*!< Select Rx2 Disable Gain Slicer External GPIO */ +} adi_adrv9025_Rx2ExtSlicerGpioSel_e; + +/** + * \brief Enum to hold ADRV9025 integer mode number of embedded slicer bits and positions + */ +typedef enum adi_adrv9025_RxSlicerEmbeddedBits +{ + ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS = 0, /*!< Disabled all embedded slicer bits */ + ADI_ADRV9025_EMBED_1_SLICERBIT_AT_MSB, /*!< Embeds 1 slicer bits on I and 1 slicer bits on Q and the MSB position in the data frame */ + ADI_ADRV9025_EMBED_1_SLICERBIT_AT_LSB, /*!< Embeds 1 slicer bits on I and 1 slicer bits on Q and the LSB position in the data frame */ + ADI_ADRV9025_EMBED_2_SLICERBITS_AT_MSB_3_BIT_SLICER, /*!< Embeds 2 slicer bits on I and 2 slicer bits on Q and the MSB position in the data frame whereas only 3 bits are used for slicer ctrl (2 bits on I, 1 bit Q) */ + ADI_ADRV9025_EMBED_2_SLICERBITS_AT_LSB_3_BIT_SLICER, /*!< Embeds 2 slicer bits on I and 2 slicer bits on Q and the LSB position in the data frame whereas only 3 bits are used for slicer ctrl (2 bits on I, 1 bit Q) */ + ADI_ADRV9025_EMBED_2_SLICERBITS_AT_MSB_4_BIT_SLICER, /*!< Embeds 2 slicer bits on I and 2 slicer bits on Q and the MSB position in the data frame and all 4 bits are used for slicer ctrl*/ + ADI_ADRV9025_EMBED_2_SLICERBITS_AT_LSB_4_BIT_SLICER /*!< Embeds 2 slicer bits on I and 2 slicer bits on Q and the LSB position in the data frame and all 4 bits are used for slicer ctrl*/ +} adi_adrv9025_RxSlicerEmbeddedBits_e; + +/** + * \brief Enum to hold ADRV9025 slicer control word nibble position + */ +typedef enum adi_adrv9025_RxSlicerEmbeddedPos +{ + ADI_ADRV9025_LOWER_NIBBLE_ON_Q = 0, /*!< Place the lower control nibble on Q and the upper control nibble on I */ + ADI_ADRV9025_LOWER_NIBBLE_ON_I /*!< Place the lower control nibble on I and the upper control nibble on Q */ +} adi_adrv9025_RxSlicerEmbeddedPos_e; + +/** +* \brief Enum to hold ADRV9025 integer sample resolution +*/ +typedef enum adi_adrv9025_RxIntSampleResolution +{ + ADI_ADRV9025_INTEGER_12BIT_2SCOMP = 0, /*!< Selects integer sample 12 bit resolution with 2s compliment */ + ADI_ADRV9025_INTEGER_12BIT_SIGNED, /*!< Selects integer sample 12 bit resolution with signed magnitude */ + ADI_ADRV9025_INTEGER_16BIT_2SCOMP, /*!< Selects integer sample 16 bit resolution with 2s compliment */ + ADI_ADRV9025_INTEGER_16BIT_SIGNED, /*!< Selects integer sample 16 bit resolution with signed magnitude */ + ADI_ADRV9025_INTEGER_24BIT_2SCOMP, /*!< Selects integer sample 24 bit resolution with 2s compliment */ + ADI_ADRV9025_INTEGER_24BIT_SIGNED /*!< Selects integer sample 24 bit resolution with signed magnitude */ +} adi_adrv9025_RxIntSampleResolution_e; + +/** +* \brief Enum to hold ADRV9025 Embedded Monitor Mode sources +*/ +typedef enum adi_adrv9025_RxEmbeddedMonitorSrc +{ + ADI_ADRV9025_RX_EMB_MON_SRC_NO_MON_DATA_EMBEDDED = 0, /*!< Embedded overload monitor data is not embedded for the selected bit position in 16 bit Rx data */ + ADI_ADRV9025_RX_EMB_MON_SRC_HB2_LOW_THRESH = 3, /*!< Selects digital HB2 low threshold monitor data to be embedded in Rx data */ + ADI_ADRV9025_RX_EMB_MON_SRC_HB2_HIGH_THRESH = 4, /*!< Selects digital HB2 high threshold monitor data to be embedded in Rx data */ + ADI_ADRV9025_RX_EMB_MON_SRC_APD_LOW_THRESH = 5, /*!< Selects analog peak detector low threshold monitor data to be embedded in Rx data */ + ADI_ADRV9025_RX_EMB_MON_SRC_APD_HIGH_THRESH = 6, /*!< Selects analog peak detector high threshold monitor data to be embedded in Rx data */ + ADI_ADRV9025_RX_EMB_MON_SRC_INVALID = 7 /*!< Invalid embedded monitoring source */ +} adi_adrv9025_RxEmbeddedMonitorSrc_e; + +/** +* \brief Enum to hold ADRV9025 Embedded Monitor Mode HB2 Low source +*/ +typedef enum adi_adrv9025_RxHb2LowEmbeddedMonitorSrc +{ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW = 0, /*!< Selects digital HB2 lower threshold exceeded flag as HB2 low threshold monitor data */ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT0 = 1, /*!< Selects digital HB2 interval 0 lower threshold exceeded flag as HB2 low threshold monitor data */ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1 = 2, /*!< Selects digital HB2 interval 1 lower threshold exceeded flag as HB2 low threshold monitor data */ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_THRESH_CNTR_EXCEEDED = 4, /*!< Selects digital HB2 lower threshold exceeded counter flag as HB2 low threshold monitor data */ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT0_THRESH_CNTR_EXCEEDED = 5, /*!< Selects digital HB2 interval 0 lower threshold exceeded counter flag as HB2 low threshold monitor data */ + ADI_ADRV9025_HB2_LOW_SRC_OVRG_LOW_INT1_THRESH_CNTR_EXCEEDED = 6, /*!< Selects digital HB2 interval 1 lower threshold exceeded counter flag as HB2 low threshold monitor data */ + ADI_ADRV9025_HB2_LOW_SRC_INVALID /*!< Invalid HB2 low source */ +} adi_adrv9025_RxHb2LowEmbeddedMonitorSrc_e; + +/** +* \brief Enum to hold ADRV9025 Embedded Monitor Mode HB2 High source +*/ +typedef enum adi_adrv9025_RxHb2HighEmbeddedMonitorSrc +{ + ADI_ADRV9025_HB2_HIGH_SRC_OVRG_HIGH = 0, /*!< Selects digital HB2 overrange high threshold exceeded flag as HB2 high threshold monitor data */ + ADI_ADRV9025_HB2_HIGH_SRC_OVRG_HIGH_CNTR_EXCEEDED, /*!< Selects digital HB2 overrange high threshold counter exceeded flag as HB2 high threshold monitor data */ + ADI_ADRV9025_HB2_HIGH_SRC_INVALID /*!< Invalid HB2 high source */ +} adi_adrv9025_RxHb2HighEmbeddedMonitorSrc_e; + +/** +* \brief Enum to hold ADRV9025 Embedded Monitor Mode Analog Peak Detector High source +*/ +typedef enum adi_adrv9025_RxApdHighEmbeddedMonitorSrc +{ + ADI_ADRV9025_APD_HIGH_SRC_UPPER_LEVEL_BLOCKER_EXCEEDED = 0, /*!< Selects analog peak detector upper level blocker exceeded flag as APD high threshold monitor data */ + ADI_ADRV9025_APD_HIGH_SRC_UPPER_LEVEL_BLOCKER_CNTR_EXCEEDED, /*!< Selects analog peak detector upper level blocker counter exceeded flag as APD high threshold monitor data */ + ADI_ADRV9025_APD_HIGH_SRC_INVALID /*!< Invalid APD high source */ +} adi_adrv9025_RxApdHighEmbeddedMonitorSrc_e; + +/** +* \brief Enum to hold ADRV9025 Embedded Monitor Mode Analog Peak Detector Low source +*/ +typedef enum adi_adrv9025_RxApdLowEmbeddedMonitorSrc +{ + ADI_ADRV9025_APD_LOW_SRC_LOWER_LEVEL_BLOCKER_EXCEEDED = 0, /*!< Selects analog peak detector lower level blocker exceeded flag as APD low threshold monitor data */ + ADI_ADRV9025_APD_LOW_SRC_LOWER_LEVEL_BLOCKER_CNTR_EXCEEDED, /*!< Selects analog peak detector lower level blocker counter exceeded flag as APD low threshold monitor data */ + ADI_ADRV9025_APD_LOW_SRC_INVALID /*!< Invalid APD low source */ +} adi_adrv9025_RxApdLowEmbeddedMonitorSrc_e; + +/** +* \brief Enum to hold ADRV9025 RxNcoChannel options +*/ +typedef enum adi_adrv9025_RxNcoChannel +{ + ADI_ADRV9025_RX1_NCO1A = 0, + ADI_ADRV9025_RX1_NCO1B, + ADI_ADRV9025_RX1_NCO2A, + ADI_ADRV9025_RX1_NCO2B, + ADI_ADRV9025_RX2_NCO1A, + ADI_ADRV9025_RX2_NCO1B, + ADI_ADRV9025_RX2_NCO2A, + ADI_ADRV9025_RX2_NCO2B +} adi_adrv9025_RxNcoChannel_e; + +/** +* \brief Enum to hold ADRV9025 RxNcoBand Select options +*/ +typedef enum adi_adrv9025_RxNcoBandSelect +{ + ADI_ADRV9025_NCO_BANDA = 0, + ADI_ADRV9025_NCO_BANDB = 1 +} adi_adrv9025_RxNcoBandSelect_e; + +/** +* \brief Enum of possible DDC Modes +*/ +typedef enum adi_adrv9025_RxDdc +{ + ADI_ADRV9025_RXDDC_BYPASS = 0, /*!< No Half Band Enabled */ + ADI_ADRV9025_RXDDC_FILTERONLY, /*!< Half Band Filters only */ + ADI_ADRV9025_RXDDC_INT2, /*!< Half Band Interpolation by 2 */ + ADI_ADRV9025_RXDDC_DEC2, /*!< Half Band Decimate by 2 */ + ADI_ADRV9025_RXDDC_BYPASS_REALIF, /*!< No Half Band Enabled */ + ADI_ADRV9025_RXDDC_FILTERONLY_REALIF, /*!< Half Band Filters only */ + ADI_ADRV9025_RXDDC_INT2_REALIF, /*!< Half Band Interpolation by 2 */ + ADI_ADRV9025_RXDDC_DEC2_REALIF /*!< Half Band Decimate by 2 */ +} adi_adrv9025_RxDdc_e; + +/** +* \brief Enum to hold ADRV9025 RxNco enable options +*/ +typedef enum adi_adrv9025_RxNcoEnable +{ + ADI_ADRV9025_NCO_OFF = 0x00, /*!< No NCO enabled */ + ADI_ADRV9025_BAND_A_NCO_1 = 0x01, /*!< Enable Band A on NCO 1 */ + ADI_ADRV9025_BAND_B_NCO_1 = 0x02, /*!< Enable Band B on NCO 1 */ + ADI_ADRV9025_BAND_A_NCO_2 = 0x04, /*!< Enable Band A on NCO 2 */ + ADI_ADRV9025_BAND_B_NCO_2 = 0x08, /*!< Enable Band B on NCO 2 */ + ADI_ADRV9025_BAND_A_B_NCO_1_2 = 0x0F /*!< Enable NCO 1 & 2, Band A & B */ +} adi_adrv9025_RxNcoEnable_e; + +/** +* \brief Enum of possible Ext Ctrl pin output for ADRV9025 +*/ +typedef enum adi_adrv9025_RxExtCtrlPinOuputEnable +{ + ADI_ADRV9025_DISABLE_RX1_RX2_EXT_CTRL_GPIOS, /*!< Disable Rx1 and Rx2 Ext Ctrl Word output on Analog GPIOs */ + ADI_ADRV9025_ENABLE_RX1_RX2_EXT_CTRL_GPIOS, /*!< Enable Rx1 and Rx2 Ext Ctrl Word output on Analog GPIOs */ + ADI_ADRV9025_DISABLE_RX3_RX4_EXT_CTRL_GPIOS, /*!< Disable Rx3 and Rx4 Ext Ctrl Word output on Analog GPIOs */ + ADI_ADRV9025_ENABLE_RX3_RX4_EXT_CTRL_GPIOS, /*!< Enable Rx1 and Rx2 Ext Ctrl Word output on Analog GPIOs */ + ADI_ADRV9025_DISABLE_RX1_RX2_RX3_RX4_EXT_CTRL_GPIOS, /*!< Disable Rx1,Rx2,Rx3 and Rx4 Ext Ctrl Word output on Analog GPIOs */ + ADI_ADRV9025_ENABLE_RX1_RX2_RX3_RX4_EXT_CTRL_GPIOS /*!< Enable Rx1,Rx2,Rx3 and Rx4 Ext Ctrl Word output on Analog GPIOs */ +} adi_adrv9025_RxExtCtrlPinOuputEnable_e; + +/** + * \brief Data structure to hold ADRV9025 Rx gain table row entry + */ +typedef struct adi_adrv9025_RxGainTableRow +{ + uint8_t rxFeGain; /*!< Rx Front End gain for a given gain index */ + uint8_t extControl; /*!< External LNA control word */ + uint8_t adcTiaGain; /*!< ADC and TIA control for a given gain index */ + int16_t digGain; /*!< Digital gain ranging from -18dB to 50dB (68dB total range) */ + uint16_t phaseOffset; /*!< 16 bit phase offset from 0 - 2pi in resolution of 0.005 degrees */ +} adi_adrv9025_RxGainTableRow_t; + +/** + * \brief Data structure to hold ADRV9025 Rx dualband LNA gain table entries + */ +typedef struct adi_adrv9025_DualBandLnaGtRow +{ + uint8_t dualbandControl; /*!< The external control value to be output on the 3.3V GPIO's to control the LNA (values 0-3). */ + uint8_t dualbandGain; /*!< The gain compensation value for the corresponding external control, used for RSSI and gain compensation. + Range of 0 to 63 (0 to +31.5db in 0.5db steps). */ +} adi_adrv9025_DualBandLnaGtRow_t; + +/** + * \brief Data structure to hold ADRV9025 Rx dualband RxGainTable configurations. + */ +typedef struct adi_adrv9025_DualBandRxGainTableCfg +{ + uint32_t rxChannelMask; + adi_adrv9025_DualBandLnaGtRow_t* dualBandGainTablePtr; + uint8_t numgainIndicesInTable; +} adi_adrv9025_DualBandRxGainTableCfg_t; + +/** +* \brief Data structure to hold ADRV9025 Rx gain index config +*/ +typedef struct adi_adrv9025_RxGain +{ + uint32_t rxChannelMask; /*!< Rx Channels for which gain index needs to be updated. Bits 0-3, 4-7 correspond to Rx1-Rx4, ORx1-ORx4 respectively */ + uint8_t gainIndex; /*!< Gain Index for the channels selected in rxChannelMask */ +} adi_adrv9025_RxGain_t; + +/** +* \brief Data structure to hold ADRV9025 Rx Agc Mode configurations. +*/ +typedef struct adi_adrv9025_RxAgcMode +{ + uint32_t rxChannelMask; + adi_adrv9025_RxAgcMode_e agcMode; +} adi_adrv9025_RxAgcMode_t; + +/** +* \brief Data structure to hold ADRV9025 Floating Point Formatter Configuration +*/ +typedef struct adi_adrv9025_FloatingPointConfigSettings +{ + adi_adrv9025_FpFloatDataFormat_e fpDataFormat; /*!< Floating point format to select between {Sign, Significand, Exponent} and {Sign, Exponent, Significand} */ + adi_adrv9025_FpRoundModes_e fpRoundMode; /*!< Rounding mode for floating point format (See enum values) */ + adi_adrv9025_FpExponentModes_e fpNumExpBits; /*!< Indicates the number of exponent and significand bits in the floating point number */ + adi_adrv9025_FpAttenSteps_e fpAttenSteps; /*!< Attenuate integer data when floating point mode enabled, see enum for values from 0dB to 42dB in 6dB steps */ + adi_adrv9025_FpHideLeadingOne_e fpHideLeadingOne; /*!< 1 = Hides the leading one in significand to be compatible to the IEEE754 specification. 0 = a leading one exists at the MSB of the significand. (Valid: 0, 1) */ + adi_adrv9025_FpNanEncode_e fpEncodeNan; /*!< 1 = encodes the highest value of Exponent to mean NaN (Not a Number) to be compatible to IEEE754 specification (Valid: 0 or 1) */ +} adi_adrv9025_FloatingPointConfigSettings_t; + +/** +* \brief Data structure to hold ADRV9025 Integer Formatter Configuration +*/ +typedef struct adi_adrv9025_IntegerConfigSettings +{ + adi_adrv9025_RxSlicerEmbeddedBits_e intEmbeddedBits; /*!< No. of embedded slicer bits in Rx Data */ + adi_adrv9025_RxIntSampleResolution_e intSampleResolution; /*!< Resolution of Rx Data */ + adi_adrv9025_RxIntParity_e intParity; /*!< Parity - applicable only for 3bit slicer mode */ + adi_adrv9025_RxSlicerEmbeddedPos_e intEmbeddedPos; /*!< Selects the position of the upper and lower embedded slicer control word */ +} adi_adrv9025_IntegerConfigSettings_t; + +/** + * \brief Data structure to hold ADRV9025 Slicer Configuration settings + */ +typedef struct adi_adrv9025_SlicerConfigSettings +{ + adi_adrv9025_ExtSlicerStepSizes_e extSlicerStepSize; /*!< Enum selects the external pin gain step size */ + adi_adrv9025_IntSlicerStepSizes_e intSlicerStepSize; /*!< Enum selects the internal pin gain step size */ + adi_adrv9025_RxExtSlicerGpioSel_e rx1ExtSlicerGpioSelect; /*!< Enum selects the Rx1 Ext Ctrl GPIO Configuration */ + adi_adrv9025_RxExtSlicerGpioSel_e rx2ExtSlicerGpioSelect; /*!< Enum selects the Rx2 Ext Ctrl GPIO Configuration */ + adi_adrv9025_RxExtSlicerGpioSel_e rx3ExtSlicerGpioSelect; /*!< Enum selects the Rx3 Ext Ctrl GPIO Configuration */ + adi_adrv9025_RxExtSlicerGpioSel_e rx4ExtSlicerGpioSelect; /*!< Enum selects the Rx4 Ext Ctrl GPIO Configuration */ +} adi_adrv9025_SlicerConfigSettings_t; + +/** +* \brief Data structure to hold ADRV9025 Rx Embedded Monitor Formatter Configuration +*/ +typedef struct adi_adrv9025_EmbOverloadMonitorConfigSettings +{ + adi_adrv9025_RxEmbeddedMonitorSrc_e embeddedMonitorSrcLsbI; /*!< Selects the monitor data to be embedded into LSB location of 16-bit Rx data - I sample */ + adi_adrv9025_RxEmbeddedMonitorSrc_e embeddedMonitorSrcLsbQ; /*!< Selects the monitor data to be embedded into LSB location of 16-bit Rx data - Q sample */ + adi_adrv9025_RxEmbeddedMonitorSrc_e embeddedMonitorSrcLsbPlusOneI; /*!< Selects the monitor data to be embedded into LSB+1 location of 16-bit Rx data - I sample */ + adi_adrv9025_RxEmbeddedMonitorSrc_e embeddedMonitorSrcLsbPlusOneQ; /*!< Selects the monitor data to be embedded into LSB+1 location of 16-bit Rx data - Q sample */ + adi_adrv9025_RxHb2LowEmbeddedMonitorSrc_e embeddedMonitorHb2LowSrcSel; /*!< If digital HB2 Low monitor is selected to be embedded into Rx data, the source of digital HB2 low threshold is selected by this param */ + adi_adrv9025_RxHb2HighEmbeddedMonitorSrc_e embeddedMonitorHb2HighSrcSel; /*!< If digital HB2 High monitor is selected to be embedded into Rx data, the source of digital HB2 high threshold is selected by this param */ + adi_adrv9025_RxApdLowEmbeddedMonitorSrc_e embeddedMonitorApdLowSrcSel; /*!< If analog peak detector low monitor is selected to be embedded into Rx data, the source of analog peak detector low threshold is selected by this param */ + adi_adrv9025_RxApdHighEmbeddedMonitorSrc_e embeddedMonitorApdHighSrcSel; /*!< If analog peak detector high monitor is selected to be embedded into Rx data, the source of analog peak detector low threshold is selected by this param */ + uint8_t invertHb2Flag; /*!< When inverted, Hb2 emmbedded overload monitor flag operates as active low, 0:Don't invert / Other:Invert*/ + uint8_t invertApdFlag; /*!< When inverted, Apd emmbedded overload monitor flag operates as active low, 0:Don't invert / Other:Invert*/ +} adi_adrv9025_EmbOverloadMonitorConfigSettings_t; + +/** +* \brief Data structure to hold ADRV9025 Floating Point Formatter Configuration +*/ +typedef struct adi_adrv9025_RxDataFormat +{ + uint32_t rxChannelMask; /*!< Rx Channels for which the config settings are to be applied */ + adi_adrv9025_RxDataFormatModes_e formatSelect; /*!< Rx Channel format mode selects */ + adi_adrv9025_FloatingPointConfigSettings_t floatingPointConfig; /*!< Rx Channel floating point format configuration. Ignored if formatSelect is + * NOT set to ADI_ADRV9025_GAIN_WITH_FLOATING_POINT */ + adi_adrv9025_IntegerConfigSettings_t integerConfigSettings; /*!< Rx Channel integer format configuration. Please note that integerConfigSettings.intSampleResolution needs to be set to a valid value for all modes of formatSelect */ + adi_adrv9025_SlicerConfigSettings_t slicerConfigSettings; /*!< Rx Channel integer slicer configuration. Ignored if formatSelect is NOT set to ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO, ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER or ADI_ADRV9025_GAIN_WITH_EXTERNAL_SLICER_NOGPIO */ + adi_adrv9025_EmbOverloadMonitorConfigSettings_t embOvldMonitorSettings; /*!< Rx Channel embedded overload monitor settings. Ignored if formatSelect is NOT set to ADI_ADRV9025_EMBED_MONITOR_DATA. Embedded overload monitoring is supported for Rx channels only */ + uint8_t externalLnaGain; /*!< Selects Slicer to compensate for external dualband LNA {0 - disabled, 1 - enabled} */ + uint8_t tempCompensationEnable; /*!< Selects Slicer to compensate for temperature variations {0 - disabled, 1 - enabled} */ +} adi_adrv9025_RxDataFormat_t; + +/** + * \brief Data structure to hold ADRV9025 Rx Gain Control Pin Configuration + */ +typedef struct adi_adrv9025_RxGainPinCfg +{ + //uint32_t rxChannelMask; + uint8_t incStep; /*!< Increment in gain index applied when the increment gain pin is pulsed. A value of 0 to 7 applies a step size of 1 to 8 */ + uint8_t decStep; /*!< Decrement in gain index applied when the increment gain pin is pulsed. A value of 0 to 7 applies a step size of 1 to 8 */ + adi_adrv9025_GpioPinSel_e rxGainIncPin; /*!< GPIO used for the Increment gain input: ADI_ADRV9025_GPIO00 - ADI_ADRV9025_GPIO15 can be used */ + adi_adrv9025_GpioPinSel_e rxGainDecPin; /*!< GPIO used for the Decrement gain input: ADI_ADRV9025_GPIO00 - ADI_ADRV9025_GPIO15 can be used */ + uint8_t enable; /*!< Enable (1) or disable (0) the gain pin control*/ +} adi_adrv9025_RxGainPinCfg_t; + +/** + * \brief Data structure to hold ADRV9025 Rx NCO shifter parameters for both BandA and BandB + * configurations. Settings all four element values to zero for a band will disable the NCO + * for that shift. + */ +typedef struct adi_adrv9025_RxNcoShifterCfg +{ + uint32_t bandAInputBandWidth_kHz; /*!< BandWidth in khz of the BandA input signal */ + int32_t bandAInputCenterFreq_kHz; /*!< Center Frequency in khz of the BandA input signal */ + int32_t bandANco1Freq_kHz; /*!< BandA NCO1 Frequency shift in khz */ + int32_t bandANco2Freq_kHz; /*!< BandA NCO2 Frequency shift in khz */ + uint32_t bandBInputBandWidth_kHz; /*!< BandWidth in khz of the BandB input signal */ + int32_t bandBInputCenterFreq_kHz; /*!< Center Frequency in khz of the BandB input signal */ + int32_t bandBNco1Freq_kHz; /*!< BandB NCO1 Frequency shift in khz */ + int32_t bandBNco2Freq_kHz; /*!< BandB NCO2 Frequency shift in khz */ + int32_t bandAbCombinedEnable; /*!< BandA and BandB Combined at output, 1 = Combine dualband AB, 0 disable combine dualband on AB*/ +} adi_adrv9025_RxNcoShifterCfg_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_RX_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_tx.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_tx.h new file mode 100644 index 0000000..3889116 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_tx.h @@ -0,0 +1,1352 @@ +/** +* \file adi_adrv9025_tx.h +* \brief Contains ADRV9025 transmit related function prototypes for +* adi_adrv9025_tx.c +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_TX_H_ +#define _ADI_ADRV9025_TX_H_ + +#include "adi_adrv9025_types.h" +#include "adi_adrv9025_tx_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************** +* Initialization functions +**************************************************************************** +*/ + +/** +* \brief Configures one or more TX FIR filters in the device +* +* The device stores 1 Tx filter per channel. +* Tx filters can have 20, 40, 60, or 80 taps. +* +* The function is not called directly. It is called as a part of the adi_adrv9025_initialize() function. +* The function could be used to change A FIR filter later, but would require calibrations to be rerun. +* +* \pre This function is called during device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* +* \param device Pointer to the ADRV9025 data structure +* \param txChannelMask One or more TX Channel from adi_adrv9025_TxChannels_e. +* \param gain_dB The gain_dB value (-12, -6, 0, 6). +* \param numFirCoefs The number of Fir Coefs in coefs array (20, 40, 60, 80). +* \param coefs[] Pointer to coefs array +* \param arraySize The size of coefs array +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxFirWrite(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + int8_t gain_dB, + uint8_t numFirCoefs, + int16_t coefs[], + uint8_t arraySize); + +/** +* \brief Get one Tx FIR filters information for the requested Tx channel in the device +* +* \pre This function is called during device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param txChannel adi_adrv9025_TxChannels_e enum type to select. +* \param gain_dB Pointer to the gain_dB value read from device (output) +* \param numFirCoefs Pointer to the numFirCoefs value read from device (output) +* \param coefs[] Pointer to coefs array read from the device (output) +* \param arraySize The size of coefs array +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* \ +*/ +int32_t adi_adrv9025_TxFirRead(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + int8_t* gain_dB, + uint8_t* numFirCoefs, + int16_t coefs[], + uint8_t arraySize); + +/**************************************************************************** +* Runtime functions +**************************************************************************** +*/ + +/** +* \brief Function to set the Tx attenuation configuration +* +* \pre This function is called after the device is initialized. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param txAttenCfg array of structures of type adi_adrv9025_TxAttenCfg_t which will configure one or more channels +* \param attenCfgs number of configurations passed in the array + +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxAttenCfg_t txAttenCfg[], + uint8_t attenCfgs); + +/** +* \brief Function to set the Tx attenuation configuration +* +* \pre This function is called after the device is initialized +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 data structure +* \param txChannel channel selection to read the attenuation configuration of type adi_adrv9025_TxChannels_e +* \param txAttenCfg pointer to structure of type adi_adrv9025_TxAttenCfg_t which will contain the configuration for the givven channel +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxAttenCfg_t* txAttenCfg); + +/** +* \brief This API function will set the Tx RF output attenuation table for each Tx output channel +* +* txAttenTableRows->txAttenMult: Tx Atten Multi, set to (0-4095) from table. set to max value if not in table. +* txAttenTableRows->txAttenHp : Tx Atten HP, set to (0 - 63) from table. Set to max value if not in table. +* +* The full TxAtten table can be loaded in a single call. +* Or the table can be loaded in several calls, loading a subset of the table with each function call using the txAttenIndexOffset parameter. +* +* \pre This function may be called any time after device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device's data structure +* \param txChannelMask The Mask of one or more Tx Channels +* \param txAttenIndexOffset Offset of the TxAttentable in the Device from the minimum index (0 - 1023). +* \param txAttenTableRows The Array contain TxAttenTableRows +* \param numTxAttenEntries The number of elements in the TxAttenTableRows array (1 - 1024). +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenTableWrite(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + uint32_t txAttenIndexOffset, + adi_adrv9025_TxAttenTableRow_t txAttenTableRows[], + uint32_t numTxAttenEntries); + +/** +* \brief This API function will get the Tx RF output attenuation table for each Tx output channel +* +* The return table are array of Entries. +* txAttenTableRows->txAttenMult: Tx Atten Multi, get value (0-4095) +* txAttenTableRows->txAttenHp : Tx Atten HP, get value of (0 - 63) +* +* The full TxAtten table can be read in a single call. +* Or the table can be read in several calls, reading a subset of the table with each function call using the txAttenIndexOffset parameter. +* +* \pre This function may be called any time after device initialization +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device's data structure +* \param txChannel The Mask of one or more Tx Channels +* \param txAttenIndexOffset Offset of the TxAttentable in the Device from the minimum index (0 - 1023). +* \param txAttenTableRows The Array contain TxAttenTableEntries +* \param numTxAttenEntries The number of elements in the TxAttenTableRows array (1 - 1024). +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenTableRead(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + uint32_t txAttenIndexOffset, + adi_adrv9025_TxAttenTableRow_t txAttenTableRows[], + uint32_t numTxAttenEntries); + +/** +* \brief Function to set the attenuation control mode +* +* +* \param device Pointer to the ADRV9025 device's data structure +* \param txChannelMask The Mask of one or more Tx Channels +* \param txAttenMode Tx attenuation mode selection +* \param simultaneousUpdateCfg Simultaneous update configuration, valid only when txAttenMode is selected as SPI +* \param gpioModePinCfg GPIO control mode pin configuration, valid only when txAttenMode is selected as Mode +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenModeSet(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + adi_adrv9025_TxAttenMode_e txAttenMode, + adi_adrv9025_TxAttenSimultUpdateCfg_t simultaneousUpdateCfg, + adi_adrv9025_TxAttenPinCfg_t gpioModePinCfg); + +/** +* \brief Function to get the attenuation control mode programed to the part +* +* +* \param device Pointer to the ADRV9025 device's data structure +* \param txChannel Tx channel selection to read attenuation configuration +* \param txAttenMode Pointer to attenuation mode enum to read back +* \param simultaneousUpdateCfg Pointer to simultaneous config struct to read back +* \param gpioModePinCfg Pointer to GPIO pin config struct to read back +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenModeGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxAttenMode_e* txAttenMode, + adi_adrv9025_TxAttenSimultUpdateCfg_t* simultaneousUpdateCfg, + adi_adrv9025_TxAttenPinCfg_t* gpioModePinCfg); + +/** +* \brief This API function has to be used in order to set the Tx RF output attenuation +* for the Tx output channels +* +* The attenuation given by txAttenuation.txAttenuation_mdB will be applied to the txChannel or channels +* indicated by the txAttenuation.txChannelMask as follows: +* +* txChannel | Description +* ------------------------|------------------------------------ +* ADI_ADRV9025_TX1 | sets attenuation txAttenuation_mdB for TX1 +* ADI_ADRV9025_TX2 | sets attenuation txAttenuation_mdB for TX2 +* ADI_ADRV9025_TX3 | sets attenuation txAttenuation_mdB for TX3 +* ADI_ADRV9025_TX4 | sets attenuation txAttenuation_mdB for TX4 +* +* \pre This function may be called any time after device initialization +* \pre This feature requires the initialization to be complete and the attenuation table to be loaded. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device's data structure +* \param txAttenuation array of structure type adi_adrv9025_TxAtten_t +* which indicates the channel and the desired TxAttenuation in milli-dB +* (Range: 0 to 41950 mdB) +* \param numTxAttenConfigs array size passed in txAttenuation array +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxAtten_t txAttenuation[], + uint8_t numTxAttenConfigs); + +/** +* \brief Reads back the attenuation setting for the Tx channel output for the selected channel +* +* This function reads back the Tx attenuation setting for either the Tx1, Tx2, Tx3 or Tx4 RF channel currently applied to the transmit chain. +* This function can work with SPI mode or pin controlled Tx attenuation mode using the increment/decrement GPIO +* pins. +* +* \pre This feature requires the initialization to be complete and the attenuation table to be loaded. +* \pre The Tx data path must be powered up for the current attenuation value to be valid. If the Tx data path +* is powered down or the radio is off, the last Tx attenuation setting when the Tx output was previously active will be +* read back. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device's data structure +* \param txChannel channel selection to read the attenuation is of type adi_adrv9025_TxChannels_e +* \param txAttenuation Pointer to structure of adi_adrv9025_TxAtten_t type to store the readback value of the desired Tx channel attenuation in milli-dB (Range: 0 to 41950 mdB) +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxAtten_t* txAttenuation); + +/** +* \brief Sets the DAC full scale current boost +* +* This function can be used to adjust the DAC fullscale. +* This will change the Tx output power. The DAC fullscale of zero DB is the +* default setting. +* +* \pre This function must be called before loading the ADRV9025 ARM processor +* WARNING: This function should only be called once during init time before performing init calibrations +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device's data structure +* \param txChannel Channel to set the Dac scale +* \param dacFullScale Is an enum that sets the DAC boost levels. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DacFullScaleSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_DacFullScale_e dacFullScale); + +/** +* \brief Gets the DAC full scale current boost +* +* \pre This function must be called before loading the ADRV9025 ARM processor +* +* \param device Pointer to the ADRV9025 device's data structure +* \param txChannel Channel to get the Dac scale +* \param dacFullScale pointer to an enum that will contain the DAC boost levels. +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DacFullScaleGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_DacFullScale_e* dacFullScale); + +/** +* \brief Enables/Disables the Tx NCO test tone +* +* This function enables/disables a digital numerically controlled oscillator +* in the ADRV9025 Digital to create a test CW tone on the selected Tx RF output/s. +* +* The TxAttenuation is forced in this function to max analog output power. +* Ensure no other API's are called that change the Tx attenuation mode when using this +* function +* +* When the Tx NCO test tone is disabled, the function sets the Tx attenuation +* to the SPI mode. User may need to use other functions to change the mode. +* +* \param device Pointer to the ADRV9025 device's data structure +* \param txNcoTestToneCfg Pointer to adi_adrv9025_TxTestToneCfg_t structure that +* contains the configuration for the Tx NCO test tone +* \param arraySize +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxTestToneSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxTestToneCfg_t txNcoTestToneCfg[], + uint8_t arraySize); + +/** +* \brief Read back the Tx NCO test tone +* +* This function reads the settings for test CW tone on the selected Tx RF output/s. +* +* \param device Pointer to the ADRV9025 device's data structure +* \param txChannel Channel to get the test tone settings +* \param txNcoTestToneCfg Pointer to adi_adrv9025_TxTestToneCfg_t structure to write +* the configuration for the Tx NCO test tone read back from the part +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxTestToneGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxTestToneCfg_t* txNcoTestToneCfg); + +/** +* \brief Configures Attenuation steps and the GPIO inputs for Tx attenuation control +* +* This API function configures the GPIO input pin and step size to allow the +* BBP to control attenuation changes in Tx signal chain. +* A high pulse on the 'txAttenIncPin' in pin control mode will increment the +* gain by the value set in 'stepSize'. +* A high pulse on the 'txAttenDecPin' in pin control mode will decrement the +* gain by the value set in 'stepSize'. +* This function should only be used to change GPIO pins which are currently used for +* Tx attenuation control GPIO mode. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* +* +* \param txAttenPinCfg Pointer to an array of adi_adrv9025_TxAttenPinCfg_t structure that +* configures the Tx attenuation pin control. +* \param numTxAttenPinConfigs Number of channelized Tx Atten Pin configuration passed in the array txAttenPinCfg +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenPinCtrlCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxAttenPinCfg_t txAttenPinCfg[], + uint8_t numTxAttenPinConfigs); + +/** +* \brief This API function returns the configuration (Gain steps and the GPIO +* inputs) for Tx Attenuation pin control. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param txChannel enum type to select the Tx channel to read the Tx Attenuation pin control +* configuration from. +* \param txAttenPinCfg Pointer to structure that return values will be returned in +* for Tx attenuation pin control. +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenPinCtrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxAttenPinCfg_t* txAttenPinCfg); + +/** +* \brief Configures GPIO pin for Tx attenuation simultaneous update of selected Tx channels +* This function should only be used to change GPIO pin which is currently used for Tx attenuation +* simultaneous update. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param txChannelMask Multiple Tx channel selection for configuration +* \param gpioSelection GPIO pin selection for simultaneous Tx attenuation update +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenUpdateGpioPinCtrlCfgSet(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + adi_adrv9025_GpioPinSel_e gpioSelection); + +/** +* \brief Read GPIO pin configuration for Tx attenuation simultaneous update of selected Tx channels +* +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param txChannelSelect Tx channel selection to read configuration +* \param gpioSelection Pointer to enum which will be used to readback configuration +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenUpdateGpioPinCtrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannelSelect, + adi_adrv9025_GpioPinSel_e* gpioSelection); + +/** +* \brief This function updates Tx attenuation simultaneously for selected Tx channels. +* +* Update happens from tx attenuation value on spi register into the internal hardware +* Simultaneous update with this function can be triggered only when attenuation mode is SPI. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param txChannelMask Multiple Tx channel selection to trigger Tx attenuation update +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_COMMON_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenUpdate(adi_adrv9025_Device_t* device, + uint32_t txChannelMask); + +/** +* \brief Writes ADRV9025 device registers with settings for the PA Protection feature. +* +* This function sets up the PA Protection functionality and enables Tx sample +* power measurements. It does not enable the ability to change Tx Attenuation +* automatically. +* +* The PA Protection feature allows for error flags to go high if the +* average TX IQ sample power (before interpolation at JESD204 interface) in +* the data path exceeds a programmable threshold level based on samples taken +* in a programmable duration. Also, the peak power measurement mode allows +* flagging an error when the instantaneous power exceeds a threshold more than a +* programmable count value within the average duration. +* +* \pre Complete normal ADRV9025 initialization and init cals before running this function. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* Peak threshold value table for Silicon A +* peakThreshold Value | dBFS threshold = 10 * Log10(peakThresholdVal/128) +* --------------------|---------------------------------------------------------- +* 0 | Invalid +* 1 | -21.07 dBFS +* 2 | -18.06 dBFS +* 3 | -16.30 dBFS +* 4 | -15.05 dBFS +* 5 | -14.08 dBFS +* 6 | -13.29 dBFS +* 7 | -12.62 dBFS +* 8 | -12.04 dBFS +* ... | Calculate with EQ above +* 16 | -9.03 dBFS +* ... | ... +* 32 | -6.02 dBFS +* ... | ... +* 64 | -3.01 dBFS +* ... | ... +* 128 | 0 dBFS +* ... | ... +* 255 | 3.01 dBFS +* +* Peak threshold value table for Silicon B +* peakThreshold Value | dBFS threshold = 10 * Log10(peakThresholdVal/8192) +* --------------------|---------------------------------------------------------- +* 0 | Invalid +* 1 | -39.12 dBFS +* 2 | -36.11 dBFS +* 3 | -34.35 dBFS +* 4 | -33.10 dBFS +* 5 | -32.13 dBFS +* 6 | -31.34 dBFS +* 7 | -30.67 dBFS +* 8 | -30.09 dBFS +* ... | Calculate with EQ above +* 16 | -27.08 dBFS +* ... | ... +* 32 | -24.07 dBFS +* ... | ... +* 64 | -21.06 dBFS +* ... | ... +* 128 | -18.05 dBFS +* ... | ... +* 256 | -15.04 dBFS +* ... | ... +* 512 | -12.03 dBFS +* ... | ... +* 1024 | -9.02 dBFS +* ... | ... +* 2048 | -6.01 dBFS +* ... | ... +* 8191 | 0 dBFS +* +* Avg Power threshold value table for Silicon A +* powerThreshold Value| dBFS threshold = 10 * Log10(powerThreshold/4096) +* --------------------|---------------------------------------------------------- +* 0 | Invalid +* 1 | -36.12 dBFS +* 2 | -33.11 dBFS +* 3 | -31.35 dBFS +* 4 | -30.10 dBFS +* 5 | -29.13 dBFS +* 6 | -28.34 dBFS +* 7 | -27.67 dBFS +* 8 | -27.09 dBFS +* ... | Calculate with EQ above +* 16 | -24.08 dBFS +* ... | ... +* 32 | -21.07 dBFS +* ... | ... +* 64 | -18.06 dBFS +* ... | ... +* 128 | -15.05 dBFS +* ... | ... +* 256 | -12.04 dBFS +* ... | ... +* 512 | -9.03 dBFS +* 1024 | -6.02 dBFS +* ... | ... +* 2048 | -3.01 dBFS +* ... | ... +* 8191 | 3 dBFS +* +* Avg Power threshold value table for Silicon B +* powerThreshold Value| dBFS threshold = 10 * Log10(powerThreshold/8192) +* --------------------|---------------------------------------------------------- +* 0 | Invalid +* 1 | -39.12 dBFS +* 2 | -36.11 dBFS +* 3 | -34.35 dBFS +* 4 | -33.10 dBFS +* 5 | -32.13 dBFS +* 6 | -31.34 dBFS +* 7 | -30.67 dBFS +* 8 | -30.09 dBFS +* ... | Calculate with EQ above +* 16 | -27.08 dBFS +* ... | ... +* 32 | -24.07 dBFS +* ... | ... +* 64 | -21.06 dBFS +* ... | ... +* 128 | -18.05 dBFS +* ... | ... +* 256 | -15.04 dBFS +* ... | ... +* 512 | -12.03 dBFS +* ... | ... +* 1024 | -9.02 dBFS +* ... | ... +* 2048 | -6.01 dBFS +* ... | ... +* 8191 | 0 dBFS +* +* \param device Pointer to the device settings structure +* \param txPaProtectCfg array of structure holding the setup values for the Tx PA Protection feature +* \param arraySize number of txChannels to be configured +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxPaProtectionCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxPaProtectCfg_t txPaProtectCfg[], + uint8_t arraySize); + +/** +* \brief Reads ADRV9025 device registers to retrieve settings for the PA Protection feature. +* +* The PA Protection feature allows for error flags to go high if the +* average TX IQ sample power (before interpolation at JESD204 interface) in +* the data path exceeds a programmable threshold level based on samples taken +* in a programmable duration. Also, the peak power measurement mode allows +* flagging an error when the instantaneous power exceeds a threshold more than a +* programmable count value within the average duration. +* +* \pre Complete normal ADRV9025 initialization and init cals before running this function. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param txChannel enum type to select the Tx channel to read the Tx Attenuation pin control +* configuration from. +* \param txPaProtectCfg Structure to return the setup values for the Tx PA Protection feature +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxPaProtectionCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxPaProtectCfg_t* txPaProtectCfg); + +/** +* \brief Read back Tx average IQ sample power (input samples at JESD204 port) +* based on settings from adi_adrv9025_TxPaProtectionCfgSet() +* +* avgPower and avgErrorPower return value is not returned in dBFS. To calculate the dBFS value +* perform the follow calculation: +* Average Power in dBFS = 10 * log10(avgPower/2^16) +* Power Error in dBFS = 10 * log10(avgErrorPower/2^16) +* +* Ratio calculation for avgPeakRatio : avgPower/peakPower = ((avgPeakRatio) / 2^15) +* +* \pre Complete normal ADRV9025 initialization and init cals, and call +* adi_adrv9025_TxPaProtectionCfgSet() before using adi_adrv9025_TxSamplePowerGet() +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param txChannel enum type to select the Tx channel to read the Tx Attenuation pin control +* configuration from. +* \param status pointer to structure that will be populated with the most recent +* tx average IQ sample power for specified tx channel (linear power with 65536 = 0dB) +* and the avgPeakRatio +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxPaProtectionStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxPaProtectStatus_t* status); + +/** +* \brief Read back Tx PA Protection error IRQ flags +* +* If Tx PA Protection is configured and enabled, the error flags per channel +* can be read back to determine which transmitter exceeded the set peak or +* average power threshold. The PA protection error flags can also be set +* to assert the GP interrupt pin for immediate feedback to the BBIC when the +* Tx power into the PA is of concern. +* +* \pre Complete normal ADRV9025 initialization and init cals, and call +* adi_adrv9025_TxPaProtectionCfgSet() first +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param txChannel enum type to select the Tx channel to read the Tx Attenuation pin control +* configuration from. +* \param errorFlags Returns error flag per channel. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxPaProtectionErrFlagsGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxPaProtectionErr_t* errorFlags); + +/** +* \brief Clears PA Protection error IRQ flags for the given channel. +* +* If Tx PA Protection is configured and enabled, the error flags per channel +* can be read back using the adi_adrv9025_TxPaProtectionErrFlagsGet function. The +* error flags will stay asserted until manually cleared if they're set to be sticky +* by using adi_adrv9025_TxAttenuationRampUpStickyModeEnable API function +* +* If the PA protection error flags are sticky, it is preferred to assign Pa protection +* events to any of the GPINT pins to monitor the error status and clear the error flags +* with this function +* +* Calling adi_adrv9025_TxPaProtectionCfgSet() will also clear the error flags at the +* end of the function to make sure PA protection is enabled with the error +* flags in a known state. +* +* \pre Complete normal ADRV9025 initialization and init cals, and call +* adi_adrv9025_TxPaProtectionCfgSet() first +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param txChannel of which flags are to be cleared. +* \param errorFlags to be cleared. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxPaProtectionErrFlagsReset(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxPaProtectErrFlags_e errorFlags); + +/** +* \brief Configures Attenuation SPI2 GPIO inputs for Tx attenuation control +* +* This API function configures the SPI2 GPIO input pin +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param txAttenSpi2PinCfg[] Pointer to an array of adi_adrv9025_TxAttenSpi2PinCfg_t structure that +* configures the Tx attenuation Spi2 pin control. +* \param numTxAttenSpi2PinConfigs Number of channelized Tx Atten Spi2 Pin configuration passed in the array txAttenSpi2PinCfg +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenSpi2PinCtrlCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxAttenSpi2PinCfg_t txAttenSpi2PinCfg[], + uint8_t numTxAttenSpi2PinConfigs); + +/** +* \brief This API function returns the configuration for Tx Attenuation SPi2 pin control. +* +* \dep_begin +* \dep{device->halDevInfo} +* \dep_end +* +* \param device Pointer to the device settings structure +* \param txChannel enum type to select the Tx channel to read the Tx configuration from. +* \param txAttenSpi2PinCfg Pointer to structure that return values will be returned in +* for Tx attenuation SPI2 pin control. +* +* \retval ADI_ADRV9025_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_ADRV9025_ERR_CHECK_PARAM Invalid parameter passed +* \retval ADI_ADRV9025_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_ADRV9025_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenSpi2PinCtrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxAttenSpi2PinCfg_t* txAttenSpi2PinCfg); + +/** +* \brief This function reads back the LO Source Mapping to the requested Tx channel. +* +* The LO source select for a given channel is configured during init time. This function +* can be used to read back the configuration during run time. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannel Enum to select Tx Channel. +* \param txLoSource Pointer to store Rx channel LO source mapping read back (Output) +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxLoSourceGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_LoSel_e* txLoSource); + +/** +* \brief This function reads back SRL Irq status(read only) of selected Tx channel. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannel Enum to select Tx Channel. +* \param enable Pointer to memory location where read back status will be written +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_SrlIrqGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + uint8_t* enable); + +/** +* \brief This function enables/disables SRL interrupts for selected Tx channel. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannel Enum to select Tx Channel. +* \param enable 0:Disable SRL interrupts for selected channel / Other:Enable SRL interrupts for selected channel +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_SrlIrqEnableSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + uint8_t enable); + +/** +* \brief This function reads whether SRL interrupts are enabled for selected Tx channel. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannel Enum to select Tx Channel. +* \param enable Pointer to memory location where readback value will be written +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_SrlIrqEnableGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + uint8_t* enable); + +/** +* \brief This function reads SRL statistics which is number of samples which have been +* slew rate limited(Maximum = 65536 sample count) +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannel Enum to select Tx Channel. +* \param clearStats 0:Don't clear statistics after reading / Other: Clear statistics after reading. +* \param statisticsReadBack Pointer to memory location where readback value will be written +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_SrlStatisticsRead(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + uint8_t clearStats, + uint16_t* statisticsReadBack); + +/** +* \brief This function sets the configuration of slew rate limiter for tx channels +* selected within the configuration struct (txChannelMask) +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param slewRateLimiterCfg SRL configuration to be written +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_SrlCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_SlewRateLimiterCfg_t slewRateLimiterCfg); + +/** +* \brief This function reads the configuration of slew rate limiter of selected Tx channel +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannel Enum to select Tx Channel. +* \param slewRateLimiterCfg Pointer to memory location where the configuration read back value will be written +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_SrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_SlewRateLimiterCfg_t* slewRateLimiterCfg); + +/** +* \brief This function sets the configuration of slew rate limiter for tx channels +* selected within the configuration struct (txChannelMask) +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param timerMicroSec SRL ramp timer in microseconds. Min is 80 us and max is 5000000 us (5 seconds). +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_SrlRampTimerSet(adi_adrv9025_Device_t* device, + uint32_t timerMicroSec); + +/** +* \brief This function reads the slew rate limiter ramp timer value. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param timerMicroSec Pointer to memory location where the ramp timer read back value will be written +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_SrlRampTimerGet(adi_adrv9025_Device_t* device, + uint32_t* timerMicroSec); + +/** +* \brief This function enables/disables ramp-down of Tx power in case of a PLL unlock or +* Dfrm IRQ(0-1) or PA protection events(Average/Peak Power Errors and SRL errors). +* +* There are 10 different events that can trigger Tx power ramp-down. +* Each Tx Channel(1-4) has independent ramp-down configurations. Prior to enabling ramp down +* for Deframer interrupts, user should enable the deframer links. Deframer interrupts should also be +* enabled by using adi_adrv9025_DfrmIrqMaskSet API. +* A powered down PLL will be seen as an unlocked PLL by the device, hence ramping should be enabled +* only for PLL's that are enabled. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannelMask Mask to select one or more Tx channels from adi_adrv9025_TxChannels_e. +* \param irqMask Mask to select one or more events to be enabled/disabled. +* Bit | Description +* -------------|----------------------------------------------------------------------------- +* [8-31] | Unused +* [7] | PA PROTECTION ERROR - This bit enables/disables Tx power ramp down on Average/Peak power errors and Slew Rate Limiter Errors(SRL IRQ should be enabled) +* [6] | SERDES PLL UNLOCK +* [5] | RF2 PLL UNLOCK +* [4] | RF1 PLL UNLOCK +* [3] | AUX PLL UNLOCK +* [2] | CLK PLL UNLOCK +* [1] | Deframer Irq - 1 +* [0] | Deframer Irq - 0 +* +* \param enable Byte to enable/disable ramp-down for selected events 0:Disable Other:Enable +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PaPllDfrmEventRampDownEnableSet(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + uint32_t irqMask, + uint8_t enable); + +/** +* \brief This function enables/disables ramp-down of Tx power. The user can set SRL Mode 4 then +* call this function. +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannelMask Mask to select one or more Tx channels from adi_adrv9025_TxChannels_e. +* \param enable Byte to enable/disable ramp-down for selected events 0:Disable Other:Enable +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PaProtectionRampDownEnableSet(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + uint8_t enable); + +/** +* \brief This function to read pa protection ramp-down enable bit. +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannelSelect Enum to select Tx channel to read pa protection ramp-down enable bit. +* \param enable Pointer to byte to read pa protection ramp-down enable bit. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PaProtectionRampDownEnableGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannelSelect, + uint8_t* enable); + +/** +* \brief This function enables/disables ramp-up of Tx power. The user can set SRL Mode 4 then +* call this function. +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannelMask Mask to select one or more Tx channels from adi_adrv9025_TxChannels_e. +* \param enable Byte to enable/disable ramp-up for selected events 0:Disable Other:Enable +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PaProtectionRampUpEnableSet(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + uint8_t enable); + +/** +* \brief This function to read pa protection ramp-up enable bit. +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannelSelect Enum to select Tx channel to read pa protection ramp-up enable bit. +* \param enable Pointer to byte to read pa protection ramp-up enable bit. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PaProtectionRampUpEnableGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannelSelect, + uint8_t* enable); + +/** +* \brief This function reads the status of Tx power ramp-down functionality for PLL Unlock +* and Dfrm IRQ(0-1) and PA protection events(Average/Peak Power Errors and SRL errors). +* +* There are 10 different events that can trigger Tx power ramp-down. +* Each Tx Channel(1-4) has independent ramp-down configurations. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannelSelect Enum to select Tx channels to read power ramp-down enabled status. +* \param irqSelect Enum to select the event to read power ramp-down enabled status. +* \param enable Pointer to byte to read power ramp-down enabled status. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PaPllDfrmEventRampDownEnableGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannelSelect, + adi_adrv9025_PaPllDfrmRampDownEnSel_e irqSelect, + uint8_t* enable); + +/** +* \brief This function reads the status of events causing Tx power ramp down +* +* Each Tx Channel(1-4) has independent ramp-down event status bits. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannelSelect Enum to select Tx channels to read event bits +* \param eventBits +* Bit | Description +* -------------|----------------------------------------------------------------------------- +* [3-7] | Unused +* [2] | Pll Unlock / Dfrm Error (B0 Only) +* [1] | Pa Protection Peak Power Error +* [0] | Pa Protection Average Power Error +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PaPllDfrmEventGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannelSelect, + uint8_t* eventBits); + +/** +* \brief This function will clear the sticky bits of selected events causing Tx power ramp down +* +* Each Tx Channel(1-4) has independent ramp-down event sticky bits. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannelSelect Enum to select Tx channels to clear sticky event bits +* \param eventBits +* Bit | Description +* -------------|----------------------------------------------------------------------------- +* [3-7] | Unused +* [2] | Pll Unlock / Dfrm Error Sticky Bit (B0 Only) +* [1] | Pa Protection Peak Power Error Sticky Bit +* [0] | Pa Protection Average Power Error Sticky Bit + +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PaPllDfrmEventClear(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannelSelect, + uint8_t eventBits); + +/** +* \brief This function configures Tx attenuation ramp up sticky mode for selected Tx channel. If +* an event is configured as non-sticky, Tx power will ramp up automatically once the error is +* recovered. To allow ramp-up in case of jesd events, user should manually clear the interrupt with +* adi_adrv9025_DfrmIrqSourceReset API, even if Pll/Jesd event is non-sticky. +* If an event is configured as sticky, user should use adi_adrv9025_PaPllDfrmEventClear API to clear +* the error and to allow ramp-up. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param channelMask Tx channel selection to enable Tx attenuation ramp up and sticky mode +* \param txPllJesdProtClrReqd Clear required for pll and jesd gain ramp down events 0-disable, 1-enable. This bit +* should always be 1 +* \param txPaProtectionAvgpowerErrorClearRequired PA Protection avg power error clearing required 0-disable, 1-enable +* \param txPaProtectionPeakpowerErrorClearRequired PA Protection peak power error clearing required 0-disable, 1-enable +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenuationRampUpStickyModeEnable(adi_adrv9025_Device_t* device, + uint32_t channelMask, + uint8_t txPllJesdProtClrReqd, + uint8_t txPaProtectionAvgpowerErrorClearRequired, + uint8_t txPaProtectionPeakpowerErrorClearRequired); + +/** +* \brief This function configures Tx NCO for two modes of operation. +* 1- Inject a tone at the specified frequency and gain. +* 2- Mix the signal up or down the band by the specified frequency amount. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param shifterCfg Tx NCO configuration container +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxNcoShifterSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxNcoShifterCfg_t shifterCfg); + +/** +* \brief This function retrieves the Tx NCO configuration for the specified Tx Channel. +* Note: The Tx Channel is specified by setting the txChannelMask member of the adi_adrv9025_TxNcoShifterCfg_t +* structure, whose pointer is passed to the function, with bitmask of the desired channel to get. This txChannelMask +* member is over written by the value of the actual txChannel from which the returned configuration was read. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param shifterCfg Pointer to Tx NCO configuration container +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxNcoShifterGet(adi_adrv9025_Device_t *device, + adi_adrv9025_TxNcoShifterCfg_t *shifterCfg); + +/** +* \brief This function is to set the Tx Analog Attenuation Early Delay Counter. +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannelMask Mask to select one or more Tx channels from adi_adrv9025_TxChannels_e. +* \param delayValue Byte value of delay counter. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAnalogAttenEarlyDelaySet(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + uint8_t delayValue); + +/** +* \brief This function to read the Tx Analog Attenuation Early Delay Counter. +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param txChannelSelect Enum to select Tx channel to read pa protection ramp-down enable bit. +* \param delayValue Pointer to byte to read value of delay counter. +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAnalogAttenEarlyDelayGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannelSelect, + uint8_t* delayValue); + +/**************************************************************************** +* Helper functions +**************************************************************************** +*/ + +/**************************************************************************** +* Debug functions +**************************************************************************** +*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_TX_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_tx_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_tx_types.h new file mode 100644 index 0000000..62ae3d8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_tx_types.h @@ -0,0 +1,455 @@ +/** +* \file adi_adrv9025_tx_types.h +* \brief Contains ADRV9025 API Tx datapath data types +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_TX_TYPES_H_ +#define _ADI_ADRV9025_TX_TYPES_H_ + +#include "adi_adrv9025_gpio_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define ADRV9025_TX_ATTEN_TABLE_MAX 960 +#define ADRV9025_TX_ATTEN_VALUE_MAX_MDB 41950 /*!< Maximum Value of TX Attenuation in mDb */ + +#define ADRV9025_ADDR_TX1_ATTEN_TABLE 0xA2000000 +#define ADRV9025_ADDR_TX2_ATTEN_TABLE 0xAA000000 +#define ADRV9025_ADDR_TX3_ATTEN_TABLE 0xB2000000 +#define ADRV9025_ADDR_TX4_ATTEN_TABLE 0xBA000000 + +#define ADRV9025_TX_ATTEN_TABLE_HP_MASK 0x0003F000 +#define ADRV9025_TX_ATTEN_TABLE_HP_SHIFT 12 +#define ADRV9025_TX_ATTEN_TABLE_MULT_MASK 0x00000FFF +#define ADRV9025_TX_ATTEN_TABLE_MULT_SHIFT 0 +#define ADRV9025_NUMBER_OF_TX_CHANNELS 4 + +/** +* \brief Enum of possible Tx channel enables +*/ +typedef enum adi_adrv9025_TxChannels +{ + ADI_ADRV9025_TXOFF = 0, + /*!< No Tx channels are enabled */ + ADI_ADRV9025_TX1 = 1, + /*!< Tx0 channel enabled */ + ADI_ADRV9025_TX2 = 2, + /*!< Tx1 channel enabled */ + ADI_ADRV9025_TX3 = 4, + /*!< Tx2 channel enabled */ + ADI_ADRV9025_TX4 = 8, + /*!< Tx3 channel enabled */ + ADI_ADRV9025_TXALL = 0x0F /*!< All tx channel mask */ +} adi_adrv9025_TxChannels_e; + +/** +* \brief Enum to set the Tx Atenuation step size +*/ +typedef enum adi_adrv9025_TxAttenStepSize +{ + ADI_ADRV9025_TXATTEN_0P05_DB = 0, + /*!< Tx attenuation 0.05dB step size */ + ADI_ADRV9025_TXATTEN_0P1_DB = 1, + /*!< Tx attenuation 0.1dB step size */ + ADI_ADRV9025_TXATTEN_0P2_DB = 2, + /*!< Tx attenuation 0.2dB step size */ + ADI_ADRV9025_TXATTEN_0P4_DB = 3 /*!< Tx attenuation 0.4dB step size */ +} adi_adrv9025_TxAttenStepSize_e; + +/** +* \brief Enum for the different attenuation mode +*/ +typedef enum adi_adrv9025_TxAttenMode +{ + ADI_ADRV9025_TXATTEN_BYPASS_MODE = 0, + /*!< Tx attenuation mode Bypass: zero total attenuation */ + ADI_ADRV9025_TXATTEN_SPI_MODE = 1, + /*!< Tx attenuation mode set by 10-bit attenuation index used to determine total attenuation */ + ADI_ADRV9025_TXATTEN_GPIO_MODE = 3, + /*!< Tx attenuation is control with GPIO Incr/Decr: total attenuation is altered incrementally using pin control */ + ADI_ADRV9025_TXATTEN_SPI2_MODE = 4 /*!< Tx attenuation control is done over Spi2 interface */ +} adi_adrv9025_TxAttenMode_e; + +/** + * \brief Enum of possible Tx DAC FS boost options + */ +typedef enum adi_adrv9025_DacFullScale +{ + ADI_ADRV9025_TX_DACFS_0DB = 0x0, + /*!< No Full Scale Boost */ + ADI_ADRV9025_TX_DACFS_3DB = 0x01 /*!< Full scale boost = 3dB */ +} adi_adrv9025_DacFullScale_e; + +/** +* \brief Enumerated list of options to disable Tx data when PLL unlocks +*/ +typedef enum adi_adrv9025_TxDataIfUnlock +{ + ADI_ADRV9025_TXUNLOCK_TX_NOT_DISABLED = 0x0, + /*!< Tx data is not disabled when unlock event */ + ADI_ADRV9025_TXUNLOCK_TX_RAMP_TO_MAX_ATTEN = 0x1 /*!< Tx data is ramped down to zero when unlock event */ +} adi_adrv9025_TxDataIfUnlock_e; + +/** +* \brief Enumerated list of test tone Gains +*/ +typedef enum adi_adrv9025_TxNcoGain +{ + ADI_ADRV9025_TX_NCO_NEG18_DB = 0, + /*!< Nco gain -18 dB */ + ADI_ADRV9025_TX_NCO_NEG12_DB = 1, + /*!< Nco gain -12 dB */ + ADI_ADRV9025_TX_NCO_NEG6_DB = 2, + /*!< Nco gain -6 dB */ + ADI_ADRV9025_TX_NCO_0_DB = 3 /*!< Nco gain 0 dB */ +} adi_adrv9025_TxNcoGain_e; + +/* +* \brief Enum to select Ramp Step Size and Ramp Step Duration +* +* tdd ramp Step/ | Corresponding Step/ +* Duration [4 bits] | Duration in dB +* ----------------------|---------------------------- +* 0 | 0.5 +* 1 | 1.0 +* 2 | 1.5 +* 3 | 2.0 +* 4 | 2.5 +* 5 | 3.0 +* 6 | 3.5 +* 7 | 4.0 +* 8 | 4.5 +* 9 | 5.0 +* 10 | 5.5 +* 11 | 6.0 +* +*/ +typedef enum adi_adrv9025_TxRampStepSize +{ + ADI_ADRV9025_TXRAMP_0P5_DB = 0x00, + ADI_ADRV9025_TXRAMP_1P0_DB, + ADI_ADRV9025_TXRAMP_1P5_DB, + ADI_ADRV9025_TXRAMP_2P0_DB, + ADI_ADRV9025_TXRAMP_2P5_DB, + ADI_ADRV9025_TXRAMP_3P0_DB, + ADI_ADRV9025_TXRAMP_3P5_DB, + ADI_ADRV9025_TXRAMP_4P0_DB, + ADI_ADRV9025_TXRAMP_4P5_DB, + ADI_ADRV9025_TXRAMP_5P0_DB, + ADI_ADRV9025_TXRAMP_5P5_DB, + ADI_ADRV9025_TXRAMP_6P0_DB +} adi_adrv9025_TxRamp_e; + +/** +* \brief Enum select Error flags to be cleared +*/ +typedef enum adi_adrv9025_TxPaProtectErrFlags +{ + ADI_ADRV9025_TXPA_PROTECT_FLAGS_AVG_POWER_ERR = 1, + ADI_ADRV9025_TXPA_PROTECT_FLAGS_PEAK_POWER_ERR = 2, + ADI_ADRV9025_TXPA_PROTECT_FLAGS_ALL = 3 +} adi_adrv9025_TxPaProtectErrFlags_e; + +/** +* \brief Enum to select event for Tx power ramp-down enable/disable feature +*/ +typedef enum adi_adrv9025_PaPllDfrmRampDownEnSel +{ + ADI_ADRV9025_RAMP_DOWN_ON_DFRMIRQ0 = 0x0001, + ADI_ADRV9025_RAMP_DOWN_ON_DFRMIRQ1 = 0x0002, + ADI_ADRV9025_RAMP_DOWN_ON_CLKPLLUNLOCK = 0x0004, + ADI_ADRV9025_RAMP_DOWN_ON_AUXPLLUNLOCK = 0x0008, + ADI_ADRV9025_RAMP_DOWN_ON_RF1PLLUNLOCK = 0x0010, + ADI_ADRV9025_RAMP_DOWN_ON_RF2PLLUNLOCK = 0x0020, + ADI_ADRV9025_RAMP_DOWN_ON_SERDESPLLUNLOCK = 0x0040, + ADI_ADRV9025_RAMP_DOWN_ON_PA_PROT_ERROR = 0x0080 +} adi_adrv9025_PaPllDfrmRampDownEnSel_e; + +/** +* \brief Enum to select event for Tx power ramp-down enable/disable feature +*/ +typedef enum adi_adrv9025_PaPllDfrmRampDownErrSel +{ + ADI_ADRV9025_AVGPOWER_ERR = 0x0001, + ADI_ADRV9025_PEAKPOWER_ERR = 0x0002, + ADI_ADRV9025_PLLDFRM_ERR = 0x0004 +} adi_adrv9025_PaPllDfrmRampDownErrSel_e; + +/** +* \brief Enum select for slew rate limiter operation mode +*/ +typedef enum adi_adrv9025_SrlModeSel +{ + ADI_ADRV9025_SRL_DISABLED = 0x0000, + /*!< Slew rate limiter is disabled */ + ADI_ADRV9025_SRL_BASIC = 0x0001, + /*!< Slew rate limiter is enabled, but it just limits slew and doesn't do any ramping */ + ADI_ADRV9025_SRL_RAMP_DOWN = 0x0002, + /*!< Slew rate limiter is enabled, it limits slew and ramps down Tx power when a violation is detected */ + ADI_ADRV9025_SRL_RAMP_DOWN_WITH_BBIC_INTERRUPT = 0x0003 + /*!< In addition to RAMP_DOWN mode, FW sends a BBIC interrupt. BBIC should manually ramp-up Tx power after recovery */ +} adi_adrv9025_SrlModeSel_e; + +/** +* \brief Enum select for slew rate table +*/ +typedef enum adi_adrv9025_SrlTableSel +{ + ADI_ADRV9025_SRL_TABLE0 = 0x0000, + /*!< Slew limit is %10 of full scale */ + ADI_ADRV9025_SRL_TABLE1 = 0x0001, + /*!< Slew limit is %20 of full scale */ + ADI_ADRV9025_SRL_TABLE2 = 0x0002, + /*!< Slew limit is %30 of full scale */ + ADI_ADRV9025_SRL_TABLE3 = 0x0003 /*!< Slew limit is %50 of full scale */ +} adi_adrv9025_SrlTableSel_e; + +/** +* \brief Enum select for Tx attenuation simultaneous update +*/ +typedef enum adi_adrv9025_TxAttenSimultaneousUpdate +{ + ADI_ADRV9025_TXATTEN_SIMULTAN_UPDATE_DISABLED = 0x0000, + /*!< Simultaneous Update Disabled */ + ADI_ADRV9025_TXATTEN_SIMULTAN_UPDATE_SPI = 0x0001, + /*!< Simultaneous Update with SPI writes */ + ADI_ADRV9025_TXATTEN_SIMULTAN_UPDATE_GPIO = 0x0002 /*!< Simultaneous Update with GPIO pins */ +} adi_adrv9025_TxAttenSimultaneousUpdate_e; + +/** +* \brief Enum select for pa protection input +*/ +typedef enum adi_adrv9025_PaProtectionInputSel +{ + ADI_ADRV9025_COMPLEX_MULT_OUTPUT = 0x0000, + /*!< Input data to Pa protection block is probed from complex mult output */ + ADI_ADRV9025_TXQEC_ACTUATOR_OUTPUT = 0x0001 /*!< Input data to Pa protection block is probed from tx qec actuator output */ +} adi_adrv9025_PaProtectionInputSel_e; + +/** +* \brief Enum values representing bitmasks for Tx Ramp Down Events +*/ +typedef enum adi_adrv9025_InitTxRampDownEvents +{ + ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_DFRMIRQ0 = 0x0001, + /*!< During device initialization, mask(disable) Tx ramp down on Jesd deframer Irq 0 event */ + ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_DFRMIRQ1 = 0x0002, + /*!< During device initialization, mask(disable) Tx ramp down on Jesd deframer Irq 1 event*/ + ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_RF1PLLUNLOCK = 0x0004, + /*!< During device initialization, mask(disable) Tx ramp down on RF1 PLL Unlock */ + ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_RF2PLLUNLOCK = 0x0008, + /*!< During device initialization, mask(disable) Tx ramp down on RF2 PLL Unlock */ + ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_SERDESPLLUNLOCK = 0x0010, + /*!< During device initialization, mask(disable) Tx ramp down on Serdes PLL Unlock */ + ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_CLKPLLUNLOCK = 0x0020, + /*!< During device initialization, mask(disable) Tx ramp down on Clk PLL Unlock */ + ADI_ADRV9025_TX_RAMP_DOWN_AUTOSELECT = 0x0080 + /*!< During device initialization, automatically decide the events for which Tx ramp down enabled. This bitmask will ignore + the status of other bits. In auto mode, Tx ramp down will be enabled for active Jesd deframer/s and LO source/s (RF1/RF2 PLL) of Tx channels + Tx ramp down on Serdes Pll(if its being used) and Clk Pll unlock events will be enabled */ +} adi_adrv9025_InitTxRampDownEvents_e; + +/** +* \brief Enum values representing possible Tx NCO shifter operation modes +*/ +typedef enum adi_adrv9025_TxNcoShifterMode +{ + ADI_ADRV9025_TXNCO_INJECT = 0x0000, + /*!< Injects a single tone at the specified shift frequency at the specified gain */ + ADI_ADRV9025_TXNCO_MIX = 0x0001 + /*!< Mixes the data signal by the specified shift frequency up or down the band */ +} adi_adrv9025_TxNcoShifterMode_e; + +/** +* \brief Enum values representing possible Tx NCO shifter Tone Injection Gain +*/ +typedef enum adi_adrv9025_TxNcoToneGain +{ + ADI_ADRV9025_TXNCO_GAIN_0dB = 3, + /*!< Injects a single tone at the specified shift frequency at the 0dB gain */ + ADI_ADRV9025_TXNCO_GAIN_minus6dB = 2, + /*!< Injects a single tone at the specified shift frequency at the -6dB gain */ + ADI_ADRV9025_TXNCO_GAIN_minus12dB = 1, + /*!< Injects a single tone at the specified shift frequency at the -12dB gain */ + ADI_ADRV9025_TXNCO_GAIN_minus18dB = 0 + /*!< Injects a single tone at the specified shift frequency at the -18dB gain */ +} adi_adrv9025_TxNcoToneGain_e; + +/** +* \brief Data structure to hold ADRV9025 Tx PA Protection configuration settings +*/ +typedef struct adi_adrv9025_TxPaProtectCfg +{ + adi_adrv9025_TxChannels_e txChannel; /*!< Tx Channel to be configered */ + uint8_t avgDuration; /*!< PA Protection Average Power Measurement Duration. */ + uint8_t peakDuration; /*!< PA Protection Peak Power Measurement Duration */ + uint8_t txAttenStep; + /*!< PA Protection Attenuation gain step. Gain step down is not allowed for Tokelau device. This field is not being used actively. */ + uint8_t gainStepDownEn; + /*!< PA Protection Gain Step Down Enable. Gain step down is not allowed for Tokelau device. This field is not being used actively.*/ + uint16_t powerThreshold; /*!< PA Protection Average Power Threshold. */ + uint8_t peakCount; /*!< Peak Count Causing PA Error. */ + uint16_t peakThreshold; /*!< PA Protection Peak Power Threshold. Max value for Silicon A: 255 Max Value for Silicon B: 8191 */ + uint8_t rampStepDuration; + /*!< PA Protection Ramp Step duration. This field is not being used actively. It is set to a hardcoded value by PaPllDfrmEventRampDownEnableSet API */ + uint8_t rampStepSize; + /*!< PA Protection Ramp Step Size. This field is not being used actively. It is set to a hardcoded value by PaPllDfrmEventRampDownEnableSet API */ + uint8_t rampMaxAtten; + /*!< PA Protection Ramp Max Attenuation. This field is not being used actively. It is set to a hardcoded value by PaPllDfrmEventRampDownEnableSet API */ + uint8_t avgPowerEnable; + /*!< This enables average power measurement block. If enabled, PA error is flagged when average power measurement is above average power threshold */ + uint8_t peakPowerEnable; + /*!< This enables peak power measurement block. If enabled, PA error is flagged when peak power count is above peak count threshold */ + adi_adrv9025_PaProtectionInputSel_e inputSel; /*!< This selects the source of input signal for Pa protection block */ + uint8_t avgPeakRatioEnable; + /*!< This enables average to peak power ratio calculation block, both avgPower and peakPower calculations must be enabled before enabling ratio calculation */ +} adi_adrv9025_TxPaProtectCfg_t; + +/** +* \brief Data structure to readback errors realated to power +*/ +typedef struct adi_adrv9025_TxPaProtectionErr +{ + uint8_t peakPowerErr; /*!< PA Protection Peak Power Error. + Sticky. When set, disables power calculations unless "error_clear_required" bit is clear */ + uint8_t avgPowerErr; /*!< PA Protection Average Power Error. + Sticky. When set, disables power calculations unless "error_clear_required" bit is clear.*/ + uint16_t powerErr; /*!< PA Protection Error Power. Updated when average power error occurs. */ +} adi_adrv9025_TxPaProtectionErr_t; + +/** +* \brief Data structure to hold ADRV9025 Tx PA Protection current status values +*/ +typedef struct adi_adrv9025_TxPaProtectStatus +{ + uint16_t avgPower; /*!< PA protection power for readback. */ + uint16_t avgPeakRatio; /*!< Average to Peak power ratio for readback. */ + uint16_t avgErrorPower; /*!< Value of average power when average power Pa protection error is triggered */ +} adi_adrv9025_TxPaProtectStatus_t; + +/** + * \brief Configuration structure for Tx power control + */ +typedef struct adi_adrv9025_TxAttenSimultUpdateCfg +{ + adi_adrv9025_GpioPinSel_e gpioUpdatePin; + /*!< Gpio Pin selection to trigger Tx attenutaion simultaneous update, select INVALID when simultaneous update with GPIO is disabled */ + adi_adrv9025_TxAttenSimultaneousUpdate_e simultaneousUpdate; /*!< Tx attenuation simultaneous update mode selection */ +} adi_adrv9025_TxAttenSimultUpdateCfg_t; + +/** +* \brief Data structure to hold ADRV9025 Tx Attenuation Pin Control Configuration +*/ +typedef struct adi_adrv9025_TxAttenPinCfg +{ + uint32_t txChannelMask; /*!< One or multiple Tx channel selection. */ + uint8_t stepSize; /*!< The step that will increase or decrease the channel attenuation. This parameter sets the + change in Tx attenuation for each increment or decrement signal received in incr/decr mode. + Step of 1 changes attenuation by 0.05dB. Valid range is from 0 to 31 */ + adi_adrv9025_GpioPinSel_e txAttenIncPin; /*!< GPIO used to increment Tx attenuation - GPIO00-GPIO15 */ + adi_adrv9025_GpioPinSel_e txAttenDecPin; /*!< GPIO used to decrement Tx attenuation - GPIO00-GPIO15 */ +} adi_adrv9025_TxAttenPinCfg_t; + +/** +* \brief Configuration structure for Tx power control +*/ +typedef struct adi_adrv9025_TxAttenCfg +{ + uint32_t txChannelMask; + adi_adrv9025_TxAttenStepSize_e txAttenStepSize; /*!< Tx Attenuation step size */ + adi_adrv9025_TxDataIfUnlock_e disTxDataIfPllUnlock; + /*!< Option to disable transmit data when a PLL unlocks. Note: This field is not being used actively. + If user enables at least one pll unlock event with adi_adrv9025_PaPllDfrmEventRampDownEnableSet, + gain ramp down on pll unlock is automatically enabled */ + adi_adrv9025_TxDataIfUnlock_e rampJesdDfrm; + /*!< Ramp up attenuation when a deframer link unlocks. Note: This field is not being used actively. + If user enables at least one dfrm event with adi_adrv9025_PaPllDfrmEventRampDownEnableSet, + gain ramp down on dfrm event is automatically enabled */ + adi_adrv9025_TxAttenMode_e attenMode; /*!< */ + adi_adrv9025_DacFullScale_e dacFullScale; + /*!< Tx Dac full scale Setting. WARNING: This field is not being used actively, left for backward compatibility*/ + adi_adrv9025_TxAttenSimultUpdateCfg_t simultaneousUpdateCfg; + /*!< Tx Attenuation Simultaneous Update Configuration, it is only used when attenMode is selected as SPI */ + adi_adrv9025_TxAttenPinCfg_t gpioModePinCfg; /*!< Tx Attenuation GPIO mode pin configuration, it is only used when attenMode is selected as GPIO */ +} adi_adrv9025_TxAttenCfg_t; + +/** +* \brief Data structure to hold a adrv9025 device Tx attenuation calls +*/ +typedef struct adi_adrv9025_TxAtten +{ + uint32_t txChannelMask; + uint16_t txAttenuation_mdB; +} adi_adrv9025_TxAtten_t; + +/** + * \brief Data structure to hold ADRV9025 Tx NCO test tone Configuration + */ +typedef struct adi_adrv9025_TxTestToneCfg +{ + uint8_t txChannelMask; + uint8_t enable; /*!< 0 = Disable Tx NCO, 1 = Enable Tx NCO on both transmitters */ + int32_t txToneFreq_Hz; /*!< Signed frequency in Hz of the desired Tx tone */ + adi_adrv9025_TxNcoGain_e txToneGain; /*< NCO tone gain given by the enum adi_adrv9025_TxNcoGain_e */ +} adi_adrv9025_TxTestToneCfg_t; + +/** +* \brief Data structure to hold an adrv9025 device Tx attenuation Table Row +* (Single row of a complete table) +*/ +typedef struct adi_adrv9025_TxAttenTableRow +{ + uint16_t txAttenMult; + uint8_t txAttenHp; + uint8_t Reserve; +} adi_adrv9025_TxAttenTableRow_t; + +/** +* \brief Data structure to hold ADRV9025 Tx Attenuation Spi2 Pin Control Configuration +*/ +typedef struct adi_adrv9025_TxAttenSpi2PinCfg +{ + uint32_t txChannelMask; + adi_adrv9025_Spi2TxAttenGpioSel_e txAttenSpi2Pin; +} adi_adrv9025_TxAttenSpi2PinCfg_t; + +/** +* \brief Data structure to hold ADRV9025 Tx Slew Rate Limiter Configuration +*/ +typedef struct adi_adrv9025_SlewRateLimiterCfg_t +{ + uint32_t txChannelMask; + adi_adrv9025_SrlModeSel_e modeSel; /*!< Slew rate limiter mode selection; DISABLED/BASIC/RAMPDOWN/RAMPDOWNWITHBBICINTERRUPT */ + adi_adrv9025_SrlTableSel_e tableSel; /*!< Table selection for slew rate limit; %10 / %20 / %30 / %50 of full scale */ + uint8_t srlOffset; + /*!< Slew rate threshold to trigger limiter. (0 = straight table, 1 = 15/16 -- 1.0, 2 = 15/16 and 14/16 -- 1.0, etc.) */ +} adi_adrv9025_SlewRateLimiterCfg_t; + +/** +* \brief Data structure to hold ADRV9025 Tx NCO Shifter Configuration +*/ +typedef struct adi_adrv9025_TxNcoShifterCfg +{ + uint32_t txChannelMask; /*!< Tx Channel to which the configuration is applied */ + adi_adrv9025_TxNcoShifterMode_e shifterMode; /*!< Tx NCO operation mode 0 - inject tone, 1 - mix band frequency */ + int32_t shiftFrequency_kHz; /*!< Frequency at which to inject tone or frequency to shift signal up/down band */ + adi_adrv9025_TxNcoToneGain_e shiftGain; /*!< Gain to apply to injected tone */ + uint8_t enable; /*!< flag indicating if the NCO is enabled = 1 or disabled = 0 */ +} adi_adrv9025_TxNcoShifterCfg_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_TX_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_types.h new file mode 100644 index 0000000..5d25ad9 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_types.h @@ -0,0 +1,535 @@ +/*! +* \file adi_adrv9025_types.h +* \brief Contains ADRV9025 API configuration and run-time type definitions +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_ADRV9025_TYPES_H_ +#define _ADI_ADRV9025_TYPES_H_ + +#include +#include "adi_adrv9025_tx_types.h" +#include "adi_adrv9025_rx_types.h" +#include "adi_adrv9025_cpu_types.h" +#include "adi_adrv9025_data_interface_types.h" +#include "adi_common.h" +#include "../../private/include/adrv9025_shared_resource_manager_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define PRIVATE_TYPE_9025 adrv9025_SharedResourcePool_t + +#define ADI_ADRV9025_TX_PROFILE_VALID 0x01 +#define ADI_ADRV9025_RX_PROFILE_VALID 0x02 +#define ADI_ADRV9025_ORX_PROFILE_VALID 0x04 +#define ADI_ADRV9025_LB_PROFILE_VALID 0x08 + +#define ADI_ADRV9025_MAX_TXCHANNELS 4 +#define ADI_ADRV9025_MAX_RXCHANNELS 10 +#define ADI_ADRV9025_MAX_RX_ONLY 4 +#define ADI_ADRV9025_MAX_ORX_ONLY 4 +#define ADI_ADRV9025_MAX_LB_CHANNEL_START 8 +#define ADI_ADRV9025_MAX_LB_CHANNEL_END 9 +#define ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET 12 +#define ADI_ADRV9025_MAX_TX_CHANNEL_START 0 +#define ADI_ADRV9025_MAX_TX_CHANNEL_END 3 +#define ADI_ADRV9025_MAX_RX_CHANNEL_START 0 +#define ADI_ADRV9025_MAX_RX_CHANNEL_END 3 +#define ADI_ADRV9025_MAX_ORX_CHANNEL_START 4 +#define ADI_ADRV9025_MAX_ORX_CHANNEL_END 7 + +#define ADI_ADRV9025_NUM_FRAMERS 3 +#define ADI_ADRV9025_NUM_DEFRAMERS 2 + +#define ADI_ADRV9025_MAX_RXPFIR_COEFS 72 +#define ADI_ADRV9025_MAX_TXPFIR_COEFS 80 +#define ADI_ADRV9025_RXADC_COEFS 41 + +#define ADI_ADRV9025_MAX_SERDES_LANES 4u /* Number of lanes in serializer and deserializer */ + +#define ADI_ADRV9025_MAX_AUXDACS 8U + +/** + * \brief Data structure to hold ADRV9025 API State + */ +typedef enum adi_adrv9025_ApiStates +{ + ADI_ADRV9025_STATE_POWERONRESET = 0x00, + ADI_ADRV9025_STATE_INITIALIZED = 0x01, + ADI_ADRV9025_STATE_STREAMLOADED = 0x02, + ADI_ADRV9025_STATE_CPUDEBUGLOADED = 0x04, + ADI_ADRV9025_STATE_CPULOADED = 0x08, + ADI_ADRV9025_STATE_INITCALS_RUN = 0x10, + ADI_ADRV9025_STATE_RADIOON = 0x20 +} adi_adrv9025_ApiStates_e; + +/** + * \brief Enumerated list of CMOS pads drive strength options for SPI_DO signal + */ +typedef enum adi_adrv9025_CmosPadDrvStr +{ + ADI_ADRV9025_CMOSPAD_DRV_WEAK = 0, /*!< 5pF load @ 75MHz */ + ADI_ADRV9025_CMOSPAD_DRV_STRONG = 1 /*!< 100pF load @ 20MHz */ +} adi_adrv9025_CmosPadDrvStr_e; + +/** +* \brief Enumerated list of options to use to set the LO source for the Rx/Tx and ORx mixers. +*/ +typedef enum adi_adrv9025_LoSel +{ + ADI_ADRV9025_LOSEL_LO1 = 1, + ADI_ADRV9025_LOSEL_LO2 = 2, + ADI_ADRV9025_LOSEL_AUXLO = 3 +} adi_adrv9025_LoSel_e; + +/** +* \brief Enumerated list of options to use to set the LO source for the ORx mixers. +*/ +typedef enum adi_adrv9025_OrxLoSel +{ + ADI_ADRV9025_ORXLOSEL_TXLO = 1, + ADI_ADRV9025_ORXLOSEL_AUXLO = 2 +} adi_adrv9025_OrxLoSel_e; + +/** +* \brief Enumerated list of options to use to set the ADRV9025 PLL Output and Input modes. +*/ +typedef enum adi_adrv9025_PllLoMode +{ + ADI_ADRV9025_INTLO_NOOUTPUT = 0, /*!< Use internal RFPLL LO frequency, do not output from ADRV9025 */ + ADI_ADRV9025_INTLO_OUTPUT = 1, /*!< Internal RFPLL LO frequency will output from ADR9025 */ + ADI_ADRV9025_EXTLO_2X_INPUT = 2, /*!< Provided external LO will be divided by 2 in ADRV9025 to generate the LO frequency */ + ADI_ADRV9025_EXTLO_4X_INPUT = 3, /*!< Provided external LO will be divided by 4 in ADRV9025 to generate the LO frequency */ + ADI_ADRV9025_EXTLO_8X_INPUT = 4 /*!< Provided external LO will be divided by 8 in ADRV9025 to generate the LO frequency */ +} adi_adrv9025_PllLoMode_e; + +/** + * \brief Enumerated list of RFPLL phase synchronization modes + * + * RFPLL Phase sync requires extra time to sync each time the RFPLL frequency + * is changed. If RFPLL phase sync is not required, it may be desired to + * disable the feature to allow the RFPLL to lock faster. + * + * Depending on the desired accuracy of the RFPLL phase sync, several options + * are provided. + */ +typedef enum adi_adrv9025_RfPllMcs +{ + ADI_ADRV9025_RFPLLMCS_NOSYNC = 0, /*!< Disable RFPLL phase synchronization */ + ADI_ADRV9025_RFPLLMCS_INIT_AND_SYNC = 1, /*!< Enable RFPLL phase sync init only */ + ADI_ADRV9025_RFPLLMCS_INIT_AND_CONTTRACK = 2 /*!< Enable RFPLL phase sync init and track continuously */ +} adi_adrv9025_RfPllMcs_e; + +/** +* \brief Enum to select the proper gain for the FIR +*/ +typedef enum adi_adrv9025_FirGain +{ + ADRV9025_FIR_GAIN_NEG12_DB = -12, /*!< ADRV9025 FIR gain -12 */ + ADRV9025_FIR_GAIN_NEG6_DB = -6, /*!< ADRV9025 FIR gain -6 */ + ADRV9025_FIR_GAIN_0_DB = 0, /*!< ADRV9025 FIR gain 0 */ + ADRV9025_FIR_GAIN_POS6_DB = 6 /*!< ADRV9025 FIR gain 6 */ +} adi_adrv9025_FirGain_e; + +/** +* \brief Data structure to hold ADRV9025 MCS Control +*/ +typedef enum adi_adrv9025_McsControl +{ + ADI_ADRV9025_MCS_NONE = 0x00, + ADI_ADRV9025_MCS_ENABLE = 0x01, + ADI_ADRV9025_MCS_JESD_ENABLE = 0x02, + ADI_ADRV9025_MCS_DIGITAL_ENABLE = 0x04, + ADI_ADRV9025_MCS_CLKGEN_ENABLE = 0x08, + ADI_ADRV9025_MCS_SDM_ENABLE = 0x10, + ADI_ADRV9025_MCS_DEVCLK_ENABLE = 0x20 +} adi_adrv9025_McsControl_e; + +/** +* \brief Enum of possible Capability Feature enables +*/ +typedef enum adi_adrv9025_Feature +{ + ADI_ADRV9025_FEATUREOFF = 0x00000000, /*!< No Capability Feature enabled */ + ADI_ADRV9025_FEATURE_RESERVED1 = 0x00000001, /*!< Reserve1 feature enabled */ + ADI_ADRV9025_FEATURE_SIP2 = 0x00000002, /*!< SPI2 feature enabled */ + ADI_ADRV9025_FEATURE_DPD = 0x00000004, /*!< DPD feature enabled */ + ADI_ADRV9025_FEATURE_CFR = 0x00000008, /*!< CFR feature enabled */ + ADI_ADRV9025_FEATURE_TXSRL = 0x00000010, /*!< Tx Slew Rate Limiter feature enabled */ + ADI_ADRV9025_FEATURE_ARMDPD = 0x00000020, /*!< ARM D with DPD enabled */ + ADI_ADRV9025_FEATURE_RESERVED2 = 0x00000040, /*!< Reserve2 feature enabled jesd compression */ + ADI_ADRV9025_FEATURE_RFLO1 = 0x00000080, /*!< RF LO1 Channel1 enable */ + ADI_ADRV9025_FEATURE_RFLO2 = 0x00000100, /*!< RF LO2 Channel1 enable */ + ADI_ADRV9025_FEATUREALL = 0x000001FF, /*!< All Capability feature enabled */ + ADI_ADRV9025_FEATUREMAX = 11 /*!< Max Capability feature */ +} adi_adrv9025_Feature_e; + +/** +* \brief Enum of possible Lane Mask enables +*/ +typedef enum adi_adrv9025_Lane_Enable +{ + ADI_ADRV9025_ALL_LANES_DISABLED = 0x00000000, /*!< Disable all lanes */ + ADI_ADRV9025_LANE0_ENABLE = 0x00000001, /*!< Enable Lane 0 */ + ADI_ADRV9025_LANE1_ENABLE = 0x00000002, /*!< Enable Lane 1 */ + ADI_ADRV9025_LANE2_ENABLE = 0x00000004, /*!< Enable Lane 2 */ + ADI_ADRV9025_LANE3_ENABLE = 0x00000008, /*!< Enable Lane 3 */ + ADI_ADRV9025_LANE4_ENABLE = 0x00000010, /*!< Enable Lane 4 */ + ADI_ADRV9025_LANE5_ENABLE = 0x00000020, /*!< Enable Lane 5 */ + ADI_ADRV9025_LANE6_ENABLE = 0x00000040, /*!< Enable Lane 6 */ + ADI_ADRV9025_LANE7_ENABLE = 0x00000080, /*!< Enable Lane 7 */ + ADI_ADRV9025_ALL_LANES_ENABLED = 0x000000FF, /*!< Enable all lanes */ + ADI_ADRV9025_MAX_NUMBER_LANES = 0x8 /*!< Maximum Number of Lanes */ +} adi_adrv9025_Lane_Enable_e; + +/** +* \brief Data structure to hold ADRV9025 API version information +*/ +typedef struct adi_adrv9025_ApiVersion +{ + uint32_t majorVer; /*!< API Major Version number */ + uint32_t minorVer; /*!< API Minor Version number */ + uint32_t maintenanceVer; /*!< API Maintenance number */ + uint32_t buildVer; /*!< API Build Version number */ +} adi_adrv9025_ApiVersion_t; + +/** + * \brief Data structure to hold ADRV9025 Rx FIR filter settings + */ +typedef struct adi_adrv9025_RxFir +{ + int8_t gain_dB; /*!< Filter gain in dB (-12dB, -6dB, 0dB, +6dB) */ + uint8_t numFirCoefs; /*!< Number of coefficients in the FIR filter */ + int16_t coefs[ADI_ADRV9025_MAX_RXPFIR_COEFS]; /*!< An array of filter coefficients */ +} adi_adrv9025_RxFir_t; + +/** + * \brief Data structure to hold ADRV9025 Tx FIR filter settings + */ +typedef struct adi_adrv9025_TxFir +{ + int8_t gain_dB; /*!< Filter gain in dB (-12dB, -6dB, 0dB, +6dB) */ + uint8_t numFirCoefs; /*!< Number of coefficients in the FIR filter */ + int16_t coefs[ADI_ADRV9025_MAX_TXPFIR_COEFS]; /*!< An array of filter coefficients */ +} adi_adrv9025_TxFir_t; + +/** + * \brief Data structure to hold ADRV9025 Tx Profile Configuration settings + */ +typedef struct adi_adrv9025_TxProfile +{ + uint32_t txInputRate_kHz; /*!< Tx input data rate in kHz */ + uint32_t primarySigBandwidth_kHz; /*!< Tx primary signal BW */ + uint32_t rfBandwidth_kHz; /*!< Tx RF passband bandwidth for the profile */ + uint32_t txDac3dBCorner_kHz; /*!< DAC filter 3dB corner in kHz */ + uint32_t txBbf3dBCorner_kHz; /*!< Tx BBF 3dB corner in kHz */ + uint8_t dpdHb1Interpolation; /*!< Tx DPD HB1 filter interpolation (1,2) */ + uint8_t dpdHb2Interpolation; /*!< Tx DPD HB2 filter interpolation (1,2) */ + uint8_t txFirInterpolation; /*!< Tx programmable FIR filter interpolation (1,2,4) */ + uint8_t thb1Interpolation; /*!< Tx Halfband1 (HB1) filter interpolation (1,2) */ + uint8_t thb2Interpolation; /*!< Tx Halfband2 (HB2) filter interpolation (1,2) */ + uint8_t thb3Interpolation; /*!< Tx Halfband3 (HB3) filter interpolation (1,2) */ + uint8_t txInt5Interpolation; /*!< Tx Int5 filter interpolation (1,5) */ + adi_adrv9025_TxFir_t txFir; /*!< Tx FIR filter structure */ + uint8_t txBbfPowerMode; /*!< Tx BBF power scaling mode selection = 0 for Maximum power. */ +} adi_adrv9025_TxProfile_t; + +/** + * \brief Data structure to hold ADRV9025 Tx Attenuation Control settings + */ +typedef struct adi_adrv9025_TxAttenControl +{ + adi_adrv9025_TxAttenStepSize_e txAttenStepSize; /*!< Tx Attenuation step size */ + uint32_t txRampDownEvents; /*!< Initial mask values for individual Tx ramp down events. Masks the event (Disable) if corresponding bit value equals to 1. + Unmasks the event (Enable) if corresponding bit value equals to 0. For bit mapping and auto mode, please see adi_adrv9025_InitTxRampDownEvents_e */ + uint32_t reserved; /*!< Reserved field */ + adi_adrv9025_TxAttenMode_e attenMode; /*!< Tx attenuation mode for init time. Init time mode selection shouldn't be either GPIO or SPI2 mode */ + adi_adrv9025_DacFullScale_e dacFullScale; /*!< Tx Dac full scale Setting. WARNING: This field is not being used actively, left for backward compatibility. It's moved to TxChannelCfg_t*/ + uint16_t txAttenInit_mdB; /*!< Initial Tx Attenuation. Note: This initial Tx attenuation value is programmed only if initial Tx attenuation mode is selected as SPI mode */ +} adi_adrv9025_TxAttenControl_t; + +/** + * \brief Data structure to hold Tx data path settings + */ +typedef struct adi_adrv9025_TxChannelCfg +{ + adi_adrv9025_TxProfile_t profile; /*!< Tx datapath profile, 3dB corner frequencies, and digital filter enables */ + adi_adrv9025_TxAttenControl_t txAttenCtrl; + adi_adrv9025_DacFullScale_e dacFullScale; /*!< Tx Dac full scale Setting*/ +} adi_adrv9025_TxChannelCfg_t; + +/** + * \brief Data structure to hold ADRV9025 Tx Channel configuration settings + */ +typedef struct adi_adrv9025_TxSettings +{ + uint32_t txInitChannelMask; /*!< Tx channel mask of which channels to initialize */ + adi_adrv9025_TxChannelCfg_t txChannelCfg[ADI_ADRV9025_MAX_TXCHANNELS]; /*!< Tx settings per Tx channel */ +} adi_adrv9025_TxSettings_t; + +/** + * \brief Data structure to hold settings for the current Rx specific use case profile + */ +typedef struct adi_adrv9025_RxProfile +{ + adi_adrv9025_RxChannels_e channelType; /*!< Channel type described by this profile (Rx/ORx/Loopback) */ + uint8_t rxFirDecimation; /*!< Rx FIR decimation (1,2,4) */ + uint8_t rxDec5Decimation; /*!< Decimation of Dec5 or Dec4 filter (5,4) */ + uint8_t rhb1Decimation; /*!< RX Halfband1 (HB1) decimation. Can be either 1 or 2 */ + uint8_t rhb1WideBandMode; /*!< 1 = HB1 is wider, 0 = HB1 is narrow, ORx and loopback profiles ignore this field */ + uint8_t rhb2Decimation; /*!< RX Halfband2 (HB2) decimation. Can be either 1 or 2 */ + uint8_t rhb3Decimation; /*!< RX Halfband3 (HB3) decimation. Can be either 1 or 2 */ + uint8_t rxFir1Decimation; /*!< Rx FIR decimation (1,2) */ + uint8_t rxFir2Decimation; /*!< Rx FIR decimation (1,2), ORx and loopback profiles ignore this field */ + uint32_t rxOutputRate_kHz; /*!< Rx Output data rate in kHz */ + uint32_t rfBandwidth_kHz; /*!< Rx RF passband bandwidth for the profile */ + uint32_t rxBbf3dBCorner_kHz; /*!< Rx BBF (TIA) 3dB corner in kHz */ + uint32_t rxAdcBandWidth_kHz; /*!< Rx ADC bandwidth - tunes the bandwidth of the passband and noise transfer functions of the ADC */ + adi_adrv9025_RxFir_t rxFir; /*!< Rx FIR filter structure */ + adi_adrv9025_RxDdc_e rxDdcMode; /*!< Rx DDC mode */ + adi_adrv9025_RxNcoShifterCfg_t rxNcoShifterCfg; /*!< Rx NCO Shift parameters used for ZIF->RIF, CIF->ZIF, ORX only uses band A members */ + uint8_t tiaPowerMode; /*!< 5 options for TIA power reduction modes (range 0-4, where 4 = allow ARM to set based on LUT for power saving) */ + adi_adrv9025_RxDataFormat_t rxDataFormat; /*!< Rx Data Format settings structure */ + int16_t rxAdc[ADI_ADRV9025_RXADC_COEFS]; /*!< RxAdc profile for that channel*/ +} adi_adrv9025_RxProfile_t; + +/** + * \brief Data structure to hold Tx data path settings + */ +typedef struct adi_adrv9025_RxChannelCfg +{ + adi_adrv9025_RxProfile_t profile; /*!< Rx datapath profile, 3dB corner frequencies, and digital filter enables */ +} adi_adrv9025_RxChannelCfg_t; + +/** + * \brief Data structure to hold ADRV9025 Rx Channel configuration settings + */ +typedef struct adi_adrv9025_RxSettings +{ + uint32_t rxInitChannelMask; /*!< Rx channel mask of which channels to initialize */ + adi_adrv9025_RxChannelCfg_t rxChannelCfg[ADI_ADRV9025_MAX_RXCHANNELS]; /*!< Rx settings per Rx channel */ +} adi_adrv9025_RxSettings_t; + +/** + * \brief Data structure to hold digital clock settings + */ +typedef struct adi_adrv9025_ClockSettings +{ + uint32_t deviceClock_kHz; /*!< Device clock frequency in kHz */ + uint32_t clkPllVcoFreq_kHz; /*!< CLKPLL VCO frequency in kHz */ + uint32_t serdesPllVcoFreq_kHz; /*!< SERDESPLL VCO frequency in kHz */ + uint8_t ldoSelect; /*!< LDO select flag 0-Non-Bypass, 1-Bypass, WARNING: Damage may occur if set incorrectly for your PCB layout. */ + uint32_t extLoFreq1_kHz; /*!< EXT LO frequency 1 in kHz */ + uint32_t extLoFreq2_kHz; /*!< EXT LO frequency 2 in kHz */ + adi_adrv9025_PllLoMode_e rfPll1LoMode; /*!< internal LO generation for RF LO1, internal LO can be output, or external LO can be input */ + adi_adrv9025_PllLoMode_e rfPll2LoMode; /*!< internal LO generation for RF LO2, internal LO can be output, or external LO can be input */ + uint8_t rfPll1LoOutDivider; /*!< Only valid in LO output mode. This divider is independent from internal LO gen divider (valid 1, 2, 4, 8, 16, 32, 64, 128) */ + uint8_t rfPll2LoOutDivider; /*!< Only valid in LO output mode. This divider is independent from internal LO gen divider (valid 1, 2, 4, 8, 16, 32, 64, 128) */ + adi_adrv9025_RfPllMcs_e rfPllPhaseSyncMode; /*!< Set RF PLL phase synchronization mode. Adds extra time to lock RF PLL when PLL frequency changed. See enum for options */ + adi_adrv9025_LoSel_e rx12LoSelect; /*!< Rx1/Rx2 LO select: 1 = LO1, 2 = LO2 */ + adi_adrv9025_LoSel_e rx34LoSelect; /*!< Rx3/Rx4 LO select: 1 = LO1, 2 = LO2 */ + adi_adrv9025_LoSel_e tx12LoSelect; /*!< Tx1/Tx2 LO select: 1 = LO1, 2 = LO2 */ + adi_adrv9025_LoSel_e tx34LoSelect; /*!< Tx3/Tx4 LO select: 1 = LO1, 2 = LO2 */ + adi_adrv9025_OrxLoSel_e orx12LoSelect; /*!< ORx1/ORx2 LO select: 1 = TX12 LO Source, 2 = AuxLO */ + adi_adrv9025_OrxLoSel_e orx34LoSelect; /*!< ORx3/ORx4 LO select: 1 = TX34 LO Source, 2 = AuxLO */ +} adi_adrv9025_ClockSettings_t; + +/** +* \brief Data Structure to hold ADRV9025 device Rx Max and Min gain indices +*/ +typedef struct +{ + uint8_t rx1MinGainIndex; /*!< Current device minimum Rx1 gain index */ + uint8_t rx1MaxGainIndex; /*!< Current device maximum Rx1 gain index */ + uint8_t rx2MinGainIndex; /*!< Current device minimum Rx2 gain index */ + uint8_t rx2MaxGainIndex; /*!< Current device maximum Rx2 gain index */ + uint8_t rx3MinGainIndex; /*!< Current device minimum Rx3 gain index */ + uint8_t rx3MaxGainIndex; /*!< Current device maximum Rx3 gain index */ + uint8_t rx4MinGainIndex; /*!< Current device minimum Rx4 gain index */ + uint8_t rx4MaxGainIndex; /*!< Current device maximum Rx4 gain index */ + uint8_t orx1orx2MinGainIndex; /*!< Current device minimum Orx1 gain index */ + uint8_t orx1orx2MaxGainIndex; /*!< Current device maximum Orx1 gain index */ + uint8_t orx3orx4MinGainIndex; /*!< Current device minimum Orx3 gain index */ + uint8_t orx3orx4MaxGainIndex; /*!< Current device maximum Orx3 gain index */ +} adi_adrv9025_GainIndex_t; + +/** + * \brief Data structure to hold SPI settings for all system device types + */ +typedef struct adi_adrv9025_SpiSettings +{ + uint8_t msbFirst; /*!< 1 = MSB First, 0 = LSB First Bit order for SPI transaction */ + uint8_t enSpiStreaming; /*!< Not Recommended - most registers in ADRV9025 API are not consecutive */ + uint8_t autoIncAddrUp; /*!< For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr = addr-1 */ + uint8_t fourWireMode; /*!< 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */ + adi_adrv9025_CmosPadDrvStr_e cmosPadDrvStrength; /*!< Drive strength of CMOS pads when used as outputs (SDIO, SDO, GP_INTERRUPT, GPIO 1, GPIO 0) */ +} adi_adrv9025_SpiSettings_t; + +#define ADC_PROFILE_MAX 56 + +/** + * \brief Data structure to hold ADRV9025 ADC Profile settings + */ +typedef struct adi_adrv9025_AdcProfiles +{ + uint16_t RxChannel1[ADC_PROFILE_MAX]; /*!< Receiver channel ADC Profile.*/ + uint16_t RxChannel2[ADC_PROFILE_MAX]; /*!< Receiver channel ADC Profile.*/ + uint16_t RxChannel3[ADC_PROFILE_MAX]; /*!< Receiver channel ADC Profile.*/ + uint16_t RxChannel4[ADC_PROFILE_MAX]; /*!< Receiver channel ADC Profile.*/ + uint16_t OrxChannel1Profile0[ADC_PROFILE_MAX]; /*!< Orx channel 1, profile number 0 .*/ + uint16_t OrxChannel1Profile1[ADC_PROFILE_MAX]; /*!< Orx channel 1, profile number 1 .*/ + uint16_t OrxChannel1Profile2[ADC_PROFILE_MAX]; /*!< Orx channel 1, profile number 2 .*/ + uint16_t OrxChannel1Profile3[ADC_PROFILE_MAX]; /*!< Orx channel 1, profile number 3 .*/ + uint16_t OrxChannel2Profile0[ADC_PROFILE_MAX]; /*!< Orx channel 2, profile number 0 .*/ + uint16_t OrxChannel2Profile1[ADC_PROFILE_MAX]; /*!< Orx channel 2, profile number 1 .*/ + uint16_t OrxChannel2Profile2[ADC_PROFILE_MAX]; /*!< Orx channel 2, profile number 2 .*/ + uint16_t OrxChannel2Profile3[ADC_PROFILE_MAX]; /*!< Orx channel 2, profile number 3 .*/ + uint8_t OrxChannel1Index; /*!< /Orx Channel 1, active profile. */ + uint8_t OrxChannel2Index; /*!< /Orx Channel 2, active profile. */ +} adi_adrv9025_AdcProfiles_t; + +/** + * \brief Data structure to hold ADRV9025 device instance initialization settings + */ +typedef struct adi_adrv9025_Init +{ + adi_adrv9025_ClockSettings_t clocks; /*!< Holds settings for CLKPLL and reference clock */ + adi_adrv9025_GpInterruptSettings_t gpInterrupts; /*!< Holds settings for default gp interrupt masks for pin 0 and 1 */ + adi_adrv9025_RxSettings_t rx; /*!< Rx settings data structure */ + adi_adrv9025_TxSettings_t tx; /*!< Tx settings data structure */ + adi_adrv9025_DataInterfaceCfg_t dataInterface; /*!< Holds the Data Interface JESD204B/C data link settings */ + adi_adrv9025_AdcProfiles_t adcProfiles; /*!< Rx ADC Profiles*/ +} adi_adrv9025_Init_t; + +/** +* \brief Data structure for ADRV9025 enable MCS Mask +*/ +typedef struct adi_adrv9025_enableMcsMask +{ + uint8_t clkMcsControlMask; + uint8_t rf1McsControlMask; + uint8_t rf2McsControlMask; + uint8_t auxMcsControlMask; +} adi_adrv9025_enableMcsMask_t; + +/** +* \brief Data structure to hold clock divide ratios +*/ +typedef struct adi_adrv9025_ClkDivideRatios +{ + uint8_t armClkDivideRatio; /*ARM clock divide ratio w.r.t hsDigClk*/ + uint8_t agcClkDivideRatio; /*AGC module clock divide ratio w.r.t hsDigClk*/ + uint8_t regClkDivideRatio; /*Register bus clock divide ratio w.r.t hsDigClk*/ + uint8_t txAttenDeviceClockDivideRatio; /*Tx Atten module clock divide ratio w.r.t hsDigClk*/ +} adi_adrv9025_ClkDivideRatios_t; + +/** + * \brief Data structure to hold a ADRV9025 device instance status information + * + * Application layer allocates this memory, but only API writes to it to keep up with the API run time state. + */ +typedef struct adi_adrv9025_Info +{ + uint8_t deviceSiRev; /*!< ADRV9025 silicon rev read during HWOpen */ + uint8_t deviceProductId; /*!< ADRV9025 Product ID read during HWOpen */ + adi_adrv9025_ApiStates_e devState; /*!< Current device state of the part, i.e., radio on, radio off, arm loaded, etc., defined by deviceState enum */ + uint32_t initializedChannels; /*!< Holds Rx/ORx/Tx channels that were initialized and calibrated for the current device */ + uint32_t profilesValid; /*!< Current device profilesValid bit field for use notification, i.e., Tx = 0x01, Rx = 0x02, Orx = 0x04 */ + + adi_adrv9025_TxAttenStepSize_e txAttenStepSize[ADI_ADRV9025_MAX_TXCHANNELS]; /*!< Current tx Atten step size for each Tx channel */ + adi_adrv9025_TxAttenMode_e txAttenMode[ADI_ADRV9025_MAX_TXCHANNELS]; /*!< Current tx Atten mode for each Tx channel */ + uint32_t swTest; /*!< Software testmode signal */ + uint32_t hsDigClk_kHz; /*!< Calculated in initialize() digital clock used throughout API functions */ + adi_adrv9025_ClkDivideRatios_t clkDivideRatios; /*!< Clock divide ratios w.r.t hsDigClk for various modules in the device */ + + uint32_t txInputRate_kHz[ADI_ADRV9025_MAX_TXCHANNELS]; /*!< Tx Input sample rate from currently loaded profile */ + uint32_t rxOutputRate_kHz[ADI_ADRV9025_MAX_RXCHANNELS]; /*!< Rx Output sample rate from currently loaded profile */ + adi_adrv9025_GainIndex_t gainIndexes; /*!< Current device Rx min max gain index values */ + uint32_t rxAgcPeakModeMask; /*!< Previous AGC config peak vs power mode */ + uint16_t chunkStreamImageSize[12]; /*!< Stream Image Size */ + uint16_t chunkStreamImageOffset[12]; /*!< Stream Image Offset */ + uint32_t currentStreamBinBaseAddr; /*!< Address to load current stream */ + uint32_t currentStreamBaseAddr; /*!< Address to load current stream base */ + uint8_t currentStreamNumberStreams; /*!< Number of Streams for current stream */ + uint8_t currentStreamImageIndex; /*!< Index of current stream */ + uint32_t currentStreamImageSize; /*!< Image size of current stream */ + uint8_t rxFramerNp; /*!< Rx Framer Np - converter sample resolution (12, 16, 24) */ + uint8_t rxChannel3bitSlicerMode; /*!< If a bit is set - corresponding Rx Channel Data format slicer ctrl is 3 bits */ + + PRIVATE_TYPE_9025 sharedResourcePool[ADRV9025_NUM_SHARED_RESOURCES]; /*!< Shared resource pool for the given device instance*/ + adi_adrv9025_GpioPinSel_e extDpdCaptureTriggerGpio; /*!< External DPD capture trigger GPIO */ + uint8_t extDpdLutSwapModeEn; /*!< External DPD LUT swap mode enable setting */ + uint8_t linkSharingEnabled; /*!< Link sharing enabled if 1, disabled otherwise */ + adi_adrv9025_Cpu_t cpu; /*!< Processor related info */ + adi_adrv9025_JesdDataProfileCfg_t jesdCfg; /*!< JESD Profile Configuration */ + uint32_t txRfBandWidth_kHz[ADI_ADRV9025_MAX_TXCHANNELS]; /*!< Tx Rf Bandwidth from currently loaded profile */ + uint32_t rxRfBandWidth_kHz[ADI_ADRV9025_MAX_RXCHANNELS]; /*!< Rx Rf Bandwidth from currently loaded profile */ + uint8_t txSrlRateInvalidMask; /*!< TX bitmask indicates which TX channel has invalid SRL rate */ +} adi_adrv9025_Info_t; + +/* +* \brief Data structure to hold ADRV9025 device capability settings +*/ +typedef struct adi_adrv9025_CapabilityModel +{ + uint8_t productId; /*!< Current device Product Id */ + uint8_t siRevision; /*!< Current device silicon version */ + uint8_t txNumber; /*!< Current device number of Tx */ + uint8_t rxNumber; /*!< Current device number of Rx */ + uint8_t orxNumber; /*!< Current device number of Orx */ + uint32_t txChannelMask; /*!< Current device ChannelMask of Tx */ + uint32_t rxChannelMask; /*!< Current device ChannelMask of Rx */ + uint32_t orxChannelMask; /*!< Current device ChannelMask of Rx */ + uint32_t featureMask; /*!< Current device featureMask*/ + uint32_t txMaxBw_kHz; /*!< Current device max BW for Tx */ + uint32_t rxMaxBw_kHz; /*!< Current device max BW for Rx */ + uint32_t orxMaxBw_kHz; /*!< Current device max BW for Orx */ + uint32_t rfFreqRangeMin_kHz; /*!< Current device RF Freq Range Min */ + uint32_t rfFreqRangeMax_kHz; /*!< Current device RF Freq Range Max */ + uint32_t serializerLaneEnableMask; /*!< Mask of Hardware Enabled Serializer Lanes */ + uint32_t deserializerLaneEnableMask; /*!< Mask of Hardware Enabled Deserializer Lanes */ +} adi_adrv9025_CapabilityModel_t; + +/** +* \brief Data structure to hold ADRV9025 Tx Ramp down init time configuration +*/ +typedef struct adi_adrv9025_TxRampDownInitCfg +{ + uint32_t txRampDownEvents; /*!< Init time Tx ramp down event masks selected through profile. For details, please see adi_adrv9025_InitTxRampDownEvents_e */ + adi_adrv9025_TxChannels_e txChannel; /*!< Tx channel selection to apply init time config */ + adi_adrv9025_LoSel_e txLoSel; /*!< Init time LO selection for Tx channel through profile */ + uint8_t deserializerLanesEnabledDfrm0; /*!< Init time lane enable selection for Jesd Dfrm 0 through profile*/ + uint8_t deserializerLanesEnabledDfrm1; /*!< Init time lane enable selection for Jesd Dfrm 1 through profile*/ + uint32_t serdesPllVcoFreq_kHz; /*!< Init time SERDES Pll Frequency through profile*/ +} adi_adrv9025_TxRampDownInitCfg_t; + +/** +* \brief Data structure to hold ADRV9025 device instance settings +*/ +typedef struct adi_adrv9025_Device +{ + adi_common_Device_t common; /*!< Common layer structure */ + adi_adrv9025_Info_t devStateInfo; /*!< ADRV9025 run time state information container */ + adi_adrv9025_SpiSettings_t spiSettings; /*!< ADRV9025 SPI Settings */ + adi_adrv9025_CapabilityModel_t deviceCapability; /*!< ADRV9025 Device Capability Settings */ +} adi_adrv9025_Device_t; + +#ifndef UNUSED_PARA +#define UNUSED_PARA(x) (void)(x) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_user.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_user.h new file mode 100644 index 0000000..58889a1 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_user.h @@ -0,0 +1,765 @@ +/** +* \file adi_adrv9025_user.h +* \brief Contains ADRV9025 API macro definitions and global structure declarations for adi_adrv9025_user.c +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_USER_H_ +#define _ADI_ADRV9025_USER_H_ + +#include "adi_adrv9025_types.h" + +#ifdef __cplusplus +extern +"C" + { +#endif + +/* + ***************************************** + * Interface Macros + ****************************************** + */ +#ifndef ADI_ADRV9025_VERBOSE +#define ADI_ADRV9025_VERBOSE 1 /*Use strings 0 not use, 1 use */ +#endif /* !ADI_ADRV9025_VERBOSE */ + +#ifndef ADI_ADRV9025_CPU_VERBOSE +#define ADI_ADRV9025_CPU_VERBOSE 1 /*Use strings 0 not use, 1 use */ +#endif /* !ADI_ADRV9025_VERBOSE */ + +#ifndef ADI_ADRV9025_LOGGING +#define ADI_ADRV9025_LOGGING ADI_COMMON_LOG_MSG | \ + ADI_COMMON_LOG_WARN | \ + ADI_COMMON_LOG_ERR | \ + ADI_COMMON_LOG_API /*LogLevel Set to API, Messages, Warnings, Error*/ +#endif /* !ADI_ADRV9025_LOGGING */ + +#ifndef ADI_ADRV9025_RESET_ON_ERR +#define ADI_ADRV9025_RESET_ON_ERR 1 /*API Reset on Severe Errors*/ +#endif + +#ifndef ADI_ADRV9025_NUMBER_SPI_RETRY +#define ADI_ADRV9025_NUMBER_SPI_RETRY 2 +#endif + +#ifndef ADI_ADRV9025_PFIR_COEFF_AUTO_INCR +#define ADI_ADRV9025_PFIR_COEFF_AUTO_INCR 0 +#endif + +#ifndef ADI_ADRV9025_CPU_MEM_AUTO_INCR +#define ADI_ADRV9025_CPU_MEM_AUTO_INCR 1 +#endif + +#ifndef ADI_ADRV9025_CPU_MEMWRITE_CACHE_ENABLE +#define ADI_ADRV9025_CPU_MEMWRITE_CACHE_ENABLE 1 +#endif + +#ifndef ADI_ADRV9025_CPU_MEMREAD_CACHE_ENABLE +#define ADI_ADRV9025_CPU_MEMREAD_CACHE_ENABLE 0 +#endif + + +#ifndef ADI_ADRV9025_SW_TEST +#define ADI_ADRV9025_SW_TEST 0 +#endif + +#ifndef ADI_ADRV9025_PROFILE_CHECKSUM_ENABLE +#define ADI_ADRV9025_PROFILE_CHECKSUM_ENABLE 0 +#endif + + +#ifndef ADRV9025_BITFIELD_ADDR_CHECK +#define ADRV9025_BITFIELD_ADDR_CHECK 1 +#endif + +#ifndef ADRV9025_BITFIELD_NULL_CHECK +#define ADRV9025_BITFIELD_NULL_CHECK 1 +#endif + +#ifndef ADRV9025_BITFIELD_VALUE_CHECK +#define ADRV9025_BITFIELD_VALUE_CHECK 0 +#endif + + +#ifndef ADRV9025_BITFIELD_LOG +#define ADRV9025_BITFIELD_LOG 0 +#endif + +#ifndef ADRV9025_BITFIELD_HAL_LOG +#define ADRV9025_BITFIELD_HAL_LOG 0 +#endif + +#ifndef ADI_ADRV9025_HAL_LOG +#define ADI_ADRV9025_HAL_LOG 0 +#endif + + +#ifndef ADI_ADRV9025_TX_ATTEN_TABLE_CACHE_MAX +#define ADI_ADRV9025_TX_ATTEN_TABLE_CACHE_MAX 256 /*Cache value: up to 1024, multiple of 4 */ +#endif + + +#ifndef ADI_ADRV9025_MEM_DUMP_CHUNK_SIZE +#define ADI_ADRV9025_MEM_DUMP_CHUNK_SIZE 256 /*Cache value: up to 1024, multiple of 4 */ +#endif + +#ifndef ADI_ADRV9025_STREAM_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES +#define ADI_ADRV9025_STREAM_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES (1024) /*Please ensure that the Stream bin size is perfectly divisible by the chunk size*/ +#endif + +#ifndef ADI_ADRV9025_CPU_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES +#define ADI_ADRV9025_CPU_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES (1024) /*Please ensure that the CPU FW bin size is perfectly divisible by the chunk size*/ +#endif + +/* TODO: A few examples for timeout and interval values, remove once new code added */ + +/* These values can be modified by the end user to adjust how active the SPI reads are + * to help prevent over using the SPI resource */ + +#ifndef ADI_ADRV9025_SETDEFAULTCONDITION_TIMEOUT_US +#define ADI_ADRV9025_SETDEFAULTCONDITION_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETDEFAULTCONDITION_INTERVAL_US +#define ADI_ADRV9025_SETDEFAULTCONDITION_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_VERIFY_CPU_CHKSUM_TIMEOUT_US +#define ADI_ADRV9025_VERIFY_CPU_CHKSUM_TIMEOUT_US 200000 +#endif + +#ifndef ADI_ADRV9025_VERIFY_CPU_CHKSUM_INTERVAL_US +#define ADI_ADRV9025_VERIFY_CPU_CHKSUM_INTERVAL_US 5000 +#endif + +#ifndef ADI_ADRV9025_CLKPLL_CPCAL_TIMEOUT_US +#define ADI_ADRV9025_CLKPLL_CPCAL_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_CLKPLL_CPCAL_INTERVAL_US +#define ADI_ADRV9025_CLKPLL_CPCAL_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_CLKPLL_LOCK_TIMEOUT_US +#define ADI_ADRV9025_CLKPLL_LOCK_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_CLKPLL_LOCK_INTERVAL_US +#define ADI_ADRV9025_CLKPLL_LOCK_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_CLKPLL_POWERUP_US +#define ADI_ADRV9025_CLKPLL_POWERUP_US 200000 +#endif + +#ifndef ADI_ADRV9025_CLKPLL_LOCK_US +#define ADI_ADRV9025_CLKPLL_LOCK_US 100000 +#endif + +#ifndef ADI_ADRV9025_SETARMGPIO_TIMEOUT_US +#define ADI_ADRV9025_SETARMGPIO_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETARMGPIO_INTERVAL_US +#define ADI_ADRV9025_SETARMGPIO_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETARMGPIO_TIMEOUT_US +#define ADI_ADRV9025_GETARMGPIO_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETARMGPIO_INTERVAL_US +#define ADI_ADRV9025_GETARMGPIO_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETTXTOORXMAP_TIMEOUT_US +#define ADI_ADRV9025_SETTXTOORXMAP_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETTXTOORXMAP_INTERVAL_US +#define ADI_ADRV9025_SETTXTOORXMAP_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETTXTOORXMAP_TIMEOUT_US +#define ADI_ADRV9025_GETTXTOORXMAP_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETTXTOORXMAP_INTERVAL_US +#define ADI_ADRV9025_GETTXTOORXMAP_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETTEMPERATURE_TIMEOUT_US +#define ADI_ADRV9025_GETTEMPERATURE_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETTEMPERATURE_INTERVAL_US +#define ADI_ADRV9025_GETTEMPERATURE_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETRFPLL_TIMEOUT_US +#define ADI_ADRV9025_SETRFPLL_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETRFPLL_INTERVAL_US +#define ADI_ADRV9025_SETRFPLL_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETRFPLL_TIMEOUT_US +#define ADI_ADRV9025_GETRFPLL_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETRFPLL_INTERVAL_US +#define ADI_ADRV9025_GETRFPLL_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETEXTDPDCAPTURETRIG_TIMEOUT_US +#define ADI_ADRV9025_SETEXTDPDCAPTURETRIG_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETEXTDPDCAPTURETRIG_INTERVAL_US +#define ADI_ADRV9025_SETEXTDPDCAPTURETRIG_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETEXTDPDCAPTUREDONE_INTERVAL_US +#define ADI_ADRV9025_SETEXTDPDCAPTUREDONE_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETEXTDPDCAPTUREDONE_TIMEOUT_US +#define ADI_ADRV9025_SETEXTDPDCAPTUREDONE_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETEXTDPDCAPTUREDONE_INTERVAL_US +#define ADI_ADRV9025_GETEXTDPDCAPTUREDONE_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETEXTDPDCAPTUREDONE_TIMEOUT_US +#define ADI_ADRV9025_GETEXTDPDCAPTUREDONE_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETEXTDPDENABLE_INTERVAL_US +#define ADI_ADRV9025_SETEXTDPDENABLE_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETEXTDPDENABLE_TIMEOUT_US +#define ADI_ADRV9025_SETEXTDPDENABLE_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETEXTDPDENABLE_INTERVAL_US +#define ADI_ADRV9025_GETEXTDPDENABLE_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETEXTDPDENABLE_TIMEOUT_US +#define ADI_ADRV9025_GETEXTDPDENABLE_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETEXTDMODELSELECT_INTERVAL_US +#define ADI_ADRV9025_SETEXTDMODELSELECT_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETEXTDMODELSELECT_TIMEOUT_US +#define ADI_ADRV9025_SETEXTDMODELSELECT_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETEXTDMODELSELECT_INTERVAL_US +#define ADI_ADRV9025_GETEXTDMODELSELECT_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETEXTDMODELSELECT_TIMEOUT_US +#define ADI_ADRV9025_GETEXTDMODELSELECT_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETEXTDHARDCLIPPER_INTERVAL_US +#define ADI_ADRV9025_SETEXTDHARDCLIPPER_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETEXTDHARDCLIPPER_TIMEOUT_US +#define ADI_ADRV9025_SETEXTDHARDCLIPPER_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETEXTDHARDCLIPPER_INTERVAL_US +#define ADI_ADRV9025_GETEXTDHARDCLIPPER_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETEXTDHARDCLIPPER_TIMEOUT_US +#define ADI_ADRV9025_GETEXTDHARDCLIPPER_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETEXTDLUTCLEAR_INTERVAL_US +#define ADI_ADRV9025_SETEXTDLUTCLEAR_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETEXTDLUTCLEAR_TIMEOUT_US +#define ADI_ADRV9025_SETEXTDLUTCLEAR_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETEXTDLUTUPDATE_INTERVAL_US +#define ADI_ADRV9025_SETEXTDLUTUPDATE_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETEXTDLUTUPDATE_TIMEOUT_US +#define ADI_ADRV9025_SETEXTDLUTUPDATE_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETDPDRESET_INTERVAL_US +#define ADI_ADRV9025_SETDPDRESET_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETDPDRESET_TIMEOUT_US +#define ADI_ADRV9025_SETDPDRESET_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETDPDTRACKCONFIG_INTERVAL_US +#define ADI_ADRV9025_SETDPDTRACKCONFIG_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETDPDTRACKCONFIG_TIMEOUT_US +#define ADI_ADRV9025_SETDPDTRACKCONFIG_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETDPDTRACKCONFIG_INTERVAL_US +#define ADI_ADRV9025_GETDPDTRACKCONFIG_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETDPDTRACKCONFIG_TIMEOUT_US +#define ADI_ADRV9025_GETDPDTRACKCONFIG_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETDPDFAULTCONDITION_INTERVAL_US +#define ADI_ADRV9025_SETDPDFAULTCONDITION_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETDPDFAULTCONDITION_TIMEOUT_US +#define ADI_ADRV9025_SETDPDFAULTCONDITION_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETDPDFAULTCONDITION_INTERVAL_US +#define ADI_ADRV9025_GETDPDFAULTCONDITION_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETDPDFAULTCONDITION_TIMEOUT_US +#define ADI_ADRV9025_GETDPDFAULTCONDITION_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETDPDRECOVERYACTION_INTERVAL_US +#define ADI_ADRV9025_SETDPDRECOVERYACTION_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETDPDRECOVERYACTION_TIMEOUT_US +#define ADI_ADRV9025_SETDPDRECOVERYACTION_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETDPDRECOVERYACTION_INTERVAL_US +#define ADI_ADRV9025_GETDPDRECOVERYACTION_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETDPDRECOVERYACTION_TIMEOUT_US +#define ADI_ADRV9025_GETDPDRECOVERYACTION_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETEXTPATHDELAY_INTERVAL_US +#define ADI_ADRV9025_SETEXTPATHDELAY_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETEXTPATHDELAY_TIMEOUT_US +#define ADI_ADRV9025_SETEXTPATHDELAY_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETHARDCLIPENABLE_INTERVAL_US +#define ADI_ADRV9025_SETHARDCLIPENABLE_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETHARDCLIPENABLE_TIMEOUT_US +#define ADI_ADRV9025_SETHARDCLIPENABLE_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETCFRCTRLCFG_INTERVAL_US +#define ADI_ADRV9025_SETCFRCTRLCFG_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETCFRCTRLCFG_TIMEOUT_US +#define ADI_ADRV9025_SETCFRCTRLCFG_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SENDCPUCMD_TIMEOUT_US +#define ADI_ADRV9025_SENDCPUCMD_TIMEOUT_US 2000000 +#endif + +#ifndef ADI_ADRV9025_SENDCPUCMD_INTERVAL_US +#define ADI_ADRV9025_SENDCPUCMD_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_READCPUCFG_TIMEOUT_US +#define ADI_ADRV9025_READCPUCFG_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_READCPUCFG_INTERVAL_US +#define ADI_ADRV9025_READCPUCFG_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_WRITECPUCFG_TIMEOUT_US +#define ADI_ADRV9025_WRITECPUCFG_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_WRITECPUCFG_INTERVAL_US +#define ADI_ADRV9025_WRITECPUCFG_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETCPUBOOTUP_TIMEOUT_US +#define ADI_ADRV9025_GETCPUBOOTUP_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETCPUBOOTUP_INTERVAL_US +#define ADI_ADRV9025_GETCPUBOOTUP_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETCPUBOOTUPMCS_TIMEOUT_US +#define ADI_ADRV9025_SETCPUBOOTUPMCS_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETCPUBOOTUPMCS_INTERVAL_US +#define ADI_ADRV9025_SETCPUBOOTUPMCS_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_WRITECPUEXCEPTION_TIMEOUT_US +#define ADI_ADRV9025_WRITECPUEXCEPTION_TIMEOUT_US 5000000 +#endif + +#ifndef ADI_ADRV9025_WRITECPUEXCEPTION_INTERVAL_US +#define ADI_ADRV9025_WRITECPUEXCEPTION_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_INITCALSWAIT_INTERVAL_US +#define ADI_ADRV9025_INITCALSWAIT_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_INITCALSABORT_TIMEOUT_US +#define ADI_ADRV9025_INITCALSABORT_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_INITCALSABORT_INTERVAL_US +#define ADI_ADRV9025_INITCALSABORT_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_INITCALSTATUSGET_TIMEOUT_US +#define ADI_ADRV9025_INITCALSTATUSGET_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_INITCALSTATUSGET_INTERVAL_US +#define ADI_ADRV9025_INITCALSTATUSGET_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_ENTRACKINGCALS_TIMEOUT_US +#define ADI_ADRV9025_ENTRACKINGCALS_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_ENTRACKINGCALS_INTERVAL_US +#define ADI_ADRV9025_ENTRACKINGCALS_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETSRLCONFIG_TIMEOUT_US +#define ADI_ADRV9025_SETSRLCONFIG_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETSRLCONFIG_INTERVAL_US +#define ADI_ADRV9025_SETSRLCONFIG_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETSRLCONFIG_TIMEOUT_US +#define ADI_ADRV9025_GETSRLCONFIG_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETSRLCONFIG_INTERVAL_US +#define ADI_ADRV9025_GETSRLCONFIG_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETSRLSTATS_TIMEOUT_US +#define ADI_ADRV9025_GETSRLSTATS_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETSRLSTATS_INTERVAL_US +#define ADI_ADRV9025_GETSRLSTATS_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETTXLOLSTATUS_TIMEOUT_US +#define ADI_ADRV9025_GETTXLOLSTATUS_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETTXLOLSTATUS_INTERVAL_US +#define ADI_ADRV9025_GETTXLOLSTATUS_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETTXQECSTATUS_TIMEOUT_US +#define ADI_ADRV9025_GETTXQECSTATUS_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETTXQECSTATUS_INTERVAL_US +#define ADI_ADRV9025_GETTXQECSTATUS_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETRXQECSTATUS_TIMEOUT_US +#define ADI_ADRV9025_GETRXQECSTATUS_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETRXQECSTATUS_INTERVAL_US +#define ADI_ADRV9025_GETRXQECSTATUS_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETORXQECSTATUS_TIMEOUT_US +#define ADI_ADRV9025_GETORXQECSTATUS_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETORXQECSTATUS_INTERVAL_US +#define ADI_ADRV9025_GETORXQECSTATUS_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETTXVSWRSTATUS_TIMEOUT_US +#define ADI_ADRV9025_GETTXVSWRSTATUS_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETTXVSWRSTATUS_INTERVAL_US +#define ADI_ADRV9025_GETTXVSWRSTATUS_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETTXCLGCSTATUS_TIMEOUT_US +#define ADI_ADRV9025_GETTXCLGCSTATUS_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETTXCLGCSTATUS_INTERVAL_US +#define ADI_ADRV9025_GETTXCLGCSTATUS_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETTXDPDSTATUS_TIMEOUT_US +#define ADI_ADRV9025_GETTXDPDSTATUS_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETTXDPDSTATUS_INTERVAL_US +#define ADI_ADRV9025_GETTXDPDSTATUS_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETTXCFRSTATUS_TIMEOUT_US +#define ADI_ADRV9025_GETTXCFRSTATUS_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETTXCFRSTATUS_INTERVAL_US +#define ADI_ADRV9025_GETTXCFRSTATUS_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETRXHD2STATUS_TIMEOUT_US +#define ADI_ADRV9025_GETRXHD2STATUS_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETRXHD2STATUS_INTERVAL_US +#define ADI_ADRV9025_GETRXHD2STATUS_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETTCALS_STATE_TIMEOUT_US +#define ADI_ADRV9025_GETTCALS_STATE_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETTCALS_STATE_INTERVAL_US +#define ADI_ADRV9025_GETTCALS_STATE_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETDESSTATUS_TIMEOUT_US +#define ADI_ADRV9025_GETDESSTATUS_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETDESSTATUS_INTERVAL_US +#define ADI_ADRV9025_GETDESSTATUS_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_GETBANDSWITCHSTAT_TIMEOUT_US +#define ADI_ADRV9025_GETBANDSWITCHSTAT_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_GETBANDSWITCHSTAT_INTERVAL_US +#define ADI_ADRV9025_GETBANDSWITCHSTAT_INTERVAL_US 1000 +#endif + +#ifndef ADI_ADRV9025_SETMCS_DONE_TIMEOUT_US +#define ADI_ADRV9025_SETMCS_DONE_TIMEOUT_US 1000000 +#endif + +#ifndef ADI_ADRV9025_SETMCS_DONE_INTERVAL_US +#define ADI_ADRV9025_SETMCS_DONE_INTERVAL_US 1000 +#endif +#ifndef ADI_ADRV9025_TEST_MODE_TIMEOUT_US +#define ADI_ADRV9025_TEST_MODE_TIMEOUT_US 30000000 +#endif + +#ifndef ADI_ADRV9025_TEST_MODE_INTERVAL_US +#define ADI_ADRV9025_TEST_MODE_INTERVAL_US 10000 +#endif +/* + ***************************************** + * Rx and ObsRx gain tables + ****************************************** + */ + +#ifndef ADI_ADRV9025_MAX_GAIN_TABLE_INDEX +#define ADI_ADRV9025_MAX_GAIN_TABLE_INDEX 255 +#endif + +#ifndef ADI_ADRV9025_MIN_GAIN_TABLE_INDEX +#define ADI_ADRV9025_MIN_GAIN_TABLE_INDEX 0 +#endif + + +#ifndef ADI_ADRV9025_START_RX_GAIN_INDEX +#define ADI_ADRV9025_START_RX_GAIN_INDEX 255 +#endif + +#ifndef ADI_ADRV9025_MIN_RX_GAIN_TABLE_INDEX +#define ADI_ADRV9025_MIN_RX_GAIN_TABLE_INDEX 0 +#endif + + +#ifndef ADI_ADRV9025_START_ORX_GAIN_INDEX +#define ADI_ADRV9025_START_ORX_GAIN_INDEX 255 +#endif + +#ifndef ADI_ADRV9025_MIN_ORX_GAIN_TABLE_INDEX +#define ADI_ADRV9025_MIN_ORX_GAIN_TABLE_INDEX 0 +#endif + + +#ifndef ADI_ADRV9025_RX_RANGE_CHECK +#define ADI_ADRV9025_RX_RANGE_CHECK 1 +#endif + +#ifndef ADI_ADRV9025_RADIOCTRL_RANGE_CHECK +#define ADI_ADRV9025_RADIOCTRL_RANGE_CHECK 1 +#endif + +#ifndef ADI_ADRV9025_TX_RANGE_CHECK +#define ADI_ADRV9025_TX_RANGE_CHECK 1 +#endif + +#ifndef ADI_ADRV9025_AGC_RANGE_CHECK +#define ADI_ADRV9025_AGC_RANGE_CHECK 1 +#endif + +#ifndef ADI_ADRV9025_EXT_DPD_RANGE_CHECK +#define ADI_ADRV9025_EXT_DPD_RANGE_CHECK 1 +#endif + +#ifndef ADI_ADRV9025_FOVR_RANGE_CHECK +#define ADI_ADRV9025_FOVR_RANGE_CHECK 1 +#endif + +#ifndef ADI_ADRV9025_GPIO_RANGE_CHECK +#define ADI_ADRV9025_GPIO_RANGE_CHECK 1 +#endif + +#ifndef ADI_ADRV9025_DPD_RANGE_CHECK +#define ADI_ADRV9025_DPD_RANGE_CHECK 1 +#endif + +#ifndef ADI_ADRV9025_PCA_RANGE_CHECK +#define ADI_ADRV9025_PCA_RANGE_CHECK 1 +#endif + +#ifndef ADI_ADRV9025_PHM_RANGE_CHECK +#define ADI_ADRV9025_PHM_RANGE_CHECK 1 +#endif + +#ifndef ADI_ADRV9025_CFR_RANGE_CHECK +#define ADI_ADRV9025_CFR_RANGE_CHECK 1 +#endif + +#ifndef ADI_ADRV9025_CLGC_RANGE_CHECK +#define ADI_ADRV9025_CLGC_RANGE_CHECK 1 +#endif + +#ifndef ADI_ADRV9025_INIT_RANGE_CHECK +#define ADI_ADRV9025_INIT_RANGE_CHECK 0 +#endif + + /** + * SPI Write Streaming Enable + * + * If enabled, dma full word write transactions are performed with Spi streaming. This allows API to write a full word as + * A A D D D D package of 6 bytes. If disabled, API writes a full word as A A D A A D A A D A A D package of 12 bytes. + * Streaming speeds up the memory access when there is large number of bytes to be written. + */ +#ifndef ADI_ADRV9025_SPI_WRITE_STREAMING_ENABLE + +#define ADI_ADRV9025_SPI_WRITE_STREAMING_ENABLE 0 + +#endif + + + /** + * SPI Read Streaming Enable + * + * If enabled, dma full word read transactions are performed with Spi streaming. This allows API to read a full word as + * A A D D D D package of 6 bytes. If disabled, API reads a full word as A A D A A D A A D A A D package of 12 bytes. + * Streaming speeds up the memory access when there is large number of bytes to be read. + */ +#ifndef ADI_ADRV9025_SPI_READ_STREAMING_ENABLE +#define ADI_ADRV9025_SPI_READ_STREAMING_ENABLE 0 +#endif + +#ifndef ADI_ADRV9025_LITTLE_ENDIAN_ENABLE +#define ADI_ADRV9025_LITTLE_ENDIAN_ENABLE 1 +#endif + + +#if ADI_ADRV9025_LITTLE_ENDIAN_ENABLE == 1 +#define HTOCLL( x ) ( x ) +#define CTOHLL( x ) ( x ) +#define HTOCL( x ) ( x ) +#define CTOHL( x ) ( x ) +#define HTOCS( x ) ( x ) +#define CTOHS( x ) ( x ) +#else +#define HTOCLL( x ) ((((x) & 0xFF00000000000000ull) >> 56u) | \ + (((x) & 0x00FF000000000000ull) >> 40u) | \ + (((x) & 0x0000FF0000000000ull) >> 24u) | \ + (((x) & 0x000000FF00000000ull) >> 8u) | \ + (((x) & 0x00000000FF000000ull) << 8u) | \ + (((x) & 0x0000000000FF0000ull) << 24u) | \ + (((x) & 0x000000000000FF00ull) << 40u) | \ + (((x) & 0x00000000000000FFull) << 56u)) +#define CTOHLL( x ) ((((x) & 0xFF00000000000000ull) >> 56u) | \ + (((x) & 0x00FF000000000000ull) >> 40u) | \ + (((x) & 0x0000FF0000000000ull) >> 24u) | \ + (((x) & 0x000000FF00000000ull) >> 8u) | \ + (((x) & 0x00000000FF000000ull) << 8u) | \ + (((x) & 0x0000000000FF0000ull) << 24u) | \ + (((x) & 0x000000000000FF00ull) << 40u) | \ + (((x) & 0x00000000000000FFull) << 56u)) +#define HTOCL( x ) ((((x) & 0xFF000000ul) >> 24) | (((x) & 0x00FF0000ul) >> 8) | (((x) & 0x0000FF00ul) << 8) | (((x) & 0x000000FFul) << 24)) +#define CTOHL( x ) ((((x) & 0xFF000000ul) >> 24) | (((x) & 0x00FF0000ul) >> 8) | (((x) & 0x0000FF00ul) << 8) | (((x) & 0x000000FFul) << 24)) +#define HTOCS( x ) ((((x) & 0xFF00u) >> 8) | (((x) & 0x00FFu) << 8)) +#define CTOHS( x ) ((((x) & 0xFF00u) >> 8) | (((x) & 0x00FFu) << 8)) +#endif + + /** + * ADI_ADRV9025_MAX_DPD_FEATURES + * + * Number of dpd model coefficients (defaulted to 190 which is the maximum) + */ +#ifndef ADI_ADRV9025_MAX_DPD_FEATURES +#define ADI_ADRV9025_MAX_DPD_FEATURES 190u +#endif + +#ifndef ADI_ADRV9025_HW_RMW_ENABLE + +#define ADI_ADRV9025_HW_RMW_ENABLE 1 /* Enable/Disable HW_RMW for ADRV9025 */ + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_utilities.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_utilities.h new file mode 100644 index 0000000..3be4cda --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_utilities.h @@ -0,0 +1,690 @@ +/** +* \file adi_adrv9025_utilities.h +* \brief Contains ADRV9025 utility functions to load ARM binaries +* load stream binaries, load Rx Gain Table, load Tx Atten Table. +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_UTILITIES_H_ +#define _ADI_ADRV9025_UTILITIES_H_ + +#include "adi_adrv9025_utilities_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Macro to restore wrOnly bit in case there is a failure within PreMcsInit_v2 +* +* \param commonDev Device variable having wrOnly bit to be restored +* \param wrOnlyRestore wrOnly bit value to restore +* \param recoveryAction Action to be tested against ADI_COMMON_ACT_NO_ACTION +*/ +#define ADI_ADRV9025_PREMCS_RESTORE_WRONLY(commonDev, wrOnlyRestore, recoveryAction) \ + if(recoveryAction != ADI_COMMON_ACT_NO_ACTION){ commonDev.cacheInfo.wrOnly = wrOnlyRestore; } + +/** +* \brief This utility function loads ADRV9025 ARM binary image through ArmImageWrite() API +* +* This function reads the ARM binary file from a specified location +* (typically in an SD card) and programs the ARM with the specified binary image +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* Please note that a large chunk size defined by ADI_ADRV9025_ARM_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES +* in adi_adrv9025_user.h could potentially cause the stack to crash. Please optimize the chunk size +* in accordance with the stack space available +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param armImagePath is a string containing absolute path of the ARM image to be programmed +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_ArmImageLoad(adi_adrv9025_Device_t* device, + const char* armImagePath); + +/** +* \brief This utility function loads ADRV9025 CPU FW image through ArmImageWrite() API +* +* This function reads the CPU FW file from a specified location +* (typically in an SD card) and programs the FW with the specified binary image +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* Please note that a large chunk size defined by ADI_ADRV9025_CPU_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES +* in adi_adrv9025_user.h could potentially cause the stack to crash. Please optimize the chunk size +* in accordance with the stack space available +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param fwImagePath is a string containing absolute path of the FW image to be programmed +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_CpuImageLoad(adi_adrv9025_Device_t* device, + const char* fwImagePath); + +/** +* \brief This utility function loads ADRV9025 Stream binary image through StreamImageWrite() API +* +* This function reads the ADRV9025 stream binary file from a specified location +* (typically in an SD card) and programs the stream processor with the specified binary image +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* Please note that a large chunk size defined by ADI_ADRV9025_STREAM_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES +* in adi_adrv9025_user.h could potentially cause the stack to crash. Please optimize the chunk size +* in accordance with the stack space available. +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param streamImagePath is a string containing absolute path of the stream image to be programmed +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_StreamImageLoad(adi_adrv9025_Device_t* device, + const char* streamImagePath); + +/** +* \brief This function performs a Sequential AHB Memory Read +* +* WARNING: Caller is responsible for allocating the correct buffer size for the read +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param start_address Start Address of the Sequential Memory Read +* \param buffer Buffer for Data Read +* \param size Number of Memory Locations to be Read +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_DmaMemoryRead(adi_adrv9025_Device_t* const device, + const uint32_t start_address, + uint8_t buffer[], + const uint32_t size); + +/** +* \brief This utility function loads ADRV9025 Rx Gain table file in csv format to ADRV9025 gain table SRAM +* +* This function reads the ADRV9025 Rx Gain Table file in csv format from a specified location +* (typically in an SD card) and programs the ADRV9025 SRAM with the gain table for the requested channels +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param rxGainTablePath is a string containing path to the Rx gain table in csv format to be programmed +* \param rxChannelMask Rx channels to be programmed. Valid masks include +* ADI_ADRV9025_RX1 - ADI_ADRV9025_RX4, ADI_ADRV9025_ORX1 - ADI_ADRV9025_ORX4. +* +* Rx Gain Table columns should be arranged in the following order +* +* -------------------------------------------------------------------------------------------------------- +* | Gain Index | FE Control Word | TIA Control | ADC Control | Ext Control | Phase Offset | Digital Gain | +* -------------------------------------------------------------------------------------------------------- +* +* Rx Gain Indices should be arranged in ascending order for row entries starting with the lowest gain index and +* and progressing to highest gain Index +* +* Eg: If the gain table contains entries from index 192 to index 255, the table has to be arranged such that +* first line should contain row entries for index 192 and the last line should contain row entries to index 255 +* with a total of 64 entries. +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainTableLoad(adi_adrv9025_Device_t* device, + const char* rxGainTablePath, + uint32_t rxChannelMask); + +/** +* \brief This utility function loads ADRV9025 Tx Attenuation table file in csv format to ADRV9025 Tx Atten table SRAM +* +* This function reads the ADRV9025 Tx Atten Table file in csv format from a specified location +* (typically in an SD card) and programs the ADRV9025 SRAM with the gain table for the requested Tx channels +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param txAttenTablePath is a string containing path to the Tx atten table in csv format to be programmed +* \param txChannelMask Tx channels to be programmed. Valid masks include +* ADI_ADRV9025_TX1 - ADI_ADRV9025_TX4. +* +* Tx Atten Table columns should be arranged in the following order +* +* ------------------------------------------------ +* | Tx Atten Index | Tx Atten Hp | Tx Atten Mult | +* ------------------------------------------------ +* +* Rx Gain Indices should be arranged in ascending order for row entries starting with the lowest tx atten index and +* and progressing to highest tx atten Index (Eg: Starting from index 0 and progressing to index 1023) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenTableLoad(adi_adrv9025_Device_t* device, + const char* txAttenTablePath, + uint32_t txChannelMask); + +/** +* \brief This utility function executes the Pre-MCS init sequence +* +* This function executes the following set of sub-functions required to be +* complete before sending sysref pulses for multi chip sync +* -> Reset Hardware +* -> Setup SPI controller, master bias, enable pin pads, Load PFIRs (adi_adrv9025_Initialize) +* -> Load ARM binary image from a .bin file +* -> Load Stream binary image from a .bin file +* -> Load Requested Rx gain tables from .csv files for initialized channels +* -> Load Reqeuested Tx atten tables from .csv files for initialized channels +* -> Load ARM profile +* -> Load ADC profile +* -> ARM bootup +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param init Pointer to ADRV9025 init settings structure +* \param armImagePath is a string containing absolute path of the arm image to be programmed +* \param streamImagePath is a string containing absolute path of the stream image to be programmed +* \param rxGainTableFileArr Channelized array of strings which hold the path to Rx gain table csv file +* \param rxGainTableFileArrSize Size of rxGainTableFileArr array holding list of paths to rx gain tables +* \param txAttenTableFileArr Channelized array of strings which hold the path to Tx atten table csv file +* \param txAttenTableFileArrSize Size of txAttenTableFileArr array holding list of paths to tx atten tables +* +* Rx Gain Table columns should be arranged in the following order +* +* -------------------------------------------------------------------------------------------------------- +* | Gain Index | FE Control Word | TIA Control | ADC Control | Ext Control | Phase Offset | Digital Gain | +* -------------------------------------------------------------------------------------------------------- +* +* Rx Gain Indices should be arranged in ascending order for row entries starting with the lowest gain index and +* and progressing to highest gain Index +* +* Eg: If the gain table contains entries from index 192 to index 255, the table has to be arranged such that +* first line should contain row entries for index 192 and the last line should contain row entries to index 255 +* with a total of 64 entries. +* +* Tx Atten Table columns should be arranged in the following order +* +* ------------------------------------------------ +* | Tx Atten Index | Tx Atten Hp | Tx Atten Mult | +* ------------------------------------------------ +* +* Tx Atten Indices should be arranged in ascending order for row entries starting with the lowest tx atten index and +* and progressing to highest tx atten Index (Eg: Starting from index 0 and progressing to index 1023) +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PreMcsInit_v2(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init, + const char* armImagePath, + const char* streamImagePath, + adi_adrv9025_RxGainTableFile_t rxGainTableFileArr[], + uint8_t rxGainTableFileArrSize, + adi_adrv9025_TxAttenTableFile_t txAttenTableFileArr[], + uint8_t txAttenTableFileArrSize); + +/** +* \brief This utility function executes the non-broadcastable part of +* Pre-MCS init sequence +* +* It should be called after adi_adrv9025_PreMcsInit_v2 and before +* adi_adrv9025_MultichipSyncSet. This function executes the following +* set of sub-functions required to be completed before sending sysref +* pulses for multi chip sync. +* -> Configure Rx Data Formatter +* -> Check Arm Status +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param init Pointer to ADRV9025 init settings structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PreMcsInit_NonBroadCast(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init); + +/** +* \brief This utility function mostly performs initialization at the feature level +* +* This function attempts to place individual features into a required init state +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param utilityInit Pointer to ADRV9025 utility init settings structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_PostMcsInit(adi_adrv9025_Device_t* device, + adi_adrv9025_PostMcsInit_t* utilityInit); + +/** +* \brief This utility function initialize the ADC Profiles +* +* The ADC profiles is initialize using fix profile with ADC bandwidth and ADC clock. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param init Pointer to ADRV9025 init settings structure +* \param adcProfile Pointer to ADRV9025 ADC profile settings structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AdcProfilesInit(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init, + adi_adrv9025_AdcProfiles_t* adcProfile); + +/** +* \brief This utility function edits the requested DAC word to compensate inaccuracies and +* temperature effects and sets the updated DAC word. Compensation has best accuracy +* between 0.25V - 1.5V outputs. Function has ADI_COMMON_LOG_API level logging. Logging +* level may be decreased prior to this function call for faster operation. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param auxDacSet Pointer to Aux Dac Value structure consisting of AuxDAC word, compensation mode and external temperature +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_AuxDacCompensatedSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxDacValueToCompensate_t* auxDacSet); + +/** +* \brief Utility function that will initialize an ADRV9025 init struct +* +* This reads the configuration file to scan for ADRV9025 init settings. +* +* \dep_begin +* \dep{NONE} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param configFile The absolute filepath of the Configuration File +* \param init Pointer to the ADRV9025 init device structure to initialize +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no +* action required +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter +* check +*/ +int32_t adi_adrv9025_ConfigFileLoad(adi_adrv9025_Device_t* device, + const char* configFile, + adi_adrv9025_Init_t* init); + +/** +* \brief Utility function that will initialize an ADRV9025 Utility Postmcs init struct +* +* +* This reads the utility init file to scan for ADRV9025 Utility Init settings. +* +* \dep_begin +* \dep{NONE} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param utilInitFile The absolute filepath of the Configuration File +* \param utilInit Pointer to the ADRV9025 utility init structure to initialize +* +* Example json file format as follows: +* { +* "radioCtrlInit": { +* "radioCtrlModeCfg": { +* "txRadioCtrlModeCfg": { +* "txEnableMode": 0, +* "txChannelMask": 15 +* }, +* "rxRadioCtrlModeCfg": { +* "rxEnableMode": 0, +* "rxChannelMask": 1023 +* }, +* "orxRadioCtrlModeCfg": { +* "orxEnableMode": 0, +* "orxPinSelectSettlingDelay_armClkCycles": 0, +* "singleChannel1PinModeOrxSel": 0, +* "singleChannel2PinModeLowOrxSel": 0, +* "singleChannel2PinModeHighOrxSel": 0, +* "dualChannel2PinModeOrxSel": 0 +* } +* }, +* "txToOrxMapping": { +* "orx1Map": 2, +* "orx2Map": 3, +* "orx3Map": 2, +* "orx4Map": 3 +* }, +* "streamGpioCfg": { +* "streamGpInput0": 19, +* "streamGpInput1": 19, +* "streamGpInput2": 19, +* "streamGpInput3": 19, +* "streamGpInput4": 19, +* "streamGpInput5": 19, +* "streamGpInput6": 19, +* "streamGpInput7": 19, +* "streamGpInput8": 19, +* "streamGpInput9": 19, +* "streamGpInput10": 19, +* "streamGpInput11": 19, +* "streamGpInput12": 19, +* "streamGpInput13": 19, +* "streamGpInput14": 19, +* "streamGpInput15": 19 +* }, +* "lo1PllFreq_Hz": 3500000000, +* "lo2PllFreq_Hz": 3600000000, +* "auxPllFreq_Hz": 0 +* }, +* "initCals": { +* "calMask": 866303, +* "channelMask": 15, +* "warmBoot": 0 +* }, +* "calRsltsFile": "", +* "checkFwVer": 0 +* } +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +*/ +int32_t adi_adrv9025_UtilityInitFileLoad(adi_adrv9025_Device_t* device, + const char* utilInitFile, + adi_adrv9025_PostMcsInit_t* utilInit); + +/* +* \brief This utility function dumps the ADRV9025 ARM program and data memory through ArmMemRead() API +* +* This function reads the ARM-C Memory and writes the binary byte array directly to a binary file.First 224K bytes are program memory followed +* by 160K bytes of data memory.The binaryFilename is opened before reading the ARM memory to verify that the filepath is has valid write access +* before reading ARM memory.A file IO exception will be thrown if write access is not valid for the binaryFilename path. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param binaryFilename is a string containing absolute path of the Arm memory to be dumped +*/ +int32_t adi_adrv9025_ArmMemDump(adi_adrv9025_Device_t* device, + const char* binaryFilename); + +/* +* \brief This utility function dumps the ADRV9025 ARM program and data memory through ArmMemRead() API +* +* This function reads the selected CPU Memory and writes the binary byte array directly to a binary file.First 224K bytes are program memory followed +* by 160K bytes of data memory for ARM-C. First 96K bytes are program memory followed by 160K bytes of data memory for ARM-D(Last 48K bytes is shared +* between ARM-C and ARM-D). The binaryFilename is opened before reading the ARM memory to verify that the filepath is has valid write access +* before reading ARM memory.A file IO exception will be thrown if write access is not valid for the binaryFilename path. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param cpuType Select CPU of which memory will be dumped +* \param binaryFilename is a string containing absolute path of the Arm memory to be dumped +*/ +int32_t adi_adrv9025_CpuMemDump(adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + const char* binaryFilename); + +/* +* \brief This utility function dumps the ADRV9025 ARM program and data memory through ArmMemRead() API +* +* This function reads the program and data memory of selected CPU and writes the binary byte array directly to a binary file. +* The binaryFilename is opened before reading the memory to verify that the filepath is has valid write access +* before reading memory.A file IO exception will be thrown if write access is not valid for the binaryFilename path. +* Note: This function doesn't force CPU to throw an exception, so it doesn't stop CPU's operation before reading data/program memories. +* Hence it should only be called when CPU code isn't running. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param cpuType CPU selection for which memory dump will be performed +* \param binaryFilename is a string containing absolute path of the Arm memory to be dumped +*/ +int32_t adi_adrv9025_CpuMemDumpWithoutException(adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + const char* binaryFilename); + +/* +* \brief This utility function initializes GP interrupt masks for pin0 and pin1 as provided to it. +* +* The intent of this function is that it gets called during init time to set the GP interrupt masks. By default these are setup as +* provided by the profile files, however, this function can be called anytime to set to other custom values. +* +* \dep_begin +* \dep{NONE} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param gpIntInit Pointer to adi_adrv9025_GpInterruptSettings_t structure containing mask for both pin0 and pin1. +*/ +int32_t adi_adrv9025_GpIntInit(adi_adrv9025_Device_t* device, + adi_adrv9025_GpInterruptSettings_t* gpIntInit); + +/** +* \brief This function should be called during device initialization after Jesd Dfrm links are brought up and Pll 's are locked. + It first clears Jesd Dfrm Irq's (by latching jrx_dl_204b_irq_clr bitfields). Then it masks all the ramp down events except + for the ones selected through 'txRampDownEvents' field in profile (It's users responsibility to mask the events for unused PLL sources, + if auto bit is not set in 'txRampDownEvents' field). Finally it sets master bits ('tx_data_ramp_down_on_pll_unlock' and + 'tx_data_ramp_down_on_jesd_dfrm_irq') to enable Pll Unlock and Jesd Dfrm Tx ramp down functionality. +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param init Pointer to the ADRV9025 init device structure +* +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_CHECK_TIMER Recovery action for timer time-out check required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxRampDownInit(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init); + +/** +* \brief This utility function reads ADRV9025 Rx Gain table file checksum value +* +* This function reads the ADRV9025 Rx Gain Table file in csv format from a specified location +* (typically in an SD card) and get checksum information, 32bit, hex format, in the last line +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param rxGainTablePath is a string containing path to the Rx gain table in csv format to be programmed +* \param rxGainTableChecksum is Rx gain table checksum information, 32bit +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainTableChecksumRead(adi_adrv9025_Device_t* device, + const char* rxGainTablePath, + uint32_t* rxGainTableChecksum); + +/** +* \brief This utility function calculates ADRV9025 Rx Gain table file checksum value +* +* This function calculates the ADRV9025 Rx Gain Table from ARM memory and calculate checksum value +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param rxChannel is Rx channel index +* \param rxGainTableChecksum is Rx gain table checksum information, 32bit +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RxGainTableChecksumCalculate(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint32_t* rxGainTableChecksum); + +/** +* \brief This utility function reads ADRV9025 Tx Atten Table file checksum value +* +* This function reads the ADRV9025 Tx Atten Table file in csv format from a specified location +* (typically in an SD card) and get checksum information, 32bit, hex format, in the last line +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param txAttenTablePath is a string containing path to the Tx atten table in csv format to be programmed +* \param txAttenTableChecksum is Tx atten table checksum information, 32bit +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenTableChecksumRead(adi_adrv9025_Device_t* device, + const char* txAttenTablePath, + uint32_t* txAttenTableChecksum); + +/** +* \brief This utility function calculates ADRV9025 Tx Atten table file checksum value +* +* This function calculates the ADRV9025 Tx Atten Table from ARM memory and calculate checksum value +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param txChannel is a Tx channel index +* \param txAttenTableChecksum is Tx atten table checksum information, 32bit +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_TxAttenTableChecksumCalculate(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + uint32_t* txAttenTableChecksum); + +/** +* \brief This utility function initializes radioctrl parameters +* +* This function performs the following +* -> Sets up the ARM GPIO Pins +* -> Sets up the Radio Ctrl Mode (Pin or SPI mode) for signal chain enable/disable +* -> Initializes PLL frequencies +* -> Enables/Disables Rx and Tx signal chains(only applicable for SPI mode) +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param radioCtrlInit Pointer to ADRV9025 Radioctrl init settings structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_RadioctrlInit(adi_adrv9025_Device_t *device, + adi_adrv9025_RadioctrlInit_t *radioCtrlInit); + +/** +* \brief This utility function gets ADRV9025 API/ARM/Stream version and compares with the expected version +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure containing settings +* \param srcVersion is expected version +* \param result is compared result with bitmask type, Bit0 - API, Bit1 - ARM, Bit2 - Stream, 0 is same and 1 is different +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_adrv9025_ApiArmStreamVersionCompare(adi_adrv9025_Device_t *device, + adi_adrv9025_ApiArmStreamVersions_t *srcVersion, + uint8_t *result); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_ADRV9025_UTILITIES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_utilities_types.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_utilities_types.h new file mode 100644 index 0000000..e363749 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_utilities_types.h @@ -0,0 +1,144 @@ +/*! +* \file adi_adrv9025_utilities_types.h +* \brief Contains ADRV9025 API utility initialization type definitions +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_UTILITIES_TYPES_H_ +#define _ADI_ADRV9025_UTILITIES_TYPES_H_ + +#include +#include "adi_adrv9025_types.h" +#include "adi_adrv9025_tx_types.h" +#include "adi_adrv9025_rx_types.h" +#include "adi_adrv9025_data_interface_types.h" +#include "adi_common_error_types.h" +#include "adi_adrv9025_radioctrl_types.h" +#include "adi_adrv9025_cals_types.h" +#include "adi_adrv9025_arm_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \brief Enum to select AuxDAC compensation mode +*/ +typedef enum adi_adrv9025_AuxDacCompensationMode +{ + ADI_ADRV9025_NO_COMPENSATION = 0x01, /*!< No compensation is applied, requested DAC word is written to device directly */ + ADI_ADRV9025_NO_TEMP_COMPENSATION = 0x02, /*!< No temp compensation is applied, only innaccuracy compensation is applied */ + ADI_ADRV9025_COMPENSATE_WITH_INT_TEMP = 0x03, /*!< Both inaccuracy and temp compensation is enabled. On-board temperature sensor measurement is used for temp compensation*/ + ADI_ADRV9025_COMPENSATE_WITH_EXT_TEMP = 0x04 /*!< Both inaccuracy and temp compensation is enabled. User supplied temperature data is used for temp compensation*/ +} adi_adrv9025_AuxDacCompensationMode_e; + +/** +* \brief Data structure to hold Radio Ctrl Utility Init structures +*/ +typedef struct adi_adrv9025_RadioctrlInit_s +{ + adi_adrv9025_RadioCtrlModeCfg_t radioCtrlModeCfg; /*!< Configuration to hold Radio Ctrl Mode (Pin vs SPI) initialization */ + adi_adrv9025_TxToOrxMappingConfig_t txToOrxMapping; /*!< Configuration to hold Tx to ORx mapping config on initialization (Reqd for Ext LOL cal)*/ + adi_adrv9025_StreamGpioPinCfg_t streamGpioCfg; /*!< Configuration to hold GPIO mappings for the 4 Stream Trigger pin inputs to ADRV9025 */ + uint64_t lo1PllFreq_Hz; /*!< Configuration to hold LO1 PLL frequency on init */ + uint64_t lo2PllFreq_Hz; /*!< Configuration to hold LO2 PLL frequency on init */ + uint64_t auxPllFreq_Hz; /*!< Configuration to hold Aux PLL frequency on init */ +} adi_adrv9025_RadioctrlInit_t; + +/** +* \brief Data structure to hold ADRV9025 AuxDAC Value to be compensated +*/ +typedef struct adi_adrv9025_AuxDacValueToCompensate +{ + adi_adrv9025_AuxDacVoltage_t auxDacValue; /* User supplied AuxDac Value */ + adi_adrv9025_AuxDacCompensationMode_e auxDacValueCompensationMode; /* AuxDac Compensation Mode */ + int16_t extTemperatureDegC; /* User supplied temperature [degC], only used when auxDacValueCompensationMode = ADI_ADRV9025_COMPENSATE_WITH_EXT_TEMP */ +} adi_adrv9025_AuxDacValueToCompensate_t; + +/** +* \brief Data structure to hold Utility Init structures +*/ +typedef struct adi_adrv9025_PostMcsInit_s +{ + adi_adrv9025_RadioctrlInit_t radioCtrlInit; /*!< Radioctrl Initialization configuration */ + adi_adrv9025_InitCals_t initCals; /*!< Cals Initialization configuration */ + char calRsltsFile[ADI_MAX_PATH]; /*!< File containing cal. results for warm-boot */ + uint8_t checkFwVer; /*!< Before warm-boot check f/w ver in cal. rslts matches current f/w */ +} adi_adrv9025_PostMcsInit_t; + +/** +* \brief Data structure to hold Rx Gain Table files to load +*/ +typedef struct adi_adrv9025_RxGainTableFile +{ + char rxGainTableCsvFileName[128]; /*!< Rx Gain Table file name */ + uint32_t rxChannelMask; /*!< Rx Channels to be initialized with the given Rx Gain Table file */ +} adi_adrv9025_RxGainTableFile_t; + +/** +* \brief Data structure to hold Tx Atten Table files to load +*/ +typedef struct adi_adrv9025_TxAttenTableFile +{ + char txAttenTableCsvFileName[128]; /*!< Tx Atten Table file name */ + uint32_t txChannelMask; /*!< Tx Channels to be initialized with the given Tx Atten Table file */ +} adi_adrv9025_TxAttenTableFile_t; + +/** +* \brief Data structure to hold platform file addresses on the SD card +*/ +typedef struct adi_adrv9025_PlatformFiles +{ + char armImageFile[168]; + char streamImageFile[128]; + adi_adrv9025_RxGainTableFile_t rxGainTableFileArr[ADI_ADRV9025_MAX_RX_ONLY + ADI_ADRV9025_MAX_ORX_ONLY]; + uint8_t rxGainTableFileArrSize; + adi_adrv9025_TxAttenTableFile_t txAttenTableFileArr[ADI_ADRV9025_MAX_TXCHANNELS]; + uint8_t txAttenTableFileArrSize; +} adi_adrv9025_PlatformFiles_t; + +/** +* \brief Data Structure to hold stream settings +*/ +typedef struct adi_adrv9025_StreamSettings +{ + uint8_t rxM; /*!< If link sharing, M value for Rx channels */ + uint8_t rxS; /*!< If link sharing, S value for Rx channels */ + uint8_t orxM; /*!< If link sharing, M value for ORx channels */ + uint8_t orxS; /*!< If link sharing, S value for ORx channels */ + adi_adrv9025_AdcSampleXbarCfg_t rxSampleXBar; + adi_adrv9025_AdcSampleXbarCfg_t orxSampleXBar; + uint8_t linkSharing; /*!<1 if link sharing. 0 otherwise */ +} adi_adrv9025_StreamSettings_t; + +/** +* \brief Data Structure to hold stream settings +*/ +typedef struct adi_adrv9025_PinModeSettings +{ + adi_adrv9025_AdcSampleXbarCfg_t sampleXBar[3]; +} adi_adrv9025_PinModeSettings_t; + +/** +* \brief Data Structure to API/ARM/Stream versions +*/ +typedef struct adi_adrv9025_ApiArmStreamVersions +{ + adi_adrv9025_ApiVersion_t apiVersion; + adi_adrv9025_ArmVersion_t armVersion; + adi_adrv9025_StreamVersion_t streamVersion; +} adi_adrv9025_ApiArmStreamVersions_t; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_version.h b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_version.h new file mode 100644 index 0000000..d5e9ec4 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/include/adi_adrv9025_version.h @@ -0,0 +1,30 @@ +/** + * \file adi_adrv9025_version.h + * \brief Contains the version number for the ADRV9025 API + * + * ADRV9025 API version: 6.4.0.14 + */ + + /** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_ADRV9025_VERSION_H_ +#define _ADI_ADRV9025_VERSION_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADI_ADRV9025_CURRENT_MAJOR_VERSION 6 +#define ADI_ADRV9025_CURRENT_MINOR_VERSION 4 +#define ADI_ADRV9025_CURRENT_MAINTENANCE_VERSION 0 +#define ADI_ADRV9025_CURRENT_BUILD_VERSION 14 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025.c new file mode 100644 index 0000000..bda3a00 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025.c @@ -0,0 +1,1374 @@ +/** +* \file adi_adrv9025.c +* \brief Contains Adrv9025 features related function implementation defined in +* adi_adrv9025.h +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "adi_adrv9025.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_error.h" +#include "adi_adrv9025_version.h" +#include "adi_adrv9025_tx.h" +#include "adi_adrv9025_rx.h" +#include "adi_adrv9025_cpu.h" +#include "../../private/include/adrv9025_reg_addr_macros.h" +#include "../../private/include/adrv9025_init.h" +#include "../../private/include/adrv9025_cpu_macros.h" +#include "../../private/include/adrv9025_rx.h" +#include "../../private/include/adrv9025_cpu.h" +#include "../../private/include/adrv9025_bf_core.h" + +#ifdef _RELEASE_BUILD_ + #line __LINE__ "adi_adrv9025.c" +#endif + +int32_t adi_adrv9025_HwOpen(adi_adrv9025_Device_t* device, + adi_adrv9025_SpiSettings_t* spiSettings) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + /* Check for Hal layer functions */ + /* TODO: move section to common layer (add new function) */ + if ((adi_hal_HwOpen == NULL) || (adi_hal_HwClose == NULL) || + (adi_hal_HwReset == NULL) || (adi_hal_SpiInit == NULL) || + (adi_hal_SpiWrite == NULL) || (adi_hal_SpiRead == NULL) || + (adi_hal_LogFileOpen == NULL) || (adi_hal_LogLevelSet == NULL) || + (adi_hal_LogLevelGet == NULL) || (adi_hal_LogWrite == NULL) || + (adi_hal_Wait_us == NULL) || (adi_hal_Wait_ms == NULL) || + (adi_hal_HwVerify == NULL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_HAL_LIBRARY_NOT_AVAILABLE, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Hal library Function pointers not set properlly"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + adi_common_LogLevelSet(&device->common, + ADI_ADRV9025_LOGGING); + + recoveryAction = adi_common_hal_HwOpen(&device->common); + + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + switch (recoveryAction) + { + case ADI_COMMON_HAL_SPI_FAIL: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI error"); + ADI_ERROR_RETURN(device->common.error.newAction); + case ADI_COMMON_HAL_GPIO_FAIL: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_RESET_FEATURE, + NULL, + "GPIO error"); + ADI_ERROR_RETURN(device->common.error.newAction); + case ADI_COMMON_HAL_TIMER_FAIL: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_TIMER, + NULL, + "Timer error"); + ADI_ERROR_RETURN(device->common.error.newAction); + case ADI_COMMON_HAL_GEN_SW: /* fall through */ + default: + printf("ERR: recoveryAction = %d. %s %d\n", recoveryAction, __func__, __LINE__); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Param error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + device->spiSettings.autoIncAddrUp = spiSettings->autoIncAddrUp; + /* Following line is where fpga9025Devic->common.devHalInfo pointer is overwritten */ + device->spiSettings.cmosPadDrvStrength = spiSettings->cmosPadDrvStrength; + device->spiSettings.enSpiStreaming = spiSettings->enSpiStreaming; + device->spiSettings.fourWireMode = spiSettings->fourWireMode; + device->spiSettings.msbFirst = spiSettings->msbFirst; + + /* Toggle RESETB pin, Configure and Verify SPI */ + #if 0 + recoveryAction = adi_adrv9025_HwReset(device); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to reset device and set SPI Config"); + ADI_ERROR_RETURN(device->common.error.newAction); + #endif + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_HwClose(adi_adrv9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADRV9025_BUGINFO(__FUNCTION__); + + recoveryAction = adi_common_hal_HwClose(&device->common); + + + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + switch (recoveryAction) + { + case ADI_COMMON_HAL_SPI_FAIL: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI error"); + ADI_ERROR_RETURN(device->common.error.newAction); + case ADI_COMMON_HAL_GPIO_FAIL: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_RESET_FEATURE, + NULL, + "GPIO error"); + ADI_ERROR_RETURN(device->common.error.newAction); + case ADI_COMMON_HAL_TIMER_FAIL: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_TIMER, + NULL, + "Timer error"); + ADI_ERROR_RETURN(device->common.error.newAction); + case ADI_COMMON_HAL_GEN_SW: /* fall through */ + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Param error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_HwReset(adi_adrv9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + static const uint8_t RESETB_LEVEL_LOW = 0; + static const uint8_t RESETB_LEVEL_HIGH = 1; + static const uint8_t RESETB_WAIT_MS = 250; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADRV9025_BUGINFO(__FUNCTION__); + + /* check that the hardware is available */ + recoveryAction = adi_adrv9025_HwVerify(device); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + return device->common.error.newAction; + } + /* toggle RESETB on device with matching spi chip select index */ + recoveryAction = adi_common_hal_HwReset(&device->common, + RESETB_LEVEL_LOW); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_RESET_FEATURE, + NULL, + "GPIO Reset error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adi_common_hal_Wait_ms(&device->common, + RESETB_WAIT_MS); + + + + + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_TIMER, + NULL, + "Timer error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adi_common_hal_HwReset(&device->common, + RESETB_LEVEL_HIGH); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_RESET_FEATURE, + NULL, + "GPIO Reset error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Configure and Verify Spi */ + recoveryAction = adi_adrv9025_SpiCfgSet(device, + &device->spiSettings); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to set SPI Config"); + ADI_ERROR_RETURN(device->common.error.newAction); + + device->devStateInfo.devState = ADI_ADRV9025_STATE_POWERONRESET; + + return (device->common.error.newAction); +} + +/* +Set Masterbias +*/ +static int32_t adrv9025_MasterBiasSet(adi_adrv9025_Device_t* device) +{ + uint8_t masterbiasConfig0 = 0; + uint8_t masterbiasConfig1 = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADRV9025_BUGINFO(__FUNCTION__); + + /* core.masterbias_config_0 */ + masterbiasConfig0 &= ~ADRV9025_CONFIG_0_PD_MASTERBIAS; + /* trm_vbg_abs */ + masterbiasConfig0 |= ADRV9025_CONFIG_0_TRM_VBG_ABS; + ADRV9025_SPIWRITEBYTE("MASTERBIAS_CONFIG_0", + ADRV9025_ADDR_MASTERBIAS_CONFIG_0, + masterbiasConfig0); + + /* core.masterbias_config_1 */ + /* trm_vbg_tempco */ + masterbiasConfig1 |= ADRV9025_CONFIG_1_TRM_VBG_TEMPCO; + ADRV9025_SPIWRITEBYTE("MASTERBIAS_CONFIG_1", + ADRV9025_ADDR_MASTERBIAS_CONFIG_1, + masterbiasConfig1); + + return (device->common.error.newAction); +} + +/* +Set pad configurations for SYSREF, REFCLK and SYNCB pins +*/ +int32_t adrv9025_PadConfigsSet(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init) +{ + uint8_t sysrefPad = 0; + uint8_t sysrefControl1 = 0; + uint8_t txSyncPad = 0; + uint8_t syncPadSelect = 0; + uint8_t syncPadLvdsMode = 0; + uint8_t syncPadLvdsPnInv = 0; + uint8_t syncDrvSelect = 0; + uint8_t syncPadOnchipTerm = 0; + uint8_t rxSyncPad = 0; + uint8_t rxSync3Pad = 0; + int i = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + init); + + ADRV9025_BUGINFO(__FUNCTION__); + + /* SysRef Configuration */ + /*ADDR_bf.sysref_pad_pd.set(1'b0); 0=Power-up */ + sysrefPad &= ~ADRV9025_SYSREF_PAD_PD; + /*ADDR_bf.sysref_pad_lvds_mode.set(1'b1); LVDS only */ + sysrefPad |= ADRV9025_SYSREF_PAD_LVDS_MODE; + ADRV9025_SPIWRITEBYTE("SYSREF_PAD_CONFIG", + ADRV9025_ADDR_SYSREF_PAD_CONFIG, + sysrefPad); + + /*ADDR_bf.sysref_register_enable.set(1'b1); */ + sysrefControl1 |= ADRV9025_SYSREF_REGISTER_ENABLE; + /*ADDR_bf.sysref_sample_enable.set(1'b0);*/ + sysrefControl1 |= ADRV9025_SYSREF_SAMPLE_ENABLE; + /*ADDR_bf.sysref_buffer_enable.set(1'b1); Enable sysref buffer */ + sysrefControl1 |= ADRV9025_SYSREF_BUFFER_ENABLE; + ADRV9025_SPIWRITEBYTE("SYSREF_CONTROL_1", + ADRV9025_ADDR_SYSREF_CONTROL_1, + sysrefControl1); + + /*SyncB Config */ + /*tx_sync_pad_config */ + for (i = 0; i < ADI_ADRV9025_NUM_DEFRAMERS; i++) + { + if (init->dataInterface.deframer[i].deserializerLanesEnabled != 0) + { + syncPadSelect = init->dataInterface.deframer[i].syncbOutSelect; + syncPadLvdsMode = ((init->dataInterface.deframer[i].syncbOutLvdsMode == 0) ? 0 : 1); + syncPadLvdsPnInv = ((init->dataInterface.deframer[i].syncbOutLvdsPnInvert == 0) ? 0 : 1); + syncDrvSelect = init->dataInterface.deframer[i].syncbOutCmosDriveLevel; + + if (syncPadSelect == 0) + { + /*core.tx_sync1_pad_pd */ + txSyncPad &= ~ADRV9025_TX_SYNC1_PAD_PD; + /*core.tx_sync1_pad_lvds_mode */ + if (syncPadLvdsMode) + { + txSyncPad |= ADRV9025_TX_SYNC1_PAD_LVDS_MODE; + } + + /*core.tx_sync1_pad_lvds_pn_inv */ + if (syncPadLvdsPnInv) + { + txSyncPad |= ADRV9025_TX_SYNC1_PAD_LVSD_PN_INV; + } + + /*core.tx_sync_drv_select */ + txSyncPad |= ADRV9025_BF_ENCODE(syncDrvSelect, + ADRV9025_TX_SYNC_DRV_SELECT_MASK, + ADRV9025_TX_SYNC_DRV_SELECT_SHIFT); + } + else + { + /*core.tx_sync2_pad_pd */ + txSyncPad &= ~ADRV9025_TX_SYNC2_PAD_PD; + /*core.tx_sync2_pad_lvds_mode */ + if (syncPadLvdsMode) + { + txSyncPad |= ADRV9025_TX_SYNC2_PAD_LVDS_MODE; + } + /*core.tx_sync2_pad_lvds_pn_inv */ + if (syncPadLvdsPnInv) + { + txSyncPad |= ADRV9025_TX_SYNC2_PAD_LVSD_PN_INV; + } + + /*core.tx_sync_drv_select */ + txSyncPad |= ADRV9025_BF_ENCODE(syncDrvSelect, + ADRV9025_TX_SYNC_DRV_SELECT_MASK, + ADRV9025_TX_SYNC_DRV_SELECT_SHIFT); + } + } + } + + ADRV9025_SPIWRITEBYTE("TX_SYNC_PAD_CONFIG", + ADRV9025_ADDR_TX_SYNC_PAD_CONFIG, + txSyncPad); + + /*SyncB Config */ + /*Register: core.rx_sync1_2_3_pad_config */ + for (i = 0; i < ADI_ADRV9025_NUM_FRAMERS; i++) + { + if (init->dataInterface.framer[i].serializerLanesEnabled != 0) + { + syncPadSelect = init->dataInterface.framer[i].syncbInSelect; + syncPadLvdsMode = ((init->dataInterface.framer[i].syncbInLvdsMode == 0) ? 0 : 1); + syncPadLvdsPnInv = ((init->dataInterface.framer[i].syncbInLvdsPnInvert == 0) ? 0 : 1); + syncPadOnchipTerm = ((init->dataInterface.framer[i].syncbInLvdsMode == 0) ? 0 : 1); + + if (syncPadSelect == 0) + { + /*core.rx_sync1_pad_pd */ + rxSyncPad &= ~ADRV9025_RX_SYNC1_PAD_PD; + /*core.rx_sync1_pad_lvds_mode */ + if (syncPadLvdsMode) + { + rxSyncPad |= ADRV9025_RX_SYNC1_PAD_LVDS_MODE; + } + + /*core.rx_sync1_pad_lvds_pn_inv */ + if (syncPadLvdsPnInv) + { + rxSyncPad |= ADRV9025_RX_SYNC1_PAD_LVSD_PN_INV; + } + + /*core.rx_sync1_onchip_term */ + if (syncPadOnchipTerm) + { + rxSyncPad |= ADRV9025_RX_SYNC1_PAD_ONCHIP_TERM; + } + } + else if (syncPadSelect == 1) + { + /*core.rx_sync2_pad_pd */ + rxSyncPad &= ~ADRV9025_RX_SYNC2_PAD_PD; + /*core.rx_sync2_pad_lvds_mode */ + if (syncPadLvdsMode) + { + rxSyncPad |= ADRV9025_RX_SYNC2_PAD_LVDS_MODE; + } + + /*core.rx_sync2_pad_lvds_pn_inv */ + if (syncPadLvdsPnInv) + { + rxSyncPad |= ADRV9025_RX_SYNC2_PAD_LVSD_PN_INV; + } + + /*core.rx_sync2_onchip_term */ + if (syncPadOnchipTerm) + { + rxSyncPad |= ADRV9025_RX_SYNC2_PAD_ONCHIP_TERM; + } + } + else + { + /*core.rx_sync3_pad_pd */ + rxSync3Pad &= ~ADRV9025_RX_SYNC3_PAD_PD; + /*core.rx_sync3_pad_lvds_mode */ + if (syncPadLvdsMode) + { + rxSync3Pad |= ADRV9025_RX_SYNC3_PAD_LVDS_MODE; + } + + /*core.rx_sync3_pad_lvds_pn_inv */ + if (syncPadLvdsPnInv) + { + rxSync3Pad |= ADRV9025_RX_SYNC3_PAD_LVSD_PN_INV; + } + + /*core.rx_sync3_onchip_term */ + if (syncPadOnchipTerm) + { + rxSync3Pad |= ADRV9025_RX_SYNC3_PAD_ONCHIP_TERM; + } + } + } + } + + ADRV9025_SPIWRITEBYTE("RX_SYNC12_PAD_CONFIG", + ADRV9025_ADDR_RX_SYNC12_PAD_CONFIG, + rxSyncPad); + + ADRV9025_SPIWRITEBYTE("RX_SYNC3_PAD_CONFIG", + ADRV9025_ADDR_RX_SYNC3_PAD_CONFIG, + rxSync3Pad); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_Initialize(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init) +{ + uint32_t i = 0; + uint32_t txMaskArray[ADI_ADRV9025_MAX_TXCHANNELS] = {ADI_ADRV9025_TX1, ADI_ADRV9025_TX2, ADI_ADRV9025_TX3, ADI_ADRV9025_TX4}; + uint32_t rxMaskArray[ADI_ADRV9025_MAX_RXCHANNELS] = { + ADI_ADRV9025_RX1, + ADI_ADRV9025_RX2, + ADI_ADRV9025_RX3, + ADI_ADRV9025_RX4, + ADI_ADRV9025_ORX1, + ADI_ADRV9025_ORX2, + ADI_ADRV9025_ORX3, + ADI_ADRV9025_ORX4, + ADI_ADRV9025_LB12, + ADI_ADRV9025_LB34 + }; + + adi_adrv9025_Info_t devStateInfoClear = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + init); + + /* Restore silicon revision from current device structure */ + devStateInfoClear.deviceSiRev = device->devStateInfo.deviceSiRev; + + ADRV9025_BUGINFO(__FUNCTION__); + + device->devStateInfo = devStateInfoClear; + + adrv9025_CpuInitialize(device); + + + + adrv9025_MasterBiasSet(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Disable stream pin mode until after streams are loaded */ + /* Disable Tx pin mode for all Tx and Rx channels, ORx was defaulted with pin mode disabled */ + ADRV9025_SPIWRITEBYTE("TXALL_BBIC_ENABLE", + ADRV9025_ADDR_TXALL_BBIC_ENABLE, + 0x00); + ADRV9025_SPIWRITEBYTE("RXALL_BBIC_ENABLE", + ADRV9025_ADDR_RXALL_BBIC_ENABLE, + 0x00); + + adrv9025_LdoEnable(device, + init->clocks.ldoSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_PadConfigsSet(device, + init); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_adrv9025_ProfilesVerify(device, + init); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_ClocksSet(device, + init); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Program FIR filters */ + if (device->devStateInfo.profilesValid & ADI_ADRV9025_TX_PROFILE_VALID) + { + for (i = 0; i < ADI_ADRV9025_MAX_TXCHANNELS; i++) + { + if (ADRV9025_BF_EQUAL(init->tx.txInitChannelMask, + txMaskArray[i])) + { + device->devStateInfo.initializedChannels |= (txMaskArray[i] << ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET); + + if (init->tx.txChannelCfg[i].profile.txFir.numFirCoefs > 0) + { + adi_adrv9025_TxFirWrite(device, + txMaskArray[i], + init->tx.txChannelCfg[i].profile.txFir.gain_dB, + init->tx.txChannelCfg[i].profile.txFir.numFirCoefs, + &init->tx.txChannelCfg[i].profile.txFir.coefs[0], + ADI_ADRV9025_MAX_TXPFIR_COEFS); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + } + + if (device->devStateInfo.profilesValid & ADI_ADRV9025_RX_PROFILE_VALID) + { + for (i = 0; i < ADI_ADRV9025_MAX_RX_ONLY; i++) + { + if (ADRV9025_BF_EQUAL(init->rx.rxInitChannelMask, + rxMaskArray[i])) + { + device->devStateInfo.initializedChannels |= rxMaskArray[i]; + + if (init->rx.rxChannelCfg[i].profile.rxFir.numFirCoefs > 0) + { + adi_adrv9025_RxFirWrite(device, + rxMaskArray[i], + init->rx.rxChannelCfg[i].profile.rxFir.gain_dB, + init->rx.rxChannelCfg[i].profile.rxFir.numFirCoefs, + &init->rx.rxChannelCfg[i].profile.rxFir.coefs[0], + ADI_ADRV9025_MAX_RXPFIR_COEFS); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + for (i = 0; i < ADI_ADRV9025_MAX_RXCHANNELS; i++) + { + device->devStateInfo.rxOutputRate_kHz[i] = init->rx.rxChannelCfg[i].profile.rxOutputRate_kHz; + device->devStateInfo.rxRfBandWidth_kHz[i] = init->rx.rxChannelCfg[i].profile.rfBandwidth_kHz; + } + } + + if (device->devStateInfo.profilesValid & ADI_ADRV9025_ORX_PROFILE_VALID) + { + for (i = ADI_ADRV9025_MAX_RX_ONLY; i < ADI_ADRV9025_MAX_LB_CHANNEL_START; i++) + { + if (ADRV9025_BF_EQUAL(init->rx.rxInitChannelMask, + rxMaskArray[i])) + { + device->devStateInfo.initializedChannels |= rxMaskArray[i]; + + if (init->rx.rxChannelCfg[i].profile.rxFir.numFirCoefs > 0) + { + adi_adrv9025_RxFirWrite(device, + rxMaskArray[i], + init->rx.rxChannelCfg[i].profile.rxFir.gain_dB, + init->rx.rxChannelCfg[i].profile.rxFir.numFirCoefs, + &init->rx.rxChannelCfg[i].profile.rxFir.coefs[0], + ADI_ADRV9025_MAX_RXPFIR_COEFS); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + } + + if (device->devStateInfo.profilesValid & ADI_ADRV9025_LB_PROFILE_VALID) + { + for (i = ADI_ADRV9025_MAX_LB_CHANNEL_START; i < ADI_ADRV9025_MAX_RXCHANNELS; i++) + { + if (ADRV9025_BF_EQUAL(init->rx.rxInitChannelMask, + rxMaskArray[i]) && + (init->rx.rxChannelCfg[i].profile.rxFir.numFirCoefs > 0)) + { + device->devStateInfo.initializedChannels |= rxMaskArray[i]; + adi_adrv9025_RxFirWrite(device, + rxMaskArray[i], + init->rx.rxChannelCfg[i].profile.rxFir.gain_dB, + init->rx.rxChannelCfg[i].profile.rxFir.numFirCoefs, + &init->rx.rxChannelCfg[i].profile.rxFir.coefs[0], + ADI_ADRV9025_MAX_RXPFIR_COEFS); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + device->devStateInfo.devState = (adi_adrv9025_ApiStates_e)(device->devStateInfo.devState | ADI_ADRV9025_STATE_INITIALIZED); + + device->devStateInfo.linkSharingEnabled = init->dataInterface.linkSharingCfg.linkSharingEnabled; + + if (device->devStateInfo.profilesValid & ADI_ADRV9025_TX_PROFILE_VALID) + { + for (i = 0; i < ADI_ADRV9025_MAX_TXCHANNELS; i++) + { + device->devStateInfo.txInputRate_kHz[i] = init->tx.txChannelCfg[i].profile.txInputRate_kHz; + device->devStateInfo.txRfBandWidth_kHz[i] = init->tx.txChannelCfg[i].profile.rfBandwidth_kHz; + } + } + + /* + * Save some JESD Profile configuration into devStateInfo + */ + for (i = 0; i < ADI_ADRV9025_NUM_FRAMERS; i++) + { + device->devStateInfo.jesdCfg.framerCfg[i].enableJesd204C = init->dataInterface.framer[i].enableJesd204C; + device->devStateInfo.jesdCfg.framerCfg[i].serializerLanesEnabled = init->dataInterface.framer[i].serializerLanesEnabled; + } + + for (i = 0; i < ADI_ADRV9025_NUM_DEFRAMERS; i++) + { + device->devStateInfo.jesdCfg.deframerCfg[i].enableJesd204C = init->dataInterface.deframer[i].enableJesd204C; + device->devStateInfo.jesdCfg.deframerCfg[i].deserializerLanesEnabled = init->dataInterface.deframer[i].deserializerLanesEnabled; + printf("deframer_%d: 204cStatus: %d, enableLane: %X\n", i, + device->devStateInfo.jesdCfg.deframerCfg[i].enableJesd204C, + device->devStateInfo.jesdCfg.deframerCfg[i].deserializerLanesEnabled); + } + + device->devStateInfo.extDpdCaptureTriggerGpio = ADI_ADRV9025_GPIO_INVALID; + + device->devStateInfo.extDpdLutSwapModeEn = (uint8_t)0; + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_Shutdown(adi_adrv9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADRV9025_BUGINFO(__FUNCTION__); + + recoveryAction = adi_adrv9025_HwReset(device); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to reset device"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_MultichipSyncSet(adi_adrv9025_Device_t* device, + uint8_t enableSync) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t payload[4] = {0}; + uint8_t cmdStatusByte = 0; + static const uint8_t ARM_ERR_MASK = 0x0E; + uint8_t mcsDonePayload[1] = { ADRV9025_CPU_OBJECTID_MCS_DONE }; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADRV9025_BUGINFO(__FUNCTION__); + + payload[0] = ADRV9025_CPU_OBJECTID_MCS; + payload[1] = 0; + payload[2] = 0; + payload[3] = 0; + + if (enableSync > 0) + { + recoveryAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_SET_OPCODE, + &payload[0], + 4); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to send ARM command"); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_SET_OPCODE, + &cmdStatusByte, + ADI_ADRV9025_SETCPUBOOTUPMCS_TIMEOUT_US, + ADI_ADRV9025_SETCPUBOOTUPMCS_INTERVAL_US); + + + + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((cmdStatusByte & ARM_ERR_MASK) > 0) + { + adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + ADI_ADRV9025_SRC_CPUCMD, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_MCS, + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* MCS Fix Clear ARM_M3_RUN */ + adrv9025_CoreArmM3RunBfSet(device, + ADRV9025_BF_CORE, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* MCS Fix Set ARM_M3_RUN */ + adrv9025_CoreArmM3RunBfSet(device, + ADRV9025_BF_CORE, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Send MCS done command to ARM */ + recoveryAction = adi_adrv9025_CpuCmdWrite(device, ADI_ADRV9025_CPU_TYPE_C, (uint8_t)ADRV9025_CPU_SET_OPCODE, &mcsDonePayload[0], sizeof(mcsDonePayload)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, mcsDonePayload, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_SET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_SETMCS_DONE_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_SETMCS_DONE_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte & ARM_ERR_MASK) > 0) + { + recoveryAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + ADI_ADRV9025_SRC_CPUCMD, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, mcsDonePayload[0], cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + cmdStatusByte, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_MultichipSyncStatusGet(adi_adrv9025_Device_t* device, + uint32_t* mcsStatus) +{ + uint8_t mcsStatusRead = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + mcsStatus); + + ADRV9025_BUGINFO(__FUNCTION__); + + ADRV9025_SPIREADBYTE("CLK_PLL_MCS_CONTROL_3", + ADRV9025_ADDR_CLK_PLL + ADRV9025_ADDR_MCS_CONTROL_3_OFFSET, + &mcsStatusRead); + + *mcsStatus = (uint32_t)mcsStatusRead; + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ProfilesVerify(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + init); + + recoveryAction = adrv9025_ProfilesVerify(device, + init); + ADI_ERROR_RETURN(device->common.error.newAction); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "ADRV9025 Profiles are invalid"); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_SpiCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_SpiSettings_t* spi) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t spiConfigA = 0; + uint8_t spiConfigB = 0; + uint8_t ioControl = 0; + static const uint8_t SPICFG_MSBFIRST_OFF = 0; + static const uint8_t SPICFG_AUTOINC_DOWN = 0; + static const uint8_t SPICFG_FOURWIREMODE_OFF = 0; + static const uint8_t SPICFG_ENSPISTREAMING_OFF = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + spi); + + ADRV9025_BUGINFO(__FUNCTION__); + + if ((spi->cmosPadDrvStrength != ADI_ADRV9025_CMOSPAD_DRV_WEAK) && + (spi->cmosPadDrvStrength != ADI_ADRV9025_CMOSPAD_DRV_STRONG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + spi->cmosPadDrvStrength, + "Invalid Cmos Pad Drive Strength\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* core.spi_interface_config_A */ + /* SPI bit is 1 = LSB first */ + if (spi->msbFirst == SPICFG_MSBFIRST_OFF) + { + spiConfigA |= ADRV9025_CONFIG_A_SPI_LSB_FIRST; + } + + if (spi->autoIncAddrUp != SPICFG_AUTOINC_DOWN) + { + spiConfigA |= ADRV9025_CONFIG_A_SPI_ADDR_ASCENSION; + } + + if (spi->fourWireMode != SPICFG_FOURWIREMODE_OFF) + { + spiConfigA |= ADRV9025_CONFIG_A_SPI_SDO_ACTIVE; + } + + ADRV9025_SPIWRITEBYTE("SPI_INTERFACE_CONFIG_A", + ADRV9025_ADDR_SPI_INTERFACE_CONFIG_A, + spiConfigA); + + if (spi->cmosPadDrvStrength == ADI_ADRV9025_CMOSPAD_DRV_STRONG) + { + ioControl |= ADRV9025_IO_CONTROL_SPI_OUTS_DRV_SEL; + } + + /* Force PAD mode */ + ADRV9025_SPIWRITEBYTE("DIGITAL_IO_CONTROL", + ADRV9025_ADDR_DIGITAL_IO_CONTROL, + ioControl); + + /* core.spi_interface_config_B */ + if (spi->enSpiStreaming == SPICFG_ENSPISTREAMING_OFF) + { + spiConfigB |= ADRV9025_CONFIG_B_SINGLE_INSTRUCTION; + } + + /* Force single instruction mode */ + ADRV9025_SPIWRITEBYTE("SPI_INTERFACE_CONFIG_B", + ADRV9025_ADDR_SPI_INTERFACE_CONFIG_B, + spiConfigB); + + recoveryAction = adi_adrv9025_SpiVerify(device); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "SPI Verify failed"); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_SpiCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_SpiSettings_t* spi) +{ + uint8_t spiConfigA = 0; + uint8_t spiConfigB = 0; + uint8_t ioControl = 0; + static const uint8_t SPICFG_MSBFIRST_OFF = 0; + static const uint8_t SPICFG_AUTOINC_DOWN = 0; + static const uint8_t SPICFG_FOURWIREMODE_OFF = 0; + static const uint8_t SPICFG_ENSPISTREAMING_OFF = 0; + static const uint8_t SPICFG_MSBFIRST_ON = 1; + static const uint8_t SPICFG_AUTOINC_UP = 1; + static const uint8_t SPICFG_FOURWIREMODE_ON = 1; + static const uint8_t SPICFG_ENSPISTREAMING_ON = 1; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + spi); + + ADRV9025_BUGINFO(__FUNCTION__); + + ADRV9025_SPIREADBYTE("SPI_INTERFACE_CONFIG_A", + ADRV9025_ADDR_SPI_INTERFACE_CONFIG_A, + &spiConfigA); + + /* core.spi_interface_config_A */ + /* SPI bit is 1 = LSB first */ + if (ADRV9025_BF_EQUAL(spiConfigA, + ADRV9025_CONFIG_A_SPI_LSB_FIRST)) + { + spi->msbFirst = SPICFG_MSBFIRST_OFF; + } + else + { + spi->msbFirst = SPICFG_MSBFIRST_ON; + } + + if (ADRV9025_BF_EQUAL(spiConfigA, + ADRV9025_CONFIG_A_SPI_ADDR_ASCENSION)) + { + spi->autoIncAddrUp = SPICFG_AUTOINC_UP; + } + else + { + spi->autoIncAddrUp = SPICFG_AUTOINC_DOWN; + } + + if (ADRV9025_BF_EQUAL(spiConfigA, + ADRV9025_CONFIG_A_SPI_SDO_ACTIVE)) + { + spi->fourWireMode = SPICFG_FOURWIREMODE_ON; + } + else + { + spi->fourWireMode = SPICFG_FOURWIREMODE_OFF; + } + + /* Read PAD mode */ + ADRV9025_SPIREADBYTE("DIGITAL_IO_CONTROL", + ADRV9025_ADDR_DIGITAL_IO_CONTROL, + &ioControl); + + if (ADRV9025_BF_EQUAL(ioControl, + ADRV9025_IO_CONTROL_SPI_OUTS_DRV_SEL)) + { + spi->cmosPadDrvStrength = ADI_ADRV9025_CMOSPAD_DRV_STRONG; + } + else + { + spi->cmosPadDrvStrength = ADI_ADRV9025_CMOSPAD_DRV_WEAK; + } + + /* Read single instruction mode */ + ADRV9025_SPIREADBYTE("SPI_INTERFACE_CONFIG_B", + ADRV9025_ADDR_SPI_INTERFACE_CONFIG_B, + &spiConfigB); + + /* core.spi_interface_config_B */ + if (ADRV9025_BF_EQUAL(spiConfigB, + ADRV9025_CONFIG_B_SINGLE_INSTRUCTION)) + { + spi->enSpiStreaming = SPICFG_ENSPISTREAMING_OFF; + } + else + { + spi->enSpiStreaming = SPICFG_ENSPISTREAMING_ON; + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_SpiVerify(adi_adrv9025_Device_t* device) +{ + uint8_t spiReg = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADRV9025_BUGINFO(__FUNCTION__); + + static const uint8_t SCRATCH_PAD_1 = 0xB6; /* DATA 10110110 */ + static const uint8_t SCRATCH_PAD_2 = 0x49; /* DATA 01001001*/ + static const uint8_t VENDOR_ID_0 = 0x56; + static const uint8_t VENDOR_ID_1 = 0x04; + + /* check that the hardware is available */ + int32_t recoveryAction = adi_adrv9025_HwVerify(device); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + return device->common.error.newAction; + } + + /* Check SPI read - VENDOR_ID_0 */ + ADRV9025_SPIREADBYTE("VENDOR_ID_0", + ADRV9025_ADDR_VENDOR_ID_0, + &spiReg); + + if (spiReg != VENDOR_ID_0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + spiReg, + "Cannot read from a low SPI address\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check SPI read - VENDOR_ID_1 */ + spiReg = 0; + ADRV9025_SPIREADBYTE("VENDOR_ID_1", + ADRV9025_ADDR_VENDOR_ID_1, + &spiReg); + + + + if (spiReg != VENDOR_ID_1) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + spiReg, + "Cannot read from a low SPI address\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check SPI write - SCRATCHPAD : Data = 10110110 */ + spiReg = 0; + ADRV9025_SPIWRITEBYTE("SCRATCH_PAD", + ADRV9025_ADDR_SCRATCH_PAD, + SCRATCH_PAD_1); + + ADRV9025_SPIREADBYTE("SCRATCH_PAD", + ADRV9025_ADDR_SCRATCH_PAD, + &spiReg); + + + + if (spiReg != SCRATCH_PAD_1) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + spiReg, + "Cannot write to a low SPI address\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check SPI write - SCRATCHPAD : Data = 01001001 */ + spiReg = 0; + ADRV9025_SPIWRITEBYTE("SCRATCH_PAD", + ADRV9025_ADDR_SCRATCH_PAD, + SCRATCH_PAD_2); + + ADRV9025_SPIREADBYTE("SCRATCH_PAD", + ADRV9025_ADDR_SCRATCH_PAD, + &spiReg); + + + + if (spiReg != SCRATCH_PAD_2) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + spiReg, + "Cannot write to a low SPI address\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check SPI write - SCRATCH_PAD_UPPER_ADDRESS_SPACE : Data = 10110110 */ + spiReg = 0; + ADRV9025_SPIWRITEBYTE("SCRATCH_PAD_UPPER", + ADRV9025_ADDR_SCRATCH_PAD_UPPER_ADDRESS_SPACE, + SCRATCH_PAD_1); + + ADRV9025_SPIREADBYTE("SCRATCH_PAD_UPPER", + ADRV9025_ADDR_SCRATCH_PAD_UPPER_ADDRESS_SPACE, + &spiReg); + + + + if (spiReg != SCRATCH_PAD_1) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + spiReg, + "Cannot write to a high SPI address\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check SPI write - SCRATCH_PAD_UPPER_ADDRESS_SPACE : Data = 01001001 */ + spiReg = 0; + ADRV9025_SPIWRITEBYTE("SCRATCH_PAD_UPPER_ADDR", + ADRV9025_ADDR_SCRATCH_PAD_UPPER_ADDRESS_SPACE, + SCRATCH_PAD_2); + + ADRV9025_SPIREADBYTE("SCRATCH_PAD_UPPER_ADDR", + ADRV9025_ADDR_SCRATCH_PAD_UPPER_ADDRESS_SPACE, + &spiReg); + + + + if (spiReg != SCRATCH_PAD_2) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + spiReg, + "Cannot write to a high SPI address\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* TODO: Add code to check Spi Streaming when HAL support is available. */ + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ApiVersionGet(adi_adrv9025_Device_t* device, + adi_adrv9025_ApiVersion_t* apiVersion) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + apiVersion); + + ADRV9025_BUGINFO(__FUNCTION__); + + apiVersion->majorVer = ADI_ADRV9025_CURRENT_MAJOR_VERSION; + apiVersion->minorVer = ADI_ADRV9025_CURRENT_MINOR_VERSION; + apiVersion->maintenanceVer = ADI_ADRV9025_CURRENT_MAINTENANCE_VERSION; + apiVersion->buildVer = ADI_ADRV9025_CURRENT_BUILD_VERSION; + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DeviceRevGet(adi_adrv9025_Device_t* device, + uint8_t* siRevision) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + siRevision); + + ADRV9025_BUGINFO(__FUNCTION__); + + ADRV9025_SPIREADBYTE("PRODUCT_ID_1", + ADRV9025_ADDR_PRODUCT_ID_1, + siRevision); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ProductIdGet(adi_adrv9025_Device_t* device, + uint8_t* productId) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + productId); + + ADRV9025_BUGINFO(__FUNCTION__); + + ADRV9025_SPIREADBYTE("PRODUCT_ID_0", + ADRV9025_ADDR_PRODUCT_ID_0, + productId); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DeviceCapabilityGet(adi_adrv9025_Device_t* device, + adi_adrv9025_CapabilityModel_t* devCapability) +{ + uint8_t productId = 0; + uint8_t siRevision = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + devCapability); + + ADRV9025_SPIREADBYTE("PRODUCT_ID_0", + ADRV9025_ADDR_PRODUCT_ID_0, + &productId); + ADRV9025_SPIREADBYTE("PRODUCT_ID_1", + ADRV9025_ADDR_PRODUCT_ID_1, + &siRevision); + + /* set devCapability to default settings */ + devCapability->productId = productId; + devCapability->siRevision = siRevision; + devCapability->txNumber = 4; + devCapability->rxNumber = 4; + devCapability->orxNumber = 4; + devCapability->txChannelMask = ADI_ADRV9025_TXALL; + devCapability->rxChannelMask = ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4; + devCapability->orxChannelMask = ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2 | ADI_ADRV9025_ORX3 | ADI_ADRV9025_ORX4; + devCapability->featureMask = ADI_ADRV9025_FEATUREALL; + devCapability->txMaxBw_kHz = 450000; + devCapability->rxMaxBw_kHz = 200000; + devCapability->orxMaxBw_kHz = 450000; + devCapability->rfFreqRangeMin_kHz = 400000; + devCapability->rfFreqRangeMax_kHz = 6000000; + devCapability->serializerLaneEnableMask = ADI_ADRV9025_ALL_LANES_ENABLED; + devCapability->deserializerLaneEnableMask = ADI_ADRV9025_ALL_LANES_ENABLED; + + /* productId mapping */ + switch (productId) + { + case 0x80: + devCapability->featureMask = ADI_ADRV9025_FEATUREALL; + break; + case 0x81: + devCapability->featureMask = devCapability->featureMask & ~(ADI_ADRV9025_FEATURE_RESERVED1 | ADI_ADRV9025_FEATURE_RESERVED2); + break; + case 0x82: + devCapability->featureMask = devCapability->featureMask & ~(ADI_ADRV9025_FEATURE_CFR | ADI_ADRV9025_FEATURE_DPD | ADI_ADRV9025_FEATURE_RESERVED1 | + ADI_ADRV9025_FEATURE_RESERVED2); + break; + case 0x83: + devCapability->featureMask = devCapability->featureMask & ~(ADI_ADRV9025_FEATURE_CFR | ADI_ADRV9025_FEATURE_RESERVED2); + break; + case 0x84: + devCapability->featureMask = devCapability->featureMask & ~(ADI_ADRV9025_FEATURE_RESERVED1 | ADI_ADRV9025_FEATURE_RESERVED2); + break; + case 0x85: + devCapability->featureMask = devCapability->featureMask & ~(ADI_ADRV9025_FEATURE_RESERVED1 | ADI_ADRV9025_FEATURE_RESERVED2); + break; + case 0x86: + devCapability->featureMask = devCapability->featureMask & ~(ADI_ADRV9025_FEATURE_RESERVED1 | ADI_ADRV9025_FEATURE_RESERVED2); + break; + case 0x87: + devCapability->featureMask = devCapability->featureMask & ~(ADI_ADRV9025_FEATURE_RESERVED1 | ADI_ADRV9025_FEATURE_RESERVED2 | ADI_ADRV9025_FEATURE_CFR | ADI_ADRV9025_FEATURE_DPD); + break; + case 0x88: + devCapability->featureMask = devCapability->featureMask & ~(ADI_ADRV9025_FEATURE_RESERVED2); + break; + + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "No ProductId found in Capability Model"); + break; + } + + return (device->common.error.newAction); +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_agc.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_agc.c new file mode 100644 index 0000000..a11ecc8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_agc.c @@ -0,0 +1,1980 @@ +/** +* \file adi_adrv9025_agc.c +* \brief Contains AGC features related function implementation defined in +* adi_adrv9025_agc.h +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "adi_adrv9025_agc.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_error.h" +#include "adi_adrv9025.h" +#include "adi_adrv9025_gpio.h" +#include "../../private/include/adrv9025_bf_rx.h" +#include "../../private/include/adrv9025_bf_analog_rx_mem_map.h" +#include "../../private/include/adrv9025_init.h" +#include "../../private/include/adrv9025_reg_addr_macros.h" +#include "../../private/include/adrv9025_cpu_macros.h" +#include "../../private/include/adrv9025_shared_resource_manager.h" + +#ifdef _RELEASE_BUILD_ + #line __LINE__ "adi_adrv9025_agc.c" +#endif + +int32_t adi_adrv9025_AgcCfgSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_AgcCfg_t agcConfig[], + uint8_t arraySize) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + static const uint8_t MINIMUM_NUM_AGC_CONFIGS = 1; + static const uint8_t MAXIMUM_NUM_AGC_CONFIGS = 4; + static const uint8_t AGC_PEAK_WAIT_TIME_MAX = 0x1F; + static const uint32_t AGC_GAIN_UPDATE_COUNTER_MAX = 0x003FFFFF; + static const uint8_t UNDER_RANGE_HIGH_POWER_THRESH_MAX = 0x7F; + static const uint8_t UNDER_RANGE_LOW_POWER_THRESH_MAX = 0x1F; + static const uint8_t UNDER_RANGE_HIGH_POWER_GAIN_STEP_RECOVERY_MAX = 0x1F; + static const uint8_t UNDER_RANGE_LOW_POWER_GAIN_STEP_RECOVERY_MAX = 0x1F; + static const uint8_t POWER_MEASUREMENT_DURATION_MAX = 0x1F; + static const uint8_t AGC_SLOW_LOOP_SETTLING_DELAY_MAX = 0x7F; + static const uint8_t APD_HIGH_THRESH_MAX = 0x3F; + static const uint8_t APD_LOW_GAIN_MODE_HIGH_THRESH_MAX = 0x3F; + static const uint8_t APD_LOW_THRESH_MAX = 0x3F; + static const uint8_t APD_LOW_GAIN_MODE_LOW_THRESH_MAX = 0x3F; + static const uint8_t APD_LOW_GAIN_STEP_ATTACK_MAX = 0x1F; + static const uint8_t APD_GAIN_STEP_RECOVERY_MAX = 0x1F; + static const uint8_t HB2_OVER_LOAD_DURATION_CNT_MAX = 0x07; + static const uint8_t HB2_OVER_LOAD_THRESH_CNT_MAX = 0x0F; + static const uint16_t HB2_HIGH_THRESH_MAX = 0x3FFF; + static const uint16_t HB2_UNDER_RANGE_LOW_THRESH_MAX = 0x3FFF; + static const uint16_t HB2_UNDER_RANGE_MID_THRESH_MAX = 0x3FFF; + static const uint16_t HB2_UNDER_RANGE_HIGH_THRESH_MAX = 0x3FFF; + static const uint8_t HB2_GAIN_STEP_HIGH_RECOVERY_MAX = 0x1F; + static const uint8_t HB2_GAIN_STEP_LOW_RECOVERY_MAX = 0x1F; + static const uint8_t HB2_GAIN_STEP_ATTACK_MAX = 0x1F; + static const uint8_t HB2_GAIN_STEP_MID_RECOVERY_MAX = 0x1F; + static const uint8_t HB2_THRESH_CONFIG = 0x03; + static const uint8_t OVER_RANGE_HIGH_POWER_THRESH_MID_RECOVERY_MAX = 0x7F; + static const uint8_t OVER_RANGE_LOW_POWER_THRESH_MID_RECOVERY_MAX = 0x0F; + static const uint8_t OVER_RANGE_HIGH_POWER_GAIN_STEP_ATTACK_MAX = 0x1F; + static const uint8_t OVER_RANGE_LOW_POWER_GAIN_STEP_ATTACK_MAX = 0x1F; + static const uint8_t POWER_INPUT_SELECT_MAX = 0x03; + static const uint8_t AGC_CHANGE_GAIN_IF_THRESH_HIGH_MAX = 0x03; + static const uint8_t AGC_RX_ATTACK_DELAY_MAX = 0x3F; + static const uint8_t AGC_UNDER_RANGE_MID_INTERVAL_MAX = 0x3F; + static const uint8_t AGC_UNDER_RANGE_HIGH_INTERVAL_MAX = 0x3F; + static const uint8_t AGC_ENABLE_MAX = 0x01; + static const uint8_t AGC_RXCHANNEL_MAX = 0x0F; + + uint8_t configIndex = 0; + uint8_t i = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, agcConfig); + + if (arraySize < MINIMUM_NUM_AGC_CONFIGS) + { + /* invalid number of configs */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + arraySize, + "Invalid number of AGC configs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (arraySize > MAXIMUM_NUM_AGC_CONFIGS) + { + /* Unexpected number of configs */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_WARN_CHECK_PARAM, + arraySize, + "WARNING: Number of AGC configs is larger than expected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (configIndex = 0; configIndex < arraySize; configIndex++) + { + uint32_t rxChannelMask = agcConfig[configIndex].rxChannelMask; + if ((rxChannelMask > AGC_RXCHANNEL_MAX) || (rxChannelMask == 0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "Invalid rxChannelMask. Valid range (1/2/4/8/15)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_ADRV9025_MAX_RX_ONLY; i++) + { + if ((rxChannelMask & ADI_ADRV9025_RX1) == ADI_ADRV9025_RX1) + { + rxChannelMask &= ~ADI_ADRV9025_RX1; + + /* range check the gain against the max and min expected values */ + if ((agcConfig[configIndex].agcRxMaxGainIndex > device->devStateInfo.gainIndexes.rx1MaxGainIndex) + || (agcConfig[configIndex].agcRxMinGainIndex < device->devStateInfo.gainIndexes.rx1MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Gain index less than minimum index or greater than maximum gain index"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else if ((rxChannelMask & ADI_ADRV9025_RX2) == ADI_ADRV9025_RX2) + { + rxChannelMask &= ~ADI_ADRV9025_RX2; + /* range check the gain against the max and min expected values */ + if ((agcConfig[configIndex].agcRxMaxGainIndex > device->devStateInfo.gainIndexes.rx2MaxGainIndex) + || (agcConfig[configIndex].agcRxMinGainIndex < device->devStateInfo.gainIndexes.rx2MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Gain index less than minimum index or greater than maximum gain index"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else if ((rxChannelMask & ADI_ADRV9025_RX3) == ADI_ADRV9025_RX3) + { + rxChannelMask &= ~ADI_ADRV9025_RX3; + /* range check the gain against the max and min expected values */ + if ((agcConfig[configIndex].agcRxMaxGainIndex > device->devStateInfo.gainIndexes.rx3MaxGainIndex) + || (agcConfig[configIndex].agcRxMinGainIndex < device->devStateInfo.gainIndexes.rx3MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Gain index less than minimum index or greater than maximum gain index"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else if ((rxChannelMask & ADI_ADRV9025_RX4) == ADI_ADRV9025_RX4) + { + rxChannelMask &= ~ADI_ADRV9025_RX4; + /* range check the gain against the max and min expected values */ + if ((agcConfig[configIndex].agcRxMaxGainIndex > device->devStateInfo.gainIndexes.rx4MaxGainIndex) + || (agcConfig[configIndex].agcRxMinGainIndex < device->devStateInfo.gainIndexes.rx4MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Gain index less than minimum index or greater than maximum gain index"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else + { + break; + } + + /* performing range check for gain update time */ + if (agcConfig[configIndex].agcGainUpdateCounter > AGC_GAIN_UPDATE_COUNTER_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcGainUpdateCounter out of range (0-4194303)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* performing AGC peak wait time value check */ + if (agcConfig[configIndex].agcPeakWaitTime > AGC_PEAK_WAIT_TIME_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeakWaitTime is out of range (0-31)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcRxAttackDelay > AGC_RX_ATTACK_DELAY_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcRxAttackDelay out of range (0-63)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* AGC Control register checks and write */ + if (agcConfig[configIndex].agcLowThreshPreventGainInc > AGC_ENABLE_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcLowThreshPreventGainInc out of range (0-1)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcChangeGainIfThreshHigh > AGC_CHANGE_GAIN_IF_THRESH_HIGH_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcChangeGainIfThreshHigh out of range (0-3)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeakThreshGainControlMode > AGC_ENABLE_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeakThreshGainControlMode out of range (0-1)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcResetOnRxon > AGC_ENABLE_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcResetOnRxon out of range (0-1)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcEnableSyncPulseForGainCounter > AGC_ENABLE_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcEnableSyncPulseForGainCounter out of range (0-1)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcEnableFastRecoveryLoop > AGC_ENABLE_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcEnableFastRecoveryLoop out of range (0-1)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcSlowLoopSettlingDelay > AGC_SLOW_LOOP_SETTLING_DELAY_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcSlowLoopSettlingDelay out of range (0-127)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Agc Peak */ + /* performing range check for gain update time */ + if (agcConfig[configIndex].agcPeak.agcUnderRangeMidInterval > AGC_UNDER_RANGE_MID_INTERVAL_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.agcUnderRangeMidInterval is out of range (0-63)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.agcUnderRangeHighInterval > AGC_UNDER_RANGE_HIGH_INTERVAL_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.agcUnderRangeHighInterval is out of range (0-63)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.apdHighThresh > APD_HIGH_THRESH_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.apdHighThresh out of range (0-63)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.apdLowGainModeHighThresh > APD_LOW_GAIN_MODE_HIGH_THRESH_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.apdLowGainModeHighThresh out of range (0-63)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.apdLowThresh > APD_LOW_THRESH_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.apdLowThresh out of range (0-63)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.apdLowGainModeLowThresh > APD_LOW_GAIN_MODE_LOW_THRESH_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.apdLowGainModeLowThresh out of range (0-63)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.apdGainStepAttack > APD_LOW_GAIN_STEP_ATTACK_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.apdGainStepAttack out of range (0-31)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.apdGainStepRecovery > APD_GAIN_STEP_RECOVERY_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.apdGainStepRecovery out of range (0-31)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* HB2 Configuration */ + if (agcConfig[configIndex].agcPeak.enableHb2Overload > AGC_ENABLE_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.enableHb2Overload out of range (0-1)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.hb2OverloadDurationCnt > HB2_OVER_LOAD_DURATION_CNT_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.hb2OverloadDurationCnt out of range (0-7)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.hb2OverloadThreshCnt > HB2_OVER_LOAD_THRESH_CNT_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.hb2OverloadDurationCnt out of range (0-15)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.hb2HighThresh > HB2_HIGH_THRESH_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.hb2HighThresh out of range (0-16383)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.hb2UnderRangeLowThresh > HB2_UNDER_RANGE_LOW_THRESH_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.hb2UnderRangeLowThresh out of range (0-16383)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.hb2UnderRangeMidThresh > HB2_UNDER_RANGE_MID_THRESH_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.hb2UnderRangeMidThresh out of range (0-16383)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.hb2UnderRangeHighThresh > HB2_UNDER_RANGE_HIGH_THRESH_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.hb2UnderRangeHighThresh out of range (0-16383)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.hb2GainStepHighRecovery > HB2_GAIN_STEP_HIGH_RECOVERY_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.hb2GainStepHighRecovery out of range (0-31)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.hb2GainStepLowRecovery > HB2_GAIN_STEP_LOW_RECOVERY_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.hb2GainStepLowRecovery out of range (0-31)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.hb2GainStepMidRecovery > HB2_GAIN_STEP_MID_RECOVERY_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.hb2GainStepMidRecovery out of range (0-31)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.hb2GainStepAttack > HB2_GAIN_STEP_ATTACK_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.hb2GainStepAttack out of range (0-31)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.hb2OverloadPowerMode > AGC_ENABLE_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.hb2OverloadPowerMode out of range (0-1)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPeak.hb2ThreshConfig != HB2_THRESH_CONFIG) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPeak.hb2ThreshConfig out of range (3)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Power Configuration register */ + if (agcConfig[configIndex].agcPower.powerEnableMeasurement > AGC_ENABLE_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPower.powerEnableMeasurement out of range (0-1)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPower.powerInputSelect > POWER_INPUT_SELECT_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPower.powerInputSelect out of range (0-3)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPower.underRangeHighPowerThresh > UNDER_RANGE_HIGH_POWER_THRESH_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPower.underRangeHighPowerThresh out of range (0-127)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPower.underRangeLowPowerThresh > UNDER_RANGE_LOW_POWER_THRESH_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPower.underRangeLowPowerThresh out of range (0-31)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPower.underRangeHighPowerGainStepRecovery > UNDER_RANGE_HIGH_POWER_GAIN_STEP_RECOVERY_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPower.underRangeHighPowerGainStepRecovery out of range (0-31)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPower.underRangeLowPowerGainStepRecovery > UNDER_RANGE_LOW_POWER_GAIN_STEP_RECOVERY_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPower.underRangeLowPowerGainStepRecovery out of range (0-31)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPower.powerMeasurementDuration > POWER_MEASUREMENT_DURATION_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPower.powerMeasurementDuration out of range (0-31)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPower.overRangeHighPowerThresh > OVER_RANGE_HIGH_POWER_THRESH_MID_RECOVERY_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPower.overRangeHighPowerThresh out of range (0-127)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPower.overRangeLowPowerThresh > OVER_RANGE_LOW_POWER_THRESH_MID_RECOVERY_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPower.overRangeLowPowerThresh out of range (0-15)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPower.powerLogShift != AGC_ENABLE_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPower.powerLogShift out of range (1)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPower.overRangeHighPowerGainStepAttack > OVER_RANGE_HIGH_POWER_GAIN_STEP_ATTACK_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPower.overRangeHighPowerGainStepAttack out of range (0-31)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (agcConfig[configIndex].agcPower.overRangeLowPowerGainStepAttack > OVER_RANGE_LOW_POWER_GAIN_STEP_ATTACK_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "agcPower.overRangeLowPowerGainStepAttack out of range (0-31)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return recoveryAction; +} + +int32_t adi_adrv9025_AgcCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AgcCfg_t agcConfig[], + uint8_t arraySize) +{ + adrv9025_BfRxChanAddr_e baseAddr = ADRV9025_BF_RX_CH0; + adrv9025_BfAnalogRxMemMapChanAddr_e baseAddrAnalog = ADRV9025_BF_ANALOG_RX_CH0; + uint8_t bfValue = 0; + uint8_t configIndex = 0; + uint8_t i = 0; + uint8_t refClockCycles = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + agcConfig); + + if (arraySize == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + arraySize, + "Invalid number of AGC configs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + +#if ADI_ADRV9025_AGC_RANGE_CHECK > 0 + adi_adrv9025_AgcCfgSetRangeCheck(device, + agcConfig, + arraySize); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + for (configIndex = 0; configIndex < arraySize; configIndex++) + { + uint32_t rxChannelMask = agcConfig[configIndex].rxChannelMask; + uint32_t rxChannelSelect = 0; + for (i = 0; i < ADI_ADRV9025_MAX_RX_ONLY; i++) + { + if ((rxChannelMask & ADI_ADRV9025_RX1) == ADI_ADRV9025_RX1) + { + baseAddr = ADRV9025_BF_RX_CH0; + baseAddrAnalog = ADRV9025_BF_ANALOG_RX_CH0; + rxChannelMask &= ~ADI_ADRV9025_RX1; + rxChannelSelect = ADI_ADRV9025_RX1; + } + else if ((rxChannelMask & ADI_ADRV9025_RX2) == ADI_ADRV9025_RX2) + { + baseAddr = ADRV9025_BF_RX_CH1; + baseAddrAnalog = ADRV9025_BF_ANALOG_RX_CH1; + rxChannelMask &= ~ADI_ADRV9025_RX2; + rxChannelSelect = ADI_ADRV9025_RX2; + } + else if ((rxChannelMask & ADI_ADRV9025_RX3) == ADI_ADRV9025_RX3) + { + baseAddr = ADRV9025_BF_RX_CH2; + baseAddrAnalog = ADRV9025_BF_ANALOG_RX_CH2; + rxChannelMask &= ~ADI_ADRV9025_RX3; + rxChannelSelect = ADI_ADRV9025_RX3; + } + else if ((rxChannelMask & ADI_ADRV9025_RX4) == ADI_ADRV9025_RX4) + { + baseAddr = ADRV9025_BF_RX_CH3; + baseAddrAnalog = ADRV9025_BF_ANALOG_RX_CH3; + rxChannelMask &= ~ADI_ADRV9025_RX4; + rxChannelSelect = ADI_ADRV9025_RX4; + } + else + { + break; + } + + + /* Read the reference clock cycles for the given channel */ + adrv9025_RxReferenceClockCyclesBfGet(device, baseAddr, &refClockCycles); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Configure delay counter base rate with reference clock cycle value */ + adrv9025_RxAgcDelayCounterBaseRateBfSet(device, baseAddr, refClockCycles); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcPeakWaitTimeBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeakWaitTime); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* writing Rx max and min gain indices */ + adrv9025_RxAgcMaximumGainIndexBfSet(device, + baseAddr, + agcConfig[configIndex].agcRxMaxGainIndex); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcMinimumGainIndexBfSet(device, + baseAddr, + agcConfig[configIndex].agcRxMinGainIndex); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcGainUpdateCounterBfSet(device, + baseAddr, + agcConfig[configIndex].agcGainUpdateCounter); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcAttackDelayBfSet(device, + baseAddr, + agcConfig[configIndex].agcRxAttackDelay); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* AGC Control register - Slowloop_config*/ + adrv9025_RxAgcEnableFastRecoveryLoopBfSet(device, + baseAddr, + agcConfig[configIndex].agcEnableFastRecoveryLoop); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Fast recovery loop is enabled for peak AGC mode and disabled for AGC power mode */ + if (agcConfig[configIndex].agcEnableFastRecoveryLoop > 0) + { + device->devStateInfo.rxAgcPeakModeMask |= rxChannelSelect; + } + else + { + device->devStateInfo.rxAgcPeakModeMask &= ~rxChannelSelect; + } + + adrv9025_RxAgcLowThsPreventGainIncBfSet(device, + baseAddr, + agcConfig[configIndex].agcLowThreshPreventGainInc); + ADI_ERROR_RETURN(device->common.error.newAction); + + bfValue = agcConfig[configIndex].agcChangeGainIfThreshHigh & 0x01; + adrv9025_RxAgcChangeGainIfUlbthHighBfSet(device, + baseAddr, + bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + + bfValue = (agcConfig[configIndex].agcChangeGainIfThreshHigh >> 1) & 0x01; + adrv9025_RxAgcChangeGainIfAdcovrgHighBfSet(device, + baseAddr, + bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcPeakThresholdGainControlModeBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeakThreshGainControlMode); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcResetOnRxonBfSet(device, + baseAddr, + agcConfig[configIndex].agcResetOnRxon); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcEnableSyncPulseForGainCounterBfSet(device, + baseAddr, + agcConfig[configIndex].agcEnableSyncPulseForGainCounter); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcSlowLoopSettlingDelayBfSet(device, + baseAddr, + agcConfig[configIndex].agcSlowLoopSettlingDelay); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcAdcResetGainStepBfSet(device, + baseAddr, + agcConfig[configIndex].agcAdcResetGainStep); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcSlowloopFastGainChangeBlockEnableBfSet(device, + baseAddr, + agcConfig[configIndex].agcSlowloopFastGainChangeBlockEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Agc Peak */ + adrv9025_RxAgcUrangeInterval0BfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.agcUnderRangeLowInterval); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUrangeInterval1MultBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.agcUnderRangeMidInterval); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUrangeInterval2MultBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.agcUnderRangeHighInterval); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Digital: adrv9025_RxUpperLevelBlockerThresholdBfSet */ + adrv9025_AnalogRxMemMapRxBlockDetUlbthBfSet(device, + baseAddrAnalog, + 0, + agcConfig[configIndex].agcPeak.apdHighThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Digital: adrv9025_RxUpperLevelBlockerThresholdTiaLowGainModeBfSet */ + adrv9025_AnalogRxMemMapRxBlockDetUlbthBfSet(device, + baseAddrAnalog, + 1, + agcConfig[configIndex].agcPeak.apdLowGainModeHighThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Digital: adrv9025_RxLowerLevelBlockerThresholdBfSet */ + adrv9025_AnalogRxMemMapRxBlockDetLlbthBfSet(device, + baseAddrAnalog, + 0, + agcConfig[configIndex].agcPeak.apdLowThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Digital: adrv9025_RxLowerLevelBlockerThresholdTiaLowGainModeBfSet */ + adrv9025_AnalogRxMemMapRxBlockDetLlbthBfSet(device, + baseAddrAnalog, + 1, + agcConfig[configIndex].agcPeak.apdLowGainModeLowThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + bfValue = 0; + adrv9025_AnalogRxMemMapRxBlockDetDecayBfSet(device, + baseAddrAnalog, + bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + bfValue = 1; + adrv9025_AnalogRxMemMapRxTiaForceUpdateBfSet(device, + baseAddrAnalog, + bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + bfValue = 0; + adrv9025_AnalogRxMemMapRxTiaForceUpdateBfSet(device, + baseAddrAnalog, + bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUlbThresholdExceededCounterBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.apdUpperThreshPeakExceededCnt); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcLlbThresholdExceededCounterBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.apdLowerThreshPeakExceededCnt); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUlbGainStepBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.apdGainStepAttack); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcLlbGainStepBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.apdGainStepRecovery); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*HB2 Configuration register*/ + adrv9025_RxEnableDecOverloadBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.enableHb2Overload); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecOverloadDurationCountBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.hb2OverloadDurationCnt); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecOverloadThresholdCountBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.hb2OverloadThreshCnt); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* HB2 */ + adrv9025_RxDecimatedDataOverloadUpperThresholdBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.hb2HighThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecimatedDataOverloadInt0LowerThresholdBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.hb2UnderRangeLowThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecimatedDataOverloadInt1LowerThresholdBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.hb2UnderRangeMidThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecimatedDataOverloadLowerThresholdBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.hb2UnderRangeHighThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcAdcHighOvrgExceededCounterBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.hb2UpperThreshPeakExceededCnt); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcAdcLowOvrgExceededCounterBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.hb2UnderRangeHighThreshExceededCnt); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcOvrgLowGainStepBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.hb2GainStepHighRecovery); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcOvrgLowInt0GainStepBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.hb2GainStepLowRecovery); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcOvrgLowInt1GainStepBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.hb2GainStepMidRecovery); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcOvrgHighGainStepBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.hb2GainStepAttack); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecOverloadPowerModeBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.hb2OverloadPowerMode); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* agcConfig[configIndex].agcPeak.hb2ThreshConfig */ + bfValue = 3; /* Fixed to 3 */ + adrv9025_RxDecThresholdConfigBfSet(device, + baseAddr, + bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcAdcovrgLowInt1CounterBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.hb2UnderRangeMidThreshExceededCnt); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcAdcovrgLowInt0CounterBfSet(device, + baseAddr, + agcConfig[configIndex].agcPeak.hb2UnderRangeLowThreshExceededCnt); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* APD Low Frequency MITIGATION Mode Setup */ + static const uint8_t APD_LOW_FREQ_ADCOVRG_2ND_HIGH_COUNTER = 3; + static const uint8_t APD_LOW_FREQ_ERROR_MITIGATION_MODE = 1; + static const uint16_t APD_LOW_FREQ_THRESH_OFFSET = 6; + + adrv9025_RxDecimatedDataOverloadSecondaryUpperThresholdBfSet(device, + baseAddr, + (agcConfig[configIndex].agcPeak.hb2HighThresh - APD_LOW_FREQ_THRESH_OFFSET)); + ADI_ERROR_RETURN(device->common.error.newAction); + + bfValue = APD_LOW_FREQ_ADCOVRG_2ND_HIGH_COUNTER; + adrv9025_RxAdcovrg2ndHighCounterBfSet(device, + baseAddr, + bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + + bfValue = APD_LOW_FREQ_ERROR_MITIGATION_MODE; + adrv9025_RxAgcApdLowFreqErrorMitigationModeBfSet(device, + baseAddr, + bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Power Configuration register */ + adrv9025_RxDecPowerEnableMeasBfSet(device, + baseAddr, + agcConfig[configIndex].agcPower.powerEnableMeasurement); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecPowerInputSelectBfSet(device, + baseAddr, + agcConfig[configIndex].agcPower.powerInputSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcLower0ThresholdBfSet(device, + baseAddr, + agcConfig[configIndex].agcPower.underRangeHighPowerThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcLower1ThresholdBfSet(device, + baseAddr, + agcConfig[configIndex].agcPower.underRangeLowPowerThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcLower0ThresholdExceededGainStepBfSet(device, + baseAddr, + agcConfig[configIndex].agcPower.underRangeHighPowerGainStepRecovery); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcLower1ThresholdExceededGainStepBfSet(device, + baseAddr, + agcConfig[configIndex].agcPower.underRangeLowPowerGainStepRecovery); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecPowerMeasurementDurationBfSet(device, + baseAddr, + agcConfig[configIndex].agcPower.powerMeasurementDuration); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUlSigPowerMeasDurationBfSet(device, + baseAddr, + agcConfig[configIndex].agcPower.rxTddPowerMeasDuration); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUlSigPowerMeasDelayBfSet(device, + baseAddr, + agcConfig[configIndex].agcPower.rxTddPowerMeasDelay); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcLockLevelBfSet(device, + baseAddr, + agcConfig[configIndex].agcPower.overRangeHighPowerThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUpper1ThresholdBfSet(device, + baseAddr, + agcConfig[configIndex].agcPower.overRangeLowPowerThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* agcConfig[configIndex].agcPower.powerLogShift */ + bfValue = 1; /* Fixed to 1 */ + adrv9025_RxDecPowerLogShiftBfSet(device, + baseAddr, + bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUpper0ThresholdExceededGainStepBfSet(device, + baseAddr, + agcConfig[configIndex].agcPower.overRangeHighPowerGainStepAttack); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUpper1ThresholdExceededGainStepBfSet(device, + baseAddr, + agcConfig[configIndex].agcPower.overRangeLowPowerGainStepAttack); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_AgcCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_AgcCfg_t* agcConfig) +{ + adrv9025_BfRxChanAddr_e baseAddr = ADRV9025_BF_RX_CH0; + adrv9025_BfAnalogRxMemMapChanAddr_e baseAddrAnalog = ADRV9025_BF_ANALOG_RX_CH0; + uint8_t bfValue = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + agcConfig); + + if (rxChannel == ADI_ADRV9025_RX1) + { + baseAddr = ADRV9025_BF_RX_CH0; + baseAddrAnalog = ADRV9025_BF_ANALOG_RX_CH0; + } + else if (rxChannel == ADI_ADRV9025_RX2) + { + baseAddr = ADRV9025_BF_RX_CH1; + baseAddrAnalog = ADRV9025_BF_ANALOG_RX_CH1; + } + else if (rxChannel == ADI_ADRV9025_RX3) + { + baseAddr = ADRV9025_BF_RX_CH2; + baseAddrAnalog = ADRV9025_BF_ANALOG_RX_CH2; + } + else if (rxChannel == ADI_ADRV9025_RX4) + { + baseAddr = ADRV9025_BF_RX_CH3; + baseAddrAnalog = ADRV9025_BF_ANALOG_RX_CH3; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid rxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + agcConfig->rxChannelMask = (uint32_t)rxChannel; + + adrv9025_RxAgcPeakWaitTimeBfGet(device, + baseAddr, + &agcConfig->agcPeakWaitTime); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Error while attemtpting to get Rx Agc Config"); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcMaximumGainIndexBfGet(device, + baseAddr, + &agcConfig->agcRxMaxGainIndex); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcMinimumGainIndexBfGet(device, + baseAddr, + &agcConfig->agcRxMinGainIndex); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcGainUpdateCounterBfGet(device, + baseAddr, + &agcConfig->agcGainUpdateCounter); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcAttackDelayBfGet(device, + baseAddr, + &agcConfig->agcRxAttackDelay); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* AGC Control register - Slowloop_config*/ + adrv9025_RxAgcEnableFastRecoveryLoopBfGet(device, + baseAddr, + &agcConfig->agcEnableFastRecoveryLoop); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcLowThsPreventGainIncBfGet(device, + baseAddr, + &agcConfig->agcLowThreshPreventGainInc); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcChangeGainIfUlbthHighBfGet(device, + baseAddr, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + agcConfig->agcChangeGainIfThreshHigh = (bfValue & 0x01); + + adrv9025_RxAgcChangeGainIfAdcovrgHighBfGet(device, + baseAddr, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + agcConfig->agcChangeGainIfThreshHigh |= ((bfValue << 1) & 0x02); + + adrv9025_RxAgcPeakThresholdGainControlModeBfGet(device, + baseAddr, + &agcConfig->agcPeakThreshGainControlMode); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcResetOnRxonBfGet(device, + baseAddr, + &agcConfig->agcResetOnRxon); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcEnableSyncPulseForGainCounterBfGet(device, + baseAddr, + &agcConfig->agcEnableSyncPulseForGainCounter); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcSlowLoopSettlingDelayBfGet(device, + baseAddr, + &agcConfig->agcSlowLoopSettlingDelay); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcAdcResetGainStepBfGet(device, + baseAddr, + &agcConfig->agcAdcResetGainStep); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Agc Peak */ + adrv9025_RxAgcUrangeInterval0BfGet(device, + baseAddr, + &agcConfig->agcPeak.agcUnderRangeLowInterval); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUrangeInterval1MultBfGet(device, + baseAddr, + &agcConfig->agcPeak.agcUnderRangeMidInterval); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUrangeInterval2MultBfGet(device, + baseAddr, + &agcConfig->agcPeak.agcUnderRangeHighInterval); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Digital: adrv9025_RxUpperLevelBlockerThresholdBfGet */ + adrv9025_AnalogRxMemMapRxBlockDetUlbthBfGet(device, + baseAddrAnalog, + 0, + &agcConfig->agcPeak.apdHighThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Digital: adrv9025_RxUpperLevelBlockerThresholdTiaLowGainModeBfGet */ + adrv9025_AnalogRxMemMapRxBlockDetUlbthBfGet(device, + baseAddrAnalog, + 1, + &agcConfig->agcPeak.apdLowGainModeHighThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Digital: adrv9025_RxLowerLevelBlockerThresholdBfGet */ + adrv9025_AnalogRxMemMapRxBlockDetLlbthBfGet(device, + baseAddrAnalog, + 0, + &agcConfig->agcPeak.apdLowThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Digital: adrv9025_RxLowerLevelBlockerThresholdTiaLowGainModeBfGet */ + adrv9025_AnalogRxMemMapRxBlockDetLlbthBfGet(device, + baseAddrAnalog, + 1, + &agcConfig->agcPeak.apdLowGainModeLowThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUlbThresholdExceededCounterBfGet(device, + baseAddr, + &agcConfig->agcPeak.apdUpperThreshPeakExceededCnt); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcLlbThresholdExceededCounterBfGet(device, + baseAddr, + &agcConfig->agcPeak.apdLowerThreshPeakExceededCnt); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUlbGainStepBfGet(device, + baseAddr, + &agcConfig->agcPeak.apdGainStepAttack); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcLlbGainStepBfGet(device, + baseAddr, + &agcConfig->agcPeak.apdGainStepRecovery); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*HB2 Configuration register*/ + adrv9025_RxEnableDecOverloadBfGet(device, + baseAddr, + &agcConfig->agcPeak.enableHb2Overload); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecOverloadDurationCountBfGet(device, + baseAddr, + &agcConfig->agcPeak.hb2OverloadDurationCnt); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecOverloadThresholdCountBfGet(device, + baseAddr, + &agcConfig->agcPeak.hb2OverloadThreshCnt); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecimatedDataOverloadUpperThresholdBfGet(device, + baseAddr, + &agcConfig->agcPeak.hb2HighThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecimatedDataOverloadInt0LowerThresholdBfGet(device, + baseAddr, + &agcConfig->agcPeak.hb2UnderRangeLowThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecimatedDataOverloadInt1LowerThresholdBfGet(device, + baseAddr, + &agcConfig->agcPeak.hb2UnderRangeMidThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecimatedDataOverloadLowerThresholdBfGet(device, + baseAddr, + &agcConfig->agcPeak.hb2UnderRangeHighThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcAdcHighOvrgExceededCounterBfGet(device, + baseAddr, + &agcConfig->agcPeak.hb2UpperThreshPeakExceededCnt); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcAdcLowOvrgExceededCounterBfGet(device, + baseAddr, + &agcConfig->agcPeak.hb2UnderRangeHighThreshExceededCnt); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcOvrgLowGainStepBfGet(device, + baseAddr, + &agcConfig->agcPeak.hb2GainStepHighRecovery); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcOvrgLowInt0GainStepBfGet(device, + baseAddr, + &agcConfig->agcPeak.hb2GainStepLowRecovery); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcOvrgLowInt1GainStepBfGet(device, + baseAddr, + &agcConfig->agcPeak.hb2GainStepMidRecovery); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcOvrgHighGainStepBfGet(device, + baseAddr, + &agcConfig->agcPeak.hb2GainStepAttack); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecOverloadPowerModeBfGet(device, + baseAddr, + &agcConfig->agcPeak.hb2OverloadPowerMode); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecThresholdConfigBfGet(device, + baseAddr, + &agcConfig->agcPeak.hb2ThreshConfig); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcAdcovrgLowInt1CounterBfGet(device, + baseAddr, + &agcConfig->agcPeak.hb2UnderRangeMidThreshExceededCnt); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcAdcovrgLowInt0CounterBfGet(device, + baseAddr, + &agcConfig->agcPeak.hb2UnderRangeLowThreshExceededCnt); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Power Configuration register */ + adrv9025_RxDecPowerEnableMeasBfGet(device, + baseAddr, + &agcConfig->agcPower.powerEnableMeasurement); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecPowerInputSelectBfGet(device, + baseAddr, + &agcConfig->agcPower.powerInputSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecPowerLogShiftBfGet(device, + baseAddr, + &agcConfig->agcPower.powerLogShift); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcLower0ThresholdBfGet(device, + baseAddr, + &agcConfig->agcPower.underRangeHighPowerThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcLower1ThresholdBfGet(device, + baseAddr, + &agcConfig->agcPower.underRangeLowPowerThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcLower0ThresholdExceededGainStepBfGet(device, + baseAddr, + &agcConfig->agcPower.underRangeHighPowerGainStepRecovery); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcLower1ThresholdExceededGainStepBfGet(device, + baseAddr, + &agcConfig->agcPower.underRangeLowPowerGainStepRecovery); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDecPowerMeasurementDurationBfGet(device, + baseAddr, + &agcConfig->agcPower.powerMeasurementDuration); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUlSigPowerMeasDurationBfGet(device, + baseAddr, + &agcConfig->agcPower.rxTddPowerMeasDuration); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUlSigPowerMeasDelayBfGet(device, + baseAddr, + &agcConfig->agcPower.rxTddPowerMeasDelay); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcLockLevelBfGet(device, + baseAddr, + &agcConfig->agcPower.overRangeHighPowerThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUpper1ThresholdBfGet(device, + baseAddr, + &agcConfig->agcPower.overRangeLowPowerThresh); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUpper0ThresholdExceededGainStepBfGet(device, + baseAddr, + &agcConfig->agcPower.overRangeHighPowerGainStepAttack); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcUpper1ThresholdExceededGainStepBfGet(device, + baseAddr, + &agcConfig->agcPower.overRangeLowPowerGainStepAttack); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_AgcDualBandCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AgcDualBandCfg_t rxAgcCtrlDualBand[], + uint8_t arraySize) +{ + UNUSED_PARA(device); + UNUSED_PARA(rxAgcCtrlDualBand); + UNUSED_PARA(arraySize); + return 0; +} + +int32_t adi_adrv9025_AgcDualBandCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_AgcDualBandCfg_t* rxAgcCtrlDualBand) +{ + UNUSED_PARA(device); + UNUSED_PARA(rxChannel); + UNUSED_PARA(rxAgcCtrlDualBand); + return 0; +} + +int32_t adi_adrv9025_AgcDualBandLnaGpioOutGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_DualBandLnaCfg_t* rxDualBandLnaControls) +{ + UNUSED_PARA(device); + UNUSED_PARA(rxChannel); + UNUSED_PARA(rxDualBandLnaControls); + return 0; +} + +int32_t adi_adrv9025_AgcGainIndexRangeSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AgcGainRange_t agcGainRange[], + uint8_t arraySize) +{ + adrv9025_BfRxChanAddr_e baseAddr = ADRV9025_BF_RX_CH0; + uint8_t bfValue = 0; + uint8_t configIndex = 0; + uint8_t i = 0; + uint32_t rxChannelMask = 0; + uint8_t maxGainIndex = 0; + uint8_t minGainIndex = 0; + + static uint8_t const AGC_RXCHANNEL_MAX = 0x0F; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + agcGainRange); + + if (arraySize == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + arraySize, + "Invalid arraySize"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (configIndex = 0; configIndex < arraySize; configIndex++) + { + rxChannelMask = agcGainRange[configIndex].rxChannelMask; + + if ((rxChannelMask > AGC_RXCHANNEL_MAX) || (rxChannelMask == 0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "Invalid rxChannelMask. Valid range (1/2/4/8/15)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Ensure that Max Gain Index is always greater than Min Gain Index */ + maxGainIndex = agcGainRange[configIndex].maxGainIndex; + minGainIndex = agcGainRange[configIndex].minGainIndex; + if (minGainIndex >= maxGainIndex) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + maxGainIndex, + "Min Gain Index cannot be greater than Max Gain Index Param"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_ADRV9025_MAX_RX_ONLY; i++) + { + if ((rxChannelMask & ADI_ADRV9025_RX1) == ADI_ADRV9025_RX1) + { + baseAddr = ADRV9025_BF_RX_CH0; + rxChannelMask &= ~ADI_ADRV9025_RX1; + /* range check the gain against the max and min expected values */ + if ((maxGainIndex > device->devStateInfo.gainIndexes.rx1MaxGainIndex) + || (minGainIndex < device->devStateInfo.gainIndexes.rx1MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + maxGainIndex, + "Gain index less than minimum index or greater than maximum gain index"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else if ((rxChannelMask & ADI_ADRV9025_RX2) == ADI_ADRV9025_RX2) + { + baseAddr = ADRV9025_BF_RX_CH1; + rxChannelMask &= ~ADI_ADRV9025_RX2; + /* range check the gain against the max and min expected values */ + if ((maxGainIndex > device->devStateInfo.gainIndexes.rx2MaxGainIndex) + || (minGainIndex < device->devStateInfo.gainIndexes.rx2MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + maxGainIndex, + "Gain index less than minimum index or greater than maximum gain index"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else if ((rxChannelMask & ADI_ADRV9025_RX3) == ADI_ADRV9025_RX3) + { + baseAddr = ADRV9025_BF_RX_CH2; + rxChannelMask &= ~ADI_ADRV9025_RX3; + /* range check the gain against the max and min expected values */ + if ((maxGainIndex > device->devStateInfo.gainIndexes.rx3MaxGainIndex) + || (minGainIndex < device->devStateInfo.gainIndexes.rx3MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + maxGainIndex, + "Gain index less than minimum index or greater than maximum gain index"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else if ((rxChannelMask & ADI_ADRV9025_RX4) == ADI_ADRV9025_RX4) + { + baseAddr = ADRV9025_BF_RX_CH3; + rxChannelMask &= ~ADI_ADRV9025_RX4; + /* range check the gain against the max and min expected values */ + if ((maxGainIndex > device->devStateInfo.gainIndexes.rx4MaxGainIndex) + || (minGainIndex < device->devStateInfo.gainIndexes.rx4MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + maxGainIndex, + "Gain index less than minimum index or greater than maximum gain index"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else + { + break; + } + + /* Writing Rx1 max and min gain indices to the SPI registers*/ + bfValue = agcGainRange[configIndex].maxGainIndex; + adrv9025_RxAgcMaximumGainIndexBfSet(device, + baseAddr, + bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + + bfValue = agcGainRange[configIndex].minGainIndex; + adrv9025_RxAgcMinimumGainIndexBfSet(device, + baseAddr, + bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_AgcGainIndexRangeGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_AgcGainRange_t* agcGainRange) +{ + adrv9025_BfRxChanAddr_e baseAddr = ADRV9025_BF_RX_CH0; + uint8_t bfValue = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + agcGainRange); + + if (rxChannel == ADI_ADRV9025_RX1) + { + baseAddr = ADRV9025_BF_RX_CH0; + } + else if (rxChannel == ADI_ADRV9025_RX2) + { + baseAddr = ADRV9025_BF_RX_CH1; + } + else if (rxChannel == ADI_ADRV9025_RX3) + { + baseAddr = ADRV9025_BF_RX_CH2; + } + else if (rxChannel == ADI_ADRV9025_RX4) + { + baseAddr = ADRV9025_BF_RX_CH3; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid rxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + agcGainRange->rxChannelMask = rxChannel; + + /* Writing Rx1 max and min gain indices to the SPI registers*/ + adrv9025_RxAgcMaximumGainIndexBfGet(device, + baseAddr, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + agcGainRange->maxGainIndex = bfValue; + + adrv9025_RxAgcMinimumGainIndexBfGet(device, + baseAddr, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + agcGainRange->minGainIndex = bfValue; + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_AgcReset(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask) +{ + adrv9025_BfRxChanAddr_e baseAddr = ADRV9025_BF_RX_CH0; + uint8_t i = 0; + + static const uint8_t AGC_RESET = 1; + static const uint8_t AGC_RESET_CLEAR = 0; + static const uint8_t AGC_RXCHANNEL_MAX = 0x0F; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if ((rxChannelMask > AGC_RXCHANNEL_MAX) || (rxChannelMask == 0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "Invalid rxChannelMask. Valid range (1/2/4/8/15)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_ADRV9025_MAX_RX_ONLY; i++) + { + if ((rxChannelMask & ADI_ADRV9025_RX1) == ADI_ADRV9025_RX1) + { + baseAddr = ADRV9025_BF_RX_CH0; + rxChannelMask &= ~ADI_ADRV9025_RX1; + } + else if ((rxChannelMask & ADI_ADRV9025_RX2) == ADI_ADRV9025_RX2) + { + baseAddr = ADRV9025_BF_RX_CH1; + rxChannelMask &= ~ADI_ADRV9025_RX2; + } + else if ((rxChannelMask & ADI_ADRV9025_RX3) == ADI_ADRV9025_RX3) + { + baseAddr = ADRV9025_BF_RX_CH2; + rxChannelMask &= ~ADI_ADRV9025_RX3; + } + else if ((rxChannelMask & ADI_ADRV9025_RX4) == ADI_ADRV9025_RX4) + { + baseAddr = ADRV9025_BF_RX_CH3; + rxChannelMask &= ~ADI_ADRV9025_RX4; + } + else + { + break; + } + + adrv9025_RxAgcSoftResetBfSet(device, + baseAddr, + AGC_RESET); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcSoftResetBfSet(device, + baseAddr, + AGC_RESET_CLEAR); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_AgcOverloadIndicatorGpioSet(adi_adrv9025_Device_t* device, + uint8_t overloadEnable) +{ + /* Check that the passed device pointer is not NULL */ + ADI_NULL_DEVICE_PTR_RETURN(device); + /* Add entry to the API log */ + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + uint8_t sharedResourceAcqReleaseStatus = 0x00; /* Will be passed as reference, used to confirm that the shared resource has been acquired */ + uint32_t sharedResourceId = 0x00; /* To iterate over ADRV9025_GPIO for loop */ + static const uint32_t gpioOutputMask = 0x3FFC0; /* 111111111111000000 mask to set pins to output */ + static const uint32_t gpioSrcCtrl = 0xEEEE0; /* 11101110111011100000 sets the output source control for each set of four GPIO pins */ + static const uint32_t gpioSrcCtrlReset = 0x00000; /* Sets the output source control for each set of four GPIO pins */ + int32_t recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + adrv9025_FeatureID_e sharedResourceFeatureId = ADRV9025_FEATURE_UNUSED; + + int32_t sharedResourceArr[] = {6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17}; + + if (overloadEnable) + { + /* Iterate throught pins ADRV9025_GPIO_06 to ADRV9025_GPIO_17 */ + /* Get the current shared resource feature ID of each pin */ + /* If the pin is not in an unused state i.e ADRV9025_FEATURE_UNUSED */ + /* Set feature flag to false and break from the loop */ + for (sharedResourceId = (uint32_t)ADRV9025_GPIO_06; sharedResourceId < (uint32_t)ADRV9025_GPIO_18; sharedResourceId++) + { + adrv9025_SharedResourceFeatureGet(device, (adrv9025_SharedResourceID_e)sharedResourceId, &sharedResourceFeatureId); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* The calling application is responsible for setting the shared resource to ADRV9025_FEATURE_UNUSED */ + /* If the shared resource is not ADRV9025_FEATURE_UNUSED, API can not proceed */ + if (sharedResourceFeatureId != ADRV9025_FEATURE_UNUSED) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + sharedResourceAcqReleaseStatus, + "GPIO pins are not in ADRV9025_FEATURE_UNUSED state"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Acquire the shared resource ADRV9025_FEATURE_ADC_OVERLOAD_INDICATION */ + recoveryAction = adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + ADI_ADRV9025_NUM_GPIOS_IN_AGCOOVERLOADINDICATOR_FEATURE, + ADRV9025_FEATURE_ADC_OVERLOAD_INDICATION, + &sharedResourceAcqReleaseStatus); + + /* Confirm that the shared resource has been acquired */ + /* If the shared resource has not been acquired - exception will be thrown */ + if (sharedResourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + sharedResourceAcqReleaseStatus, + "Failed to acquire the shared rescource for GPIO overload"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Set the direction of all pins to output */ + if (adi_adrv9025_GpioOutputDirSet(device, gpioOutputMask) != ADI_COMMON_ACT_NO_ACTION) + { + /* Failed to set the direction of the GPIOs */ + /* Release the shared resource ADRV9025_FEATURE_ADC_OVERLOAD_INDICATION */ + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + ADI_ADRV9025_NUM_GPIOS_IN_AGCOOVERLOADINDICATOR_FEATURE, + ADRV9025_FEATURE_ADC_OVERLOAD_INDICATION, + &sharedResourceAcqReleaseStatus); + + /* Check the status after attempting the release */ + if (sharedResourceAcqReleaseStatus == ADI_FAILURE) + { + /* GPIO output direction failed and the feature has failed to be released from shared resource */ + /* ADI_COMMON_ACT_ERR_RESET_FULL is now required to release the shared resource and set ADRV9025_FEATURE_UNUSED */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + sharedResourceAcqReleaseStatus, + "Unable to set GPIO output direction & Failed to release Overload GPIO feature from shared resource"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + dpdCaptureDoneStatusPin, + "Unable to set GPIO output direction for GPIO overload status indication"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adi_adrv9025_GpioOutSourceCtrlSet(device, gpioSrcCtrl); + + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + /* Release the shared resource ADRV9025_FEATURE_ADC_OVERLOAD_INDICATION */ + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + ADI_ADRV9025_NUM_GPIOS_IN_AGCOOVERLOADINDICATOR_FEATURE, + ADRV9025_FEATURE_ADC_OVERLOAD_INDICATION, + &sharedResourceAcqReleaseStatus); + + /* Check the status after attempting the release */ + if (sharedResourceAcqReleaseStatus == ADI_FAILURE) + { + /* GPIO output source control set has failed and the feature has failed to be released from shared resource */ + /* ADI_COMMON_ACT_ERR_RESET_FULL is now required to release the shared resource and set ADRV9025_FEATURE_UNUSED */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + sharedResourceAcqReleaseStatus, + "Failed to set GPIO output source control set & Failed to release Overload GPIO feature from shared resource"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + gpioSrcCtrl, + "Failed to set GPIO output source control"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } // end of if (overloadEnable) + else + { + /* Iterate throught pins ADRV9025_GPIO_06 to ADRV9025_GPIO_17 */ + /* Get the current shared resource feature ID of each pin */ + /* If the pin is not in an overload feature state i.e ADRV9025_FEATURE_ADC_OVERLOAD_INDICATION */ + /* Throw exception */ + for (sharedResourceId = (uint32_t)ADRV9025_GPIO_06; sharedResourceId < (uint32_t)ADRV9025_GPIO_18; sharedResourceId++) + { + adrv9025_SharedResourceFeatureGet(device, (adrv9025_SharedResourceID_e)sharedResourceId, &sharedResourceFeatureId); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* If the shared resource is not ADRV9025_FEATURE_ADC_OVERLOAD_INDICATION, API can not proceed */ + if (sharedResourceFeatureId != ADRV9025_FEATURE_ADC_OVERLOAD_INDICATION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + sharedResourceAcqReleaseStatus, + "GPIO pins are not in ADRV9025_FEATURE_ADC_OVERLOAD_INDICATION state, API cannot release feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Release the shared resource ADRV9025_FEATURE_ADC_OVERLOAD_INDICATION */ + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + ADI_ADRV9025_NUM_GPIOS_IN_AGCOOVERLOADINDICATOR_FEATURE, + ADRV9025_FEATURE_ADC_OVERLOAD_INDICATION, + &sharedResourceAcqReleaseStatus); + + /* Check the status after attempting the release */ + if (sharedResourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + sharedResourceAcqReleaseStatus, + "Failed to release Overload GPIO feature from shared resource"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adi_adrv9025_GpioOutSourceCtrlSet(device, gpioSrcCtrlReset); + + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + gpioSrcCtrlReset, + "Failed to set GPIO output source control"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + return (device->common.error.newAction); +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_arm.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_arm.c new file mode 100644 index 0000000..6d3de52 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_arm.c @@ -0,0 +1,265 @@ +/** +* \file adi_adrv9025_arm.c +* \brief Contains ARM features related function implementation defined in +* adi_adrv9025_arm.h +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "adi_adrv9025_arm.h" +#include "adi_adrv9025_cpu.h" + +#ifdef _RELEASE_BUILD_ + #line __LINE__ "adi_adrv9025_arm.c" +#endif + +int32_t adi_adrv9025_ArmStart(adi_adrv9025_Device_t* device, + const adi_adrv9025_Init_t* init) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + (void)init; + adi_adrv9025_CpuStart(device); + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ArmStartStatusCheck(adi_adrv9025_Device_t* device, + uint32_t timeout_us) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + adi_adrv9025_CpuStartStatusCheck(device, + timeout_us); + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ArmProfileWrite(adi_adrv9025_Device_t* device, + const adi_adrv9025_Init_t* init) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + adi_adrv9025_CpuProfileWrite(device, + init); + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ArmImageWrite(adi_adrv9025_Device_t* device, + uint32_t byteOffset, + const uint8_t binary[], + uint32_t byteCount) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + adi_adrv9025_CpuImageWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + byteOffset, + binary, + byteCount); + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_AdcProfilesWrite(adi_adrv9025_Device_t* device, + const adi_adrv9025_AdcProfiles_t* adcProfiles) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + adi_adrv9025_CpuAdcProfilesWrite(device, + adcProfiles); + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ArmMemRead(adi_adrv9025_Device_t* device, + uint32_t address, + uint8_t returnData[], + uint32_t byteCount, + uint8_t autoIncrement) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + adi_adrv9025_CpuMemRead(device, + address, + returnData, + byteCount, + autoIncrement); + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ArmMemWrite(adi_adrv9025_Device_t* device, + uint32_t address, + const uint8_t data[], + uint32_t byteCount) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + adi_adrv9025_CpuMemWrite(device, + address, + data, + byteCount, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ArmConfigWrite(adi_adrv9025_Device_t* device, + uint8_t objectId, + uint16_t byteOffset, + const uint8_t data[], + uint8_t byteCount) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + adi_adrv9025_CpuConfigWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + objectId, + byteOffset, + data, + byteCount); + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ArmConfigRead(adi_adrv9025_Device_t* device, + uint8_t objectId, + uint16_t byteOffset, + uint8_t returnData[], + uint8_t byteCount) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + adi_adrv9025_CpuConfigRead(device, + ADI_ADRV9025_CPU_TYPE_C, + objectId, + byteOffset, + returnData, + byteCount); + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ArmCmdStatusGet(adi_adrv9025_Device_t *device, + uint16_t *errorWord, + uint16_t *statusWord) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, errorWord); + ADI_NULL_PTR_RETURN(&device->common, statusWord); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + adi_adrv9025_CpuCmdStatusGet(device, ADI_ADRV9025_CPU_TYPE_C, errorWord, statusWord); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ArmCmdStatusOpcodeGet(adi_adrv9025_Device_t *device, + uint8_t opCode, + uint8_t *cmdStatByte) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, cmdStatByte); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + adi_adrv9025_CpuCmdStatusOpcodeGet(device, ADI_ADRV9025_CPU_TYPE_C, opCode, cmdStatByte); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ArmCmdStatusWait(adi_adrv9025_Device_t* device, + uint8_t opCode, + uint8_t* cmdStatusByte, + uint32_t timeout_us, + uint32_t waitInterval_us) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + opCode, + cmdStatusByte, + timeout_us, + waitInterval_us); + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ArmCmdWrite(adi_adrv9025_Device_t* device, + uint8_t opCode, + const uint8_t extendedData[], + uint8_t byteCount) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + opCode, + extendedData, + byteCount); + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ArmVersionGet(adi_adrv9025_Device_t* device, + adi_adrv9025_ArmVersion_t* armVersion) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + adi_adrv9025_CpuFwVersionGet(device, + ADI_ADRV9025_CPU_TYPE_C, + (adi_adrv9025_CpuFwVersion_t*)armVersion); + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ArmChecksumTableGet(adi_adrv9025_Device_t* device, + adi_adrv9025_ChecksumTable_t* checksum, + uint8_t* checksumValid) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + adi_adrv9025_CpuChecksumTableGet(device, + ADI_ADRV9025_CPU_TYPE_C, + checksum, + checksumValid); + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ArmMailboxBusyGet(adi_adrv9025_Device_t* device, + uint8_t* mailboxBusy) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + adi_adrv9025_CpuMailboxBusyGet(device, + ADI_ADRV9025_CPU_TYPE_C, + mailboxBusy); + return device->common.error.newAction; +} + +int32_t adi_adrv9025_ArmSystemErrorGet(adi_adrv9025_Device_t* device, + const char** errorMessage) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + adi_adrv9025_CpuSystemErrorGet(device, + ADI_ADRV9025_CPU_TYPE_C, + errorMessage); + return device->common.error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_cals.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_cals.c new file mode 100644 index 0000000..e4a85b5 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_cals.c @@ -0,0 +1,2660 @@ +/** +* \file adi_adrv9025_cals.c +* \brief Contains Calibration features related function implementation defined in +* adi_adrv9025_cals.h +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "adi_adrv9025_cals.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_error.h" +#include "adi_adrv9025.h" +#include "adi_adrv9025_cpu.h" +#include "../../private/include/adrv9025_init.h" +#include "../../private/include/adrv9025_cpu.h" +#include "../../private/include/adrv9025_cpu_macros.h" +#include "../../private/include/adrv9025_reg_addr_macros.h" +#include "../../private/include/adrv9025_cals.h" +#include "../../private/include/adrv9025_bf_orx.h" +#include "../../private/include/adrv9025_bf_rx.h" + +#ifdef _RELEASE_BUILD_ + #line __LINE__ "adi_adrv9025_cals.c" +#endif + +int32_t adi_adrv9025_InitCalsRun(adi_adrv9025_Device_t* device, + adi_adrv9025_InitCals_t* initCals) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t payloadMailbox[4] = {0}; + uint8_t payload[1] = {0}; + + static const uint8_t CAL_CHANNEL_ALL_MASK = 0x0F; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + initCals); + + recoveryAction = adrv9025_InitCalStructureCheck(device, + initCals); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + initCals->calMask &= ADI_ADRV9025_MAX_INIT_CAL_MASK; + payloadMailbox[0] = (uint8_t)initCals->calMask; + payloadMailbox[1] = (uint8_t)(initCals->calMask >> 8); + payloadMailbox[2] = (uint8_t)(initCals->calMask >> 16); + payloadMailbox[3] = (uint8_t)(initCals->calMask >> 24); + + recoveryAction = adi_adrv9025_CpuMemWrite(device, + ADRV9025_CPU_C_ADDR_MAILBOX_RUN_INIT, + &payloadMailbox[0], + 4, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to write CPU memory"); + ADI_ERROR_RETURN(device->common.error.newAction); + + payload[0] = initCals->channelMask & CAL_CHANNEL_ALL_MASK; + adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_RUNINIT_OPCODE, + &payload[0], + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + device->devStateInfo.devState = (adi_adrv9025_ApiStates_e)(device->devStateInfo.devState | ADI_ADRV9025_STATE_INITCALS_RUN); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_InitCalsWait(adi_adrv9025_Device_t* device, + uint32_t timeoutMs, + uint8_t* errorFlag) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t cmdStatusByte = 0; + uint8_t errFlag = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + errorFlag); + + static const uint16_t TIMEOUT_MS_FACTOR = 1000; + + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_RUNINIT_OPCODE, + &cmdStatusByte, + (timeoutMs * TIMEOUT_MS_FACTOR), + ADI_ADRV9025_INITCALSWAIT_INTERVAL_US); + errFlag = (cmdStatusByte >> 1); + + + + /* Don't update errorFlag if SPI error because errorFlag could be a random */ + /* value but update error flag for other recovery action types */ + if (recoveryAction == ADI_COMMON_ACT_ERR_RESET_INTERFACE) + { + *errorFlag = 0; + } + else + { + *errorFlag = errFlag; + } + + /* ARM error handler to provide valid recovery action based on ARM error code */ + if (errFlag > 0) + { + adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + ADI_ADRV9025_SRC_CPUCMD, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_RUNINIT_OPCODE, + 0, + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_InitCalsCheckCompleteGet(adi_adrv9025_Device_t* device, + uint8_t* areCalsRunning, + uint8_t* errorFlag) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t cmdStatusByte = 0; + uint8_t armErrorFlag = 0; + static const uint8_t ARM_PENDING = 0x01; + static const uint8_t ARM_ERR_SHIFT = 1; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + areCalsRunning); + + /* read the command status register for the initialization calibration opcode */ + recoveryAction = adi_adrv9025_CpuCmdStatusOpcodeGet(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_RUNINIT_OPCODE, + &cmdStatusByte); + /* don't check cmdStatusByte until return parameters are updated */ + + + + armErrorFlag = (cmdStatusByte >> ARM_ERR_SHIFT); + + if (recoveryAction == ADI_COMMON_ACT_ERR_RESET_INTERFACE) + { + *areCalsRunning = 0; + } + else + { + *areCalsRunning = (cmdStatusByte & ARM_PENDING); + } + + /* Don't update errorFlag if SPI error because errorFlag could be a random */ + /* value but update error flag for other recovery action types */ + if (errorFlag != NULL) + { + if (recoveryAction == ADI_COMMON_ACT_ERR_RESET_INTERFACE) + { + *errorFlag = 0; + } + else + { + *errorFlag = armErrorFlag; + } + } + + if (armErrorFlag > 0) + { + adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + ADI_ADRV9025_SRC_CPUCMD, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_RUNINIT_OPCODE, + 0, + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_InitCalsAbort(adi_adrv9025_Device_t* device, + uint32_t* calsCompleted) +{ + uint8_t cmdStatusByte = 0; + uint8_t calCompleteBitField[4] = {0}; + uint8_t extData[1] = {ADRV9025_CPU_OBJECTID_INITCAL_STATUS}; + + static const uint8_t ARM_ERR_SHIFT = 1; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADRV9025_BUGINFO(__FUNCTION__); + + /* send ARM abort opcode */ + adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_ABORT_OPCODE, + 0, + 0); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* wait for command completion */ + adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_ABORT_OPCODE, + &cmdStatusByte, + ADI_ADRV9025_INITCALSABORT_TIMEOUT_US, + ADI_ADRV9025_INITCALSABORT_INTERVAL_US); + + + + if ((cmdStatusByte >> ARM_ERR_SHIFT) > 0) + { + adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + ADI_ADRV9025_SRC_CPUCMD, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_ABORT_OPCODE, + 0, + cmdStatusByte), + ADI_COMMON_ACT_ERR_RESET_FULL); + } + else + { + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (calsCompleted != NULL) + { + /* send ARM get opcode for the init cals completed */ + adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* wait for command completion */ + adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_ABORT_OPCODE, + &cmdStatusByte, + ADI_ADRV9025_INITCALSABORT_TIMEOUT_US, + ADI_ADRV9025_INITCALSABORT_INTERVAL_US); + + + if ((cmdStatusByte >> ARM_ERR_SHIFT) > 0) + { + adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + ADI_ADRV9025_SRC_CPUCMD, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + extData[0], + cmdStatusByte), + ADI_COMMON_ACT_ERR_RESET_FULL); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* read the ARM memory for the init cals completed bit field */ + adi_adrv9025_CpuMemRead(device, + ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &calCompleteBitField[0], + 4, + 0); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* form the calsComplted word and return if requested */ + *calsCompleted = (((uint32_t)calCompleteBitField[3]) << 24) | (((uint32_t)calCompleteBitField[2]) << 16) | (((uint32_t)calCompleteBitField[1]) << 8) | ( + ((uint32_t)calCompleteBitField[0])); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_InitCalsDetailedStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_InitCalStatus_t* initStatus) +{ + uint8_t cmdStatusByte = 0; + uint8_t calBitField[48] = {0}; + uint8_t i = 0; + uint8_t offset = 0; + + static const uint8_t InitCalDoneObjectID = 0x43; + static const uint8_t byteCnt = 48; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + initStatus); + + ADRV9025_BUGINFO(__FUNCTION__); + + /* sending get command to ARM */ + adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &InitCalDoneObjectID, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* waiting for command completion */ + adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &cmdStatusByte, + ADI_ADRV9025_INITCALSTATUSGET_TIMEOUT_US, + ADI_ADRV9025_INITCALSTATUSGET_INTERVAL_US); + + + + if ((cmdStatusByte >> 1) > 0) + { + adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + ADI_ADRV9025_SRC_CPUCMD, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + InitCalDoneObjectID, + cmdStatusByte), + ADI_COMMON_ACT_ERR_RESET_FEATURE); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* reading the calibration bit field value */ + adi_adrv9025_CpuMemRead(device, + ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &calBitField[0], + byteCnt, + 0); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* getting the offending error code */ + initStatus->initErrCode = (((uint32_t)calBitField[3]) << 24) | (((uint32_t)calBitField[2]) << 16) | (((uint32_t)calBitField[1]) << 8) | (((uint32_t) + calBitField[0])); + + /* getting the object ID reporting the error */ + initStatus->initErrCal = (((uint32_t)calBitField[7]) << 24) | (((uint32_t)calBitField[6]) << 16) | (((uint32_t)calBitField[5]) << 8) | (((uint32_t) + calBitField[4])); + + /* getting the Duration time in uSec of the last init cals run */ + initStatus->calsDurationUsec = (((uint32_t)calBitField[11]) << 24) | (((uint32_t)calBitField[10]) << 16) | (((uint32_t)calBitField[9]) << 8) | (((uint32_t) + calBitField[8])); + + /* getting the number of calibrations since power up */ + for (i = 0; i < 4; i++) + { + offset = i * 4 + 0xC; + initStatus->calsSincePowerUp[i] = (((uint32_t)calBitField[offset + 3]) << 24) | (((uint32_t)calBitField[offset + 2]) << 16) | (((uint32_t)calBitField[ + offset + 1]) << 8) | (((uint32_t)calBitField[offset + 0])); + } + + /* getting the number of calibrations since the last sequence */ + for (i = 0; i < 4; i++) + { + offset = i * 4 + 0x1C; + initStatus->calsLastRun[i] = (((uint32_t)calBitField[offset + 3]) << 24) | (((uint32_t)calBitField[offset + 2]) << 16) | (((uint32_t)calBitField[offset + + 1]) << 8) | (((uint32_t)calBitField[offset + 0])); + } + + + + if (initStatus->initErrCode > 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUINITCALS, + initStatus->initErrCode, + ADI_ADRV9025_ACT_ERR_RESET_CPU, + device, + adrv9025_CalsErrMsgGet(device, initStatus->initErrCode)); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TrackingCalsEnableSet(adi_adrv9025_Device_t* device, + uint64_t enableMask, + adi_adrv9025_TrackingCalEnableDisable_e enableDisableFlag) +{ + uint8_t armData[8] = {0}; + uint8_t extData[2] = {0}; + uint32_t fwStatus = 0; + uint8_t status = 0; + + static const uint8_t TRACKING_CAL_BITMAP_MODE = 0x80; + static const uint8_t TRACKING_CAL_ENABLE_MODE = 0x40; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* read firmware state to make sure ARM is in ready/IDLE mode */ + ADRV9025_SPIREADBYTE("ARM_CMD_STATUS_8", + ADRV9025_CPU_C_ADDR_CMD_STATUS_8, + &status); + ADI_ERROR_RETURN(device->common.error.newAction); + + fwStatus = (uint32_t)status; + + + /* throw error if not in READY state */ + if (fwStatus != ADRV9025_CPU_FW_STATUS_READY) + { + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUCMD, + ADI_COMMON_ERR_API_FAIL, + ADI_ADRV9025_ACT_ERR_RESET_CPU, + device, + "Device not in READY state. Error in adi_adrv9025_TrackingCalsEnableSet()\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + extData[0] = ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE; + + /* Selecting Enable/ Disable operation by setting the Enable/ Disable bit */ + switch (enableDisableFlag) + { + case ADI_ADRV9025_TRACKING_CAL_DISABLE: + extData[1] = TRACKING_CAL_BITMAP_MODE; + break; + case ADI_ADRV9025_TRACKING_CAL_ENABLE: + extData[1] = TRACKING_CAL_ENABLE_MODE | TRACKING_CAL_BITMAP_MODE; + break; + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + enableDisableFlag, + "Invalid enableDisableFlag"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* populating armData array */ + armData[0] = (uint8_t)(enableMask & 0xFF); + armData[1] = (uint8_t)((enableMask >> 8) & 0xFF); + armData[2] = (uint8_t)((enableMask >> 16) & 0xFF); + armData[3] = (uint8_t)((enableMask >> 24) & 0xFF); + armData[4] = (uint8_t)((enableMask >> 32) & 0xFF); + armData[5] = (uint8_t)((enableMask >> 40) & 0xFF); + armData[6] = (uint8_t)((enableMask >> 48) & 0xFF); + armData[7] = (uint8_t)((enableMask >> 56) & 0xFF); + + /* writing armData to ARM memory */ + adi_adrv9025_CpuMemWrite(device, + ADRV9025_CPU_C_ADDR_MAILBOX_SET, + &armData[0], + 8, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* sending write config command and wait for status */ + adi_adrv9025_CpuCmdWriteWait( + device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_SET_OPCODE, + &extData[0], + 2, + ADI_ADRV9025_ENTRACKINGCALS_TIMEOUT_US, + ADI_ADRV9025_ENTRACKINGCALS_INTERVAL_US, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TrackingCalsEnableGet(adi_adrv9025_Device_t* device, + uint64_t* enableMask) +{ + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + uint8_t extData = 0; + uint8_t armData[8] = {0}; + //uint8_t cmdStatusByte = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + enableMask); + + extData = (uint8_t)ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE; + + /* Executing TRACKING_CALS_STATE Arm Command */ + adi_adrv9025_CpuCmdWriteWait( + device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &extData, + sizeof(extData), + ADI_ADRV9025_ENTRACKINGCALS_TIMEOUT_US, + ADI_ADRV9025_ENTRACKINGCALS_INTERVAL_US, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Test tone config from ARM mailbox */ + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + 8, + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Deserializing Tracking Enable/Disable status (first 8 bytes) */ + *enableMask = (uint64_t)(((uint64_t)armData[0]) | + ((uint64_t)armData[1] << 8) | + ((uint64_t)armData[2] << 16) | + ((uint64_t)armData[3] << 24) | + ((uint64_t)armData[4] << 32) | + ((uint64_t)armData[5] << 40) | + ((uint64_t)armData[6] << 48) | + ((uint64_t)armData[7] << 56)); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TrackingCalDeserializerStatusGet(adi_adrv9025_Device_t* device, + uint8_t desLane, + adi_adrv9025_DesTrackingCalStatus_t* desStatus) +{ + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + + uint8_t extData[3] = {0}; + uint8_t armData[20] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + desStatus); + + if ((desLane < 0) || (desLane > 4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + desLane, + "Invalid Deserializer Lane selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + extData[0] = ADRV9025_CPU_OBJECTID_CAL_STATUS; + extData[1] = ADRV9025_CPU_OBJECTID_DES_TRACKING; + extData[2] = desLane; + + /* Executing Tracking cals Tx LOL status get Arm Command */ + adi_adrv9025_CpuCmdWriteWait( + device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData), + ADI_ADRV9025_GETDESSTATUS_TIMEOUT_US, + ADI_ADRV9025_GETDESSTATUS_INTERVAL_US, + ADRV9025_CPU_OBJECTID_DES_TRACKING); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Tx LOL config from ARM mailbox */ + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Deserializing Tx Lol Status into the structure. */ + desStatus->errorCode = (uint32_t)(((uint32_t)armData[0]) | + ((uint32_t)armData[1] << 8) | + ((uint32_t)armData[2] << 16) | + ((uint32_t)armData[3] << 24)); + + desStatus->percentComplete = (uint32_t)(((uint32_t)armData[4]) | + ((uint32_t)armData[5] << 8) | + ((uint32_t)armData[6] << 16) | + ((uint32_t)armData[7] << 24)); + + desStatus->varianceMetric = (uint32_t)(((uint32_t)armData[8]) | + ((uint32_t)armData[9] << 8) | + ((uint32_t)armData[10] << 16) | + ((uint32_t)armData[11] << 24)); + + desStatus->iterCount = (uint32_t)(((uint32_t)armData[12]) | + ((uint32_t)armData[13] << 8) | + ((uint32_t)armData[14] << 16) | + ((uint32_t)armData[15] << 24)); + + desStatus->updateCount = (uint32_t)(((uint32_t)armData[16]) | + ((uint32_t)armData[17] << 8) | + ((uint32_t)armData[18] << 16) | + ((uint32_t)armData[19] << 24)); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TrackingCalTxLolStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxLolStatus_t* txLolStatus) +{ + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + + uint8_t extData[3] = {ADRV9025_CPU_OBJECTID_CAL_STATUS, ADRV9025_CPU_OBJECTID_TXLOL_TRACKING, 0}; + uint8_t armData[20] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txLolStatus); + + switch (txChannel) + { + case ADI_ADRV9025_TX1: + extData[2] = 0; /*!< Tx0 channel enabled */ + break; + case ADI_ADRV9025_TX2: + extData[2] = 1; /*!< Tx1 channel enabled */ + break; + case ADI_ADRV9025_TX3: + extData[2] = 2; /*!< Tx2 channel enabled */ + break; + case ADI_ADRV9025_TX4: + extData[2] = 3; /*!< Tx3 channel enabled */ + break; + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid Tx Channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Executing Tracking cals Tx LOL status get Arm Command */ + adi_adrv9025_CpuCmdWriteWait( + device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData), + ADI_ADRV9025_GETTXLOLSTATUS_TIMEOUT_US, + ADI_ADRV9025_GETTXLOLSTATUS_INTERVAL_US, + ADRV9025_CPU_OBJECTID_TXLOL_TRACKING); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Tx LOL config from ARM mailbox */ + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Deserializing Tx Lol Status into the structure. */ + txLolStatus->errorCode = (uint32_t)(((uint32_t)armData[0]) | + ((uint32_t)armData[1] << 8) | + ((uint32_t)armData[2] << 16) | + ((uint32_t)armData[3] << 24)); + + txLolStatus->percentComplete = (uint32_t)(((uint32_t)armData[4]) | + ((uint32_t)armData[5] << 8) | + ((uint32_t)armData[6] << 16) | + ((uint32_t)armData[7] << 24)); + + txLolStatus->varianceMetric = (uint32_t)(((uint32_t)armData[8]) | + ((uint32_t)armData[9] << 8) | + ((uint32_t)armData[10] << 16) | + ((uint32_t)armData[11] << 24)); + + txLolStatus->iterCount = (uint32_t)(((uint32_t)armData[12]) | + ((uint32_t)armData[13] << 8) | + ((uint32_t)armData[14] << 16) | + ((uint32_t)armData[15] << 24)); + + txLolStatus->updateCount = (uint32_t)(((uint32_t)armData[16]) | + ((uint32_t)armData[17] << 8) | + ((uint32_t)armData[18] << 16) | + ((uint32_t)armData[19] << 24)); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TrackingCalTxQecStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxQecStatus_t* txQecStatus) +{ + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + + uint8_t extData[3] = {ADRV9025_CPU_OBJECTID_CAL_STATUS, ADRV9025_CPU_OBJECTID_TXQEC_TRACKING, 0}; + uint8_t armData[24] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txQecStatus); + + switch (txChannel) + { + case ADI_ADRV9025_TX1: + extData[2] = 0; /*!< Tx0 channel enabled */ + break; + case ADI_ADRV9025_TX2: + extData[2] = 1; /*!< Tx1 channel enabled */ + break; + case ADI_ADRV9025_TX3: + extData[2] = 2; /*!< Tx2 channel enabled */ + break; + case ADI_ADRV9025_TX4: + extData[2] = 3; /*!< Tx3 channel enabled */ + break; + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid Tx Channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Executing Tracking cals TxQec status get Arm Command */ + adi_adrv9025_CpuCmdWriteWait( + device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData), + ADI_ADRV9025_GETTXQECSTATUS_TIMEOUT_US, + ADI_ADRV9025_GETTXQECSTATUS_INTERVAL_US, + ADRV9025_CPU_OBJECTID_TXQEC_TRACKING); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Tx Qec config from ARM mailbox */ + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Deserializing TxQec Status into the structure. */ + txQecStatus->errorCode = (uint32_t)(((uint32_t)armData[0]) | + ((uint32_t)armData[1] << 8) | + ((uint32_t)armData[2] << 16) | + ((uint32_t)armData[3] << 24)); + + txQecStatus->percentComplete = (uint32_t)(((uint32_t)armData[4]) | + ((uint32_t)armData[5] << 8) | + ((uint32_t)armData[6] << 16) | + ((uint32_t)armData[7] << 24)); + + txQecStatus->correctionMetric = (uint32_t)(((uint32_t)armData[8]) | + ((uint32_t)armData[9] << 8) | + ((uint32_t)armData[10] << 16) | + ((uint32_t)armData[11] << 24)); + + txQecStatus->iterCount = (uint32_t)(((uint32_t)armData[12]) | + ((uint32_t)armData[13] << 8) | + ((uint32_t)armData[14] << 16) | + ((uint32_t)armData[15] << 24)); + + txQecStatus->updateCount = (uint32_t)(((uint32_t)armData[16]) | + ((uint32_t)armData[17] << 8) | + ((uint32_t)armData[18] << 16) | + ((uint32_t)armData[19] << 24)); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TrackingCalRxQecStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxQecStatus_t* rxQecStatus) +{ + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + + uint8_t extData[3] = {ADRV9025_CPU_OBJECTID_CAL_STATUS, ADRV9025_CPU_OBJECTID_RXQEC_TRACKING, 0}; + uint8_t armData[20] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + rxQecStatus); + + switch (rxChannel) + { + case ADI_ADRV9025_RX1: + extData[2] = 0; /*!< Rx0 channel enabled */ + break; + case ADI_ADRV9025_RX2: + extData[2] = 1; /*!< Rx1 channel enabled */ + break; + case ADI_ADRV9025_RX3: + extData[2] = 2; /*!< Rx2 channel enabled */ + break; + case ADI_ADRV9025_RX4: + extData[2] = 3; /*!< Rx3 channel enabled */ + break; + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Executing Tracking cals RxQec status get Arm Command */ + adi_adrv9025_CpuCmdWriteWait( + device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData), + ADI_ADRV9025_GETRXQECSTATUS_TIMEOUT_US, + ADI_ADRV9025_GETRXQECSTATUS_INTERVAL_US, + ADRV9025_CPU_OBJECTID_RXQEC_TRACKING); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Rx QEC status config from ARM mailbox */ + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Deserializing Rx Qec Status into the structure. */ + rxQecStatus->errorCode = (uint32_t)(((uint32_t)armData[0]) | + ((uint32_t)armData[1] << 8) | + ((uint32_t)armData[2] << 16) | + ((uint32_t)armData[3] << 24)); + + rxQecStatus->percentComplete = (uint32_t)(((uint32_t)armData[4]) | + ((uint32_t)armData[5] << 8) | + ((uint32_t)armData[6] << 16) | + ((uint32_t)armData[7] << 24)); + + rxQecStatus->selfcheckIrrDb = (uint32_t)(((uint32_t)armData[8]) | + ((uint32_t)armData[9] << 8) | + ((uint32_t)armData[10] << 16) | + ((uint32_t)armData[11] << 24)); + + rxQecStatus->iterCount = (uint32_t)(((uint32_t)armData[12]) | + ((uint32_t)armData[13] << 8) | + ((uint32_t)armData[14] << 16) | + ((uint32_t)armData[15] << 24)); + + rxQecStatus->updateCount = (uint32_t)(((uint32_t)armData[16]) | + ((uint32_t)armData[17] << 8) | + ((uint32_t)armData[18] << 16) | + ((uint32_t)armData[19] << 24)); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TrackingCalOrxQecStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e orxChannel, + adi_adrv9025_OrxQecStatus_t* orxQecStatus) +{ + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + + uint8_t extData[3] = {ADRV9025_CPU_OBJECTID_CAL_STATUS, ADRV9025_CPU_OBJECTID_ORXQEC_TRACKING, 0}; + uint8_t armData[20] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + orxQecStatus); + + switch (orxChannel) + { + case ADI_ADRV9025_ORX1: + extData[2] = 0; /*!< ORx0 channel enabled */ + break; + case ADI_ADRV9025_ORX2: + extData[2] = 1; /*!< ORx1 channel enabled */ + break; + case ADI_ADRV9025_ORX3: + extData[2] = 2; /*!< ORx2 channel enabled */ + break; + case ADI_ADRV9025_ORX4: + extData[2] = 3; /*!< ORx3 channel enabled */ + break; + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + orxChannel, + "Invalid ORx Channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Executing Tracking cals ORxQec status get Arm Command */ + adi_adrv9025_CpuCmdWriteWait( + device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData), + ADI_ADRV9025_GETORXQECSTATUS_TIMEOUT_US, + ADI_ADRV9025_GETORXQECSTATUS_INTERVAL_US, + ADRV9025_CPU_OBJECTID_ORXQEC_TRACKING); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Orx QEC status config from ARM mailbox */ + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Deserializing Orx Qec Status into the structure. */ + orxQecStatus->errorCode = (uint32_t)(((uint32_t)armData[0]) | + ((uint32_t)armData[1] << 8) | + ((uint32_t)armData[2] << 16) | + ((uint32_t)armData[3] << 24)); + + orxQecStatus->percentComplete = (uint32_t)(((uint32_t)armData[4]) | + ((uint32_t)armData[5] << 8) | + ((uint32_t)armData[6] << 16) | + ((uint32_t)armData[7] << 24)); + + orxQecStatus->selfcheckIrrDb = (uint32_t)(((uint32_t)armData[8]) | + ((uint32_t)armData[9] << 8) | + ((uint32_t)armData[10] << 16) | + ((uint32_t)armData[11] << 24)); + + orxQecStatus->iterCount = (uint32_t)(((uint32_t)armData[12]) | + ((uint32_t)armData[13] << 8) | + ((uint32_t)armData[14] << 16) | + ((uint32_t)armData[15] << 24)); + + orxQecStatus->updateCount = (uint32_t)(((uint32_t)armData[16]) | + ((uint32_t)armData[17] << 8) | + ((uint32_t)armData[18] << 16) | + ((uint32_t)armData[19] << 24)); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TrackingCalClgcStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_ClgcTrackingCalStatus_t* clgcStatus) +{ + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + + uint8_t extData[3] = {ADRV9025_CPU_OBJECTID_CAL_STATUS, ADRV9025_CPU_OBJECTID_CLGC_TRACKING, 0}; + uint8_t armData[20] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + clgcStatus); + + switch (txChannel) + { + case ADI_ADRV9025_TX1: + extData[2] = 0; /*!< Tx0 channel enabled */ + break; + case ADI_ADRV9025_TX2: + extData[2] = 1; /*!< Tx1 channel enabled */ + break; + case ADI_ADRV9025_TX3: + extData[2] = 2; /*!< Tx2 channel enabled */ + break; + case ADI_ADRV9025_TX4: + extData[2] = 3; /*!< Tx3 channel enabled */ + break; + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid Tx Channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Executing Tracking cals Tx LOL status get Arm Command */ + adi_adrv9025_CpuCmdWriteWait( + device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData), + ADI_ADRV9025_GETTXCLGCSTATUS_TIMEOUT_US, + ADI_ADRV9025_GETTXCLGCSTATUS_INTERVAL_US, + ADRV9025_CPU_OBJECTID_CLGC_TRACKING); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Tx LOL config from ARM mailbox */ + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Deserializing CLGC Status into the structure. */ + clgcStatus->errorCode = (adi_adrv9025_ClgcTrackingCalError_e)(((uint32_t)armData[0]) | + ((uint32_t)armData[1] << 8) | + ((uint32_t)armData[2] << 16) | + ((uint32_t)armData[3] << 24)); + + clgcStatus->percentComplete = (uint32_t)(((uint32_t)armData[4]) | + ((uint32_t)armData[5] << 8) | + ((uint32_t)armData[6] << 16) | + ((uint32_t)armData[7] << 24)); + + clgcStatus->varianceMetric = (uint32_t)(((uint32_t)armData[8]) | + ((uint32_t)armData[9] << 8) | + ((uint32_t)armData[10] << 16) | + ((uint32_t)armData[11] << 24)); + + clgcStatus->iterCount = (uint32_t)(((uint32_t)armData[12]) | + ((uint32_t)armData[13] << 8) | + ((uint32_t)armData[14] << 16) | + ((uint32_t)armData[15] << 24)); + + clgcStatus->updateCount = (uint32_t)(((uint32_t)armData[16]) | + ((uint32_t)armData[17] << 8) | + ((uint32_t)armData[18] << 16) | + ((uint32_t)armData[19] << 24)); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TrackingCalRxHd2StatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxHd2Status_t* rxHd2Status) +{ + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + + uint8_t extData[3] = {ADRV9025_CPU_OBJECTID_CAL_STATUS, ADRV9025_CPU_OBJECTID_RXHD2_TRACKING, 0}; + uint8_t armData[20] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + rxHd2Status); + + switch (rxChannel) + { + case ADI_ADRV9025_RX1: + extData[2] = 0; /*!< Rx0 channel enabled */ + break; + case ADI_ADRV9025_RX2: + extData[2] = 1; /*!< Rx1 channel enabled */ + break; + case ADI_ADRV9025_RX3: + extData[2] = 2; /*!< Rx2 channel enabled */ + break; + case ADI_ADRV9025_RX4: + extData[2] = 3; /*!< Rx3 channel enabled */ + break; + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Executing Tracking cals RxHd2 status get Arm Command */ + adi_adrv9025_CpuCmdWriteWait( + device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &extData[0], + 3, + ADI_ADRV9025_GETRXHD2STATUS_TIMEOUT_US, + ADI_ADRV9025_GETRXHD2STATUS_INTERVAL_US, + ADRV9025_CPU_OBJECTID_RXHD2_TRACKING); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Rx Hd2 status config from ARM mailbox */ + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Deserializing Rx Hd2 Status into the structure. */ + rxHd2Status->errorCode = (uint32_t)(((uint32_t)armData[0]) | + ((uint32_t)armData[1] << 8) | + ((uint32_t)armData[2] << 16) | + ((uint32_t)armData[3] << 24)); + + rxHd2Status->percentComplete = (uint32_t)(((uint32_t)armData[4]) | + ((uint32_t)armData[5] << 8) | + ((uint32_t)armData[6] << 16) | + ((uint32_t)armData[7] << 24)); + + rxHd2Status->confidenceLevel = (uint32_t)(((uint32_t)armData[8]) | + ((uint32_t)armData[9] << 8) | + ((uint32_t)armData[10] << 16) | + ((uint32_t)armData[11] << 24)); + + rxHd2Status->iterCount = (uint32_t)(((uint32_t)armData[12]) | + ((uint32_t)armData[13] << 8) | + ((uint32_t)armData[14] << 16) | + ((uint32_t)armData[15] << 24)); + + rxHd2Status->updateCount = (uint32_t)(((uint32_t)armData[16]) | + ((uint32_t)armData[17] << 8) | + ((uint32_t)armData[18] << 16) | + ((uint32_t)armData[19] << 24)); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TrackingCalRxHd2CfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxHd2Config_t* hd2CalConfig) +{ + uint8_t armData[6] = {0}; + uint32_t fwStatus = 0; + uint8_t status = 0; + uint16_t byteOffset = 0; + uint8_t byteCount = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, hd2CalConfig); + + /* read firmware state to make sure ARM is in ready/IDLE mode */ + ADRV9025_SPIREADBYTE("ARM_CMD_STATUS_8", + ADRV9025_CPU_C_ADDR_CMD_STATUS_8, + &status); + ADI_ERROR_RETURN(device->common.error.newAction); + + fwStatus = (uint32_t)status; + + /* Throw error if not in READY state */ + if (fwStatus != ADRV9025_CPU_FW_STATUS_READY) + { + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUCMD, + ADI_COMMON_ERR_API_FAIL, + ADI_ADRV9025_ACT_ERR_RESET_CPU, + device, + "Device not in READY state. Error in adi_adrv9025_TrackingCalRxHd2CfgSet()\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Range check to see if only sideband update needed */ + if ((hd2CalConfig->control == 0) && (hd2CalConfig->correctStart == 0) && (hd2CalConfig->correctStop == 0)) + { + armData[0] = (uint8_t)((hd2CalConfig->posSideBandSel > 0) ? 1 : 0); + byteCount = 1; + } + + /* range check start stop freq range */ + else if ((hd2CalConfig->correctStart >= hd2CalConfig->correctStop)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + hd2CalConfig->correctStart, + "Invalid correction start/stop frequency range specified"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + else + { + armData[0] = (uint8_t)((hd2CalConfig->posSideBandSel > 0) ? 1 : 0); + armData[1] = (uint8_t)hd2CalConfig->control; + armData[2] = (uint8_t)hd2CalConfig->correctStart; + armData[3] = (uint8_t)(hd2CalConfig->correctStart >> 8); + armData[4] = (uint8_t)hd2CalConfig->correctStop; + armData[5] = (uint8_t)(hd2CalConfig->correctStop >> 8); + byteCount = 6; + } + + adi_adrv9025_CpuConfigWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_OBJECTID_RXHD2_TRACKING, + byteOffset, + &armData[0], + byteCount); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TrackingCalRxHd2CfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxHd2Config_t* hd2CalConfig) +{ + uint8_t armData[6] = {0}; + uint32_t fwStatus = 0; + uint8_t status = 0; + uint16_t byteOffset = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, hd2CalConfig); + + /* read firmware state to make sure ARM is in ready/IDLE mode */ + ADRV9025_SPIREADBYTE("ARM_CMD_STATUS_8", + ADRV9025_CPU_C_ADDR_CMD_STATUS_8, + &status); + ADI_ERROR_RETURN(device->common.error.newAction); + + fwStatus = (uint32_t)status; + + /* Throw error if not in READY state */ + if (fwStatus != ADRV9025_CPU_FW_STATUS_READY) + { + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUCMD, + ADI_COMMON_ERR_API_FAIL, + ADI_ADRV9025_ACT_ERR_RESET_CPU, + device, + "Device not in READY state. Error in adi_adrv9025_TrackingCalsEnableSet()\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + adi_adrv9025_CpuConfigRead(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_OBJECTID_RXHD2_TRACKING, + byteOffset, + &armData[0], + 6); + ADI_ERROR_RETURN(device->common.error.newAction); + + hd2CalConfig->posSideBandSel = armData[0]; + hd2CalConfig->control = armData[1]; + hd2CalConfig->correctStart = (uint32_t)(((uint32_t)armData[2]) | + ((uint32_t)armData[3] << 8)); + hd2CalConfig->correctStop = (uint32_t)(((uint32_t)armData[4]) | + ((uint32_t)armData[5] << 8)); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TrackingCalAllStateGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TrackingCalState_t* CalState) +{ + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + + uint8_t extData[1] = {ADRV9025_CPU_OBJECTID_TRACKING_CALS_STATE}; + uint8_t armData[41] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, CalState); + + /* Executing TRACKING_CALS_STATE Arm Command */ + adi_adrv9025_CpuCmdWriteWait(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData), + ADI_ADRV9025_GETTCALS_STATE_TIMEOUT_US, + ADI_ADRV9025_GETTCALS_STATE_INTERVAL_US, + ADRV9025_CPU_OBJECTID_TRACKING_CALS_STATE); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Test tone config from ARM mailbox */ + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Deserialize ARM Data into TrackingCalState Structure */ + + /* Deserializing calibration Error (first 4 bytes) */ + CalState->calError = (uint32_t)(((uint32_t)armData[0]) | + ((uint32_t)armData[1] << 8) | + ((uint32_t)armData[2] << 16) | + ((uint32_t)armData[3] << 24)); + + /* Deserializing Rx Qec state for channel 1/2/3/4 */ + CalState->rx1Qec = armData[8]; + CalState->rx2Qec = armData[9]; + CalState->rx3Qec = armData[10]; + CalState->rx4Qec = armData[11]; + + /* Deserializing Orx Qec state for channel 1/2/3/4 */ + CalState->orx1Qec = armData[12]; + CalState->orx2Qec = armData[13]; + CalState->orx3Qec = armData[14]; + CalState->orx4Qec = armData[15]; + + /* Deserializing Tx LOL state for channel 1/2/3/4 */ + CalState->tx1Lol = armData[16]; + CalState->tx2Lol = armData[17]; + CalState->tx3Lol = armData[18]; + CalState->tx4Lol = armData[19]; + + /* Deserializing Tx Qec state for channel 1/2/3/4 */ + CalState->tx1Qec = armData[20]; + CalState->tx2Qec = armData[21]; + CalState->tx3Qec = armData[22]; + CalState->tx4Qec = armData[23]; + + /* Deserializing Tx DPD state for channel 1/2/3/4 */ + CalState->tx1Dpd = armData[24]; + CalState->tx2Dpd = armData[25]; + CalState->tx3Dpd = armData[26]; + CalState->tx4Dpd = armData[27]; + + /* Deserializing Tx CLGC state for channel 1/2/3/4 */ + CalState->tx1Clgc = armData[28]; + CalState->tx2Clgc = armData[29]; + CalState->tx3Clgc = armData[30]; + CalState->tx4Clgc = armData[31]; + + /* Deserializing VSWR state for channel 1/2/3/4 */ + CalState->tx1Vswr = armData[32]; + CalState->tx2Vswr = armData[33]; + CalState->tx3Vswr = armData[34]; + CalState->tx4Vswr = armData[35]; + + /* Deserializing Rx Hd2 state for channel 1/2/3/4 */ + CalState->rx1Hd2 = armData[36]; + CalState->rx2Hd2 = armData[37]; + CalState->rx3Hd2 = armData[38]; + CalState->rx4Hd2 = armData[39]; + + /* Deserializer Deserializer tracking cal state */ + CalState->deserializer = armData[40]; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_ExternalPathDelaySet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_ExternalPathDelay_t* externalPathDelay) +{ + static const uint8_t DPD_PATH_DELAY_CTRL_PARAM = 0x10; + static const uint8_t MAX_INTERPOLATION_INDEX = 15; + + uint8_t extData[4] = {ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL, ADRV9025_CPU_OBJECTID_DPD_TRACKING, (uint8_t)txChannel, DPD_PATH_DELAY_CTRL_PARAM}; + uint8_t armData[2] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, externalPathDelay); + + armData[0] = externalPathDelay->fifoDelay; + armData[1] = externalPathDelay->interpolationIndex; + + /* Throw an error if the requested Tx channel is invalid */ + if ((txChannel != ADI_ADRV9025_TX1) && + (txChannel != ADI_ADRV9025_TX2) && + (txChannel != ADI_ADRV9025_TX3) && + (txChannel != ADI_ADRV9025_TX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid target Tx Channel requested to set external path delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Throw an error if the interpolation index is greater than 15 */ + if (externalPathDelay->interpolationIndex > MAX_INTERPOLATION_INDEX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + externalPathDelay, + "Invalid interpolation index encountered while attempting to configure external path delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Write the external path delay config to ARM mailbox */ + adi_adrv9025_CpuMemWrite(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_SET, + &armData[0], + sizeof(armData), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Executing external path delay set Arm Command */ + adi_adrv9025_CpuCmdWriteWait(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_SET_OPCODE, + &extData[0], + sizeof(extData), + ADI_ADRV9025_SETEXTPATHDELAY_TIMEOUT_US, + ADI_ADRV9025_SETEXTPATHDELAY_INTERVAL_US, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ExternalPathDelayGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_ExternalPathDelay_t* externalPathDelay) +{ + static const uint8_t DPD_PATH_DELAY_CTRL_PARAM = 0x00; + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + + uint8_t extData[4] = {ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL, ADRV9025_CPU_OBJECTID_DPD_TRACKING, (uint8_t)txChannel, DPD_PATH_DELAY_CTRL_PARAM}; + uint8_t armData[20] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, externalPathDelay); + + /* Throw an error if the requested Tx channel is invalid */ + if ((txChannel != ADI_ADRV9025_TX1) && + (txChannel != ADI_ADRV9025_TX2) && + (txChannel != ADI_ADRV9025_TX3) && + (txChannel != ADI_ADRV9025_TX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid Tx Channel requested to retrieve external path delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Executing external path delay get Arm Command */ + adi_adrv9025_CpuCmdWriteWait(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_SET_OPCODE, + &extData[0], + sizeof(extData), + ADI_ADRV9025_SETEXTPATHDELAY_TIMEOUT_US, + ADI_ADRV9025_SETEXTPATHDELAY_INTERVAL_US, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL); + ADI_ERROR_RETURN(device->common.error.newAction); + + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_SET, + &armData[0], + sizeof(armData), + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Update the external path delay struct with the value read from the device */ + externalPathDelay->fifoDelay = armData[0]; + externalPathDelay->interpolationIndex = armData[1]; + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DigDcOffsetMShiftSet(adi_adrv9025_Device_t* device, + adi_adrv9025_DcOffSet_t dcOffSetMShift) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + static const uint8_t MSHIFT_MAX_RANGE = 31; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* range check mShift value */ + if (dcOffSetMShift.mShift > MSHIFT_MAX_RANGE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + dcOffSetMShift.mShift, + "mShift value out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* check channel and set the address */ + switch (dcOffSetMShift.dcChannelSelect) + { + case ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH0: + recoveryAction = adrv9025_RxBbdcMShiftBfSet(device, + ADRV9025_BF_RX_CH0, + dcOffSetMShift.mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH1: + recoveryAction = adrv9025_RxBbdcMShiftBfSet(device, + ADRV9025_BF_RX_CH1, + dcOffSetMShift.mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH2: + recoveryAction = adrv9025_RxBbdcMShiftBfSet(device, + ADRV9025_BF_RX_CH2, + dcOffSetMShift.mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH3: + recoveryAction = adrv9025_RxBbdcMShiftBfSet(device, + ADRV9025_BF_RX_CH3, + dcOffSetMShift.mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX2_CH0: + recoveryAction = adrv9025_OrxBbdcOrx2MShiftBfSet(device, + ADRV9025_BF_ORX_CH0, + dcOffSetMShift.mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX2_CH1: + recoveryAction = adrv9025_OrxBbdcOrx2MShiftBfSet(device, + ADRV9025_BF_ORX_CH1, + dcOffSetMShift.mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX_CH0: + recoveryAction = adrv9025_OrxBbdcMShiftBfSet(device, + ADRV9025_BF_ORX_CH0, + dcOffSetMShift.mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX_CH1: + recoveryAction = adrv9025_OrxBbdcMShiftBfSet(device, + ADRV9025_BF_ORX_CH1, + dcOffSetMShift.mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK1_CH0: + recoveryAction = adrv9025_OrxBbdcLoopbackMShiftBfSet(device, + ADRV9025_BF_ORX_CH0, + dcOffSetMShift.mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK1_CH1: + recoveryAction = adrv9025_OrxBbdcLoopbackMShiftBfSet(device, + ADRV9025_BF_ORX_CH1, + dcOffSetMShift.mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + dcOffSetMShift.dcChannelSelect, + "Invalid DcOffSet Channel Selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DigDcOffsetMShiftGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DcOffSet_t* dcOffSetMShift) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + dcOffSetMShift); + + /* check channel and set the address */ + switch (dcOffSetMShift->dcChannelSelect) + { + case ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH0: + recoveryAction = adrv9025_RxBbdcMShiftBfGet(device, + ADRV9025_BF_RX_CH0, + &dcOffSetMShift->mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH1: + recoveryAction = adrv9025_RxBbdcMShiftBfGet(device, + ADRV9025_BF_RX_CH1, + &dcOffSetMShift->mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH2: + recoveryAction = adrv9025_RxBbdcMShiftBfGet(device, + ADRV9025_BF_RX_CH2, + &dcOffSetMShift->mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH3: + recoveryAction = adrv9025_RxBbdcMShiftBfGet(device, + ADRV9025_BF_RX_CH3, + &dcOffSetMShift->mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX2_CH0: + recoveryAction = adrv9025_OrxBbdcOrx2MShiftBfGet(device, + ADRV9025_BF_ORX_CH0, + &dcOffSetMShift->mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX2_CH1: + recoveryAction = adrv9025_OrxBbdcOrx2MShiftBfGet(device, + ADRV9025_BF_ORX_CH1, + &dcOffSetMShift->mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX_CH0: + recoveryAction = adrv9025_OrxBbdcMShiftBfGet(device, + ADRV9025_BF_ORX_CH0, + &dcOffSetMShift->mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX_CH1: + recoveryAction = adrv9025_OrxBbdcMShiftBfGet(device, + ADRV9025_BF_ORX_CH1, + &dcOffSetMShift->mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK1_CH0: + recoveryAction = adrv9025_OrxBbdcLoopbackMShiftBfGet(device, + ADRV9025_BF_ORX_CH0, + &dcOffSetMShift->mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + case ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK1_CH1: + recoveryAction = adrv9025_OrxBbdcLoopbackMShiftBfGet(device, + ADRV9025_BF_ORX_CH1, + &dcOffSetMShift->mShift); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + dcOffSetMShift.dcChannelSelect, + "Invalid DcOffSet Channel Selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DigDcOffsetEnableSet(adi_adrv9025_Device_t* device, + uint16_t channelDisableEnableMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* RX Channel0 */ + if ((channelDisableEnableMask & (uint16_t)ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH0) > 0) + { + recoveryAction = adrv9025_RxBbdcTrackingEnableBfSet(device, + ADRV9025_BF_RX_CH0, + ADI_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_RxBbdcTrackingEnableBfSet(device, + ADRV9025_BF_RX_CH0, + ADI_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* RX Channel1 */ + if ((channelDisableEnableMask & (uint16_t)ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH1) > 0) + { + recoveryAction = adrv9025_RxBbdcTrackingEnableBfSet(device, + ADRV9025_BF_RX_CH1, + ADI_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_RxBbdcTrackingEnableBfSet(device, + ADRV9025_BF_RX_CH1, + ADI_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* RX Channel2 */ + if ((channelDisableEnableMask & (uint16_t)ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH2) > 0) + { + recoveryAction = adrv9025_RxBbdcTrackingEnableBfSet(device, + ADRV9025_BF_RX_CH2, + ADI_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_RxBbdcTrackingEnableBfSet(device, + ADRV9025_BF_RX_CH2, + ADI_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* RX Channel3 */ + if ((channelDisableEnableMask & (uint16_t)ADI_ADRV9025_MSHIFT_DC_OFFSET_RX_CH3) > 0) + { + recoveryAction = adrv9025_RxBbdcTrackingEnableBfSet(device, + ADRV9025_BF_RX_CH3, + ADI_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_RxBbdcTrackingEnableBfSet(device, + ADRV9025_BF_RX_CH3, + ADI_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* ORX Channel0 */ + if ((channelDisableEnableMask & (uint16_t)ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX_CH0) > 0) + { + recoveryAction = adrv9025_OrxBbdcTrackingEnableBfSet(device, + ADRV9025_BF_ORX_CH0, + ADI_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_OrxBbdcTrackingEnableBfSet(device, + ADRV9025_BF_ORX_CH0, + ADI_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* ORX Channel1 */ + if ((channelDisableEnableMask & (uint16_t)ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX_CH1) > 0) + { + recoveryAction = adrv9025_OrxBbdcTrackingEnableBfSet(device, + ADRV9025_BF_ORX_CH1, + ADI_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_OrxBbdcTrackingEnableBfSet(device, + ADRV9025_BF_ORX_CH1, + ADI_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* ORX2 Channel0 */ + if ((channelDisableEnableMask & (uint16_t)ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX2_CH0) > 0) + { + recoveryAction = adrv9025_OrxBbdcOrx2TrackingEnableBfSet(device, + ADRV9025_BF_ORX_CH0, + ADI_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_OrxBbdcOrx2TrackingEnableBfSet(device, + ADRV9025_BF_ORX_CH0, + ADI_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* ORX2 Channel1 */ + if ((channelDisableEnableMask & (uint16_t)ADI_ADRV9025_MSHIFT_DC_OFFSET_ORX2_CH1) > 0) + { + recoveryAction = adrv9025_OrxBbdcOrx2TrackingEnableBfSet(device, + ADRV9025_BF_ORX_CH1, + ADI_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_OrxBbdcOrx2TrackingEnableBfSet(device, + ADRV9025_BF_ORX_CH1, + ADI_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* ORXLoopback1 Channel0 */ + if ((channelDisableEnableMask & (uint16_t)ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK1_CH0) > 0) + { + recoveryAction = adrv9025_OrxBbdcLoopback1TrackingEnableBfSet(device, + ADRV9025_BF_ORX_CH0, + ADI_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_OrxBbdcLoopback1TrackingEnableBfSet(device, + ADRV9025_BF_ORX_CH0, + ADI_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* ORXLoopback1 Channel1 */ + if ((channelDisableEnableMask & (uint16_t)ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK1_CH1) > 0) + { + recoveryAction = adrv9025_OrxBbdcLoopback1TrackingEnableBfSet(device, + ADRV9025_BF_ORX_CH1, + ADI_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_OrxBbdcLoopback1TrackingEnableBfSet(device, + ADRV9025_BF_ORX_CH1, + ADI_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* ORXLoopback2 Channel0 */ + if ((channelDisableEnableMask & (uint16_t)ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK2_CH0) > 0) + { + recoveryAction = adrv9025_OrxBbdcLoopback2TrackingEnableBfSet(device, + ADRV9025_BF_ORX_CH0, + ADI_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_OrxBbdcLoopback2TrackingEnableBfSet(device, + ADRV9025_BF_ORX_CH0, + ADI_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* ORXLoopback2 Channel1 */ + if ((channelDisableEnableMask & (uint16_t)ADI_ADRV9025_MSHIFT_DC_OFFSET_ORXLPBACK2_CH1) > 0) + { + recoveryAction = adrv9025_OrxBbdcLoopback2TrackingEnableBfSet(device, + ADRV9025_BF_ORX_CH1, + ADI_ENABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_OrxBbdcLoopback2TrackingEnableBfSet(device, + ADRV9025_BF_ORX_CH1, + ADI_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DigDcOffsetEnableGet(adi_adrv9025_Device_t* device, + uint16_t* channelDisableEnableMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t enableStatus = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + channelDisableEnableMask); + + *channelDisableEnableMask = 0; + + /* ORXLoopback2 Channel1 */ + recoveryAction = adrv9025_OrxBbdcLoopback2TrackingEnableBfGet(device, + ADRV9025_BF_ORX_CH1, + &enableStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + *channelDisableEnableMask = (*channelDisableEnableMask | (uint16_t)enableStatus) << 1; + + /* ORXLoopback2 Channel0 */ + recoveryAction = adrv9025_OrxBbdcLoopback2TrackingEnableBfGet(device, + ADRV9025_BF_ORX_CH0, + &enableStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + *channelDisableEnableMask = (*channelDisableEnableMask | (uint16_t)enableStatus) << 1; + + /* ORXLoopback1 Channel1 */ + recoveryAction = adrv9025_OrxBbdcLoopback1TrackingEnableBfGet(device, + ADRV9025_BF_ORX_CH1, + &enableStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + *channelDisableEnableMask = (*channelDisableEnableMask | (uint16_t)enableStatus) << 1; + + /* ORXLoopback1 Channel0 */ + recoveryAction = adrv9025_OrxBbdcLoopback1TrackingEnableBfGet(device, + ADRV9025_BF_ORX_CH0, + &enableStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + *channelDisableEnableMask = (*channelDisableEnableMask | (uint16_t)enableStatus) << 1; + + /* ORX2 Channel1 */ + recoveryAction = adrv9025_OrxBbdcOrx2TrackingEnableBfGet(device, + ADRV9025_BF_ORX_CH1, + &enableStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + *channelDisableEnableMask = (*channelDisableEnableMask | (uint16_t)enableStatus) << 1; + + /* ORX2 Channel0 */ + recoveryAction = adrv9025_OrxBbdcOrx2TrackingEnableBfGet(device, + ADRV9025_BF_ORX_CH0, + &enableStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + *channelDisableEnableMask = (*channelDisableEnableMask | (uint16_t)enableStatus) << 1; + + /* ORX Channel1 */ + recoveryAction = adrv9025_OrxBbdcTrackingEnableBfGet(device, + ADRV9025_BF_ORX_CH1, + &enableStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + *channelDisableEnableMask = (*channelDisableEnableMask | (uint16_t)enableStatus) << 1; + + /* ORX Channel0 */ + recoveryAction = adrv9025_OrxBbdcTrackingEnableBfGet(device, + ADRV9025_BF_ORX_CH0, + &enableStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + *channelDisableEnableMask = (*channelDisableEnableMask | (uint16_t)enableStatus) << 1; + + /* RX Channel3 */ + recoveryAction = adrv9025_RxBbdcTrackingEnableBfGet(device, + ADRV9025_BF_RX_CH3, + &enableStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + *channelDisableEnableMask = (*channelDisableEnableMask | (uint16_t)enableStatus) << 1; + + /* RX Channel2 */ + recoveryAction = adrv9025_RxBbdcTrackingEnableBfGet(device, + ADRV9025_BF_RX_CH2, + &enableStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + *channelDisableEnableMask = (*channelDisableEnableMask | (uint16_t)enableStatus) << 1; + + /* RX Channel1 */ + recoveryAction = adrv9025_RxBbdcTrackingEnableBfGet(device, + ADRV9025_BF_RX_CH1, + &enableStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + *channelDisableEnableMask = (*channelDisableEnableMask | (uint16_t)enableStatus) << 1; + + /* RX Channel0 */ + recoveryAction = adrv9025_RxBbdcTrackingEnableBfGet(device, + ADRV9025_BF_RX_CH0, + &enableStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + *channelDisableEnableMask = (*channelDisableEnableMask | (uint16_t)enableStatus); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ExtTxLolChannelReset(adi_adrv9025_Device_t* device, + adi_adrv9025_ExtTxLolChannelReset_t* txLolReset) +{ + uint32_t i = 0; + uint8_t extData[4] = {ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL, ADRV9025_CPU_OBJECTID_TXLOLEXT_INIT, 0, txLolReset->resetType}; + uint8_t txChannel = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, txLolReset); + + /* Range check */ + if ((txLolReset->channelSelect & ADI_ADRV9025_TXALL) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + dcOffSetMShift.dcChannelSelect, + "Invalid TX Channel Selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADRV9025_NUMBER_OF_TX_CHANNELS; i++) + { + txChannel = (1 << i); + if (txLolReset->channelSelect & txChannel) + { + extData[2] = txChannel; + } + else + { + continue; + } + + /* sending write config command */ + adi_adrv9025_CpuCmdWriteWait(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_SET_OPCODE, + &extData[0], + 4, + ADI_ADRV9025_ENTRACKINGCALS_TIMEOUT_US, + ADI_ADRV9025_ENTRACKINGCALS_INTERVAL_US, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_ENABLE); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DualBandSwitchingTimeGet(adi_adrv9025_Device_t* device, + uint32_t* milliseconds) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t data[4] = {0}; + uint16_t byteOffset = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + milliseconds); + + recoveryAction = adi_adrv9025_CpuConfigRead(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_OBJECTID_DUALBANDCFG, + byteOffset, + &data[0], + sizeof(data)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to read Dual Band switching time command"); + ADI_ERROR_RETURN(device->common.error.newAction); + + *milliseconds = (uint32_t)(data[0] | data[1] << 8 | data[2] << 16 | data[3] << 24); + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DualBandSwitchingTimeSet(adi_adrv9025_Device_t* device, + uint32_t milliseconds) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t armData[4] = {0}; + uint16_t byteOffset = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Range check */ + if ((milliseconds < ADI_ADRV9025_SWITCH_TIME_MIN) || (milliseconds > ADI_ADRV9025_SWITCH_TIME_MAX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + milliseconds, + "Invalid Parameter, Milliseconds out of expected range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + armData[0] = (uint8_t)((milliseconds >> 0) & 0xff); + armData[1] = (uint8_t)((milliseconds >> 8) & 0xff); + armData[2] = (uint8_t)((milliseconds >> 16) & 0xff); + armData[3] = (uint8_t)((milliseconds >> 24) & 0xff); + + recoveryAction = adi_adrv9025_CpuConfigWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_OBJECTID_DUALBANDCFG, + byteOffset, + &armData[0], + sizeof(armData)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "CpuConfigWrite failed writing CPU memory"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + + +int32_t adi_adrv9025_ClgcExternalPathDelaySet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_ExternalPathDelay_t* externalPathDelay) +{ + static const uint8_t PATH_DELAY_CTRL_PARAM = 0x10; + static const uint8_t MAX_INTERPOLATION_INDEX = 15; + + uint8_t extData[4] = { ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL, ADRV9025_CPU_OBJECTID_CLGC_TRACKING, (uint8_t)txChannel, PATH_DELAY_CTRL_PARAM }; + uint8_t armData[2] = { 0 }; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, externalPathDelay); + + armData[0] = externalPathDelay->fifoDelay; + armData[1] = externalPathDelay->interpolationIndex; + + /* Throw an error if the requested Tx channel is invalid */ + if ((txChannel != ADI_ADRV9025_TX1) && + (txChannel != ADI_ADRV9025_TX2) && + (txChannel != ADI_ADRV9025_TX3) && + (txChannel != ADI_ADRV9025_TX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid target Tx Channel requested to set CLGC external path delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Throw an error if the interpolation index is greater than 15 */ + if (externalPathDelay->interpolationIndex > MAX_INTERPOLATION_INDEX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + externalPathDelay, + "Invalid interpolation index encountered while attempting to configure CLGC external path delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Write the external path delay config to ARM mailbox */ + adi_adrv9025_CpuMemWrite(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_SET, + &armData[0], + sizeof(armData), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Executing external path delay set Arm Command */ + adi_adrv9025_CpuCmdWriteWait(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_SET_OPCODE, + &extData[0], + sizeof(extData), + ADI_ADRV9025_SETEXTPATHDELAY_TIMEOUT_US, + ADI_ADRV9025_SETEXTPATHDELAY_INTERVAL_US, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ClgcExternalPathDelayGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_ExternalPathDelay_t* externalPathDelay) +{ + static const uint8_t PATH_DELAY_CTRL_PARAM = 0x00; + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + + uint8_t extData[4] = { ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL, ADRV9025_CPU_OBJECTID_CLGC_TRACKING, (uint8_t)txChannel, PATH_DELAY_CTRL_PARAM }; + uint8_t armData[20] = { 0 }; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + externalPathDelay); + + /* Throw an error if the requested Tx channel is invalid */ + if ((txChannel != ADI_ADRV9025_TX1) && + (txChannel != ADI_ADRV9025_TX2) && + (txChannel != ADI_ADRV9025_TX3) && + (txChannel != ADI_ADRV9025_TX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid Tx Channel requested to retrieve CLGC external path delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Executing external path delay get Arm Command */ + adi_adrv9025_CpuCmdWriteWait(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_SET_OPCODE, + &extData[0], + sizeof(extData), + ADI_ADRV9025_SETEXTPATHDELAY_TIMEOUT_US, + ADI_ADRV9025_SETEXTPATHDELAY_INTERVAL_US, + ADRV9025_CPU_OBJECTID_TRACKING_CAL_CTRL); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_SET, + &armData[0], + sizeof(armData), + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Update the external path delay struct with the value read from the device */ + externalPathDelay->fifoDelay = armData[0]; + externalPathDelay->interpolationIndex = armData[1]; + + return (device->common.error.newAction); +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_cpu.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_cpu.c new file mode 100644 index 0000000..cf590ed --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_cpu.c @@ -0,0 +1,1924 @@ +/** +* \file adi_adrv9025_cpu.c +* \brief Contains Adrv9025's processor features related function +* implementation declared in adi_adrv9025.h +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.txt" file in this zip file. +*/ + +#include "adi_adrv9025.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_cpu.h" +#include "adi_adrv9025_error.h" +#include "../../private/include/adrv9025_bf_core.h" +#include "../../private/include/adrv9025_cpu.h" +#include "../../private/include/adrv9025_reg_addr_macros.h" +#include "../../private/include/adrv9025_init.h" + +#ifdef _RELEASE_BUILD_ +#line __LINE__ "adi_adrv9025_cpu.c" +#endif + +/*****************************************************************************/ +/***** Helper functions' prototypes ******************************************/ +/*****************************************************************************/ +static int32_t adrv9025_CpuStackPtrWrite( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + const uint32_t* buf); + +static int32_t adrv9025_CpuBootAddrWrite( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + const uint32_t* buf); + +static uint32_t adrv9025_CpuIntFromBytesGet( + const uint8_t* buf, + uint8_t size); + +/*****************************************************************************/ +/***** Helper functions' definition ******************************************/ +/*****************************************************************************/ +int32_t adrv9025_CpuStackPtrWrite(adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + const uint32_t* buf) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + const uint8_t* bytes = (const uint8_t *)buf; + + cpuAddr = adrv9025_CpuAddrGet(&device->devStateInfo.cpu, + cpuType); + ADI_NULL_PTR_RETURN(&device->common, + cpuAddr); + ADRV9025_SPIWRITEBYTE("CPU_STACK_PTR_BYTE_0", + cpuAddr->stackPtrAddr, + bytes[0]); + ADRV9025_SPIWRITEBYTE("CPU_STACK_PTR_BYTE_1", + cpuAddr->stackPtrAddr + 1u, + bytes[1]); + ADRV9025_SPIWRITEBYTE("CPU_STACK_PTR_BYTE_2", + cpuAddr->stackPtrAddr + 2u, + bytes[2]); + ADRV9025_SPIWRITEBYTE("CPU_STACK_PTR_BYTE_3", + cpuAddr->stackPtrAddr + 3u, + bytes[3]); + return (device->common.error.newAction); +} + +int32_t adrv9025_CpuBootAddrWrite(adi_adrv9025_Device_t *device, + adi_adrv9025_CpuType_e cpuType, + const uint32_t *buf) +{ + adi_adrv9025_CpuAddr_t *cpuAddr = NULL; + const uint8_t *bytes = (const uint8_t *)buf; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + cpuAddr = adrv9025_CpuAddrGet(&device->devStateInfo.cpu, cpuType); + + ADI_NULL_PTR_RETURN(&device->common, cpuAddr); + + ADRV9025_SPIWRITEBYTE("CPU_BOOT_ADDR_BYTE_0", cpuAddr->bootAddr, bytes[0]); + ADRV9025_SPIWRITEBYTE("CPU_BOOT_ADDR_BYTE_1", cpuAddr->bootAddr + 1u, bytes[1]); + ADRV9025_SPIWRITEBYTE("CPU_BOOT_ADDR_BYTE_2", cpuAddr->bootAddr + 2u, bytes[2]); + ADRV9025_SPIWRITEBYTE("CPU_BOOT_ADDR_BYTE_3", cpuAddr->bootAddr + 3u, bytes[3]); + + return (device->common.error.newAction); +} + +uint32_t adrv9025_CpuIntFromBytesGet(const uint8_t* buf, + uint8_t size) +{ + uint32_t result = 0; + uint8_t i = 0; + + if (size <= 4) + { + for (i = 0; i < size; i++) + { + result |= (uint32_t)(*(buf + i)) << (i * 8); + } + } + + return result; +} + +/*****************************************************************************/ +/***** Public functions' definition ******************************************/ +/*****************************************************************************/ +int32_t adi_adrv9025_CpuStartStatusCheck( + adi_adrv9025_Device_t* device, + uint32_t timeout_us) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t halError = (int32_t)ADI_COMMON_HAL_OK; + uint8_t i = 0; + adi_adrv9025_CpuType_e cpuType = ADI_ADRV9025_CPU_TYPE_C; + uint32_t fwStatus = 0; + uint32_t waitInterval_us = 0; + uint32_t numEventChecks = 1; + uint32_t eventCheck = 0; + uint8_t status = 0; + adi_adrv9025_CpuChecksumTable_t checksum = {{0}}; + uint8_t checksumValid = 0; + uint8_t cpuDebugLoaded = + ((device->devStateInfo.devState & ADI_ADRV9025_STATE_CPUDEBUGLOADED) == ADI_ADRV9025_STATE_CPUDEBUGLOADED) ? 1 : 0; + uint8_t statusReadErrorFlag = 0; + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + const char* errStr = NULL; + + static const uint32_t ADRV9025_CPU_FWSTATUS_ERROR = ADI_ADRV9025_SRC_CPUFWSTATUS << 16; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADRV9025_BUGINFO(__FUNCTION__); + + /* Wait for CPU to exit BOOTUP state */ + waitInterval_us = (ADI_ADRV9025_GETCPUBOOTUP_INTERVAL_US > timeout_us) ? + timeout_us : ADI_ADRV9025_GETCPUBOOTUP_INTERVAL_US; + numEventChecks = (waitInterval_us == 0) ? 1 : (timeout_us / waitInterval_us); + + /* Get ARM-C address map */ + cpuAddr = adrv9025_CpuAddrGet(&device->devStateInfo.cpu, cpuType); + ADI_NULL_PTR_RETURN(&device->common, + cpuAddr); + + for (eventCheck = 0; eventCheck <= numEventChecks && cpuAddr->enabled != ADI_FALSE; eventCheck++) + { + ADRV9025_SPIREADBYTE("CPU_CMD_STATUS_8", + cpuAddr->cmdStatusAddr + 8u, + &status); + fwStatus = (uint32_t)status; + + /* if Non-boot status or Non-ready status encountered retry read for sticky error reported */ + if ((fwStatus != ADRV9025_CPU_FW_STATUS_POWERUP)) + { + /* Confirm CPU status is consistent for 5 reads*/ + for (i = 0; i < 5; i++) + { + ADRV9025_SPIREADBYTE("CPU_CMD_STATUS_8", + cpuAddr->cmdStatusAddr + 8u, + &status); + + if ((uint8_t)fwStatus != status) + { + statusReadErrorFlag = 1; + break; + } + } + } + + if (statusReadErrorFlag == 0) + { + if (fwStatus == ADRV9025_CPU_FW_STATUS_POWERUP) + { + /* Evaluate first since it's the most common case. Wait interval then check again */ + /* If the ARM is stuck in powerup state, the API needs to generate an error */ + if (eventCheck == numEventChecks) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + (ADRV9025_CPU_FWSTATUS_ERROR + fwStatus), + ADI_COMMON_ACT_ERR_RESET_FEATURE, + device, + "CpuBootStatus_e: 1 - : CPU is stuck in Powerup mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + halError = adi_common_hal_Wait_us(&device->common, + waitInterval_us); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + halError, + ADI_COMMON_ACT_ERR_CHECK_TIMER, + device, + "Timer not working"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if ((cpuDebugLoaded == 1) && (fwStatus == ADRV9025_CPU_FW_STATUS_CPU_DEBUG_READY)) + { + /* Wait for CPU to load from JTAG */ + halError = adi_common_hal_Wait_us(&device->common, + waitInterval_us); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + halError, + ADI_COMMON_ACT_ERR_CHECK_TIMER, + device, + "Timer not working"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if ((cpuDebugLoaded == 0) && (fwStatus == ADRV9025_CPU_FW_STATUS_CPU_DEBUG_READY)) + { + device->devStateInfo.devState = (adi_adrv9025_ApiStates_e)(device->devStateInfo.devState | ADI_ADRV9025_STATE_CPUDEBUGLOADED); + return (device->common.error.newAction); + } + else if (fwStatus == ADRV9025_CPU_FW_STATUS_READY) + { + break; /* Valid case - CPU booted successfully */ + } + else + { + recoveryAction = ADI_ADRV9025_ACT_ERR_RESET_CPU; + switch (fwStatus) + { + case ADRV9025_CPU_FW_STATUS_FW_CHECKSUM_ERROR: + errStr = "CpuBootStatus_e: 2 - CPU Firmware checksum error"; + break; + case ADRV9025_CPU_FW_STATUS_DATA_MEMORY_ERROR: + errStr = "CpuBootStatus_e: 3 - CPU data memory error"; + break; + case ADRV9025_CPU_FW_STATUS_STREAM_CHECKSUM_ERROR: + errStr = "CpuBootStatus_e: 4 - Stream image checksum error"; + break; + case ADRV9025_CPU_FW_STATUS_PROFILE_ERROR: + errStr = "CpuBootStatus_e: 5 - Device profile checksum error"; + break; + case ADRV9025_CPU_FW_STATUS_CLKPLL_PROGRAMING_ERROR: + errStr = "CpuBootStatus_e: 6 - Bootup clkgen setup error"; + break; + case ADRV9025_CPU_FW_STATUS_JESD_SETUP_CONFIG_ERROR: + errStr = "CpuBootStatus_e: 7 - Bootup Jesd setup error"; + break; + case ADRV9025_CPU_FW_STATUS_POWER_UP_INIT_ERROR: + errStr = "CpuBootStatus_e: 8 - Power init setup error"; + break; + case ADRV9025_CPU_FW_STATUS_CLKLOGEN_ERROR: + errStr = "CpuBootStatus_e: 10 - Bootup clock LOGEN error"; + break; + case ADRV9025_CPU_FW_STATUS_RXQEC_HARDWARE_ERROR: + errStr = "CpuBootStatus_e: 11 - Error initializing RxQEC hardware"; + break; + case ADRV9025_CPU_FW_STATUS_HW_TIMER_ERROR: + errStr = "CpuBootStatus_e: 12 - Failed to create Health monitor timers"; + break; + case ADRV9025_CPU_FW_STATUS_ADC_RCAL_ERROR: + errStr = "CpuBootStatus_e: 13 - ADC RCAL error"; + break; + case ADRV9025_CPU_FW_STATUS_STREAM_RUNTIME_ERROR: + errStr = "CpuBootStatus_e: 14 - STREAM RUNTIME error"; + break; + case ADRV9025_CPU_FW_STATUS_BOOT_CLKGEN_RCAL_ERROR: + errStr = "CpuBootStatus_e: 15 - BOOT CLKGEN RCAL error"; + break; + case ADRV9025_CPU_FW_STATUS_BOOT_LDO_CONFIG_ERROR: + /* Attempt full hardware reset if LDO configuration is incorrect */ + recoveryAction = adi_adrv9025_HwReset(device); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "CpuBootStatus_e: 16 - LDO Configured Incorrectly, adi_adrv9025_HwReset Failed"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + errStr = "CpuBootStatus_e: 16 - LDO Configured Incorrectly"; + recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + break; + case ADRV9025_CPU_FW_STATUS_INVCHN_CONFIG_ERROR: + errStr = "CpuBootStatus_e: 17 - Detected device does not support the configured init channel mask"; + break; + case ADRV9025_CPU_D_FW_STATUS_CHECKSUM_ERROR: + errStr = "CpuBootStatus_e: 19 - ARM-D Firmware checksum error"; + break; + case ADRV9025_CPU_D_FW_STATUS_BOOT_ERROR: + errStr = "CpuBootStatus_e: 20 - ARM-D Boot error"; + break; + default: + errStr = "CpuBootStatus_e: CPU Unknown error during bootup"; + break; + } + + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUFWSTATUS, + (ADRV9025_CPU_FWSTATUS_ERROR + fwStatus), + recoveryAction, + device, + errStr); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else + { + statusReadErrorFlag = 0; + } + } + + if (cpuDebugLoaded == 0) + { + checksumValid = ADI_FALSE; + recoveryAction = adi_adrv9025_CpuChecksumTableGet(device, + cpuType, + &checksum, + &checksumValid); + if (checksumValid == ADI_FALSE) + { + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPU, + ADI_COMMON_ERR_API_FAIL, + ADI_ADRV9025_ACT_ERR_RESET_CPU, + checksumValid, + "Checksum is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + } + + + device->devStateInfo.devState = (adi_adrv9025_ApiStates_e)(device->devStateInfo.devState | ADI_ADRV9025_STATE_CPULOADED); + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "CpuStartStatusCheck Failed"); + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuChecksumTableGet( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + adi_adrv9025_CpuChecksumTable_t* checksum, + uint8_t* checksumValid) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t halError = (int32_t)ADI_COMMON_HAL_OK; + uint32_t buildTimeChecksum = 0x00000000; + uint32_t calculatedChecksum = 0x00000000; + uint8_t checkData[sizeof(adi_adrv9025_CpuChecksumTable_t)] = {0}; + uint32_t checkAddr = 0; + uint32_t timeout_us = ADI_ADRV9025_VERIFY_CPU_CHKSUM_TIMEOUT_US; + uint32_t waitInterval_us = ADI_ADRV9025_VERIFY_CPU_CHKSUM_INTERVAL_US; + uint32_t numEventChecks = 1; + uint32_t eventCheck = 0; + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + uint8_t cpuDebugLoaded = + ((device->devStateInfo.devState & ADI_ADRV9025_STATE_CPUDEBUGLOADED) == ADI_ADRV9025_STATE_CPUDEBUGLOADED) ? 1 : 0; + int j = 0; + int i = 0; + + static const uint8_t CHECKSUM_BYTES = 0x4; + static const uint8_t CHECKSUMENTRYSIZE = 8; + static const uint32_t MIN_TIMEOUT_US = 10000; + + /* Cpu stream checksum order: main, rx1/2/3/4, tx1/2/3/4, orx12/34 */ + static const uint32_t streamChannel[] = { + 0xFFFFFFFF, + ADI_ADRV9025_RX1, + ADI_ADRV9025_RX2, + ADI_ADRV9025_RX3, + ADI_ADRV9025_RX4, + ADI_ADRV9025_TX1 << ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET, + ADI_ADRV9025_TX2 << ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET, + ADI_ADRV9025_TX3 << ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET, + ADI_ADRV9025_TX4 << ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET, + (ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2 | ADI_ADRV9025_LB12), + (ADI_ADRV9025_ORX3 | ADI_ADRV9025_ORX4 | ADI_ADRV9025_LB34) + }; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + checksum); + + ADI_NULL_PTR_RETURN(&device->common, + checksumValid); + + ADRV9025_BUGINFO(__FUNCTION__); + + /* This function is only supported for ARM-C */ + if ((adi_adrv9025_CpuType_e)cpuType != ADI_ADRV9025_CPU_TYPE_C) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + cpuType, + "This function can only be called for CPU-C"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + + + /* get the particular processor's address map */ + cpuAddr = adrv9025_CpuAddrGet(&device->devStateInfo.cpu, + cpuType); + ADI_NULL_PTR_RETURN(&device->common, + cpuAddr); + + if (timeout_us < MIN_TIMEOUT_US) + { + /* Set minimum timeout of 10 ms. Prevent divide by zero error */ + timeout_us = MIN_TIMEOUT_US; + } + + recoveryAction = adi_adrv9025_CpuMemRead(device, + cpuAddr->structChecksumAddr, + checkData, + CHECKSUM_BYTES, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to read CPU memory"); + ADI_ERROR_RETURN(device->common.error.newAction); + + checkAddr = ((((uint32_t)checkData[3]) << 24) | (((uint32_t)checkData[2]) << 16) | (((uint32_t)checkData[1]) << 8) | ((uint32_t)checkData[0])); + + + + waitInterval_us = (waitInterval_us > timeout_us) ? timeout_us : waitInterval_us; + numEventChecks = (waitInterval_us == 0) ? 1 : (timeout_us / waitInterval_us); + + for (eventCheck = 0; eventCheck <= numEventChecks; eventCheck++) + { + adi_adrv9025_CpuMemRead(device, + checkAddr, + &checkData[0], + sizeof(checkData), + 0); + ADI_ERROR_RETURN(device->common.error.newAction); + + buildTimeChecksum = ((((uint32_t)checkData[3]) << 24) | (((uint32_t)checkData[2]) << 16) | (((uint32_t)checkData[1]) << 8) | ((uint32_t)checkData[0])); + calculatedChecksum = ((((uint32_t)checkData[7]) << 24) | (((uint32_t)checkData[6]) << 16) | (((uint32_t)checkData[5]) << 8) | ((uint32_t)checkData[4])); + + + + if ((calculatedChecksum == 0) && (eventCheck < numEventChecks)) + { + /* wait */ + halError = adi_common_hal_Wait_us(&device->common, + timeout_us); + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + halError, + ADI_COMMON_ACT_ERR_CHECK_TIMER, + eventCheck, + "Timer not working"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + break; + } + } + + + + /* CPU completed calculating checksum */ + if ((calculatedChecksum > 0) && (buildTimeChecksum > 0)) + { + *checksumValid = 1; + checksum->fwCheckSums.buildChecksum = buildTimeChecksum; + checksum->fwCheckSums.runChecksum = calculatedChecksum; + + + + /* performing checksum check, skip if checksum was not calculated (CPU DEBUG_MODE)*/ + if ((cpuDebugLoaded == 0) && (buildTimeChecksum != calculatedChecksum)) + { + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPU, + ADI_COMMON_ERR_API_FAIL, + ADI_ADRV9025_ACT_ERR_RESET_CPU, + calculatedChecksum, + "FW checksum is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (j = 0; j < 11; j++) + { + i = CHECKSUMENTRYSIZE * (j + 1); + buildTimeChecksum = ((((uint32_t)checkData[i + 3]) << 24) | (((uint32_t)checkData[i + 2]) << 16) | (((uint32_t)checkData[i + 1]) << 8) | ((uint32_t) + checkData[i + 0])); + calculatedChecksum = ((((uint32_t)checkData[i + 7]) << 24) | (((uint32_t)checkData[i + 6]) << 16) | (((uint32_t)checkData[i + 5]) << 8) | ((uint32_t + )checkData[i + 4])); + + + checksum->streamsCheckSum[j].buildChecksum = buildTimeChecksum; + checksum->streamsCheckSum[j].runChecksum = calculatedChecksum; + + /* Skip if channel not initialize */ + if ((device->devStateInfo.initializedChannels & streamChannel[j]) > 0) + { + /* performing checksum check */ + if (buildTimeChecksum != calculatedChecksum) + { + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUCMD, + ADI_COMMON_ERR_API_FAIL, + ADI_ADRV9025_ACT_ERR_RESET_CPU, + calculatedChecksum, + "Streams checksum is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + //i = offsetof(adi_adrv9025_checksumTable_t, deviceProfileCheckSum); + i = CHECKSUMENTRYSIZE * 12; + buildTimeChecksum = ((((uint32_t)checkData[i + 3]) << 24) | (((uint32_t)checkData[i + 2]) << 16) | (((uint32_t)checkData[i + 1]) << 8) | ((uint32_t) + checkData[i + 0])); + calculatedChecksum = ((((uint32_t)checkData[i + 7]) << 24) | (((uint32_t)checkData[i + 6]) << 16) | (((uint32_t)checkData[i + 5]) << 8) | ((uint32_t) + checkData[i + 4])); + + + checksum->deviceProfileCheckSum.buildChecksum = buildTimeChecksum; + checksum->deviceProfileCheckSum.runChecksum = calculatedChecksum; + +#if ADI_ADRV9025_PROFILE_CHECKSUM_ENABLE > 0 + /* performing checksum check */ + if (buildTimeChecksum != calculatedChecksum) + { + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUCMD, + ADI_COMMON_ERR_API_FAIL, + ADI_ADRV9025_ACT_ERR_RESET_CPU, + calculatedChecksum, + "CPU's Device Profile checksum is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + i = CHECKSUMENTRYSIZE * 13; + buildTimeChecksum = ((((uint32_t)checkData[i + 3]) << 24) | (((uint32_t)checkData[i + 2]) << 16) | (((uint32_t)checkData[i + 1]) << 8) | ((uint32_t) + checkData[i + 0])); + calculatedChecksum = ((((uint32_t)checkData[i + 7]) << 24) | (((uint32_t)checkData[i + 6]) << 16) | (((uint32_t)checkData[i + 5]) << 8) | ((uint32_t) + checkData[i + 4])); + + + checksum->adcProfilefwCheckSum.buildChecksum = buildTimeChecksum; + checksum->adcProfilefwCheckSum.runChecksum = calculatedChecksum; + +#if ADI_ADRV9025_PROFILE_CHECKSUM_ENABLE > 0 + /* performing checksum check */ + if (buildTimeChecksum != calculatedChecksum) + { + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUCMD, + ADI_COMMON_ERR_API_FAIL, + ADI_ADRV9025_ACT_ERR_RESET_CPU, + calculatedChecksum, + "Adc Profile checksum is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuCmdStatusGet(adi_adrv9025_Device_t *device, + adi_adrv9025_CpuType_e cpuType, + uint16_t *errorWord, + uint16_t *statusWord) +{ + uint8_t i = 0; + uint8_t bytes[8] = {0}; + uint8_t status = 0; + static const uint8_t CPU_ERR_MASK_LO = 0x0E; + static const uint8_t CPU_ERR_MASK_HI = 0xE0; + static const uint8_t CPU_PENDING_LO = 0x01; + static const uint8_t CPU_PENDING_HI = 0x10; + static const uint8_t ERROR_WORD_LO = 0x0001; + static const uint8_t ERROR_WORD_HI = 0x0002; + static const uint8_t STATUS_WORD_SHIFT_HI = 3; + static const uint8_t CMD_STATUS_MAX = 8; + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + +#if (ADRV9025_INIT_SPI_DEBUG > 0) + static const char *cmdStatus[8] = + { + "CPU_CMD_STATUS_0", + "CPU_CMD_STATUS_1", + "CPU_CMD_STATUS_2", + "CPU_CMD_STATUS_3", + "CPU_CMD_STATUS_4", + "CPU_CMD_STATUS_5", + "CPU_CMD_STATUS_6", + "CPU_CMD_STATUS_7" + }; +#endif + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, errorWord); + + ADI_NULL_PTR_RETURN(&device->common, statusWord); + + ADRV9025_BUGINFO(__FUNCTION__); + + /* ensuring the errorWord and statusWord are cleared */ + *errorWord = 0; + *statusWord = 0; + + /* get the particular processor's address map */ + cpuAddr = adrv9025_CpuAddrGet(&device->devStateInfo.cpu, cpuType); + + ADI_NULL_PTR_RETURN(&device->common, cpuAddr); + + /* read in the entire 64-bit status register into a byte array and parse one byte at a time */ + for (i = 0; i < CMD_STATUS_MAX; i++) + { +#if (ADRV9025_INIT_SPI_DEBUG > 0) + ADRV9025_SPIREADBYTE(cmdStatus[i], cpuAddr->cmdStatusAddr + i, &bytes[i]); +#else + ADRV9025_SPIREADBYTE("", cpuAddr->cmdStatusAddr + i, &bytes[i]); +#endif + + + /* assigning each pending bit from every opcode to a weighted position in statusWord */ + status = (bytes[i] & CPU_PENDING_HI) >> STATUS_WORD_SHIFT_HI; + status |= (bytes[i] & CPU_PENDING_LO); + *statusWord |= (uint16_t)(status << (i * 2)); + + /* checking each 3-bit error field per nibble for > 0, then assigning to weighted bit in errorWord */ + if ((bytes[i] & CPU_ERR_MASK_LO) > 0) + { + *errorWord |= (ERROR_WORD_LO << (i * 2)); + } + + if ((bytes[i] & CPU_ERR_MASK_HI) > 0) + { + *errorWord |= (ERROR_WORD_HI << (i * 2)); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuConfigWrite( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint8_t objectId, + uint16_t byteOffset, + const uint8_t data[], + uint8_t byteCount) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + uint8_t extendedData[4] = {0}; + uint8_t cmdStatusByte = 0; + static const uint8_t CPU_ERR_MASK = 0x0E; + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + data); + + ADRV9025_BUGINFO(__FUNCTION__); + + /* check for valid byteCount */ + if (byteCount == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid byteCount"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* get the particular processor's address map */ + cpuAddr = adrv9025_CpuAddrGet(&device->devStateInfo.cpu, + cpuType); + ADI_NULL_PTR_RETURN(&device->common, + cpuAddr); + + extendedData[0] = byteCount; + extendedData[1] = 0; + extendedData[2] = 0; + extendedData[3] = 0; + recoveryAction = adi_adrv9025_CpuMemWrite(device, + cpuAddr->mailboxSetAddr, + &extendedData[0], + 1, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "CpuConfigWrite failed writing CPU memory"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_adrv9025_CpuMemWrite(device, + cpuAddr->mailboxSetAddr + 1, + &data[0], + byteCount, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* CPU Object id, byte offset LSB, offset MSB = 0, copy 2 bytes */ + extendedData[0] = ADRV9025_CPU_OBJECTID_CONFIG; + extendedData[1] = objectId; + extendedData[2] = (byteOffset & 0xFF); + extendedData[3] = ((byteOffset >> 8) & 0xFF); + + adi_adrv9025_CpuCmdWrite(device, + cpuType, + ADRV9025_CPU_SET_OPCODE, + &extendedData[0], + 4); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + cpuType, + ADRV9025_CPU_SET_OPCODE, + &cmdStatusByte, + ADI_ADRV9025_WRITECPUCFG_TIMEOUT_US, + ADI_ADRV9025_WRITECPUCFG_INTERVAL_US); + + + + if ((cmdStatusByte & CPU_ERR_MASK) > 0) + { + adrv9025_CpuCmdErrorHandler(device, + cpuType, + ADI_ADRV9025_SRC_CPUCMD, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuAdcProfilesWrite( + adi_adrv9025_Device_t* device, + const adi_adrv9025_AdcProfiles_t* adcProfiles) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + adcProfiles); + + ADRV9025_BUGINFO(__FUNCTION__); + + recoveryAction = adrv9025_CpuAdcProfilesWrite(device, + adcProfiles); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "CpuAdcProfilesWrite Failed"); + + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuProfileWrite( + adi_adrv9025_Device_t* device, + const adi_adrv9025_Init_t* init) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + init); + + ADRV9025_BUGINFO(__FUNCTION__); + + recoveryAction = adrv9025_CpuProfileWrite(device, + init); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "CpuProfileWrite Failed"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuStart( + adi_adrv9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t reg = 0u; + uint8_t mailBox[4] = {0xFF, 0xFF, 0xFF, 0xFF}; + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADRV9025_BUGINFO(__FUNCTION__); + + /* get the processor's address map for ARM-C and start it. ARM-D will be started by ARM-C if available*/ + cpuAddr = adrv9025_CpuAddrGet(&device->devStateInfo.cpu, + ADI_ADRV9025_CPU_TYPE_C); + ADI_NULL_PTR_RETURN(&device->common, + cpuAddr); + + if (cpuAddr->enabled != ADI_FALSE) + { + /* Set MailBox 0xFF for ARM-C. ARM-D doesn't have mailbox get buffer */ + recoveryAction = adi_adrv9025_CpuMemWrite(device, + cpuAddr->mailboxGetAddr, + &mailBox[0], + 4, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "CpuStart Failed"); + ADI_ERROR_RETURN(device->common.error.newAction); + + reg = ADRV9025_CPU_MASK_CTL1_DEBUG_ENABLE | ADRV9025_CPU_MASK_CTL1_M3_RUN; + ADRV9025_SPIWRITEBYTE("ARM_CTL_1", + cpuAddr->ctlAddr, + reg); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "CPU type C's FW image need to be loaded"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuCmdStatusOpcodeGet(adi_adrv9025_Device_t *device, + adi_adrv9025_CpuType_e cpuType, + uint8_t opCode, + uint8_t *cmdStatByte) +{ + uint8_t cmdByteIndex = 0; + uint8_t cmdByte = 0; + uint8_t cmdByteVerify = 0; + uint8_t cpuStatusBitShift = 0; + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + static const uint8_t CPU_STATUS_MASK = 0x0F; + static const uint8_t CPU_STATUS_SHIFT_HI = 4; + static const uint8_t CPU_PENDING = 0x01; + +#if (ADRV9025_INIT_SPI_DEBUG > 0) + static const char *cmdStatus[8] = { + "CPU_CMD_STATUS_0", + "CPU_CMD_STATUS_1", + "CPU_CMD_STATUS_2", + "CPU_CMD_STATUS_3", + "CPU_CMD_STATUS_4", + "CPU_CMD_STATUS_5", + "CPU_CMD_STATUS_6", + "CPU_CMD_STATUS_7" + }; +#endif + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, cmdStatByte); + + ADRV9025_BUGINFO(__FUNCTION__); + + /* check for even-numbered opCodes including opcode 0, but must not be greater than 31 */ + if ((opCode != (uint8_t)ADRV9025_CPU_STREAM_TRIGGER_OPCODE) && ADRV9025_CPU_OPCODE_VALID(opCode)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid CPU opcode given to adi_adrv9025_CpuCmdStatusOpcodeGet()"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* get the particular processor's address map */ + cpuAddr = adrv9025_CpuAddrGet(&device->devStateInfo.cpu, cpuType); + ADI_NULL_PTR_RETURN(&device->common, cpuAddr); + + /* Set offset for stream and cpu status read */ + if (opCode == ADRV9025_CPU_STREAM_TRIGGER_OPCODE) + { + cpuStatusBitShift = CPU_STATUS_SHIFT_HI + 2; + } + else + { + cpuStatusBitShift = CPU_STATUS_SHIFT_HI; + } + + /* calculating command status register offset based on opcode status packing */ + cmdByteIndex = opCode >> 2; + + /* reading the command status register for given opcode */ + /* Two reads back to back for verify correct SPI operation */ +#if (ADRV9025_INIT_SPI_DEBUG > 0) + ADRV9025_SPIREADBYTE(cmdStatus[(cmdByteIndex % 8)], ((uint16_t)ADRV9025_CPU_C_ADDR_CMD_STATUS_0 + cmdByteIndex), &cmdByte); + + ADRV9025_SPIREADBYTE(cmdStatus[(cmdByteIndex % 8)], ((uint16_t)ADRV9025_CPU_C_ADDR_CMD_STATUS_0 + cmdByteIndex), &cmdByteVerify); +#else + ADRV9025_SPIREADBYTE("", cpuAddr->cmdStatusAddr + cmdByteIndex, &cmdByte); + + ADRV9025_SPIREADBYTE("", cpuAddr->cmdStatusAddr + cmdByteIndex, &cmdByteVerify); +#endif + + /* identifying nibble location in command register for given opcode */ + /* Manually set the pending bit if verification fails */ + if (((opCode >> 1) & (uint8_t)0x01) == (uint8_t)0x01) + { + *cmdStatByte = ((cmdByte == cmdByteVerify) ? ((cmdByte >> cpuStatusBitShift) & CPU_STATUS_MASK) + : ((cmdByte >> cpuStatusBitShift) & CPU_STATUS_MASK) | CPU_PENDING); + } + else + { + *cmdStatByte = ((cmdByte == cmdByteVerify) ? (cmdByte & CPU_STATUS_MASK) : (cmdByte & CPU_STATUS_MASK) | CPU_PENDING); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuCmdStatusWait( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint8_t opCode, + uint8_t* cmdStatusByte, + uint32_t timeout_us, + uint32_t waitInterval_us) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t halError = (int32_t)ADI_COMMON_HAL_OK; + uint32_t eventCheck = 0; + uint32_t numEventChecks = 0; + static const uint8_t CPU_ERR_MASK = 0x0E; + static const uint8_t CPU_PENDING = 0x01; + uint32_t exceptionValue = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + cmdStatusByte); + + ADRV9025_BUGINFO(__FUNCTION__); + + /* check for even-numbered opCodes including opcode 0, but must not be greater than 30 */ + if ((opCode != (uint8_t)ADRV9025_CPU_STREAM_TRIGGER_OPCODE) && ADRV9025_CPU_OPCODE_VALID(opCode)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid CPU opcode given to adi_adrv9025_CpuCmdStatusWait()"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + waitInterval_us = (waitInterval_us > timeout_us) ? timeout_us : waitInterval_us; + numEventChecks = (waitInterval_us == 0) ? 1 : (timeout_us / waitInterval_us); + + /* timeout event check loop */ + for (eventCheck = 0; eventCheck <= numEventChecks; eventCheck++) + { + /* read status of opcode */ + recoveryAction = adi_adrv9025_CpuCmdStatusOpcodeGet(device, + cpuType, + opCode, + cmdStatusByte); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to get CPU command status"); + ADI_ERROR_RETURN(device->common.error.newAction); + + + /* If error code is non zero in [3:1], - return error */ + if ((*cmdStatusByte & CPU_ERR_MASK) > 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUCMD, + ADI_COMMON_ERR_API_FAIL, + ADI_ADRV9025_ACT_ERR_RESET_CPU, + device, + "CpuCmdStatusWait() failed due to thrown CPU error. Is device in correct state for calling command?"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* if pending bit is set for opcode of interest and the number of events have not expired, perform wait */ + if (((*cmdStatusByte & CPU_PENDING) > 0) && + (eventCheck < numEventChecks)) + { + halError = adi_common_hal_Wait_us(&device->common, + waitInterval_us); + + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUCMD, + halError, + ADI_COMMON_ACT_ERR_CHECK_TIMER, + device, + "Timer not working in CpuCmdStatusWait()"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + break; + } + } + + /* if CPU Command did not complete within the timeout period */ + if ((*cmdStatusByte & CPU_PENDING) > 0) + { + /* Check if exception has occurred */ + recoveryAction = adi_adrv9025_CpuExceptionGet(device, + cpuType, + &exceptionValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Fail to get CPU exception"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (exceptionValue > 0) + { + if (exceptionValue == 0xFFFFFFFF) + { + exceptionValue = ADI_COMMON_ERR_CPU_EXCEPTION; + } + + /* Return the ARM Exception in Err code */ + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUCMD, + exceptionValue, + ADI_ADRV9025_ACT_ERR_RESET_CPU, + device, + "CpuCmdStatusWait() failed due to thrown CPU error. CPU time out "); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUCMD, + ADI_COMMON_ERR_API_FAIL, + ADI_ADRV9025_ACT_ERR_RESET_CPU, + device, + "CpuCmdStatusWait() failed due to thrown CPU error. CPU time out "); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuMailboxBusyGet( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint8_t* mailboxBusy) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + mailboxBusy); + + /* Read arm_command_busy bit in arm_command(0x00c3) register*/ + if (cpuType == ADI_ADRV9025_CPU_TYPE_C) + { + recoveryAction = adrv9025_CoreArmCommandBusyBfGet(device, + ADRV9025_BF_CORE, + mailboxBusy); + } + else if (cpuType == ADI_ADRV9025_CPU_TYPE_D) + { + recoveryAction = adrv9025_CoreArmDCommandBusyBfGet(device, + ADRV9025_BF_CORE, + mailboxBusy); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Invalid Get for cpu type"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Invalid Get for mailboxBusy"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_CpuCmdWrite( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint8_t opCode, + const uint8_t extendedData[], + uint8_t byteCount) +{ + int32_t halError = (int32_t)ADI_COMMON_HAL_OK; + uint8_t cpuCommandBusy = 0; + uint8_t i = 0; + uint32_t timeout_us = ADI_ADRV9025_SENDCPUCMD_TIMEOUT_US; + uint32_t waitInterval_us = ADI_ADRV9025_SENDCPUCMD_INTERVAL_US; + uint32_t eventCheck = 0; + uint32_t numEventChecks = 0; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + uint32_t exceptionValue = 0; + +#define EXT_CMD_BYTE_MAX 4 + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if (byteCount > 0) + { + ADI_NULL_PTR_RETURN(&device->common, + extendedData); + } + + ADRV9025_BUGINFO(__FUNCTION__); + + /* check for even-numbered opCodes only including opcode 0, but must not be greater than opCode 30 */ + if ((opCode != (uint8_t)ADRV9025_CPU_STREAM_TRIGGER_OPCODE) && ADRV9025_CPU_OPCODE_VALID(opCode)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid CPU opcode given to adi_adrv9025_CpuCmdWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* the number of valid extended data bytes is from 0-4 */ + if (byteCount > EXT_CMD_BYTE_MAX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid number of extended data in adi_adrv9025_CpuCmdWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* setting a 2 second timeout for mailbox busy bit to be clear (can't send an cpu mailbox command until mailbox is ready) */ + + waitInterval_us = (waitInterval_us > timeout_us) ? timeout_us : waitInterval_us; + numEventChecks = (waitInterval_us == 0) ? 1 : (timeout_us / waitInterval_us); + + /* timeout event loop to permit non-blocking of thread */ + for (eventCheck = 0; eventCheck <= numEventChecks; eventCheck++) + { + recoveryAction = adi_adrv9025_CpuMailboxBusyGet(device, + cpuType, + &cpuCommandBusy); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Invalid Get for adi_adrv9025_CpuMailboxBusyGet()"); + ADI_ERROR_RETURN(device->common.error.newAction); + + + if (cpuCommandBusy == ADI_TRUE) + { + halError = adi_common_hal_Wait_us(&device->common, + waitInterval_us); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + halError, + ADI_COMMON_ACT_ERR_CHECK_TIMER, + device, + "Timer not working in adi_adrv9025_CpuCmdWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + break; + } + } + + /* if busy bit remains set after timeout event loop function is exited, otherwise command is sent after extended bytes */ + if (cpuCommandBusy == ADI_TRUE) + { + /* Check if exception has occurred */ + recoveryAction = adi_adrv9025_CpuExceptionGet(device, + cpuType, + &exceptionValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Fail to get CPU exception"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (exceptionValue > 0) + { + if (exceptionValue == 0xFFFFFFFF) + { + exceptionValue = ADI_COMMON_ERR_CPU_EXCEPTION; + } + /* Return the ARM Exception in Err code */ + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUCMD, + exceptionValue, + ADI_ADRV9025_ACT_ERR_RESET_CPU, + device, + "CPU Mailbox Busy. Command not executed in adi_adrv9025_CpuCmdWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUCMD, + ADI_COMMON_ERR_API_FAIL, + ADI_ADRV9025_ACT_ERR_RESET_CPU, + device, + "CPU Mailbox Busy. Command not executed in adi_adrv9025_CpuCmdWrite()"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else + { + /* get the particular processor's address map */ + cpuAddr = adrv9025_CpuAddrGet(&device->devStateInfo.cpu, + cpuType); + ADI_NULL_PTR_RETURN(&device->common, + cpuAddr); + + if (byteCount > 0) + { + for (i = 0; i < byteCount; i++) + { + ADRV9025_SPIWRITEBYTE("Extend Data", + cpuAddr->extCmdAddr + i, + extendedData[i]); + } + } + + ADRV9025_SPIWRITEBYTE("CPU_COMMAND", + cpuAddr->cmdAddr, + opCode); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuCmdWriteWait(adi_adrv9025_Device_t *device, + adi_adrv9025_CpuType_e cpuType, + uint8_t armOpCode, + const uint8_t extendedData[], + uint8_t byteCount, + uint32_t waitTimeoutUs, + uint32_t waitIntervalUs, + uint8_t armObjId) +{ + uint8_t cmdStatusByte = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + adi_adrv9025_CpuCmdWrite(device, + cpuType, + armOpCode, + extendedData, + byteCount); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* waiting for command to finish successfully */ + adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + armOpCode, + &cmdStatusByte, + waitTimeoutUs, + waitIntervalUs); + + if ((cmdStatusByte >> ADRV9025_CPU_ERROR_SHIFT) > 0) + { + adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + ADI_ADRV9025_SRC_CPUCMD, + ADRV9025_CPU_CMD_ERRCODE(armOpCode, + armObjId, + cmdStatusByte), + ADI_COMMON_ACT_ERR_RESET_FEATURE); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuConfigRead( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint8_t objectId, + uint16_t byteOffset, + uint8_t returnData[], + uint8_t byteCount) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + uint8_t extendedData[4] = {0}; + uint8_t cmdStatusByte = 0; + static const uint8_t CPU_ERR_MASK = 0x0E; + static const uint8_t AUTO_INC_BIT = 0u; + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + returnData); + + ADRV9025_BUGINFO(__FUNCTION__); + + /* check for valid byteCount */ + if (byteCount == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid byteCount"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + extendedData[0] = byteCount; + extendedData[1] = 0; + extendedData[2] = 0; + extendedData[3] = 0; + + /* get the particular processor's address map */ + cpuAddr = adrv9025_CpuAddrGet(&device->devStateInfo.cpu, + cpuType); + ADI_NULL_PTR_RETURN(&device->common, + cpuAddr); + + recoveryAction = adi_adrv9025_CpuMemWrite(device, + cpuAddr->mailboxGetAddr, + &extendedData[0], + 1u, + AUTO_INC_BIT); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "adi_adrv9025_CpuMemWrite() failed"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* CPU Object id, byte offset LSB, offset MSB = 0, byteCount will read that number of bytes */ + extendedData[0] = ADRV9025_CPU_OBJECTID_CONFIG; + extendedData[1] = objectId; + extendedData[2] = (byteOffset & 0xFF); + extendedData[3] = ((byteOffset >> 8) & 0xFF); + + /* send the read config CPU opcode */ + adi_adrv9025_CpuCmdWrite(device, + cpuType, + ADRV9025_CPU_GET_OPCODE, + &extendedData[0], + 4); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* check the command status for timeout */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + cpuType, + ADRV9025_CPU_GET_OPCODE, + &cmdStatusByte, + ADI_ADRV9025_READCPUCFG_TIMEOUT_US, + ADI_ADRV9025_READCPUCFG_INTERVAL_US); + + + + if ((cmdStatusByte & CPU_ERR_MASK) > 0) + { + adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + ADI_ADRV9025_SRC_CPUCMD, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_RETURN(device->common.error.newAction); + } + + adi_adrv9025_CpuMemRead(device, + cpuAddr->mailboxGetAddr, + &returnData[0], + byteCount, + AUTO_INC_BIT); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuFwVersionGet( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + adi_adrv9025_CpuFwVersion_t* fwVersion) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t ver[8] = {0}; + uint32_t fullVersion = 0; + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + static const uint8_t CPU_FW_BUILD_DEBUG = 0x01; + static const uint8_t CPU_FW_BUILD_TESTOBJ = 0x04; + static const uint8_t CPU_FW_BUILD_USES_FOUR_DIGIT_VERSION = 0x01; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + fwVersion); + + ADRV9025_BUGINFO(__FUNCTION__); + + if ((device->devStateInfo.devState & ADI_ADRV9025_STATE_CPULOADED) != ADI_ADRV9025_STATE_CPULOADED) + { + ADI_ERROR_REPORT(&device->common, + ADI_ADRV9025_SRC_CPUCMD, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "CPU binary must be loaded before calling adi_adrv9025_CpuFwVersionGet()"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* get the particular processor's address map */ + cpuAddr = adrv9025_CpuAddrGet(&device->devStateInfo.cpu, + cpuType); + ADI_NULL_PTR_RETURN(&device->common, + cpuAddr); + + recoveryAction = adi_adrv9025_CpuMemRead(device, + cpuAddr->versionAddr, + &ver[0], + sizeof(ver), + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to read CPU memory"); + ADI_ERROR_RETURN(device->common.error.newAction); + + fullVersion = (((uint32_t)ver[0]) | (((uint32_t)ver[1]) << 8) | (((uint32_t)ver[2]) << 16) | (((uint32_t)ver[3]) << 24)); + + + if (ver[5] & CPU_FW_BUILD_USES_FOUR_DIGIT_VERSION) + { + fwVersion->majorVer = (uint8_t)(fullVersion >> 28) & 0x0F; + fwVersion->minorVer = (uint8_t)(fullVersion >> 24) & 0x0F; + fwVersion->maintVer = (uint8_t)(fullVersion >> 16) & 0xFF; + fwVersion->rcVer = (uint16_t)(fullVersion & 0xFFFF); + } + else + { + fwVersion->rcVer = (uint8_t)(fullVersion % 100); + fwVersion->minorVer = (uint8_t)((fullVersion / 100) % 100); + fwVersion->majorVer = (uint8_t)(fullVersion / 10000); + fwVersion->maintVer = 0; + } + + if (ver[4] & CPU_FW_BUILD_DEBUG) + { + fwVersion->cpuFwBuildType = ADI_ADRV9025_CPU_FW_BUILD_DEBUG; + } + else if (ver[4] & CPU_FW_BUILD_TESTOBJ) + { + fwVersion->cpuFwBuildType = ADI_ADRV9025_CPU_FW_BUILD_TESTOBJ; + } + else + { + fwVersion->cpuFwBuildType = ADI_ADRV9025_CPU_FW_BUILD_RELEASE; + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuMemRead( + adi_adrv9025_Device_t* device, + uint32_t address, + uint8_t returnData[], + uint32_t byteCount, + uint8_t autoIncrement) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + returnData); + + ADRV9025_BUGINFO(__FUNCTION__); + + /* check for bytecount */ + if (byteCount == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_NULL_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + byteCount, + "byteCount is zero"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (adrv9025_CpuValidateMemoryAddr(&device->devStateInfo.cpu, + address, + byteCount) == ADI_FALSE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + address, + "Invalid CPU Memory Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_CpuDmaMemRead(device, + address, + returnData, + byteCount, + autoIncrement); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "adrv9025_CpuDmaMemRead() failed during DMA transaction"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuImageWrite( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint32_t byteOffset, + const uint8_t binary[], + uint32_t byteCount) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + static const uint32_t ADRV9025_ADDR_DEVICE_PROFILE_OFFSET = 0x00000274; + static const uint32_t ADRV9025_ADDR_ADC_PROFILE_OFFSET = 0x00000278; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + binary); + + ADRV9025_BUGINFO(__FUNCTION__); + + if ((byteCount % 4) > 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + byteCount, + "Invalid byteCount. Must be multiple of 4."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((byteOffset % 4) > 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + byteCount, + "Invalid byteOffset. Must be multiple of 4."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* extraction of stack pointer and boot address from top of array */ + if (byteOffset == 0) + { + if (byteCount < 8) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + byteCount, + "Invalid byteCount. Must be larger than 8."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + adrv9025_CpuStackPtrWrite(device, + cpuType, + (const uint32_t *)binary); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_CpuBootAddrWrite(device, + cpuType, + (const uint32_t *)&binary[4]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (cpuType == ADI_ADRV9025_CPU_TYPE_C) + { + /* extraction of profile address */ + if ((ADRV9025_ADDR_DEVICE_PROFILE_OFFSET >= byteOffset) && + (ADRV9025_ADDR_DEVICE_PROFILE_OFFSET < (byteOffset + byteCount + 4))) + { + device->devStateInfo.cpu.devProfileAddr = adrv9025_CpuIntFromBytesGet( + binary + ADRV9025_ADDR_DEVICE_PROFILE_OFFSET - byteOffset, + 4); + } + + /* extraction of ADC profile address */ + if ((ADRV9025_ADDR_ADC_PROFILE_OFFSET >= byteOffset) && + (ADRV9025_ADDR_ADC_PROFILE_OFFSET < (byteOffset + byteCount + 4))) + { + device->devStateInfo.cpu.adcProfileAddr = adrv9025_CpuIntFromBytesGet( + binary + ADRV9025_ADDR_ADC_PROFILE_OFFSET - byteOffset, + 4); + } + } + + /* get the particular processor's address map */ + cpuAddr = adrv9025_CpuAddrGet(&device->devStateInfo.cpu, + cpuType); + ADI_NULL_PTR_RETURN(&device->common, + cpuAddr); + + recoveryAction = adi_adrv9025_CpuMemWrite( + device, + cpuAddr->progStartAddr + byteOffset, + &binary[0], + byteCount, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "CpuImageWrite Failed"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* mark the image loaded */ + cpuAddr->enabled = ADI_TRUE; + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuMemWrite( + adi_adrv9025_Device_t* device, + uint32_t address, + const uint8_t data[], + uint32_t byteCount, + uint8_t autoIncrement) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + data); + + ADRV9025_BUGINFO(__FUNCTION__); + + /* check for bytecount*/ + if (byteCount == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_NULL_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + byteCount, + "byteCount is zero"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (adrv9025_CpuValidateMemoryAddr(&device->devStateInfo.cpu, + address, + byteCount) == ADI_FALSE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + address, + "Invalid CPU Memory Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_CpuDmaMemWrite(device, + address, + data, + byteCount, + autoIncrement); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "CpuMemWrite failed during DMA transaction"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuExceptionGet( + adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + uint32_t* exceptionValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t exceptionArray[4] = {0}; + uint32_t armExceptionAddr = 0; /* Exception Flag Memory */ + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + exceptionValue); + + if (cpuType == ADI_ADRV9025_CPU_TYPE_C) + { + armExceptionAddr = 0x20028210; + } + else if (cpuType == ADI_ADRV9025_CPU_TYPE_D) + { + armExceptionAddr = 0x20000000; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Invalid CPU type selection for CpuExceptionGet"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adi_adrv9025_CpuMemRead(device, + armExceptionAddr, + &exceptionArray[0], + 4, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Read Arm memory"); + ADI_ERROR_RETURN(device->common.error.newAction); + + *exceptionValue = (uint32_t)(exceptionArray[0] | (exceptionArray[1] << 8) | (exceptionArray[2] << 16) | (exceptionArray[3] << 24)); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_CpuSystemErrorGet(adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + const char** errorMessage) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + const char* const localErrorMessage = "No CPU system error detected"; + uint16_t systemErrCode = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + errorMessage); + + recoveryAction = adrv9025_CpuSystemErrCodeGet(device, + cpuType, + &systemErrCode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + systemErrCode, + "Error while reading Arm System Error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Report Arm mailboxErrCode*/ + if (systemErrCode > 0) + { + *errorMessage = adrv9025_CpuErrCodeToString(device, + (uint32_t)systemErrCode); + if (*errorMessage == NULL) + { + /* We have an error code but it doesn't match anything in error list */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + systemErrCode, + ADI_COMMON_ACT_ERR_RESET_FEATURE, + systemErrCode, + "Error code couldn't be found, please check errCode field in device error structure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else + { + /* There is no ARM system error to be reported */ + *errorMessage = localErrorMessage; + } + + return ADI_COMMON_ACT_NO_ACTION; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_data_interface.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_data_interface.c new file mode 100644 index 0000000..3d25829 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_data_interface.c @@ -0,0 +1,4632 @@ +/** +* \file adi_adrv9025_data_interface.c +* \brief Contains Data interface features related function implementation defined in +* adi_adrv9025_data_interface.h +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "adi_adrv9025_data_interface.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_error.h" +#include "adi_adrv9025.h" +#include "../../private/include/adrv9025_data_interface.h" +#include "../../private/include/adrv9025_init.h" +#include "../../private/include/adrv9025_reg_addr_macros.h" +#include "../../private/include/adrv9025_bf_tx.h" +#include "../../private/include/adrv9025_bf_jesd_common.h" +#include "../../private/include/adrv9025_bf_jrx_link.h" +#include "../../private/include/adrv9025_bf_jtx_link.h" +#include "../../private/include/adrv9025_bf_rx.h" +#include "../../private/include/adrv9025_bf_core.h" + +#ifdef _RELEASE_BUILD_ + #line __LINE__ "adi_adrv9025_data_interface.c" +#endif + +int32_t adi_adrv9025_FramerCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_FramerSel_e framerSel, + adi_adrv9025_FrmCfg_t* framerCfg) +{ + adrv9025_BfJtxLinkChanAddr_e baseAddr = ADRV9025_BF_JTX_LINK0; + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + uint8_t channelId = 0; + uint8_t dataByte = 0; + uint8_t converter = 0; + uint8_t enabledFramers = 0; + uint8_t framerIdx = 0; + uint8_t* pLaneFramerOutSel = NULL; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_NULL_PTR_RETURN(&device->common, + framerCfg); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + retVal = adrv9025_JesdCommonJtxLinkEnBfGet(device, + ADRV9025_BF_JESD_COMMON, + &enabledFramers); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read jtx_link_en"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* check if the framer is enabled */ + if ((framerSel & enabledFramers) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Error framer is not enabled"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (framerSel == ADI_ADRV9025_FRAMER_0) + { + baseAddr = ADRV9025_BF_JTX_LINK0; + } + else if (framerSel == ADI_ADRV9025_FRAMER_1) + { + baseAddr = ADRV9025_BF_JTX_LINK1; + framerIdx = 1; + } + else if (framerSel == ADI_ADRV9025_FRAMER_2) + { + baseAddr = ADRV9025_BF_JTX_LINK2; + framerIdx = 2; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Error invalid Framer Config Get framerSel Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + framerCfg->enableJesd204C = device->devStateInfo.jesdCfg.framerCfg[framerIdx].enableJesd204C; + + retVal = adrv9025_JtxLinkJtxBidCfgBfGet(device, + baseAddr, + &framerCfg->bankId); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: bankId"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_JtxLinkJtxDidCfgBfGet(device, + baseAddr, + &framerCfg->deviceId); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: deviceId"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_JtxLinkJtxLidCfgBfGet(device, + baseAddr, + &framerCfg->lane0Id); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: lane0Id"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_JtxLinkJtxMCfgBfGet(device, + baseAddr, + &framerCfg->jesd204M); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: jesd204M"); + ADI_ERROR_RETURN(device->common.error.newAction); + ++framerCfg->jesd204M; + + retVal = adrv9025_JtxLinkJtxKCfgBfGet(device, + baseAddr, + (uint8_t*)&framerCfg->jesd204K); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: jesd204K"); + ADI_ERROR_RETURN(device->common.error.newAction); + ++framerCfg->jesd204K; + + retVal = adrv9025_JtxLinkJtxFCfgBfGet(device, + baseAddr, + &framerCfg->jesd204F); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: jesd204F"); + ADI_ERROR_RETURN(device->common.error.newAction); + ++framerCfg->jesd204F; + + retVal = adrv9025_JtxLinkJtxNpCfgBfGet(device, + baseAddr, + &framerCfg->jesd204Np); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: jesd204Np"); + ADI_ERROR_RETURN(device->common.error.newAction); + ++framerCfg->jesd204Np; + + framerCfg->jesd204E = 0; + if (framerCfg->enableJesd204C) + { + retVal = adrv9025_JtxLinkJtxECfgBfGet(device, + baseAddr, + &framerCfg->jesd204E); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: jesd204E"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + retVal = adrv9025_JtxLinkJtxScrCfgBfGet(device, + baseAddr, + &framerCfg->scramble); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: scramble"); + ADI_ERROR_RETURN(device->common.error.newAction); + + framerCfg->serializerLanesEnabled = 0; + for (channelId = 0; channelId < ADI_ADRV9025_MAX_SERDES_LANES; ++channelId) + { + retVal = adrv9025_JtxLinkJtxLaneSelBfGet(device, + baseAddr, + channelId, + &dataByte); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: serializerLanesEnabled"); + ADI_ERROR_RETURN(device->common.error.newAction); + if (dataByte < 0x1F) + { + framerCfg->serializerLanesEnabled |= (0x1 << channelId); + } + } + + retVal = adrv9025_JtxLinkJtxTplPhaseAdjustBfGet(device, + baseAddr, + &framerCfg->lmfcOffset); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: lmfcOffset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_JtxLinkJtxSysrefForRelinkBfGet(device, + baseAddr, + &framerCfg->newSysrefOnRelink); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: newSysrefOnRelink"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_JtxLinkJtxSyncNSelBfGet(device, + baseAddr, + &framerCfg->syncbInSelect); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: syncbInSelect"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* currently not used */ + framerCfg->overSample = 0; + + framerCfg->syncbInLvdsMode = 0; + framerCfg->syncbInLvdsPnInvert = 0; + if (framerCfg->syncbInSelect == 0) + { + retVal = adrv9025_CoreRxSync1PadLvdsModeBfGet(device, + ADRV9025_BF_CORE, + &framerCfg->syncbInLvdsMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: syncbInLvdsMode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_CoreRxSync1PadLvdsPnInvBfGet(device, + ADRV9025_BF_CORE, + &framerCfg->syncbInLvdsPnInvert); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: syncbInLvdsPnInvert"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (framerCfg->syncbInSelect == 1) + { + retVal = adrv9025_CoreRxSync2PadLvdsModeBfGet(device, + ADRV9025_BF_CORE, + &framerCfg->syncbInLvdsMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: syncbInLvdsMode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_CoreRxSync2PadLvdsPnInvBfGet(device, + ADRV9025_BF_CORE, + &framerCfg->syncbInLvdsPnInvert); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: syncbInLvdsPnInvert"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (framerCfg->syncbInSelect == 2) + { + retVal = adrv9025_CoreRxSync3PadLvdsModeBfGet(device, + ADRV9025_BF_CORE, + &framerCfg->syncbInLvdsMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: syncbInLvdsMode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_CoreRxSync3PadLvdsPnInvBfGet(device, + ADRV9025_BF_CORE, + &framerCfg->syncbInLvdsPnInvert); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: syncbInLvdsPnInvert"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error syncbInSelect is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + pLaneFramerOutSel = &framerCfg->serializerLaneCrossbar.lane0FramerOutSel; + for (channelId = 0; channelId < ADI_ADRV9025_MAX_SERDES_LANES; ++channelId) + { + /* get physical lane selection */ + if ((framerCfg->serializerLanesEnabled & (1 << channelId)) > 0) + { + retVal = adrv9025_JtxLinkJtxLaneSelBfGet(device, + baseAddr, + channelId, + pLaneFramerOutSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: serializerLaneCrossbar"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + *pLaneFramerOutSel = 0x04; + } + + pLaneFramerOutSel++; + } + + retVal = adi_adrv9025_AdcSampleXbarGet(device, + framerSel, + &framerCfg->adcCrossbar); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: adcCrossbar"); + ADI_ERROR_RETURN(device->common.error.newAction); + /* Check jesd204M for number of ADCs, mark the unused ones as ADI_ADRV9025_ADC_DISABLE */ + for (converter = framerCfg->jesd204M; converter < 24; converter++) + { + *(&framerCfg->adcCrossbar.conv0 + converter) = ADI_ADRV9025_ADC_DISABLE; + } + + retVal = adrv9025_JtxLinkJtxSysrefForStartupBfGet(device, + baseAddr, + &framerCfg->sysrefForStartup); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: sysrefForStartup"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_JtxLinkJtxTplSysrefNShotEnableBfGet(device, + baseAddr, + &framerCfg->sysrefNShotEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: sysrefNShotEnable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_JtxLinkJtxTplSysrefNShotCountBfGet(device, + baseAddr, + &framerCfg->sysrefNShotCount); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: sysrefNShotCount"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_JtxLinkJtxTplSysrefIgnoreWhenLinkedBfGet(device, + baseAddr, + &framerCfg->sysrefIgnoreWhenLinked); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Error failed to read framer config: sysrefIgnoreWhenLinked"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_DeframerCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSel, + adi_adrv9025_DfrmCfg_t* deframerCfg) +{ + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfJrxLinkChanAddr_e baseAddr = ADRV9025_BF_JRX_LINK0; + uint8_t tempDataByte = 0; + uint8_t channelId = 0; + uint8_t arrayLaneSel[ADI_ADRV9025_MAX_SERDES_LANES] = {0}; + uint8_t deframerIdx = 0; + uint8_t enabledLinks = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_NULL_PTR_RETURN(&device->common, + deframerCfg); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if (deframerSel == ADI_ADRV9025_DEFRAMER_0) + { + baseAddr = ADRV9025_BF_JRX_LINK0; + deframerIdx = 0; + } + + else if (deframerSel == ADI_ADRV9025_DEFRAMER_1) + { + baseAddr = ADRV9025_BF_JRX_LINK1; + deframerIdx = 1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSel, + "Error Invalid Deframer deframerSel Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* get Enabled Links */ + retVal = adrv9025_JesdCommonJrxLinkEnBfGet(device, + ADRV9025_BF_JESD_COMMON, + &enabledLinks); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for enabledLinks"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((enabledLinks & (uint8_t)deframerSel) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSel, + "Selected deframer is not enabled"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* get jesd204C Enabled */ + retVal = adrv9025_JrxLinkJrxLinkTypeBfGet(device, + baseAddr, + &deframerCfg->enableJesd204C); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for enableJesd204C"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* get bankID*/ + /* Bank ID for Jrx is not available, assign it to zero */ + deframerCfg->bankId = 0; + + /* get deviceID */ + retVal = adrv9025_JrxLinkJrxDidCfgBfGet(device, + baseAddr, + &deframerCfg->deviceId); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for deviceId"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* get lane0Id*/ + // TODO: Deframer has 4 lanes each has its own lane ID. + retVal = adrv9025_JrxLinkJrxLidCfgBfGet(device, + baseAddr, + 0, + &deframerCfg->lane0Id); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for lane0Id"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* get M */ + retVal = adrv9025_JrxLinkJrxMCfgBfGet(device, + baseAddr, + &tempDataByte); + deframerCfg->jesd204M = tempDataByte + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for jesd204M"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* get K */ + retVal = adrv9025_JrxLinkJrxKCfgBfGet(device, + baseAddr, + &tempDataByte); + deframerCfg->jesd204K = ((uint16_t)tempDataByte) + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for jesd204K"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* get Np */ + retVal = adrv9025_JrxLinkJrxNpCfgBfGet(device, + baseAddr, + &tempDataByte); + deframerCfg->jesd204Np = tempDataByte + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for jesd204Np"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* get F */ + retVal = adrv9025_JrxLinkJrxFCfgBfGet(device, + baseAddr, + &tempDataByte); + deframerCfg->jesd204F = tempDataByte + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for jesd204F"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* get E */ + /* This parameter is only valid for Jesd204C */ + if (deframerCfg->enableJesd204C == 1) + { + retVal = adrv9025_JrxLinkJrxDl204cMbReqdCfgBfGet(device, + baseAddr, + &deframerCfg->jesd204E); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for jesd204E"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + deframerCfg->jesd204E = 0; + } + + /* get scramble */ + retVal = adrv9025_JrxLinkJrxDscrCfgBfGet(device, + baseAddr, + &deframerCfg->scramble); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for scramble"); + ADI_ERROR_RETURN(device->common.error.newAction); + + deframerCfg->deserializerLanesEnabled = 0; + + for (channelId = 0; channelId < ADI_ADRV9025_MAX_SERDES_LANES; channelId++) + { + /* get physical lane selection */ + if ((device->devStateInfo.jesdCfg.deframerCfg[deframerIdx].deserializerLanesEnabled & (1 << channelId)) > 0) + { + retVal = adrv9025_JrxLinkJrxLinkLaneSelBfGet(device, + baseAddr, + channelId, + &arrayLaneSel[channelId]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for deserializerLaneCrossbar"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + arrayLaneSel[channelId] = 0x04; + } + } + /* apply conversion to bitmask to convert from pad lane numbers to ball lane numbers*/ + deframerCfg->deserializerLanesEnabled = device->devStateInfo.jesdCfg.deframerCfg[deframerIdx].deserializerLanesEnabled; + + /* apply conversion to lane selections to convert from pad lane numbers to ball lane numbers*/ + deframerCfg->deserializerLaneCrossbar.deframerInput0LaneSel = arrayLaneSel[0]; + deframerCfg->deserializerLaneCrossbar.deframerInput1LaneSel = arrayLaneSel[1]; + deframerCfg->deserializerLaneCrossbar.deframerInput2LaneSel = arrayLaneSel[2]; + deframerCfg->deserializerLaneCrossbar.deframerInput3LaneSel = arrayLaneSel[3]; + + /* get lmfc offset */ + retVal = adrv9025_JrxLinkJrxTplPhaseAdjustBfGet(device, + baseAddr, + &deframerCfg->lmfcOffset); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for lmfcOffset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* get sync out select */ + retVal = adrv9025_JrxLinkJrxSyncNSelBfGet(device, + baseAddr, + &tempDataByte); + deframerCfg->syncbOutSelect = tempDataByte - 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for syncbOutSelect"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* get syncbOutCmosDriveLevel for both Txsync1 and Txsync2 */ + adrv9025_CoreTxSyncDrvSelectBfGet(device, + ADRV9025_BF_CORE, + &deframerCfg->syncbOutCmosDriveLevel); + + if ((deframerCfg->syncbOutSelect == 0) || (deframerCfg->syncbOutSelect == 2)) + { + /* get syncbOut Lvds mode */ + retVal = adrv9025_CoreTxSync1PadLvdsModeBfGet(device, + ADRV9025_BF_CORE, + &deframerCfg->syncbOutLvdsMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for syncbOutLvdsMode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* get lvds pin invert */ + retVal = adrv9025_CoreTxSync1PadLvdsPnInvBfGet(device, + ADRV9025_BF_CORE, + &deframerCfg->syncbOutLvdsPnInvert); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for syncbOutLvdsPnInvert"); + ADI_ERROR_RETURN(device->common.error.newAction); + + deframerCfg->syncbOutCmosDriveLevel = deframerCfg->syncbOutCmosDriveLevel & ((uint8_t)0x01); + } + else if (deframerCfg->syncbOutSelect == 1) + { + /* get syncbOut Lvds mode */ + retVal = adrv9025_CoreTxSync2PadLvdsModeBfGet(device, + ADRV9025_BF_CORE, + &deframerCfg->syncbOutLvdsMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for syncbOutLvdsMode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* get lvds pin invert */ + retVal = adrv9025_CoreTxSync2PadLvdsPnInvBfGet(device, + ADRV9025_BF_CORE, + &deframerCfg->syncbOutLvdsPnInvert); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for syncbOutLvdsPnInvert"); + ADI_ERROR_RETURN(device->common.error.newAction); + + deframerCfg->syncbOutCmosDriveLevel = (deframerCfg->syncbOutCmosDriveLevel & ((uint8_t)0x02)) >> 1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_ADRV9025_ACT_ERR_RESET_SPI, + NULL, + "Invalid 'syncbOutSelect', should be 0-2"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* TODO: slew rate is not used, remove this once adi_adrv9025_DfrmCfg_t is updated */ + deframerCfg->syncbOutCmosSlewRate = 0; + + /* get Deframer output to DAC mapping */ + retVal = adi_adrv9025_DacSampleXbarGet(device, + deframerSel, + &deframerCfg->dacCrossbar); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for dacCrossbar"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* get sysref on relink enable */ + retVal = adrv9025_JrxLinkJrxSysrefForRelinkBfGet(device, + baseAddr, + &deframerCfg->newSysrefOnRelink); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for newSysrefOnRelink"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* get sysrefForStartup */ + retVal = adrv9025_JrxLinkJrxSysrefForStartupBfGet(device, + baseAddr, + &deframerCfg->sysrefForStartup); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for sysrefForStartup"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* get sysrefNhot Enable*/ + retVal = adrv9025_JrxLinkJrxTplSysrefNShotEnableBfGet(device, + baseAddr, + &deframerCfg->sysrefNShotEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for sysrefNShotEnable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* get sysrefNshotCount */ + retVal = adrv9025_JrxLinkJrxTplSysrefNShotCountBfGet(device, + baseAddr, + &deframerCfg->sysrefNShotCount); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for sysrefNShotCount"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* get sysrefIgnoreWhenLinked*/ + retVal = adrv9025_JrxLinkJrxTplSysrefIgnoreWhenLinkedBfGet(device, + baseAddr, + &deframerCfg->sysrefIgnoreWhenLinked); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Invalid Get for sysrefIgnoreWhenLinked"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_FramerLinkStateSet(adi_adrv9025_Device_t* device, + uint8_t framerSelMask, + uint8_t enable) +{ + uint8_t enableBits = (enable > 0) ? 7 : 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if ((framerSelMask <= 0) || (framerSelMask >= 8)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Error invalid JESD Framer Select Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((enable != 1) && (enable != 0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + enable, + "Error invalid JESD Framer Enable Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Note that we are not using a bitfield, since the destination fields are not channelized. */ + ADRV9025_SPIFIELDWRITE(device, + ADRV9025_ADDR_JTX_COMMON_0, + enableBits, + framerSelMask, + 0, + "ADRV9025_ADDR_JTX_COMMON_0"); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_FramerLinkStateGet(adi_adrv9025_Device_t* device, + uint8_t* enable) +{ + uint8_t mask = 0x7; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + enable); + + /* Note that we are not using a bitfield, since the destination fields are not channelized. */ + ADRV9025_SPIFIELDREAD(device, + ADRV9025_ADDR_JTX_COMMON_0, + enable, + mask, + 0, + "ADRV9025_ADDR_JTX_COMMON_0"); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_DfrmLinkStateSet(adi_adrv9025_Device_t* device, + uint8_t deframerSelMask, + uint8_t enable) +{ + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + uint8_t enableBits = (enable > 0) ? 3 : 0; + uint8_t desLaneMask = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if ((deframerSelMask < ADI_ADRV9025_DEFRAMER_0) || (deframerSelMask > ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelMask, + "Error invalid JESD Deframer Select Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((enable != 1) && (enable != 0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + enable, + "Error invalid JESD Framer Enable Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Power up/down the appropriate lanes */ + if ((deframerSelMask & (uint8_t)ADI_ADRV9025_DEFRAMER_0) == (uint8_t)ADI_ADRV9025_DEFRAMER_0) + { + desLaneMask |= device->devStateInfo.jesdCfg.deframerCfg[0].deserializerLanesEnabled; + } + + if ((deframerSelMask & (uint8_t)ADI_ADRV9025_DEFRAMER_1) == (uint8_t)ADI_ADRV9025_DEFRAMER_1) + { + desLaneMask |= device->devStateInfo.jesdCfg.deframerCfg[1].deserializerLanesEnabled; + } + + adrv9025_DeserializerLaneEnable(device, + desLaneMask, + enable); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adi_common_hal_Wait_ms(&device->common, + 50); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Note that we are not using a bitfield, since the destination fields are not channelized. */ + ADRV9025_SPIFIELDWRITE(device, + ADRV9025_ADDR_JRX_COMMON_0, + enableBits, + deframerSelMask, + 0, + "ADRV9025_ADDR_JRX_COMMON_0"); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_DfrmLinkStateGet(adi_adrv9025_Device_t* device, + uint8_t* enable) +{ + uint8_t mask = 0x3; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + enable); + + /* Note that we are not using a bitfield, since the destination fields are not channelized. */ + ADRV9025_SPIFIELDREAD(device, + ADRV9025_ADDR_JRX_COMMON_0, + enable, + mask, + 0, + "ADRV9025_ADDR_JRX_COMMON_0"); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_FramerSysrefCtrlSet(adi_adrv9025_Device_t* device, + uint8_t framerSelMask, + uint8_t enable) +{ + uint8_t maskSysref = (enable > 0) ? 0 : 1; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if ((framerSelMask <= 0) || (framerSelMask >= 8)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Error invalid Framer Sysref framerSel Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((enable != 1) && (enable != 0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + enable, + "Error invalid Framer Sysref Enable Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((framerSelMask & (uint8_t)ADI_ADRV9025_FRAMER_0) == (uint8_t)ADI_ADRV9025_FRAMER_0) + { + adrv9025_JtxLinkJtxTplSysrefMaskBfSet(device, + ADRV9025_BF_JTX_LINK0, + maskSysref); + + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((framerSelMask & (uint8_t)ADI_ADRV9025_FRAMER_1) == (uint8_t)ADI_ADRV9025_FRAMER_1) + { + adrv9025_JtxLinkJtxTplSysrefMaskBfSet(device, + ADRV9025_BF_JTX_LINK1, + maskSysref); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((framerSelMask & (uint8_t)ADI_ADRV9025_FRAMER_2) == (uint8_t)ADI_ADRV9025_FRAMER_2) + { + adrv9025_JtxLinkJtxTplSysrefMaskBfSet(device, + ADRV9025_BF_JTX_LINK2, + maskSysref); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_FramerSysrefCtrlGet(adi_adrv9025_Device_t* device, + adi_adrv9025_FramerSel_e framerSel, + uint8_t* enable) +{ + uint8_t maskSysref = 0; + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + enable); + + if (framerSel == ADI_ADRV9025_FRAMER_0) + { + adrv9025_JtxLinkJtxTplSysrefMaskBfGet(device, + ADRV9025_BF_JTX_LINK0, + &maskSysref); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (framerSel == ADI_ADRV9025_FRAMER_1) + { + adrv9025_JtxLinkJtxTplSysrefMaskBfGet(device, + ADRV9025_BF_JTX_LINK1, + &maskSysref); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (framerSel == ADI_ADRV9025_FRAMER_2) + { + adrv9025_JtxLinkJtxTplSysrefMaskBfGet(device, + ADRV9025_BF_JTX_LINK2, + &maskSysref); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Error invalid Framer Sysref framerSel Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *enable = ((~maskSysref) & 0x01); + return device->common.error.newAction; +} + +int32_t adi_adrv9025_DeframerSysrefCtrlSet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSel, + uint8_t enable) +{ + uint8_t maskSysref = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if ((deframerSel <= 0) || (deframerSel > ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSel, + "Error invalid Deframer Sysref deframerSel Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((enable != 1) && (enable != 0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + enable, + "Error invalid Deframer Sysref Enable Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + maskSysref = ((~enable) & 0x01); + if ((deframerSel == ADI_ADRV9025_DEFRAMER_0) || + (deframerSel == ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + adrv9025_JrxLinkJrxTplSysrefMaskBfSet(device, + ADRV9025_BF_JRX_LINK0, + maskSysref); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((deframerSel == ADI_ADRV9025_DEFRAMER_1) || + (deframerSel == ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + adrv9025_JrxLinkJrxTplSysrefMaskBfSet(device, + ADRV9025_BF_JRX_LINK1, + maskSysref); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_DeframerSysrefCtrlGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSel, + uint8_t* enable) +{ + uint8_t maskSysref = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + enable); + + if (deframerSel == ADI_ADRV9025_DEFRAMER_0) + + { + adrv9025_JrxLinkJrxTplSysrefMaskBfGet(device, + ADRV9025_BF_JRX_LINK0, + &maskSysref); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (deframerSel == ADI_ADRV9025_DEFRAMER_1) + { + adrv9025_JrxLinkJrxTplSysrefMaskBfGet(device, + ADRV9025_BF_JRX_LINK1, + &maskSysref); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *enable = ((~maskSysref) & 0x01); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_FramerStatusGet(adi_adrv9025_Device_t *device, + adi_adrv9025_FramerSel_e framerSel, + adi_adrv9025_FramerStatus_t* framerStatus) +{ + uint8_t sysrefReceived = 0; + uint8_t sysrefPhaseErr = 0; + uint8_t syncbLevel = 0; + adrv9025_BfJtxLinkChanAddr_e baseAddr = ADRV9025_BF_JTX_LINK0; + adrv9025_BfJtxLinkChanAddr_e baseAddrLs = ADRV9025_BF_JTX_LINK0; + adrv9025_BfJtxLinkChanAddr_e baseAddrSyncbInSelect = ADRV9025_BF_JTX_LINK0; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adi_adrv9025_FrmCfg_t framerCfg = { 0 }; + adi_adrv9025_FrmCfg_t *framerCfgPtr = &framerCfg; + uint8_t frameridx = 0; + uint8_t frameridxLs = 0; + static const uint8_t syncNSelValueZeroCheck = 0; + static const uint8_t syncNSelValueOneCheck = 1; + static const uint8_t syncNSelValueTwoCheck = 2; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, framerStatus); + + if (framerSel == ADI_ADRV9025_FRAMER_0) + { + baseAddr = ADRV9025_BF_JTX_LINK0; + frameridx = 0; + } + else if (framerSel == ADI_ADRV9025_FRAMER_1) + { + baseAddr = ADRV9025_BF_JTX_LINK1; + frameridx = 1; + } + else if (framerSel == ADI_ADRV9025_FRAMER_2) + { + baseAddr = ADRV9025_BF_JTX_LINK2; + frameridx = 2; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Error invalid Framer Status framerSel Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* In Link Sharing profiles framer 0 is used to transmit data from both Rx and ORx. */ + /* When querying the JESD link status, the SYSREF phase error bit should be read from framer 1 for link sharing profiles.*/ + if ((device->devStateInfo.linkSharingEnabled > 0) && (framerSel == ADI_ADRV9025_FRAMER_0)) + { + baseAddrLs = ADRV9025_BF_JTX_LINK1; + frameridxLs = 1; + } + else + { + baseAddrLs = baseAddr; + frameridxLs = frameridx; + } + + // Read state for JESD204C + if(device->devStateInfo.jesdCfg.framerCfg[frameridxLs].enableJesd204C == 1) + { + adrv9025_JtxLinkJtxDl204cSysrefRcvdGet(device, baseAddr, &framerStatus->status); + ADI_ERROR_RETURN(device->common.error.newAction); + } + // Read state for JESD204B + else + { + /* Calling adrv9025_JtxLinkJtxSyncNSelBfGet to return the current value for syncbInSelect */ + /* syncbInSelect is needed for the API to target the correct register when syncbInSelect is not set to default value of zero */ + recoveryAction = adrv9025_JtxLinkJtxSyncNSelBfGet(device, baseAddr, &framerCfgPtr->syncbInSelect); + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Error failed to read framer config: syncbInSelect"); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JtxLinkJtxTplCfgInvalidBfGet(device, baseAddr, &framerStatus->status); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JtxLinkJtxTplSysrefRcvdBfGet(device, baseAddr, &sysrefReceived); + ADI_ERROR_RETURN(device->common.error.newAction); + + framerStatus->status |= ((sysrefReceived << 1) & 0x2); + + adrv9025_JtxLinkJtxTplSysrefPhaseErrBfGet(device, baseAddrLs, &sysrefPhaseErr); + ADI_ERROR_RETURN(device->common.error.newAction); + + framerStatus->status |= ((sysrefPhaseErr << 2) & 0x4); + + /* Read the syncbInSelect and then select the correct register to read */ + if (framerCfg.syncbInSelect == syncNSelValueZeroCheck) + { + /* If syncNSel is equal to zero, register 0x6E68 should be read */ + /* Base address 0x6E00, i.e ADRV9025_BF_JTX_LINK0 needs to be passed */ + baseAddrSyncbInSelect = ADRV9025_BF_JTX_LINK0; + } + else if (framerCfg.syncbInSelect == syncNSelValueOneCheck) + { + /* If syncNSel is equal to one, then the API needs to read from register 0x7068 */ + /* Base aaddress 0x7000 i.e ADRV9025_BF_JTX_LINK1 needs to be passed */ + baseAddrSyncbInSelect = ADRV9025_BF_JTX_LINK1; + } + else if (framerCfg.syncbInSelect == syncNSelValueTwoCheck) + { + /* If syncNSel is equal to two, then the API needs to read from register 0x7268 */ + /* Base aaddress 0x7200 i.e ADRV9025_BF_JTX_LINK2 needs to be passed */ + baseAddrSyncbInSelect = ADRV9025_BF_JTX_LINK2; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerCfg.syncbInSelect, + "Error invalid syncbInSelect Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + adrv9025_JtxLinkJtxDl204bSyncNBfGet(device, baseAddrSyncbInSelect, &syncbLevel); + ADI_ERROR_RETURN(device->common.error.newAction); + + framerStatus->status |= ((syncbLevel << 3) & 0x8); + + adrv9025_JtxLinkJtxSyncNSelBfGet(device, baseAddr, &framerStatus->syncNSel); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JtxLinkJtxDl204bSyncNeCountBfGet(device, baseAddr, &framerStatus->framerSyncNeCount); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JtxLinkJtxDl204bStateBfGet(device, baseAddr, &framerStatus->qbfStateStatus); + ADI_ERROR_RETURN(device->common.error.newAction); + } + return device->common.error.newAction; +} +int32_t adi_adrv9025_DeframerStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSel, + adi_adrv9025_DeframerStatus_t* deframerStatus) +{ + uint8_t dfrmSysrefReceived = 0; + uint8_t dfrm204bUserDataState = 0; + uint8_t dfrmFsLost = 0; + uint8_t dfrmEomfEvent = 0; + uint8_t dfrmEofEvent = 0; + uint8_t dfrmValidChecksum = 0; + uint8_t channelId = 0; + uint8_t deframerIdx = 0; + uint8_t laneSel = 0; + uint8_t laneIdx = 0; + adrv9025_BfJrxLinkChanAddr_e baseAddr = ADRV9025_BF_JRX_LINK0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, deframerStatus); + + if (deframerSel == ADI_ADRV9025_DEFRAMER_0) + { + baseAddr = ADRV9025_BF_JRX_LINK0; + deframerIdx = 0; + } + else if (deframerSel == ADI_ADRV9025_DEFRAMER_1) + { + baseAddr = ADRV9025_BF_JRX_LINK1; + deframerIdx = 1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + JESDdata->deframerSel, + "Error invalid Deframer Status deframerSel Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (channelId = 0; channelId < ADI_ADRV9025_NUM_LANES; channelId++) + { + laneSel = 1 << channelId; + if ((device->devStateInfo.jesdCfg.deframerCfg[deframerIdx].deserializerLanesEnabled & laneSel) == laneSel) + { + // First lane in use. + laneIdx = channelId; + break; + } + } + + // Read state for JESD204C + if (device->devStateInfo.jesdCfg.deframerCfg[deframerIdx].enableJesd204C == 1) + { + adrv9025_JrxLinkJrxDl204cStateGet(device, baseAddr, laneIdx, &deframerStatus->status); + ADI_ERROR_RETURN(device->common.error.newAction); + } + // Read state for JESD204B + else + { + adrv9025_JrxLinkJrxDl204bSyncNBfGet(device, + baseAddr, + laneIdx, + &deframerStatus->status); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JrxLinkJrxTplSysrefRcvdBfGet(device, + baseAddr, + &dfrmSysrefReceived); + ADI_ERROR_RETURN(device->common.error.newAction); + deframerStatus->status |= ((dfrmSysrefReceived << 1) & 0x2); + + adrv9025_JrxLinkJrxDl204bUserDataBfGet(device, + baseAddr, + laneIdx, + &dfrm204bUserDataState); + ADI_ERROR_RETURN(device->common.error.newAction); + deframerStatus->status |= ((dfrm204bUserDataState << 2) & 0x4); + + adrv9025_JrxLinkJrxDl204bFsLostBfGet(device, + baseAddr, + laneIdx, + &dfrmFsLost); + ADI_ERROR_RETURN(device->common.error.newAction); + deframerStatus->status |= ((dfrmFsLost << 4) & 0x10); + + adrv9025_JrxLinkJrxDl204bEomfEventBfGet(device, + baseAddr, + laneIdx, + &dfrmEomfEvent); + ADI_ERROR_RETURN(device->common.error.newAction); + deframerStatus->status |= ((dfrmEomfEvent << 5) & 0x20); + + adrv9025_JrxLinkJrxDl204bEofEventBfGet(device, + baseAddr, + laneIdx, + &dfrmEofEvent); + ADI_ERROR_RETURN(device->common.error.newAction); + deframerStatus->status |= ((dfrmEofEvent << 6) & 0x40); + + adrv9025_JrxLinkJrxDl204bValidCksumBfGet(device, + baseAddr, + laneIdx, + &dfrmValidChecksum); + ADI_ERROR_RETURN(device->common.error.newAction); + deframerStatus->status |= ((dfrmValidChecksum << 7) & 0x80); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_DacSampleXbarSet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSel, + adi_adrv9025_DacSampleXbarCfg_t* dacXbar) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t mValue = 0; + uint8_t channelIndex = 0; + uint8_t disabledCount = 0; + adrv9025_BfJrxLinkChanAddr_e baseAddr = ADRV9025_BF_JRX_LINK0; + static const uint8_t MAXNUMCONVERTERS = 8; + uint8_t arrayXBarCfg[] = {0, 0, 0, 0, 0, 0, 0, 0}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + dacXbar); + + if (deframerSel == ADI_ADRV9025_DEFRAMER_0) + { + baseAddr = ADRV9025_BF_JRX_LINK0; + } + else if (deframerSel == ADI_ADRV9025_DEFRAMER_1) + { + baseAddr = ADRV9025_BF_JRX_LINK1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSel, + "Invalid Deframer Selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* read back the configured M value for the deframer to write */ + adrv9025_JrxLinkJrxMCfgBfGet(device, + baseAddr, + &mValue); + ADI_ERROR_RETURN(recoveryAction); + + /* load the config array */ + arrayXBarCfg[0] = (uint8_t)dacXbar->tx1DacChanI; + arrayXBarCfg[1] = (uint8_t)dacXbar->tx1DacChanQ; + arrayXBarCfg[2] = (uint8_t)dacXbar->tx2DacChanI; + arrayXBarCfg[3] = (uint8_t)dacXbar->tx2DacChanQ; + arrayXBarCfg[4] = (uint8_t)dacXbar->tx3DacChanI; + arrayXBarCfg[5] = (uint8_t)dacXbar->tx3DacChanQ; + arrayXBarCfg[6] = (uint8_t)dacXbar->tx4DacChanI; + arrayXBarCfg[7] = (uint8_t)dacXbar->tx4DacChanQ; + + /* Count number of disabled selections, this should be equal to 'MAXNUMCONVERTERS -(mValue + 1)' */ + for (channelIndex = 0; channelIndex < MAXNUMCONVERTERS; channelIndex++) + { + if (arrayXBarCfg[channelIndex] == (uint8_t)ADI_ADRV9025_DEFRAMER_OUT_DISABLE) + { + disabledCount++; + } + else if ((arrayXBarCfg[channelIndex] != (uint8_t)ADI_ADRV9025_DEFRAMER_OUT0) && (arrayXBarCfg[channelIndex] != (uint8_t)ADI_ADRV9025_DEFRAMER_OUT1) + && (arrayXBarCfg[channelIndex] != (uint8_t)ADI_ADRV9025_DEFRAMER_OUT2) && (arrayXBarCfg[channelIndex] != (uint8_t)ADI_ADRV9025_DEFRAMER_OUT3) + && (arrayXBarCfg[channelIndex] != (uint8_t)ADI_ADRV9025_DEFRAMER_OUT4) && (arrayXBarCfg[channelIndex] != (uint8_t)ADI_ADRV9025_DEFRAMER_OUT5) + && (arrayXBarCfg[channelIndex] != (uint8_t)ADI_ADRV9025_DEFRAMER_OUT6) && (arrayXBarCfg[channelIndex] != (uint8_t)ADI_ADRV9025_DEFRAMER_OUT7)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + arrayXBarCfg, + "Invalid DAC Output selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if (disabledCount != (MAXNUMCONVERTERS - (mValue + 1))) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + disabledCount, + "Number of valid converter selections doesn't match with deframer m value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (channelIndex = 0; channelIndex < MAXNUMCONVERTERS; channelIndex++) + { + recoveryAction = adrv9025_JrxLinkJrxConvSelBfSet(device, + baseAddr, + channelIndex, + arrayXBarCfg[channelIndex]); + ADI_ERROR_RETURN(recoveryAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_DacSampleXbarGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSel, + adi_adrv9025_DacSampleXbarCfg_t* dacXbar) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t channelIndex = 0; + adrv9025_BfJrxLinkChanAddr_e baseAddr = ADRV9025_BF_JRX_LINK0; + static const uint8_t MAXNUMCONVERTERS = 8; + uint8_t arrayXBarCfg[] = {0, 0, 0, 0, 0, 0, 0, 0}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + dacXbar); + + if (deframerSel == ADI_ADRV9025_DEFRAMER_0) + { + baseAddr = ADRV9025_BF_JRX_LINK0; + } + else if (deframerSel == ADI_ADRV9025_DEFRAMER_1) + { + baseAddr = ADRV9025_BF_JRX_LINK1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSel, + "Invalid Deframer Selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (channelIndex = 0; channelIndex < MAXNUMCONVERTERS; channelIndex++) + { + recoveryAction = adrv9025_JrxLinkJrxConvSelBfGet(device, + baseAddr, + channelIndex, + &arrayXBarCfg[channelIndex]); + ADI_ERROR_RETURN(recoveryAction); + } + + /* load the dacXbar struct */ + dacXbar->tx1DacChanI = (adi_adrv9025_DacSampleXbarSel_e)arrayXBarCfg[0]; + dacXbar->tx1DacChanQ = (adi_adrv9025_DacSampleXbarSel_e)arrayXBarCfg[1]; + dacXbar->tx2DacChanI = (adi_adrv9025_DacSampleXbarSel_e)arrayXBarCfg[2]; + dacXbar->tx2DacChanQ = (adi_adrv9025_DacSampleXbarSel_e)arrayXBarCfg[3]; + dacXbar->tx3DacChanI = (adi_adrv9025_DacSampleXbarSel_e)arrayXBarCfg[4]; + dacXbar->tx3DacChanQ = (adi_adrv9025_DacSampleXbarSel_e)arrayXBarCfg[5]; + dacXbar->tx4DacChanI = (adi_adrv9025_DacSampleXbarSel_e)arrayXBarCfg[6]; + dacXbar->tx4DacChanQ = (adi_adrv9025_DacSampleXbarSel_e)arrayXBarCfg[7]; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_AdcSampleXbarSet(adi_adrv9025_Device_t* device, + adi_adrv9025_FramerSel_e framerSel, + adi_adrv9025_AdcSampleXbarCfg_t* adcXbar) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfJtxLinkChanAddr_e baseAddress = ADRV9025_BF_JTX_LINK0; + static const uint8_t MAXNUMCONVERTERS = 24; + static const uint8_t CONVERTERDISABLE = 0x7F; + static const uint8_t OFFSET = 1; + uint8_t channelIndex = 0; + uint8_t mValue = 0; + uint8_t adcXbardata[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + adcXbar); + + switch (framerSel) + { + case ADI_ADRV9025_FRAMER_0: + baseAddress = ADRV9025_BF_JTX_LINK0; + break; + case ADI_ADRV9025_FRAMER_1: + baseAddress = ADRV9025_BF_JTX_LINK1; + break; + case ADI_ADRV9025_FRAMER_2: + baseAddress = ADRV9025_BF_JTX_LINK2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Invalid Framer Selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + /* read back the configured M value and set the offset */ + recoveryAction = adrv9025_JtxLinkJtxMCfgBfGet(device, + baseAddress, + &mValue); + ADI_ERROR_RETURN(recoveryAction); + mValue += OFFSET; + + /* load the adc config array */ + adcXbardata[0] = (uint8_t)adcXbar->conv0; + adcXbardata[1] = (uint8_t)adcXbar->conv1; + adcXbardata[2] = (uint8_t)adcXbar->conv2; + adcXbardata[3] = (uint8_t)adcXbar->conv3; + adcXbardata[4] = (uint8_t)adcXbar->conv4; + adcXbardata[5] = (uint8_t)adcXbar->conv5; + adcXbardata[6] = (uint8_t)adcXbar->conv6; + adcXbardata[7] = (uint8_t)adcXbar->conv7; + adcXbardata[8] = (uint8_t)adcXbar->conv8; + adcXbardata[9] = (uint8_t)adcXbar->conv9; + adcXbardata[10] = (uint8_t)adcXbar->conv10; + adcXbardata[11] = (uint8_t)adcXbar->conv11; + adcXbardata[12] = (uint8_t)adcXbar->conv12; + adcXbardata[13] = (uint8_t)adcXbar->conv13; + adcXbardata[14] = (uint8_t)adcXbar->conv14; + adcXbardata[15] = (uint8_t)adcXbar->conv15; + adcXbardata[16] = (uint8_t)adcXbar->conv16; + adcXbardata[17] = (uint8_t)adcXbar->conv17; + adcXbardata[18] = (uint8_t)adcXbar->conv18; + adcXbardata[19] = (uint8_t)adcXbar->conv19; + adcXbardata[20] = (uint8_t)adcXbar->conv20; + adcXbardata[21] = (uint8_t)adcXbar->conv21; + adcXbardata[22] = (uint8_t)adcXbar->conv22; + adcXbardata[23] = (uint8_t)adcXbar->conv23; + + /* program the converters */ + for (channelIndex = 0; channelIndex < MAXNUMCONVERTERS; channelIndex++) + { + /* program converter if channel is not greater than M-1 */ + if (channelIndex < mValue) + { + /* range check the converter settings */ + if ((adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DISABLE) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_RX1_I) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_RX1_Q) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_RX2_I) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_RX2_Q) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_RX3_I) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_RX3_Q) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_RX4_I) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_RX4_Q) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DUALBAND_RX1_BAND_A_I) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DUALBAND_RX1_BAND_A_Q) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DUALBAND_RX2_BAND_A_I) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DUALBAND_RX2_BAND_A_Q) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DUALBAND_RX3_BAND_A_I) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DUALBAND_RX3_BAND_A_Q) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DUALBAND_RX4_BAND_A_I) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DUALBAND_RX4_BAND_A_Q) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DUALBAND_RX1_BAND_B_I) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DUALBAND_RX1_BAND_B_Q) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DUALBAND_RX2_BAND_B_I) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DUALBAND_RX2_BAND_B_Q) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DUALBAND_RX3_BAND_B_I) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DUALBAND_RX3_BAND_B_Q) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DUALBAND_RX4_BAND_B_I) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_DUALBAND_RX4_BAND_B_Q) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_ORX1_I) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_ORX1_Q) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_ORX2_I) && + (adcXbardata[channelIndex] != ADI_ADRV9025_ADC_ORX2_Q)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + adcXbardata[channelIndex], + "Invalid ADC Converter Selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + adrv9025_JtxLinkJtxConvSelBfSet(device, + baseAddress, + channelIndex, + adcXbardata[channelIndex]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* disable converter if channel greater than M */ + else + { + adrv9025_JtxLinkJtxConvSelBfSet(device, + baseAddress, + channelIndex, + CONVERTERDISABLE); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_AdcSampleXbarGet(adi_adrv9025_Device_t* device, + adi_adrv9025_FramerSel_e framerSel, + adi_adrv9025_AdcSampleXbarCfg_t* adcXbar) +{ + adrv9025_BfJtxLinkChanAddr_e baseAddress = ADRV9025_BF_JTX_LINK0; + uint8_t bfValue = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + adcXbar); + + switch (framerSel) + { + case ADI_ADRV9025_FRAMER_0: + baseAddress = ADRV9025_BF_JTX_LINK0; + break; + case ADI_ADRV9025_FRAMER_1: + baseAddress = ADRV9025_BF_JTX_LINK1; + break; + case ADI_ADRV9025_FRAMER_2: + baseAddress = ADRV9025_BF_JTX_LINK2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Invalid Framer Selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 0, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv0 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 1, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv1 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 2, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv2 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 3, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv3 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 4, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv4 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 5, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv5 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 6, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv6 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 7, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv7 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 8, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv8 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 9, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv9 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 10, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv10 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 11, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv11 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 12, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv12 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 13, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv13 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 14, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv14 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 15, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv15 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 16, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv16 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 17, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv17 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 18, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv18 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 19, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv19 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 20, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv20 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 21, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv21 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 22, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv22 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + adrv9025_JtxLinkJtxConvSelBfGet(device, + baseAddress, + 23, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + adcXbar->conv23 = (adi_adrv9025_AdcSampleXbarSel_e)bfValue; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_FramerTestDataSet(adi_adrv9025_Device_t* device, + adi_adrv9025_FrmTestDataCfg_t* frmTestDataCfg) +{ + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + frmTestDataCfg); + + if (((frmTestDataCfg->testDataSource < ADI_ADRV9025_FTD_ADC_DATA) || (frmTestDataCfg->testDataSource > ADI_ADRV9025_FTD_RAMP)) && + (frmTestDataCfg->testDataSource != ADI_ADRV9025_FTD_PATTERN_REPEAT) && + (frmTestDataCfg->testDataSource != ADI_ADRV9025_FTD_PATTERN_ONCE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + frmTestDataCfg->testDataSource, + "Invalid DataSource Selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (frmTestDataCfg->framerSelMask >= 8) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Invalid Framer Selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((frmTestDataCfg->injectPoint > ADI_ADRV9025_FTD_POST_LANEMAP) || (frmTestDataCfg->injectPoint < ADI_ADRV9025_FTD_FRAMERINPUT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + frmTestDataCfg->injectPoint, + "Invalid DataInject Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((frmTestDataCfg->framerSelMask & 0x01) == 0x01) + { + adrv9025_JtxLinkJtxTestGenModeBfSet(device, + ADRV9025_BF_JTX_LINK0, + frmTestDataCfg->testDataSource); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_JtxLinkJtxTestGenSelBfSet(device, + ADRV9025_BF_JTX_LINK0, + frmTestDataCfg->injectPoint); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((frmTestDataCfg->framerSelMask & 0x02) == 0x02) + { + adrv9025_JtxLinkJtxTestGenModeBfSet(device, + ADRV9025_BF_JTX_LINK1, + frmTestDataCfg->testDataSource); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_JtxLinkJtxTestGenSelBfSet(device, + ADRV9025_BF_JTX_LINK1, + frmTestDataCfg->injectPoint); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((frmTestDataCfg->framerSelMask & 0x04) == 0x4) + { + adrv9025_JtxLinkJtxTestGenModeBfSet(device, + ADRV9025_BF_JTX_LINK2, + frmTestDataCfg->testDataSource); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_JtxLinkJtxTestGenSelBfSet(device, + ADRV9025_BF_JTX_LINK2, + frmTestDataCfg->injectPoint); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_FramerTestDataGet(adi_adrv9025_Device_t* device, + adi_adrv9025_FramerSel_e framerSelect, + adi_adrv9025_FrmTestDataCfg_t* frmTestDataCfg) +{ + adrv9025_BfJtxLinkChanAddr_e baseAddr = ADRV9025_BF_JTX_LINK0; + uint8_t injectionPoint = 0; + uint8_t dataSource = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + frmTestDataCfg); + + if (framerSelect == ADI_ADRV9025_FRAMER_0) + { + baseAddr = ADRV9025_BF_JTX_LINK0; + } + else if (framerSelect == ADI_ADRV9025_FRAMER_1) + { + baseAddr = ADRV9025_BF_JTX_LINK1; + } + else if (framerSelect == ADI_ADRV9025_FRAMER_2) + { + baseAddr = ADRV9025_BF_JTX_LINK2; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSelect, + "Error invalid Framer Status framerSel Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + adrv9025_JtxLinkJtxTestGenSelBfGet(device, + baseAddr, + &injectionPoint); + ADI_ERROR_RETURN(device->common.error.newAction); + frmTestDataCfg->injectPoint = (adi_adrv9025_FramerDataInjectPoint_e)injectionPoint; + + adrv9025_JtxLinkJtxTestGenModeBfGet(device, + baseAddr, + &dataSource); + ADI_ERROR_RETURN(device->common.error.newAction); + frmTestDataCfg->testDataSource = (adi_adrv9025_FramerDataSource_e)dataSource; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_FramerTestDataInjectError(adi_adrv9025_Device_t* device, + adi_adrv9025_FramerSel_e framerSelect, + uint8_t laneMask) +{ + adrv9025_BfJtxLinkChanAddr_e baseAddr = ADRV9025_BF_JTX_LINK0; + uint8_t ballLane = 0; + uint8_t invert = 0; + uint8_t pnInvertBit = 0; + uint8_t dieLaneId = 0; + uint8_t framerOutForLane = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if (framerSelect == ADI_ADRV9025_FRAMER_0) + { + baseAddr = ADRV9025_BF_JTX_LINK0; + } + else if (framerSelect == ADI_ADRV9025_FRAMER_1) + { + baseAddr = ADRV9025_BF_JTX_LINK1; + } + else if (framerSelect == ADI_ADRV9025_FRAMER_2) + { + baseAddr = ADRV9025_BF_JTX_LINK2; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSel, + "Error invalid framerSel Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (ballLane = 0; ballLane <= 7; ballLane++) + { + invert = ((laneMask >> ballLane) & 0x01); + + if (invert == 1) + { + dieLaneId = adrv9025_SerializerLamLaneOffsetGet(ballLane); + + /* PN Invert occurs at framer output before lane crossbar */ + adrv9025_JtxLinkJtxLaneSelBfGet(device, + baseAddr, + dieLaneId, + &framerOutForLane); + + if (framerOutForLane <= 7) + { + /* Read current PN invert setting and set it back at end*/ + adrv9025_JtxLinkJtxLaneInvBfGet(device, + baseAddr, + framerOutForLane, + &pnInvertBit); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JtxLinkJtxLaneInvBfSet(device, + baseAddr, + framerOutForLane, + ((~pnInvertBit) & 0x01)); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JtxLinkJtxLaneInvBfSet(device, + baseAddr, + framerOutForLane, + pnInvertBit); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Lane disabled - do not invert */ + } + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_DfrmPrbsCheckerStateSet(adi_adrv9025_Device_t* device, + adi_adrv9025_DfrmPrbsCfg_t* dfrmPrbsCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t prbsCheckLocation = 0; + uint8_t pbrsPolyOrder = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + dfrmPrbsCfg); + + if (((dfrmPrbsCfg->polyOrder == ADI_ADRV9025_PRBS_DISABLE) || + (dfrmPrbsCfg->polyOrder == ADI_ADRV9025_PRBS7) || + (dfrmPrbsCfg->polyOrder == ADI_ADRV9025_PRBS9) || + (dfrmPrbsCfg->polyOrder == ADI_ADRV9025_PRBS15) || + (dfrmPrbsCfg->polyOrder == ADI_ADRV9025_PRBS31) || + (dfrmPrbsCfg->polyOrder == ADI_ADRV9025_USERDATA)) && + ((dfrmPrbsCfg->checkerLocation == ADI_ADRV9025_PRBSCHECK_LANEDATA) || + (dfrmPrbsCfg->checkerLocation == ADI_ADRV9025_PRBSCHECK_SAMPLEDATA))) + { + prbsCheckLocation = (uint8_t)dfrmPrbsCfg->checkerLocation; + pbrsPolyOrder = dfrmPrbsCfg->polyOrder; + + recoveryAction = adi_adrv9025_DfrmPrbsCountReset(device); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to reset Deframer PRBS count"); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JesdCommonJrxTestSourceBfSet(device, + ADRV9025_BF_JESD_COMMON, + prbsCheckLocation); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JesdCommonJrxTestModeBfSet(device, + ADRV9025_BF_JESD_COMMON, + pbrsPolyOrder); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + dfrmPrbsCfg->polyOrder, + "Invalid polyOrder/checkerLocation value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_DfrmPrbsCheckerStateGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DfrmPrbsCfg_t* dfrmPrbsCfg) +{ + uint32_t recoveryAction = (int32_t)ADI_COMMON_HAL_OK; + uint8_t prbsCheckLocation = 0; + uint8_t pbrsPolyOrder = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + recoveryAction = adrv9025_JesdCommonJrxTestModeBfGet(device, + ADRV9025_BF_JESD_COMMON, + &pbrsPolyOrder); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to get Deframer PRBS mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JesdCommonJrxTestSourceBfGet(device, + ADRV9025_BF_JESD_COMMON, + &prbsCheckLocation); + ADI_ERROR_RETURN(device->common.error.newAction); + + dfrmPrbsCfg->checkerLocation = (adi_adrv9025_DeframerPrbsCheckLoc_e)prbsCheckLocation; + dfrmPrbsCfg->polyOrder = (adi_adrv9025_DeframerPrbsOrder_e)pbrsPolyOrder; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_DfrmPrbsCountReset(adi_adrv9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Write the bit value to a 1 and then to a zero in order to clear the register, its not self clearing */ + recoveryAction = adrv9025_JesdCommonJrxTestLaneClearErrorsBfSet(device, + ADRV9025_BF_JESD_COMMON, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to clear deframer lane PRBS errors"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JesdCommonJrxTestLaneClearErrorsBfSet(device, + ADRV9025_BF_JESD_COMMON, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to clear deframer lane PRBS errors"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write the bit value to a 1 and then to a zero in order to clear the register, its not self clearing */ + recoveryAction = adrv9025_JesdCommonJrxTestSampleClearErrorsBfSet(device, + ADRV9025_BF_JESD_COMMON, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to clear deframer sample PRBS errors"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JesdCommonJrxTestSampleClearErrorsBfSet(device, + ADRV9025_BF_JESD_COMMON, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to clear deframer sample PRBS errors"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_DfrmPrbsErrCountGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DfrmPrbsErrCounters_t* counters) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t prbsInvalidDataFlag = 0; + uint8_t prbsErrorFlag = 0; + uint8_t prbsLaneInv = 0; + uint8_t lane = 0; + uint8_t sampleSource = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + counters); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + recoveryAction = adrv9025_JesdCommonJrxTestSourceBfGet(device, + ADRV9025_BF_JESD_COMMON, + &sampleSource); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to read deframer PRBS errors"); + ADI_ERROR_RETURN(device->common.error.newAction); + counters->sampleSource = (adi_adrv9025_DeframerPrbsCheckLoc_e)sampleSource; + + if (counters->sampleSource == ADI_ADRV9025_PRBSCHECK_SAMPLEDATA) + { + /* Trigger update of the sample error counters */ + adrv9025_JesdCommonJrxTestSampleUpdateErrorCountBfSet(device, + ADRV9025_BF_JESD_COMMON, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Now read the sample counter value. We use the zeroth index only in sample mode. */ + adrv9025_JesdCommonJrxTestSampleErrorCountBfGet(device, + ADRV9025_BF_JESD_COMMON, + (uint8_t *)&counters->laneErrors[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JesdCommonJrxTestSampleErrorFlagBfGet(device, + ADRV9025_BF_JESD_COMMON, + &prbsErrorFlag); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JesdCommonJrxTestSampleClearErrorsBfGet(device, + ADRV9025_BF_JESD_COMMON, + &prbsInvalidDataFlag); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Create the errorStatus. Note that there is no inverted value flag specific to sample mode */ + counters->errorStatus[0] = (prbsInvalidDataFlag << 1) & (prbsErrorFlag << 2); + } + else if (counters->sampleSource == ADI_ADRV9025_PRBSCHECK_LANEDATA) + { + /* Trigger update of lane error counters */ + recoveryAction = adrv9025_JesdCommonJrxTestLaneUpdateErrorCountBfSet(device, + ADRV9025_BF_JESD_COMMON, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + for (lane = 0; lane < ADI_ADRV9025_NUM_LANES; lane++) + { + prbsInvalidDataFlag = 0; + prbsErrorFlag = 0; + prbsLaneInv = 0; + + adrv9025_JesdCommonJrxTestLaneErrorCountBfGet(device, + ADRV9025_BF_JESD_COMMON, + lane, + &counters->laneErrors[lane]); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JesdCommonJrxTestLaneInvBfGet(device, + ADRV9025_BF_JESD_COMMON, + lane, + &prbsLaneInv); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JesdCommonJrxTestLaneInvalidDataFlagBfGet(device, + ADRV9025_BF_JESD_COMMON, + lane, + &prbsInvalidDataFlag); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JesdCommonJrxTestLaneErrorFlagBfGet(device, + ADRV9025_BF_JESD_COMMON, + lane, + &prbsErrorFlag); + ADI_ERROR_RETURN(device->common.error.newAction); + + counters->errorStatus[lane] = prbsLaneInv | (prbsInvalidDataFlag << 1) | (prbsErrorFlag << 2); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_DfrmIlasMismatchGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect, + adi_adrv9025_DfrmCompareData_t* dfrmData) +{ + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfJrxLinkChanAddr_e baseAddrRx = ADRV9025_BF_JRX_LINK0; + uint8_t readData = 0; + uint32_t mismatchMask = 0x0001; + uint8_t channelId = 0; + uint8_t deframerIdx = 0; + uint8_t laneSel = 0; + uint8_t laneIdx = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + dfrmData); + + dfrmData->zeroCheckFlag = 0; + dfrmData->ilasMismatchDfrm = 0; + + /* Range Check deframerSelect */ + if (deframerSelect == ADI_ADRV9025_DEFRAMER_0) + { + baseAddrRx = ADRV9025_BF_JRX_LINK0; + deframerIdx = 0; + } + else if (deframerSelect == ADI_ADRV9025_DEFRAMER_1) + { + baseAddrRx = ADRV9025_BF_JRX_LINK1; + deframerIdx = 1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + JESDdata->deframerSel, + "Error invalid JESD Deframer Select Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (channelId = 0; channelId < ADI_ADRV9025_NUM_LANES; channelId++) + { + laneSel = 1 << channelId; + if ((device->devStateInfo.jesdCfg.deframerCfg[deframerIdx].deserializerLanesEnabled & laneSel) == laneSel) + { + // First lane in use. + laneIdx = channelId; + break; + } + } + + mismatchMask = 0x00000001; + + /* ILAS DID */ + retVal = adrv9025_JrxLinkJrxDl204bL0Rxcfg0BfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read ILAS DID"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmIlasData.dfrmDID = readData; + dfrmData->zeroCheckFlag = dfrmData->zeroCheckFlag | (uint32_t)readData; + + /* CFG DID */ + retVal = adrv9025_JrxLinkJrxDidCfgBfGet(device, + baseAddrRx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read CFG DID"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmCfgData.dfrmDID = readData; + + /* compare DID */ + if (dfrmData->dfrmIlasData.dfrmDID != dfrmData->dfrmCfgData.dfrmDID) + { + dfrmData->ilasMismatchDfrm = dfrmData->ilasMismatchDfrm | mismatchMask; + } + mismatchMask = mismatchMask << 1; + + /* ILAS BID */ + retVal = adrv9025_JrxLinkJrxDl204bL0Rxcfg1BfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read ILAS BID"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmIlasData.dfrmBID = (readData & 0x0F); + dfrmData->zeroCheckFlag = dfrmData->zeroCheckFlag | (uint32_t)readData; + + /* CFG BID */ + /* BID is not supported in TOK deframer assign it to value read */ + dfrmData->dfrmCfgData.dfrmBID = dfrmData->dfrmIlasData.dfrmBID; + + /* compare BID */ + if (dfrmData->dfrmIlasData.dfrmBID != dfrmData->dfrmCfgData.dfrmBID) + { + dfrmData->ilasMismatchDfrm = dfrmData->ilasMismatchDfrm | mismatchMask; + } + mismatchMask = mismatchMask << 1; + + /* ILAS LID0 */ + retVal = adrv9025_JrxLinkJrxDl204bL0Rxcfg2BfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read ILAS LID0"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmIlasData.dfrmLID0 = (readData & 0x1F); + dfrmData->zeroCheckFlag = dfrmData->zeroCheckFlag | (uint32_t)readData; + + /* CFG LID0 */ + retVal = adrv9025_JrxLinkJrxLidCfgBfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read CFG LID0"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmCfgData.dfrmLID0 = readData; + + /* compare LID0 */ + if (dfrmData->dfrmIlasData.dfrmLID0 != dfrmData->dfrmCfgData.dfrmLID0) + { + dfrmData->ilasMismatchDfrm = dfrmData->ilasMismatchDfrm | mismatchMask; + } + mismatchMask = mismatchMask << 1; + + /* ILAS L */ + retVal = adrv9025_JrxLinkJrxDl204bL0Rxcfg3BfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read ILAS L"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmIlasData.dfrmL = (readData & 0x1F); + dfrmData->zeroCheckFlag = dfrmData->zeroCheckFlag | (uint32_t)readData; + + /* CFG L */ + retVal = adrv9025_JrxLinkJrxLCfgBfGet(device, + baseAddrRx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read CFG L"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmCfgData.dfrmL = readData; + + /* compare L */ + if (dfrmData->dfrmIlasData.dfrmL != dfrmData->dfrmCfgData.dfrmL) + { + dfrmData->ilasMismatchDfrm = dfrmData->ilasMismatchDfrm | mismatchMask; + } + mismatchMask = mismatchMask << 1; + + /* ILAS SCR */ + retVal = adrv9025_JrxLinkJrxDl204bL0Rxcfg3BfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read ILAS SCR"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmIlasData.dfrmSCR = ((readData & 0x80) >> 7); + dfrmData->zeroCheckFlag = dfrmData->zeroCheckFlag | (uint32_t)readData; + + /* CFG SCR */ + retVal = adrv9025_JrxLinkJrxDscrCfgBfGet(device, + baseAddrRx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read CFG SCR"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmCfgData.dfrmSCR = readData; + + /* compare SCR */ + if (dfrmData->dfrmIlasData.dfrmSCR != dfrmData->dfrmCfgData.dfrmSCR) + { + dfrmData->ilasMismatchDfrm = dfrmData->ilasMismatchDfrm | mismatchMask; + } + mismatchMask = mismatchMask << 1; + + /* ILAS F */ + retVal = adrv9025_JrxLinkJrxDl204bL0Rxcfg4BfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read ILAS F"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmIlasData.dfrmF = readData; + dfrmData->zeroCheckFlag = dfrmData->zeroCheckFlag | (uint32_t)readData; + + /* CFG F */ + retVal = adrv9025_JrxLinkJrxFCfgBfGet(device, + baseAddrRx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read CFG F"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmCfgData.dfrmF = readData; + + /* compare F */ + if (dfrmData->dfrmIlasData.dfrmF != dfrmData->dfrmCfgData.dfrmF) + { + dfrmData->ilasMismatchDfrm = dfrmData->ilasMismatchDfrm | mismatchMask; + } + mismatchMask = mismatchMask << 1; + + /* ILAS K */ + retVal = adrv9025_JrxLinkJrxDl204bL0Rxcfg5BfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read ILAS K"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmIlasData.dfrmK = (readData & 0x1F); + dfrmData->zeroCheckFlag = dfrmData->zeroCheckFlag | (uint32_t)readData; + + /* CFG K */ + retVal = adrv9025_JrxLinkJrxKCfgBfGet(device, + baseAddrRx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read CFG K"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmCfgData.dfrmK = readData; + + /* compare K */ + if (dfrmData->dfrmIlasData.dfrmK != dfrmData->dfrmCfgData.dfrmK) + { + dfrmData->ilasMismatchDfrm = dfrmData->ilasMismatchDfrm | mismatchMask; + } + mismatchMask = mismatchMask << 1; + + /* ILAS M */ + retVal = adrv9025_JrxLinkJrxDl204bL0Rxcfg6BfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read ILAS M"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmIlasData.dfrmM = readData; + dfrmData->zeroCheckFlag = dfrmData->zeroCheckFlag | (uint32_t)readData; + + /* CFG M */ + retVal = adrv9025_JrxLinkJrxMCfgBfGet(device, + baseAddrRx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read CFG M"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmCfgData.dfrmM = readData; + + /* compare M*/ + if (dfrmData->dfrmIlasData.dfrmM != dfrmData->dfrmCfgData.dfrmM) + { + dfrmData->ilasMismatchDfrm = dfrmData->ilasMismatchDfrm | mismatchMask; + } + mismatchMask = mismatchMask << 1; + + /* ILAS N */ + retVal = adrv9025_JrxLinkJrxDl204bL0Rxcfg7BfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read ILAS N"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmIlasData.dfrmN = (readData & 0x1F); + dfrmData->zeroCheckFlag = dfrmData->zeroCheckFlag | (uint32_t)readData; + + /* CFG N */ + retVal = adrv9025_JrxLinkJrxNCfgBfGet(device, + baseAddrRx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read CFG N"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmCfgData.dfrmN = readData; + + /* compare N */ + if (dfrmData->dfrmIlasData.dfrmN != dfrmData->dfrmCfgData.dfrmN) + { + dfrmData->ilasMismatchDfrm = dfrmData->ilasMismatchDfrm | mismatchMask; + } + mismatchMask = mismatchMask << 1; + + /* ILAS CS */ + retVal = adrv9025_JrxLinkJrxDl204bL0Rxcfg7BfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read ILAS CS"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmIlasData.dfrmCS = ((readData & 0xC0) >> 6); + dfrmData->zeroCheckFlag = dfrmData->zeroCheckFlag | (uint32_t)readData; + + /* CFG CS */ + retVal = adrv9025_JrxLinkJrxCsCfgBfGet(device, + baseAddrRx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read CFG S"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmCfgData.dfrmCS = readData; + + /* compare CS*/ + if (dfrmData->dfrmIlasData.dfrmCS != dfrmData->dfrmCfgData.dfrmCS) + { + dfrmData->ilasMismatchDfrm = dfrmData->ilasMismatchDfrm | mismatchMask; + } + mismatchMask = mismatchMask << 1; + + /* ILAS NP */ + retVal = adrv9025_JrxLinkJrxDl204bL0Rxcfg8BfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read ILAS NP"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmIlasData.dfrmNP = (readData & 0x1F); + dfrmData->zeroCheckFlag = dfrmData->zeroCheckFlag | (uint32_t)readData; + + /* CFG NP */ + retVal = adrv9025_JrxLinkJrxNpCfgBfGet(device, + baseAddrRx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read CFG NP"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmCfgData.dfrmNP = readData; + + /* compare NP */ + if (dfrmData->dfrmIlasData.dfrmNP != dfrmData->dfrmCfgData.dfrmNP) + { + dfrmData->ilasMismatchDfrm = dfrmData->ilasMismatchDfrm | mismatchMask; + } + mismatchMask = mismatchMask << 1; + + /* ILAS S */ + retVal = adrv9025_JrxLinkJrxDl204bL0Rxcfg9BfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read ILAS S"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmIlasData.dfrmS = (readData & 0x1F); + dfrmData->zeroCheckFlag = dfrmData->zeroCheckFlag | (uint32_t)readData; + + /* CFG S */ + retVal = adrv9025_JrxLinkJrxSCfgBfGet(device, + baseAddrRx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read CFG S"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmCfgData.dfrmS = readData; + + /* compare S */ + if (dfrmData->dfrmIlasData.dfrmS != dfrmData->dfrmCfgData.dfrmS) + { + dfrmData->ilasMismatchDfrm = dfrmData->ilasMismatchDfrm | mismatchMask; + } + mismatchMask = mismatchMask << 1; + + /* ILAS CF */ + retVal = adrv9025_JrxLinkJrxDl204bL0Rxcfg10BfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read ILAS CF"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmIlasData.dfrmCF = (readData & 0x1F); + dfrmData->zeroCheckFlag = dfrmData->zeroCheckFlag | (uint32_t)readData; + + /* CFG CF */ + /* CF is not supported in TOK deframer assign it to value read */ + dfrmData->dfrmCfgData.dfrmCF = dfrmData->dfrmIlasData.dfrmCF; + + /* compare CF */ + if (dfrmData->dfrmIlasData.dfrmCF != dfrmData->dfrmCfgData.dfrmCF) + { + dfrmData->ilasMismatchDfrm = dfrmData->ilasMismatchDfrm | mismatchMask; + } + mismatchMask = mismatchMask << 1; + + /* ILAS HD */ + retVal = adrv9025_JrxLinkJrxDl204bL0Rxcfg10BfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read ILAS HD"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmIlasData.dfrmHD = ((readData & 0x80) >> 7); + dfrmData->zeroCheckFlag = dfrmData->zeroCheckFlag | (uint32_t)readData; + + /* CFG HD */ + retVal = adrv9025_JrxLinkJrxHdCfgBfGet(device, + baseAddrRx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read CFG HD"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmCfgData.dfrmHD = readData; + + /* compare HD */ + if (dfrmData->dfrmIlasData.dfrmHD != dfrmData->dfrmCfgData.dfrmHD) + { + dfrmData->ilasMismatchDfrm = dfrmData->ilasMismatchDfrm | mismatchMask; + } + mismatchMask = mismatchMask << 1; + + /* ILAS FCHK0 */ + retVal = adrv9025_JrxLinkJrxDl204bL0Rxcfg13BfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read ILAS FCHK0"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmIlasData.dfrmFCHK0 = readData; + + /* CFG FCHK0 */ + retVal = adrv9025_JrxLinkJrxChksumCfgBfGet(device, + baseAddrRx, + laneIdx, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read CFG FCHK0"); + ADI_ERROR_RETURN(device->common.error.newAction); + dfrmData->dfrmCfgData.dfrmFCHK0 = readData; + + /* compare FCHK0 */ + if (dfrmData->dfrmIlasData.dfrmFCHK0 != dfrmData->dfrmCfgData.dfrmFCHK0) + { + dfrmData->ilasMismatchDfrm = dfrmData->ilasMismatchDfrm | mismatchMask; + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DfrmIrqMaskGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect, + adi_adrv9025_DeframerIrq_Mask_Vector_t* irqMask) +{ + adrv9025_BfJrxLinkChanAddr_e baseAddr = ADRV9025_BF_JRX_LINK0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + irqMask); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Range Check deframerSelect */ + if ((deframerSelect != ADI_ADRV9025_DEFRAMER_0) && (deframerSelect != ADI_ADRV9025_DEFRAMER_1) && (deframerSelect != ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelect, + "Error invalid JESD Deframer Select Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + else + { + /* read back the Dfrm IRQ Vector */ + if ((deframerSelect == ADI_ADRV9025_DEFRAMER_0) || (deframerSelect == ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + baseAddr = ADRV9025_BF_JRX_LINK0; + adrv9025_JrxLinkJrxDl204bIrqClrBfGet(device, + baseAddr, + &irqMask->deframer0); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (deframerSelect != ADI_ADRV9025_DEFRAMER_0) + { + baseAddr = ADRV9025_BF_JRX_LINK1; + adrv9025_JrxLinkJrxDl204bIrqClrBfGet(device, + baseAddr, + &irqMask->deframer1); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DfrmIrqMaskSet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect, + adi_adrv9025_DeframerIrq_Mask_Vector_t irqMask) +{ + adrv9025_BfJrxLinkChanAddr_e baseAddr = ADRV9025_BF_JRX_LINK0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Range Check deframerSelect */ + if ((deframerSelect != ADI_ADRV9025_DEFRAMER_0) && (deframerSelect != ADI_ADRV9025_DEFRAMER_1) && (deframerSelect != ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelect, + "Error invalid JESD Deframer Select Value"); + return (device->common.error.newAction); + } + + else + { + /* read back the Dfrm IRQ Vector */ + if ((deframerSelect == ADI_ADRV9025_DEFRAMER_0) || (deframerSelect == ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + baseAddr = ADRV9025_BF_JRX_LINK0; + adrv9025_JrxLinkJrxDl204bIrqClrBfSet(device, + baseAddr, + irqMask.deframer0); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JrxLinkJrxDl204hIrqClrBfSet(device, + baseAddr, + irqMask.deframer0); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((deframerSelect == ADI_ADRV9025_DEFRAMER_1) || (deframerSelect == ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + baseAddr = ADRV9025_BF_JRX_LINK1; + adrv9025_JrxLinkJrxDl204bIrqClrBfSet(device, + baseAddr, + irqMask.deframer1); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JrxLinkJrxDl204hIrqClrBfSet(device, + baseAddr, + irqMask.deframer1); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DfrmIrqSourceReset(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect) +{ + adrv9025_BfJrxLinkChanAddr_e baseAddr = ADRV9025_BF_JRX_LINK0; + adi_adrv9025_DeframerIrq_Mask_Vector_t irqMask_Save = {0, 0}; + const static adi_adrv9025_DeframerIrq_Mask_Vector_t irqMask_Clr = {0xFFFF, 0xFFFF}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Range Check deframerSelect */ + if ((deframerSelect != ADI_ADRV9025_DEFRAMER_0) && (deframerSelect != ADI_ADRV9025_DEFRAMER_1) && (deframerSelect != ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelect, + "Error invalid JESD Deframer Select Value"); + return (device->common.error.newAction); + } + + else + { + /* read back the Dfrm IRQ Vector, clear interrupts, restore original mask */ + if ((deframerSelect == ADI_ADRV9025_DEFRAMER_0) || (deframerSelect == ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + baseAddr = ADRV9025_BF_JRX_LINK0; + + adrv9025_JrxLinkJrxDl204bIrqClrBfGet(device, + baseAddr, + &irqMask_Save.deframer0); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JrxLinkJrxDl204bIrqClrBfSet(device, + baseAddr, + irqMask_Clr.deframer0); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JrxLinkJrxDl204bIrqClrBfSet(device, + baseAddr, + irqMask_Save.deframer0); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JrxLinkJrxDl204hIrqClrBfGet(device, + baseAddr, + &irqMask_Save.deframer0); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JrxLinkJrxDl204hIrqClrBfSet(device, + baseAddr, + irqMask_Clr.deframer0); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JrxLinkJrxDl204hIrqClrBfSet(device, + baseAddr, + irqMask_Save.deframer0); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((deframerSelect == ADI_ADRV9025_DEFRAMER_1) || (deframerSelect == ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + baseAddr = ADRV9025_BF_JRX_LINK1; + adrv9025_JrxLinkJrxDl204bIrqClrBfGet(device, + baseAddr, + &irqMask_Save.deframer1); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JrxLinkJrxDl204bIrqClrBfSet(device, + baseAddr, + irqMask_Clr.deframer1); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JrxLinkJrxDl204bIrqClrBfSet(device, + baseAddr, + irqMask_Save.deframer1); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JrxLinkJrxDl204hIrqClrBfGet(device, + baseAddr, + &irqMask_Save.deframer1); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JrxLinkJrxDl204hIrqClrBfSet(device, + baseAddr, + irqMask_Clr.deframer1); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_JrxLinkJrxDl204hIrqClrBfSet(device, + baseAddr, + irqMask_Save.deframer1); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DfrmIrqSourceGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect, + adi_adrv9025_DeframerIrq_Mask_Vector_t* irqSourceValue) +{ + uint8_t channelId = 0; + adrv9025_BfJrxLinkChanAddr_e baseAddr = ADRV9025_BF_JRX_LINK0; + uint8_t laneSel = 0; + uint8_t deframer0Done = ADI_FALSE; + uint8_t deframer1Done = ADI_FALSE; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + ADI_NULL_PTR_RETURN(&device->common, + irqSourceValue); + + /* Range Check deframerSelect */ + if ((deframerSelect != ADI_ADRV9025_DEFRAMER_0) && + (deframerSelect != ADI_ADRV9025_DEFRAMER_1) && + (deframerSelect != ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelect, + "Error invalid JESD Deframer Select Value"); + return (device->common.error.newAction); + } + else + { + /* read back the Dfrm IRQ Vector */ + for (channelId = 0; channelId < ADI_ADRV9025_NUM_LANES; channelId++) + { + laneSel = 1 << channelId; + + if ((deframerSelect == ADI_ADRV9025_DEFRAMER_0) || (deframerSelect == ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + // Only get first lane in used. + if ((device->devStateInfo.jesdCfg.deframerCfg[0].deserializerLanesEnabled & laneSel) && (deframer0Done == ADI_FALSE)) + { + baseAddr = ADRV9025_BF_JRX_LINK0; + adrv9025_JrxLinkJrxDl204bIrqVecBfGet(device, + baseAddr, + channelId, + &irqSourceValue->deframer0); + ADI_ERROR_RETURN(device->common.error.newAction); + deframer0Done = ADI_TRUE; + } + } + + if ((deframerSelect != ADI_ADRV9025_DEFRAMER_0) || (deframerSelect == ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + // Only get first lane in used. + if ((device->devStateInfo.jesdCfg.deframerCfg[1].deserializerLanesEnabled & laneSel) && (deframer1Done == ADI_FALSE)) + { + baseAddr = ADRV9025_BF_JRX_LINK1; + adrv9025_JrxLinkJrxDl204bIrqVecBfGet(device, + baseAddr, + channelId, + &irqSourceValue->deframer1); + ADI_ERROR_RETURN(device->common.error.newAction); + deframer1Done = ADI_TRUE; + } + } + } + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_SerializerReset(adi_adrv9025_Device_t* device, + uint32_t pllClkSource) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t readData = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if (pllClkSource > 0) + { + recoveryAction = adrv9025_JesdCommonJtxOverrideSrstEnBfSet(device, + ADRV9025_BF_JESD_COMMON, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to set jtx_override_srst_en to 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JesdCommonJtxOverrideSrstEnBfGet(device, + ADRV9025_BF_JESD_COMMON, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to get jtx_override_srst_en"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (readData != 1) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to set jtx_override_srst_en to 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_JesdCommonJtxOverrideSrstEnBfSet(device, + ADRV9025_BF_JESD_COMMON, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to set jtx_override_srst_en to 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JesdCommonJtxOverrideSrstEnBfGet(device, + ADRV9025_BF_JESD_COMMON, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to get jtx_override_srst_en"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (readData != 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to set jtx_override_srst_en to 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else + { + recoveryAction = adrv9025_JesdCommonJtxTriggerSrstNBfSet(device, + ADRV9025_BF_JESD_COMMON, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to set jtx_trigger_srst_n to 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JesdCommonJtxTriggerSrstNBfGet(device, + ADRV9025_BF_JESD_COMMON, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to get jtx_trigger_srst_n"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (readData != 1) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to set jtx_trigger_srst_n to 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_JesdCommonJtxTriggerSrstNBfSet(device, + ADRV9025_BF_JESD_COMMON, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to set jtx_trigger_srst_n to 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JesdCommonJtxTriggerSrstNBfGet(device, + ADRV9025_BF_JESD_COMMON, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to get jtx_trigger_srst_n"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (readData != 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to set jtx_trigger_srst_n to 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DfrmErrCntrCntrlSet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect, + adi_adrv9025_DfrmErrCounterIrqSel_e interruptEnable, + uint8_t laneNumber, + uint8_t errCounterControl, + uint8_t errCounterHoldCfg) +{ + static const uint16_t IRQERRCOUNTERMASK = 0x00E0; + static const uint8_t ERRCOUNTERRSTMASK = 0X70; + static const uint8_t ERRCOUNTERCNTRLMASK = 0x07; + static const uint8_t ERRCOUNTERHOLDMASK = 0x07; + static const uint8_t ERRCOUNTERRSTSHIFT = 4; + + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfJrxLinkChanAddr_e baseAddrRx = ADRV9025_BF_JRX_LINK0; + adi_adrv9025_DeframerIrq_Mask_Vector_t irqMask = {0}; + uint8_t errorCounterReset = 0x00; + uint8_t errorCounterConfig = 0x00; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Read current irq mask for selected deframer for read/modify/write */ + retVal = adi_adrv9025_DfrmIrqMaskGet(device, + deframerSelect, + &irqMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read irq mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (deframerSelect == ADI_ADRV9025_DEFRAMER_0) + { + baseAddrRx = ADRV9025_BF_JRX_LINK0; + + if (interruptEnable == ADI_ADRV9025_DFRM_ERR_COUNT_ENABLE_IRQ) + { + irqMask.deframer0 = irqMask.deframer0 & (~IRQERRCOUNTERMASK); + } + else if (interruptEnable == ADI_ADRV9025_DFRM_ERR_COUNT_DISABLE_IRQ) + { + irqMask.deframer0 = irqMask.deframer0 | IRQERRCOUNTERMASK; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + interruptEnable, + "Error Invalid Interrupt selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else if (deframerSelect == ADI_ADRV9025_DEFRAMER_1) + { + baseAddrRx = ADRV9025_BF_JRX_LINK1; + + if (interruptEnable == ADI_ADRV9025_DFRM_ERR_COUNT_ENABLE_IRQ) + { + irqMask.deframer1 = irqMask.deframer1 & (~IRQERRCOUNTERMASK); + } + else if (interruptEnable == ADI_ADRV9025_DFRM_ERR_COUNT_DISABLE_IRQ) + { + irqMask.deframer1 = irqMask.deframer1 | IRQERRCOUNTERMASK; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + interruptEnable, + "Error Invalid Interrupt selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelect, + "Error Invalid Deframer deframerSelect Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (laneNumber > 7) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + laneNumber, + "Error invalid Lane number Select Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Write modified irq mask for selected deframer */ + retVal = adi_adrv9025_DfrmIrqMaskSet(device, + deframerSelect, + irqMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to write modified irq mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Extract 3 reset bits from input argument */ + errorCounterReset = (errCounterControl & ERRCOUNTERRSTMASK) >> ERRCOUNTERRSTSHIFT; + + /* Mask 3 config bits from input argument */ + errorCounterConfig = errCounterControl & ERRCOUNTERCNTRLMASK; + errCounterHoldCfg = errCounterHoldCfg & ERRCOUNTERHOLDMASK; + + /* Reset the requested error counters */ + retVal = adrv9025_JrxLinkJrxDl204bEcntRstBfSet(device, + baseAddrRx, + laneNumber, + errorCounterReset); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to reset error counter"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Clear reset bits */ + retVal = adrv9025_JrxLinkJrxDl204bEcntRstBfSet(device, + baseAddrRx, + laneNumber, + 0x00); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to clear reset flag for error counters"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set error counter threshold to 255 */ + retVal = adrv9025_JrxLinkJrxDl204bEthBfSet(device, + baseAddrRx, + 0xFF); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to clear set error threshold"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write counter enable bits */ + retVal = adrv9025_JrxLinkJrxDl204bEcntEnaBfSet(device, + baseAddrRx, + laneNumber, + errorCounterConfig); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to write error counter enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write the error counter hold configuration */ + retVal = adrv9025_JrxLinkJrxDl204bEcntTchBfSet(device, + baseAddrRx, + laneNumber, + errCounterHoldCfg); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to write error counter hold configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DfrmErrCntrCntrlGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint8_t laneNumber, + uint8_t* errCounterControl, + uint8_t* errCounterHoldCfg) +{ + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfJrxLinkChanAddr_e baseAddrRx = ADRV9025_BF_JRX_LINK0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + errCounterControl); + + ADI_NULL_PTR_RETURN(&device->common, + errCounterHoldCfg); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if (deframerSelect == ADI_ADRV9025_DEFRAMER_0) + { + baseAddrRx = ADRV9025_BF_JRX_LINK0; + } + else if (deframerSelect == ADI_ADRV9025_DEFRAMER_1) + { + baseAddrRx = ADRV9025_BF_JRX_LINK1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelect, + "Error Invalid Deframer deframerSelect Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (laneNumber > 7) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + laneNumber, + "Error invalid Lane number Select Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* read out the contents of the error counter control */ + retVal = adrv9025_JrxLinkJrxDl204bEcntEnaBfGet(device, + baseAddrRx, + laneNumber, + errCounterControl); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read error counter control"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* read out the contents of the error counter hold configuration */ + retVal = adrv9025_JrxLinkJrxDl204bEcntTchBfGet(device, + baseAddrRx, + laneNumber, + errCounterHoldCfg); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read error counter hold configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DfrmErrCounterStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint8_t laneNumber, + adi_adrv9025_DfrmErrCounterStatus_t* errCounterStatus) +{ + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfJrxLinkChanAddr_e baseAddrRx = ADRV9025_BF_JRX_LINK0; + uint8_t readData = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + errCounterStatus); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if (deframerSelect == ADI_ADRV9025_DEFRAMER_0) + { + baseAddrRx = ADRV9025_BF_JRX_LINK0; + } + else if (deframerSelect == ADI_ADRV9025_DEFRAMER_1) + { + baseAddrRx = ADRV9025_BF_JRX_LINK1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelect, + "Error invalid JESD Deframer Select Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (laneNumber > 7) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + laneNumber, + "Error invalid Lane number Select Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Reset lane status */ + errCounterStatus->laneStatus = 0; + + /* Read deframer status */ + retVal = adrv9025_JrxLinkJrxDl204bUekBfGet(device, + baseAddrRx, + laneNumber, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read deframer status - UEK Errors"); + ADI_ERROR_RETURN(device->common.error.newAction); + errCounterStatus->laneStatus |= readData; + errCounterStatus->laneStatus <<= 1; + + retVal = adrv9025_JrxLinkJrxDl204bNitBfGet(device, + baseAddrRx, + laneNumber, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read deframer status - NIT Errors"); + ADI_ERROR_RETURN(device->common.error.newAction); + errCounterStatus->laneStatus |= readData; + errCounterStatus->laneStatus <<= 1; + + retVal = adrv9025_JrxLinkJrxDl204bIlsBfGet(device, + baseAddrRx, + laneNumber, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read deframer status - ILAS Status"); + ADI_ERROR_RETURN(device->common.error.newAction); + errCounterStatus->laneStatus |= readData; + errCounterStatus->laneStatus <<= 1; + + retVal = adrv9025_JrxLinkJrxDl204bIldBfGet(device, + baseAddrRx, + laneNumber, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read deframer status - Inter-Lane De-skew Status"); + ADI_ERROR_RETURN(device->common.error.newAction); + errCounterStatus->laneStatus |= readData; + errCounterStatus->laneStatus <<= 1; + + retVal = adrv9025_JrxLinkJrxDl204bFsBfGet(device, + baseAddrRx, + laneNumber, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read deframer status - Frame Sync Status"); + ADI_ERROR_RETURN(device->common.error.newAction); + errCounterStatus->laneStatus |= readData; + errCounterStatus->laneStatus <<= 1; + + retVal = adrv9025_JrxLinkJrxDl204bCksBfGet(device, + baseAddrRx, + laneNumber, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read deframer status - Completed Checksum Status"); + ADI_ERROR_RETURN(device->common.error.newAction); + errCounterStatus->laneStatus |= readData; + errCounterStatus->laneStatus <<= 1; + + retVal = adrv9025_JrxLinkJrxDl204bCgsBfGet(device, + baseAddrRx, + laneNumber, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read deframer status - CGS Status"); + ADI_ERROR_RETURN(device->common.error.newAction); + errCounterStatus->laneStatus |= readData; + errCounterStatus->laneStatus <<= 1; + + retVal = adrv9025_JrxLinkJrxDl204bBdeBfGet(device, + baseAddrRx, + laneNumber, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read deframer status - BDE Status"); + ADI_ERROR_RETURN(device->common.error.newAction); + errCounterStatus->laneStatus |= readData; + + /* read deframer bad disparity counter value */ + retVal = adrv9025_JrxLinkJrxDl204bBdCntBfGet(device, + baseAddrRx, + laneNumber, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read deframer bad disparity counter value"); + ADI_ERROR_RETURN(device->common.error.newAction); + errCounterStatus->bdCntValue = readData; + + /* read deframer UEK counter value */ + retVal = adrv9025_JrxLinkJrxDl204bUekCntBfGet(device, + baseAddrRx, + laneNumber, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read deframer UEK counter value"); + ADI_ERROR_RETURN(device->common.error.newAction); + errCounterStatus->uekCntValue = readData; + + /* read deframer NITcounter value */ + retVal = adrv9025_JrxLinkJrxDl204bNitCntBfGet(device, + baseAddrRx, + laneNumber, + &readData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read deframer NIT counter value"); + ADI_ERROR_RETURN(device->common.error.newAction); + errCounterStatus->nitCntValue = readData; + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DfrmLinkConditionGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint8_t* dfrmLinkCondition) +{ + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfJrxLinkChanAddr_e baseAddrRx = ADRV9025_BF_JRX_LINK0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_NULL_PTR_RETURN(&device->common, + dfrmLinkCondition); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if (deframerSelect == ADI_ADRV9025_DEFRAMER_0) + { + baseAddrRx = ADRV9025_BF_JRX_LINK0; + } + else if (deframerSelect == ADI_ADRV9025_DEFRAMER_1) + { + baseAddrRx = ADRV9025_BF_JRX_LINK1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelect, + "Error invalid JESD Deframer Link Condition Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* read deframer link condition value */ + *dfrmLinkCondition = 0; + retVal = adrv9025_JrxLinkJrxTplUsrDataRdyBfGet(device, + baseAddrRx, + dfrmLinkCondition); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read deframer link condition"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DesEyeSweep(adi_adrv9025_Device_t* device, + uint8_t laneNumber, + adi_adrv9025_DesEyeSweepResults_t* spoSweepResults) +{ + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + static const uint8_t LF_GENERAL = 0x0E; + static const uint8_t CAL_DCD_0 = 0x14; + int16_t spo = 0; + uint8_t prbsErrorFlag = 0; + uint8_t laneConverted = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, spoSweepResults); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if ((laneNumber != 0x01) && (laneNumber != 0x02) && (laneNumber != 0x04) && (laneNumber != 0x08)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Only one lane is allowed at a time for SPO sweep"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Lane conversion from laminate swaps */ + laneConverted = laneNumber; //adrv9025_DeserializerLamLaneOffsetGet(laneNumber); + + spoSweepResults->goodSpoLeft = 0; + spoSweepResults->goodSpoRight = 0; + spoSweepResults->goodSpoTotal = 0; + + /* disable ck90 skew */ + retVal = adrv9025_CbusRegisterWrite(device, + LF_GENERAL, + laneConverted, + 0x03); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + "Failed to write LF_GENERAL"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* freeze content of slice adjust loop */ + retVal = adrv9025_CbusRegisterWrite(device, + CAL_DCD_0, + laneConverted, + 0x01); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + "Failed to write CAL_DCD_0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Remember, SPO uses two's complement & is 7 bits; step down SPO to -31 */ + for (spo = 127; spo > 96; spo--) + { + retVal = adrv9025_SpoSet(device, + laneConverted, + (uint8_t)(spo & 0x7F)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + "Failed to write SPO"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Sweep SPO -31 to -1 */ + for (spo = 97; spo < 128; spo++) + { + retVal = adrv9025_SpoSet(device, + laneConverted, + (uint8_t)(spo & 0x7F)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + "Failed to write SPO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adi_adrv9025_DfrmPrbsCountReset(device); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adi_common_hal_Wait_us(&device->common, + 500); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_JesdCommonJrxTestLaneErrorFlagBfGet(device, + ADRV9025_BF_JESD_COMMON, + laneConverted, + &prbsErrorFlag); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read deframer link condition"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (prbsErrorFlag == 0) + { + spoSweepResults->goodSpoLeft++; + } + } + + /* Sweep SPO 0 to 31 */ + for (spo = 0x0; spo < 32; spo++) + { + retVal = adrv9025_SpoSet(device, + laneConverted, + (uint8_t)(spo & 0x7F)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + "Failed to write SPO"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adi_adrv9025_DfrmPrbsCountReset(device); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adi_common_hal_Wait_us(&device->common, + 500); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adrv9025_JesdCommonJrxTestLaneErrorFlagBfGet(device, + ADRV9025_BF_JESD_COMMON, + laneConverted, + &prbsErrorFlag); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + retVal, + NULL, + "Failed to read deframer link condition"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (prbsErrorFlag == 0) + { + spoSweepResults->goodSpoRight++; + } + } + + /* Return SPO to zero offset */ + for (spo = 31; spo > -1; spo--) + { + retVal = adrv9025_SpoSet(device, + laneConverted, + (uint8_t)(spo & 0x7F)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + "Failed to write SPO"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* enable ck0/ck90 skew correction */ + retVal = adrv9025_CbusRegisterWrite(device, + LF_GENERAL, + laneConverted, + 0x01); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + "Failed to write LF_GENERAL"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* enable slice adjust loop */ + retVal = adrv9025_CbusRegisterWrite(device, + CAL_DCD_0, + laneConverted, + 0x00); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + retVal, + NULL, + "Failed to write CAL_DCD_0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + spoSweepResults->goodSpoTotal = spoSweepResults->goodSpoRight + spoSweepResults->goodSpoLeft; + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DfrmFifoDepthGet(adi_adrv9025_Device_t *device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint8_t channelId, + uint8_t *fifoDepth) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + adrv9025_BfJrxLinkChanAddr_e baseAddr = ADRV9025_BF_JRX_LINK0; + + /* NULL pointer check */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, fifoDepth); + + /* Write to log file */ + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + if (deframerSelect == ADI_ADRV9025_DEFRAMER_0) + { + baseAddr = ADRV9025_BF_JRX_LINK0; + } + else if (deframerSelect == ADI_ADRV9025_DEFRAMER_1) + { + baseAddr = ADRV9025_BF_JRX_LINK1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelect, + "Error invalid JESD Deframer Select Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_JrxLinkJrxTplBufDepthBfGet(device, baseAddr, channelId, fifoDepth); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to return the elastic FIFO depth"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DfrmBufferProtectionStatusGet(adi_adrv9025_Device_t *device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint8_t *bufferProtectionStatus) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + adrv9025_BfJrxLinkChanAddr_e baseAddr = ADRV9025_BF_JRX_LINK0; + + /* NULL pointer check */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, bufferProtectionStatus); + + /* Write to log file */ + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + if (deframerSelect == ADI_ADRV9025_DEFRAMER_0) + { + baseAddr = ADRV9025_BF_JRX_LINK0; + } + else if (deframerSelect == ADI_ADRV9025_DEFRAMER_1) + { + baseAddr = ADRV9025_BF_JRX_LINK1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelect, + "Error invalid JESD Deframer Select Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_JrxLinkJrxTplBufProtectionBfGet(device, baseAddr, bufferProtectionStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to read Buffer Protection status"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DfrmBufferProtectionSet(adi_adrv9025_Device_t *device, + uint8_t bufferProtectionSet, + adi_adrv9025_DeframerSel_e deframerSelect) +{ + uint8_t i = 0; + uint32_t dfrmSelect = deframerSelect; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + adrv9025_BfJrxLinkChanAddr_e baseAddr = ADRV9025_BF_JRX_LINK0; + + /* NULL pointer check */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + /* Write to log file */ + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + if ((deframerSelect != ADI_ADRV9025_DEFRAMER_0) && + (deframerSelect != ADI_ADRV9025_DEFRAMER_1) && + (deframerSelect != ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelect, + "Error invalid JESD Deframer Select Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < deframerSelect; i++) + { + if ((dfrmSelect & ADI_ADRV9025_DEFRAMER_0) == ADI_ADRV9025_DEFRAMER_0) + { + baseAddr = ADRV9025_BF_JRX_LINK0; + dfrmSelect -= ADI_ADRV9025_DEFRAMER_0; + } + else if ((dfrmSelect & ADI_ADRV9025_DEFRAMER_1) == ADI_ADRV9025_DEFRAMER_1) + { + baseAddr = ADRV9025_BF_JRX_LINK1; + dfrmSelect -= ADI_ADRV9025_DEFRAMER_1; + } + else + { + break; + } + + recoveryAction = adrv9025_JrxLinkJrxTplBufProtectEnBfSet(device, baseAddr, bufferProtectionSet); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Failed to disable/enable the underflow protection for the buffer"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DfrmBufferProtectionGet(adi_adrv9025_Device_t *device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint8_t *bufferProtectionGet) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + adrv9025_BfJrxLinkChanAddr_e baseAddr = ADRV9025_BF_JRX_LINK0; + + /* NULL pointer check */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, bufferProtectionGet); + + /* Write to log file */ + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + if (deframerSelect == ADI_ADRV9025_DEFRAMER_0) + { + baseAddr = ADRV9025_BF_JRX_LINK0; + } + else if (deframerSelect == ADI_ADRV9025_DEFRAMER_1) + { + baseAddr = ADRV9025_BF_JRX_LINK1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelect, + "Error invalid JESD Deframer Select Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_JrxLinkJrxTplBufProtectEnBfGet(device, baseAddr, bufferProtectionGet); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Failed to return current state of the buffer protection"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DfrmLmfcOffsetSet(adi_adrv9025_Device_t *device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint16_t lmfcOffset) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfJrxLinkChanAddr_e baseAddrRx = ADRV9025_BF_JRX_LINK0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + /* Range Check deframerSelect */ + if ((deframerSelect != ADI_ADRV9025_DEFRAMER_0) && (deframerSelect != ADI_ADRV9025_DEFRAMER_1) && (deframerSelect != ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelect, + "Error invalid JESD Deframer Select Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((deframerSelect == ADI_ADRV9025_DEFRAMER_0) || (deframerSelect == ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + baseAddrRx = ADRV9025_BF_JRX_LINK0; + recoveryAction = adrv9025_JrxLinkJrxTplPhaseAdjustBfSet(device, baseAddrRx, lmfcOffset); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to set LMFC Offset for Deframer 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((deframerSelect == ADI_ADRV9025_DEFRAMER_1) || (deframerSelect == ADI_ADRV9025_DEFRAMER_0_AND_1)) + { + baseAddrRx = ADRV9025_BF_JRX_LINK1; + recoveryAction = adrv9025_JrxLinkJrxTplPhaseAdjustBfSet(device, baseAddrRx, lmfcOffset); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to set LMFC Offset for Deframer 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_DfrmLmfcOffsetGet(adi_adrv9025_Device_t *device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint16_t *lmfcOffset) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfJrxLinkChanAddr_e baseAddrRx = ADRV9025_BF_JRX_LINK0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, lmfcOffset); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, lmfcOffset); + + /* Range Check deframerSelect */ + if ((deframerSelect != ADI_ADRV9025_DEFRAMER_0) && (deframerSelect != ADI_ADRV9025_DEFRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelect, + "Error invalid JESD Deframer Select Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (deframerSelect == ADI_ADRV9025_DEFRAMER_0) + { + baseAddrRx = ADRV9025_BF_JRX_LINK0; + recoveryAction = adrv9025_JrxLinkJrxTplPhaseAdjustBfGet(device, baseAddrRx, lmfcOffset); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to set LMFC Offset for Deframer 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (deframerSelect == ADI_ADRV9025_DEFRAMER_1) + { + baseAddrRx = ADRV9025_BF_JRX_LINK1; + recoveryAction = adrv9025_JrxLinkJrxTplPhaseAdjustBfGet(device, baseAddrRx, lmfcOffset); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to set LMFC Offset for Deframer 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + + +int32_t adi_adrv9025_DfrmPhaseDiffGet(adi_adrv9025_Device_t *device, + adi_adrv9025_DeframerSel_e deframerSelect, + uint8_t channelId, + uint8_t *phaseDiff) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + adrv9025_BfJrxLinkChanAddr_e baseAddr = ADRV9025_BF_JRX_LINK0; + + /* NULL pointer check */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, phaseDiff); + + /* Write to log file */ + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + if (deframerSelect == ADI_ADRV9025_DEFRAMER_0) + { + baseAddr = ADRV9025_BF_JRX_LINK0; + } + else if (deframerSelect == ADI_ADRV9025_DEFRAMER_1) + { + baseAddr = ADRV9025_BF_JRX_LINK1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelect, + "Error invalid JESD Deframer Select Value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_JrxLinkJrxTplPhaseDiffBfGet(device, baseAddr, channelId, phaseDiff); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to return the elastic FIFO depth"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_GenerateEyeDiagramQRMode(adi_adrv9025_Device_t *device, + uint8_t lane, + adi_adrv9025_EyeDiagramResultsQR_t **results) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + static const uint8_t numPhasesPerUI = ADRV9025_QR_EYE_NUM_PHASES; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_DEVICE_PTR_RETURN(results); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + /* calculate positive eye i.e. direction 1 */ + recoveryAction = adrv9025_GenerateEyeDiagram_Direction(device, lane, results, numPhasesPerUI, 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to read calculate positive eye"); + ADI_ERROR_RETURN(device->common.error.newAction); + /* calculate negative eye i.e. direction 0 */ + recoveryAction = adrv9025_GenerateEyeDiagram_Direction(device, lane, results, numPhasesPerUI, 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to read calculate negative eye"); + ADI_ERROR_RETURN(device->common.error.newAction); + + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_dynamic_slicer.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_dynamic_slicer.c new file mode 100644 index 0000000..ff47ff2 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_dynamic_slicer.c @@ -0,0 +1,336 @@ +/** +* \file adi_adrv9025_dynamic_slicer.c +* \brief Contains dynamic slicer function implementation defined in adi_adrv9025_dynamic_slicer.h +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "adi_adrv9025_error.h" +#include "adi_adrv9025_dynamic_slicer.h" +#include "adi_adrv9025_hal.h" +#include "../../private/include/adrv9025_dynamic_slicer.h" +#include "../../private/include/adrv9025_rx.h" +#include "../../private/include/adrv9025_bf_rx.h" +#include "../../private/include/adrv9025_bf_orx.h" + +#ifdef _RELEASE_BUILD_ +#line __LINE__ "adi_adrv9025_dynamic_slicer.c" +#endif + +int32_t adi_adrv9025_RxDynamicSlicerConfigSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxDynamicSlicerConfig_t rxDynamicSlicerCfg[], + uint8_t arraySize) +{ + uint8_t rxDynamicSlicerConfigIndex = 0; + uint8_t intDataResolution = 0; + uint8_t intDataFormat = 0; + adi_adrv9025_IntegerConfigSettings_t integerConfigSettings = {ADI_ADRV9025_NO_EMBEDDED_SLICER_BITS}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check Rx data format config pointer is not NULL*/ + ADI_NULL_PTR_RETURN(&device->common, + rxDynamicSlicerCfg); + +#if ADI_ADRV9025_RX_RANGE_CHECK > 0 + adrv9025_RxDynamicSlicerConfigSetRangeCheck(device, + rxDynamicSlicerCfg, + arraySize); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + for (rxDynamicSlicerConfigIndex = 0; rxDynamicSlicerConfigIndex < arraySize; rxDynamicSlicerConfigIndex++) + { + /* Resolve integer sample resolution and data format */ + integerConfigSettings.intSampleResolution = rxDynamicSlicerCfg[rxDynamicSlicerConfigIndex].intSampleResolution; + adrv9025_RxIntSampleResFormatResolve(device, + &integerConfigSettings, + &intDataResolution, + &intDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Disable gain compensation and reset the formatter settings to default */ + adrv9025_RxDataFormatGainCompDisable(device, + rxDynamicSlicerCfg[rxDynamicSlicerConfigIndex].rxChannelMask, + intDataFormat, + intDataResolution); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Setup Dynamic slicer config */ + adrv9025_RxDynamicSlicerEnableSet(device, + rxDynamicSlicerCfg, + rxDynamicSlicerCfg[rxDynamicSlicerConfigIndex].dynamicSlicerEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_RxDynamicSlicerConfigGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxDynamicSlicerConfig_t* rxDynamicSlicerCfg) +{ + static const uint32_t ALL_RX_MASK = (ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4); + static const uint32_t ALL_ORX_MASK = (ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2 | ADI_ADRV9025_ORX3 | ADI_ADRV9025_ORX4); + + uint8_t intDataResolution = 0; + uint8_t intDataFormat = 0; + uint8_t intEmbedSlicerPos = 0; + uint8_t intEmbedSlicerNumber = 0; + uint8_t intSlicerStepSize = 0; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddress = (adrv9025_BfRxChanAddr_e)0; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddress = (adrv9025_BfOrxChanAddr_e)0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check Rx dynamic slicer config pointer is not NULL*/ + ADI_NULL_PTR_RETURN(&device->common, + rxDynamicSlicerCfg); + + /*Check that the requested rxChannel is exactly 1 valid channel*/ + if ((rxChannel != ADI_ADRV9025_RX1) && + (rxChannel != ADI_ADRV9025_RX2) && + (rxChannel != ADI_ADRV9025_RX3) && + (rxChannel != ADI_ADRV9025_RX4) && + (rxChannel != ADI_ADRV9025_ORX1) && + (rxChannel != ADI_ADRV9025_ORX2) && + (rxChannel != ADI_ADRV9025_ORX3) && + (rxChannel != ADI_ADRV9025_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx channel encountered while attempting to retrieve the dynamic slicer configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((ALL_RX_MASK & (uint32_t)rxChannel) == (uint32_t)rxChannel) + { + adrv9025_RxBitfieldAddressGet(device, + rxChannel, + &rxChannelBitfieldAddress); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDynamicSlicerModeEnBfGet(device, + rxChannelBitfieldAddress, + &rxDynamicSlicerCfg->dynamicSlicerEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDynamicSlicerAgcSyncEnableBfGet(device, + rxChannelBitfieldAddress, + &rxDynamicSlicerCfg->dynamicSlicerAgcSyncEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDynamicSlicerSyncHeadBfGet(device, + rxChannelBitfieldAddress, + &rxDynamicSlicerCfg->dynamicSlicerSyncHeader); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxIntDataResolutionBfGet(device, + rxChannelBitfieldAddress, + &intDataResolution); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxIntDataFormatBfGet(device, + rxChannelBitfieldAddress, + &intDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxIntEmbedSlicerNumberBfGet(device, + rxChannelBitfieldAddress, + &intEmbedSlicerNumber); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxIntEmbedSlicerPosBfGet(device, + rxChannelBitfieldAddress, + &intEmbedSlicerPos); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxSlicerPinControlStepBfGet(device, + rxChannelBitfieldAddress, + &intSlicerStepSize); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if ((ALL_ORX_MASK & (uint32_t)rxChannel) == (uint32_t)rxChannel) + { + adrv9025_OrxBitfieldAddressGet(device, + rxChannel, + &orxChannelBitfieldAddress); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_OrxDynamicSlicerModeEnBfGet(device, + orxChannelBitfieldAddress, + &rxDynamicSlicerCfg->dynamicSlicerEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_OrxDynamicSlicerAgcSyncEnableBfGet(device, + orxChannelBitfieldAddress, + &rxDynamicSlicerCfg->dynamicSlicerAgcSyncEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_OrxDynamicSlicerSyncHeadBfGet(device, + orxChannelBitfieldAddress, + &rxDynamicSlicerCfg->dynamicSlicerSyncHeader); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_OrxIntDataResolutionBfGet(device, + orxChannelBitfieldAddress, + &intDataResolution); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_OrxIntDataFormatBfGet(device, + orxChannelBitfieldAddress, + &intDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_OrxIntEmbedSlicerNumberBfGet(device, + orxChannelBitfieldAddress, + &intEmbedSlicerNumber); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_OrxIntEmbedSlicerPosBfGet(device, + orxChannelBitfieldAddress, + &intEmbedSlicerPos); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_OrxSlicerPinControlStepBfGet(device, + orxChannelBitfieldAddress, + &intSlicerStepSize); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + adrv9025_RxIntSampleResFormatEncode(device, + intDataResolution, + intDataFormat, + &rxDynamicSlicerCfg->intSampleResolution); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxIntEmbSlicerConfigEncode(device, + rxChannel, + rxDynamicSlicerCfg->dynamicSlicerEnable, + intEmbedSlicerPos, + intEmbedSlicerNumber, + &rxDynamicSlicerCfg->intEmbeddedBits); + ADI_ERROR_RETURN(device->common.error.newAction); + + rxDynamicSlicerCfg->intSlicerStepSize = (adi_adrv9025_IntSlicerStepSizes_e)intSlicerStepSize; + rxDynamicSlicerCfg->rxChannelMask = (uint32_t)rxChannel; + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_RxDynamicSlicerDataResend(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask) +{ + static const adi_adrv9025_RxChannels_e RX_CHANNEL_ARR[] = {ADI_ADRV9025_RX1, ADI_ADRV9025_RX2, ADI_ADRV9025_RX3, ADI_ADRV9025_RX4}; + static const adi_adrv9025_RxChannels_e ORX_CHANNEL_ARR[] = {ADI_ADRV9025_ORX1, ADI_ADRV9025_ORX2, ADI_ADRV9025_ORX3, ADI_ADRV9025_ORX4}; + static const uint8_t DYNAMIC_SLICER_RESEND_ASSERT = 1; + static const uint8_t DYNAMIC_SLICER_RESEND_DEASSERT = 0; + + uint8_t rxChannelIndex = 0; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddress = (adrv9025_BfRxChanAddr_e)0; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddress = (adrv9025_BfOrxChanAddr_e)0; + adi_adrv9025_RxDynamicSlicerConfig_t rxDynamicSlicerConfig = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + for (rxChannelIndex = 0; rxChannelIndex < (sizeof(RX_CHANNEL_ARR) / sizeof(RX_CHANNEL_ARR[0])); rxChannelIndex++) + { + if ((rxChannelMask & (uint32_t)RX_CHANNEL_ARR[rxChannelIndex]) == (uint32_t)RX_CHANNEL_ARR[rxChannelIndex]) + { + adi_adrv9025_RxDynamicSlicerConfigGet(device, + RX_CHANNEL_ARR[rxChannelIndex], + &rxDynamicSlicerConfig); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (rxDynamicSlicerConfig.dynamicSlicerEnable == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxDynamicSlicerConfig.dynamicSlicerEnable, + "Dynamic slicer mode needs to be enabled to issue a dynamic slicer data resend request"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Resolve the baseaddress of the target Rx channel */ + adrv9025_RxBitfieldAddressGet(device, + RX_CHANNEL_ARR[rxChannelIndex], + &rxChannelBitfieldAddress); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Assert the dynamic slicer data resend signal */ + adrv9025_RxDynamicSlicerResendBfSet(device, + rxChannelBitfieldAddress, + DYNAMIC_SLICER_RESEND_ASSERT); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Deassert the dynamic slicer data resend signal */ + adrv9025_RxDynamicSlicerResendBfSet(device, + rxChannelBitfieldAddress, + DYNAMIC_SLICER_RESEND_DEASSERT); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + for (rxChannelIndex = 0; rxChannelIndex < (sizeof(ORX_CHANNEL_ARR) / sizeof(ORX_CHANNEL_ARR[0])); rxChannelIndex++) + { + if ((rxChannelMask & (uint32_t)ORX_CHANNEL_ARR[rxChannelIndex]) == (uint32_t)ORX_CHANNEL_ARR[rxChannelIndex]) + { + adi_adrv9025_RxDynamicSlicerConfigGet(device, + ORX_CHANNEL_ARR[rxChannelIndex], + &rxDynamicSlicerConfig); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (rxDynamicSlicerConfig.dynamicSlicerEnable == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxDynamicSlicerConfig.dynamicSlicerEnable, + "Dynamic slicer mode needs to be enabled to issue a dynamic slicer data resend request"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Resolve the baseaddress of the target ORx channel */ + adrv9025_OrxBitfieldAddressGet(device, + ORX_CHANNEL_ARR[rxChannelIndex], + &orxChannelBitfieldAddress); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Assert the dynamic slicer data resend signal */ + adrv9025_OrxDynamicSlicerResendBfSet(device, + orxChannelBitfieldAddress, + DYNAMIC_SLICER_RESEND_ASSERT); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Deassert the dynamic slicer data resend signal */ + adrv9025_OrxDynamicSlicerResendBfSet(device, + orxChannelBitfieldAddress, + DYNAMIC_SLICER_RESEND_DEASSERT); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_gpio.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_gpio.c new file mode 100644 index 0000000..df06b31 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_gpio.c @@ -0,0 +1,1930 @@ +/** +* \file adi_adrv9025_gpio.c +* \brief Contains gpio features related function implementation defined in +* adi_adrv9025_gpio.h +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/* +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "adi_adrv9025_gpio.h" +#include "adi_adrv9025_cpu.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_error.h" +#include "../../private/include/adrv9025_gpio.h" +#include "../../private/include/adrv9025_cpu.h" +#include "../../private/include/adrv9025_bf_core.h" +#include "../../private/include/adrv9025_reg_addr_macros.h" +#include "../../private/include/adrv9025_cpu_macros.h" +#include "../../private/include/adrv9025_bf_tx.h" +#include "../../private/include/adrv9025_shared_resource_manager.h" +#include "../../private/include/adrv9025_bf_analog_tx_mem_map.h" +#include "../../private/include/adrv9025_bf_orx.h" + +#ifdef _RELEASE_BUILD_ + #line __LINE__ "adi_adrv9025_gpio.c" +#endif + +int32_t adi_adrv9025_GpioOeGet(adi_adrv9025_Device_t* device, + uint32_t* gpioOutEn) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check GPIO out en write back pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + gpioOutEn); + + recoveryAction = adrv9025_CoreGpioDirectionControlOeBfGet(device, + ADRV9025_BF_CORE, + gpioOutEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read GPIO Direction Control bitfields"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_GpioInputDirSet(adi_adrv9025_Device_t* device, + uint32_t gpioInputMask) +{ + static const uint32_t GPIO_OE_MASK = 0x7FFFF; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t gpioOutEn = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that GPIO Input Mask is within range */ + if (gpioInputMask > GPIO_OE_MASK) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + gpioInputMask, + "GPIO input mask is out of range. Valid range 0x00000-0x7FFFF(GPIO0-GPIO18)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Read the current status of GPIO direction control of ADRV9025 */ + recoveryAction = adi_adrv9025_GpioOeGet(device, + &gpioOutEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error reading current ADRV9025 GPIO OE while attempting to set GPIO input mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* To set the GPIOs as input, 0 has to be written to the corresponding GPIO direction control bitfield */ + gpioOutEn &= GPIO_OE_MASK; + gpioOutEn &= ~gpioInputMask; + recoveryAction = adrv9025_CoreGpioDirectionControlOeBfSet(device, + ADRV9025_BF_CORE, + gpioOutEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + gpioInputMask, + "Error writing ADRV9025 GPIO OE while attempting to set GPIO input direction control"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_GpioAnalogInputDirSet(adi_adrv9025_Device_t* device, + uint8_t gpioAnalogInputMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t gpioAnalogOutEn = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Read the current status of GPIO direction control of ADRV9025 */ + recoveryAction = adrv9025_CoreGpioAnalogDirectionControlOeBfGet(device, + ADRV9025_BF_CORE, + &gpioAnalogOutEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error reading current ADRV9025 Analog GPIO OE while attempting to set GPIO_ANA input direction control"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* To set the GPIOs as input, 0 has to be written to the corresponding GPIO direction control bitfield */ + gpioAnalogOutEn &= ~gpioAnalogInputMask; + recoveryAction = adrv9025_CoreGpioAnalogDirectionControlOeBfSet(device, + ADRV9025_BF_CORE, + gpioAnalogOutEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + gpioAnalogInputMask, + "Error writing ADRV9025 Analog GPIO OE while attempting to set GPIO_ANA input direction control"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_GpioAnalogOutputDirSet(adi_adrv9025_Device_t* device, + uint8_t gpioAnalogOutputMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t gpioAnalogOutEn = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Read the current status of GPIO direction control of ADRV9025 */ + recoveryAction = adrv9025_CoreGpioAnalogDirectionControlOeBfGet(device, + ADRV9025_BF_CORE, + &gpioAnalogOutEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error reading current ADRV9025 Analog GPIO OE while attempting to set GPIO_ANA output mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* To set the GPIOs as output, 1 has to be written to the corresponding GPIO direction control bitfield */ + gpioAnalogOutEn |= gpioAnalogOutputMask; + recoveryAction = adrv9025_CoreGpioAnalogDirectionControlOeBfSet(device, + ADRV9025_BF_CORE, + gpioAnalogOutEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + gpio3v3OutputMask, + "Error writing ADRV9025 Analog GPIO OE while attempting to set GPIO_ANA output direction control"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_GpioOutputDirSet(adi_adrv9025_Device_t* device, + uint32_t gpioOutputMask) + +{ + static const uint32_t GPIO_OE_MASK = 0x7FFFF; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t gpioOutEn = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that GPIO Input Mask is within range */ + if (gpioOutputMask > GPIO_OE_MASK) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + gpioOutputMask, + "GPIO output mask is out of range. Valid range 0x00000-0x7FFFF(GPIO0-GPIO18)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Read the current status of GPIO direction control of ADRV9025 */ + recoveryAction = adi_adrv9025_GpioOeGet(device, + &gpioOutEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + recoveryAction, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "Error reading current ADRV9025 GPIO OE while attempting to set GPIO input mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* To set the GPIOs as output, 1 has to be written to the corresponding GPIO direction control bitfield */ + gpioOutEn |= gpioOutputMask; + + recoveryAction = adrv9025_CoreGpioDirectionControlOeBfSet(device, + ADRV9025_BF_CORE, + gpioOutEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + recoveryAction, + recoveryAction, + gpioOutputMask, + "Error writing ADRV9025 GPIO OE while attempting to set GPIO output direction control"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_GpioOeSet(adi_adrv9025_Device_t* device, + uint32_t gpioOutEn, + uint32_t gpioUsedMask) +{ + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + UNUSED_PARA(device); + UNUSED_PARA(gpioOutEn); + UNUSED_PARA(gpioUsedMask); + return 0; +} + +int32_t adi_adrv9025_GpioOutSourceCtrlSet(adi_adrv9025_Device_t* device, + uint32_t gpioSrcCtrl) +{ + static const uint32_t GPIO_SRC_MASK = 0xFFFFF; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t regData = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that GPIO Source Control is within range */ + if (gpioSrcCtrl > GPIO_SRC_MASK) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + gpioInputMask, + "GPIO output Source Control is out of range. Valid range 0x00000-0x7FFFF(GPIO0-GPIO18)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + regData = (uint8_t)((gpioSrcCtrl >> 0) & 0x0000000F); + recoveryAction = adrv9025_CoreGpioLowerByteLowerNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + regData); + ADI_ERROR_RETURN(device->common.error.newAction); + + regData = (uint8_t)((gpioSrcCtrl >> 4) & 0x0000000F); + recoveryAction = adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + regData); + ADI_ERROR_RETURN(device->common.error.newAction); + + regData = (uint8_t)((gpioSrcCtrl >> 8) & 0x0000000F); + recoveryAction = adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + regData); + ADI_ERROR_RETURN(device->common.error.newAction); + + regData = (uint8_t)((gpioSrcCtrl >> 12) & 0x0000000F); + recoveryAction = adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + regData); + ADI_ERROR_RETURN(device->common.error.newAction); + + regData = (uint8_t)((gpioSrcCtrl >> 16) & 0x0000000F); + recoveryAction = adrv9025_CoreGpioExtraBitsSourceControlBfSet(device, + ADRV9025_BF_CORE, + regData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error from BF CODE"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_GpioOutSourceCtrlGet(adi_adrv9025_Device_t* device, + uint32_t* gpioSrcCtrl) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t regData[5] = {0}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + gpioSrcCtrl); + + recoveryAction = adrv9025_CoreGpioLowerByteLowerNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + ®Data[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpioLowerByteUpperNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + ®Data[1]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpioUpperByteLowerNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + ®Data[2]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpioUpperByteUpperNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + ®Data[3]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreGpioExtraBitsSourceControlBfGet(device, + ADRV9025_BF_CORE, + ®Data[4]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error from BF CODE"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* reconstructing byte reads into gpioSrcCtrl word */ + *gpioSrcCtrl = ((uint32_t)(regData[4] & 0x0F) << 16) | ((uint32_t)(regData[3] & 0x0F) << 12) | + ((uint32_t)(regData[2] & 0x0F) << 8) | ((uint32_t)(regData[1] & 0x0F) << 4) | ((uint32_t)(regData[0] & 0x0F)); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_GpioOutPinLevelSet(adi_adrv9025_Device_t* device, + uint32_t gpioOutPinLevel) +{ + static const uint32_t GPIO_PIN_MASK = 0x7FFFF; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that GPIO Output Mask is within range */ + if (gpioOutPinLevel > GPIO_PIN_MASK) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + gpioInputMask, + "GPIO output Pin Level is out of range. Valid range 0x00000-0x7FFFF(GPIO0-GPIO18)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_CoreGpioSpiSourceBfSet(device, + ADRV9025_BF_CORE, + gpioOutPinLevel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + gpioInPinLevel, + "Error writing ADRV9025 GPIO Output Pin Level"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (recoveryAction); +} + +int32_t adi_adrv9025_GpioInputPinLevelGet(adi_adrv9025_Device_t* device, + uint32_t* gpioInPinLevel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + gpioInPinLevel); + + recoveryAction = adrv9025_CoreGpioSpiReadBfGet(device, + ADRV9025_BF_CORE, + gpioInPinLevel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + gpioInPinLevel, + "Error reading ADRV9025 GPIO Input Pin Level"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (recoveryAction); +} + +int32_t adi_adrv9025_GpioOutPinLevelGet(adi_adrv9025_Device_t* device, + uint32_t* gpioOutPinLevel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + gpioOutPinLevel); + + recoveryAction = adrv9025_CoreGpioSpiSourceBfGet(device, + ADRV9025_BF_CORE, + gpioOutPinLevel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + gpioOutPinLevel, + "Error reading GPIO Output Pin Level"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (recoveryAction); +} + +int32_t adi_adrv9025_GpioMonitorOutSrcSet(adi_adrv9025_Device_t* device, + uint8_t monitorIndex, + uint8_t monitorMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t regData = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + recoveryAction = adrv9025_CoreMonitorOutBfSet(device, + ADRV9025_BF_CORE, + monitorIndex); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error writing GPIO Monitor Index"); + ADI_ERROR_RETURN(device->common.error.newAction); + + regData = (monitorMask & 0x01); + recoveryAction = adrv9025_CoreEnCtrl0BfSet(device, + ADRV9025_BF_CORE, + regData); + ADI_ERROR_RETURN(device->common.error.newAction); + + regData = (monitorMask >> 1) & 0x01; + recoveryAction = adrv9025_CoreEnCtrl1BfSet(device, + ADRV9025_BF_CORE, + regData); + ADI_ERROR_RETURN(device->common.error.newAction); + + regData = (monitorMask >> 2) & 0x01; + recoveryAction = adrv9025_CoreEnCtrl2BfSet(device, + ADRV9025_BF_CORE, + regData); + ADI_ERROR_RETURN(device->common.error.newAction); + + regData = (monitorMask >> 3) & 0x01; + recoveryAction = adrv9025_CoreEnCtrl3BfSet(device, + ADRV9025_BF_CORE, + regData); + ADI_ERROR_RETURN(device->common.error.newAction); + + regData = (monitorMask >> 4) & 0x01; + recoveryAction = adrv9025_CoreEnCtrl4BfSet(device, + ADRV9025_BF_CORE, + regData); + ADI_ERROR_RETURN(device->common.error.newAction); + + regData = (monitorMask >> 5) & 0x01; + recoveryAction = adrv9025_CoreEnCtrl5BfSet(device, + ADRV9025_BF_CORE, + regData); + ADI_ERROR_RETURN(device->common.error.newAction); + + regData = (monitorMask >> 6) & 0x01; + recoveryAction = adrv9025_CoreEnCtrl6BfSet(device, + ADRV9025_BF_CORE, + regData); + ADI_ERROR_RETURN(device->common.error.newAction); + + regData = (monitorMask >> 7) & 0x01; + recoveryAction = adrv9025_CoreEnCtrl7BfSet(device, + ADRV9025_BF_CORE, + regData); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (recoveryAction); +} + +int32_t adi_adrv9025_GpioMonitorOutSrcGet(adi_adrv9025_Device_t* device, + uint8_t* monitorIndex, + uint8_t* monitorMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t regData[8] = {0}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + monitorIndex); + + ADI_NULL_PTR_RETURN(&device->common, + monitorMask); + + recoveryAction = adrv9025_CoreMonitorOutBfGet(device, + ADRV9025_BF_CORE, + monitorIndex); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error reading GPIO Monitor Index"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreEnCtrl0BfGet(device, + ADRV9025_BF_CORE, + ®Data[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreEnCtrl1BfGet(device, + ADRV9025_BF_CORE, + ®Data[1]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreEnCtrl2BfGet(device, + ADRV9025_BF_CORE, + ®Data[2]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreEnCtrl3BfGet(device, + ADRV9025_BF_CORE, + ®Data[3]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreEnCtrl4BfGet(device, + ADRV9025_BF_CORE, + ®Data[4]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreEnCtrl5BfGet(device, + ADRV9025_BF_CORE, + ®Data[5]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreEnCtrl6BfGet(device, + ADRV9025_BF_CORE, + ®Data[6]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_CoreEnCtrl7BfGet(device, + ADRV9025_BF_CORE, + ®Data[7]); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* reconstructing bit reads into monitorMask */ + *monitorMask = (((regData[7] & 0x01) << 7) | ((regData[6] & 0x01) << 6) | + ((regData[5] & 0x01) << 5) | ((regData[4] & 0x01) << 4) | + ((regData[3] & 0x01) << 3) | ((regData[2] & 0x01) << 2) | + ((regData[1] & 0x01) << 1) | (regData[0] & 0x01)); + + return (recoveryAction); +} + +int32_t adi_adrv9025_GPIntClearStatusRegister(adi_adrv9025_Device_t* device) +{ + static const uint64_t STATUS_CLEAR_ALL = 0xFFFFFFFFFFFFFFFF; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint64_t status = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Clearing status register in hardware requires all sticky bits set to 1 to clear their corresponding status bit */ + /* First save current state of sticky mask reg */ + recoveryAction = adrv9025_CoreGpInterruptsStickyBitMaskBfGet(device, + ADRV9025_BF_CORE, + &status); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set all bits to one to clear corresponding status register bit */ + recoveryAction = adrv9025_CoreGpInterruptsStickyBitMaskBfSet(device, + ADRV9025_BF_CORE, + STATUS_CLEAR_ALL); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Restore sticky mask reg to what it was before clearing. */ + recoveryAction = adrv9025_CoreGpInterruptsStickyBitMaskBfSet(device, + ADRV9025_BF_CORE, + status); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_adrv9025_GpInt0Handler(adi_adrv9025_Device_t* device, + adi_adrv9025_gpIntStatus_t* gpInt0Status) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + static const uint64_t GPINT_CLEAR_INTERRUPTS = 0x0000000000000000; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + gpInt0Status); + + /* block all gpInt1 (lower Priority) Interrupts during gpInt0 processing */ + /* retrieve the general purpose interrupt Pin0 IRQ mask */ + recoveryAction = adrv9025_CoreGpInterruptsMaskPin0BfGet(device, + ADRV9025_BF_CORE, + &gpInt0Status->gp_Int_Save_Irq_Mask0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* retrieve the general purpose interrupt Pin1 IRQ mask */ + recoveryAction = adrv9025_CoreGpInterruptsMaskPin1BfGet(device, + ADRV9025_BF_CORE, + &gpInt0Status->gp_Int_Save_Irq_Mask1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* retrieve status register sticky mask */ + recoveryAction = adrv9025_CoreGpInterruptsStickyBitMaskBfGet(device, + ADRV9025_BF_CORE, + &gpInt0Status->gp_Int_StickyBit_Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* retrieve general purpose interrupt status word */ + recoveryAction = adrv9025_CoreGpInterruptsStatusWordBfGet(device, + ADRV9025_BF_CORE, + &gpInt0Status->gp_Interrupt_Status); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Clear all events as we process the status register (this also clears the relevant bits of the status register)*/ + recoveryAction = adrv9025_CoreGpInterruptsStickyBitMaskBfSet(device, + ADRV9025_BF_CORE, + GPINT_CLEAR_INTERRUPTS); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Save current GP Int pin0 mask to the mask variable */ + gpInt0Status->gp_Int_Irq_Mask = gpInt0Status->gp_Int_Save_Irq_Mask0; + + /* Mask for active sources */ + gpInt0Status->gp_Int_Active_Sources = (gpInt0Status->gp_Interrupt_Status & ~gpInt0Status->gp_Int_Irq_Mask); + + /* call the gp handler */ + adrv9025_GpIntHandler(device, + gpInt0Status); + + return recoveryAction; +} + +int32_t adi_adrv9025_GpInt1Handler(adi_adrv9025_Device_t* device, + adi_adrv9025_gpIntStatus_t* gpInt1Status) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + static const uint64_t GPINT_CLEAR_INTERRUPTS = 0x0000000000000000; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + gpInt1Status); + + /* block all gpInt0 (lower Priority) Interrupts during gpInt1 processing */ + /* retrieve the general purpose interrupt Pin0 IRQ mask */ + recoveryAction = adrv9025_CoreGpInterruptsMaskPin0BfGet(device, + ADRV9025_BF_CORE, + &gpInt1Status->gp_Int_Save_Irq_Mask0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* retrieve the general purpose interrupt Pin1 IRQ mask */ + recoveryAction = adrv9025_CoreGpInterruptsMaskPin1BfGet(device, + ADRV9025_BF_CORE, + &gpInt1Status->gp_Int_Save_Irq_Mask1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* retrieve status register sticky mask */ + recoveryAction = adrv9025_CoreGpInterruptsStickyBitMaskBfGet(device, + ADRV9025_BF_CORE, + &gpInt1Status->gp_Int_StickyBit_Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* retrieve general purpose interrupt status word */ + recoveryAction = adrv9025_CoreGpInterruptsStatusWordBfGet(device, + ADRV9025_BF_CORE, + &gpInt1Status->gp_Interrupt_Status); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Clear all events as we process the status register (this also clears the relevant bits of the status register)*/ + recoveryAction = adrv9025_CoreGpInterruptsStickyBitMaskBfSet(device, + ADRV9025_BF_CORE, + GPINT_CLEAR_INTERRUPTS); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Save current GP Int pin1 mask to the mask variable */ + gpInt1Status->gp_Int_Irq_Mask = gpInt1Status->gp_Int_Save_Irq_Mask1; + + /* Mask for active sources */ + gpInt1Status->gp_Int_Active_Sources = (gpInt1Status->gp_Interrupt_Status & ~gpInt1Status->gp_Int_Irq_Mask); + + /* call the gp handler */ + adrv9025_GpIntHandler(device, + gpInt1Status); + + return recoveryAction; +} + +int32_t adi_adrv9025_GpIntMaskSet(adi_adrv9025_Device_t* device, + adi_adrv9025_gpMaskSelect_e maskSelect, + adi_adrv9025_gp_MaskArray_t* maskArray) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + maskArray); + + /* range check channel enum */ + if ((maskSelect != ADI_ADRV9025_GPINT0) && (maskSelect != ADI_ADRV9025_GPINT1) && (maskSelect != ADI_ADRV9025_GPINTALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + maskSelect, + "Channel provided is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((maskSelect == ADI_ADRV9025_GPINT0) || (maskSelect == ADI_ADRV9025_GPINTALL)) + { + /* retrieve the general purpose interrupt Pin0 IRQ mask */ + recoveryAction = adrv9025_CoreGpInterruptsMaskPin0BfSet(device, + ADRV9025_BF_CORE, + maskArray->gpInt0Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + maskArray, + "Error while trying to set CoreGpInterruptsMaskPin0 - Silicon B"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((maskSelect == ADI_ADRV9025_GPINT1) || (maskSelect == ADI_ADRV9025_GPINTALL)) + { + /* retrieve the general purpose interrupt Pin1 IRQ mask */ + recoveryAction = adrv9025_CoreGpInterruptsMaskPin1BfSet(device, + ADRV9025_BF_CORE, + maskArray->gpInt1Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + maskArray, + "Error while trying to set CoreGpInterruptsMaskPin1 - Silicon B"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_GpIntMaskGet(adi_adrv9025_Device_t* device, + adi_adrv9025_gpMaskSelect_e maskSelect, + adi_adrv9025_gp_MaskArray_t* maskArray) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + maskArray); + + /* range check channel enum */ + if ((maskSelect != ADI_ADRV9025_GPINT0) && (maskSelect != ADI_ADRV9025_GPINT1) && (maskSelect != ADI_ADRV9025_GPINTALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + maskSelect, + "Channel provided is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((maskSelect == ADI_ADRV9025_GPINT0) || (maskSelect == ADI_ADRV9025_GPINTALL)) + { + /* retrieve the general purpose interrupt Pin0 IRQ mask */ + recoveryAction = adrv9025_CoreGpInterruptsMaskPin0BfGet(device, + ADRV9025_BF_CORE, + &maskArray->gpInt0Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + maskArray, + "Error while trying to get CoreGpInterruptsMaskPin0 - Silicon B"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((maskSelect == ADI_ADRV9025_GPINT1) || (maskSelect == ADI_ADRV9025_GPINTALL)) + { + /* retrieve the general purpose interrupt Pin1 IRQ mask */ + recoveryAction = adrv9025_CoreGpInterruptsMaskPin1BfGet(device, + ADRV9025_BF_CORE, + &maskArray->gpInt1Mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + maskArray, + "Error while trying to get CoreGpInterruptsMaskPin1 - Silicon B"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_GpIntStatusGet(adi_adrv9025_Device_t* device, + uint64_t* gpIntStatus) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + gpIntStatus); + + /* retrieve the general purpose interrupt Pin0 IRQ mask */ + recoveryAction = adrv9025_CoreGpInterruptsStatusWordBfGet(device, + ADRV9025_BF_CORE, + gpIntStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + gpIntStatus, + "Error while trying to get GP Int Status - Silicon B"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_GpIntStickyBitMaskSet(adi_adrv9025_Device_t* device, + uint64_t eventMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + recoveryAction = adrv9025_CoreGpInterruptsStickyBitMaskBfSet(device, + ADRV9025_BF_CORE, + eventMask); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + eventMask, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_adrv9025_GpIntStickyBitMaskGet(adi_adrv9025_Device_t* device, + uint64_t* eventMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + eventMask); + + recoveryAction = adrv9025_CoreGpInterruptsStickyBitMaskBfGet(device, + ADRV9025_BF_CORE, + eventMask); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + eventMask, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_adrv9025_TemperatureGet(adi_adrv9025_Device_t* device, + int16_t* temperatureDegC) +{ + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t armExtData[1] = {ADRV9025_CPU_OBJECTID_TEMP_SENSOR}; + uint8_t cmdStatusByte = 0; + uint8_t armReadBack[2] = {0}; + int32_t errHdl = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + temperatureDegC); + + /* Execute ARM command to retrieve temperature */ + recoveryAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &armExtData[0], + sizeof(armExtData)); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &cmdStatusByte, + ADI_ADRV9025_GETTEMPERATURE_TIMEOUT_US, + ADI_ADRV9025_GETTEMPERATURE_INTERVAL_US); + + if ((cmdStatusByte >> 1) > 0) + { + recoveryAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + armExtData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Temperature from ARM mailbox */ + recoveryAction = adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armReadBack[0], + sizeof(armReadBack), + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + *temperatureDegC = (int16_t)((uint16_t)armReadBack[0] | ((uint16_t)armReadBack[1] << 8)); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_Spi2CfgSet(adi_adrv9025_Device_t* device, + uint8_t spi2Enable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t regData = 0; + uint8_t currentSpi2En = 0; + uint8_t resourceAcquisitionStatus = ADI_FAILURE; + uint8_t resourceReleaseStatus = ADI_FAILURE; +#define NUM_GPIOS_IN_SPI2_CTRL_PIN_FEATURE 4U + int32_t sharedResourceArr[NUM_GPIOS_IN_SPI2_CTRL_PIN_FEATURE] = {0}; + uint32_t spi2GpioPinMask = 0; + uint8_t sharedResourceCounter = 0; + + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_SPI2_CTRL_PIN; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + adi_adrv9025_Spi2CfgGet(device, + ¤tSpi2En); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Free current resource */ + if (currentSpi2En > 0) + { + /* Disable SPI2 */ + regData = 0; + recoveryAction = adrv9025_CoreSpi2EnBfSet(device, + ADRV9025_BF_CORE, + regData); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* GPIO 0/1/2/3 for SPI2 */ + sharedResourceArr[sharedResourceCounter++] = (uint32_t)ADI_ADRV9025_GPIO_00; + /* Release GPIO[1] if it is 4-wire mode */ + if (device->spiSettings.fourWireMode == 1) + { + sharedResourceArr[sharedResourceCounter++] = (uint32_t)ADI_ADRV9025_GPIO_01; + } + sharedResourceArr[sharedResourceCounter++] = (uint32_t)ADI_ADRV9025_GPIO_02; + sharedResourceArr[sharedResourceCounter++] = (uint32_t)ADI_ADRV9025_GPIO_03; + + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + sharedResourceCounter, + THIS_FEATURE_ID, + &resourceReleaseStatus); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceReleaseStatus, + "Error while attempting to release GPIO shared resouce for GPIO SPI2 ctrl Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Set released GPIO pins as inputs since unused pins are supposed to be inputs */ + spi2GpioPinMask = 0x0000000F; + recoveryAction = adi_adrv9025_GpioInputDirSet(device, + spi2GpioPinMask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (spi2Enable > 0) + { + sharedResourceCounter = 0; + + /* GPIO 0/1/2/3 for SPI2 */ + sharedResourceArr[sharedResourceCounter++] = (uint32_t)ADI_ADRV9025_GPIO_00; + if (device->spiSettings.fourWireMode == 1) + { + sharedResourceArr[sharedResourceCounter++] = (uint32_t)ADI_ADRV9025_GPIO_01; + } + sharedResourceArr[sharedResourceCounter++] = (uint32_t)ADI_ADRV9025_GPIO_02; + sharedResourceArr[sharedResourceCounter++] = (uint32_t)ADI_ADRV9025_GPIO_03; + + recoveryAction = adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + sharedResourceCounter, + THIS_FEATURE_ID, + &resourceAcquisitionStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to acquire GPIO shared resouce for GPIO SPI2 Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceAcquisitionStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceAcquisitionStatus, + "Error while attempting to acquire GPIO shared resouce for GPIO SPI2 Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Enable SPI2 */ + regData = 1; + recoveryAction = adrv9025_CoreSpi2EnBfSet(device, + ADRV9025_BF_CORE, + regData); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_Spi2CfgGet(adi_adrv9025_Device_t* device, + uint8_t* spi2Enable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + spi2Enable); + + /* Get current value of SPI2 */ + recoveryAction = adrv9025_CoreSpi2EnBfGet(device, + ADRV9025_BF_CORE, + spi2Enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error from BF CODE"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_AuxDacCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxDacCfg_t auxDacConfig[], + uint8_t numberOfCfg) +{ + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_AUX_DAC_OUT; + + /* Variables to iterate over configurations to be set */ + uint8_t i = 0; + uint8_t k = 0; + adi_adrv9025_AuxDacs_e auxDacSel = ADI_ADRV9025_AUXDAC0; + + /* Variable to hold enable/disable configuration */ + uint8_t bfEnable = 0; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Variables to handle shared GPIO sources */ + int32_t sharedResourceArr[ADI_ADRV9025_MAX_AUXDACS] = {0}; + uint8_t numSharedResources = 0; + uint8_t resourceAcquisitionStatus = ADI_FAILURE; + uint8_t resourceReleaseStatus = ADI_FAILURE; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + auxDacConfig); + + /* check that if number of configs is > 0 and <= 8 */ + if (numberOfCfg == 0 || numberOfCfg > 8) + { + /* no valid configs */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + numberOfCfg, + "Invalid number of configurations"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < numberOfCfg; i++) + { + /* Reset shared resource variable */ + numSharedResources = 0; + + /* Range check for all the values */ + if (adrv9025_AuxDacCfgRangeCheck(device, + &auxDacConfig[i]) != ADI_COMMON_ACT_NO_ACTION) + { + /* Configuration is not valid */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + auxDacConfig, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + for (k = 0; k < ADI_ADRV9025_MAX_AUXDACS; k++) + { + if (ADRV9025_BF_EQUAL(auxDacConfig[i].auxDacMask, + ((uint32_t)1 << (uint32_t)k))) + { + /* Add GPIO pin to shared resources array */ + sharedResourceArr[numSharedResources++] = (int32_t)k; + + /* Set AuxDAC configuration */ + auxDacSel = (adi_adrv9025_AuxDacs_e)((uint8_t)(1 << k)); + recoveryAction = adrv9025_AuxDacCfgSet(device, + auxDacSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Unable to set AuxDAC configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Read AuxDAC enable status for read/modify/write */ + recoveryAction = adrv9025_CorePdAuxdacBfGet(device, + ADRV9025_BF_CORE, + &bfEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while reading AuxDACs enabled bits"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Power up/down selected AuxDACs at this channel */ + bfEnable = bfEnable | auxDacConfig[i].auxDacMask; + + /*Try to Release Shared GPIOs */ + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, + &sharedResourceArr[0], + numSharedResources, + THIS_FEATURE_ID, + &resourceReleaseStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while releasing shared GPIO pins while disabling AuxDACs"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_ADRV9025_ERR_SHARED_RESOURCE_RELEASE, + ADI_ADRV9025_ACT_ERR_RESET_GPIO, + resourceReleaseStatus, + "Unable to release GPIOs for AuxDACs while disabling AuxDACs "); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Configure GPIO pin as input */ + recoveryAction = adi_adrv9025_GpioInputDirSet(device, + auxDacConfig[i].auxDacMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Unable to set GPIO direction as input "); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (auxDacConfig[i].enable > 0) + { + bfEnable = bfEnable & (~auxDacConfig[i].auxDacMask); + + /* Try to acquire Shared Analog GPIOs */ + recoveryAction = adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, + &sharedResourceArr[0], + numSharedResources, + THIS_FEATURE_ID, + &resourceAcquisitionStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while acquiring shared GPIO pins while enabling AuxDACs"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceAcquisitionStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_ADRV9025_ERR_SHARED_RESOURCE_ACQUIRE, + ADI_ADRV9025_ACT_ERR_RESET_GPIO, + resourceAcquisitionStatus, + "Unable to acquire shared Analog GPIOs while enabling AuxDACs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Set GPIO analog pins as output */ + if ((recoveryAction = adi_adrv9025_GpioOutputDirSet(device, + auxDacConfig[i].auxDacMask)) != ADI_COMMON_ACT_NO_ACTION) + { + /*Clear the error so that clean up functions execute */ + recoveryAction = adi_common_ErrorClear(&device->common); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while clearing error "); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Release Shared GPIOs if setting of GPIO Input Dir is unsuccessful */ + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, + &sharedResourceArr[0], + numSharedResources, + THIS_FEATURE_ID, + &resourceReleaseStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while releasing shared GPIO pins "); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_ADRV9025_ERR_SHARED_RESOURCE_RELEASE, + ADI_ADRV9025_ACT_ERR_RESET_GPIO, + resourceReleaseStatus, + "Unable to release GPIOs for AuxDACs while attempting to exit due to GPIO dir set error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_ADRV9025_ACT_ERR_RESET_SPI, + gpioAnalogInputOutputMask, + "Unable to set GPIO output direction for AuxDACs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + recoveryAction = adrv9025_CorePdAuxdacBfSet(device, + ADRV9025_BF_CORE, + bfEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while setting enable/disable for AuxDACs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + return device->common.error.newAction; +} + +int32_t adi_adrv9025_AuxDacCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxDacs_e auxDacMask, + adi_adrv9025_AuxDacCfg_t* auxDacConfig) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + adi_adrv9025_AuxDacCfg_t auxDacConfigTmp = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + auxDacConfig); + + /* Check whether selected AuxDAC index is valid */ + if ((auxDacMask != ADI_ADRV9025_AUXDAC0) && (auxDacMask != ADI_ADRV9025_AUXDAC1) && + (auxDacMask != ADI_ADRV9025_AUXDAC2) && (auxDacMask != ADI_ADRV9025_AUXDAC3) && + (auxDacMask != ADI_ADRV9025_AUXDAC4) && (auxDacMask != ADI_ADRV9025_AUXDAC5) && + (auxDacMask != ADI_ADRV9025_AUXDAC6) && (auxDacMask != ADI_ADRV9025_AUXDAC7)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + auxDacMask, + "Invalid AuxDAC index is selected for AuxDAC. Valid AuxDAC indexes are AuxDAC0-7."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Assign auxDacMask to auxDacMask input */ + auxDacConfigTmp.auxDacMask = (uint32_t)auxDacMask; + + /* Read enable bit for selected Tx Channel and AuxDAC */ + recoveryAction = adrv9025_CorePdAuxdacBfGet(device, + ADRV9025_BF_CORE, + &auxDacConfigTmp.enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while reading AuxDACs enabled bits"); + ADI_ERROR_RETURN(device->common.error.newAction); + + auxDacConfigTmp.enable = (~auxDacConfigTmp.enable) & (uint8_t)auxDacMask; + auxDacConfigTmp.enable = (auxDacConfigTmp.enable > 0 ? 1 : 0); + + /* Assign temporary struct content to readback pointer */ + *auxDacConfig = auxDacConfigTmp; + return device->common.error.newAction; +} + +int32_t adi_adrv9025_AuxDacValueSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxDacValue_t auxDacValues[], + uint8_t numberOfCfg) +{ + static const uint32_t ALL_AUXDAC_MASK = (uint32_t)ADI_ADRV9025_AUXDAC0 | (uint32_t)ADI_ADRV9025_AUXDAC1 | + (uint32_t)ADI_ADRV9025_AUXDAC2 | (uint32_t)ADI_ADRV9025_AUXDAC3 | + (uint32_t)ADI_ADRV9025_AUXDAC4 | (uint32_t)ADI_ADRV9025_AUXDAC5 | + (uint32_t)ADI_ADRV9025_AUXDAC6 | (uint32_t)ADI_ADRV9025_AUXDAC7; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + adi_adrv9025_AuxDacs_e auxDacSel = ADI_ADRV9025_AUXDAC0; + + /* Variables to iterate over DAC words to be set */ + uint8_t i = 0; + uint8_t k = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + auxDacValues); + + /* Check that if number of configs is > 0 */ + if (numberOfCfg == 0) + { + /* no valid configs */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + numberOfCfg, + "Invalid number of configurations"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < numberOfCfg; i++) + { + /* Check whether selected AuxDAC index is valid */ + if (((auxDacValues[i].auxDacMask & (~ALL_AUXDAC_MASK)) != 0) || auxDacValues[i].auxDacMask == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + auxDacMask, + "Invalid AuxDAC index is selected for AuxDAC. Valid values are between 1-255."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (k = 0; k < ADI_ADRV9025_MAX_AUXDACS; k++) + { + if (ADRV9025_BF_EQUAL(auxDacValues[i].auxDacMask, + ((uint32_t)1 << (uint32_t)k))) + { + auxDacSel = (adi_adrv9025_AuxDacs_e)((uint8_t)(1 << k)); + + /* Set 12 bit AuxDAC word */ + recoveryAction = adrv9025_AuxDacValueSet(device, + auxDacSel, + auxDacValues[i].dacWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Unable to set 12 bit AuxDAC word"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_AuxDacValueGet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxDacs_e auxDacMask, + adi_adrv9025_AuxDacValue_t* auxDacValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + auxDacValue); + + /* Check whether selected AuxDAC index is valid */ + if ((auxDacMask != ADI_ADRV9025_AUXDAC0) && (auxDacMask != ADI_ADRV9025_AUXDAC1) && + (auxDacMask != ADI_ADRV9025_AUXDAC2) && (auxDacMask != ADI_ADRV9025_AUXDAC3) && + (auxDacMask != ADI_ADRV9025_AUXDAC4) && (auxDacMask != ADI_ADRV9025_AUXDAC5) && + (auxDacMask != ADI_ADRV9025_AUXDAC6) && (auxDacMask != ADI_ADRV9025_AUXDAC7)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + auxDacMask, + "Invalid AuxDAC index is selected for AuxDAC. Valid AuxDAC indexes are AuxDAC0-7."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Assign auxDacMask field from function input */ + auxDacValue->auxDacMask = auxDacMask; + + /* Get 12 bit DAC word from selected AuxDAC */ + if (auxDacMask == ADI_ADRV9025_AUXDAC0) + { + recoveryAction = adrv9025_AnalogTxMemMapAuxdac0BfGet(device, + ADRV9025_BF_ANALOG_TX_CH1, + &auxDacValue->dacWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while reading DAC word for AuxDAC0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (auxDacMask == ADI_ADRV9025_AUXDAC1) + { + recoveryAction = adrv9025_AnalogTxMemMapAuxdac1BfGet(device, + ADRV9025_BF_ANALOG_TX_CH1, + &auxDacValue->dacWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while reading DAC word for AuxDAC1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (auxDacMask == ADI_ADRV9025_AUXDAC2) + { + recoveryAction = adrv9025_AnalogTxMemMapAuxdac2BfGet(device, + ADRV9025_BF_ANALOG_TX_CH1, + &auxDacValue->dacWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while reading DAC word for AuxDAC2"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (auxDacMask == ADI_ADRV9025_AUXDAC3) + { + recoveryAction = adrv9025_AnalogTxMemMapAuxdac3BfGet(device, + ADRV9025_BF_ANALOG_TX_CH1, + &auxDacValue->dacWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while reading DAC word for AuxDAC3"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (auxDacMask == ADI_ADRV9025_AUXDAC4) + { + recoveryAction = adrv9025_AnalogTxMemMapAuxdac0BfGet(device, + ADRV9025_BF_ANALOG_TX_CH2, + &auxDacValue->dacWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while reading DAC word for AuxDAC4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (auxDacMask == ADI_ADRV9025_AUXDAC5) + { + recoveryAction = adrv9025_AnalogTxMemMapAuxdac1BfGet(device, + ADRV9025_BF_ANALOG_TX_CH2, + &auxDacValue->dacWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while reading DAC word for AuxDAC5"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (auxDacMask == ADI_ADRV9025_AUXDAC6) + { + recoveryAction = adrv9025_AnalogTxMemMapAuxdac2BfGet(device, + ADRV9025_BF_ANALOG_TX_CH2, + &auxDacValue->dacWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while reading DAC word for AuxDAC6"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_AnalogTxMemMapAuxdac3BfGet(device, + ADRV9025_BF_ANALOG_TX_CH2, + &auxDacValue->dacWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while reading DAC word for AuxDAC7"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_AuxAdcCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcCfg_t* auxAdcConfig, + uint8_t arraySize) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t i = 0; /* iteration variable */ + + /* variables used for configuration checking */ + uint32_t auxAdcSelectMask = 0; + uint32_t auxAdcSelection = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + auxAdcConfig); + + if ((arraySize > 0u) && (arraySize <= ADI_ADRV9025_AUXADC_NUM)) + { + /* Ensure that no configurations are targeting the same ADCs */ + /* No need to check if arraySize == 1 */ + for (i = 0; i < arraySize; i++) + { +#if ADI_ADRV9025_GPIO_RANGE_CHECK > 0 + /* use one hot encoding to check if multiple configuration structs + * are targeting the same ADC */ + auxAdcSelection = 1u << auxAdcConfig[i].auxAdcSelect; + if ((auxAdcSelection & auxAdcSelectMask) > 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + auxAdcConfig[i].auxAdcSelect, + "More than one ADC configuration is targeting a common ADC"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + auxAdcSelectMask |= auxAdcSelection; + } + + /* Range Check the supplied configuration */ + recoveryAction = adrv9025_AuxAdcCfgRangeCheck(device, + &auxAdcConfig[i]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + auxAdcConfig[i], + "Error while range checking supplied configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + +#endif /* #if ADI_ADRV9025_GPIO_RANGE_CHECK > 0 */ + + /* Configuration is fine, configure ADC */ + recoveryAction = adrv9025_AuxAdcCfgWrite(device, + &auxAdcConfig[i]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + auxAdcConfig[i], + "Error while writing supplied configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + arraySize, + "arraySize is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_AuxAdcCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcSelect_e auxAdcSelect, + adi_adrv9025_AuxAdcCfg_t* auxAdcConfig) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + auxAdcConfig); + + recoveryAction = adrv9025_AuxAdcCfgRead(device, + auxAdcSelect, + auxAdcConfig); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read aux ADC configuration"); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_AuxAdcValueGet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcSelect_e auxAdcSelect, + adi_adrv9025_AuxAdcValue_t* auxAdcValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + auxAdcValue); + + recoveryAction = adrv9025_AuxAdcValueGet(device, + auxAdcSelect, + auxAdcValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to obtain ADC sample"); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_AuxAdcMeasurementStart(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxAdcSelect_e auxAdcSelect) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + recoveryAction = adrv9025_AuxAdcMeasurementStart(device, + auxAdcSelect); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while starting Aux Adc Measurement"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_hal.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_hal.c new file mode 100644 index 0000000..3a42ed1 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_hal.c @@ -0,0 +1,1123 @@ +/** +* \file adi_adrv9025_hal.c +* \brief Contains ADI Transceiver Hardware Abstraction functions +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/* Intermediate platform HAL layer maintained by Analog Devices */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ +#include "adi_adrv9025_user.h" +#include "adi_common_hal.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_error.h" +#include "adi_platform.h" + +#ifdef _RELEASE_BUILD_ + #line __LINE__ "adi_adrv9025_hal.c" +#endif + +int32_t adi_adrv9025_SpiByteWrite(adi_adrv9025_Device_t* device, + uint16_t addr, + uint8_t data) +{ + int32_t halError = 0; + int32_t i = 0; + uint16_t numTxBytes = 0; + uint8_t txData[ADRV9025_SPI_BYTES] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_VARIABLE_LOG(&device->common, + ADI_COMMON_LOG_SPI, + "%s(0x%04X, 0x%02X)", + addr, + data); + + adi_adrv9025_SpiDataPack(device, + &txData[0], + &numTxBytes, + addr, + 0xFF, + data, + ADRV9025_SPI_WRITE_POLARITY); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_ADRV9025_NUMBER_SPI_RETRY; i++) + { + halError = adi_hal_SpiWrite(device->common.devHalInfo, + &txData[0], + numTxBytes); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + (adi_common_ErrSources_e)halError, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI write error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SpiCacheWrite(adi_adrv9025_Device_t* device, + const uint32_t wrCache[], + uint32_t count) +{ + int32_t halError = 0; + uint32_t i = 0; + uint16_t numWrBytes = 0; + uint8_t wrData[ADI_COMMON_HAL_SPIARRAYSIZE] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_ADRV9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + for (i = 0; i < count; i++) + { + ADI_FUNCTION_ENTRY_VARIABLE_LOG(&device->common, + ADI_COMMON_LOG_SPI, + "%s(0x%04X, 0x%02X)", + (uint16_t)(wrCache[i] >> SPI_ADDR_SIZE), + (uint8_t)wrCache[i]); + } + +#endif + + for (i = 0; i < count; i++) + { + adi_adrv9025_SpiDataPack(device, + &wrData[0], + &numWrBytes, + wrCache[i] >> SPI_ADDR_SIZE, + wrCache[i] >> SPI_MASK_SIZE, + wrCache[i], + ADRV9025_SPI_WRITE_POLARITY); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_ADRV9025_NUMBER_SPI_RETRY; i++) + { + halError = adi_hal_SpiWrite(device->common.devHalInfo, + &wrData[0], + numWrBytes); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + (adi_common_ErrSources_e)halError, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI write error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SpiBytesWrite(adi_adrv9025_Device_t* device, + const uint16_t addr[], + const uint8_t data[], + uint32_t count) +{ + int32_t halError = 0; + uint32_t i = 0; + uint16_t numWrBytes = 0; + uint8_t wrData[ADI_COMMON_HAL_SPIARRAYSIZE] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + for (i = 0; i < count; i++) + { + ADI_FUNCTION_ENTRY_VARIABLE_LOG(&device->common, + ADI_COMMON_LOG_SPI, + "%s(0x%04X, 0x%02X)", + addr[i], + data[i]); + } + + ADI_NULL_PTR_RETURN(&device->common, + addr); + + ADI_NULL_PTR_RETURN(&device->common, + data); + + for (i = 0; i < count; i++) + { + adi_adrv9025_SpiDataPack(device, + &wrData[0], + &numWrBytes, + addr[i], + 0xFF, + data[i], + ADRV9025_SPI_WRITE_POLARITY); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_ADRV9025_NUMBER_SPI_RETRY; i++) + { + halError = adi_hal_SpiWrite(device->common.devHalInfo, + &wrData[0], + numWrBytes); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + (adi_common_ErrSources_e)halError, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI write error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SpiDmaWordWrite(adi_adrv9025_Device_t* device, + const uint32_t data, + uint16_t startAddress) +{ + static const uint8_t FULL_WORD_SIZE = 4; + int32_t halError = 0; + uint8_t i = 0; + uint8_t byteToWrite = 0; + uint16_t numWrBytes = 0; + uint8_t wrData[ADI_COMMON_HAL_SPIARRAYSIZE] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + for (i = 0; i < FULL_WORD_SIZE; i++) + { + byteToWrite = (uint8_t)(data >> (uint32_t)((FULL_WORD_SIZE - 1 - i) * 8)); + ADI_FUNCTION_ENTRY_VARIABLE_LOG(&device->common, + ADI_COMMON_LOG_SPI, + "%s(0x%04X, 0x%02X)", + startAddress, + byteToWrite); + + adi_adrv9025_SpiDataPack(device, + &wrData[0], + &numWrBytes, + startAddress++, + 0xFF, + byteToWrite, + ADRV9025_SPI_WRITE_POLARITY); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + //TODO make macro + for (i = 0; i < ADI_ADRV9025_NUMBER_SPI_RETRY; i++) + { + halError = adi_hal_SpiWrite(device->common.devHalInfo, + &wrData[0], + numWrBytes); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + halError, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI write error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SpiWriteStreamWithCustomHalFunction(adi_adrv9025_Device_t* device, + const uint8_t data[], + uint32_t count, + uint16_t address) +{ + static const uint8_t NUM_OF_BYTES_OF_ADDRESS = 2; + static const uint8_t NUM_OF_BYTES_OF_DATA_PER_STREAM = 4; + int32_t halError = 0; + uint8_t i = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, + data); + + if (adi_hal_CustomSpiStreamWrite == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + adi_hal_CustomSpiStreamWrite, + "adi_hal_CustomSpiStreamWrite should point to a user defined hal layer function prior calling this function\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if (device->spiSettings.enSpiStreaming != 1) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->spiSettings.enSpiStreaming, + "Please enable spi streaming prior calling this function\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_ADRV9025_NUMBER_SPI_RETRY; i++) + { + halError = adi_hal_CustomSpiStreamWrite(device->common.devHalInfo, + address, + data, + count, + NUM_OF_BYTES_OF_ADDRESS, + NUM_OF_BYTES_OF_DATA_PER_STREAM); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + halError, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI write error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_SpiReadStreamWithCustomHalFunction(adi_adrv9025_Device_t* device, + uint8_t readData[], + uint32_t count, + uint16_t address) +{ + static const uint8_t NUM_OF_BYTES_OF_ADDRESS = 2; + static const uint8_t NUM_OF_BYTES_OF_DATA_PER_STREAM = 4; + int32_t halError = 0; + uint8_t i = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, + readData); + + if (adi_hal_CustomSpiStreamRead == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + adi_hal_CustomSpiStreamRead, + "adi_hal_CustomSpiStreamRead should point to a user defined hal layer function prior calling this function\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if (device->spiSettings.enSpiStreaming != 1) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->spiSettings.enSpiStreaming, + "Please enable spi streaming prior calling this function\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_ADRV9025_NUMBER_SPI_RETRY; i++) + { + halError = adi_hal_CustomSpiStreamRead(device->common.devHalInfo, + address, + readData, + count, + NUM_OF_BYTES_OF_ADDRESS, + NUM_OF_BYTES_OF_DATA_PER_STREAM); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + halError, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI read error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_SpiDmaWordWriteStream(adi_adrv9025_Device_t* device, + const uint8_t data[], + uint32_t count, + uint16_t address) +{ +#define NUM_OF_BYTES_TO_WRITE 6 + static const uint8_t WORD_LENGTH = 4; + + int32_t halError = 0; + uint8_t i = 0; + uint32_t j = 0; + uint8_t dataToWrite[NUM_OF_BYTES_TO_WRITE] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, + data); + + if (device->spiSettings.enSpiStreaming != 1) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->spiSettings.enSpiStreaming, + "Please enable spi streaming prior calling this function\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((count % WORD_LENGTH) != 0) || (count == 0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + count, + "This function only supports full dma word transfers \n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + dataToWrite[0] = (uint8_t)((address >> 8) & 0x007F) | (uint8_t)((ADRV9025_SPI_WRITE_POLARITY & 0x01) << 7); + dataToWrite[1] = (uint8_t)(address & 0x00FF); + for (j = 0; j < count; j += WORD_LENGTH) + { + dataToWrite[2] = data[j + 3]; + dataToWrite[3] = data[j + 2]; + dataToWrite[4] = data[j + 1]; + dataToWrite[5] = data[j + 0]; + for (i = 0; i < ADI_ADRV9025_NUMBER_SPI_RETRY; i++) + { + halError = adi_hal_SpiWrite(device->common.devHalInfo, + &dataToWrite[0], + NUM_OF_BYTES_TO_WRITE); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + halError, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI write error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SpiDmaWordReadStream(adi_adrv9025_Device_t* device, + uint8_t readData[], + uint32_t count, + uint16_t address) +{ +#define NUM_OF_BYTES_TO_READ 6 + static const uint8_t WORD_LENGTH = 4; + + int32_t halError = 0; + uint8_t i = 0; + uint32_t j = 0; + uint8_t dataToWrite[NUM_OF_BYTES_TO_READ] = {0}; + uint8_t dataToRead[NUM_OF_BYTES_TO_READ] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, + readData); + + if (device->spiSettings.enSpiStreaming != 1) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->spiSettings.enSpiStreaming, + "Please enable spi streaming prior calling this function\n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((count % WORD_LENGTH) != 0) || (count == 0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + count, + "This function only supports full dma word transfers \n"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + dataToWrite[0] = (uint8_t)((address >> 8) & 0x007F) | (uint8_t)((~ADRV9025_SPI_WRITE_POLARITY & 0x01) << 7); + dataToWrite[1] = (uint8_t)(address & 0x00FF); + for (j = 0; j < count; j += WORD_LENGTH) + { + for (i = 0; i < ADI_ADRV9025_NUMBER_SPI_RETRY; i++) + { + halError = adi_hal_SpiRead(device->common.devHalInfo, + &dataToWrite[0], + &dataToRead[0], + NUM_OF_BYTES_TO_READ); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + halError, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI write error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + readData[j + 0] = dataToRead[5]; + readData[j + 1] = dataToRead[4]; + readData[j + 2] = dataToRead[3]; + readData[j + 3] = dataToRead[2]; + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SpiByteRead(adi_adrv9025_Device_t* device, + uint16_t addr, + uint8_t* readData) +{ + int32_t halError = 0; + int32_t i = 0; + uint16_t numWrBytes = 0; + uint8_t wrData[ADRV9025_SPI_BYTES] = {0}; + uint8_t regVal = 0; + uint8_t regData[ADRV9025_SPI_BYTES] = {0}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, + readData); + + if (device->common.cacheInfo.wrOnly == ADI_TRUE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->common.cacheInfo.wrOnly, + "Read Operations cannot be called when wrOnly is enabled"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + adi_adrv9025_SpiDataPack(device, + &wrData[0], + &numWrBytes, + addr, + 0xFF, + regVal, + ~ADRV9025_SPI_WRITE_POLARITY); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_ADRV9025_NUMBER_SPI_RETRY; i++) + { + halError = (adi_common_hal_Err_e)adi_hal_SpiRead(device->common.devHalInfo, + &wrData[0], + ®Data[0], + numWrBytes); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + (adi_common_ErrSources_e)halError, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI write error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + *readData = regData[2]; + + ADI_FUNCTION_ENTRY_VARIABLE_LOG(&device->common, + ADI_COMMON_LOG_SPI, + "%s(0x%04X, 0x%02X)", + addr, + *readData); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SpiBytesRead(adi_adrv9025_Device_t* device, + const uint16_t addr[], + uint8_t readData[], + uint32_t count) +{ + uint32_t i = 0; + uint32_t j = 0; + int32_t halError = 0; + uint8_t wrData[ADI_COMMON_HAL_SPIARRAYSIZE] = {0}; + uint8_t rdData[ADI_COMMON_HAL_SPIARRAYSIZE] = {0}; + uint16_t numWrBytes = 0; + uint8_t regVal = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, + addr); + + ADI_NULL_PTR_RETURN(&device->common, + readData); + + if (device->common.cacheInfo.wrOnly == ADI_TRUE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->common.cacheInfo.wrOnly, + "Read Operations cannot be called when wrOnly is enabled"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < count; i++) + { + adi_adrv9025_SpiDataPack(device, + &wrData[0], + &numWrBytes, + addr[i], + 0xFF, + regVal, + ~ADRV9025_SPI_WRITE_POLARITY); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (j = 0; j < ADI_ADRV9025_NUMBER_SPI_RETRY; j++) + { + halError = adi_hal_SpiRead(device->common.devHalInfo, + &wrData[0], + &rdData[0], + numWrBytes); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + + for (i = 0; i < count; i++) + { + ADI_FUNCTION_ENTRY_VARIABLE_LOG(&device->common, + ADI_COMMON_LOG_SPI, + "%s(0x%04X, 0x%02X)", + addr[i], + rdData[(i * 3) + 2]); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + (adi_common_ErrSources_e)halError, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI write error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < count; i++) + { + readData[i] = rdData[(i * 3) + 2]; + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SpiDmaWordRead(adi_adrv9025_Device_t* device, + uint32_t* data, + uint16_t startAddress) +{ + static const uint8_t FULL_WORD_SIZE = 4; + uint32_t i = 0; + uint32_t j = 0; + int32_t halError = 0; + uint8_t wrData[ADI_COMMON_HAL_SPIARRAYSIZE] = {0}; + uint8_t rdData[ADI_COMMON_HAL_SPIARRAYSIZE] = {0}; + uint16_t numWrBytes = 0; + uint8_t regVal = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, + data); + + for (i = 0; i < FULL_WORD_SIZE; i++) + { + adi_adrv9025_SpiDataPack(device, + &wrData[0], + &numWrBytes, + startAddress++, + 0xFF, + regVal, + ~ADRV9025_SPI_WRITE_POLARITY); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (j = 0; j < ADI_ADRV9025_NUMBER_SPI_RETRY; j++) + { + halError = adi_hal_SpiRead(device->common.devHalInfo, + &wrData[0], + &rdData[0], + numWrBytes); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + + /* Revert the value of startAddress to its original value */ + startAddress -= FULL_WORD_SIZE; + for (i = 0; i < FULL_WORD_SIZE; i++) + { + ADI_FUNCTION_ENTRY_VARIABLE_LOG(&device->common, + ADI_COMMON_LOG_SPI, + "%s(0x%04X, 0x%02X)", + startAddress++, + rdData[(i * 3) + 2]); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + halError, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI read error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + *data = 0; + for (i = 0; i < FULL_WORD_SIZE; i++) + { + *data |= ((uint32_t)rdData[(i * 3) + 2] << ((FULL_WORD_SIZE - 1 - i) * 8)); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SpiCacheRead(adi_adrv9025_Device_t* device, + const uint32_t rdCache[], + uint8_t readData[], + uint32_t count) +{ + uint32_t i = 0; + uint32_t j = 0; + int32_t halError = 0; + uint8_t wrData[ADI_COMMON_HAL_SPIARRAYSIZE] = {0}; + uint8_t rdData[ADI_COMMON_HAL_SPIARRAYSIZE] = {0}; + uint16_t numWrBytes = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, + rdCache); + + ADI_NULL_PTR_RETURN(&device->common, + readData); + + if (device->common.cacheInfo.wrOnly == ADI_TRUE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->common.cacheInfo.wrOnly, + "Read Operations cannot be called when wrOnly is enabled"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < count; i++) + { + adi_adrv9025_SpiDataPack(device, + &wrData[0], + &numWrBytes, + rdCache[i] >> SPI_ADDR_SIZE, + 0xFF, + 0, + ~ADRV9025_SPI_WRITE_POLARITY); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (j = 0; j < ADI_ADRV9025_NUMBER_SPI_RETRY; j++) + { + halError = adi_hal_SpiRead(device->common.devHalInfo, + &wrData[0], + &readData[0], + numWrBytes); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + + for (i = 0; i < count; i++) + { + ADI_FUNCTION_ENTRY_VARIABLE_LOG(&device->common, + ADI_COMMON_LOG_SPI, + "%s(0x%04X, 0x%02X)", + wrData[i], + rdData[(i * 3) + 2]); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + (adi_common_ErrSources_e)halError, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI write error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SpiFieldWrite(adi_adrv9025_Device_t* device, + uint16_t addr, + uint8_t fieldVal, + uint8_t mask, + uint8_t startBit) +{ + int32_t halError = 0; + uint16_t numWrBytes = 0; + uint8_t regVal = ((fieldVal << startBit) & mask); + uint8_t newRegVal = 0; + + uint8_t registerVal[ADRV9025_SPI_BYTES] = {0}; + uint8_t wrData[ADRV9025_HW_RMW_BYTES] = {0}; + uint8_t i = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_VARIABLE_LOG(&device->common, + ADI_COMMON_LOG_SPI, + "%s(0x%04X, 0x%02X)", + addr, + regVal); + + if (device->common.cacheInfo.HW_RMW_Enabled) + { + /* Write with mask(with 12 byte packages) when HW_RMW_Enabled is available */ + adi_adrv9025_SpiDataPack(device, + &wrData[0], + &numWrBytes, + addr, + mask, + regVal, + ADRV9025_SPI_WRITE_POLARITY); + ADI_ERROR_RETURN(device->common.error.newAction); + for (i = 0; i < ADI_ADRV9025_NUMBER_SPI_RETRY; i++) + { + halError = adi_hal_SpiWrite(device->common.devHalInfo, + &wrData[0], + numWrBytes); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + } + else + { + /* Generate an error if wrOnly is TRUE, since rest of the code will perform manual read/modify/write */ + if (device->common.cacheInfo.wrOnly == ADI_TRUE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->common.cacheInfo.wrOnly, + "Cannot write to spi field when wrOnly is true and HW_RMW is not enabled"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + adi_adrv9025_SpiDataPack(device, + &wrData[0], + &numWrBytes, + addr, + 0xFF, + regVal, + ~ADRV9025_SPI_WRITE_POLARITY); + ADI_ERROR_RETURN(device->common.error.newAction); + for (i = 0; i < ADI_ADRV9025_NUMBER_SPI_RETRY; i++) + { + halError = adi_hal_SpiRead(device->common.devHalInfo, + &wrData[0], + ®isterVal[0], + numWrBytes); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + (adi_common_ErrSources_e)halError, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI read error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + newRegVal = (registerVal[2] & ~mask) | (regVal & mask); + numWrBytes = 0; + + adi_adrv9025_SpiDataPack(device, + &wrData[0], + &numWrBytes, + addr, + 0xFF, + newRegVal, + ADRV9025_SPI_WRITE_POLARITY); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_ADRV9025_NUMBER_SPI_RETRY; i++) + { + halError = adi_hal_SpiWrite(device->common.devHalInfo, + &wrData[0], + numWrBytes); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + (adi_common_ErrSources_e)halError, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "SPI write error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SpiFieldRead(adi_adrv9025_Device_t* device, + uint16_t addr, + uint8_t* fieldVal, + uint8_t mask, + uint8_t startBit) +{ + /* only use if caching is off */ + int32_t halError = 0; + uint16_t numWrBytes = 0; + uint8_t wrData[8] = {0}; + uint8_t rdData[8] = {0}; + uint8_t regVal = 0; + uint8_t i = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, + fieldVal); + + if (device->common.cacheInfo.wrOnly == ADI_TRUE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->common.cacheInfo.wrOnly, + "Read Operations cannot be called when wrOnly is enabled"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + adi_adrv9025_SpiDataPack(device, + &wrData[0], + &numWrBytes, + addr, + 0xFF, + regVal, + ~ADRV9025_SPI_WRITE_POLARITY); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_ADRV9025_NUMBER_SPI_RETRY; i++) + { + halError = adi_hal_SpiRead(device->common.devHalInfo, + &wrData[0], + &rdData[0], + numWrBytes); + if (halError == ADI_COMMON_HAL_OK) + { + break; + } + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + (adi_common_ErrSources_e)halError, + ADI_ADRV9025_ACT_ERR_RESET_SPI, + NULL, + "SPI write error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + regVal = rdData[2]; + startBit = startBit & 0x0F; + + *fieldVal = (uint8_t)((regVal & mask) >> startBit); + + ADI_FUNCTION_ENTRY_VARIABLE_LOG(&device->common, + ADI_COMMON_LOG_SPI, + "%s(0x%04X, 0x%02X)", + addr, + regVal); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SpiDataPack(adi_adrv9025_Device_t* device, + uint8_t* wrData, + uint16_t* numWrBytes, + uint16_t addr, + uint8_t mask, + uint8_t data, + uint8_t writeFlag) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API_PRIV); + + ADI_NULL_PTR_RETURN(&device->common, + wrData); + + ADI_NULL_PTR_RETURN(&device->common, + numWrBytes); + + if (mask == 0xFF) + { + /* if the mask is 0xFF then the entire 8 bits is being written to the + register and so no masking is required and the operation can be + achieved using 3 bytes*/ + if ((*numWrBytes + ADRV9025_SPI_BYTES) > ADI_COMMON_HAL_SPIARRAYSIZE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + ADRV9025HAL_BUFFER_OVERFLOW, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "Buffer size Exceeded error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + wrData[(*numWrBytes)++] = (uint8_t)(((writeFlag & 0x01) << 7) | ((addr >> 8) & 0x7F)); + wrData[(*numWrBytes)++] = (uint8_t)(addr); + /* coverty will trigger an error which is ok in this case. */ + wrData[(*numWrBytes)++] = (uint8_t)data; + } + else + { + if (device->common.cacheInfo.HW_RMW_Enabled == ADI_FALSE) + { + /* Generate an error if HW_RMW is not enabled yet */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_ADI_HAL, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->common.cacheInfo.HW_RMW_Enabled, + "Cannot use HW_RMW functionality to write a field in Spi register because HW_RMW_Enabled is not available"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((*numWrBytes + ADRV9025_HW_RMW_BYTES) > ADI_COMMON_HAL_SPIARRAYSIZE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + ADRV9025HAL_BUFFER_OVERFLOW, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "Buffer size Exceeded error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* pack the low address byte*/ + wrData[(*numWrBytes)++] = (uint8_t)(ADRV9025_HW_RMW_LO_ADDR >> 8); + wrData[(*numWrBytes)++] = (uint8_t)(ADRV9025_HW_RMW_LO_ADDR); + wrData[(*numWrBytes)++] = (uint8_t)addr; + + /* pack the high address byte*/ + wrData[(*numWrBytes)++] = (uint8_t)(ADRV9025_HW_RMW_HI_ADDR >> 8); + wrData[(*numWrBytes)++] = (uint8_t)(ADRV9025_HW_RMW_HI_ADDR); + wrData[(*numWrBytes)++] = (uint8_t)(addr >> 8); + + /* pack the mask byte*/ + wrData[(*numWrBytes)++] = (uint8_t)(ADRV9025_HW_RMW_MASK >> 8); + wrData[(*numWrBytes)++] = (uint8_t)(ADRV9025_HW_RMW_MASK); + wrData[(*numWrBytes)++] = (uint8_t)mask; + + /* pack the mask byte*/ + wrData[(*numWrBytes)++] = (uint8_t)(ADRV9025_HW_RMW_DATA >> 8); + wrData[(*numWrBytes)++] = (uint8_t)(ADRV9025_HW_RMW_DATA); + /*coverty will trigger an error which is ok in this case.*/ + wrData[(*numWrBytes)++] = (uint8_t)data; + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_HwVerify(adi_adrv9025_Device_t *device) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API_PRIV); + + return adi_common_hal_HwVerify(&device->common); +} + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_radioctrl.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_radioctrl.c new file mode 100644 index 0000000..f821984 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_radioctrl.c @@ -0,0 +1,3070 @@ +/** +* \file adi_adrv9025_radioctrl.c +* \brief Contains features related function implementation defined in +* adi_adrv9025_radioctrl.h +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "adi_adrv9025_radioctrl.h" +#include "adi_adrv9025_cals.h" +#include "adi_adrv9025_cpu.h" +#include "adi_adrv9025_gpio.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_error.h" +#include "adi_adrv9025.h" +#include "adi_adrv9025_arm.h" +#include "adi_adrv9025_rx.h" +#include "adi_adrv9025_tx.h" +#include "../../private/include/adrv9025_radioctrl.h" +#include "../../private/include/adrv9025_init.h" +#include "../../private/include/adrv9025_cpu.h" +#include "../../private/include/adrv9025_cpu_macros.h" +#include "../../private/include/adrv9025_reg_addr_macros.h" +#include "../../private/include/adrv9025_bf_pll_mem_map.h" +#include "../../private/include/adrv9025_shared_resource_manager.h" + +#ifdef _RELEASE_BUILD_ + #line __LINE__ "adi_adrv9025_radioctrl.c" +#endif + +/**************************************************************************** + * Initialization functions + **************************************************************************** + */ + +static void adrv9025_BinaryImageInfoGet(adi_adrv9025_Device_t* device, + const uint8_t binary[], + uint16_t* binaryImageSize, + uint16_t* binaryImageOffset) +{ + UNUSED_PARA(device); + /* populating variables from binary array */ + *binaryImageSize = ((((uint16_t)binary[1]) << 8) | ((uint16_t)binary[0])); + *binaryImageOffset = ((((uint16_t)binary[3]) << 8) | (uint16_t)(binary[2])); +} + +static void adrv9025_BinaryParamsGetBaseAddr(adi_adrv9025_Device_t* device, + const uint8_t binary[], + uint32_t* word) +{ + UNUSED_PARA(device); + /* populating variables from binary array */ + *word = (((uint32_t)binary[3]) << 24) | (((uint32_t)binary[2]) << 16) | (((uint32_t)binary[1]) << 8) | (uint32_t)(binary[0]); +} + +static void adrv9025_BinaryParamsGetNumberStreamImageSize(adi_adrv9025_Device_t* device, + const uint8_t binary[], + uint8_t* numberStreams, + uint32_t* imageSize) +{ + UNUSED_PARA(device); + *numberStreams = binary[0]; + *imageSize = (((uint32_t)binary[3]) << 8) | (uint32_t)(binary[2]); +} + +int32_t adi_adrv9025_StreamImageWrite(adi_adrv9025_Device_t* device, + uint32_t byteOffset, + uint8_t binary[], + uint32_t byteCount) +{ + uint16_t binaryImageSize = 0; + uint16_t binaryImageOffset = 0; + uint32_t i = 0; + uint32_t addr = 0; + uint32_t word1 = 0; + uint32_t binOffset = 0; + uint8_t streamCtl = 0; + uint8_t byte1 = 0; + uint32_t imageSize = 0; + uint32_t imageOffset = 0; + uint8_t mainStreamBankSel = 0; + uint32_t streamAddr[] = { ADRV9025_ADDR_MAIN_STREAM_CTL_OFFSET, + ADRV9025_ADDR_TX0_STREAM_CTL_OFFSET, + ADRV9025_ADDR_TX1_STREAM_CTL_OFFSET, + ADRV9025_ADDR_TX2_STREAM_CTL_OFFSET, + ADRV9025_ADDR_TX3_STREAM_CTL_OFFSET, + ADRV9025_ADDR_RX0_STREAM_CTL_OFFSET, + ADRV9025_ADDR_RX1_STREAM_CTL_OFFSET, + ADRV9025_ADDR_RX2_STREAM_CTL_OFFSET, + ADRV9025_ADDR_RX3_STREAM_CTL_OFFSET, + ADRV9025_ADDR_ORX0_STREAM_CTL_OFFSET, + ADRV9025_ADDR_ORX1_STREAM_CTL_OFFSET + }; + + uint8_t streamControlDefaultVal[] = {0x80, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xFC, 0xFC}; + +#ifdef ADRV9025_INIT_DEBUG + static const char * imageName[] = { "MAIN_STREAM", "TX0_STREAM", "TX1_STREAM","TX2_STREAM","TX3_STREAM", + "RX0_STREAM","RX1_STREAM","RX2_STREAM","RX3_STREAM", "ORX0_STREAM", "ORX1_STREAM" }; +#endif + static const uint8_t MIN_BYTECOUNT = 68; + static const uint8_t MAIN_IMAGE_OFFSET = 64; + + /* Arm stream download order: main, tx1/2/3/4, rx1/2/3/4, orx12/34 */ + static const uint32_t streamChannel[] = { + 0xFFFFFFFF, + ADI_ADRV9025_TX1 << ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET, + ADI_ADRV9025_TX2 << ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET, + ADI_ADRV9025_TX3 << ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET, + ADI_ADRV9025_TX4 << ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET, + ADI_ADRV9025_RX1, + ADI_ADRV9025_RX2, + ADI_ADRV9025_RX3, + ADI_ADRV9025_RX4, + (ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2 | ADI_ADRV9025_LB12), + (ADI_ADRV9025_ORX3 | ADI_ADRV9025_ORX4 | ADI_ADRV9025_LB34) + }; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + binary); + + ADRV9025_BUGINFO(__FUNCTION__); + + if ((byteCount % 4) > 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + byteCount, + "Invalid byteCount. Must be multiple of 4."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((byteOffset % 4) > 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + byteCount, + "Invalid byteOffset. Must be multiple of 4."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (byteOffset == 0) + { + if (byteCount < MIN_BYTECOUNT) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + byteCount, + "Invalid byteCount. Must be 68 or greater."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADRV9025_STREAM_MAX; i++) + { + adrv9025_BinaryImageInfoGet(device, + &binary[12 + i * 4], + &binaryImageSize, + &binaryImageOffset); + device->devStateInfo.chunkStreamImageSize[i] = binaryImageSize; + device->devStateInfo.chunkStreamImageOffset[i] = binaryImageOffset; +#ifdef ADRV9025_INIT_DEBUG + ADRV9025_BUGINFO(imageName[i]); + ADRV9025_BUGINFO_NUM("binaryImageOffset", (uint32_t)binaryImageOffset); + ADRV9025_BUGINFO_NUM("binaryImageSize", (uint32_t)binaryImageSize); +#endif + } + + device->devStateInfo.currentStreamImageIndex = 0; + device->devStateInfo.currentStreamBinBaseAddr = 0; + device->devStateInfo.currentStreamBaseAddr = 0; + device->devStateInfo.currentStreamImageSize = 0; + device->devStateInfo.currentStreamNumberStreams = 0; + } + + for (i = device->devStateInfo.currentStreamImageIndex; i < ADRV9025_STREAM_MAX; i++) + { +#ifdef ADRV9025_INIT_DEBUG + ADRV9025_BUGINFO(imageName[i]); + ADRV9025_BUGINFO_NUM("binary", (uint32_t)binary); + ADRV9025_BUGINFO_NUM("byteCount", (uint32_t)byteCount); +#endif + imageOffset = device->devStateInfo.chunkStreamImageOffset[i]; + if (i == 0) + { + imageOffset = MAIN_IMAGE_OFFSET; + } + if ((byteOffset <= imageOffset) && + ((byteOffset + byteCount) >= imageOffset + 4)) + { + binOffset = imageOffset - byteOffset; + adrv9025_BinaryParamsGetBaseAddr(device, + &binary[binOffset], + &word1); + device->devStateInfo.currentStreamBinBaseAddr = word1; + device->devStateInfo.currentStreamImageSize = device->devStateInfo.chunkStreamImageSize[i]; + } + + if ((byteOffset <= imageOffset + 4) && + ((byteOffset + byteCount) >= imageOffset + 8)) + { + binOffset = imageOffset + 4 - byteOffset; + adrv9025_BinaryParamsGetBaseAddr(device, + &binary[binOffset], + &word1); + device->devStateInfo.currentStreamBaseAddr = word1; + } + + if ((byteOffset <= imageOffset + 8) && + ((byteOffset + byteCount) >= imageOffset + 12)) + { + binOffset = imageOffset + 8 - byteOffset; + adrv9025_BinaryParamsGetNumberStreamImageSize(device, + &binary[binOffset], + &byte1, + &word1); + device->devStateInfo.currentStreamNumberStreams = byte1; + //device->devStateInfo.chunkImageSize = word1; + } + + if ((device->devStateInfo.currentStreamBinBaseAddr > 0) && + (device->devStateInfo.currentStreamImageSize > 0)) + { + addr = streamAddr[i]; + + if (device->devStateInfo.currentStreamImageSize == device->devStateInfo.chunkStreamImageSize[i]) + { + if ((device->devStateInfo.initializedChannels & streamChannel[i]) > 0) + { + streamCtl = streamControlDefaultVal[i] | ADRV9025_STREAM_RESET; + ADRV9025_SPIWRITEBYTE("STREAM_CTL", + addr, + streamCtl); + } + } + + /* 3. Load the stream image to memory, starting at the memory address specified by Stream_binary_base. */ + if (byteCount >= device->devStateInfo.currentStreamImageSize) + { + imageSize = device->devStateInfo.currentStreamImageSize; + } + else + { + imageSize = byteCount; + } + + if ((device->devStateInfo.initializedChannels & streamChannel[i]) > 0) + { + adrv9025_CpuDmaMemWrite(device, + device->devStateInfo.currentStreamBinBaseAddr, + &binary[0], + imageSize, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + byteCount -= imageSize; + byteOffset += imageSize; + binary += imageSize; + device->devStateInfo.currentStreamImageSize -= imageSize; + device->devStateInfo.currentStreamBinBaseAddr += imageSize; + + if (device->devStateInfo.currentStreamImageSize == 0) + { + if ((device->devStateInfo.initializedChannels & streamChannel[i]) > 0) + { + /* 4. Populate registers(stream_base_byte0) and (stream_base_byte1)with the lower 16 bits of the Stream_base. */ + ADRV9025_SPIWRITEBYTE("STREAM_BASE_BYTE0", + addr + ADRV9025_STREAM_BASE_BYTE0_OFFSET, + (uint8_t)(device->devStateInfo.currentStreamBaseAddr)); + + ADRV9025_SPIWRITEBYTE("STREAM_BASE_BYTE1", + addr + ADRV9025_STREAM_BASE_BYTE1_OFFSET, + (uint8_t)(device->devStateInfo.currentStreamBaseAddr >> 8)); + + /* 5. Populate register (last_stream_num)with the No_of_streams value. */ + ADRV9025_SPIWRITEBYTE("LAST_STREAM_NUMBER", + addr + ADRV9025_LAST_STREAM_NUMBER_OFFSET, + device->devStateInfo.currentStreamNumberStreams - 1); + + /* 6. Clear bit D0 in register (stream_reset) */ + if (i == 0) + { + /* Set memory bank select for main stream processor */ + if ((device->devStateInfo.currentStreamBaseAddr >= 0x20018000) && + (device->devStateInfo.currentStreamBaseAddr <= 0x2004FFFF)) + { + mainStreamBankSel = (device->devStateInfo.currentStreamBaseAddr >> 16) & 0x07; + + /* Set memory bank select for main stream processor */ + streamCtl = (mainStreamBankSel << 5) & ~ADRV9025_STREAM_RESET; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + mainStreamBankSel, + "Main Stream Processor image has invalid memory location"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else + { + /* Just clear reset bit on other channel processors */ + streamCtl = streamControlDefaultVal[i] & ~ADRV9025_STREAM_RESET; + } + + ADRV9025_SPIWRITEBYTE("STREAM_CTL", + addr, + streamCtl); + } + + device->devStateInfo.currentStreamImageIndex++; + device->devStateInfo.currentStreamBinBaseAddr = 0; + device->devStateInfo.currentStreamBaseAddr = 0; + device->devStateInfo.currentStreamImageSize = 0; + device->devStateInfo.currentStreamNumberStreams = 0; + } + } + else + { + break; + } + + if (byteCount == 0) + { + break; + } + } + + if (device->devStateInfo.currentStreamImageIndex == ADRV9025_STREAM_MAX) + { + device->devStateInfo.devState = (adi_adrv9025_ApiStates_e)(device->devStateInfo.devState | ADI_ADRV9025_STATE_STREAMLOADED); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_ArmGpioPinsSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_ArmGpioCfg_t* armGpio) +{ + static const uint8_t SIGNAL_ID[] = { ADRV9025_CPU_ORX1_TX_SEL0_SIGNALID, + ADRV9025_CPU_ORX1_TX_SEL1_SIGNALID, + ADRV9025_CPU_ORX2_TX_SEL0_SIGNALID, + ADRV9025_CPU_ORX2_TX_SEL1_SIGNALID, + ADRV9025_CPU_ORX3_TX_SEL0_SIGNALID, + ADRV9025_CPU_ORX3_TX_SEL1_SIGNALID, + ADRV9025_CPU_ORX4_TX_SEL0_SIGNALID, + ADRV9025_CPU_ORX4_TX_SEL1_SIGNALID, + ADRV9025_CPU_TX12CAL_ENA_SIGNALID, + ADRV9025_CPU_TX34CAL_ENA_SIGNALID, + ADRV9025_CPU_CAL_UPDATE0_SIGNALID, + ADRV9025_CPU_CAL_UPDATE1_SIGNALID, + ADRV9025_CPU_CAL_UPDATE2_SIGNALID, + ADRV9025_CPU_RF_PLL_FREQ_HOP_SIGNALID + }; + + uint8_t signalIndex = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + armGpio); + + for (signalIndex = 0; signalIndex < sizeof(SIGNAL_ID); signalIndex++) + { + switch (SIGNAL_ID[signalIndex]) + { + case(ADRV9025_CPU_ORX1_TX_SEL0_SIGNALID): + { + if ((armGpio->orx1TxSel0Pin.enable > 0) && + (armGpio->orx1TxSel0Pin.gpioPinSel > ADI_ADRV9025_GPIO_18)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armGpio->orx1TxSel0Pin.gpioPinSel, + "Invalid Gpio Pin encountered for signal ORX1_TX_SEL0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + break; + } + case(ADRV9025_CPU_ORX1_TX_SEL1_SIGNALID): + { + if ((armGpio->orx1TxSel1Pin.enable > 0) && + (armGpio->orx1TxSel1Pin.gpioPinSel > ADI_ADRV9025_GPIO_18)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armGpio->orx1TxSel1Pin.gpioPinSel, + "Invalid Gpio Pin encountered for signal ORX1_TX_SEL1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + case(ADRV9025_CPU_ORX2_TX_SEL0_SIGNALID): + { + if ((armGpio->orx2TxSel0Pin.enable > 0) && + (armGpio->orx2TxSel0Pin.gpioPinSel > ADI_ADRV9025_GPIO_18)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armGpio->orx2TxSel0Pin.gpioPinSel, + "Invalid Gpio Pin encountered for signal ORX2_TX_SEL0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + case(ADRV9025_CPU_ORX2_TX_SEL1_SIGNALID): + { + if ((armGpio->orx2TxSel1Pin.enable > 0) && + (armGpio->orx2TxSel1Pin.gpioPinSel > ADI_ADRV9025_GPIO_18)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armGpio->orx2TxSel1Pin.gpioPinSel, + "Invalid Gpio Pin encountered for signal ORX2_TX_SEL1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + case(ADRV9025_CPU_ORX3_TX_SEL0_SIGNALID): + { + if ((armGpio->orx3TxSel0Pin.enable > 0) && + (armGpio->orx3TxSel0Pin.gpioPinSel > ADI_ADRV9025_GPIO_18)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armGpio->orx3TxSel0Pin.gpioPinSel, + "Invalid Gpio Pin encountered for signal ORX3_TX_SEL0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + case(ADRV9025_CPU_ORX3_TX_SEL1_SIGNALID): + { + if ((armGpio->orx3TxSel1Pin.enable > 0) && + (armGpio->orx3TxSel1Pin.gpioPinSel > ADI_ADRV9025_GPIO_18)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armGpio->orx3TxSel1Pin.gpioPinSel, + "Invalid Gpio Pin encountered for signal ORX3_TX_SEL1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + case(ADRV9025_CPU_ORX4_TX_SEL0_SIGNALID): + { + if ((armGpio->orx4TxSel0Pin.enable > 0) && + (armGpio->orx4TxSel0Pin.gpioPinSel > ADI_ADRV9025_GPIO_18)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armGpio->orx4TxSel0Pin.gpioPinSel, + "Invalid Gpio Pin encountered for signal ORX4_TX_SEL0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + case(ADRV9025_CPU_ORX4_TX_SEL1_SIGNALID): + { + if ((armGpio->orx4TxSel1Pin.enable > 0) && + (armGpio->orx4TxSel1Pin.gpioPinSel > ADI_ADRV9025_GPIO_18)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armGpio->orx4TxSel1Pin.gpioPinSel, + "Invalid Gpio Pin encountered for signal ORX4_TX_SEL1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + case(ADRV9025_CPU_TX12CAL_ENA_SIGNALID): + { + if ((armGpio->tx12CalEnPin.enable > 0) && + (armGpio->tx12CalEnPin.gpioPinSel > ADI_ADRV9025_GPIO_18)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armGpio->tx12CalEnPin.gpioPinSel, + "Invalid Gpio Pin encountered for signal TX12CAL_ENA"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + case(ADRV9025_CPU_TX34CAL_ENA_SIGNALID): + { + if ((armGpio->tx34CalEnPin.enable > 0) && + (armGpio->tx34CalEnPin.gpioPinSel > ADI_ADRV9025_GPIO_18)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armGpio->tx34CalEnPin.gpioPinSel, + "Invalid Gpio Pin encountered for signal TX34CAL_ENA"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + case(ADRV9025_CPU_CAL_UPDATE0_SIGNALID): + { + if ((armGpio->calUpdate0Pin.enable > 0) && + (armGpio->calUpdate0Pin.gpioPinSel > ADI_ADRV9025_GPIO_18)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armGpio->calUpdate0Pin.gpioPinSel, + "Invalid Gpio Pin encountered for signal CAL_UPDATE0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + case(ADRV9025_CPU_CAL_UPDATE1_SIGNALID): + { + if ((armGpio->calUpdate1Pin.enable > 0) && + (armGpio->calUpdate1Pin.gpioPinSel > ADI_ADRV9025_GPIO_18)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armGpio->calUpdate1Pin.gpioPinSel, + "Invalid Gpio Pin encountered for signal CAL_UPDATE1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + case(ADRV9025_CPU_CAL_UPDATE2_SIGNALID): + { + if ((armGpio->calUpdate2Pin.enable > 0) && + (armGpio->calUpdate2Pin.gpioPinSel > ADI_ADRV9025_GPIO_18)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armGpio->calUpdate2Pin.gpioPinSel, + "Invalid Gpio Pin encountered for signal CAL_UPDATE2"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + case(ADRV9025_CPU_RF_PLL_FREQ_HOP_SIGNALID): + { + if ((armGpio->rfPllFreqHopPin.enable > 0) && + (armGpio->rfPllFreqHopPin.gpioPinSel > ADI_ADRV9025_GPIO_18)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armGpio->calUpdate2Pin.gpioPinSel, + "Invalid Gpio Pin encountered for signal RF_PLL_FREQ_HOP"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + SIGNAL_ID[signalIndex], + "Invalid Signal ID encountered while attempting to configure ARM GPIO pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_ArmGpioPinsSet(adi_adrv9025_Device_t* device, + adi_adrv9025_ArmGpioCfg_t* armGpio) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, armGpio); + + UNUSED_PARA(device); + UNUSED_PARA(armGpio); + return 0; +} + +int32_t adi_adrv9025_ArmGpioPinsGet(adi_adrv9025_Device_t* device, + adi_adrv9025_ArmGpioCfg_t* armGpio) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, armGpio); + + UNUSED_PARA(device); + UNUSED_PARA(armGpio); + return 0; +} + +int32_t adi_adrv9025_RadioCtrlCfgSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RadioCtrlModeCfg_t* radioCtrlCfg) +{ + static const uint8_t MAX_PIN_SEL_SETTLING_DELAY_ARM_CLK_CYCLES = 0x0F; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + radioCtrlCfg); + + if (((device->devStateInfo.profilesValid & ADI_ADRV9025_RX_PROFILE_VALID) == ADI_ADRV9025_RX_PROFILE_VALID) && + (radioCtrlCfg->rxRadioCtrlModeCfg.rxEnableMode != ADI_ADRV9025_RX_EN_INVALID_MODE) && + (radioCtrlCfg->rxRadioCtrlModeCfg.rxChannelMask != ADI_ADRV9025_RXOFF)) + { + if ((radioCtrlCfg->rxRadioCtrlModeCfg.rxEnableMode != ADI_ADRV9025_RX_EN_SPI_MODE) && + (radioCtrlCfg->rxRadioCtrlModeCfg.rxEnableMode != ADI_ADRV9025_RX_EN_PIN_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + radioCtrlCfg->rxRadioCtrlModeCfg.rxEnableMode, + "Invalid Rx signal chain enable mode selected. Valid values include SPI, Pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if (((device->devStateInfo.profilesValid & ADI_ADRV9025_TX_PROFILE_VALID) == ADI_ADRV9025_TX_PROFILE_VALID) && + (radioCtrlCfg->txRadioCtrlModeCfg.txEnableMode != ADI_ADRV9025_TX_EN_INVALID_MODE) && + (radioCtrlCfg->txRadioCtrlModeCfg.txChannelMask != ADI_ADRV9025_TXOFF)) + { + if ((radioCtrlCfg->txRadioCtrlModeCfg.txEnableMode != ADI_ADRV9025_TX_EN_SPI_MODE) && + (radioCtrlCfg->txRadioCtrlModeCfg.txEnableMode != ADI_ADRV9025_TX_EN_PIN_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + radioCtrlCfg->txRadioCtrlModeCfg.txEnableMode, + "Invalid Tx signal chain enable mode selected. Valid values include SPI, Pin mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if (((device->devStateInfo.profilesValid & ADI_ADRV9025_ORX_PROFILE_VALID) == ADI_ADRV9025_ORX_PROFILE_VALID) && + (radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode != ADI_ADRV9025_ORX_EN_INVALID_MODE)) + { + if ((radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode != ADI_ADRV9025_ORX_EN_SPI_MODE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode != ADI_ADRV9025_ORX_EN_SINGLE_CH_3PIN_MODE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode != ADI_ADRV9025_ORX_EN_SINGLE_CH_2PIN_MODE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode != ADI_ADRV9025_ORX_EN_SINGLE_CH_1PIN_MODE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode != ADI_ADRV9025_ORX_EN_DUAL_CH_4PIN_MODE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode != ADI_ADRV9025_ORX_EN_DUAL_CH_2PIN_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode, + "Invalid ORx signal chain enable mode selected. Valid values include SPI, Single channel 3 Pin, 2 Pin, 1 Pin modes, Dual channel 4 pin, 2 pin modes"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode != ADI_ADRV9025_ORX_EN_SPI_MODE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.orxPinSelectSettlingDelay_armClkCycles > MAX_PIN_SEL_SETTLING_DELAY_ARM_CLK_CYCLES)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + radioCtrlCfg->orxRadioCtrlModeCfg.orxPinSelectSettlingDelay_armClkCycles, + "Out of range pin select settling delay detected. Valid values are in the range 0x00 - 0x0F(2-18 ARM clk cycles)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode == ADI_ADRV9025_ORX_EN_SINGLE_CH_1PIN_MODE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.singleChannel1PinModeOrxSel != ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX1_FE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.singleChannel1PinModeOrxSel != ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.singleChannel1PinModeOrxSel != ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX3_FE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.singleChannel1PinModeOrxSel != ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX4_FE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + radioCtrlCfg->orxRadioCtrlModeCfg.singleChannel1PinModeOrxSel, + "Single channel 1 Pin ORx enable mode selected but ORx select is out of range. Valid ORx selects include ORx1, ORx2, ORx3, ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode == ADI_ADRV9025_ORX_EN_SINGLE_CH_2PIN_MODE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.singleChannel2PinModeLowOrxSel != ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX1_FE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.singleChannel2PinModeLowOrxSel != ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.singleChannel2PinModeLowOrxSel != ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX3_FE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.singleChannel2PinModeLowOrxSel != ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX4_FE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + radioCtrlCfg->orxRadioCtrlModeCfg.singleChannel2PinModeLowOrxSel, + "Single channel 2 Pin ORx enable mode selected but pin level low ORx select is out of range. Valid ORx selects include ORx1, ORx2, ORx3, ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode == ADI_ADRV9025_ORX_EN_SINGLE_CH_2PIN_MODE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.singleChannel2PinModeHighOrxSel != ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX1_FE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.singleChannel2PinModeHighOrxSel != ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.singleChannel2PinModeHighOrxSel != ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX3_FE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.singleChannel2PinModeHighOrxSel != ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX4_FE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + radioCtrlCfg->orxRadioCtrlModeCfg.singleChannel2PinModeHighOrxSel, + "Single channel 2 Pin ORx enable mode selected but pin level high ORx select is out of range. Valid ORx selects include ORx1, ORx2, ORx3, ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode == ADI_ADRV9025_ORX_EN_DUAL_CH_2PIN_MODE) && + (radioCtrlCfg->orxRadioCtrlModeCfg.dualChannel2PinModeOrxSel != ADI_ADRV9025_DUAL_CH_PIN_MODE_ORX1_ORX3_SEL) && + (radioCtrlCfg->orxRadioCtrlModeCfg.dualChannel2PinModeOrxSel != ADI_ADRV9025_DUAL_CH_PIN_MODE_ORX1_ORX4_SEL) && + (radioCtrlCfg->orxRadioCtrlModeCfg.dualChannel2PinModeOrxSel != ADI_ADRV9025_DUAL_CH_PIN_MODE_ORX2_ORX3_SEL) && + (radioCtrlCfg->orxRadioCtrlModeCfg.dualChannel2PinModeOrxSel != ADI_ADRV9025_DUAL_CH_PIN_MODE_ORX2_ORX4_SEL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + radioCtrlCfg->orxRadioCtrlModeCfg.singleChannel2PinModeHighOrxSel, + "Dual channel 2 Pin ORx enable mode selected but ORx select is out of range. Valid ORx combinations include {ORx1,ORx3}, {ORx1,ORx4}, {ORx2,ORx3}, {ORx2,ORx4}"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RadioCtrlCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RadioCtrlModeCfg_t* radioCtrlCfg) +{ + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + radioCtrlCfg); + +#if ADI_ADRV9025_RADIOCTRL_RANGE_CHECK > 0 + adi_adrv9025_RadioCtrlCfgSetRangeCheck(device, + radioCtrlCfg); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + if (((device->devStateInfo.profilesValid & ADI_ADRV9025_RX_PROFILE_VALID) == ADI_ADRV9025_RX_PROFILE_VALID) && + (radioCtrlCfg->rxRadioCtrlModeCfg.rxEnableMode != ADI_ADRV9025_RX_EN_INVALID_MODE) && + (radioCtrlCfg->rxRadioCtrlModeCfg.rxChannelMask != ADI_ADRV9025_RXOFF)) + { + adrv9025_RxRadioCtrlCfgSet(device, + &radioCtrlCfg->rxRadioCtrlModeCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((device->devStateInfo.profilesValid & ADI_ADRV9025_TX_PROFILE_VALID) == ADI_ADRV9025_TX_PROFILE_VALID) && + (radioCtrlCfg->txRadioCtrlModeCfg.txEnableMode != ADI_ADRV9025_TX_EN_INVALID_MODE) && + (radioCtrlCfg->txRadioCtrlModeCfg.txChannelMask != ADI_ADRV9025_TXOFF)) + { + adrv9025_TxRadioCtrlCfgSet(device, + &radioCtrlCfg->txRadioCtrlModeCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((device->devStateInfo.profilesValid & ADI_ADRV9025_ORX_PROFILE_VALID) == ADI_ADRV9025_ORX_PROFILE_VALID) && + (radioCtrlCfg->orxRadioCtrlModeCfg.orxEnableMode != ADI_ADRV9025_ORX_EN_INVALID_MODE)) + { + adrv9025_OrxRadioCtrlCfgSet(device, + &radioCtrlCfg->orxRadioCtrlModeCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RadioCtrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_RadioCtrlModeCfg_t* radioCtrlCfg) +{ + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + radioCtrlCfg); + + adrv9025_RxRadioCtrlCfgGet(device, + rxChannel, + &radioCtrlCfg->rxRadioCtrlModeCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_TxRadioCtrlCfgGet(device, + txChannel, + &radioCtrlCfg->txRadioCtrlModeCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_OrxRadioCtrlCfgGet(device, + &radioCtrlCfg->orxRadioCtrlModeCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RadioStateGet(adi_adrv9025_Device_t* device, + uint32_t* radioStatus) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, radioStatus); + + UNUSED_PARA(device); + UNUSED_PARA(radioStatus); + return 0; +} + +int32_t adi_adrv9025_RxTxEnableSetRangeCheck(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint32_t txChannelMask) +{ + /*TODO : update this static const once Tx channels have been numbered from Tx1 - Tx4*/ + static const uint32_t ALL_TX_MASK = (ADI_ADRV9025_TX1 | ADI_ADRV9025_TX2 | ADI_ADRV9025_TX3 | ADI_ADRV9025_TX4); + static const uint32_t ALL_RX_MASK = (ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4); + static const uint32_t ALL_ORX_MASK = (ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2 | ADI_ADRV9025_ORX3 | ADI_ADRV9025_ORX4); + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /*Check that ARM and Stream processors have been loaded before enabling*/ + if (device->devStateInfo.devState < ADI_ADRV9025_STATE_CPULOADED) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "Channel Enable/Disable is valid only after ARM and stream processors have been loaded"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that Rx/ORx channel mask is valid*/ + if (rxChannelMask > (ALL_RX_MASK | ALL_ORX_MASK)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "Invalid Rx/ORx Channel mask encountered while attempting to enable Rx/ORx signal chain in SPI mode. Valid masks are Rx1-Rx4, ORx1 - ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that Tx channel mask is valid*/ + if (txChannelMask > ALL_TX_MASK) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "Invalid Tx Channel mask encountered while attempting to enable Tx signal chain in SPI mode. Valid masks are Tx1-Tx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that requested Rx/ORx channels are initialized*/ + if ((rxChannelMask & device->devStateInfo.initializedChannels) != rxChannelMask) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "Requested Rx/ORx channels to enable are not initialized"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that requested Tx channels are initialized*/ + if ((txChannelMask & (device->devStateInfo.initializedChannels >> ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET)) != txChannelMask) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "Requested Tx channels to enable are not initialized"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxTxEnableSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint32_t txChannelMask) +{ + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + +#if ADI_ADRV9025_RADIOCTRL_RANGE_CHECK > 0 + adi_adrv9025_RxTxEnableSetRangeCheck(device, + rxChannelMask, + txChannelMask); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /*Enable requested Rx Channel signal chains*/ + adrv9025_RxEnableSet(device, + rxChannelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Enable requested ORx Channel signal chains*/ + adrv9025_OrxEnableSet(device, + rxChannelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Enable requested Tx Channel signal chains*/ + adrv9025_TxEnableSet(device, + txChannelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxTxEnableGet(adi_adrv9025_Device_t* device, + uint32_t* rxChannelMask, + uint32_t* txChannelMask) +{ + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + rxChannelMask); + + ADI_NULL_PTR_RETURN(&device->common, + txChannelMask); + + adrv9025_RxEnableGet(device, + rxChannelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_OrxEnableGet(device, + rxChannelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_TxEnableGet(device, + txChannelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxToOrxMappingSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e orxChannel, + adi_adrv9025_TxChannels_e txChannel) +{ + uint8_t TXMAP_ORX1_EN_RISE_STREAM_ID = 0; + uint8_t TXMAP_ORX1_EN_FALL_STREAM_ID = 0; + uint8_t TXMAP_ORX1_SEL_RISE_STREAM_ID = 0; + uint8_t TXMAP_ORX1_SEL_FALL_STREAM_ID = 0; + uint8_t TXMAP_ORX2_EN_RISE_STREAM_ID = 0; + uint8_t TXMAP_ORX2_EN_FALL_STREAM_ID = 0; + uint8_t TXMAP_ORX2_SEL_RISE_STREAM_ID = 0; + uint8_t TXMAP_ORX2_SEL_FALL_STREAM_ID = 0; + uint8_t TXMAP_ORX3_EN_RISE_STREAM_ID = 0; + uint8_t TXMAP_ORX3_EN_FALL_STREAM_ID = 0; + uint8_t TXMAP_ORX3_SEL_RISE_STREAM_ID = 0; + uint8_t TXMAP_ORX3_SEL_FALL_STREAM_ID = 0; + uint8_t TXMAP_ORX4_EN_RISE_STREAM_ID = 0; + uint8_t TXMAP_ORX4_EN_FALL_STREAM_ID = 0; + uint8_t TXMAP_ORX4_SEL_RISE_STREAM_ID = 0; + uint8_t TXMAP_ORX4_SEL_FALL_STREAM_ID = 0; + + TXMAP_ORX1_EN_RISE_STREAM_ID = 0x80; + TXMAP_ORX1_EN_FALL_STREAM_ID = 0x82; + TXMAP_ORX1_SEL_RISE_STREAM_ID = 0x81; + TXMAP_ORX1_SEL_FALL_STREAM_ID = 0x83; + TXMAP_ORX2_EN_RISE_STREAM_ID = 0x88; + TXMAP_ORX2_EN_FALL_STREAM_ID = 0x8A; + TXMAP_ORX2_SEL_RISE_STREAM_ID = 0x89; + TXMAP_ORX2_SEL_FALL_STREAM_ID = 0x8B; + TXMAP_ORX3_EN_RISE_STREAM_ID = 0x84; + TXMAP_ORX3_EN_FALL_STREAM_ID = 0x86; + TXMAP_ORX3_SEL_RISE_STREAM_ID = 0x85; + TXMAP_ORX3_SEL_FALL_STREAM_ID = 0x87; + TXMAP_ORX4_EN_RISE_STREAM_ID = 0x8C; + TXMAP_ORX4_EN_FALL_STREAM_ID = 0x8E; + TXMAP_ORX4_SEL_RISE_STREAM_ID = 0x8D; + TXMAP_ORX4_SEL_FALL_STREAM_ID = 0x8F; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + +#if ADI_ADRV9025_RADIOCTRL_RANGE_CHECK > 0 + adrv9025_TxToOrxMappingSetRangeCheck(device, + orxChannel, + txChannel); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + switch (orxChannel) + { + case(ADI_ADRV9025_ORX1): + { + if (txChannel == ADI_ADRV9025_TXOFF) + { + adrv9025_StreamTrigger(device, + TXMAP_ORX1_EN_FALL_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (txChannel == ADI_ADRV9025_TX1) + { + adrv9025_StreamTrigger(device, + TXMAP_ORX1_EN_RISE_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamTrigger(device, + TXMAP_ORX1_SEL_FALL_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (txChannel == ADI_ADRV9025_TX2) + { + adrv9025_StreamTrigger(device, + TXMAP_ORX1_EN_RISE_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamTrigger(device, + TXMAP_ORX1_SEL_RISE_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid Tx channel selected for Tx-ORx1 mapping. Valid Tx channels are Tx1, Tx2, TxOFF(disable)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + break; + } + case(ADI_ADRV9025_ORX2): + { + if (txChannel == ADI_ADRV9025_TXOFF) + { + adrv9025_StreamTrigger(device, + TXMAP_ORX2_EN_FALL_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (txChannel == ADI_ADRV9025_TX1) + { + adrv9025_StreamTrigger(device, + TXMAP_ORX2_EN_RISE_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamTrigger(device, + TXMAP_ORX2_SEL_FALL_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (txChannel == ADI_ADRV9025_TX2) + { + adrv9025_StreamTrigger(device, + TXMAP_ORX2_EN_RISE_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamTrigger(device, + TXMAP_ORX2_SEL_RISE_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid Tx channel selected for Tx-ORx2 mapping. Valid Tx channels are Tx1, Tx2, TxOFF(disable)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + break; + } + case(ADI_ADRV9025_ORX3): + { + if (txChannel == ADI_ADRV9025_TXOFF) + { + adrv9025_StreamTrigger(device, + TXMAP_ORX3_EN_FALL_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (txChannel == ADI_ADRV9025_TX3) + { + adrv9025_StreamTrigger(device, + TXMAP_ORX3_EN_RISE_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamTrigger(device, + TXMAP_ORX3_SEL_FALL_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (txChannel == ADI_ADRV9025_TX4) + { + adrv9025_StreamTrigger(device, + TXMAP_ORX3_EN_RISE_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamTrigger(device, + TXMAP_ORX3_SEL_RISE_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid Tx channel selected for Tx-ORx3 mapping. Valid Tx channels are Tx3, Tx4, TxOFF(disable)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + break; + } + case(ADI_ADRV9025_ORX4): + { + if (txChannel == ADI_ADRV9025_TXOFF) + { + adrv9025_StreamTrigger(device, + TXMAP_ORX4_EN_FALL_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (txChannel == ADI_ADRV9025_TX3) + { + adrv9025_StreamTrigger(device, + TXMAP_ORX4_EN_RISE_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamTrigger(device, + TXMAP_ORX4_SEL_FALL_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (txChannel == ADI_ADRV9025_TX4) + { + adrv9025_StreamTrigger(device, + TXMAP_ORX4_EN_RISE_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamTrigger(device, + TXMAP_ORX4_SEL_RISE_STREAM_ID); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid Tx channel selected for Tx-ORx3 mapping. Valid Tx channels are Tx3, Tx4, TxOFF(disable)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + break; + } + + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + orxChannel, + "Invalid ORx channel selected for Tx to ORx mapping. Valid ORx channels are ORx1-ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxToOrxMappingGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e orxChannel, + adi_adrv9025_TxChannels_e* txChannel) +{ + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + static const uint8_t ARM_CMD_ERROR_MASK = 0x0E; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint16_t encodedTxToOrxMapping = 0; + uint8_t armData[2] = {0}; + uint8_t extData[1] = {0}; + uint8_t cmdStatusByte = 0; + int32_t errHdl = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txChannel); + + /* Executing the GET Tx-ORx mapping command */ + extData[0] = ADRV9025_CPU_OBJECTID_TX_ORX_MAPPING; + adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_GET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_GETTXTOORXMAP_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_GETTXTOORXMAP_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte & ARM_CMD_ERROR_MASK) > 0) + { + adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read the encoded Tx-ORx mapping from ARM mailbox */ + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Decode Tx-ORx mapping */ + encodedTxToOrxMapping = (uint16_t)(((uint16_t)armData[1] << 8) | (uint16_t)armData[0]); + recoveryAction = adrv9025_OrxMapDecode(device, + encodedTxToOrxMapping, + orxChannel, + txChannel); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_StreamGpioConfigSet(adi_adrv9025_Device_t* device, + adi_adrv9025_StreamGpioPinCfg_t* streamGpioPinCfg) +{ + uint8_t signalId = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + streamGpioPinCfg); + +#if ADI_ADRV9025_RADIOCTRL_RANGE_CHECK > 0 + adrv9025_StreamGpioConfigSetRangeCheck(device, + streamGpioPinCfg); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /* Loop through each pin and call the corresponding set function */ + signalId = 0; + adrv9025_StreamGpioPinSet(device, + signalId++, + streamGpioPinCfg->streamGpInput0); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinSet(device, + signalId++, + streamGpioPinCfg->streamGpInput1); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinSet(device, + signalId++, + streamGpioPinCfg->streamGpInput2); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinSet(device, + signalId++, + streamGpioPinCfg->streamGpInput3); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinSet(device, + signalId++, + streamGpioPinCfg->streamGpInput4); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinSet(device, + signalId++, + streamGpioPinCfg->streamGpInput5); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinSet(device, + signalId++, + streamGpioPinCfg->streamGpInput6); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinSet(device, + signalId++, + streamGpioPinCfg->streamGpInput7); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinSet(device, + signalId++, + streamGpioPinCfg->streamGpInput8); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinSet(device, + signalId++, + streamGpioPinCfg->streamGpInput9); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinSet(device, + signalId++, + streamGpioPinCfg->streamGpInput10); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinSet(device, + signalId++, + streamGpioPinCfg->streamGpInput11); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinSet(device, + signalId++, + streamGpioPinCfg->streamGpInput12); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinSet(device, + signalId++, + streamGpioPinCfg->streamGpInput13); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinSet(device, + signalId++, + streamGpioPinCfg->streamGpInput14); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinSet(device, + signalId++, + streamGpioPinCfg->streamGpInput15); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_StreamGpioConfigGet(adi_adrv9025_Device_t* device, + adi_adrv9025_StreamGpioPinCfg_t* streamGpioPinCfg) +{ + uint8_t signalId = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + streamGpioPinCfg); + + /* Loop through each pin and call the corresponding get function */ + signalId = 0; + adrv9025_StreamGpioPinGet(device, + signalId++, + &streamGpioPinCfg->streamGpInput0); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinGet(device, + signalId++, + &streamGpioPinCfg->streamGpInput1); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinGet(device, + signalId++, + &streamGpioPinCfg->streamGpInput2); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinGet(device, + signalId++, + &streamGpioPinCfg->streamGpInput3); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinGet(device, + signalId++, + &streamGpioPinCfg->streamGpInput4); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinGet(device, + signalId++, + &streamGpioPinCfg->streamGpInput5); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinGet(device, + signalId++, + &streamGpioPinCfg->streamGpInput6); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinGet(device, + signalId++, + &streamGpioPinCfg->streamGpInput7); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinGet(device, + signalId++, + &streamGpioPinCfg->streamGpInput8); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinGet(device, + signalId++, + &streamGpioPinCfg->streamGpInput9); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinGet(device, + signalId++, + &streamGpioPinCfg->streamGpInput10); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinGet(device, + signalId++, + &streamGpioPinCfg->streamGpInput11); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinGet(device, + signalId++, + &streamGpioPinCfg->streamGpInput12); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinGet(device, + signalId++, + &streamGpioPinCfg->streamGpInput13); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinGet(device, + signalId++, + &streamGpioPinCfg->streamGpInput14); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_StreamGpioPinGet(device, + signalId++, + &streamGpioPinCfg->streamGpInput15); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PllFrequencySetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + uint64_t pllLoFrequency_Hz) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t areCalsRunning = 0; + uint8_t errorFlag = 0; + uint32_t i = 0; + int64_t freqValid = 0; + uint64_t maxRfBandwidth_kHz = 0; + adi_adrv9025_LoSel_e pllLoSelect = ADI_ADRV9025_LOSEL_LO1; + adi_adrv9025_LoSel_e loSel = ADI_ADRV9025_LOSEL_LO1; + adi_adrv9025_TxChannels_e txChannel = ADI_ADRV9025_TXOFF; + adi_adrv9025_RxChannels_e rxChannel = ADI_ADRV9025_RXOFF; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /*Check that PLL selected is valid*/ + if ((pllName != ADI_ADRV9025_LO1_PLL) && + (pllName != ADI_ADRV9025_LO2_PLL) && + (pllName != ADI_ADRV9025_AUX_PLL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pllName, + "Invalid PLL selected for setting PLL frequency"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Determine the PLL Frequency LO Selection */ + if (pllName == ADI_ADRV9025_LO1_PLL) + { + pllLoSelect = ADI_ADRV9025_LOSEL_LO1; + } + else if (pllName == ADI_ADRV9025_LO2_PLL) + { + pllLoSelect = ADI_ADRV9025_LOSEL_LO2; + } + else if (pllName == ADI_ADRV9025_AUX_PLL) + { + pllLoSelect = ADI_ADRV9025_LOSEL_AUXLO; + } + + /* Find the greatest TX Input Rates value of the same LO */ + maxRfBandwidth_kHz = 0; + if ((device->devStateInfo.profilesValid & ADI_ADRV9025_TX_PROFILE_VALID) == ADI_ADRV9025_TX_PROFILE_VALID) + { + for (i = ADI_ADRV9025_MAX_TX_CHANNEL_START; i <= ADI_ADRV9025_MAX_TX_CHANNEL_END; i++) + { + /* convert the index to matching the channel */ + txChannel = (adi_adrv9025_TxChannels_e)((uint8_t)(1 << i)); + if (((device->devStateInfo.initializedChannels >> ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET) & (uint32_t)txChannel) == (uint32_t)txChannel) + { + recoveryAction = adi_adrv9025_TxLoSourceGet(device, + txChannel, + &loSel); + if ((recoveryAction == ADI_COMMON_ACT_NO_ACTION) && + (loSel == pllLoSelect)) + { + /* Now check if matching LO then compare to get max value */ + if (device->devStateInfo.txRfBandWidth_kHz[i] > maxRfBandwidth_kHz) + { + maxRfBandwidth_kHz = device->devStateInfo.txRfBandWidth_kHz[i]; + } + } + } + } + } + + /* Find the greatest RX Output Rates value of the same LO */ + if ((device->devStateInfo.profilesValid & ADI_ADRV9025_RX_PROFILE_VALID) == ADI_ADRV9025_RX_PROFILE_VALID) + { + for (i = ADI_ADRV9025_MAX_RX_CHANNEL_START; i <= ADI_ADRV9025_MAX_RX_CHANNEL_END; i++) + { + /* convert the index to matching the channel */ + rxChannel = (adi_adrv9025_RxChannels_e)((uint8_t)(1 << i)); + if ((device->devStateInfo.initializedChannels & (uint32_t)rxChannel) == (uint32_t)rxChannel) + { + recoveryAction = adi_adrv9025_RxLoSourceGet(device, + rxChannel, + &loSel); + if ((recoveryAction == ADI_COMMON_ACT_NO_ACTION) && + (loSel == pllLoSelect)) + { + /* Now check if matching LO then compare to get max value */ + if (device->devStateInfo.rxRfBandWidth_kHz[i] > maxRfBandwidth_kHz) + { + maxRfBandwidth_kHz = device->devStateInfo.rxRfBandWidth_kHz[i]; + } + } + } + } + } + + /* Find the greatest ORX Output Rates value of the same LO */ + if ((device->devStateInfo.profilesValid & ADI_ADRV9025_ORX_PROFILE_VALID) == ADI_ADRV9025_ORX_PROFILE_VALID) + { + for (i = ADI_ADRV9025_MAX_ORX_CHANNEL_START; i <= ADI_ADRV9025_MAX_ORX_CHANNEL_END; i++) + { + /* convert the index to matching the channel */ + rxChannel = (adi_adrv9025_RxChannels_e)((uint8_t)(1 << i)); + if ((device->devStateInfo.initializedChannels & (uint32_t)rxChannel) == (uint32_t)rxChannel) + { + recoveryAction = adi_adrv9025_RxLoSourceGet(device, + rxChannel, + &loSel); + if ((recoveryAction == ADI_COMMON_ACT_NO_ACTION) && + (loSel == pllLoSelect)) + { + /* Now check if matching LO then compare to get max value */ + if (device->devStateInfo.rxRfBandWidth_kHz[i] > maxRfBandwidth_kHz) + { + maxRfBandwidth_kHz = device->devStateInfo.rxRfBandWidth_kHz[i]; + } + } + } + } + } + + /* The rule is that the PLL LO frequency must always more than half of the greatest bandwidth. */ + freqValid = (int64_t)pllLoFrequency_Hz - (int64_t)((maxRfBandwidth_kHz * 1000) >> 1); + if ((freqValid <= 0) && (maxRfBandwidth_kHz > 0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pllLoFrequency_Hz, + "(pllFreq - Bandwidth/2) should be greater than DC."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that init cals are not running*/ + adi_adrv9025_InitCalsCheckCompleteGet(device, + &areCalsRunning, + &errorFlag); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (areCalsRunning == 1) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pllLoFrequency_Hz, + "Can not set PLL frequency while InitCals are running"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PllFrequencySetRangeCheck_v2(adi_adrv9025_Device_t* device, + adi_adrv9025_PllConfig_t* pllConfig) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t areCalsRunning = 0; + uint8_t errorFlag = 0; + uint32_t i = 0; + int64_t freqValid = 0; + uint64_t maxRfBandwidth_kHz = 0; + adi_adrv9025_LoSel_e pllLoSelect = ADI_ADRV9025_LOSEL_LO1; + adi_adrv9025_LoSel_e loSel = ADI_ADRV9025_LOSEL_LO1; + adi_adrv9025_TxChannels_e txChannel = ADI_ADRV9025_TXOFF; + adi_adrv9025_RxChannels_e rxChannel = ADI_ADRV9025_RXOFF; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + pllConfig); + + /*Check that PLL selected is valid*/ + if ((pllConfig->pllName != ADI_ADRV9025_LO1_PLL) && + (pllConfig->pllName != ADI_ADRV9025_LO2_PLL) && + (pllConfig->pllName != ADI_ADRV9025_AUX_PLL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pllConfig->pllName, + "Invalid PLL selected for setting PLL frequency"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that PLL mode is valid*/ + if ((pllConfig->pllModeSel != ADI_ADRV9025_PLL_FAST_MODE) && + (pllConfig->pllModeSel != ADI_ADRV9025_PLL_SLOW_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pllConfig->pllModeSel, + "Invalid PLL mode selected for setting PLL frequency"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Determine the PLL Frequency LO Selection */ + if (pllConfig->pllName == ADI_ADRV9025_LO1_PLL) + { + pllLoSelect = ADI_ADRV9025_LOSEL_LO1; + } + else if (pllConfig->pllName == ADI_ADRV9025_LO2_PLL) + { + pllLoSelect = ADI_ADRV9025_LOSEL_LO2; + } + else if (pllConfig->pllName == ADI_ADRV9025_AUX_PLL) + { + pllLoSelect = ADI_ADRV9025_LOSEL_AUXLO; + } + + /* Find the greatest TX Input Rates value of the same LO */ + maxRfBandwidth_kHz = 0; + if ((device->devStateInfo.profilesValid & ADI_ADRV9025_TX_PROFILE_VALID) == ADI_ADRV9025_TX_PROFILE_VALID) + { + for (i = ADI_ADRV9025_MAX_TX_CHANNEL_START; i <= ADI_ADRV9025_MAX_TX_CHANNEL_END; i++) + { + /* convert the index to matching the channel */ + txChannel = (adi_adrv9025_TxChannels_e)((uint8_t)(1 << i)); + if (((device->devStateInfo.initializedChannels >> ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET) & (uint32_t)txChannel) == (uint32_t)txChannel) + { + recoveryAction = adi_adrv9025_TxLoSourceGet(device, + txChannel, + &loSel); + if ((recoveryAction == ADI_COMMON_ACT_NO_ACTION) && + (loSel == pllLoSelect)) + { + /* Now check if matching LO then compare to get max value */ + if (device->devStateInfo.txRfBandWidth_kHz[i] > maxRfBandwidth_kHz) + { + maxRfBandwidth_kHz = device->devStateInfo.txRfBandWidth_kHz[i]; + } + } + } + } + } + + /* Find the greatest RX Output Rates value of the same LO */ + if ((device->devStateInfo.profilesValid & ADI_ADRV9025_RX_PROFILE_VALID) == ADI_ADRV9025_RX_PROFILE_VALID) + { + for (i = ADI_ADRV9025_MAX_RX_CHANNEL_START; i <= ADI_ADRV9025_MAX_RX_CHANNEL_END; i++) + { + /* convert the index to matching the channel */ + rxChannel = (adi_adrv9025_RxChannels_e)((uint8_t)(1 << i)); + if ((device->devStateInfo.initializedChannels & (uint32_t)rxChannel) == (uint32_t)rxChannel) + { + recoveryAction = adi_adrv9025_RxLoSourceGet(device, + rxChannel, + &loSel); + if ((recoveryAction == ADI_COMMON_ACT_NO_ACTION) && + (loSel == pllLoSelect)) + { + /* Now check if matching LO then compare to get max value */ + if (device->devStateInfo.rxRfBandWidth_kHz[i] > maxRfBandwidth_kHz) + { + maxRfBandwidth_kHz = device->devStateInfo.rxRfBandWidth_kHz[i]; + } + } + } + } + } + + /* Find the greatest ORX Output Rates value of the same LO */ + if ((device->devStateInfo.profilesValid & ADI_ADRV9025_ORX_PROFILE_VALID) == ADI_ADRV9025_ORX_PROFILE_VALID) + { + for (i = ADI_ADRV9025_MAX_ORX_CHANNEL_START; i <= ADI_ADRV9025_MAX_ORX_CHANNEL_END; i++) + { + /* convert the index to matching the channel */ + rxChannel = (adi_adrv9025_RxChannels_e)((uint8_t)(1 << i)); + if ((device->devStateInfo.initializedChannels & (uint32_t)rxChannel) == (uint32_t)rxChannel) + { + recoveryAction = adi_adrv9025_RxLoSourceGet(device, + rxChannel, + &loSel); + if ((recoveryAction == ADI_COMMON_ACT_NO_ACTION) && + (loSel == pllLoSelect)) + { + /* Now check if matching LO then compare to get max value */ + if (device->devStateInfo.rxRfBandWidth_kHz[i] > maxRfBandwidth_kHz) + { + maxRfBandwidth_kHz = device->devStateInfo.rxRfBandWidth_kHz[i]; + } + } + } + } + } + + /* The rule is that the PLL LO frequency must always more than half of the greatest bandwidth. */ + freqValid = (int64_t)pllConfig->pllLoFrequency_Hz - (int64_t)((maxRfBandwidth_kHz * 1000) >> 1); + if ((freqValid <= 0) && (maxRfBandwidth_kHz > 0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pllConfig->pllLoFrequency_Hz, + "(pllFreq - Bandwidth/2) should be greater than DC."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that init cals are not running*/ + adi_adrv9025_InitCalsCheckCompleteGet(device, + &areCalsRunning, + &errorFlag); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (areCalsRunning == 1) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pllConfig->pllLoFrequency_Hz, + "Can not set PLL frequency while InitCals are running"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PllFrequencySet(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + uint64_t pllLoFrequency_Hz) +{ + static const uint8_t PLL_GP_INTERRUPT_PIN0_MASK = 1; + static const uint8_t PLL_GP_INTERRUPT_PIN1_MASK = 1; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t armData[8] = {0}; + uint8_t extData[2] = {0}; + uint8_t cmdStatusByte = 0; + int32_t errHdl = 0; + uint8_t pllUnlockGpInterruptPin0Mask = 0; + uint8_t pllUnlockGpInterruptPin1Mask = 0; + uint8_t auxPllGpInterruptPin0Mask = 0; + uint8_t auxPllGpInterruptPin1Mask = 0; + uint8_t pll1OverrangeGpInterruptPin0Mask = 0; + uint8_t pll1OverrangeGpInterruptPin1Mask = 0; + uint8_t pll2OverrangeGpInterruptPin0Mask = 0; + uint8_t pll2OverrangeGpInterruptPin1Mask = 0; + uint8_t auxPllOverrangeGpInterruptPin0Mask = 0; + uint8_t auxPllOverrangeGpInterruptPin1Mask = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + +#if ADI_ADRV9025_RADIOCTRL_RANGE_CHECK > 0 + adi_adrv9025_PllFrequencySetRangeCheck(device, + pllName, + pllLoFrequency_Hz); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /*Store the current PLL unlock GP Interrupt status for the requested PLL*/ + adrv9025_PllUnlockGpInterruptMaskGet(device, + pllName, + &pllUnlockGpInterruptPin0Mask, + &pllUnlockGpInterruptPin1Mask); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Mask the PLL unlock interrupt*/ + adrv9025_PllUnlockGpInterruptMaskSet(device, + pllName, + PLL_GP_INTERRUPT_PIN0_MASK, + PLL_GP_INTERRUPT_PIN1_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Mask the Aux PLL GP Interrupt if RFLO1 or RFLO2 PLLs are targeted */ + if (pllName != ADI_ADRV9025_AUX_PLL) + { + /* Store the current Aux PLL unlock GP Interrupt status for the requested PLL */ + adrv9025_PllUnlockGpInterruptMaskGet(device, + ADI_ADRV9025_AUX_PLL, + &auxPllGpInterruptPin0Mask, + &auxPllGpInterruptPin1Mask); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Mask the Aux PLL unlock interrupt */ + adrv9025_PllUnlockGpInterruptMaskSet(device, + ADI_ADRV9025_AUX_PLL, + PLL_GP_INTERRUPT_PIN0_MASK, + PLL_GP_INTERRUPT_PIN1_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Store the current PLL overrange GP Interrupt status for RF PLL1, RF PLL2 and the Aux PLL */ + adrv9025_PllOverrangeGpInterruptMaskGet(device, + ADI_ADRV9025_LO1_PLL, + &pll1OverrangeGpInterruptPin0Mask, + &pll1OverrangeGpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_PllOverrangeGpInterruptMaskGet(device, + ADI_ADRV9025_LO2_PLL, + &pll2OverrangeGpInterruptPin0Mask, + &pll2OverrangeGpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_PllOverrangeGpInterruptMaskGet(device, + ADI_ADRV9025_AUX_PLL, + &auxPllOverrangeGpInterruptPin0Mask, + &auxPllOverrangeGpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Mask the PLL overrange interrupts */ + adrv9025_PllOverrangeGpInterruptMaskSet(device, + ADI_ADRV9025_LO1_PLL, + PLL_GP_INTERRUPT_PIN0_MASK, + PLL_GP_INTERRUPT_PIN1_MASK); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_PllOverrangeGpInterruptMaskSet(device, + ADI_ADRV9025_LO2_PLL, + PLL_GP_INTERRUPT_PIN0_MASK, + PLL_GP_INTERRUPT_PIN1_MASK); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_PllOverrangeGpInterruptMaskSet(device, + ADI_ADRV9025_AUX_PLL, + PLL_GP_INTERRUPT_PIN0_MASK, + PLL_GP_INTERRUPT_PIN1_MASK); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Loading byte array with parsed bytes from pllLoFrequency_Hz word */ + armData[0] = (uint8_t)(pllLoFrequency_Hz & 0xFF); + armData[1] = (uint8_t)((pllLoFrequency_Hz >> 8) & 0xFF); + armData[2] = (uint8_t)((pllLoFrequency_Hz >> 16) & 0xFF); + armData[3] = (uint8_t)((pllLoFrequency_Hz >> 24) & 0xFF); + armData[4] = (uint8_t)((pllLoFrequency_Hz >> 32) & 0xFF); + armData[5] = (uint8_t)((pllLoFrequency_Hz >> 40) & 0xFF); + armData[6] = (uint8_t)((pllLoFrequency_Hz >> 48) & 0xFF); + armData[7] = (uint8_t)((pllLoFrequency_Hz >> 56) & 0xFF); + + /* Write PLL Frequency to ARM mailbox */ + adi_adrv9025_CpuMemWrite(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_SET, + &armData[0], + sizeof(armData), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Executing the SET PLL Freq command */ + extData[0] = ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY; + extData[1] = (uint8_t)pllName; + adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_SET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_SET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_SETRFPLL_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_SETRFPLL_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte >> 1) > 0) + { + adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Restore the current PLL overrange GP Interrupt status for RF PLL1, RF PLL2 and the Aux PLL */ + adrv9025_PllOverrangeGpInterruptMaskSet(device, + ADI_ADRV9025_LO1_PLL, + pll1OverrangeGpInterruptPin0Mask, + pll1OverrangeGpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_PllOverrangeGpInterruptMaskSet(device, + ADI_ADRV9025_LO2_PLL, + pll2OverrangeGpInterruptPin0Mask, + pll2OverrangeGpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_PllOverrangeGpInterruptMaskSet(device, + ADI_ADRV9025_AUX_PLL, + auxPllOverrangeGpInterruptPin0Mask, + auxPllOverrangeGpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Restore PLL unlock GP Interrupt Status for the requested PLL*/ + adrv9025_PllUnlockGpInterruptMaskSet(device, + pllName, + pllUnlockGpInterruptPin0Mask, + pllUnlockGpInterruptPin1Mask); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Restore Aux PLL unlock GP Interrupt Status if RFLO1 or RFLO2 are targeted*/ + if (pllName != ADI_ADRV9025_AUX_PLL) + { + adrv9025_PllUnlockGpInterruptMaskSet(device, + ADI_ADRV9025_AUX_PLL, + auxPllGpInterruptPin0Mask, + auxPllGpInterruptPin1Mask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PllFrequencySet_v2(adi_adrv9025_Device_t* device, + adi_adrv9025_PllConfig_t* pllConfig) +{ + static const uint8_t PLL_GP_INTERRUPT_PIN0_MASK = 1; + static const uint8_t PLL_GP_INTERRUPT_PIN1_MASK = 1; + static const uint8_t ARM_ERROR_CODE = 0x0E; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t armData[8] = {0}; + uint8_t extData[2] = {0}; + uint8_t cmdStatusByte = 0; + int32_t errHdl = 0; + uint8_t pllUnlockGpInterruptPin0Mask = 0; + uint8_t pllUnlockGpInterruptPin1Mask = 0; + uint8_t auxPllGpInterruptPin0Mask = 0; + uint8_t auxPllGpInterruptPin1Mask = 0; + uint8_t pll1OverrangeGpInterruptPin0Mask = 0; + uint8_t pll1OverrangeGpInterruptPin1Mask = 0; + uint8_t pll2OverrangeGpInterruptPin0Mask = 0; + uint8_t pll2OverrangeGpInterruptPin1Mask = 0; + uint8_t auxPllOverrangeGpInterruptPin0Mask = 0; + uint8_t auxPllOverrangeGpInterruptPin1Mask = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + pllConfig); + +#if ADI_ADRV9025_RADIOCTRL_RANGE_CHECK > 0 + adi_adrv9025_PllFrequencySetRangeCheck_v2(device, + pllConfig); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /*Store the current PLL unlock GP Interrupt status for the requested PLL*/ + adrv9025_PllUnlockGpInterruptMaskGet(device, + pllConfig->pllName, + &pllUnlockGpInterruptPin0Mask, + &pllUnlockGpInterruptPin1Mask); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Mask the PLL unlock interrupt*/ + adrv9025_PllUnlockGpInterruptMaskSet(device, + pllConfig->pllName, + PLL_GP_INTERRUPT_PIN0_MASK, + PLL_GP_INTERRUPT_PIN1_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Mask the Aux PLL GP Interrupt if RFLO1 or RFLO2 PLLs are targeted */ + if (pllConfig->pllName != ADI_ADRV9025_AUX_PLL) + { + /* Store the current Aux PLL unlock GP Interrupt status for the requested PLL */ + adrv9025_PllUnlockGpInterruptMaskGet(device, + ADI_ADRV9025_AUX_PLL, + &auxPllGpInterruptPin0Mask, + &auxPllGpInterruptPin1Mask); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Mask the Aux PLL unlock interrupt */ + adrv9025_PllUnlockGpInterruptMaskSet(device, + ADI_ADRV9025_AUX_PLL, + PLL_GP_INTERRUPT_PIN0_MASK, + PLL_GP_INTERRUPT_PIN1_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Store the current PLL overrange GP Interrupt status for RF PLL1, RF PLL2 and the Aux PLL */ + adrv9025_PllOverrangeGpInterruptMaskGet(device, + ADI_ADRV9025_LO1_PLL, + &pll1OverrangeGpInterruptPin0Mask, + &pll1OverrangeGpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_PllOverrangeGpInterruptMaskGet(device, + ADI_ADRV9025_LO2_PLL, + &pll2OverrangeGpInterruptPin0Mask, + &pll2OverrangeGpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_PllOverrangeGpInterruptMaskGet(device, + ADI_ADRV9025_AUX_PLL, + &auxPllOverrangeGpInterruptPin0Mask, + &auxPllOverrangeGpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Mask the PLL overrange interrupts */ + adrv9025_PllOverrangeGpInterruptMaskSet(device, + ADI_ADRV9025_LO1_PLL, + PLL_GP_INTERRUPT_PIN0_MASK, + PLL_GP_INTERRUPT_PIN1_MASK); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_PllOverrangeGpInterruptMaskSet(device, + ADI_ADRV9025_LO2_PLL, + PLL_GP_INTERRUPT_PIN0_MASK, + PLL_GP_INTERRUPT_PIN1_MASK); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_PllOverrangeGpInterruptMaskSet(device, + ADI_ADRV9025_AUX_PLL, + PLL_GP_INTERRUPT_PIN0_MASK, + PLL_GP_INTERRUPT_PIN1_MASK); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Loading byte array with parsed bytes from pllLoFrequency_Hz word */ + armData[0] = (uint8_t)(pllConfig->pllLoFrequency_Hz & 0xFF); + armData[1] = (uint8_t)((pllConfig->pllLoFrequency_Hz >> 8) & 0xFF); + armData[2] = (uint8_t)((pllConfig->pllLoFrequency_Hz >> 16) & 0xFF); + armData[3] = (uint8_t)((pllConfig->pllLoFrequency_Hz >> 24) & 0xFF); + armData[4] = (uint8_t)((pllConfig->pllLoFrequency_Hz >> 32) & 0xFF); + armData[5] = (uint8_t)((pllConfig->pllLoFrequency_Hz >> 40) & 0xFF); + armData[6] = (uint8_t)((pllConfig->pllLoFrequency_Hz >> 48) & 0xFF); + armData[7] = (uint8_t)((pllConfig->pllLoFrequency_Hz >> 56) & 0xFF); + + /* Write PLL Frequency to ARM mailbox */ + adi_adrv9025_CpuMemWrite(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_SET, + &armData[0], + sizeof(armData), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Executing the SET PLL Freq command */ + extData[0] = ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY; + extData[1] = ((uint8_t)pllConfig->pllModeSel | (uint8_t)pllConfig->pllAuxLoResyncSel | (uint8_t)pllConfig->pllAuxLoOffsetProgSel | (uint8_t)pllConfig-> + pllName); + adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_SET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_SET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_SETRFPLL_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_SETRFPLL_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte & ARM_ERROR_CODE) > 0) + { + adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Restore the current PLL overrange GP Interrupt status for RF PLL1, RF PLL2 and the Aux PLL */ + adrv9025_PllOverrangeGpInterruptMaskSet(device, + ADI_ADRV9025_LO1_PLL, + pll1OverrangeGpInterruptPin0Mask, + pll1OverrangeGpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_PllOverrangeGpInterruptMaskSet(device, + ADI_ADRV9025_LO2_PLL, + pll2OverrangeGpInterruptPin0Mask, + pll2OverrangeGpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_PllOverrangeGpInterruptMaskSet(device, + ADI_ADRV9025_AUX_PLL, + auxPllOverrangeGpInterruptPin0Mask, + auxPllOverrangeGpInterruptPin1Mask); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Restore PLL unlock GP Interrupt Status for the requested PLL*/ + adrv9025_PllUnlockGpInterruptMaskSet(device, + pllConfig->pllName, + pllUnlockGpInterruptPin0Mask, + pllUnlockGpInterruptPin1Mask); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Restore Aux PLL unlock GP Interrupt Status if RFLO1 or RFLO2 are targeted*/ + if (pllConfig->pllName != ADI_ADRV9025_AUX_PLL) + { + adrv9025_PllUnlockGpInterruptMaskSet(device, + ADI_ADRV9025_AUX_PLL, + auxPllGpInterruptPin0Mask, + auxPllGpInterruptPin1Mask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PllFrequencyGet(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + uint64_t* pllLoFrequency_Hz) +{ + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t armData[8] = {0}; + uint8_t extData[2] = {0}; + uint8_t cmdStatusByte = 0; + int32_t errHdl = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + pllLoFrequency_Hz); + + /* Executing the GET PLL Freq command */ + extData[0] = ADRV9025_CPU_OBJECTID_RFPLL_LO_FREQUENCY; + extData[1] = (uint8_t)pllName; + adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_GET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_GETRFPLL_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_GETRFPLL_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte >> 1) > 0) + { + adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read PLL Frequency from ARM mailbox */ + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Form pllFrequency word with data read back from ARM mailbox*/ + *pllLoFrequency_Hz = ((uint64_t)(armData[0])) | + ((uint64_t)(armData[1]) << 8) | + ((uint64_t)(armData[2]) << 16) | + ((uint64_t)(armData[3]) << 24) | + ((uint64_t)(armData[4]) << 32) | + ((uint64_t)(armData[5]) << 40) | + ((uint64_t)(armData[6]) << 48) | + ((uint64_t)(armData[7]) << 56); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PllStatusGet(adi_adrv9025_Device_t* device, + uint32_t* pllLockStatus) +{ + static const uint8_t CLK_PLL_LOCK_STATUS_SHIFT = 0; + static const uint8_t LO1_PLL_LOCK_STATUS_SHIFT = 1; + static const uint8_t LO2_PLL_LOCK_STATUS_SHIFT = 2; + static const uint8_t AUX_PLL_LOCK_STATUS_SHIFT = 3; + static const uint32_t PLL_STATUS_MASK = 0x0000000F; + + uint8_t pllLockStatusRead = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that pllLockStatus pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + pllLockStatus); + + /* Clear status of all PLLs */ + *pllLockStatus &= ~PLL_STATUS_MASK; + + /* Read CLK Pll status */ + adrv9025_PllMemMapSynLockBfGet(device, + ADRV9025_BF_CLK_PLL, + &pllLockStatusRead); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Update pllLockStatus bit 0 with Clk Pll Status */ + *pllLockStatus |= ((uint32_t)pllLockStatusRead & 0x00000001) << CLK_PLL_LOCK_STATUS_SHIFT; + + /* Read LO1 Pll status */ + adrv9025_PllMemMapSynLockBfGet(device, + ADRV9025_BF_RF1_PLL, + &pllLockStatusRead); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Update pllLockStatus bit 1 with LO1 Pll Status */ + *pllLockStatus |= ((uint32_t)pllLockStatusRead & 0x00000001) << LO1_PLL_LOCK_STATUS_SHIFT; + + /* Read LO2 Pll status */ + adrv9025_PllMemMapSynLockBfGet(device, + ADRV9025_BF_RF2_PLL, + &pllLockStatusRead); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Update pllLockStatus bit 2 with LO2 Pll Status */ + *pllLockStatus |= ((uint32_t)pllLockStatusRead & 0x00000001) << LO2_PLL_LOCK_STATUS_SHIFT; + + /* Read Aux Pll status */ + adrv9025_PllMemMapSynLockBfGet(device, + ADRV9025_BF_AUX_PLL, + &pllLockStatusRead); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Update pllLockStatus bit 3 with Aux Pll Status */ + *pllLockStatus |= ((uint32_t)pllLockStatusRead & 0x00000001) << AUX_PLL_LOCK_STATUS_SHIFT; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PllLoopFilterSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + adi_adrv9025_PllLoopFilterCfg_t* pllLoopFilterConfig) +{ + static const uint8_t MINIMUM_PLL_LOOP_FILTER_PHASE_MARGIN_DEGREES = 40; + static const uint8_t MAXIMUM_PLL_LOOP_FILTER_PHASE_MARGIN_DEGREES = 85; + static const uint16_t MINIMUM_LOOP_FILTER_BANDWIDTH_KHZ = 50; + static const uint16_t MAXIMUM_LOOP_FILTER_BANDWIDTH_KHZ = 1500; + static const uint8_t MINIMUM_POWER_SCALE_FACTOR = 0; + static const uint8_t MAXIMUM_POWER_SCALE_FACTOR = 10; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that pllLockStatus pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + pllLoopFilterConfig); + + /*Check that PLL selected is valid*/ + if ((pllName != ADI_ADRV9025_LO1_PLL) && + (pllName != ADI_ADRV9025_LO2_PLL) && + (pllName != ADI_ADRV9025_AUX_PLL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pllName, + "Invalid PLL selected for PLL Loop Filter setting"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that Loop Filter phase margin is between 40-85 degrees*/ + if ((pllLoopFilterConfig->phaseMargin_degrees < MINIMUM_PLL_LOOP_FILTER_PHASE_MARGIN_DEGREES) || + (pllLoopFilterConfig->phaseMargin_degrees > MAXIMUM_PLL_LOOP_FILTER_PHASE_MARGIN_DEGREES)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pllLoopFilterConfig->phaseMargin_degrees, + "Phase margin out of range for PLL loop filter setting. Valid range 40-85 degrees"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that loop filter bandwidth is in valid range*/ + if ((pllLoopFilterConfig->loopBandwidth_kHz < MINIMUM_LOOP_FILTER_BANDWIDTH_KHZ) || + (pllLoopFilterConfig->loopBandwidth_kHz > MAXIMUM_LOOP_FILTER_BANDWIDTH_KHZ)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pllLoopFilterConfig->loopBandwidth_kHz, + "Loop filter bandwidth is out of range for PLL loop filter setting. Valid range 50-1500 KHz."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that power scale factor is between 0-10*/ + if ((pllLoopFilterConfig->powerScale < MINIMUM_POWER_SCALE_FACTOR) || + (pllLoopFilterConfig->powerScale > MAXIMUM_POWER_SCALE_FACTOR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pllLoopFilterConfig->powerScale, + "Power scale factor out of range for PLL loop filter setting. Valid range 0-10"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PllLoopFilterSet(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + adi_adrv9025_PllLoopFilterCfg_t* pllLoopFilterConfig) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t armData[4] = {0}; + uint8_t extData[2] = {0}; + uint8_t cmdStatusByte = 0; + int32_t errHdl = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that pllLockStatus pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + pllLoopFilterConfig); + +#if ADI_ADRV9025_RADIOCTRL_RANGE_CHECK > 0 + adi_adrv9025_PllLoopFilterSetRangeCheck(device, + pllName, + pllLoopFilterConfig); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /* Loading byte array with parsed bytes from pllLoopFilterConfig struct */ + armData[0] = pllLoopFilterConfig->phaseMargin_degrees; + armData[1] = (uint8_t)(pllLoopFilterConfig->loopBandwidth_kHz & 0x00FF); + armData[2] = (uint8_t)((pllLoopFilterConfig->loopBandwidth_kHz >> 8) & 0x00FF); + armData[3] = pllLoopFilterConfig->powerScale; + + /* Write PLL Loop Filter Config to ARM mailbox */ + adi_adrv9025_CpuMemWrite(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_SET, + &armData[0], + sizeof(armData), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Executing the SET PLL Loop filter config command */ + extData[0] = ADRV9025_CPU_OBJECTID_PLL_LOOP_BW; + extData[1] = (uint8_t)pllName; + adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_SET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_SET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_SETRFPLL_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_SETRFPLL_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte >> 1) > 0) + { + adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PllLoopFilterGet(adi_adrv9025_Device_t* device, + adi_adrv9025_PllName_e pllName, + adi_adrv9025_PllLoopFilterCfg_t* pllLoopFilterConfig) +{ + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t armData[4] = {0}; + uint8_t extData[2] = {0}; + uint8_t cmdStatusByte = 0; + int32_t errHdl = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that pllLockStatus pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + pllLoopFilterConfig); + + /*Check that PLL selected is valid*/ + if ((pllName != ADI_ADRV9025_LO1_PLL) && + (pllName != ADI_ADRV9025_LO2_PLL) && + (pllName != ADI_ADRV9025_AUX_PLL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pllName, + "Invalid PLL selected for PLL Loop Filter setting readback"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Executing the GET PLL Freq command */ + extData[0] = ADRV9025_CPU_OBJECTID_PLL_LOOP_BW; + extData[1] = (uint8_t)pllName; + adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_GET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_GETRFPLL_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_GETRFPLL_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte >> 1) > 0) + { + adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read PLL Frequency from ARM mailbox */ + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Deserialize ARM Data into pllLoopFilterConfig Structure*/ + pllLoopFilterConfig->phaseMargin_degrees = armData[0]; + pllLoopFilterConfig->loopBandwidth_kHz = (((uint16_t)armData[1]) | + ((uint16_t)armData[2] << 8)); + pllLoopFilterConfig->powerScale = armData[3]; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_DualBandStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_DualbandStatus_e* status) +{ + static const uint8_t ARM_ERR_CODE = 0x0E; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t armData[1] = {0}; + uint8_t extData[1] = {ADRV9025_CPU_OBJECTID_BANDSWITCH_STAT}; + uint8_t cmdStatusByte = 0; + const uint8_t DUAL_BAND_ENABLE = 0; + const uint8_t DUAL_BAND_DISABLE = 4; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + status); + + recoveryAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to send ARM command"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_GET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_GETBANDSWITCHSTAT_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_GETBANDSWITCHSTAT_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte & ARM_ERR_CODE) > 0) + { + recoveryAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction, + ADI_ADRV9025_ACT_ERR_RESET_CPU); + ADI_ERROR_RETURN(device->common.error.newAction); + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + cmdStatusByte, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Dualband status from ARM mailbox */ + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (((uint8_t)armData[0] >= DUAL_BAND_ENABLE) && ((uint8_t)armData[0] < DUAL_BAND_DISABLE)) + { + /* Dualband is enabled */ + *status = ADI_ADRV9025_DUALBAND_SWITCHING_ENABLED; + } + else + { + /* Dualband is disabled */ + *status = ADI_ADRV9025_DUALBAND_SWITCHING_DISABLED; + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_StreamVersionGet(adi_adrv9025_Device_t* device, + adi_adrv9025_StreamVersion_t* streamVersion) +{ + uint8_t ver[4] = {0}; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + //Check device pointer is not null + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + streamVersion); + + ADRV9025_BUGINFO(__FUNCTION__); + + if ((device->devStateInfo.devState & ADI_ADRV9025_STATE_STREAMLOADED) != ADI_ADRV9025_STATE_STREAMLOADED) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Stream binary must be loaded before getting stream version"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adi_adrv9025_ArmMemRead(device, + ADRV9025_CPU_ADDR_STREAM_VERSION, + &ver[0], + sizeof(ver), + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to read ARM memory"); + ADI_ERROR_RETURN(device->common.error.newAction); + + //Store the StreamVersion + streamVersion->majorVer = ver[0]; + streamVersion->minorVer = ver[1]; + streamVersion->mainVer = ver[2]; + streamVersion->buildVer = ver[3]; + + return (device->common.error.newAction); +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_rx.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_rx.c new file mode 100644 index 0000000..0632bde --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_rx.c @@ -0,0 +1,4646 @@ +/** +* \file adi_adrv9025_rx.c +* \brief Contains Rx features related function implementation defined in +* adi_adrv9025_rx.h +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "adi_adrv9025_rx.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_cpu.h" +#include "adi_adrv9025_error.h" +#include "adi_adrv9025_gpio.h" +#include "adi_adrv9025_radioctrl.h" +#include "../../private/include/adrv9025_radioctrl.h" +#include "../../private/include/adrv9025_init.h" +#include "../../private/include/adrv9025_rx.h" +#include "../../private/include/adrv9025_cpu.h" +#include "../../private/include/adrv9025_bf_rx.h" +#include "../../private/include/adrv9025_bf_orx.h" +#include "../../private/include/adrv9025_bf_core.h" +#include "../../private/include/adrv9025_shared_resource_manager.h" + +#ifdef _RELEASE_BUILD_ + #line __LINE__ "adi_adrv9025_rx.c" +#endif + +#define IF_INVALID_RX_CHANNEL_RETURN(rxChannel); \ +{\ + if ((rxChannel != ADI_ADRV9025_RX1) && \ + (rxChannel != ADI_ADRV9025_RX2) && \ + (rxChannel != ADI_ADRV9025_RX3) && \ + (rxChannel != ADI_ADRV9025_RX4)) \ + { \ + ADI_ERROR_REPORT(&device->common,ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, rxChannel, \ + "Invalid Rx Channel Parameter encountered"); \ + ADI_ERROR_RETURN(device->common.error.newAction); \ + } \ +} + +#define ADI_ADRV9025_NUM_GPIOS_IN_RX_GAIN_CTRL_PIN_FEATURE 2U +#define ADI_ADRV9025_NUM_GPIOS_IN_RX_AGC_HYBRID_FEATURE 1U +#define ADI_ADRV9025_NUM_GPIOS_IN_RX_EXT_CTRL_WORD_OUTPUT_FEATURE 8U +#define ADI_ADRV9025_NUM_GPIOS_IN_RX_DUALBAND_CTRL_WORD_OUTPUT_FEATURE 8U +#define ADI_ADRV9025_NUM_BYTES_PER_RX_GAIN_INDEX 8U + +int32_t adi_adrv9025_RxGainPinCtrlCfgSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxGainPinCfg_t* rxGainPinCtrlCfg) +{ + static const uint8_t MAX_GAIN_STEP = 7; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /*Check rxGainPinCtrlCfg pointer is not null*/ + ADI_NULL_PTR_RETURN(&device->common, + rxGainPinCtrlCfg); + + /*Check that the requested rxChannel is valid*/ + IF_INVALID_RX_CHANNEL_RETURN(rxChannel); + + /*Perform range check on config parameters only on enable*/ + if (rxGainPinCtrlCfg->enable > 0) + { + /*Check that gain increment step is between 0-7*/ + if (rxGainPinCtrlCfg->incStep > MAX_GAIN_STEP) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainPinCtrlCfg->incStep, + "Gain Increment Step exceeds limit for GPIO gain control config. Valid range 0-7"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that gain decrement step is between 0-7*/ + if (rxGainPinCtrlCfg->decStep > MAX_GAIN_STEP) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainPinCtrlCfg->decStep, + "Gain Decrement Step exceeds limit for GPIO gain control config. Valid range 0-7"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*GPIOs 0-15 are valid for GPIO gain control*/ + if (rxGainPinCtrlCfg->rxGainIncPin > ADI_ADRV9025_GPIO_15) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainPinCtrlCfg->decStep, + "Gain Increment pin for GPIO gain ctrl is out of range. Valid values GPIO_0 - GPIO_15"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*GPIOs 0-15 are valid for GPIO gain control*/ + if (rxGainPinCtrlCfg->rxGainDecPin > ADI_ADRV9025_GPIO_15) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainPinCtrlCfg->decStep, + "Gain Decrement pin for GPIO gain ctrl is out of range. Valid values GPIO_0 - GPIO_15"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that gain increment and decrement GPIO pins are not the same*/ + if (rxGainPinCtrlCfg->rxGainIncPin == rxGainPinCtrlCfg->rxGainDecPin) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainPinCtrlCfg->decStep, + "Gain Decrement pin cannot be same as Gain Increment pin for GPIO gain ctrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxGainPinCtrlCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxGainPinCfg_t* rxGainPinCtrlCfg) +{ + static const uint8_t MANUAL_GAIN_PIN_CTRL_ENABLE = 1; + static const uint8_t MANUAL_GAIN_PIN_CTRL_DISABLE = 0; + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_RX_GAIN_CTRL_PIN; + static const uint32_t RX_GAIN_CTRL_INC_PIN_INDEX = 0; + static const uint32_t RX_GAIN_CTRL_DEC_PIN_INDEX = 1; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfRxChanAddr_e rxChannelBaseAddr = ADRV9025_BF_ALL_RX_CHANNELS; + int32_t sharedResourceArr[ADI_ADRV9025_NUM_GPIOS_IN_RX_GAIN_CTRL_PIN_FEATURE] = {0}; + uint8_t resourceAcquisitionStatus = ADI_FAILURE; + uint8_t resourceReleaseStatus = ADI_FAILURE; + uint8_t currentRxGainCtrlIncPin = 0; + uint8_t currentRxGainCtrlDecPin = 0; + uint8_t rxGainCtrlPinModeEn = 0; + uint32_t incGpioPinMask = 0; + uint32_t decGpioPinMask = 0; + uint32_t i = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + rxGainPinCtrlCfg); + +#if ADI_ADRV9025_RX_RANGE_CHECK > 0 + adi_adrv9025_RxGainPinCtrlCfgSetRangeCheck(device, + rxChannel, + rxGainPinCtrlCfg); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /*Initialize the local shared resource array to invalid shared resource ID. This array is used to acquire multiple shared resources*/ + for (i = 0; i < ADI_ADRV9025_NUM_GPIOS_IN_RX_GAIN_CTRL_PIN_FEATURE; i++) + { + sharedResourceArr[i] = ADRV9025_SHARED_RESOURCE_INVALID; + } + + /*Resolve Rx Channel SPI address*/ + adrv9025_RxBitfieldAddressGet(device, + rxChannel, + &rxChannelBaseAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Read the current status of GPIO gain ctrl enable*/ + adrv9025_RxAgcManualGainPinControlBfGet(device, + rxChannelBaseAddr, + &rxGainCtrlPinModeEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to read manual GPIO gain control config bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Disable Rx Manual Gain Ctrl GPIO feature by default and release currently used GPIOs if Rx Gain Pin ctrl feature is enabled*/ + if (rxGainCtrlPinModeEn == MANUAL_GAIN_PIN_CTRL_ENABLE) + { + adrv9025_RxAgcManualGainPinControlBfSet(device, + rxChannelBaseAddr, + MANUAL_GAIN_PIN_CTRL_DISABLE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set manual GPIO gain control config bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Read Rx Gain Ctrl Decrement GPIO select */ + adrv9025_RxAgcDecGainGpioSelectBfGet(device, + rxChannelBaseAddr, + ¤tRxGainCtrlDecPin); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to read manual gain control decrement GPIO select register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Read Rx Gain Ctrl Increment GPIO select*/ + adrv9025_RxAgcIncGainGpioSelectBfGet(device, + rxChannelBaseAddr, + ¤tRxGainCtrlIncPin); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to read manual gain control increment GPIO select register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Attempt to Release Gain Ctrl Increment GPIO since it is a shared resource. This is to ensure that this feature is not accidentally releasing the GPIO + which is actively in use by another feature */ + sharedResourceArr[RX_GAIN_CTRL_INC_PIN_INDEX] = currentRxGainCtrlIncPin; + sharedResourceArr[RX_GAIN_CTRL_DEC_PIN_INDEX] = currentRxGainCtrlDecPin; + adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + ADI_ADRV9025_NUM_GPIOS_IN_RX_GAIN_CTRL_PIN_FEATURE, + THIS_FEATURE_ID, + &resourceReleaseStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to release GPIO shared resouce for GPIO gain ctrl Increment/Decrement Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceReleaseStatus, + "Error while attempting to release GPIO shared resouce for GPIO gain ctrl Increment/Decrement Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Set released GPIO pins as inputs since unused pins are supposed to be inputs*/ + incGpioPinMask = ((uint32_t)0x00000001 << (uint8_t)currentRxGainCtrlIncPin); + decGpioPinMask = ((uint32_t)0x00000001 << (uint8_t)currentRxGainCtrlDecPin); + recoveryAction = adi_adrv9025_GpioInputDirSet(device, + (incGpioPinMask | decGpioPinMask)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + recoveryAction, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set GPIO Increment/Decrement Pin inputs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (rxGainPinCtrlCfg->enable > 0) + { + /* Attempt to Acquire Gain Ctrl Increment GPIO since it is a shared resource. This is to ensure that this feature is not accidentally acquiring the GPIO + which is actively in use by another feature */ + sharedResourceArr[RX_GAIN_CTRL_INC_PIN_INDEX] = (uint32_t)rxGainPinCtrlCfg->rxGainIncPin; + sharedResourceArr[RX_GAIN_CTRL_DEC_PIN_INDEX] = (uint32_t)rxGainPinCtrlCfg->rxGainDecPin; + adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + ADI_ADRV9025_NUM_GPIOS_IN_RX_GAIN_CTRL_PIN_FEATURE, + THIS_FEATURE_ID, + &resourceAcquisitionStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to acquire GPIO shared resouce for GPIO gain ctrl Increment/Decrement Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceAcquisitionStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceAcquisitionStatus, + "Error while attempting to acquire GPIO shared resouce for GPIO gain ctrl Increment/Decrement Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Configure GPIO gain increment step*/ + recoveryAction = adrv9025_RxAgcIncrGainStepSizeBfSet(device, + rxChannelBaseAddr, + rxGainPinCtrlCfg->incStep); + adrv9025_RxGainCtrlPinReportError(device, + &sharedResourceArr[0], + recoveryAction, + "Error while attempting to set manual GPIO gain control Increment Step Size"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Configure GPIO gain decrement step*/ + adrv9025_RxAgcDecrGainStepSizeBfSet(device, + rxChannelBaseAddr, + rxGainPinCtrlCfg->decStep); + adrv9025_RxGainCtrlPinReportError(device, + &sharedResourceArr[0], + recoveryAction, + "Error while attempting to set manual GPIO gain control Decrement Step Size"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set ADRV9025 GPIO Directions for Gain ctrl GPIO Increment and Decrement pins*/ + incGpioPinMask = ((uint32_t)0x00000001 << (uint8_t)rxGainPinCtrlCfg->rxGainIncPin); + decGpioPinMask = ((uint32_t)0x00000001 << (uint8_t)rxGainPinCtrlCfg->rxGainDecPin); + recoveryAction = adi_adrv9025_GpioInputDirSet(device, + (incGpioPinMask | decGpioPinMask)); + recoveryAction = adrv9025_RxGainCtrlPinReportError(device, + &sharedResourceArr[0], + recoveryAction, + "Error while attempting to set manual GPIO gain control pin"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Rx Gain Ctrl Decrement GPIO select */ + adrv9025_RxAgcDecGainGpioSelectBfSet(device, + rxChannelBaseAddr, + rxGainPinCtrlCfg->rxGainDecPin); + adrv9025_RxGainCtrlPinReportError(device, + &sharedResourceArr[0], + recoveryAction, + "Error while attempting to set manual gain control decrement GPIO select register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Rx Gain Ctrl Increment GPIO select*/ + adrv9025_RxAgcIncGainGpioSelectBfSet(device, + rxChannelBaseAddr, + rxGainPinCtrlCfg->rxGainIncPin); + adrv9025_RxGainCtrlPinReportError(device, + &sharedResourceArr[0], + recoveryAction, + "Error while attempting to set manual gain control increment GPIO select register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Enable Manual GPIO gain control*/ + adrv9025_RxAgcManualGainPinControlBfSet(device, + rxChannelBaseAddr, + MANUAL_GAIN_PIN_CTRL_ENABLE); + adrv9025_RxGainCtrlPinReportError(device, + &sharedResourceArr[0], + recoveryAction, + "Error while attempting to set manual GPIO gain control config bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxGainPinCtrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxGainPinCfg_t* rxGainPinCtrlCfg) +{ + adrv9025_BfRxChanAddr_e rxChannelBaseAddr = ADRV9025_BF_ALL_RX_CHANNELS; + uint8_t rxGainDecPinBf = 0; + uint8_t rxGainIncPinBf = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /*Check rxGainPinCtrlCfg pointer is not null*/ + ADI_NULL_PTR_RETURN(&device->common, + rxGainPinCtrlCfg); + + /*Check that the requested rxChannel is valid*/ + IF_INVALID_RX_CHANNEL_RETURN(rxChannel); + + /*Resolve Rx Channel SPI address*/ + adrv9025_RxBitfieldAddressGet(device, + rxChannel, + &rxChannelBaseAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Read the Rx Manual Gain Ctrl GPIO Enable status*/ + adrv9025_RxAgcManualGainPinControlBfGet(device, + rxChannelBaseAddr, + &rxGainPinCtrlCfg->enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to read manual GPIO gain control config bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Read GPIO gain increment step*/ + adrv9025_RxAgcIncrGainStepSizeBfGet(device, + rxChannelBaseAddr, + &rxGainPinCtrlCfg->incStep); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to read manual GPIO gain control Increment Step Size"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Read GPIO gain decrement step*/ + adrv9025_RxAgcDecrGainStepSizeBfGet(device, + rxChannelBaseAddr, + &rxGainPinCtrlCfg->decStep); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to read manual GPIO gain control Decrement Step Size"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Read Rx Gain Ctrl Decrement GPIO select */ + adrv9025_RxAgcDecGainGpioSelectBfGet(device, + rxChannelBaseAddr, + &rxGainDecPinBf); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to read manual gain control decrement GPIO select register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Read Rx Gain Ctrl Increment GPIO select*/ + adrv9025_RxAgcIncGainGpioSelectBfGet(device, + rxChannelBaseAddr, + &rxGainIncPinBf); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to read manual gain control increment GPIO select register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Update rxGainIncPin and rxGainDecPin enums with read back value*/ + rxGainPinCtrlCfg->rxGainDecPin = (adi_adrv9025_GpioPinSel_e)rxGainDecPinBf; + rxGainPinCtrlCfg->rxGainIncPin = (adi_adrv9025_GpioPinSel_e)rxGainIncPinBf; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxGainTableExtCtrlPinsSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxExtCtrlPinOuputEnable_e extCtrlGpioChannelEnable) +{ + static const uint8_t GPIO_ANA_LOWER_NIBBLE_SRC_CTRL_DEFAULT = 0x00; + static const uint8_t GPIO_ANA_UPPER_NIBBLE_SRC_CTRL_MASK = 0x0F; + static const uint8_t GPIO_ANA_LOWER_NIBBLE_SRC_CTRL_MASK = 0x0F; + static const uint8_t GPIO_ANA_RX1_RX2_EXT_CTRL_GPIO_ENABLE = 0x04; + static const uint8_t GPIO_ANA_RX3_RX4_EXT_CTRL_GPIO_ENABLE = 0x04; + + uint8_t gpioAnalogSrcCtrl = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if ((extCtrlGpioChannelEnable != ADI_ADRV9025_DISABLE_RX1_RX2_EXT_CTRL_GPIOS) && + (extCtrlGpioChannelEnable != ADI_ADRV9025_ENABLE_RX1_RX2_EXT_CTRL_GPIOS) && + (extCtrlGpioChannelEnable != ADI_ADRV9025_DISABLE_RX3_RX4_EXT_CTRL_GPIOS) && + (extCtrlGpioChannelEnable != ADI_ADRV9025_ENABLE_RX3_RX4_EXT_CTRL_GPIOS) && + (extCtrlGpioChannelEnable != ADI_ADRV9025_DISABLE_RX1_RX2_RX3_RX4_EXT_CTRL_GPIOS) && + (extCtrlGpioChannelEnable != ADI_ADRV9025_ENABLE_RX1_RX2_RX3_RX4_EXT_CTRL_GPIOS)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + extCtrlGpioChannelEnable, + "Invalid Rx Channel enable Requested for external ctrl word output Analog GPIOs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((extCtrlGpioChannelEnable == ADI_ADRV9025_DISABLE_RX1_RX2_EXT_CTRL_GPIOS) || + (extCtrlGpioChannelEnable == ADI_ADRV9025_ENABLE_RX1_RX2_EXT_CTRL_GPIOS) || + (extCtrlGpioChannelEnable == ADI_ADRV9025_DISABLE_RX1_RX2_RX3_RX4_EXT_CTRL_GPIOS) || + (extCtrlGpioChannelEnable == ADI_ADRV9025_ENABLE_RX1_RX2_RX3_RX4_EXT_CTRL_GPIOS)) + { + adrv9025_CoreGpioAnalogLowerNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &gpioAnalogSrcCtrl); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Mask Upper Nibble Src Ctrl*/ + gpioAnalogSrcCtrl &= GPIO_ANA_LOWER_NIBBLE_SRC_CTRL_MASK; + + /*If Analog GPIO Source Ctrl is set to a feature other than Ext Attenuator Ctrl Output, throw an exception*/ + if ((gpioAnalogSrcCtrl != GPIO_ANA_LOWER_NIBBLE_SRC_CTRL_DEFAULT) && + (gpioAnalogSrcCtrl != GPIO_ANA_RX1_RX2_EXT_CTRL_GPIO_ENABLE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioAnalogSrcCtrl, + "Gain Table Ext Ctrl word output for channels Rx1, Rx2 selected but Analog GPIO Src Ctrl set to another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if ((extCtrlGpioChannelEnable == ADI_ADRV9025_DISABLE_RX3_RX4_EXT_CTRL_GPIOS) || + (extCtrlGpioChannelEnable == ADI_ADRV9025_ENABLE_RX3_RX4_EXT_CTRL_GPIOS) || + (extCtrlGpioChannelEnable == ADI_ADRV9025_DISABLE_RX1_RX2_RX3_RX4_EXT_CTRL_GPIOS) || + (extCtrlGpioChannelEnable == ADI_ADRV9025_ENABLE_RX1_RX2_RX3_RX4_EXT_CTRL_GPIOS)) + { + adrv9025_CoreGpioAnalogUpperNibbleSourceControlBfGet(device, + ADRV9025_BF_CORE, + &gpioAnalogSrcCtrl); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Mask Lower Nibble Src Ctrl*/ + gpioAnalogSrcCtrl &= GPIO_ANA_UPPER_NIBBLE_SRC_CTRL_MASK; + + /*If Analog GPIO Source Ctrl is set to a feature other than Ext Attenuator Ctrl Output, throw an exception*/ + if ((gpioAnalogSrcCtrl != GPIO_ANA_LOWER_NIBBLE_SRC_CTRL_DEFAULT) && + (gpioAnalogSrcCtrl != GPIO_ANA_RX3_RX4_EXT_CTRL_GPIO_ENABLE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioAnalogSrcCtrl, + "Gain Table Ext Ctrl word output for channels Rx3, Rx4 selected but Analog GPIO Src Ctrl set to another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxGainTableExtCtrlPinsSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxExtCtrlPinOuputEnable_e extCtrlGpioChannelEnable) +{ + static const uint8_t GPIO_ANA_UPPER_NIBBLE_SRC_CTRL_DEFAULT = 0x00; + static const uint8_t GPIO_ANA_LOWER_NIBBLE_SRC_CTRL_DEFAULT = 0x00; + static const uint8_t GPIO_ANA_RX1_RX2_EXT_CTRL_GPIO_ENABLE = 0x04; + static const uint8_t GPIO_ANA_RX3_RX4_EXT_CTRL_GPIO_ENABLE = 0x04; + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_RX_EXT_CTRL_WORD_OUTPUT; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t gpioAnalogInputOutputMask = 0; + int32_t sharedResourceArr[ADI_ADRV9025_NUM_GPIOS_IN_RX_EXT_CTRL_WORD_OUTPUT_FEATURE] = {0}; + uint8_t resourceAcquisitionStatus = ADI_FAILURE; + uint8_t resourceReleaseStatus = ADI_FAILURE; + uint8_t numSharedResources = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + +#if ADI_ADRV9025_RX_RANGE_CHECK > 0 + adi_adrv9025_RxGainTableExtCtrlPinsSetRangeCheck(device, + extCtrlGpioChannelEnable); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /*Resolve Shared Analog GPIO Resources depending on channels for which ext ctrl output enable/disable is requested*/ + if ((extCtrlGpioChannelEnable == ADI_ADRV9025_DISABLE_RX1_RX2_RX3_RX4_EXT_CTRL_GPIOS) || + (extCtrlGpioChannelEnable == ADI_ADRV9025_ENABLE_RX1_RX2_RX3_RX4_EXT_CTRL_GPIOS)) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_ANA_00; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_ANA_01; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_ANA_02; + sharedResourceArr[3] = ADI_ADRV9025_GPIO_ANA_03; + sharedResourceArr[4] = ADI_ADRV9025_GPIO_ANA_04; + sharedResourceArr[5] = ADI_ADRV9025_GPIO_ANA_05; + sharedResourceArr[6] = ADI_ADRV9025_GPIO_ANA_06; + sharedResourceArr[7] = ADI_ADRV9025_GPIO_ANA_07; + numSharedResources = 8; + } + else if ((extCtrlGpioChannelEnable == ADI_ADRV9025_DISABLE_RX1_RX2_EXT_CTRL_GPIOS) || + (extCtrlGpioChannelEnable == ADI_ADRV9025_ENABLE_RX1_RX2_EXT_CTRL_GPIOS)) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_ANA_00; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_ANA_01; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_ANA_02; + sharedResourceArr[3] = ADI_ADRV9025_GPIO_ANA_03; + numSharedResources = 4; + } + else if ((extCtrlGpioChannelEnable == ADI_ADRV9025_DISABLE_RX3_RX4_EXT_CTRL_GPIOS) || + (extCtrlGpioChannelEnable == ADI_ADRV9025_ENABLE_RX3_RX4_EXT_CTRL_GPIOS)) + { + sharedResourceArr[0] = ADI_ADRV9025_GPIO_ANA_04; + sharedResourceArr[1] = ADI_ADRV9025_GPIO_ANA_05; + sharedResourceArr[2] = ADI_ADRV9025_GPIO_ANA_06; + sharedResourceArr[3] = ADI_ADRV9025_GPIO_ANA_07; + numSharedResources = 4; + } + + if ((extCtrlGpioChannelEnable == ADI_ADRV9025_DISABLE_RX1_RX2_EXT_CTRL_GPIOS) || + (extCtrlGpioChannelEnable == ADI_ADRV9025_DISABLE_RX1_RX2_RX3_RX4_EXT_CTRL_GPIOS)) + { + /*Release Shared Analog GPIOs*/ + adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, + &sharedResourceArr[0], + numSharedResources, + THIS_FEATURE_ID, + &resourceReleaseStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to release shared Analog GPIO during disabling of Rx1, Rx2 ext ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceReleaseStatus, + "Error while attempting to release shared Analog GPIO during disabling of Rx1, Rx2 ext ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Set GPIO_ANA[3:0] to input on disable request*/ + gpioAnalogInputOutputMask = (((uint8_t)1 << (uint8_t)ADI_ADRV9025_GPIO_ANA_00) | + ((uint8_t)1 << (uint8_t)ADI_ADRV9025_GPIO_ANA_01) | + ((uint8_t)1 << (uint8_t)ADI_ADRV9025_GPIO_ANA_02) | + ((uint8_t)1 << (uint8_t)ADI_ADRV9025_GPIO_ANA_03)); + adi_adrv9025_GpioAnalogInputDirSet(device, + gpioAnalogInputOutputMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set Analog GPIO lower nibble direction ctrl to default during disabling of Rx1, Rx2 ext ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Analog GPIO Src Ctrl Lower Nibble to default*/ + adrv9025_CoreGpioAnalogLowerNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + GPIO_ANA_LOWER_NIBBLE_SRC_CTRL_DEFAULT); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set Analog GPIO lower nibble source ctrl to default during disabling of Rx1, Rx2 ext ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((extCtrlGpioChannelEnable == ADI_ADRV9025_DISABLE_RX3_RX4_EXT_CTRL_GPIOS) || + (extCtrlGpioChannelEnable == ADI_ADRV9025_DISABLE_RX1_RX2_RX3_RX4_EXT_CTRL_GPIOS)) + { + /*Release Shared Analog GPIOs*/ + adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, + &sharedResourceArr[0], + numSharedResources, + THIS_FEATURE_ID, + &resourceReleaseStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to release shared Analog GPIO during disabling of Rx3, Rx4 ext ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceReleaseStatus, + "Error while attempting to release shared Analog GPIO during disabling of Rx3, Rx4 ext ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Set GPIO_ANA[7:4] to input on disabling*/ + gpioAnalogInputOutputMask = (((uint8_t)1 << (uint8_t)ADI_ADRV9025_GPIO_ANA_04) | + ((uint8_t)1 << (uint8_t)ADI_ADRV9025_GPIO_ANA_05) | + ((uint8_t)1 << (uint8_t)ADI_ADRV9025_GPIO_ANA_06) | + ((uint8_t)1 << (uint8_t)ADI_ADRV9025_GPIO_ANA_07)); + adi_adrv9025_GpioAnalogInputDirSet(device, + gpioAnalogInputOutputMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set Analog GPIO lower nibble direction ctrl to default during disabling of Rx3, Rx4 ext ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Analog GPIO Src Ctrl Lower Nibble to default*/ + adrv9025_CoreGpioAnalogUpperNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + GPIO_ANA_UPPER_NIBBLE_SRC_CTRL_DEFAULT); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set Analog GPIO lower nibble source ctrl to default during disabling of Rx3, Rx4 ext ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((extCtrlGpioChannelEnable == ADI_ADRV9025_ENABLE_RX1_RX2_EXT_CTRL_GPIOS) || + (extCtrlGpioChannelEnable == ADI_ADRV9025_ENABLE_RX1_RX2_RX3_RX4_EXT_CTRL_GPIOS)) + { + /*Acquire Shared Analog GPIOs*/ + adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, + &sharedResourceArr[0], + numSharedResources, + THIS_FEATURE_ID, + &resourceAcquisitionStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to acquire shared Analog GPIO during enabling of Rx1, Rx2 ext ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceAcquisitionStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceAcquisitionStatus, + "Error while attempting to acquire shared Analog GPIO during enabling of Rx1, Rx2 ext ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Set GPIO_ANA[3:0] to output on enable request*/ + gpioAnalogInputOutputMask = (((uint8_t)1 << (uint8_t)ADI_ADRV9025_GPIO_ANA_00) | + ((uint8_t)1 << (uint8_t)ADI_ADRV9025_GPIO_ANA_01) | + ((uint8_t)1 << (uint8_t)ADI_ADRV9025_GPIO_ANA_02) | + ((uint8_t)1 << (uint8_t)ADI_ADRV9025_GPIO_ANA_03)); + adi_adrv9025_GpioAnalogOutputDirSet(device, + gpioAnalogInputOutputMask); + adrv9025_RxExtCtrlPinReportError(device, + &sharedResourceArr[0], + numSharedResources, + recoveryAction, + "Error while attempting to set Analog GPIO lower nibble direction ctrl to output during enabling of Rx1, Rx2 ext ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Analog GPIO Src Ctrl Lower Nibble to Ext Attenuator Ctrl Output*/ + adrv9025_CoreGpioAnalogLowerNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + GPIO_ANA_RX1_RX2_EXT_CTRL_GPIO_ENABLE); + adrv9025_RxExtCtrlPinReportError(device, + &sharedResourceArr[0], + numSharedResources, + recoveryAction, + "Error while attempting to set Analog GPIO lower nibble source ctrl to ext attenutaor ctrl during enabling of Rx1, Rx2 ext ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((extCtrlGpioChannelEnable == ADI_ADRV9025_ENABLE_RX3_RX4_EXT_CTRL_GPIOS) || + (extCtrlGpioChannelEnable == ADI_ADRV9025_ENABLE_RX1_RX2_RX3_RX4_EXT_CTRL_GPIOS)) + { + /*Acquire Shared Analog GPIOs*/ + adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, + &sharedResourceArr[0], + numSharedResources, + THIS_FEATURE_ID, + &resourceAcquisitionStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to acquire shared Analog GPIO during enabling of Rx3, Rx4 ext ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceAcquisitionStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceAcquisitionStatus, + "Error while attempting to acquire shared Analog GPIO during enabling of Rx3, Rx4 ext ctrl output. Please check if the GPIOs in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Set GPIO_ANA[7:4] to output on enabling*/ + gpioAnalogInputOutputMask = (((uint8_t)1 << (uint8_t)ADI_ADRV9025_GPIO_ANA_04) | + ((uint8_t)1 << (uint8_t)ADI_ADRV9025_GPIO_ANA_05) | + ((uint8_t)1 << (uint8_t)ADI_ADRV9025_GPIO_ANA_06) | + ((uint8_t)1 << (uint8_t)ADI_ADRV9025_GPIO_ANA_07)); + adi_adrv9025_GpioAnalogOutputDirSet(device, + gpioAnalogInputOutputMask); + adrv9025_RxExtCtrlPinReportError(device, + &sharedResourceArr[0], + numSharedResources, + recoveryAction, + "Error while attempting to set Analog GPIO lower nibble direction ctrl to ext attenuator ctrl during enabling of Rx3, Rx4 ext ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Analog GPIO Src Ctrl Lower Nibble to default*/ + adrv9025_CoreGpioAnalogUpperNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + GPIO_ANA_RX3_RX4_EXT_CTRL_GPIO_ENABLE); + adrv9025_RxExtCtrlPinReportError(device, + &sharedResourceArr[0], + numSharedResources, + recoveryAction, + "Error while attempting to set Analog GPIO lower nibble source ctrl to ext attenuator ctrl during enabling of Rx3, Rx4 ext ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxGainTableWriteRangeCheck(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint8_t gainIndexOffset, + adi_adrv9025_RxGainTableRow_t gainTableRow[], + uint16_t arraySize) +{ + static const uint8_t MAX_EXT_CTRL_WORD = 3; + static const int16_t MIN_DIG_GAIN = -360; /*Dig gain is in the range -18dB to 50db*/ + static const int16_t MAX_DIG_GAIN = 1000; /*Dig gain is in the range -18dB to 50db*/ + + uint16_t gainIndex = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /*Check gainTableRow is not null*/ + ADI_NULL_PTR_RETURN(&device->common, + gainTableRow); + + /*Check the no. of gain indices parameter is not 0*/ + if (arraySize == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + arraySize, + "arraySize parameter is 0. Valid values from 1 - 256"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that the gain index offset is within range*/ + if ((gainIndexOffset < ADI_ADRV9025_MIN_RX_GAIN_TABLE_INDEX) || + (gainIndexOffset > ADI_ADRV9025_START_RX_GAIN_INDEX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gainIndexOffset, + "Invalid gainIndexOffset. Parameter gainIndexOffset should be in the range ADI_ADRV9025_MIN_RX_GAIN_TABLE_INDEX to ADI_ADRV9025_START_RX_GAIN_INDEX"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check the no. of gain indices parameter is valid*/ + if (arraySize > ((gainIndexOffset - ADI_ADRV9025_MIN_RX_GAIN_TABLE_INDEX) + 1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + arraySize, + "gainTableRow arraySize exceeds the limit. Valid range ADI_ADRV9025_MIN_RX_GAIN_TABLE_INDEX to gainIndexOffset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that rxChannelMask is valid*/ + if (rxChannelMask == ADI_ADRV9025_RXOFF) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "Invalid Rx Channel mask parameter. Valid Rx channel masks include Rx1-Rx4 and ORx1-ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (rxChannelMask > (ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4 | + ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2 | ADI_ADRV9025_ORX3 | ADI_ADRV9025_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "Invalid Rx Channel mask parameter. Valid Rx channel masks include Rx1-Rx4 and ORx1-ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that if Rx gain table is required to be loaded, Rx Profile is valid*/ + if (((rxChannelMask & (uint32_t)ADI_ADRV9025_RX1) == (uint32_t)ADI_ADRV9025_RX1) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX2) == (uint32_t)ADI_ADRV9025_RX2) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX3) == (uint32_t)ADI_ADRV9025_RX3) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX4) == (uint32_t)ADI_ADRV9025_RX4)) + { + if ((device->devStateInfo.profilesValid & ADI_ADRV9025_RX_PROFILE_VALID) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "Rx gain table selected for programming but Rx profile is invalid in device structure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Check that if ORx gain table is required to be loaded, ORx Profile is valid*/ + if (((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX1) == (uint32_t)ADI_ADRV9025_ORX1) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX2) == (uint32_t)ADI_ADRV9025_ORX2) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX3) == (uint32_t)ADI_ADRV9025_ORX3) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX4) == (uint32_t)ADI_ADRV9025_ORX4)) + { + if ((device->devStateInfo.profilesValid & ADI_ADRV9025_ORX_PROFILE_VALID) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "ORx gain table selected for programming but ORx profile is invalid in device structure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Range check individual gain table row entries*/ + for (gainIndex = 0; gainIndex < arraySize; gainIndex++) + { + /*Check that {TIA GAIN, ADC CTRL} are 0*/ + if (gainTableRow[gainIndex].adcTiaGain != 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gainTableRow[gainIndex].adcTiaGain, + "Rx Gain Table adcTiaGain parameter exceeds the limit. The only allowed value is 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that EXT_CTRL is in the range {0,1,2,3}*/ + if (gainTableRow[gainIndex].extControl > MAX_EXT_CTRL_WORD) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gainTableRow[gainIndex].extControl, + "Rx Gain Table extControl parameter exceeds the limit. Allowed values are 0,1,2,3"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that digital gain is in the range -18dB to 50dB*/ + if ((gainTableRow[gainIndex].digGain < MIN_DIG_GAIN) || + (gainTableRow[gainIndex].digGain > MAX_DIG_GAIN)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gainTableRow[gainIndex].digGain, + "Rx Gain Table digGain parameter exceeds the limit. Allowed values between -18dB to 50dB(-360 to +1000)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxGainTableWrite(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint8_t gainIndexOffset, + adi_adrv9025_RxGainTableRow_t gainTableRow[], + uint16_t arraySize) +{ + uint32_t baseIndex = 0; + uint32_t baseAddress = 0; + uint16_t numGainIndicesToWrite = arraySize; + /*Maximum Array Size = Max Gain Table Size x Bytes Per Gain Table Entry*/ + static uint8_t armDmaData[((ADI_ADRV9025_MAX_GAIN_TABLE_INDEX - ADI_ADRV9025_MIN_GAIN_TABLE_INDEX) + 1) * ADI_ADRV9025_NUM_BYTES_PER_RX_GAIN_INDEX] = + {0}; + static const uint8_t DEC_POWER_CONFIG1 = + 0x09; /* dec_power_log_shift | dec_power_enable_meas */ + static const uint8_t DIGITAL_GAIN_CONFIG2 = + 0x01; /* digital_gain_enable */ + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /*Check gainTableRow is not null*/ + ADI_NULL_PTR_RETURN(&device->common, + gainTableRow); + +#if ADI_ADRV9025_RX_RANGE_CHECK > 0 + adi_adrv9025_RxGainTableWriteRangeCheck(device, + rxChannelMask, + gainIndexOffset, + gainTableRow, + numGainIndicesToWrite); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /*Calculate base index for the config*/ + baseIndex = (gainIndexOffset - (numGainIndicesToWrite - 1)); + + /*Format Gain Table Entries*/ + adrv9025_RxGainTableFormat(device, + gainTableRow, + &armDmaData[0], + numGainIndicesToWrite); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Resolve the RX Channel SRAM to program*/ + /*If Rx1 Channel Mask Set by user for this config, load Rx1 gain table*/ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX1) == (uint32_t)ADI_ADRV9025_RX1) + { + /*Resolve Rx1 Gain Table SRAM load start address*/ + baseAddress = (uint32_t)ADI_ADRV9025_RX1_GAIN_TABLE_BASEADDR + (baseIndex * ADI_ADRV9025_NUM_BYTES_PER_RX_GAIN_INDEX); + /*Write to the SRAM via ARM DMA*/ + adrv9025_CpuDmaMemWrite(device, + baseAddress, + &armDmaData[0], + (uint32_t)(numGainIndicesToWrite * ADI_ADRV9025_NUM_BYTES_PER_RX_GAIN_INDEX), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error writing to ARM DMA while loading Rx Gain Table @ base address 0x80800000"); + ADI_ERROR_RETURN(device->common.error.newAction); + + ADRV9025_SPIWRITEBYTE("RX1_DEC_POWR_CONFIG_1", + (ADRV9025_ADDR_CH0_RX + ADRV9025_ADDR_RX_DEC_POWER_CONFIG1_OFFSET), + DEC_POWER_CONFIG1); + + ADRV9025_SPIWRITEBYTE("RX1_DIGITAL_GAIN_CONFIG2", + (ADRV9025_ADDR_CH0_RX + ADRV9025_ADDR_RX_DIGITAL_GAIN_CONFIG2_OFFSET), + DIGITAL_GAIN_CONFIG2); + } + + /*If Rx2 Channel Mask Set by user for this config, load Rx2 gain table*/ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX2) == (uint32_t)ADI_ADRV9025_RX2) + { + /*Resolve Rx2 Gain Table SRAM load start address*/ + baseAddress = (uint32_t)ADI_ADRV9025_RX2_GAIN_TABLE_BASEADDR + (baseIndex * ADI_ADRV9025_NUM_BYTES_PER_RX_GAIN_INDEX); + /*Write to the SRAM via ARM DMA*/ + adrv9025_CpuDmaMemWrite(device, + baseAddress, + &armDmaData[0], + (uint32_t)(numGainIndicesToWrite * ADI_ADRV9025_NUM_BYTES_PER_RX_GAIN_INDEX), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error writing to ARM DMA while loading Rx Gain Table @ base address 0x88800000"); + ADI_ERROR_RETURN(device->common.error.newAction); + + ADRV9025_SPIWRITEBYTE("RX2_DEC_POWR_CONFIG_1", + (ADRV9025_ADDR_CH1_RX + ADRV9025_ADDR_RX_DEC_POWER_CONFIG1_OFFSET), + DEC_POWER_CONFIG1); + + ADRV9025_SPIWRITEBYTE("RX2_DIGITAL_GAIN_CONFIG2", + (ADRV9025_ADDR_CH1_RX + ADRV9025_ADDR_RX_DIGITAL_GAIN_CONFIG2_OFFSET), + DIGITAL_GAIN_CONFIG2); + } + + /*If Rx3 Channel Mask Set by user for this config, load Rx3 gain table*/ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX3) == (uint32_t)ADI_ADRV9025_RX3) + { + /*Resolve Rx3 Gain Table SRAM load start address*/ + baseAddress = (uint32_t)ADI_ADRV9025_RX3_GAIN_TABLE_BASEADDR + (baseIndex * ADI_ADRV9025_NUM_BYTES_PER_RX_GAIN_INDEX); + /*Write to the SRAM via ARM DMA*/ + adrv9025_CpuDmaMemWrite(device, + baseAddress, + &armDmaData[0], + (uint32_t)(numGainIndicesToWrite * ADI_ADRV9025_NUM_BYTES_PER_RX_GAIN_INDEX), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error writing to ARM DMA while loading Rx Gain Table @ base address 0x90800000"); + ADI_ERROR_RETURN(device->common.error.newAction); + + ADRV9025_SPIWRITEBYTE("RX3_DEC_POWR_CONFIG_1", + (ADRV9025_ADDR_CH2_RX + ADRV9025_ADDR_RX_DEC_POWER_CONFIG1_OFFSET), + DEC_POWER_CONFIG1); + + ADRV9025_SPIWRITEBYTE("RX3_DIGITAL_GAIN_CONFIG2", + (ADRV9025_ADDR_CH2_RX + ADRV9025_ADDR_RX_DIGITAL_GAIN_CONFIG2_OFFSET), + DIGITAL_GAIN_CONFIG2); + } + + /*If Rx4 Channel Mask Set by user for this config, load Rx4 gain table*/ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX4) == (uint32_t)ADI_ADRV9025_RX4) + { + /*Resolve Rx4 Gain Table SRAM load start address*/ + baseAddress = (uint32_t)ADI_ADRV9025_RX4_GAIN_TABLE_BASEADDR + (baseIndex * ADI_ADRV9025_NUM_BYTES_PER_RX_GAIN_INDEX); + /*Write to the SRAM via ARM DMA*/ + adrv9025_CpuDmaMemWrite(device, + baseAddress, + &armDmaData[0], + (uint32_t)(numGainIndicesToWrite * ADI_ADRV9025_NUM_BYTES_PER_RX_GAIN_INDEX), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error writing to ARM DMA while loading Rx Gain Table @ base address 0x98800000"); + ADI_ERROR_RETURN(device->common.error.newAction); + + ADRV9025_SPIWRITEBYTE("RX4_DEC_POWR_CONFIG_1", + (ADRV9025_ADDR_CH3_RX + ADRV9025_ADDR_RX_DEC_POWER_CONFIG1_OFFSET), + DEC_POWER_CONFIG1); + + ADRV9025_SPIWRITEBYTE("RX3_DIGITAL_GAIN_CONFIG2", + (ADRV9025_ADDR_CH3_RX + ADRV9025_ADDR_RX_DIGITAL_GAIN_CONFIG2_OFFSET), + DIGITAL_GAIN_CONFIG2); + } + + /*If ORx1/ORx2 Channel Mask Set by user for this config, load ORx1/ORx2 gain table*/ + if (((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX1) == (uint32_t)ADI_ADRV9025_ORX1) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX2) == (uint32_t)ADI_ADRV9025_ORX2)) + { + /*Resolve ORx1 Gain Table SRAM load start address*/ + baseAddress = (uint32_t)ADI_ADRV9025_ORX1_ORX2_GAIN_TABLE_BASEADDR + (baseIndex * ADI_ADRV9025_NUM_BYTES_PER_RX_GAIN_INDEX); + /*Write to the SRAM via ARM DMA*/ + adrv9025_CpuDmaMemWrite(device, + baseAddress, + &armDmaData[0], + (uint32_t)(numGainIndicesToWrite * ADI_ADRV9025_NUM_BYTES_PER_RX_GAIN_INDEX), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error writing to ARM DMA while loading ORx Gain Table @ base address 0xC0800000"); + ADI_ERROR_RETURN(device->common.error.newAction); + + ADRV9025_SPIWRITEBYTE("ORX1_DEC_POWR_CONFIG_1", + (ADRV9025_ADDR_CH0_ORX + ADRV9025_ADDR_ORX_DEC_POWER_CONFIG1_OFFSET), + DEC_POWER_CONFIG1); + + ADRV9025_SPIWRITEBYTE("ORX1_DIGITAL_GAIN_CONFIG2", + (ADRV9025_ADDR_CH0_ORX + ADRV9025_ADDR_ORX_DIGITAL_GAIN_CONFIG2_OFFSET), + DIGITAL_GAIN_CONFIG2); + } + + /*If ORx3/ORx4 Channel Mask Set by user for this config, load ORx3/ORx4 gain table*/ + if (((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX3) == (uint32_t)ADI_ADRV9025_ORX3) || + ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX4) == (uint32_t)ADI_ADRV9025_ORX4)) + { + /*Resolve ORx2 Gain Table SRAM load start address*/ + baseAddress = (uint32_t)ADI_ADRV9025_ORX3_ORX4_GAIN_TABLE_BASEADDR + (baseIndex * ADI_ADRV9025_NUM_BYTES_PER_RX_GAIN_INDEX); + /*Write to the SRAM via ARM DMA*/ + adrv9025_CpuDmaMemWrite(device, + baseAddress, + &armDmaData[0], + (uint32_t)(numGainIndicesToWrite * ADI_ADRV9025_NUM_BYTES_PER_RX_GAIN_INDEX), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error writing to ARM DMA while loading ORx Gain Table @ base address 0xE0800000"); + ADI_ERROR_RETURN(device->common.error.newAction); + + ADRV9025_SPIWRITEBYTE("ORX2_DEC_POWR_CONFIG_1", + (ADRV9025_ADDR_CH1_ORX + ADRV9025_ADDR_ORX_DEC_POWER_CONFIG1_OFFSET), + DEC_POWER_CONFIG1); + + ADRV9025_SPIWRITEBYTE("ORX2_DIGITAL_GAIN_CONFIG2", + (ADRV9025_ADDR_CH1_ORX + ADRV9025_ADDR_ORX_DIGITAL_GAIN_CONFIG2_OFFSET), + DIGITAL_GAIN_CONFIG2); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxMinMaxGainIndexSetRangeCheck(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint8_t minGainIndex, + uint8_t maxGainIndex) +{ + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /*Check that rxChannelMask is valid*/ + if (rxChannelMask == ADI_ADRV9025_RXOFF) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "Invalid Rx Channel mask parameter. Valid Rx channel masks include Rx1-Rx4 and ORx1-ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (rxChannelMask > (ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4 | + ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2 | ADI_ADRV9025_ORX3 | ADI_ADRV9025_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "Invalid Rx Channel mask parameter. Valid Rx channel masks include Rx1-Rx4 and ORx1-ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that requested min gain index does not exceed max gain index*/ + if (minGainIndex >= maxGainIndex) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "minGainIndex should be less than maxGainIndex"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that requested min gain index is not less than the absolute min gain index possible for this device*/ + if (minGainIndex < ADI_ADRV9025_MIN_GAIN_TABLE_INDEX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "minGainIndex should be greater than or equal to ADI_ADRV9025_MIN_GAIN_TABLE_INDEX"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that requested max gain index is not greater than the absolute max gain index possible for this device*/ + if (maxGainIndex > ADI_ADRV9025_MAX_GAIN_TABLE_INDEX) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "maxGainIndex should be less than or equal to ADI_ADRV9025_MAX_GAIN_TABLE_INDEX"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxMinMaxGainIndexSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + uint8_t minGainIndex, + uint8_t maxGainIndex) +{ + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + +#if ADI_ADRV9025_RX_RANGE_CHECK > 0 + adi_adrv9025_RxMinMaxGainIndexSetRangeCheck(device, + rxChannelMask, + minGainIndex, + maxGainIndex); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /*Update device gain table min and max gain indices*/ + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX1) == (uint32_t)ADI_ADRV9025_RX1) + { + device->devStateInfo.gainIndexes.rx1MaxGainIndex = maxGainIndex; + device->devStateInfo.gainIndexes.rx1MinGainIndex = minGainIndex; + } + + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX2) == (uint32_t)ADI_ADRV9025_RX2) + { + device->devStateInfo.gainIndexes.rx2MaxGainIndex = maxGainIndex; + device->devStateInfo.gainIndexes.rx2MinGainIndex = minGainIndex; + } + + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX3) == (uint32_t)ADI_ADRV9025_RX3) + { + device->devStateInfo.gainIndexes.rx3MaxGainIndex = maxGainIndex; + device->devStateInfo.gainIndexes.rx3MinGainIndex = minGainIndex; + } + + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_RX4) == (uint32_t)ADI_ADRV9025_RX4) + { + device->devStateInfo.gainIndexes.rx4MaxGainIndex = maxGainIndex; + device->devStateInfo.gainIndexes.rx4MinGainIndex = minGainIndex; + } + + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX1) == (uint32_t)ADI_ADRV9025_ORX1) + { + device->devStateInfo.gainIndexes.orx1orx2MaxGainIndex = maxGainIndex; + device->devStateInfo.gainIndexes.orx1orx2MinGainIndex = minGainIndex; + } + + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX2) == (uint32_t)ADI_ADRV9025_ORX2) + { + device->devStateInfo.gainIndexes.orx1orx2MaxGainIndex = maxGainIndex; + device->devStateInfo.gainIndexes.orx1orx2MinGainIndex = minGainIndex; + } + + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX3) == (uint32_t)ADI_ADRV9025_ORX3) + { + device->devStateInfo.gainIndexes.orx3orx4MaxGainIndex = maxGainIndex; + device->devStateInfo.gainIndexes.orx3orx4MinGainIndex = minGainIndex; + } + + if ((rxChannelMask & (uint32_t)ADI_ADRV9025_ORX4) == (uint32_t)ADI_ADRV9025_ORX4) + { + device->devStateInfo.gainIndexes.orx3orx4MaxGainIndex = maxGainIndex; + device->devStateInfo.gainIndexes.orx3orx4MinGainIndex = minGainIndex; + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxGainTableReadRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint8_t gainIndexOffset, + adi_adrv9025_RxGainTableRow_t gainTableRow[], + uint16_t arraySize, + uint16_t* numGainIndicesRead) +{ + UNUSED_PARA(numGainIndicesRead); + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /*Check that gainTableRowPtr is not null*/ + ADI_NULL_PTR_RETURN(&device->common, + gainTableRow); + + /*Check that the channel requested is valid*/ + if ((rxChannel != ADI_ADRV9025_RX1) && + (rxChannel != ADI_ADRV9025_RX2) && + (rxChannel != ADI_ADRV9025_RX3) && + (rxChannel != ADI_ADRV9025_RX4) && + (rxChannel != ADI_ADRV9025_ORX1) && + (rxChannel != ADI_ADRV9025_ORX2) && + (rxChannel != ADI_ADRV9025_ORX3) && + (rxChannel != ADI_ADRV9025_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel Requested for gain table read. Valid Rx channels include Rx1-Rx4, ORx1-ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((arraySize > ((ADI_ADRV9025_MAX_GAIN_TABLE_INDEX - ADI_ADRV9025_MIN_GAIN_TABLE_INDEX) + 1)) || + (arraySize == 0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + arraySize, + "Invalid arraySize parameter requested for Rx Channel Gain Table Read. Valid range is 1-256"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that gainIndexOffset is correct*/ + switch (rxChannel) + { + case ADI_ADRV9025_RX1: + { + if ((gainIndexOffset > device->devStateInfo.gainIndexes.rx1MaxGainIndex) || + (gainIndexOffset < device->devStateInfo.gainIndexes.rx1MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gainIndexOffset, + "Invalid gainIndexOffset. Parameter gainIndexOffset should be within Rx1 min and max gain index range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + case ADI_ADRV9025_RX2: + { + if ((gainIndexOffset > device->devStateInfo.gainIndexes.rx2MaxGainIndex) || + (gainIndexOffset < device->devStateInfo.gainIndexes.rx2MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gainIndexOffset, + "Invalid gainIndexOffset. Parameter gainIndexOffset should be within Rx2 min and max gain index range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + break; + } + + case ADI_ADRV9025_RX3: + { + if ((gainIndexOffset > device->devStateInfo.gainIndexes.rx3MaxGainIndex) || + (gainIndexOffset < device->devStateInfo.gainIndexes.rx3MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gainIndexOffset, + "Invalid gainIndexOffset. Parameter gainIndexOffset should be within Rx3 min and max gain index range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + case ADI_ADRV9025_RX4: + { + if ((gainIndexOffset > device->devStateInfo.gainIndexes.rx4MaxGainIndex) || + (gainIndexOffset < device->devStateInfo.gainIndexes.rx4MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gainIndexOffset, + "Invalid gainIndexOffset. Parameter gainIndexOffset should be within Rx4 min and max gain index range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + case ADI_ADRV9025_ORX1: /*Fall Through*/ + case ADI_ADRV9025_ORX2: + { + if ((gainIndexOffset > device->devStateInfo.gainIndexes.orx1orx2MaxGainIndex) || + (gainIndexOffset < device->devStateInfo.gainIndexes.orx1orx2MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gainIndexOffset, + "Invalid gainIndexOffset. Parameter gainIndexOffset should be within ORx1/ORx2 min and max gain index range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + case ADI_ADRV9025_ORX3: /*Fall Through*/ + case ADI_ADRV9025_ORX4: + { + if ((gainIndexOffset > device->devStateInfo.gainIndexes.orx3orx4MaxGainIndex) || + (gainIndexOffset < device->devStateInfo.gainIndexes.orx3orx4MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gainIndexOffset, + "Invalid gainIndexOffset. Parameter gainIndexOffset should be within ORx3/ORx4 min and max gain index range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + break; + } + + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel Requested for gain table read. Valid Rx channels include Rx1-Rx4, ORx1-ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxGainTableRead(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint8_t gainIndexOffset, + adi_adrv9025_RxGainTableRow_t gainTableRow[], + uint16_t arraySize, + uint16_t* numGainIndicesRead) +{ + static const uint32_t NUM_BYTES_PER_GAIN_INDEX = 8; + static const uint32_t ARM_DMA_AUTO_INCR = 1; + + uint32_t baseAddress = 0; + uint16_t maxReadGainIndices = arraySize; + uint16_t numGainIndicesReadVal = 0; + /*Maximum Array Size = Max Gain Table Size x Bytes Per Gain Table Entry*/ + static uint8_t armDmaData[((ADI_ADRV9025_MAX_GAIN_TABLE_INDEX - ADI_ADRV9025_MIN_GAIN_TABLE_INDEX) + 1) * 8] = {0}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /*Check that gainTableRowPtr is not null*/ + ADI_NULL_PTR_RETURN(&device->common, + gainTableRow); + +#if ADI_ADRV9025_RX_RANGE_CHECK > 0 + adi_adrv9025_RxGainTableReadRangeCheck(device, + rxChannel, + gainIndexOffset, + gainTableRow, + maxReadGainIndices, + numGainIndicesRead); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /*Calculate no. of indices to read and the base address for the config*/ + adrv9025_RxGainTableReadParamsCompute(device, + rxChannel, + maxReadGainIndices, + gainIndexOffset, + &numGainIndicesReadVal, + &baseAddress); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Read Gain Table Data for the requested channel via ARM DMA*/ + adrv9025_CpuDmaMemRead(device, + baseAddress, + &armDmaData[0], + (numGainIndicesReadVal * NUM_BYTES_PER_GAIN_INDEX), + ARM_DMA_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error Reading Gain Table ARM DMA"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Parse gain table data obtained in ARM DMA data format to an rx gain table row entry datastructure memory*/ + adrv9025_RxGainTableParse(device, + &gainTableRow[0], + &armDmaData[0], + numGainIndicesReadVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error parsing gain table data"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Update no. of gain indices read*/ + if (numGainIndicesRead != NULL) + { + *numGainIndicesRead = numGainIndicesReadVal; + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxGainSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxGain_t rxGain[], + uint8_t arraySize) +{ + static const uint32_t ALL_RX_MASK = (uint32_t)(ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4); + static const uint32_t ORX12_MASK = (uint32_t)(ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2); + static const uint32_t ORX34_MASK = (uint32_t)(ADI_ADRV9025_ORX3 | ADI_ADRV9025_ORX4); + + uint32_t configIndex = 0; + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check device for null pointer */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + /*Check for null rxGain pointer*/ + ADI_NULL_PTR_RETURN(&device->common, + rxGain); + + /*Check that no. of Rx gain settings is valid*/ + if (arraySize == 0 || arraySize > 8) + { + ADI_ERROR_REPORT(&device->common,ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_NULL_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + arraySize, + "Invalid Parameter arraySize. Number of configs should be between 1 and 8"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Range check manual gain index setting for the requested channel*/ + for (configIndex = 0; configIndex < arraySize; configIndex++) + { + /*Check that Rx profile is valid*/ + if ((rxGain[configIndex].rxChannelMask & ALL_RX_MASK) > 0) + { + if ((device->devStateInfo.profilesValid & ADI_ADRV9025_RX_PROFILE_VALID) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].rxChannelMask, + "Rx gain index set requested for an Rx Channel but Rx profile is invalid in the device structure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Check that ORx profile is valid*/ + if ((rxGain[configIndex].rxChannelMask & (ORX12_MASK | ORX34_MASK)) > 0) + { + if ((device->devStateInfo.profilesValid & ADI_ADRV9025_ORX_PROFILE_VALID) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].rxChannelMask, + "Rx gain index set requested for an ORx channel but ORx profile is invalid in the device structure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Check that rxChannelMask is not out of range*/ + if ((rxGain[configIndex].rxChannelMask > (ALL_RX_MASK | ORX12_MASK | ORX34_MASK)) || + (rxGain[configIndex].rxChannelMask == ADI_ADRV9025_RXOFF)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].rxChannelMask, + "Invalid Rx Channel Mask encountered for manual rx gain index setting"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that gain indices are within range for the channel selected*/ + if ((rxGain[configIndex].rxChannelMask & (uint32_t)ADI_ADRV9025_RX1) == (uint32_t)ADI_ADRV9025_RX1) + { + if ((rxGain[configIndex].gainIndex > device->devStateInfo.gainIndexes.rx1MaxGainIndex) || + (rxGain[configIndex].gainIndex < device->devStateInfo.gainIndexes.rx1MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].gainIndex, + "Rx1 manual gain index setting is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if ((rxGain[configIndex].rxChannelMask & (uint32_t)ADI_ADRV9025_RX2) == (uint32_t)ADI_ADRV9025_RX2) + { + if ((rxGain[configIndex].gainIndex > device->devStateInfo.gainIndexes.rx2MaxGainIndex) || + (rxGain[configIndex].gainIndex < device->devStateInfo.gainIndexes.rx2MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].gainIndex, + "Rx2 manual gain index setting is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if ((rxGain[configIndex].rxChannelMask & (uint32_t)ADI_ADRV9025_RX3) == (uint32_t)ADI_ADRV9025_RX3) + { + if ((rxGain[configIndex].gainIndex > device->devStateInfo.gainIndexes.rx3MaxGainIndex) || + (rxGain[configIndex].gainIndex < device->devStateInfo.gainIndexes.rx3MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].gainIndex, + "Rx3 manual gain index setting is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if ((rxGain[configIndex].rxChannelMask & (uint32_t)ADI_ADRV9025_RX4) == (uint32_t)ADI_ADRV9025_RX4) + { + if ((rxGain[configIndex].gainIndex > device->devStateInfo.gainIndexes.rx4MaxGainIndex) || + (rxGain[configIndex].gainIndex < device->devStateInfo.gainIndexes.rx4MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].gainIndex, + "Rx4 manual gain index setting is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if (((rxGain[configIndex].rxChannelMask & (uint32_t)ADI_ADRV9025_ORX1) == (uint32_t)ADI_ADRV9025_ORX1) || + ((rxGain[configIndex].rxChannelMask & (uint32_t)ADI_ADRV9025_ORX2) == (uint32_t)ADI_ADRV9025_ORX2)) + { + if ((rxGain[configIndex].gainIndex > device->devStateInfo.gainIndexes.orx1orx2MaxGainIndex) || + (rxGain[configIndex].gainIndex < device->devStateInfo.gainIndexes.orx1orx2MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].gainIndex, + "ORx1/ORx2 manual gain index setting is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if (((rxGain[configIndex].rxChannelMask & (uint32_t)ADI_ADRV9025_ORX3) == (uint32_t)ADI_ADRV9025_ORX3) || + ((rxGain[configIndex].rxChannelMask & (uint32_t)ADI_ADRV9025_ORX4) == (uint32_t)ADI_ADRV9025_ORX4)) + { + if ((rxGain[configIndex].gainIndex > device->devStateInfo.gainIndexes.orx3orx4MaxGainIndex) || + (rxGain[configIndex].gainIndex < device->devStateInfo.gainIndexes.orx3orx4MinGainIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].gainIndex, + "ORx3/ORx4 manual gain index setting is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxGainSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxGain_t rxGain[], + uint8_t arraySize) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t configIndex = 0; + + /*Check for null device pointer*/ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /*Check for null rxGain pointer*/ + ADI_NULL_PTR_RETURN(&device->common, + rxGain); + +#if ADI_ADRV9025_RX_RANGE_CHECK > 0 + adi_adrv9025_RxGainSetRangeCheck(device, + rxGain, + arraySize); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /*Update manual gain index setting for the requested channel */ + for (configIndex = 0; configIndex < arraySize; configIndex++) + { + if ((rxGain[configIndex].rxChannelMask & ADI_ADRV9025_RX1) == ADI_ADRV9025_RX1) + { + adrv9025_RxAgcManualGainIndexBfSet(device, + ADRV9025_BF_RX_CH0, + rxGain[configIndex].gainIndex); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].gainIndex, + "Error while attemtpting to set Rx manual gain index for channel Rx1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxGain[configIndex].rxChannelMask & ADI_ADRV9025_RX2) == ADI_ADRV9025_RX2) + { + adrv9025_RxAgcManualGainIndexBfSet(device, + ADRV9025_BF_RX_CH1, + rxGain[configIndex].gainIndex); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].gainIndex, + "Error while attemtpting to set Rx manual gain index for channel Rx2"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxGain[configIndex].rxChannelMask & ADI_ADRV9025_RX3) == ADI_ADRV9025_RX3) + { + adrv9025_RxAgcManualGainIndexBfSet(device, + ADRV9025_BF_RX_CH2, + rxGain[configIndex].gainIndex); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].gainIndex, + "Error while attemtpting to set Rx manual gain index for channel Rx3"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxGain[configIndex].rxChannelMask & ADI_ADRV9025_RX4) == ADI_ADRV9025_RX4) + { + adrv9025_RxAgcManualGainIndexBfSet(device, + ADRV9025_BF_RX_CH3, + rxGain[configIndex].gainIndex); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].gainIndex, + "Error while attemtpting to set Rx manual gain index for channel Rx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxGain[configIndex].rxChannelMask & ADI_ADRV9025_ORX1) == ADI_ADRV9025_ORX1) + { + adrv9025_OrxOrx1AgcManualGainIndexBfSet(device, + ADRV9025_BF_ORX_CH0, + rxGain[configIndex].gainIndex); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].gainIndex, + "Error while attemtpting to set manual gain index for channel ORx1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write gain index to streamproc_debug_reg10 bitfield for this register erroneously masked bits 6 and 7 so using absolute address */ + recoveryAction = adi_adrv9025_SpiByteWrite(device, + 0x1B88, + rxGain[configIndex].gainIndex); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while writing spi byte, rxGainIndex to streamproc_debug_reg10"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxGain[configIndex].rxChannelMask & ADI_ADRV9025_ORX2) == ADI_ADRV9025_ORX2) + { + adrv9025_OrxOrx2AgcManualGainIndexBfSet(device, + ADRV9025_BF_ORX_CH0, + rxGain[configIndex].gainIndex); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].gainIndex, + "Error while attemtpting to set manual gain index for channel ORx2"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write gain index to streamproc_debug_reg12 bitfield for this register erroneously masked bits 6 and 7 so using absolute address */ + recoveryAction = adi_adrv9025_SpiByteWrite(device, + 0x1B8A, + rxGain[configIndex].gainIndex); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while writing spi byte, rxGainIndex to streamproc_debug_reg12"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxGain[configIndex].rxChannelMask & ADI_ADRV9025_ORX3) == ADI_ADRV9025_ORX3) + { + adrv9025_OrxOrx1AgcManualGainIndexBfSet(device, + ADRV9025_BF_ORX_CH1, + rxGain[configIndex].gainIndex); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].gainIndex, + "Error while attemtpting to set manual gain index for channel ORx3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write gain index to streamproc_debug_reg10 bitfield for this register erroneously masked bits 6 and 7 so using absolute address */ + recoveryAction = adi_adrv9025_SpiByteWrite(device, + 0x1D88, + rxGain[configIndex].gainIndex); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while writing spi byte, rxGainIndex to streamproc_debug_reg10"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((rxGain[configIndex].rxChannelMask & ADI_ADRV9025_ORX4) == ADI_ADRV9025_ORX4) + { + adrv9025_OrxOrx2AgcManualGainIndexBfSet(device, + ADRV9025_BF_ORX_CH1, + rxGain[configIndex].gainIndex); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGain[configIndex].gainIndex, + "Error while attemtpting to set manual gain index for channel ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write gain index to streamproc_debug_reg12 bitfield for this register erroneously masked bits 6 and 7 so using absolute address */ + recoveryAction = adi_adrv9025_SpiByteWrite(device, + 0x1D8A, + rxGain[configIndex].gainIndex); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while writing spi byte, rxGainIndex to streamproc_debug_reg12"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxGainGetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxGain_t* rxGain) +{ + UNUSED_PARA(rxGain); + static const uint32_t ALL_RX_MASK = (uint32_t)(ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4); + static const uint32_t ORX12_MASK = (uint32_t)(ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2); + static const uint32_t ORX34_MASK = (uint32_t)(ADI_ADRV9025_ORX3 | ADI_ADRV9025_ORX4); + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, rxGain); + + /*Check that the requested rxChannel is valid*/ + if ((rxChannel != ADI_ADRV9025_RX1) && + (rxChannel != ADI_ADRV9025_RX2) && + (rxChannel != ADI_ADRV9025_RX3) && + (rxChannel != ADI_ADRV9025_RX4) && + (rxChannel != ADI_ADRV9025_ORX1) && + (rxChannel != ADI_ADRV9025_ORX2) && + (rxChannel != ADI_ADRV9025_ORX3) && + (rxChannel != ADI_ADRV9025_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel Requested for manual rx gain read"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that rx profile is valid in current config*/ + if (((uint32_t)rxChannel & ALL_RX_MASK) > 0) + { + if ((device->devStateInfo.profilesValid & ADI_ADRV9025_RX_PROFILE_VALID) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Gain index read requested for an ORx channel but Rx profile is invalid in device structure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /*Check that orx profile is valid in current config*/ + if (((uint32_t)rxChannel & (ORX12_MASK | ORX34_MASK)) > 0) + { + if ((device->devStateInfo.profilesValid & ADI_ADRV9025_ORX_PROFILE_VALID) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Gain index read requested for an ORx channel but ORx profile is invalid in device structure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxMgcGainGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxGain_t* rxGain) +{ + static const uint32_t ALL_RX_MASK = (uint32_t)(ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4); + + adrv9025_BfRxChanAddr_e rxChannelBitFieldAddr = ADRV9025_BF_RX_CH0; + + /* Check device for null pointer */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /*Check for null rxGain pointer*/ + ADI_NULL_PTR_RETURN(&device->common, rxGain); + +#if ADI_ADRV9025_RX_RANGE_CHECK > 0 + adi_adrv9025_RxGainGetRangeCheck(device, + rxChannel, + rxGain); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid RX Channel or RX Gain value."); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /*Check for null rxGain pointer*/ + ADI_NULL_PTR_RETURN(&device->common, + rxGain); + + /*Read the manual gain index setting*/ + if ((rxChannel & ALL_RX_MASK) > 0) + { + /*Resolve the Rx channel bitfield address*/ + adrv9025_RxBitfieldAddressGet(device, + rxChannel, + &rxChannelBitFieldAddr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Error while attempting to decode Rx channel bitfield address"); + ADI_ERROR_RETURN(device->common.error.newAction); + + //Get Rx Manual gain in SPI register at offset 0x53 + adrv9025_RxAgcManualGainIndexBfGet(device, + rxChannelBitFieldAddr, + &rxGain->gainIndex); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Error while attempting to get Rx AGC gain index"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /*Resolve the ORx channel bitfield address*/ + if (rxChannel == ADI_ADRV9025_ORX1) + { + /* Get ORx gain in SPI register at offset 0xBB */ + adrv9025_OrxOrx1AgcManualGainIndexBfGet(device, ADRV9025_BF_ORX_CH0, &rxGain->gainIndex); + } + else if (rxChannel == ADI_ADRV9025_ORX2) + { + /* Get ORx gain in SPI register at offset 0xBC */ + adrv9025_OrxOrx2AgcManualGainIndexBfGet(device, ADRV9025_BF_ORX_CH0, &rxGain->gainIndex); + } + else if (rxChannel == ADI_ADRV9025_ORX3) + { + adrv9025_OrxOrx1AgcManualGainIndexBfGet(device, ADRV9025_BF_ORX_CH1, &rxGain->gainIndex); + } + else if (rxChannel == ADI_ADRV9025_ORX4) + { + adrv9025_OrxOrx2AgcManualGainIndexBfGet(device, ADRV9025_BF_ORX_CH1, &rxGain->gainIndex); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalif ORX Channel parameter."); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Error while attempting to read ORx manual gain index"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxGainGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxGain_t* rxGain) +{ + static const uint32_t ALL_RX_MASK = (uint32_t)(ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4); + + adrv9025_BfRxChanAddr_e rxChannelBitFieldAddr = ADRV9025_BF_RX_CH0; + uint8_t agcEnableGainIndexUpdate = 0; + uint32_t rxChannelStatus = 0; + uint32_t txChannelStatus = 0; + + /* Check device for null pointer */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + +#if ADI_ADRV9025_RX_RANGE_CHECK > 0 + adi_adrv9025_RxGainGetRangeCheck(device, + rxChannel, + rxGain); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid RX Channel or RX Gain value."); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /*Check for null rxGain pointer*/ + ADI_NULL_PTR_RETURN(&device->common, + rxGain); + + /*Read the manual gain index setting*/ + if ((rxChannel & ALL_RX_MASK) > 0) + { + /*Resolve the Rx channel bitfield address*/ + adrv9025_RxBitfieldAddressGet(device, + rxChannel, + &rxChannelBitFieldAddr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Error while attempting to decode Rx channel bitfield address"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Need to check agc_enable_gain_index_update. If this is enabled, then need to write dummy first before getting agc_gain_index. */ + adrv9025_RxAgcEnableGainIndexUpdateBfGet(device, + rxChannelBitFieldAddr, + &agcEnableGainIndexUpdate); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (agcEnableGainIndexUpdate == ADI_TRUE) + { + adi_adrv9025_RxTxEnableGet(device, + &rxChannelStatus, + &txChannelStatus); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((rxChannel & rxChannelStatus) != 0) + { + adrv9025_RxAgcEnableGainIndexUpdateLatch(device, + rxChannelBitFieldAddr); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "AGC gain index set in write to latch mode hence corresponding RxChannel must be enabled to read AGC gain index value."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + //Get Rx Auto gain in SPI register at offset 0x9E + adrv9025_RxAgcGainIndexBfGet(device, + rxChannelBitFieldAddr, + &rxGain->gainIndex); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Error while attempting to set Rx AGC gain index"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Need to check agc_enable_gain_index_update. If this is enabled, then need to write dummy first before getting agc_gain_index. */ + if (rxChannel == ADI_ADRV9025_ORX1 || rxChannel == ADI_ADRV9025_ORX2) + { + adrv9025_OrxAgcEnableGainIndexUpdateBfGet(device, + ADRV9025_BF_ORX_CH0, + &agcEnableGainIndexUpdate); + } + else if (rxChannel == ADI_ADRV9025_ORX3 || rxChannel == ADI_ADRV9025_ORX4) + { + adrv9025_OrxAgcEnableGainIndexUpdateBfGet(device, + ADRV9025_BF_ORX_CH1, + &agcEnableGainIndexUpdate); + } + + // if the agc_enable_gain_index_update returns true, do the dummy write to latch the gain index + if (agcEnableGainIndexUpdate == ADI_TRUE) + { + if (rxChannel == ADI_ADRV9025_ORX1) + { + adrv9025_OrxOrx1AgcEnableGainIndexUpdateLatch(device, + ADRV9025_BF_ORX_CH0); + } + else if (rxChannel == ADI_ADRV9025_ORX2) + { + adrv9025_OrxOrx2AgcEnableGainIndexUpdateLatch(device, + ADRV9025_BF_ORX_CH0); + } + else if (rxChannel == ADI_ADRV9025_ORX3) + { + adrv9025_OrxOrx1AgcEnableGainIndexUpdateLatch(device, + ADRV9025_BF_ORX_CH1); + } + else if (rxChannel == ADI_ADRV9025_ORX4) + { + adrv9025_OrxOrx2AgcEnableGainIndexUpdateLatch(device, + ADRV9025_BF_ORX_CH1); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid ORX Channel parameter."); + } + } + + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + /*Resolve the ORx channel bitfield address*/ + if (rxChannel == ADI_ADRV9025_ORX1) + { + /* Get ORx gain in SPI register at offset 0xBB */ + adrv9025_OrxOrx1AgcGainIndexBfGet(device, + ADRV9025_BF_ORX_CH0, + &rxGain->gainIndex); + } + else if (rxChannel == ADI_ADRV9025_ORX2) + { + /* Get ORx gain in SPI register at offset 0xBC */ + adrv9025_OrxOrx2AgcGainIndexBfGet(device, + ADRV9025_BF_ORX_CH0, + &rxGain->gainIndex); + } + else if (rxChannel == ADI_ADRV9025_ORX3) + { + adrv9025_OrxOrx1AgcGainIndexBfGet(device, + ADRV9025_BF_ORX_CH1, + &rxGain->gainIndex); + } + else if (rxChannel == ADI_ADRV9025_ORX4) + { + adrv9025_OrxOrx2AgcGainIndexBfGet(device, + ADRV9025_BF_ORX_CH1, + &rxGain->gainIndex); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid ORX Channel parameter."); + } + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Error while attempting to read ORx manual gain index"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxDecPowerGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint16_t* rxDecPower_mdBFS) +{ + adrv9025_BfRxChanAddr_e rxChannelBitFieldAddr = ADRV9025_BF_RX_CH0; + adrv9025_BfOrxChanAddr_e orxChannelBitFieldAddr = ADRV9025_BF_ORX_CH0; + uint8_t bfValue = 0; + + static const uint32_t ALL_RX_MASK = (uint32_t)(ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4); + static const uint8_t RX_DEC_POWER_MULT = 250; /* 250 = 1000 * 0.25dB */ + static const uint8_t DEC_MAX_POWER = 252; + + /* Check device for null pointer */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + +#if ADI_ADRV9025_RX_RANGE_CHECK > 0 + adrv9025_RxDecPowerGetRangeCheck(device, + rxChannel); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /*Check for null rxDecPower pointer*/ + ADI_NULL_PTR_RETURN(&device->common, + rxDecPower_mdBFS); + + /*Read the manual gain index setting*/ + if ((rxChannel & ALL_RX_MASK) > 0) + { + /*Resolve the Rx channel bitfield address*/ + adrv9025_RxBitfieldAddressGet(device, + rxChannel, + &rxChannelBitFieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* + * This register contains the decimated power readback value + * for the Ch1 Rx datapath.Resolution is 0.25dB. + * This register must be written(any value) to generate a strobe + * that will latch the value to be read back. + */ + ADRV9025_SPIWRITEBYTE("RX_DECIMATED_PWR", + (rxChannelBitFieldAddr + ADRV9025_ADDR_RX_DECIMATED_PWR_OFFSET), + 0x0F); + + adrv9025_RxDecPowerBfGet(device, + rxChannelBitFieldAddr, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /*Resolve the ORx channel bitfield address*/ + adrv9025_OrxBitfieldAddressGet(device, + rxChannel, + &orxChannelBitFieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* + * This register contains the decimated power readback value + * for the Ch1 Rx datapath.Resolution is 0.25dB. + * This register must be written(any value) to generate a strobe + * that will latch the value to be read back. + */ + ADRV9025_SPIWRITEBYTE("RX_DECIMATED_PWR", + (orxChannelBitFieldAddr + ADRV9025_ADDR_ORX_DECIMATED_PWR_OFFSET), + 0x0F); + + adrv9025_OrxDecPowerBfGet(device, + orxChannelBitFieldAddr, + &bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* + * Checking the DECIMATED Power range. The valid range is from 0 to -63 dB. + * With 0.25 dB step, the bfValue can't greater than 252. + * (i.e. with bfValue == 100 -> DEC power is (100 / 4) = 25 dB, + * negative sign is implicit so it is -25 dB. */ + if (bfValue > DEC_MAX_POWER) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_SPI_FAIL, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + rxChannel, + "Decimated Power is out of range."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *rxDecPower_mdBFS = (((uint16_t)bfValue) * RX_DEC_POWER_MULT); + + return device->common.error.newAction; +} + +/**************************************************************************** + * Initialization functions + ****************************************************************************/ + +int32_t adi_adrv9025_RxGainTableDualBandLnaWrite(adi_adrv9025_Device_t* device, + adi_adrv9025_DualBandRxGainTableCfg_t gainTableCfg[], + uint8_t arraySize) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, gainTableCfg); + + UNUSED_PARA(device); + UNUSED_PARA(gainTableCfg); + UNUSED_PARA(arraySize); + return 0; +} + +/* TODO: Needs doxygen header */ +int32_t adi_adrv9025_RxGainTableDualBandLnaRead(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_DualBandRxGainTableCfg_t* gainTableCfg) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, gainTableCfg); + + UNUSED_PARA(device); + UNUSED_PARA(rxChannel); + UNUSED_PARA(gainTableCfg); + return 0; +} + +int32_t adi_adrv9025_RxFirWrite(adi_adrv9025_Device_t* device, + uint32_t rxChanMask, + int8_t gain_dB, + uint8_t numFirCoefs, + int16_t coefs[], + uint8_t arraySize) +{ + uint8_t j = 0; + uint32_t maskBit = 0; + static const uint32_t maskArray[ADI_ADRV9025_MAX_RXCHANNELS] = { + ADI_ADRV9025_RX1, + ADI_ADRV9025_RX2, + ADI_ADRV9025_RX3, + ADI_ADRV9025_RX4, + ADI_ADRV9025_ORX1, + ADI_ADRV9025_ORX2, + ADI_ADRV9025_ORX3, + ADI_ADRV9025_ORX4, + ADI_ADRV9025_LB12, + ADI_ADRV9025_LB34 + }; + static const uint32_t VALID_RXCHANMASKALL = 0x000003FF; + static const uint32_t VALID_RXCHANMASK1234 = 0x0000000F; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + coefs); + + ADRV9025_BUGINFO(__FUNCTION__); + + if ((rxChanMask & VALID_RXCHANMASKALL) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChanMask, + "Invalid RxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (rxChanMask == VALID_RXCHANMASK1234) + { + adrv9025_RxFirWrite(device, + rxChanMask, + gain_dB, + numFirCoefs, + coefs, + arraySize); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Program FIR filters */ + for (j = 0; j < ADI_ADRV9025_MAX_RXCHANNELS; j++) + { + maskBit = maskArray[j]; + if (ADRV9025_BF_EQUAL(rxChanMask, + maskBit)) + { + adrv9025_RxFirWrite(device, + maskBit, + gain_dB, + numFirCoefs, + coefs, + arraySize); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_RxFirRead(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + int8_t* gain_dB, + uint8_t* numFirCoefs, + int16_t coefs[], + uint8_t arraySize) +{ + uint8_t firBankSel = 0; + uint8_t i = 0; + uint8_t j = 0; + uint8_t numTapsReg = 0; + uint8_t nTapMul = 0; + uint8_t filterGain = 0; + uint8_t pfirCoeffCtl = 0;; + uint16_t baseaddr = 0; + uint8_t rxPfirBankSel = 0; + uint8_t byteLo = 0; + uint8_t byteHi = 0; + uint8_t filterConfig = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + coefs); + ADI_NULL_PTR_RETURN(&device->common, + gain_dB); + ADI_NULL_PTR_RETURN(&device->common, + numFirCoefs); + + ADRV9025_BUGINFO(__FUNCTION__); + + static const uint8_t autoInc = ADI_ADRV9025_PFIR_COEFF_AUTO_INCR; + + static const uint8_t RXFIR_BANKA = 0x01; + static const uint8_t ORXFIR_BANKA = 0x02; + static const uint8_t ORXFIR_BANKB = 0x04; + static const uint8_t ORXFIR_BANKC = 0x08; + + static const uint8_t BANKA = 0; + static const uint8_t BANKB = 1; + static const uint8_t BANKC = 2; + + static const uint8_t RXFIR_MULTAPS = 24; + + if (adrv9025_RxAddrDecode(device, + rxChannel) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid RxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (arraySize == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + arraySize, + "arraySize is zero"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* firBankSelect and assignment of nTapMul and address firAddr.*/ + switch (rxChannel) + { + case ADI_ADRV9025_RX1: /* fall through */ + case ADI_ADRV9025_RX2: /* fall through */ + case ADI_ADRV9025_RX3: /* fall through */ + case ADI_ADRV9025_RX4: + firBankSel = RXFIR_BANKA; + nTapMul = RXFIR_MULTAPS; + break; + + case ADI_ADRV9025_ORX1: /* fall through */ + case ADI_ADRV9025_ORX3: + firBankSel = ORXFIR_BANKA; + nTapMul = RXFIR_MULTAPS; + break; + + case ADI_ADRV9025_ORX2: /* fall through */ + case ADI_ADRV9025_ORX4: + firBankSel = ORXFIR_BANKB; + nTapMul = RXFIR_MULTAPS; + break; + + case ADI_ADRV9025_LB12: /* fall through */ + case ADI_ADRV9025_LB34: + firBankSel = ORXFIR_BANKC; + nTapMul = RXFIR_MULTAPS; + break; + + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Undefined Rx rxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (firBankSel == RXFIR_BANKA) + { + pfirCoeffCtl = ADRV9025_PFIR_COEFF_PROG_CLK_EN; + if (autoInc != 0) + { + pfirCoeffCtl |= ADRV9025_PFIR_COEFF_AUTO_INCR; + } + + baseaddr = adrv9025_RxAddrDecode(device, + rxChannel); + ADRV9025_SPIREADBYTE("RX_PFIR_SETTINGS", + (baseaddr + ADRV9025_ADDR_RX_PFIR_SETTINGS_OFFSET), + &filterConfig); + numTapsReg = ADRV9025_BF_DECODE(filterConfig, + ADRV9025_RX_PFIR_TAPS_MASK, + ADRV9025_RX_PFIR_TAPS_SHIFT); + *numFirCoefs = (numTapsReg + 1) * nTapMul; + + filterGain = ADRV9025_BF_DECODE(filterConfig, + ADRV9025_RX_PFIR_GAIN_MASK, + ADRV9025_RX_PFIR_GAIN_SHIFT); + + /* Set filter gain to be used */ + switch (filterGain) + { + case 0: + *gain_dB = ADRV9025_FIR_GAIN_NEG12_DB; + break; + case 1: + *gain_dB = ADRV9025_FIR_GAIN_NEG6_DB; + break; + case 2: + *gain_dB = ADRV9025_FIR_GAIN_0_DB; + break; + case 3: + default: + *gain_dB = ADRV9025_FIR_GAIN_POS6_DB; + break; + } + + ADRV9025_SPIWRITEBYTE("RX_PFIR_COEFF_CTL", + (baseaddr + ADRV9025_ADDR_RX_PFIR_COEFF_CTL_OFFSET), + pfirCoeffCtl); + + /* pfir_coeff_addr */ + j = 0; + ADRV9025_SPIWRITEBYTE("RX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_RX_PFIR_COEFF_ADDR_OFFSET), + j); + + if (arraySize > *numFirCoefs) + { + arraySize = *numFirCoefs; + } + + for (i = 0; i < arraySize; i++) + { + /* pfir_coeff_data LSB */ + byteLo = 0; + byteHi = 0; + ADRV9025_SPIREADBYTE("RX_PFIR_COEFF_DATA_LSB", + (baseaddr + ADRV9025_ADDR_RX_PFIR_COEFF_DATA_OFFSET), + &byteLo); + + if (autoInc == 0) + { + j++; + ADRV9025_SPIWRITEBYTE("RX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_RX_PFIR_COEFF_ADDR_OFFSET), + j); + } + /* pfir_coeff_data MSB */ + ADRV9025_SPIREADBYTE("RX_PFIR_COEFF_DATA_MSB", + (baseaddr + ADRV9025_ADDR_RX_PFIR_COEFF_DATA_OFFSET), + &byteHi); + coefs[i] = (int16_t)((((uint16_t)byteHi) << 8) | byteLo); + + if (autoInc == 0) + { + j++; + ADRV9025_SPIWRITEBYTE("RX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_RX_PFIR_COEFF_ADDR_OFFSET), + j); + } + } + + /* disable pfir_coeff_prog_clk_en */ + /* disable pfir_coeff_wr_enable */ + + pfirCoeffCtl = 0; + ADRV9025_SPIWRITEBYTE("RX_PFIR_COEFF_CTL", + (baseaddr + ADRV9025_ADDR_RX_PFIR_COEFF_CTL_OFFSET), + pfirCoeffCtl); + } + + if (firBankSel & (ORXFIR_BANKA | ORXFIR_BANKB | ORXFIR_BANKC)) + { + pfirCoeffCtl = ADRV9025_PFIR_COEFF_PROG_CLK_EN; + if (autoInc != 0) + { + pfirCoeffCtl |= ADRV9025_PFIR_COEFF_AUTO_INCR; + } + + /* pfir_coeff_rx_b_sel */ + if (firBankSel & ORXFIR_BANKA) + { + pfirCoeffCtl |= ADRV9025_PFIR_COEFF_RX_A_SEL; + } + else if (firBankSel & ORXFIR_BANKB) + { + pfirCoeffCtl |= ADRV9025_PFIR_COEFF_RX_B_SEL; + } + else if (firBankSel & ORXFIR_BANKC) + { + pfirCoeffCtl |= ADRV9025_PFIR_COEFF_RX_C_SEL; + } + + baseaddr = adrv9025_RxAddrDecode(device, + rxChannel); + + /* Write FIR #taps and gain */ + /* orx_pfir_Taps */ + /* rx_pfir_Taps */ + + ADRV9025_SPIREADBYTE("ORX_PFIR_BANK_SEL", + (baseaddr + ADRV9025_ADDR_RX_PFIR_BANK_SEL_OFFSET), + &rxPfirBankSel); + + if (firBankSel & ORXFIR_BANKA) + { + ADRV9025_SPIREADBYTE("ORX_PFIR_CONFIG_SETTING_BANK_A", + (baseaddr + ADRV9025_ADDR_RX_PFIR_CONFIG_SETTINGSN_OFFSET + BANKA), + &filterConfig); + /* Verify mapping for Obs Rx1/3 to FIR Bank A */ + if (BANKA != ADRV9025_BF_DECODE(rxPfirBankSel, + ADRV9025_PFIR_CONFIG_FOR_ORX_1_MASK, + ADRV9025_PFIR_CONFIG_FOR_ORX_1_SHIFT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxPfirBankSel, + "Invalid rxPfirBankSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else if (firBankSel & ORXFIR_BANKB) + { + ADRV9025_SPIREADBYTE("ORX_PFIR_CONFIG_SETTING_BANK_B", + (baseaddr + ADRV9025_ADDR_RX_PFIR_CONFIG_SETTINGSN_OFFSET + BANKB), + &filterConfig); + /* Verify mapping for Obs Rx2/4 to FIR Bank B */ + if (BANKB != ADRV9025_BF_DECODE(rxPfirBankSel, + ADRV9025_PFIR_CONFIG_FOR_ORX_2_MASK, + ADRV9025_PFIR_CONFIG_FOR_ORX_2_SHIFT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxPfirBankSel, + "Invalid rxPfirBankSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else if (firBankSel & ORXFIR_BANKC) + { + ADRV9025_SPIREADBYTE("ORX_PFIR_CONFIG_SETTING_BANK_C", + (baseaddr + ADRV9025_ADDR_RX_PFIR_CONFIG_SETTINGSN_OFFSET + BANKC), + &filterConfig); + /* Verify mapping for internal loopback1 to Bank C */ + if (BANKC != ADRV9025_BF_DECODE(rxPfirBankSel, + ADRV9025_PFIR_CONFIG_FOR_LOOPBACK_1_MASK, + ADRV9025_PFIR_CONFIG_FOR_LOOPBACK_1_SHIFT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxPfirBankSel, + "Invalid rxPfirBankSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Verify mapping for internal loopback2 to Bank C */ + if (BANKC != ADRV9025_BF_DECODE(rxPfirBankSel, + ADRV9025_PFIR_CONFIG_FOR_LOOPBACK_2_MASK, + ADRV9025_PFIR_CONFIG_FOR_LOOPBACK_2_SHIFT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxPfirBankSel, + "Invalid rxPfirBankSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + numTapsReg = ADRV9025_BF_DECODE(filterConfig, + ADRV9025_RX_PFIR_TAPS_MASK, + ADRV9025_RX_PFIR_TAPS_SHIFT); + *numFirCoefs = (numTapsReg + 1) * nTapMul; + + filterGain = ADRV9025_BF_DECODE(filterConfig, + ADRV9025_RX_PFIR_GAIN_MASK, + ADRV9025_RX_PFIR_GAIN_SHIFT); + + /* Set filter gain to be used */ + switch (filterGain) + { + case 0: + *gain_dB = ADRV9025_FIR_GAIN_NEG12_DB; + break; + case 1: + *gain_dB = ADRV9025_FIR_GAIN_NEG6_DB; + break; + case 2: + *gain_dB = ADRV9025_FIR_GAIN_0_DB; + break; + case 3: + default: + *gain_dB = ADRV9025_FIR_GAIN_POS6_DB; + break; + } + + ADRV9025_SPIWRITEBYTE("ORX_PFIR_COEFF_CTL", + (baseaddr + ADRV9025_ADDR_ORX_PFIR_COEFF_CTL_OFFSET), + pfirCoeffCtl); + + /* pfir_coeff_addr */ + j = 0; + ADRV9025_SPIWRITEBYTE("ORX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_ORX_PFIR_COEFF_ADDR_OFFSET), + j); + + if (arraySize > *numFirCoefs) + { + arraySize = *numFirCoefs; + } + + for (i = 0; i < arraySize; i++) + { + /* pfir_coeff_data LSB */ + byteLo = 0; + byteHi = 0; + ADRV9025_SPIREADBYTE("ORX_PFIR_COEFF_DATA_LSB", + (baseaddr + ADRV9025_ADDR_ORX_PFIR_COEFF_DATA_OFFSET), + &byteLo); + + if (autoInc == 0) + { + j++; + ADRV9025_SPIWRITEBYTE("ORX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_ORX_PFIR_COEFF_ADDR_OFFSET), + j); + } + + /* pfir_coeff_data MSB */ + ADRV9025_SPIREADBYTE("ORX_PFIR_COEFF_DATA_MSB", + (baseaddr + ADRV9025_ADDR_ORX_PFIR_COEFF_DATA_OFFSET), + &byteHi); + coefs[i] = (int16_t)((((uint16_t)byteHi) << 8) | byteLo); + + if (autoInc == 0) + { + j++; + ADRV9025_SPIWRITEBYTE("ORX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_ORX_PFIR_COEFF_ADDR_OFFSET), + j); + } + } + + /* disable pfir_coeff_prog_clk_en */ + /* disable pfir_coeff_wr_enable */ + + pfirCoeffCtl = 0; + ADRV9025_SPIWRITEBYTE("ORX_PFIR_COEFF_CTL", + (baseaddr + ADRV9025_ADDR_ORX_PFIR_COEFF_CTL_OFFSET), + pfirCoeffCtl); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_RxGainCtrlModeSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxAgcMode_t gainMode[], + uint8_t arraySize) +{ + static const uint32_t ORX12_MASK = (uint32_t)(ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2); + static const uint8_t AGC_ENABLE_FAST_RECOVERY_LOOP_BITFIELD = 1; + static const uint8_t AGC_DISABLE_FAST_RECOVERY_LOOP_BITFIELD = 0; + static const adi_adrv9025_RxChannels_e rxChannelArr[] = {ADI_ADRV9025_RX1, ADI_ADRV9025_RX2, ADI_ADRV9025_RX3, ADI_ADRV9025_RX4}; + static const adi_adrv9025_RxChannels_e orxChannelArr[] = { + ADI_ADRV9025_ORX1, + ADI_ADRV9025_ORX2, + ADI_ADRV9025_ORX3, + ADI_ADRV9025_ORX4 + }; + + uint32_t gainModeIndex = 0; + uint32_t rxChannelIndex = 0; + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddr; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + gainMode); + + for (gainModeIndex = 0; gainModeIndex < arraySize; gainModeIndex++) + { + for (rxChannelIndex = 0; rxChannelIndex < (sizeof(rxChannelArr) / sizeof(rxChannelArr[0])); rxChannelIndex++) + { + if ((gainMode[gainModeIndex].rxChannelMask & (uint32_t)rxChannelArr[rxChannelIndex]) == + (uint32_t)rxChannelArr[rxChannelIndex]) + { + adrv9025_RxBitfieldAddressGet(device, + rxChannelArr[rxChannelIndex], + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxAgcSetupBfSet(device, + rxChannelBitfieldAddr, + (uint8_t)gainMode[gainModeIndex].agcMode); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (gainMode[gainModeIndex].agcMode == ADI_ADRV9025_MGC) + { + adrv9025_RxAgcEnableFastRecoveryLoopBfSet(device, + rxChannelBitfieldAddr, + AGC_DISABLE_FAST_RECOVERY_LOOP_BITFIELD); + } + else + { + if ((device->devStateInfo.rxAgcPeakModeMask & rxChannelArr[rxChannelIndex]) > 0) + { + adrv9025_RxAgcEnableFastRecoveryLoopBfSet(device, + rxChannelBitfieldAddr, + AGC_ENABLE_FAST_RECOVERY_LOOP_BITFIELD); + } + else + { + adrv9025_RxAgcEnableFastRecoveryLoopBfSet(device, + rxChannelBitfieldAddr, + AGC_DISABLE_FAST_RECOVERY_LOOP_BITFIELD); + } + } + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + for (rxChannelIndex = 0; rxChannelIndex < (sizeof(orxChannelArr) / sizeof(orxChannelArr[0])); rxChannelIndex++) + { + if ((gainMode[gainModeIndex].rxChannelMask & (uint32_t)orxChannelArr[rxChannelIndex]) == + (uint32_t)orxChannelArr[rxChannelIndex]) + { + adrv9025_OrxBitfieldAddressGet(device, + orxChannelArr[rxChannelIndex], + &orxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((gainMode[gainModeIndex].rxChannelMask & ORX12_MASK) > 0) + { + adrv9025_OrxOrx1AgcSetupBfSet(device, + orxChannelBitfieldAddr, + (uint8_t)gainMode[gainModeIndex].agcMode); + } + else + { + adrv9025_OrxOrx2AgcSetupBfSet(device, + orxChannelBitfieldAddr, + (uint8_t)gainMode[gainModeIndex].agcMode); + } + ADI_ERROR_RETURN(device->common.error.newAction); + + if (gainMode[gainModeIndex].agcMode == ADI_ADRV9025_MGC) + { + adrv9025_OrxAgcEnableFastRecoveryLoopBfSet(device, + orxChannelBitfieldAddr, + AGC_DISABLE_FAST_RECOVERY_LOOP_BITFIELD); + } + else + { + if ((device->devStateInfo.rxAgcPeakModeMask & orxChannelArr[rxChannelIndex]) > 0) + { + adrv9025_OrxAgcEnableFastRecoveryLoopBfSet(device, + orxChannelBitfieldAddr, + AGC_ENABLE_FAST_RECOVERY_LOOP_BITFIELD); + } + else + { + adrv9025_OrxAgcEnableFastRecoveryLoopBfSet(device, + orxChannelBitfieldAddr, + AGC_DISABLE_FAST_RECOVERY_LOOP_BITFIELD); + } + } + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxGainCtrlModeGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxAgcMode_t* gainMode) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + gainMode); + + gainMode->agcMode = (adi_adrv9025_RxAgcMode_e)0; + gainMode->rxChannelMask = 0; + + switch (rxChannel) + { + case(ADI_ADRV9025_RX1): + { + gainMode->rxChannelMask = (uint32_t)ADI_ADRV9025_RX1; + adrv9025_RxAgcSetupBfGet(device, + ADRV9025_BF_RX_CH0, + (uint8_t*)&gainMode->agcMode); + break; + } + case(ADI_ADRV9025_RX2): + { + gainMode->rxChannelMask = (uint32_t)ADI_ADRV9025_RX2; + adrv9025_RxAgcSetupBfGet(device, + ADRV9025_BF_RX_CH1, + (uint8_t*)&gainMode->agcMode); + break; + } + case(ADI_ADRV9025_RX3): + { + gainMode->rxChannelMask = (uint32_t)ADI_ADRV9025_RX3; + adrv9025_RxAgcSetupBfGet(device, + ADRV9025_BF_RX_CH2, + (uint8_t*)&gainMode->agcMode); + break; + } + case(ADI_ADRV9025_RX4): + { + gainMode->rxChannelMask = (uint32_t)ADI_ADRV9025_RX4; + adrv9025_RxAgcSetupBfGet(device, + ADRV9025_BF_RX_CH3, + (uint8_t*)&gainMode->agcMode); + break; + } + case(ADI_ADRV9025_ORX1): + { + gainMode->rxChannelMask = (uint32_t)ADI_ADRV9025_ORX1; + adrv9025_OrxOrx1AgcSetupBfGet(device, + ADRV9025_BF_ORX_CH0, + (uint8_t*)&gainMode->agcMode); + break; + } + case(ADI_ADRV9025_ORX2): + { + gainMode->rxChannelMask = (uint32_t)ADI_ADRV9025_ORX2; + adrv9025_OrxOrx1AgcSetupBfGet(device, + ADRV9025_BF_ORX_CH0, + (uint8_t*)&gainMode->agcMode); + break; + } + case(ADI_ADRV9025_ORX3): + { + gainMode->rxChannelMask = (uint32_t)ADI_ADRV9025_ORX3; + adrv9025_OrxOrx2AgcSetupBfGet(device, + ADRV9025_BF_ORX_CH1, + (uint8_t*)&gainMode->agcMode); + break; + } + case(ADI_ADRV9025_ORX4): + { + gainMode->rxChannelMask = (uint32_t)ADI_ADRV9025_ORX4; + adrv9025_OrxOrx2AgcSetupBfGet(device, + ADRV9025_BF_ORX_CH1, + (uint8_t*)&gainMode->agcMode); + break; + } + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid rxChannel for reading Rx Gain Ctrl Mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxDataFormatSetRangeCheck(adi_adrv9025_Device_t* device, + adi_adrv9025_RxDataFormat_t rxDataFormat[], + uint8_t arraySize) +{ + static const uint32_t ALL_RX_MASK = (uint32_t)(ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4); + static const uint32_t ALL_ORX_MASK = (uint32_t)(ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2 | ADI_ADRV9025_ORX3 | ADI_ADRV9025_ORX4); + static const uint8_t MINIMUM_NUM_FORMATTERS = 1; + static const uint8_t MAXIMUM_NUM_FORMATTERS = 4; + + uint8_t rxDataFormatConfigIndex = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + rxDataFormat); + + /* Check that arraySize is in valid range */ + if (arraySize < MINIMUM_NUM_FORMATTERS) + { + /* invalid number of formatters */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + arraySize, + "Invalid number of Rx formatters"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check that arraySize is in valid range */ + if (arraySize > MAXIMUM_NUM_FORMATTERS) + { + /* invalid number of formatters */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_WARN_CHECK_PARAM, + arraySize, + "WARNING: Number of Rx formatters is larger than expected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (rxDataFormatConfigIndex = 0; rxDataFormatConfigIndex < arraySize; rxDataFormatConfigIndex++) + { + if (rxDataFormat[rxDataFormatConfigIndex].rxChannelMask == ADI_ADRV9025_RXOFF) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->devStateInfo.profilesValid, + "Empty Rx channel mask selected for Rx data format configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((rxDataFormat[rxDataFormatConfigIndex].rxChannelMask & ALL_RX_MASK) > 0) && + ((device->devStateInfo.profilesValid & ADI_ADRV9025_RX_PROFILE_VALID) != ADI_ADRV9025_RX_PROFILE_VALID)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->devStateInfo.profilesValid, + "Rx channel selected for Rx data format configuration but Rx profile is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((rxDataFormat[rxDataFormatConfigIndex].rxChannelMask & ALL_ORX_MASK) > 0) && + ((device->devStateInfo.profilesValid & ADI_ADRV9025_ORX_PROFILE_VALID) != ADI_ADRV9025_ORX_PROFILE_VALID)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->devStateInfo.profilesValid, + "ORx channel selected for Rx data format configuration but ORx profile is invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check the format selected is valid*/ + if ((rxDataFormat[rxDataFormatConfigIndex].formatSelect != ADI_ADRV9025_GAIN_COMPENSATION_DISABLED) && + (rxDataFormat[rxDataFormatConfigIndex].formatSelect != ADI_ADRV9025_GAIN_WITH_FLOATING_POINT) && + (rxDataFormat[rxDataFormatConfigIndex].formatSelect != ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO) && + (rxDataFormat[rxDataFormatConfigIndex].formatSelect != ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) && + (rxDataFormat[rxDataFormatConfigIndex].formatSelect != ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) && + (rxDataFormat[rxDataFormatConfigIndex].formatSelect != ADI_ADRV9025_GAIN_WITH_EXTERNAL_SLICER) && + (rxDataFormat[rxDataFormatConfigIndex].formatSelect != ADI_ADRV9025_EMBED_OVERLOAD_MONITOR_DATA)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxDataFormat[rxDataFormatConfigIndex].formatSelect, + "Incorrect Rx Data Format selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Range Check params for Gain Compensation Mode Disabled*/ + if (rxDataFormat[rxDataFormatConfigIndex].formatSelect == ADI_ADRV9025_GAIN_COMPENSATION_DISABLED) + { + if ((rxDataFormat[rxDataFormatConfigIndex].integerConfigSettings.intSampleResolution != ADI_ADRV9025_INTEGER_12BIT_2SCOMP) && + (rxDataFormat[rxDataFormatConfigIndex].integerConfigSettings.intSampleResolution != ADI_ADRV9025_INTEGER_12BIT_SIGNED) && + (rxDataFormat[rxDataFormatConfigIndex].integerConfigSettings.intSampleResolution != ADI_ADRV9025_INTEGER_16BIT_2SCOMP) && + (rxDataFormat[rxDataFormatConfigIndex].integerConfigSettings.intSampleResolution != ADI_ADRV9025_INTEGER_16BIT_SIGNED) && + (rxDataFormat[rxDataFormatConfigIndex].integerConfigSettings.intSampleResolution != ADI_ADRV9025_INTEGER_24BIT_2SCOMP) && + (rxDataFormat[rxDataFormatConfigIndex].integerConfigSettings.intSampleResolution != ADI_ADRV9025_INTEGER_24BIT_SIGNED)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxDataFormat[rxDataFormatConfigIndex].integerConfigSettings.intSampleResolution, + "Incorrect Integer format and resolution selected while attempting to disable gain compensation"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + /*Check that floating point config is valid*/ + else if (rxDataFormat[rxDataFormatConfigIndex].formatSelect == ADI_ADRV9025_GAIN_WITH_FLOATING_POINT) + { + adrv9025_RxDataFormatSetFloatingPointRangeCheck(device, + &rxDataFormat[rxDataFormatConfigIndex].floatingPointConfig); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /*Check Integer and Slicer format configs if integer format selected*/ + else if ((rxDataFormat[rxDataFormatConfigIndex].formatSelect == ADI_ADRV9025_GAIN_WITH_EXTERNAL_SLICER) || + (rxDataFormat[rxDataFormatConfigIndex].formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) || + (rxDataFormat[rxDataFormatConfigIndex].formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) || + (rxDataFormat[rxDataFormatConfigIndex].formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO)) + { + adrv9025_RxDataFormatSetIntegerRangeCheck(device, + rxDataFormat[rxDataFormatConfigIndex].rxChannelMask, + rxDataFormat[rxDataFormatConfigIndex].formatSelect, + &rxDataFormat[rxDataFormatConfigIndex].integerConfigSettings, + &rxDataFormat[rxDataFormatConfigIndex].slicerConfigSettings); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* Check that embedded overload monitor config is valid */ + else if (rxDataFormat[rxDataFormatConfigIndex].formatSelect == ADI_ADRV9025_EMBED_OVERLOAD_MONITOR_DATA) + { + if ((rxDataFormat[rxDataFormatConfigIndex].rxChannelMask & ALL_ORX_MASK) > 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxDataFormat[rxDataFormatConfigIndex].rxChannelMask, + "Embedded overload indicator on Rx data is only valid for Rx1-Rx4 channels"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + adrv9025_RxDataFormatSetEmbOvldMonitorRangeCheck(device, + &rxDataFormat[rxDataFormatConfigIndex].embOvldMonitorSettings, + rxDataFormat[rxDataFormatConfigIndex].integerConfigSettings.intSampleResolution); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxDataFormatSet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxDataFormat_t rxDataFormat[], + uint8_t arraySize) +{ + static const uint8_t GAIN_COMP_EXT_LNA_DISABLE = 0; + static const uint8_t GAIN_COMP_TEMP_DISABLE = 0; + + uint8_t rxDataFormatConfigIndex = 0; + uint8_t intDataResolution = 0; + uint8_t intDataFormat = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check Rx data format config pointer is not NULL*/ + ADI_NULL_PTR_RETURN(&device->common, + rxDataFormat); + +#if ADI_ADRV9025_RX_RANGE_CHECK > 0 + adi_adrv9025_RxDataFormatSetRangeCheck(device, + rxDataFormat, + arraySize); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + for (rxDataFormatConfigIndex = 0; rxDataFormatConfigIndex < arraySize; rxDataFormatConfigIndex++) + { + /*If Floating Point mode selected, Configure floating point*/ + if (rxDataFormat[rxDataFormatConfigIndex].formatSelect == ADI_ADRV9025_GAIN_WITH_FLOATING_POINT) + { + adrv9025_RxDataFormatFloatingPointSet(device, + rxDataFormat[rxDataFormatConfigIndex].rxChannelMask, + &rxDataFormat[rxDataFormatConfigIndex].floatingPointConfig); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxGainCompExtLnaSet(device, + rxDataFormat[rxDataFormatConfigIndex].rxChannelMask, + rxDataFormat[rxDataFormatConfigIndex].externalLnaGain); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxGainCompTempEnableSet(device, + rxDataFormat[rxDataFormatConfigIndex].rxChannelMask, + rxDataFormat[rxDataFormatConfigIndex].tempCompensationEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /*Integer and slicer config settings*/ + else if ((rxDataFormat[rxDataFormatConfigIndex].formatSelect == ADI_ADRV9025_GAIN_WITH_EXTERNAL_SLICER) || + (rxDataFormat[rxDataFormatConfigIndex].formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_3PIN_MODE) || + (rxDataFormat[rxDataFormatConfigIndex].formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_4PIN_MODE) || + (rxDataFormat[rxDataFormatConfigIndex].formatSelect == ADI_ADRV9025_GAIN_WITH_INTERNAL_SLICER_NOGPIO)) + { + adrv9025_RxDataFormatIntegerSet(device, + rxDataFormat[rxDataFormatConfigIndex].rxChannelMask, + rxDataFormat[rxDataFormatConfigIndex].formatSelect, + &rxDataFormat[rxDataFormatConfigIndex].integerConfigSettings, + &rxDataFormat[rxDataFormatConfigIndex].slicerConfigSettings); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxGainCompExtLnaSet(device, + rxDataFormat[rxDataFormatConfigIndex].rxChannelMask, + rxDataFormat[rxDataFormatConfigIndex].externalLnaGain); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxGainCompTempEnableSet(device, + rxDataFormat[rxDataFormatConfigIndex].rxChannelMask, + rxDataFormat[rxDataFormatConfigIndex].tempCompensationEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* Embedded overload indicator settings */ + else if (rxDataFormat[rxDataFormatConfigIndex].formatSelect == ADI_ADRV9025_EMBED_OVERLOAD_MONITOR_DATA) + { + adrv9025_RxDataFormatEmbOvldMonitorSet(device, + rxDataFormat[rxDataFormatConfigIndex].rxChannelMask, + &rxDataFormat[rxDataFormatConfigIndex].embOvldMonitorSettings); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxGainCompExtLnaSet(device, + rxDataFormat[rxDataFormatConfigIndex].rxChannelMask, + rxDataFormat[rxDataFormatConfigIndex].externalLnaGain); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxGainCompTempEnableSet(device, + rxDataFormat[rxDataFormatConfigIndex].rxChannelMask, + rxDataFormat[rxDataFormatConfigIndex].tempCompensationEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /*If gain compensation disable is requested set floating point and integer foramatter regs to default*/ + else if (rxDataFormat[rxDataFormatConfigIndex].formatSelect == ADI_ADRV9025_GAIN_COMPENSATION_DISABLED) + { + /*Resolve Sample Resolution and format*/ + adrv9025_RxIntSampleResFormatResolve(device, + &rxDataFormat[rxDataFormatConfigIndex].integerConfigSettings, + &intDataResolution, + &intDataFormat); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Disable gain compensation and reset the formatter settings to default */ + adrv9025_RxDataFormatGainCompDisable(device, + rxDataFormat[rxDataFormatConfigIndex].rxChannelMask, + intDataFormat, + intDataResolution); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxGainCompTempEnableSet(device, + rxDataFormat[rxDataFormatConfigIndex].rxChannelMask, + GAIN_COMP_TEMP_DISABLE); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxGainCompExtLnaSet(device, + rxDataFormat[rxDataFormatConfigIndex].rxChannelMask, + GAIN_COMP_EXT_LNA_DISABLE); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxDataFormatGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxDataFormat_t* rxDataFormat) +{ + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check Rx data format config pointer is not NULL*/ + ADI_NULL_PTR_RETURN(&device->common, + rxDataFormat); + + /*Retrieve Rx Data Format select*/ + adrv9025_RxDataFormatSelectGet(device, + rxChannel, + &rxDataFormat->formatSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Fetch floating point config and update rxDataFormat with floating point config*/ + adrv9025_RxDataFormatFloatingPointGet(device, + rxChannel, + &rxDataFormat->floatingPointConfig); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get integer format config and update rxDataFormat with integer slicer config*/ + adrv9025_RxDataFormatIntegerGet(device, + rxChannel, + &rxDataFormat->integerConfigSettings, + &rxDataFormat->slicerConfigSettings); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get embedded overload indicator config and update rxDataFormat with embedded overload monitor config*/ + adrv9025_RxDataFormatEmbOvldMonitorGet(device, + rxChannel, + &rxDataFormat->embOvldMonitorSettings); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxGainCompExtLnaGet(device, + rxChannel, + &rxDataFormat->externalLnaGain); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxGainCompTempEnableGet(device, + rxChannel, + &rxDataFormat->tempCompensationEnable); + ADI_ERROR_RETURN(device->common.error.newAction); + + rxDataFormat->rxChannelMask = (uint32_t)rxChannel; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxSlicerPositionGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint8_t* slicerPosition) +{ + adrv9025_BfRxChanAddr_e rxChannelBitfieldAddr = ADRV9025_BF_ALL_RX_CHANNELS; + adrv9025_BfOrxChanAddr_e orxChannelBitfieldAddr = ADRV9025_BF_ALL_ORX_CHANNELS; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check slicerPosition pointer is not NULL*/ + ADI_NULL_PTR_RETURN(&device->common, + slicerPosition); + + if ((rxChannel == ADI_ADRV9025_RX1) || + (rxChannel == ADI_ADRV9025_RX2) || + (rxChannel == ADI_ADRV9025_RX3) || + (rxChannel == ADI_ADRV9025_RX4)) + { + adrv9025_RxBitfieldAddressGet(device, + rxChannel, + &rxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxRxdpSlicerPositionBfGet(device, + rxChannelBitfieldAddr, + slicerPosition); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if ((rxChannel == ADI_ADRV9025_ORX1) || + (rxChannel == ADI_ADRV9025_ORX2) || + (rxChannel == ADI_ADRV9025_ORX3) || + (rxChannel == ADI_ADRV9025_ORX4)) + { + adrv9025_OrxBitfieldAddressGet(device, + rxChannel, + &orxChannelBitfieldAddr); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_OrxRxdpSlicerPositionBfGet(device, + orxChannelBitfieldAddr, + slicerPosition); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Incorrect channel encountered while attempting to read slicer position. Valid Rx channels are Rx1-Rx4, ORx1-ORx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxLoSourceGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_LoSel_e* rxLoSource) +{ + static const uint32_t ALL_RX_MASK = (uint32_t)(ADI_ADRV9025_RX1 | ADI_ADRV9025_RX2 | ADI_ADRV9025_RX3 | ADI_ADRV9025_RX4); + static const uint32_t ALL_ORX_MASK = (uint32_t)(ADI_ADRV9025_ORX1 | ADI_ADRV9025_ORX2 | ADI_ADRV9025_ORX3 | ADI_ADRV9025_ORX4); + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check Rx data format config pointer is not NULL*/ + ADI_NULL_PTR_RETURN(&device->common, + rxLoSource); + +#if ADI_ADRV9025_RX_RANGE_CHECK > 0 + adrv9025_RxLoSourceGetRangeCheck(device, + rxChannel, + rxLoSource); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + if (((uint32_t)rxChannel & ALL_RX_MASK) > 0) + { + adrv9025_RxLoSourceGet(device, + rxChannel, + rxLoSource); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (((uint32_t)rxChannel & ALL_ORX_MASK) > 0) + { + adrv9025_OrxLoSourceGet(device, + rxChannel, + rxLoSource); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxTempGainCompSet(adi_adrv9025_Device_t* device, + uint32_t rxChannelMask, + int8_t gainValue) +{ + static const uint32_t ALL_RX_MASK = ((uint32_t)ADI_ADRV9025_RX1 | (uint32_t)ADI_ADRV9025_RX2 | (uint32_t)ADI_ADRV9025_RX3 | (uint32_t)ADI_ADRV9025_RX4); + static const uint32_t ALL_ORX_MASK = ((uint32_t)ADI_ADRV9025_ORX1 | (uint32_t)ADI_ADRV9025_ORX2 | (uint32_t)ADI_ADRV9025_ORX3 | (uint32_t)ADI_ADRV9025_ORX4 + ); + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfRxChanAddr_e bfRxArray[] = {ADRV9025_BF_RX_CH0, ADRV9025_BF_RX_CH1, ADRV9025_BF_RX_CH2, ADRV9025_BF_RX_CH3}; + adrv9025_BfOrxChanAddr_e bfOrxArray[] = {ADRV9025_BF_ORX_CH0, ADRV9025_BF_ORX_CH1}; + uint32_t chanIndex = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check Rx channel mask is valid. It can represent both Rx and ORx channels. Recal it is a bitfield.*/ + if ((rxChannelMask > (ALL_RX_MASK | ALL_ORX_MASK)) || + (rxChannelMask == ADI_ADRV9025_RXOFF)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "Channel provided is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check that gainValue is within allowable range.*/ + if ((gainValue < -63) || (gainValue > 63)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gainValue, + "Gain value must be within range -63 to +63."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /*Register expects sign-magnitude value hence if value is negative, need to convert out of two's compliment and set the sign bit (bit 7) to 1*/ + if (gainValue < 0) + { + gainValue = (~gainValue + 1) | 0x40; + } + } + + /* Program up the Rx channels */ + for (chanIndex = 0; chanIndex < (sizeof(bfRxArray) / sizeof(bfRxArray[0])); ++chanIndex) + { + if ((rxChannelMask & (0x1 << chanIndex)) > 0) + { + recoveryAction = adrv9025_RxRxTempGainCompBfSet(device, + bfRxArray[chanIndex], + (uint8_t)gainValue); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + rxChannelMask, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Program up the ORx channels */ + for (chanIndex = 0; chanIndex < (sizeof(bfOrxArray) / sizeof(bfOrxArray[0])); ++chanIndex) + { + /* ORx analog channels 1 and 2 map to the same digital channel ORx 0 */ + /* ORx analog channels 3 and 4 map to the same digital channel ORx 1 */ + /* chanIndex is multiplied by 2 (i.e. << 1) in order to skip two bits at a time.*/ + if ((rxChannelMask & (0x30 << (chanIndex << 1))) > 0) + { + recoveryAction = adrv9025_OrxRxTempGainCompBfSet(device, + bfOrxArray[chanIndex], + (uint8_t)gainValue); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + rxChannelMask, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxTempGainCompGet(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannelSel, + int8_t* gainValue) +{ + static const uint32_t ALL_RX_MASK = ((uint32_t)ADI_ADRV9025_RX1 | (uint32_t)ADI_ADRV9025_RX2 | (uint32_t)ADI_ADRV9025_RX3 | (uint32_t)ADI_ADRV9025_RX4); + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfRxChanAddr_e bfRxArray[] = {ADRV9025_BF_RX_CH0, ADRV9025_BF_RX_CH1, ADRV9025_BF_RX_CH2, ADRV9025_BF_RX_CH3}; + adrv9025_BfOrxChanAddr_e bfOrxArray[] = {ADRV9025_BF_ORX_CH0, ADRV9025_BF_ORX_CH1}; + uint32_t chanIndex = 0; + uint8_t gainRead = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + /* Check gain value pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + gainValue); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check Rx channel mask is valid. It can represent both Rx and ORx channels. Recal it is a bitfield.*/ + if ((rxChannelSel != ADI_ADRV9025_RX1) && + (rxChannelSel != ADI_ADRV9025_RX2) && + (rxChannelSel != ADI_ADRV9025_RX3) && + (rxChannelSel != ADI_ADRV9025_RX4) && + (rxChannelSel != ADI_ADRV9025_ORX1) && + (rxChannelSel != ADI_ADRV9025_ORX2) && + (rxChannelSel != ADI_ADRV9025_ORX3) && + (rxChannelSel != ADI_ADRV9025_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "Channel provided is out of range or multiple channels specified (only one channel can be read at a time)."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Retrieve the value from the Rx/ORx channel specified */ + if ((uint32_t)rxChannelSel < ALL_RX_MASK) + { + for (chanIndex = 0; chanIndex < (sizeof(bfRxArray) / sizeof(bfRxArray[0])); ++chanIndex) + { + if ((rxChannelSel & (0x1 << chanIndex)) > 0) + { + recoveryAction = adrv9025_RxRxTempGainCompBfGet(device, + bfRxArray[chanIndex], + &gainRead); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + rxChannelSel, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + } + } + else + { + for (chanIndex = 0; chanIndex < (sizeof(bfOrxArray) / sizeof(bfOrxArray[0])); ++chanIndex) + { + /* ORx virtual channels 1 and 3 map to the same physical channel ORx 0 */ + /* ORx virtual channels 2 and 4 map to the same physical channel ORx 1 */ + /* chanIndex is multiplied by 2 (i.e. << 1) in order to skip two bits at a time.*/ + if ((rxChannelSel & (0x30 << (chanIndex << 1))) > 0) + { + recoveryAction = adrv9025_OrxRxTempGainCompBfGet(device, + bfOrxArray[chanIndex], + &gainRead); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + rxChannelSel, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + } + } + + /* Convert from 7-bit sign magnitude format to 8-bit two's compliment */ + if ((gainRead & 0x40) > 0) + { + /* Handle the negative case */ + *gainValue = (int8_t)(~((gainRead & 0x3F) - 1)); + } + else + { + /* Handle the positive case */ + *gainValue = (int8_t)gainRead; + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_GpioForAnalogDualBandOperationSet(adi_adrv9025_Device_t* device, + uint8_t enable) +{ + static const uint8_t GPIO_ANA_UPPER_NIBBLE_SRC_CTRL_DEFAULT = 0x00; + static const uint8_t GPIO_ANA_LOWER_NIBBLE_SRC_CTRL_DEFAULT = 0x00; + static const uint8_t GPIO_ANA_UPPER_NIBBLE_SRC_CTRL_DUALBAND = 0x07; + static const uint8_t GPIO_ANA_LOWER_NIBBLE_SRC_CTRL_DUALBAND = 0x07; + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_RX_DUALBAND_LNA_CTRL_WORD_OUTPUT; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t gpioAnalogInputOutputMask = 0xFF; + uint8_t resourceAcquisitionStatus = ADI_FAILURE; + uint8_t resourceReleaseStatus = ADI_FAILURE; + uint8_t numSharedResources = 8; + int32_t sharedResourceArr[ADI_ADRV9025_NUM_GPIOS_IN_RX_DUALBAND_CTRL_WORD_OUTPUT_FEATURE] = + { + ADI_ADRV9025_GPIO_ANA_00, + ADI_ADRV9025_GPIO_ANA_01, + ADI_ADRV9025_GPIO_ANA_02, + ADI_ADRV9025_GPIO_ANA_03, + ADI_ADRV9025_GPIO_ANA_04, + ADI_ADRV9025_GPIO_ANA_05, + ADI_ADRV9025_GPIO_ANA_06, + ADI_ADRV9025_GPIO_ANA_07 + }; + + /* Sanity checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if (enable == ADI_DISABLE) + { + /*Release All Shared Analog GPIOs*/ + adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, + &sharedResourceArr[0], + numSharedResources, + THIS_FEATURE_ID, + &resourceReleaseStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to release shared Analog GPIO during disabling of Rx1, Rx2, R3, R4 dualband ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceReleaseStatus, + "Error while attempting to release shared Analog GPIO during disabling of Rx1, Rx2, R3, R4 dualband ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /*Set GPIO_ANA[7:0] to input on disable request*/ + adi_adrv9025_GpioAnalogInputDirSet(device, + gpioAnalogInputOutputMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set Analog GPIO direction ctrl to default during disabling of Rx1, Rx2, R3, R4 dualband ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + /*Set Analog GPIO Src Ctrl Lower Nibble to default*/ + adrv9025_CoreGpioAnalogLowerNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + GPIO_ANA_LOWER_NIBBLE_SRC_CTRL_DEFAULT); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set Analog GPIO lower nibble source ctrl to default during disabling of Rx1, Rx2 dualband ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Analog GPIO Src Ctrl Upper Nibble to default*/ + adrv9025_CoreGpioAnalogUpperNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + GPIO_ANA_UPPER_NIBBLE_SRC_CTRL_DEFAULT); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to set Analog GPIO lower nibble source ctrl to default during disabling of Rx3, Rx4 dualband ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Finish and return.*/ + return device->common.error.newAction; + } + + /*Acquire Shared Analog GPIOs*/ + adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO_ANALOG, + &sharedResourceArr[0], + numSharedResources, + THIS_FEATURE_ID, + &resourceAcquisitionStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error while attempting to acquire shared Analog GPIO during enabling of R1, R2, Rx3, Rx4 dualband ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceAcquisitionStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceAcquisitionStatus, + "Error while attempting to acquire shared Analog GPIO during enabling of Rx3, Rx4 dualband ctrl output. Please check if the GPIOs in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Set GPIO_ANA[7:0] to output on enabling*/ + recoveryAction = adi_adrv9025_GpioAnalogOutputDirSet(device, + gpioAnalogInputOutputMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025_RxDualbandLnaCtrlPinReportError(device, + &sharedResourceArr[0], + numSharedResources, + recoveryAction, + "Error while attempting to set Analog GPIO lower nibble direction ctrl to dualband lna ctrl during enabling of Rx3, Rx4 dualband ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Analog GPIO Src Ctrl Lower Nibble to dual band LNA ctrl */ + recoveryAction = adrv9025_CoreGpioAnalogLowerNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + GPIO_ANA_LOWER_NIBBLE_SRC_CTRL_DUALBAND); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_RxDualbandLnaCtrlPinReportError(device, + &sharedResourceArr[0], + numSharedResources, + recoveryAction, + "Error while attempting to set Analog GPIO lower nibble source ctrl to dualband lna ctrl during enabling of Rx1, Rx2 dualband ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Analog GPIO Src Ctrl Lower Nibble to dual band LNA ctrl */ + recoveryAction = adrv9025_CoreGpioAnalogUpperNibbleSourceControlBfSet(device, + ADRV9025_BF_CORE, + GPIO_ANA_UPPER_NIBBLE_SRC_CTRL_DUALBAND); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025_RxDualbandLnaCtrlPinReportError(device, + &sharedResourceArr[0], + numSharedResources, + recoveryAction, + "Error while attempting to set Analog GPIO lower nibble source ctrl to dualband lna ctrl during enabling of Rx3, Rx4 dualband ctrl output"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_RxNcoShifterSet(adi_adrv9025_Device_t *device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxNcoShifterCfg_t rxShiftConfig, + adi_adrv9025_RxDdc_e rxDdcMode, + uint32_t enableMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + uint8_t enable = 0x00; + uint8_t extData[] = {ADRV9025_CPU_OBJECTID_GS_RX_DDC, (uint8_t)rxChannel, (uint8_t)rxDdcMode, enable}; + uint8_t armData[32u] = {0u}; + uint8_t cmdStatusByte = 0u; + int32_t errHdl = 0; + + static const uint8_t CPU_ERR_CODE = 0x0E; + static const uint8_t bandANco1 = 0x0A; + static const uint8_t bandBNco1 = 0x09; + static const uint8_t bandANco2 = 0x06; + static const uint8_t bandBNco2 = 0x05; + static const uint8_t bandABEnable = 0x80; + + uint8_t rxNcoEnableMax = (ADI_ADRV9025_BAND_A_NCO_1 | ADI_ADRV9025_BAND_B_NCO_1 | ADI_ADRV9025_BAND_A_NCO_2 | ADI_ADRV9025_BAND_B_NCO_2); + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API_PRIV); + + /* Check if enable mask is valid */ + if (enableMask > rxNcoEnableMax) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Invalid enableMask"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Calculate byte to be passed to the ARM */ + if ((enableMask & ADI_ADRV9025_BAND_A_NCO_1) == ADI_ADRV9025_BAND_A_NCO_1) + { + enable = bandANco1; + } + if ((enableMask & ADI_ADRV9025_BAND_B_NCO_1) == ADI_ADRV9025_BAND_B_NCO_1) + { + enable |= bandBNco1; + } + if ((enableMask & ADI_ADRV9025_BAND_A_NCO_2) == ADI_ADRV9025_BAND_A_NCO_2) + { + enable |= bandANco2; + } + if ((enableMask & ADI_ADRV9025_BAND_B_NCO_2) == ADI_ADRV9025_BAND_B_NCO_2) + { + enable |= bandBNco2; + } + + extData[3] = enable; + + /* Check if rxDdcMode is valid */ + if (rxDdcMode > ADI_ADRV9025_RXDDC_DEC2_REALIF) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Invalid rxDdcMode value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* set the band combine bit in extended data if bandAbCombinedEnable = 1 */ + if (rxShiftConfig.bandAbCombinedEnable == 1) + { + extData[2] |= bandABEnable; + } + + /* byte pack the shifter configuration in the arm mailbox array */ + rxShiftConfig.bandAInputBandWidth_kHz = rxShiftConfig.bandAInputBandWidth_kHz * 1000; + + armData[0] = (uint8_t)(rxShiftConfig.bandAInputBandWidth_kHz & 0xFF); + armData[1] = (uint8_t)((rxShiftConfig.bandAInputBandWidth_kHz >> 8) & 0xFF); + armData[2] = (uint8_t)((rxShiftConfig.bandAInputBandWidth_kHz >> 16) & 0xFF); + armData[3] = (uint8_t)((rxShiftConfig.bandAInputBandWidth_kHz >> 24) & 0xFF); + + rxShiftConfig.bandAInputCenterFreq_kHz = rxShiftConfig.bandAInputCenterFreq_kHz * 1000; + + armData[4] = (uint8_t)(rxShiftConfig.bandAInputCenterFreq_kHz & 0xFF); + armData[5] = (uint8_t)((rxShiftConfig.bandAInputCenterFreq_kHz >> 8) & 0xFF); + armData[6] = (uint8_t)((rxShiftConfig.bandAInputCenterFreq_kHz >> 16) & 0xFF); + armData[7] = (uint8_t)((rxShiftConfig.bandAInputCenterFreq_kHz >> 24) & 0xFF); + + rxShiftConfig.bandANco1Freq_kHz = rxShiftConfig.bandANco1Freq_kHz * 1000; + + armData[8] = (uint8_t)(rxShiftConfig.bandANco1Freq_kHz & 0xFF); + armData[9] = (uint8_t)((rxShiftConfig.bandANco1Freq_kHz >> 8) & 0xFF); + armData[10] = (uint8_t)((rxShiftConfig.bandANco1Freq_kHz >> 16) & 0xFF); + armData[11] = (uint8_t)((rxShiftConfig.bandANco1Freq_kHz >> 24) & 0xFF); + + rxShiftConfig.bandANco2Freq_kHz = rxShiftConfig.bandANco2Freq_kHz * 1000; + + armData[12] = (uint8_t)(rxShiftConfig.bandANco2Freq_kHz & 0xFF); + armData[13] = (uint8_t)((rxShiftConfig.bandANco2Freq_kHz >> 8) & 0xFF); + armData[14] = (uint8_t)((rxShiftConfig.bandANco2Freq_kHz >> 16) & 0xFF); + armData[15] = (uint8_t)((rxShiftConfig.bandANco2Freq_kHz >> 24) & 0xFF); + + rxShiftConfig.bandBInputBandWidth_kHz = rxShiftConfig.bandBInputBandWidth_kHz * 1000; + + armData[16] = (uint8_t)(rxShiftConfig.bandBInputBandWidth_kHz & 0xFF); + armData[17] = (uint8_t)((rxShiftConfig.bandBInputBandWidth_kHz >> 8) & 0xFF); + armData[18] = (uint8_t)((rxShiftConfig.bandBInputBandWidth_kHz >> 16) & 0xFF); + armData[19] = (uint8_t)((rxShiftConfig.bandBInputBandWidth_kHz >> 24) & 0xFF); + + rxShiftConfig.bandBInputCenterFreq_kHz = rxShiftConfig.bandBInputCenterFreq_kHz * 1000; + + armData[20] = (uint8_t)(rxShiftConfig.bandBInputCenterFreq_kHz & 0xFF); + armData[21] = (uint8_t)((rxShiftConfig.bandBInputCenterFreq_kHz >> 8) & 0xFF); + armData[22] = (uint8_t)((rxShiftConfig.bandBInputCenterFreq_kHz >> 16) & 0xFF); + armData[23] = (uint8_t)((rxShiftConfig.bandBInputCenterFreq_kHz >> 24) & 0xFF); + + rxShiftConfig.bandBNco1Freq_kHz = rxShiftConfig.bandBNco1Freq_kHz * 1000; + + armData[24] = (uint8_t)(rxShiftConfig.bandBNco1Freq_kHz & 0xFF); + armData[25] = (uint8_t)((rxShiftConfig.bandBNco1Freq_kHz >> 8) & 0xFF); + armData[26] = (uint8_t)((rxShiftConfig.bandBNco1Freq_kHz >> 16) & 0xFF); + armData[27] = (uint8_t)((rxShiftConfig.bandBNco1Freq_kHz >> 24) & 0xFF); + + rxShiftConfig.bandBNco2Freq_kHz = rxShiftConfig.bandBNco2Freq_kHz * 1000; + + armData[28] = (uint8_t)(rxShiftConfig.bandBNco2Freq_kHz & 0xFF); + armData[29] = (uint8_t)((rxShiftConfig.bandBNco2Freq_kHz >> 8) & 0xFF); + armData[30] = (uint8_t)((rxShiftConfig.bandBNco2Freq_kHz >> 16) & 0xFF); + armData[31] = (uint8_t)((rxShiftConfig.bandBNco2Freq_kHz >> 24) & 0xFF); + + /* Write data to ARM mailbox */ + recoveryAction = adi_adrv9025_CpuMemWrite(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_SET, + &armData[0], + sizeof(armData), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + armData, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Executing Arm set Command */ + recoveryAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_SET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + extData, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_SET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_SETDEFAULTCONDITION_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_SETDEFAULTCONDITION_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte & CPU_ERR_CODE) > 0) + { + recoveryAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + cmdStatusByte, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_RxNcoShifterGet(adi_adrv9025_Device_t *device, + adi_adrv9025_RxChannels_e rxChannel, + adi_adrv9025_RxNcoBandSelect_e ncoBandSelect, + adi_adrv9025_RxNcoShifterCfg_t *rxShiftConfigGet, + adi_adrv9025_RxDdc_e *rxDdcMode, + uint32_t *enableMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t extData[] = {ADRV9025_CPU_OBJECTID_GS_RX_DDC, 0}; + uint8_t armData[34u] = {0u}; + uint8_t cmdStatusByte = 0u; + uint8_t ddcModeRead = 0x00; + int32_t errHdl = 0; + uint8_t armEnableMask = 0x00; + + static const uint8_t ARM_ERR_CODE = 0x0E; + static const uint8_t ncoOff = 0x00; + static const uint8_t bandANco1 = 0x0A; + static const uint8_t bandBNco1 = 0x09; + static const uint8_t bandANco2 = 0x06; + static const uint8_t bandBNco2 = 0x05; + static const uint8_t bandABNco_1_2 = 0x0F; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + /* Check rxShiftConfigGet pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, rxShiftConfigGet); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API_PRIV); + + if ((ncoBandSelect != ADI_ADRV9025_NCO_BANDA) && (ncoBandSelect != ADI_ADRV9025_NCO_BANDB)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NcoBandSelect, + "NCO Band Selection provided is out of range"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + extData[0] = ADRV9025_CPU_OBJECTID_GS_RX_DDC; + extData[1] = (uint8_t)rxChannel; + + /* Executing Arm set Command */ + recoveryAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + extData, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_GET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_SETDEFAULTCONDITION_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_SETDEFAULTCONDITION_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte & ARM_ERR_CODE) > 0) + { + recoveryAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Read the data from ARM mailbox */ + recoveryAction = adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + armData, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + rxShiftConfigGet->bandAInputBandWidth_kHz = (uint32_t)armData[0]; + rxShiftConfigGet->bandAInputBandWidth_kHz |= (uint32_t)(armData[1] << 8 ); + rxShiftConfigGet->bandAInputBandWidth_kHz |= (uint32_t)(armData[2] << 16); + rxShiftConfigGet->bandAInputBandWidth_kHz |= (uint32_t)(armData[3] << 24); + rxShiftConfigGet->bandAInputBandWidth_kHz = rxShiftConfigGet->bandAInputBandWidth_kHz / 1000; + + rxShiftConfigGet->bandAInputCenterFreq_kHz = (uint32_t)armData[4]; + rxShiftConfigGet->bandAInputCenterFreq_kHz |= (uint32_t)(armData[5] << 8 ); + rxShiftConfigGet->bandAInputCenterFreq_kHz |= (uint32_t)(armData[6] << 16); + rxShiftConfigGet->bandAInputCenterFreq_kHz |= (uint32_t)(armData[7] << 24); + rxShiftConfigGet->bandAInputCenterFreq_kHz = rxShiftConfigGet->bandAInputCenterFreq_kHz / 1000; + + rxShiftConfigGet->bandANco1Freq_kHz = (uint32_t)armData[8]; + rxShiftConfigGet->bandANco1Freq_kHz |= (uint32_t)(armData[9] << 8 ); + rxShiftConfigGet->bandANco1Freq_kHz |= (uint32_t)(armData[10] << 16); + rxShiftConfigGet->bandANco1Freq_kHz |= (uint32_t)(armData[11] << 24); + rxShiftConfigGet->bandANco1Freq_kHz = rxShiftConfigGet->bandANco1Freq_kHz / 1000; + + rxShiftConfigGet->bandANco2Freq_kHz = (uint32_t)armData[12]; + rxShiftConfigGet->bandANco2Freq_kHz |= (uint32_t)(armData[13] << 8 ); + rxShiftConfigGet->bandANco2Freq_kHz |= (uint32_t)(armData[14] << 16); + rxShiftConfigGet->bandANco2Freq_kHz |= (uint32_t)(armData[15] << 24); + rxShiftConfigGet->bandANco2Freq_kHz = rxShiftConfigGet->bandANco2Freq_kHz / 1000; + + rxShiftConfigGet->bandBInputBandWidth_kHz = (uint32_t)armData[16]; + rxShiftConfigGet->bandBInputBandWidth_kHz |= (uint32_t)(armData[17] << 8 ); + rxShiftConfigGet->bandBInputBandWidth_kHz |= (uint32_t)(armData[18] << 16); + rxShiftConfigGet->bandBInputBandWidth_kHz |= (uint32_t)(armData[19] << 24); + rxShiftConfigGet->bandBInputBandWidth_kHz = rxShiftConfigGet->bandBInputBandWidth_kHz / 1000; + + rxShiftConfigGet->bandBInputCenterFreq_kHz = (uint32_t)armData[20]; + rxShiftConfigGet->bandBInputCenterFreq_kHz |= (uint32_t)(armData[21] << 8 ); + rxShiftConfigGet->bandBInputCenterFreq_kHz |= (uint32_t)(armData[22] << 16); + rxShiftConfigGet->bandBInputCenterFreq_kHz |= (uint32_t)(armData[23] << 24); + rxShiftConfigGet->bandBInputCenterFreq_kHz = rxShiftConfigGet->bandBInputCenterFreq_kHz / 1000; + + rxShiftConfigGet->bandBNco1Freq_kHz = (uint32_t)armData[24]; + rxShiftConfigGet->bandBNco1Freq_kHz |= (uint32_t)(armData[25] << 8 ); + rxShiftConfigGet->bandBNco1Freq_kHz |= (uint32_t)(armData[26] << 16); + rxShiftConfigGet->bandBNco1Freq_kHz |= (uint32_t)(armData[27] << 24); + rxShiftConfigGet->bandBNco1Freq_kHz = rxShiftConfigGet->bandBNco1Freq_kHz / 1000; + + rxShiftConfigGet->bandBNco2Freq_kHz = (uint32_t)armData[28]; + rxShiftConfigGet->bandBNco2Freq_kHz |= (uint32_t)(armData[29] << 8 ); + rxShiftConfigGet->bandBNco2Freq_kHz |= (uint32_t)(armData[30] << 16); + rxShiftConfigGet->bandBNco2Freq_kHz |= (uint32_t)(armData[31] << 24); + rxShiftConfigGet->bandBNco2Freq_kHz = rxShiftConfigGet->bandBNco2Freq_kHz / 1000; + + rxShiftConfigGet->bandAbCombinedEnable = ((uint32_t)(armData[32] & 0x80) >> 7); + + ddcModeRead = (uint32_t)(armData[32] & 0x7F); + + *rxDdcMode = (adi_adrv9025_RxDdc_e)ddcModeRead; + + /* Check if rxDdcMode returned value is valid */ + if (*rxDdcMode > ADI_ADRV9025_RXDDC_DEC2_REALIF) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Invalid rxDdcMode value returned"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + armEnableMask = armData[33]; + + if (armEnableMask <= bandABNco_1_2) + { + if (armEnableMask == ncoOff) + { + *enableMask = ADI_ADRV9025_NCO_OFF; + } + /* Calculate byte to be passed to the ARM */ + if ((armEnableMask & bandANco1) == bandANco1) + { + *enableMask = ADI_ADRV9025_BAND_A_NCO_1; + } + if ((armEnableMask & bandBNco1) == bandBNco1) + { + *enableMask |= ADI_ADRV9025_BAND_B_NCO_1; + } + if ((armEnableMask & bandANco2) == bandANco2) + { + *enableMask |= ADI_ADRV9025_BAND_A_NCO_2; + } + if ((armEnableMask & bandBNco2) == bandBNco2) + { + *enableMask |= ADI_ADRV9025_BAND_B_NCO_2; + } + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Invalid RX NCO Enable value returned"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_RxAgcClkModeSet(adi_adrv9025_Device_t *device, + uint32_t rxChannelMask, + adi_adrv9025_RxAgcMode_e agcMode) +{ + /* Check that the passed device pointer is not NULL */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + /* Add entry to the API log */ + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + uint8_t rxChannelListPosition = 0; + int32_t recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + adi_adrv9025_RxChannels_e rxChannel = ADI_ADRV9025_RXOFF; + adrv9025_BfRxChanAddr_e rxChannelBfAddr = ADRV9025_BF_ALL_RX_CHANNELS; + + static const uint8_t rxChannelMax = 0x0F; + static const adi_adrv9025_RxChannels_e rxChannelList[] = {ADI_ADRV9025_RX1, ADI_ADRV9025_RX2, ADI_ADRV9025_RX3, ADI_ADRV9025_RX4}; + static const uint8_t rxChannelListSize = (adi_adrv9025_RxChannels_e)( sizeof(rxChannelList) / sizeof(rxChannelList[0])); + + if ((rxChannelMask > rxChannelMax) || (rxChannelMask == 0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannelMask, + "Invalid rxChannelMask. Valid range (1-15)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Iterate through channel mask */ + for (rxChannelListPosition = 0; rxChannelListPosition < rxChannelListSize; rxChannelListPosition++) + { + if ((rxChannelMask & (uint32_t)rxChannelList[rxChannelListPosition]) == (uint32_t)rxChannelList[rxChannelListPosition]) + { + rxChannel = (adi_adrv9025_RxChannels_e)rxChannelList[rxChannelListPosition]; + + switch (rxChannel) + { + case ADI_ADRV9025_RX1: + rxChannelBfAddr = ADRV9025_BF_RX_CH0; + break; + case ADI_ADRV9025_RX2: + rxChannelBfAddr = ADRV9025_BF_RX_CH1; + break; + case ADI_ADRV9025_RX3: + rxChannelBfAddr = ADRV9025_BF_RX_CH2; + break; + case ADI_ADRV9025_RX4: + rxChannelBfAddr = ADRV9025_BF_RX_CH3; + break; + case ADI_ADRV9025_ORX1: + case ADI_ADRV9025_ORX2: + case ADI_ADRV9025_ORX3: + case ADI_ADRV9025_ORX4: + case ADI_ADRV9025_LB12: + case ADI_ADRV9025_LB34: + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + recoveryAction = adrv9025_RxAgcClkDivideRatioBfSet(device, rxChannelBfAddr, agcMode); + + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + bfValue, + "Failed to set AGC clock ratio mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_RxAgcClkModeGet(adi_adrv9025_Device_t *device, + adi_adrv9025_RxChannels_e rxChannel, + uint8_t *agcMode) +{ + /* Check that the passed device pointer is not NULL */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + /* Check agcMode is not null */ + ADI_NULL_PTR_RETURN(&device->common, agcMode); + + /* Add entry to the API log */ + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + adrv9025_BfRxChanAddr_e rxChannelBfAddr = ADRV9025_BF_ALL_RX_CHANNELS; + + int32_t recoveryAction = ADI_COMMON_ACT_ERR_RESET_FULL; + + switch (rxChannel) + { + case ADI_ADRV9025_RX1: + rxChannelBfAddr = ADRV9025_BF_RX_CH0; + break; + case ADI_ADRV9025_RX2: + rxChannelBfAddr = ADRV9025_BF_RX_CH1; + break; + case ADI_ADRV9025_RX3: + rxChannelBfAddr = ADRV9025_BF_RX_CH2; + break; + case ADI_ADRV9025_RX4: + rxChannelBfAddr = ADRV9025_BF_RX_CH3; + break; + case ADI_ADRV9025_ORX1: + case ADI_ADRV9025_ORX2: + case ADI_ADRV9025_ORX3: + case ADI_ADRV9025_ORX4: + case ADI_ADRV9025_LB12: + case ADI_ADRV9025_LB34: + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + recoveryAction = adrv9025_RxAgcClkDivideRatioBfGet(device, rxChannelBfAddr, agcMode); + + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + bfValue, + "Failed to get AGC clock ratio mode status"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_RxAgcSyncGpioPinSet(adi_adrv9025_Device_t *device, + uint8_t rxChannelMask, + adi_adrv9025_GpioPinSel_e hybridSelPin1) +{ + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_RX_AGC_HYBRID_MODE; + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + int32_t sharedResourceArr[ADI_ADRV9025_NUM_GPIOS_IN_RX_AGC_HYBRID_FEATURE] = { 0 }; + uint32_t gpioInputDirMask = 0; + uint8_t resourceAcqReleaseStatus = ADI_FAILURE; + static uint16_t channel[4] = { 0x13CB, 0x15CB, 0x17CB, 0x19CB }; + uint8_t i, j; + + /* Check device pointer is not null */ + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + /* Setup Hybrid mode select pin0 */ + sharedResourceArr[0] = hybridSelPin1; + gpioInputDirMask = ((uint32_t)0x00000001 << hybridSelPin1); + + /*Acquire Shared GPIOs to ensure that they are not in use by another feature*/ + retVal = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + 1, + THIS_FEATURE_ID, + &resourceAcqReleaseStatus); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Unable to release requested GPIOs for Hybrid Mode use. Please check if the GPIOs are in use by another feature"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Set the direction as input for selected Rx AGC Hybrid Mode on release*/ + if ((retVal = adi_adrv9025_GpioInputDirSet(device, gpioInputDirMask)) != ADI_COMMON_ACT_NO_ACTION) + { + /*Clear the error so that clean up functions execute*/ + retVal = adi_common_ErrorClear(&device->common); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Re-Acquire Shared GPIOs if setting of GPIO Input Dir is unsuccessful*/ + retVal = adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + 1, + THIS_FEATURE_ID, + &resourceAcqReleaseStatus); + + if (resourceAcqReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Unable to re-acquire GPIOs for Rx AGC Hybrid mode while attempting to exit the function due to GPIO dir set error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + for (i = 0, j=1; i < 4; i++, j = j*2) + { + + if ((rxChannelMask&j) != 0) + { + retVal = adi_adrv9025_SpiByteWrite(device, channel[i], hybridSelPin1); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return retVal; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_tx.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_tx.c new file mode 100644 index 0000000..69e1dda --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_tx.c @@ -0,0 +1,5189 @@ +/** +* \file adi_adrv9025_tx.c +* \brief Contains Tx features related function implementation defined in +* adi_adrv9025_tx.h +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "adi_adrv9025_arm.h" +#include "adi_adrv9025_tx.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_error.h" +#include "adi_adrv9025_gpio.h" +#include "adi_adrv9025.h" +#include "adi_adrv9025_cpu.h" +#include "../../private/include/adrv9025_bf_tx.h" +#include "../../private/include/adrv9025_init.h" +#include "../../private/include/adrv9025_tx.h" +#include "../../private/include/adrv9025_cpu.h" +#include "../../private/include/adrv9025_cpu_macros.h" +#include "../../private/include/adrv9025_reg_addr_macros.h" +#include "../../private/include/adrv9025_shared_resource_manager.h" +#include "../../private/include/adrv9025_bf_core.h" +#include "../../private/include/adrv9025_bf_txdac_mem_map.h" + +#ifdef _RELEASE_BUILD_ + #line __LINE__ "adi_adrv9025_tx.c" +#endif + +#define ADI_ADRV9025_NUM_GPIOS_IN_TX_ATTEN_CTRL_SPI2_PIN_FEATURE 1U + +int32_t adi_adrv9025_TxAttenCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxAttenCfg_t txAttenCfg[], + uint8_t attenCfgs) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int8_t i = 0; + int8_t j = 0; + /* uint16_t regData = 0;*/ + adi_adrv9025_TxChannels_e txChannel = ADI_ADRV9025_TXOFF; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + uint32_t channelLoop = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txAttenCfg); + + /* check configs is > 0 */ + if (attenCfgs == 0) + { + /* no valid configs */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + attenCfgs, + "Invalid number of configs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Loop through the number of configurations passed */ + for (i = 0; i < attenCfgs; i++) + { +#if ADI_ADRV9025_TX_RANGE_CHECK > 0 + recoveryAction = adrv9025_TxAttenCfgSetRangeCheck(device, + &txAttenCfg[i]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + txAttenCfg[i], + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /* Write configuration */ + channelLoop = txAttenCfg[i].txChannelMask; + for (j = 0; j < ADI_ADRV9025_MAX_TXCHANNELS; j++) + { + if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX1)) + { + txChannel = ADI_ADRV9025_TX1; + txChannelBaseAddr = ADRV9025_BF_TX_CH0; + channelLoop = channelLoop & ~ADI_ADRV9025_TX1; + device->devStateInfo.txAttenStepSize[0] = txAttenCfg[i].txAttenStepSize; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX2)) + { + txChannel = ADI_ADRV9025_TX2; + txChannelBaseAddr = ADRV9025_BF_TX_CH1; + channelLoop = channelLoop & ~ADI_ADRV9025_TX2; + device->devStateInfo.txAttenStepSize[1] = txAttenCfg[i].txAttenStepSize; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX3)) + { + txChannel = ADI_ADRV9025_TX3; + txChannelBaseAddr = ADRV9025_BF_TX_CH2; + channelLoop = channelLoop & ~ADI_ADRV9025_TX3; + device->devStateInfo.txAttenStepSize[2] = txAttenCfg[i].txAttenStepSize; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX4)) + { + txChannel = ADI_ADRV9025_TX4; + txChannelBaseAddr = ADRV9025_BF_TX_CH3; + channelLoop = channelLoop & ~ADI_ADRV9025_TX4; + device->devStateInfo.txAttenStepSize[3] = txAttenCfg[i].txAttenStepSize; + } + + /* error condition break loop and report error */ + else if (channelLoop == 0) + { + /* All channels are set up */ + break; + } + + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenPinCfg[i].txChannelMask, + "Error while accessing selected Tx channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Configure part */ + /* Attenuation step size */ + recoveryAction = adrv9025_TxTxAttenConfigBfSet(device, + txChannelBaseAddr, + (uint8_t)(txAttenCfg[i].txAttenStepSize)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txAttenCfg[i].txAttenStepSize, + "Error while setting Tx atten step size bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Attenuation mode */ + recoveryAction = adi_adrv9025_TxAttenModeSet(device, + (uint32_t)txChannel, + txAttenCfg[i].attenMode, + txAttenCfg[i].simultaneousUpdateCfg, + txAttenCfg[i].gpioModePinCfg); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txAttenCfg[i].attenMode, + "Error while setting Tx atten mode bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxAttenCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxAttenCfg_t* txAttenCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + adi_adrv9025_TxAttenMode_e txModeRead = ADI_ADRV9025_TXATTEN_SPI_MODE; + adi_adrv9025_TxDataIfUnlock_e txJesdData = ADI_ADRV9025_TXUNLOCK_TX_NOT_DISABLED; + adi_adrv9025_TxDataIfUnlock_e txRfPllData = ADI_ADRV9025_TXUNLOCK_TX_NOT_DISABLED; + adi_adrv9025_TxAttenStepSize_e txAttenStepRead = ADI_ADRV9025_TXATTEN_0P05_DB; + adi_adrv9025_TxAttenSimultUpdateCfg_t simultaneousUpdateCfg = {ADI_ADRV9025_GPIO_INVALID, ADI_ADRV9025_TXATTEN_SIMULTAN_UPDATE_DISABLED}; + adi_adrv9025_TxAttenPinCfg_t gpioModePinCfg = {0, 0, ADI_ADRV9025_GPIO_INVALID, ADI_ADRV9025_GPIO_INVALID}; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txAttenCfg); + + if ((txChannelBaseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + txChannel)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Read Configure part */ + /* Attenuation step size */ + recoveryAction = adrv9025_TxTxAttenConfigBfGet(device, + txChannelBaseAddr, + (uint8_t*)&txAttenStepRead); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txAttenCfg[].attenMode, + "Error while attempting to set Attenuation step"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* RFPLL unlock setting for Tx attanuation ramp down - Silicon B*/ + recoveryAction = adrv9025_TxTxDataRampDownOnPllUnlockBfGet(device, + txChannelBaseAddr, + (uint8_t*)&txRfPllData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read RfPll unlock settings mode - Silicon B"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* retrieve JESD unlock setting for Tx attanuation ramp down - Silicon B*/ + recoveryAction = adrv9025_TxTxDataRampDownOnJesdDfrmIrqBfGet(device, + txChannelBaseAddr, + (uint8_t*)&txJesdData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read Jesd unlock settings mode - Silicon B"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Retrieve attenuation mode */ + recoveryAction = adi_adrv9025_TxAttenModeGet(device, + txChannel, + &txModeRead, + &simultaneousUpdateCfg, + &gpioModePinCfg); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to get attenuation mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + txAttenCfg->txChannelMask = txChannel; + txAttenCfg->attenMode = txModeRead; + txAttenCfg->disTxDataIfPllUnlock = txRfPllData; + txAttenCfg->rampJesdDfrm = txJesdData; + txAttenCfg->txAttenStepSize = txAttenStepRead; + txAttenCfg->simultaneousUpdateCfg.gpioUpdatePin = simultaneousUpdateCfg.gpioUpdatePin; + txAttenCfg->simultaneousUpdateCfg.simultaneousUpdate = simultaneousUpdateCfg.simultaneousUpdate; + txAttenCfg->gpioModePinCfg.txChannelMask = gpioModePinCfg.txChannelMask; + txAttenCfg->gpioModePinCfg.stepSize = gpioModePinCfg.stepSize; + txAttenCfg->gpioModePinCfg.txAttenIncPin = gpioModePinCfg.txAttenIncPin; + txAttenCfg->gpioModePinCfg.txAttenDecPin = gpioModePinCfg.txAttenDecPin; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxAttenModeSet(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + adi_adrv9025_TxAttenMode_e txAttenMode, + adi_adrv9025_TxAttenSimultUpdateCfg_t simultaneousUpdateCfg, + adi_adrv9025_TxAttenPinCfg_t gpioModePinCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + uint8_t k = 0; + uint8_t spi2Enable = 0; + uint8_t currentTxAttenUpdateGpioEn = 0; + uint8_t gpioSimultaneousUpdateEn = 0; + uint8_t spiSimultaneousUpdateEn = 0; + uint8_t releaseCurrentSimultUpdGpioPin = 0; + uint8_t acquireNewSimultUpdGpioPin = 0; + uint8_t releaseCurrentGpioModeIncDecPins = 0; + uint8_t acquireNewGpioModeIncDecPins = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + +#if ADI_ADRV9025_TX_RANGE_CHECK > 0 + recoveryAction = adrv9025_TxAttenModeSetRangeCheck(device, + txAttenMode, + simultaneousUpdateCfg, + gpioModePinCfg); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + txAttenModeCfg, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + for (k = 0; k < ADI_ADRV9025_MAX_TXCHANNELS; k++) + { + if (ADRV9025_BF_EQUAL(txChannelMask, + ((uint32_t)1 << (uint32_t)k))) + { + if ((txChannelBaseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + ((uint32_t)1 << (uint32_t)k))) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Read Spi2 status */ + recoveryAction = adi_adrv9025_Spi2CfgGet(device, + &spi2Enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + spi2Enable, + "Error while reading Spi2 enabled status"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Tx Attenuation GPIO Update Enable Status */ + recoveryAction = adrv9025_TxTxAttenUpdGpioEnBfGet(device, + txChannelBaseAddr, + ¤tTxAttenUpdateGpioEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read Tx attenuation update enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* If GPIO update mode is being used prior to this function call, we need to release the GPIO pin */ + if (currentTxAttenUpdateGpioEn == ADI_TRUE) + { + releaseCurrentSimultUpdGpioPin = 1; + } + + /* If Tx attenuation mode is GPIO, release current inc/dec pins */ + if (device->devStateInfo.txAttenMode[k] == ADI_ADRV9025_TXATTEN_GPIO_MODE) + { + releaseCurrentGpioModeIncDecPins = 1; + } + + /* New Attenuation mode to be set */ + if (txAttenMode == ADI_ADRV9025_TXATTEN_SPI2_MODE) + { + /* Report error if Spi2 is not enabled but user wants to use Spi2 for Tx attenuation control */ + if (spi2Enable == ADI_FALSE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + spi2Enable, + "Spi2 should be enabled to set Tx Attenation control mode to Spi2"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* To set Spi2 as Tx attenuation mode, tx_atten_mode should be set to 1 and simultaneous update should be disabled */ + recoveryAction = adrv9025_TxTxAttenModeBfSet(device, + txChannelBaseAddr, + 0x01); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + 0x01, + "Error while attempting to set control mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + spiSimultaneousUpdateEn = 0; + gpioSimultaneousUpdateEn = 0; + } + else + { + if (txAttenMode == ADI_ADRV9025_TXATTEN_SPI_MODE) + { + /* Report error if Spi2 is enabled but user wants to use Spi for Tx attenuation control */ + if (spi2Enable == ADI_TRUE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + spi2Enable, + "Spi2 shouldn't be enabled to set Tx Attenation control mode to Spi"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (simultaneousUpdateCfg.simultaneousUpdate == ADI_ADRV9025_TXATTEN_SIMULTAN_UPDATE_SPI) + { + gpioSimultaneousUpdateEn = 0; + spiSimultaneousUpdateEn = 1; + } + else if (simultaneousUpdateCfg.simultaneousUpdate == ADI_ADRV9025_TXATTEN_SIMULTAN_UPDATE_GPIO) + { + gpioSimultaneousUpdateEn = 1; + spiSimultaneousUpdateEn = 0; + acquireNewSimultUpdGpioPin = 1; + } + } + + else if (txAttenMode == ADI_ADRV9025_TXATTEN_GPIO_MODE) + { + /* If new Tx attenuation mode will be GPIO mode, acquire new inc/dec pins */ + acquireNewGpioModeIncDecPins = 1; + } + + recoveryAction = adrv9025_TxTxAttenModeBfSet(device, + txChannelBaseAddr, + txAttenMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txAttenMode, + "Error while attempting to set control mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if (releaseCurrentGpioModeIncDecPins == 1) + { + /* First release inc/dec pins */ + + /* Release/Acquire Tx attenuation inc/dec GPIO pins */ + recoveryAction = adrv9025_TxAttenPinCtrlCfgSet(device, + txChannelBaseAddr, + gpioModePinCfg, + releaseCurrentGpioModeIncDecPins, + acquireNewGpioModeIncDecPins); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to set GPIO configuration for Tx attenuation control"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Release/Acquire simultaneous update GPIO pin */ + recoveryAction = adrv9025_TxAttenUpdateGpioPinCtrlCfgSet(device, + txChannelBaseAddr, + simultaneousUpdateCfg.gpioUpdatePin, + releaseCurrentSimultUpdGpioPin, + acquireNewSimultUpdGpioPin); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while configuring GPIO for Tx attenuation simultaneous update"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* First release simultaneous update pins */ + + /* Release/Acquire simultaneous update GPIO pin */ + recoveryAction = adrv9025_TxAttenUpdateGpioPinCtrlCfgSet(device, + txChannelBaseAddr, + simultaneousUpdateCfg.gpioUpdatePin, + releaseCurrentSimultUpdGpioPin, + acquireNewSimultUpdGpioPin); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while configuring GPIO for Tx attenuation simultaneous update"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Release/Acquire Tx attenuation inc/dec GPIO pins */ + recoveryAction = adrv9025_TxAttenPinCtrlCfgSet(device, + txChannelBaseAddr, + gpioModePinCfg, + releaseCurrentGpioModeIncDecPins, + acquireNewGpioModeIncDecPins); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to set GPIO configuration for Tx attenuation control"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Set Tx attenuation Spi simultaneous update enable bit */ + recoveryAction = adrv9025_CoreTxAttenUpdCoreSpiEnBfSet(device, + ADRV9025_BF_CORE, + spiSimultaneousUpdateEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to set Tx attenuation Spi update enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set Tx attenuation Gpio simultaneous update enable bit */ + recoveryAction = adrv9025_TxTxAttenUpdGpioEnBfSet(device, + txChannelBaseAddr, + gpioSimultaneousUpdateEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to set Tx attenuation GPIO update enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Update state device info*/ + device->devStateInfo.txAttenMode[k] = txAttenMode; + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxAttenModeGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxAttenMode_e* txAttenMode, + adi_adrv9025_TxAttenSimultUpdateCfg_t* simultaneousUpdateCfg, + adi_adrv9025_TxAttenPinCfg_t* gpioModePinCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + uint8_t spiSimultaneousUpdateEn = 0; + uint8_t gpioSimultaneousUpdateEn = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if ((txChannelBaseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + txChannel)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + switch (txChannel) + { + case ADI_ADRV9025_TX1: + *txAttenMode = device->devStateInfo.txAttenMode[0]; + break; + case ADI_ADRV9025_TX2: + *txAttenMode = device->devStateInfo.txAttenMode[1]; + break; + case ADI_ADRV9025_TX3: + *txAttenMode = device->devStateInfo.txAttenMode[2]; + break; + case ADI_ADRV9025_TX4: + *txAttenMode = device->devStateInfo.txAttenMode[3]; + break; + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + recoveryAction = adi_adrv9025_TxAttenPinCtrlCfgGet(device, + txChannel, + gpioModePinCfg); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read Tx attenuation GPIO mode pin configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_adrv9025_TxAttenUpdateGpioPinCtrlCfgGet(device, + txChannel, + &simultaneousUpdateCfg->gpioUpdatePin); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read Tx attenuation GPIO update pin"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Tx attenuation Spi simultaneous update enable bit */ + recoveryAction = adrv9025_CoreTxAttenUpdCoreSpiEnBfGet(device, + ADRV9025_BF_CORE, + &spiSimultaneousUpdateEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to get Tx attenuation Spi update enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Tx attenuation Gpio simultaneous update enable bit */ + recoveryAction = adrv9025_TxTxAttenUpdGpioEnBfGet(device, + txChannelBaseAddr, + &gpioSimultaneousUpdateEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to get Tx attenuation GPIO update enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((gpioSimultaneousUpdateEn == ADI_TRUE) && (spiSimultaneousUpdateEn == ADI_FALSE)) + { + simultaneousUpdateCfg->simultaneousUpdate = ADI_ADRV9025_TXATTEN_SIMULTAN_UPDATE_GPIO; + } + else if ((gpioSimultaneousUpdateEn == ADI_FALSE) && (spiSimultaneousUpdateEn == ADI_TRUE)) + { + simultaneousUpdateCfg->simultaneousUpdate = ADI_ADRV9025_TXATTEN_SIMULTAN_UPDATE_SPI; + } + else if ((gpioSimultaneousUpdateEn == ADI_FALSE) && (spiSimultaneousUpdateEn == ADI_FALSE)) + { + simultaneousUpdateCfg->simultaneousUpdate = ADI_ADRV9025_TXATTEN_SIMULTAN_UPDATE_DISABLED; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid Simultaneous update mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxAttenSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxAtten_t txAttenuation[], + uint8_t numTxAttenConfigs) +{ + static const uint8_t MINIMUM_NUM_TX_ATTEN_CONFIGS = 1; + static const uint8_t MAXIMUM_NUM_TX_ATTEN_CONFIGS = 4; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int8_t i = 0; + int8_t j = 0; + uint32_t channelLoop = 0; + uint16_t regData = 0; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txAttenuation); + + /* Check that numTxAttenConfigs is in valid range - ERROR */ + if (numTxAttenConfigs < MINIMUM_NUM_TX_ATTEN_CONFIGS) + { + /* invalid number of configs */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + numTxAttenConfigs, + "Invalid number of Tx Attenuation configs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check that numTxAttenConfigs is in valid range - WARNING */ + if (numTxAttenConfigs > MAXIMUM_NUM_TX_ATTEN_CONFIGS) + { + /* too many configs */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_WARN_CHECK_PARAM, + numTxAttenConfigs, + "WARNING: Number of Tx Attenuation configurations is larger than maximum (4) expected. The last configuration included for any channel will be applied to the device."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Loop through the number of configurations and check attenuation mode */ + for (i = 0; i < numTxAttenConfigs; i++) + { + if (txAttenuation[i].txAttenuation_mdB > ADRV9025_TX_ATTEN_VALUE_MAX_MDB) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenuation[i].txAttenuation_mdB, + "Invalid txAttenuation_mdB value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* Check for a valid txChannel and check attenuation mode */ + channelLoop = txAttenuation[i].txChannelMask; + for (j = 0; j < ADI_ADRV9025_MAX_TXCHANNELS; j++) + { + if (ADRV9025_BF_EQUAL(channelLoop, + ((uint32_t)0x1 << j))) + { + if (device->devStateInfo.txAttenMode[j] != ADI_ADRV9025_TXATTEN_SPI_MODE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_ADRV9025_ERR_INV_TX_ATTEN_MODE, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->devStateInfo.txAttenMode[j], + "Invalid Tx attenuation control mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + } + + /* Loop through the number of configurations passed */ + for (i = 0; i < numTxAttenConfigs; i++) + { + /* Write configuration */ + /* Check for a valid txChannel and perform the Bitfield access*/ + channelLoop = txAttenuation[i].txChannelMask; + for (j = 0; j < ADI_ADRV9025_MAX_TXCHANNELS; j++) + { + if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX1)) + { + txChannelBaseAddr = ADRV9025_BF_TX_CH0; + channelLoop = channelLoop & ~ADI_ADRV9025_TX1; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX2)) + { + txChannelBaseAddr = ADRV9025_BF_TX_CH1; + channelLoop = channelLoop & ~ADI_ADRV9025_TX2; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX3)) + { + txChannelBaseAddr = ADRV9025_BF_TX_CH2; + channelLoop = channelLoop & ~ADI_ADRV9025_TX3; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX4)) + { + txChannelBaseAddr = ADRV9025_BF_TX_CH3; + channelLoop = channelLoop & ~ADI_ADRV9025_TX4; + } + /* error condition break loop and report error */ + else if (channelLoop == 0) + { + /* All channels setup */ + break; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenuation[i].txChannelMask, + "Error while accessing selected Tx channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* set step size depending on tx->txAttenStepSize */ + switch (device->devStateInfo.txAttenStepSize[j]) + { + case ADI_ADRV9025_TXATTEN_0P05_DB: + regData = (txAttenuation[i].txAttenuation_mdB / 50); + break; + case ADI_ADRV9025_TXATTEN_0P1_DB: + regData = (txAttenuation[i].txAttenuation_mdB / 100); + break; + case ADI_ADRV9025_TXATTEN_0P2_DB: + regData = (txAttenuation[i].txAttenuation_mdB / 200); + break; + case ADI_ADRV9025_TXATTEN_0P4_DB: + regData = (txAttenuation[i].txAttenuation_mdB / 400); + break; + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->devStateInfo.txAttenStepSize, + "Invalid Tx step size in structure"); + ADI_ERROR_RETURN(recoveryAction); + } + } + recoveryAction = adrv9025_TxTxAttenuationBfSet(device, + txChannelBaseAddr, + regData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + txAttenuation->txAttenuation_mdB, + "Invalid Tx attenuation setting in structure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxAttenGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxAtten_t* txAttenuation) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxChanAddr_e txBfChannel = ADRV9025_BF_TX_CH0; + uint16_t txAttenReadBack = 0; + uint16_t attenStepSizeDiv = 50; + adi_adrv9025_TxAttenStepSize_e attenStepSize = ADI_ADRV9025_TXATTEN_0P05_DB; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txAttenuation); + + if ((txBfChannel = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + txChannel)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_TxTxAttenuationBfGet(device, + txBfChannel, + &txAttenReadBack); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Failure to Read Attenuation"); + ADI_ERROR_RETURN(device->common.error.newAction); + + switch (txChannel) + { + case ADI_ADRV9025_TX1: + attenStepSize = device->devStateInfo.txAttenStepSize[0]; + break; + case ADI_ADRV9025_TX2: + attenStepSize = device->devStateInfo.txAttenStepSize[1]; + break; + case ADI_ADRV9025_TX3: + attenStepSize = device->devStateInfo.txAttenStepSize[2]; + break; + case ADI_ADRV9025_TX4: + attenStepSize = device->devStateInfo.txAttenStepSize[3]; + break; + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + switch (attenStepSize) + { + case ADI_ADRV9025_TXATTEN_0P05_DB: + attenStepSizeDiv = 50; + break; + case ADI_ADRV9025_TXATTEN_0P1_DB: + attenStepSizeDiv = 100; + break; + case ADI_ADRV9025_TXATTEN_0P2_DB: + attenStepSizeDiv = 200; + break; + case ADI_ADRV9025_TXATTEN_0P4_DB: + attenStepSizeDiv = 400; + break; + default: + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + attenStepSizeDiv, + "Invalid Tx step size in structure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Readback word always reads back with 0.05dB resolution */ + txAttenuation->txAttenuation_mdB = (txAttenReadBack * attenStepSizeDiv); + txAttenuation->txChannelMask = txChannel; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_DacFullScaleSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_DacFullScale_e dacFullScale) +{ + static const uint8_t DAC_FSC_TUNE_VAL = 0x10; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + adrv9025_BfTxdacMemMapChanAddr_e txDacChannelBaseAddr = ADRV9025_BF_ALL_TXDAC; + adrv9025_BfTxdacMemMapTxdacFscBoostI_e boostDacPowerI = ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_FSC4MA; + adrv9025_BfTxdacMemMapTxdacFscBoostQ_e boostDacPowerQ = ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_FSC4MA; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that if init cals has run */ + if (ADRV9025_BF_EQUAL(device->devStateInfo.devState, + ADI_ADRV9025_STATE_INITCALS_RUN)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + devState, + "Init cals has already run. Cannot change Tx Dac Full scale settings anymore"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that dacFullScale is in range */ + if (dacFullScale > ADI_ADRV9025_TX_DACFS_3DB) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + dacFullScale, + "Dac Full scale selection is out of range, Valid values are 0dB and 3dB"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txDacChannelBaseAddr = (adrv9025_BfTxdacMemMapChanAddr_e)adrv9025_TxDacAddrDecode(device, + (uint32_t)txChannel)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_TxdacMemMapTxdacFscTuneIBfSet(device, + txDacChannelBaseAddr, + DAC_FSC_TUNE_VAL); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + DAC_FSC_TUNE_VAL, + "Error while setting FSC Tune IDAC full scale current bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxdacMemMapTxdacFscTuneQBfSet(device, + txDacChannelBaseAddr, + DAC_FSC_TUNE_VAL); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + DAC_FSC_TUNE_VAL, + "Error while setting FSC Tune QDAC full scale current bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (dacFullScale == ADI_ADRV9025_TX_DACFS_3DB) + { + boostDacPowerI = ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_FSC5P6MA; + boostDacPowerQ = ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_FSC5P6MA; + } + else + { + boostDacPowerI = ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_FSC4MA; + boostDacPowerQ = ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_QDAC_FSC4MA; + } + + recoveryAction = adrv9025_TxdacMemMapTxdacFscBoostIBfSet(device, + txDacChannelBaseAddr, + boostDacPowerI); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + boostDacPowerI, + "Error while setting FSC Boost IDAC output power bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxdacMemMapTxdacFscBoostQBfSet(device, + txDacChannelBaseAddr, + boostDacPowerQ); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + boostDacPowerQ, + "Error while setting FSC Boost QDAC output power bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + return device->common.error.newAction; +} + +int32_t adi_adrv9025_DacFullScaleGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_DacFullScale_e* dacFullScale) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxdacMemMapTxdacFscBoostI_e txDacBoostRead = ADRV9025_BF_TXDAC_MEM_MAP_TXDAC_IDAC_FSC4MA; + adrv9025_BfTxdacMemMapChanAddr_e txDacChannelBaseAddr = ADRV9025_BF_ALL_TXDAC; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + dacFullScale); + + if ((txDacChannelBaseAddr = (adrv9025_BfTxdacMemMapChanAddr_e)adrv9025_TxDacAddrDecode(device, + txChannel)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* DAC full scale setting */ + recoveryAction = adrv9025_TxdacMemMapTxdacFscBoostIBfGet(device, + txDacChannelBaseAddr, + &txDacBoostRead); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to set Dac fulls scale"); + ADI_ERROR_RETURN(device->common.error.newAction); + + *dacFullScale = (adi_adrv9025_DacFullScale_e)txDacBoostRead; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxTestToneSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxTestToneCfg_t txNcoTestToneCfg[], + uint8_t toneCfgs) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int8_t i = 0; + int8_t j = 0; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + uint32_t channelLoop = 0; + uint32_t tuneWord = 0; + int64_t txSampleRateDiv2_Hz = 245760000; // TODO: get profiles IQ rate from device data structure + + ADI_NULL_DEVICE_PTR_RETURN(device); + + // ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + ADI_FUNCTION_ENTRY_VARIABLE_LOG(&device->common, + ADI_COMMON_LOG_API, + "%s(0x%04X, 0x%04X, 0x%02X)", + *device, + txNcoTestToneCfg, + toneCfgs); + + ADI_NULL_PTR_RETURN(&device->common, + txNcoTestToneCfg); + + /* check configs is > 0 and <= 4*/ + if (toneCfgs == 0 || toneCfgs > 4) + { + /* no valid configs */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + attenCfgs, + "Invalid number of configs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Loop through the number of configurations passed */ + for (i = 0; i < toneCfgs; i++) + { +#if ADI_ADRV9025_TX_RANGE_CHECK > 0 + recoveryAction = adrv9025_TxTestToneCfgSetRangeCheck(device, + &txNcoTestToneCfg[i]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + txAttenCfg[i], + "Invalid configuration found"); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /* Write configuration */ + channelLoop = txNcoTestToneCfg[i].txChannelMask; + for (j = 0; j < ADI_ADRV9025_MAX_TXCHANNELS; j++) + { + if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX1)) + { + txChannelBaseAddr = ADRV9025_BF_TX_CH0; + channelLoop = channelLoop & ~ADI_ADRV9025_TX1; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX2)) + { + txChannelBaseAddr = ADRV9025_BF_TX_CH1; + channelLoop = channelLoop & ~ADI_ADRV9025_TX2; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX3)) + { + txChannelBaseAddr = ADRV9025_BF_TX_CH2; + channelLoop = channelLoop & ~ADI_ADRV9025_TX3; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX4)) + { + txChannelBaseAddr = ADRV9025_BF_TX_CH3; + channelLoop = channelLoop & ~ADI_ADRV9025_TX4; + } + /* error condition break loop and report error */ + else if (channelLoop == 0) + { + /* All channels setup */ + break; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txNcoTestToneCfg[i].txChannelMask, + "Error while accessing selected Tx channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + txSampleRateDiv2_Hz = (((int64_t)device->devStateInfo.txInputRate_kHz[j]) * 1000) >> 1; + + if ((txNcoTestToneCfg[i].txToneFreq_Hz > txSampleRateDiv2_Hz) || + (txNcoTestToneCfg[i].txToneFreq_Hz < -(txSampleRateDiv2_Hz))) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txNcoTestToneCfg[i].txToneFreq_Hz, + "Tx Test Tone Frequency is too large for the Tx Profile's sample rate"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + tuneWord = (uint32_t)(((((int64_t)((0 - txNcoTestToneCfg[i].txToneFreq_Hz)) << 32) / txSampleRateDiv2_Hz) + 1) >> 1); + /* +1 >>1 is round to nearest */ + + /* Configure part */ + /* Disable Tx NCO complex multiplier */ + recoveryAction = adrv9025_TxTxDpNcoEnableBfSet(device, + txChannelBaseAddr, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txNcoTestToneCfg[i].enable, + "Error while attempting to disable the Tx Nco complex multipler"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxTxNcoGainBfSet(device, + txChannelBaseAddr, + txNcoTestToneCfg[i].txToneGain); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txNcoTestToneCfg[i].txToneGain, + "Error while attempting to set the Nco tone gain"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxTxDpNcoFtwBfSet(device, + txChannelBaseAddr, + tuneWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txNcoTestToneCfg[i].txToneFreq_Hz, + "Error while attempting to set the Nco tone frequency"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxTxDpNcoFtwUpdateBfSet(device, + txChannelBaseAddr, + ADI_ON); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txNcoTestToneCfg[i].txToneFreq_Hz, + "Error while attempting to update the Nco tone frequency"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxNcoTestEnableBfSet(device, + txChannelBaseAddr, + (txNcoTestToneCfg[i].enable > 0) ? 1 : 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txNcoTestToneCfg[i].enable, + "Error while attempting to set the Nco test tone enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxTestToneGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxTestToneCfg_t* txNcoTestToneCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + uint8_t enable = 0; + uint8_t txToneGain = 0; + uint32_t tuneWord = 0; + int64_t txSampleRateDiv2_Hz = 245760000; // TODO: get profiles IQ rate from device data structure + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txNcoTestToneCfg); + + if ((txChannelBaseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + txChannel)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Configure part */ + recoveryAction = adrv9025_TxNcoTestEnableBfGet(device, + txChannelBaseAddr, + &enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to get the Nco test tone enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxTxNcoGainBfGet(device, + txChannelBaseAddr, + &txToneGain); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to get the Nco tone gain"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxTxDpNcoFtwBfGet(device, + txChannelBaseAddr, + &tuneWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to get the Nco tone frequency"); + ADI_ERROR_RETURN(device->common.error.newAction); + + txSampleRateDiv2_Hz = (((int64_t)device->devStateInfo.txInputRate_kHz[0]) * 1000) >> 1; + + txNcoTestToneCfg->txChannelMask = txChannel; + txNcoTestToneCfg->enable = enable; + txNcoTestToneCfg->txToneGain = (adi_adrv9025_TxNcoGain_e)txToneGain; + txNcoTestToneCfg->txToneFreq_Hz = (int32_t)(((int64_t)(0 - (((((tuneWord | 0xFFFFFFFF00000000) << 1) - 1) * txSampleRateDiv2_Hz) >> 32)))); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxAttenPinCtrlCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxAttenPinCfg_t txAttenPinCfg[], + uint8_t numTxAttenPinConfigs) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t i = 0; + uint8_t j = 0; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + uint32_t channelLoop = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txAttenPinCfg); + + /* check configs is > 0 */ + if (numTxAttenPinConfigs == 0) + { + /* no valid configs */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + numTxAttenPinConfigs, + "Invalid number of configs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Loop through the number of configurations passed */ + for (i = 0; i < numTxAttenPinConfigs; i++) + { + channelLoop = txAttenPinCfg[i].txChannelMask; + + for (j = 0; j < ADI_ADRV9025_MAX_TXCHANNELS; j++) + { + if (ADRV9025_BF_EQUAL(channelLoop, ((uint32_t)1 << (uint32_t)j))) + { + if (device->devStateInfo.txAttenMode[j] == ADI_ADRV9025_TXATTEN_GPIO_MODE) + { + txChannelBaseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, ((uint32_t)1 << (uint32_t)j)); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Device is already at GPIO mode, so release old pins and acquire new pins */ + recoveryAction = adrv9025_TxAttenPinCtrlCfgSet(device, + txChannelBaseAddr, + txAttenPinCfg[i], + ADI_TRUE, + ADI_TRUE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + resourceAcquisitionStatus, + "Error while attempting to acquire GPIO shared resouce for GPIO Attenuation ctrl Increment/Decrement Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* GPIO Tx attenuation control pins can only be changed when Tx attenuation mode is GPIO */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->devStateInfo.txAttenMode[j], + "GPIO Tx attenuation control pins can only be changed when Tx attenuation mode is GPIO"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxAttenPinCtrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxAttenPinCfg_t* txAttenPinCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t stepRead = 0; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + uint8_t currentTxAttenCtrlIncPin = 0; + uint8_t currentTxAttenCtrlDecPin = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txAttenPinCfg); + + switch (txChannel) + { + case ADI_ADRV9025_TX1: + txChannelBaseAddr = ADRV9025_BF_TX_CH0; + break; + case ADI_ADRV9025_TX2: + txChannelBaseAddr = ADRV9025_BF_TX_CH1; + break; + case ADI_ADRV9025_TX3: + txChannelBaseAddr = ADRV9025_BF_TX_CH2; + break; + case ADI_ADRV9025_TX4: + txChannelBaseAddr = ADRV9025_BF_TX_CH3; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenPinCfg[i].txChannelMask, + "Error while accessing selected Tx channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Read Tx Attenuation Decrement GPIO select */ + recoveryAction = adrv9025_TxTpcDecrAttenGpioSelectBfGet(device, + txChannelBaseAddr, + ¤tTxAttenCtrlDecPin); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read Attenuation decrement GPIO select register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Read Rx Attenuation Increment GPIO select*/ + recoveryAction = adrv9025_TxTpcIncrAttenGpioSelectBfGet(device, + txChannelBaseAddr, + ¤tTxAttenCtrlIncPin); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read Attenuation increment GPIO select register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get GPIO Attenuation step size */ + recoveryAction = adrv9025_TxTxIncrDecrWordBfGet(device, + txChannelBaseAddr, + &stepRead); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to get GPIO Attenaution step size"); + ADI_ERROR_RETURN(device->common.error.newAction); + + txAttenPinCfg->stepSize = stepRead; + txAttenPinCfg->txAttenDecPin = (adi_adrv9025_GpioPinSel_e)currentTxAttenCtrlDecPin; + txAttenPinCfg->txAttenIncPin = (adi_adrv9025_GpioPinSel_e)currentTxAttenCtrlIncPin; + txAttenPinCfg->txChannelMask = txChannel; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxAttenUpdateGpioPinCtrlCfgSet(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + adi_adrv9025_GpioPinSel_e gpioSelection) +{ + static const uint32_t ALL_TX_CHANNELS = (uint32_t)(ADI_ADRV9025_TXALL); + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + uint8_t i = 0; + uint8_t currentTxAttenUpdateEn = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if ((txChannelMask == 0) || ((txChannelMask & (~ALL_TX_CHANNELS)) != 0)) + { + /* Tx channel selection is not valid */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannelMask, + "Invalid Tx channel selection, any combination of Tx1/2/3/4 channels are valid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_ADRV9025_MAX_TXCHANNELS; i++) + { + if (ADRV9025_BF_EQUAL(txChannelMask, + ((uint32_t)1 << (uint32_t)i))) + { + txChannelBaseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + ((uint32_t)1 << (uint32_t)i)); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Tx Attenuation GPIO Update Enable Status */ + recoveryAction = adrv9025_TxTxAttenUpdGpioEnBfGet(device, + txChannelBaseAddr, + ¤tTxAttenUpdateEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read Tx attenuation update enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (currentTxAttenUpdateEn == ADI_TRUE) + { + /* We're actively using Tx attenuation with GPIO feature, release the current pin and acquire the new pin */ + recoveryAction = adrv9025_TxAttenUpdateGpioPinCtrlCfgSet(device, + txChannelBaseAddr, + gpioSelection, + ADI_TRUE, + ADI_TRUE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* GPIO Tx attenuation simultaneous update is not enabled for selected Tx channel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + currentTxAttenUpdateEn, + "GPIO simultaneous update is not enabled for selected Tx channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxAttenUpdateGpioPinCtrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannelSelect, + adi_adrv9025_GpioPinSel_e* gpioSelection) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + uint8_t fieldVal = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + gpioSelection); + + if ((txChannelSelect != ADI_ADRV9025_TX1) && (txChannelSelect != ADI_ADRV9025_TX2) && + (txChannelSelect != ADI_ADRV9025_TX3) && (txChannelSelect != ADI_ADRV9025_TX4)) + { + /* Tx channel selection is not valid */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannelSelect, + "Invalid Tx channel selection, Tx1/2/3/4 channels are valid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + txChannelBaseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + (uint32_t)txChannelSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Get Tx attenuation Update GPIO select */ + recoveryAction = adrv9025_TxTxAttenUpdGpioSelectBfGet(device, + txChannelBaseAddr, + &fieldVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + fieldVal, + "Error while attempting to read GPIO Tx attenuation update pin"); + ADI_ERROR_RETURN(device->common.error.newAction); + + *gpioSelection = (adi_adrv9025_GpioPinSel_e)fieldVal; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxAttenUpdate(adi_adrv9025_Device_t* device, + uint32_t txChannelMask) +{ + static const uint32_t ALL_TX_CHANNELS = (uint32_t)ADI_ADRV9025_TX1 | (uint32_t)ADI_ADRV9025_TX2 | + (uint32_t)ADI_ADRV9025_TX3 | (uint32_t)ADI_ADRV9025_TX4; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t i = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if ((txChannelMask == 0) || ((txChannelMask & (~ALL_TX_CHANNELS)) != 0)) + { + /* Tx channel selection is not valid */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannelSelect, + "Invalid Tx channel selection, any combination of Tx1/2/3/4 channels are valid"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_ADRV9025_MAX_TXCHANNELS; i++) + { + if (ADRV9025_BF_EQUAL(txChannelMask, + ((uint32_t)1 << (uint32_t)i))) + { + if (device->devStateInfo.txAttenMode[i] != ADI_ADRV9025_TXATTEN_SPI_MODE) + { + /* Selected Tx channel is not at SPI mode */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenMode, + "Selected Tx channel for attenuation update is not working at SPI mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + /* First clear the field, it's not autoclear */ + recoveryAction = adrv9025_CoreTxAttenUpdCoreSpiBfSet(device, + ADRV9025_BF_CORE, + 0x00); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + 0x00, + "Error while attempting to clear Tx attenuation update spi register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write Tx attenuation update register to trigger Tx attenuation update*/ + recoveryAction = adrv9025_CoreTxAttenUpdCoreSpiBfSet(device, + ADRV9025_BF_CORE, + (uint8_t)txChannelMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + 0x00, + "Error while attempting to write Tx attenuation update spi register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxFirRead(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + int8_t* gain_dB, + uint8_t* numFirCoefs, + int16_t coefs[], + uint8_t arraySize) +{ + uint8_t i = 0; + uint8_t j = 0; + uint8_t numTapsReg = 0; + uint8_t nTapMul = 0; + uint8_t filterGain = 0; + uint8_t pfirCoeffCtl = 0; + uint16_t baseaddr = 0; + uint8_t byteLo = 0; + uint8_t byteHi = 0; + uint8_t filterConfig = 0; + static const uint8_t autoInc = ADI_ADRV9025_PFIR_COEFF_AUTO_INCR; + static const uint8_t TXFIR_MULTAPS = 20; + static const uint8_t TXFIR_MAXTAPS = 80; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + coefs); + ADI_NULL_PTR_RETURN(&device->common, + gain_dB); + ADI_NULL_PTR_RETURN(&device->common, + numFirCoefs); + + ADRV9025_BUGINFO(__FUNCTION__); + + if (adrv9025_TxAddrDecode(device, + txChannel) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (arraySize == 0 || arraySize > TXFIR_MAXTAPS) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + arraySize, + "Invalid arraySize. Number of coefficients should be between 1 and 80."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + nTapMul = TXFIR_MULTAPS; + + pfirCoeffCtl |= ADRV9025_PFIR_COEFF_PROG_CLK_EN; + if (autoInc != 0) + { + pfirCoeffCtl |= ADRV9025_PFIR_COEFF_AUTO_INCR; + } + + baseaddr = adrv9025_TxAddrDecode(device, + txChannel); + ADI_ERROR_RETURN(device->common.error.newAction); + + filterConfig = 0; + ADRV9025_SPIREADBYTE("TX_FILTER_CONFIG", + baseaddr + ADRV9025_ADDR_TX_FILTER_CONFIG_OFFSET, + &filterConfig); + + filterGain = ADRV9025_BF_DECODE(filterConfig, + ADRV9025_TX_PFIR_GAIN_MASK, + ADRV9025_TX_PFIR_GAIN_SHIFT); + numTapsReg = ADRV9025_BF_DECODE(filterConfig, + ADRV9025_TX_PFIR_TAPS_MASK, + ADRV9025_TX_PFIR_TAPS_SHIFT); + *numFirCoefs = (numTapsReg + 1) * nTapMul; + + /* Set filter gain to be used */ + switch (filterGain) + { + case 0: + *gain_dB = ADRV9025_FIR_GAIN_NEG12_DB; + break; + case 1: + *gain_dB = ADRV9025_FIR_GAIN_NEG6_DB; + break; + case 2: + *gain_dB = ADRV9025_FIR_GAIN_0_DB; + break; + case 3: + default: + *gain_dB = ADRV9025_FIR_GAIN_POS6_DB; + break; + } + + ADRV9025_SPIWRITEBYTE("TX_PFIR_COEFF_CTL", + (baseaddr + ADRV9025_ADDR_TX_PFIR_COEFF_CTL_OFFSET), + pfirCoeffCtl); + + //pfir_coeff_addr + j = 0; + ADRV9025_SPIWRITEBYTE("TX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_TX_PFIR_COEFF_ADDR_OFFSET), + j); + + /* Read up to arraySize */ + if (arraySize > *numFirCoefs) + { + arraySize = *numFirCoefs; + } + + for (i = 0; i < arraySize; i++) + { + byteLo = 0; + byteHi = 0; + ADRV9025_SPIREADBYTE("TX_PFIR_COEFF_DATA_LSB", + (baseaddr + ADRV9025_ADDR_TX_PFIR_COEFF_DATA_OFFSET), + &byteLo); + if (autoInc == 0) + { + j++; + ADRV9025_SPIWRITEBYTE("TX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_TX_PFIR_COEFF_ADDR_OFFSET), + j); + } + + ADRV9025_SPIREADBYTE("TX_PFIR_COEFF_DATA_MSB", + (baseaddr + ADRV9025_ADDR_TX_PFIR_COEFF_DATA_OFFSET), + &byteHi); + coefs[i] = (int16_t)((((uint16_t)byteHi) << 8) | byteLo); + + if (autoInc == 0) + { + j++; + ADRV9025_SPIWRITEBYTE("TX_PFIR_COEFF_ADDR", + (baseaddr + ADRV9025_ADDR_TX_PFIR_COEFF_ADDR_OFFSET), + j); + } + } + + /* disable pfir_coeff_prog_clk_en */ + /* disable pfir_coeff_wr_enable */ + pfirCoeffCtl = 0; + ADRV9025_SPIWRITEBYTE("TX_PFIR_COEFF_CTL", + (baseaddr + ADRV9025_ADDR_TX_PFIR_COEFF_CTL_OFFSET), + pfirCoeffCtl); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TxFirWrite(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + int8_t gain_dB, + uint8_t numFirCoefs, + int16_t coefs[], + uint8_t arraySize) +{ + uint8_t j = 0; + uint32_t maskBit = 0; + uint32_t txFirLookup[ADI_ADRV9025_MAX_TXCHANNELS] = {ADI_ADRV9025_TX1, ADI_ADRV9025_TX2, ADI_ADRV9025_TX3, ADI_ADRV9025_TX4}; + + static const uint32_t VALID_TXCHANMASK = 0x0000000F; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + coefs); + + ADRV9025_BUGINFO(__FUNCTION__); + + if ((txChannelMask & VALID_TXCHANMASK) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannelMask, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Program FIR filters */ + for (j = 0; j < ADI_ADRV9025_MAX_TXCHANNELS; j++) + { + maskBit = txFirLookup[j]; + if (ADRV9025_BF_EQUAL(txChannelMask, + maskBit)) + { + adrv9025_TxFirWrite(device, + maskBit, + gain_dB, + numFirCoefs, + coefs, + arraySize); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TxAttenTableWrite(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + uint32_t txAttenIndexOffset, + adi_adrv9025_TxAttenTableRow_t txAttenTableRows[], + uint32_t numTxAttenEntries) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t i = 0; + uint32_t j = 0; + uint32_t baseAddr = 0; + uint32_t maskBit = 0; + uint8_t cfgData[ADI_ADRV9025_TX_ATTEN_TABLE_CACHE_MAX + 10] = {0}; + uint32_t start = 0; + uint32_t stop = 0; + uint32_t data = 0; + uint32_t offset = 0; + static const uint8_t TX_ENTRY_SIZE = 4; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txAttenTableRows); + + ADRV9025_BUGINFO(__FUNCTION__); + +#if ADI_ADRV9025_TX_RANGE_CHECK > 0 + adrv9025_TxAttenTableWriteRangeCheck(device, + txChannelMask, + txAttenIndexOffset, + txAttenTableRows, + numTxAttenEntries); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + for (j = 0; j < ADI_ADRV9025_MAX_TXCHANNELS; j++) + { + maskBit = (1UL << j); + if (ADRV9025_BF_EQUAL(txChannelMask, + maskBit)) + { + baseAddr = adrv9025_txAttenAddrLookup(device, + maskBit); + + offset = (txAttenIndexOffset * TX_ENTRY_SIZE) + baseAddr; + start = 0; + stop = 0; + for (i = 0; i < numTxAttenEntries; i++) + { + data = ADRV9025_BF_ENCODE((uint32_t)(txAttenTableRows[i].txAttenHp), + ADRV9025_TX_ATTEN_TABLE_HP_MASK, + ADRV9025_TX_ATTEN_TABLE_HP_SHIFT); + data |= ADRV9025_BF_ENCODE((uint32_t)(txAttenTableRows[i].txAttenMult), + ADRV9025_TX_ATTEN_TABLE_MULT_MASK, + ADRV9025_TX_ATTEN_TABLE_MULT_SHIFT); + cfgData[start] = (uint8_t)(data & 0x000000FF); + cfgData[start + 1] = (uint8_t)((data >> 8) & 0x000000FF); + cfgData[start + 2] = (uint8_t)((data >> 16) & 0x000000FF); + cfgData[start + 3] = (uint8_t)((data >> 24) & 0x000000FF); + + start += TX_ENTRY_SIZE; + if (start >= ADI_ADRV9025_TX_ATTEN_TABLE_CACHE_MAX) + { + adrv9025_CpuDmaMemWrite(device, + offset + stop, + &cfgData[0], + start, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_RETURN(device->common.error.newAction); + stop += start; + start = 0; + } + } + + if (start > 0) + { + recoveryAction = adrv9025_CpuDmaMemWrite(device, + offset + stop, + &cfgData[0], + start, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error from DmaMemWrite"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TxAttenTableRead(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + uint32_t txAttenIndexOffset, + adi_adrv9025_TxAttenTableRow_t txAttenTableRows[], + uint32_t numTxAttenEntries) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t i = 0; + uint32_t baseAddr = 0; + uint8_t cfgData[ADI_ADRV9025_TX_ATTEN_TABLE_CACHE_MAX + 10] = {0}; + uint32_t start = 0; + uint32_t stop = 0; + uint32_t data = 0; + uint32_t offset; + uint32_t numTxAttenEntriesRead = 0; + uint32_t maxAttenIndex = 0; + + static const uint8_t TX_ENTRY_SIZE = 4; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txAttenTableRows); + + ADRV9025_BUGINFO(__FUNCTION__); + + maxAttenIndex = ADRV9025_TX_ATTEN_TABLE_MAX; + + if (adrv9025_txAttenAddrLookup(device, + txChannel) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid TxChannelMask"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((numTxAttenEntries == 0) || (numTxAttenEntries > maxAttenIndex)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device, + "Invalid numTxAttenEntries"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (txAttenIndexOffset + numTxAttenEntries > maxAttenIndex) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenIndexOffset, + "Invalid txAttenIndexOffset + numTxAttenEntries"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + baseAddr = adrv9025_txAttenAddrLookup(device, + txChannel); + + start = 0; + stop = 0; + offset = (txAttenIndexOffset * TX_ENTRY_SIZE) + baseAddr; + + numTxAttenEntriesRead = numTxAttenEntries * TX_ENTRY_SIZE; + if (numTxAttenEntriesRead > ADI_ADRV9025_TX_ATTEN_TABLE_CACHE_MAX) + { + numTxAttenEntriesRead = ADI_ADRV9025_TX_ATTEN_TABLE_CACHE_MAX; + } + + recoveryAction = adrv9025_CpuDmaMemRead(device, + offset + stop, + (uint8_t *)&cfgData[0], + numTxAttenEntriesRead, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error from DmaMemRead"); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < numTxAttenEntries; i++) + { + data = (((uint32_t)cfgData[start + 3] << 24) | ((uint32_t)cfgData[start + 2] << 16) | + ((uint32_t)cfgData[start + 1] << 8) | (uint32_t)cfgData[start + 0]); + + txAttenTableRows[i].txAttenHp = ADRV9025_BF_DECODE(data, + ADRV9025_TX_ATTEN_TABLE_HP_MASK, + ADRV9025_TX_ATTEN_TABLE_HP_SHIFT); + txAttenTableRows[i].txAttenMult = ADRV9025_BF_DECODE(data, + ADRV9025_TX_ATTEN_TABLE_MULT_MASK, + ADRV9025_TX_ATTEN_TABLE_MULT_SHIFT); + + start += TX_ENTRY_SIZE; + + if ((start >= ADI_ADRV9025_TX_ATTEN_TABLE_CACHE_MAX) && + ((i + 1) < numTxAttenEntries)) + { + numTxAttenEntriesRead = (numTxAttenEntries - (i + 1)) * TX_ENTRY_SIZE; + if (numTxAttenEntriesRead > ADI_ADRV9025_TX_ATTEN_TABLE_CACHE_MAX) + { + numTxAttenEntriesRead = ADI_ADRV9025_TX_ATTEN_TABLE_CACHE_MAX; + } + + stop += start; + adrv9025_CpuDmaMemRead(device, + offset + stop, + &cfgData[0], + numTxAttenEntriesRead, + 0); + ADI_ERROR_RETURN(device->common.error.newAction); + start = 0; + } + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TxPaProtectionCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxPaProtectCfg_t txPaProtectCfg[], + uint8_t arraySize) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int8_t i = 0; + int8_t j = 0; + uint32_t channelLoop = 0; + adi_adrv9025_TxChannels_e txChannel = ADI_ADRV9025_TXALL; + adrv9025_BfTxChanAddr_e baseAddress = ADRV9025_BF_ALL_TX_CHANNELS; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txPaProtectCfg); + + /* check configs is > 0 and <= 4 */ + if (arraySize == 0 || arraySize > 4) + { + /* no valid configs */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + arraySize, + "Invalid number of channels"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < arraySize; i++) + { + /* range check for all the values*/ + if (adrv9025_TxPaProtectCfgRangeCheck(device, + &txPaProtectCfg[i]) != 0) + { + /* no valid configs */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + arraySize, + device->common.error.errormessage); + + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + channelLoop = txPaProtectCfg[i].txChannel; + + for (j = 0; j < ADI_ADRV9025_MAX_TXCHANNELS; j++) + { + if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX1)) + { + txChannel = ADI_ADRV9025_TX1; + baseAddress = ADRV9025_BF_TX_CH0; + channelLoop = channelLoop & ~ADI_ADRV9025_TX1; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX2)) + { + txChannel = ADI_ADRV9025_TX2; + baseAddress = ADRV9025_BF_TX_CH1; + channelLoop = channelLoop & ~ADI_ADRV9025_TX2; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX3)) + { + txChannel = ADI_ADRV9025_TX3; + baseAddress = ADRV9025_BF_TX_CH2; + channelLoop = channelLoop & ~ADI_ADRV9025_TX3; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX4)) + { + txChannel = ADI_ADRV9025_TX4; + baseAddress = ADRV9025_BF_TX_CH3; + channelLoop = channelLoop & ~ADI_ADRV9025_TX4; + } + /* error condition break loop and report error */ + else if (channelLoop == 0) + { + /* All channels setup */ + break; + } + /* error condition break loop and report error */ + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenPinCfg[i].txChannelMask, + "Error while accessing selected Tx channel. Only Tx1-Tx2-Tx3-Tx4 channels are supported"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Set average duration */ + recoveryAction = adrv9025_TxPaProtectionAvrgDurBfSet(device, + baseAddress, + txPaProtectCfg[i].avgDuration); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + txPaProtectCfg[i].avgDuration, + "Error while setting Pa protection average field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set peak Duration */ + recoveryAction = adrv9025_TxPaProtectionPeakDurBfSet(device, + baseAddress, + txPaProtectCfg[i].peakDuration); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + txPaProtectCfg[i].peakDuration, + "Error while setting Pa peakDuration field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set Tx Attenuation Step. Gain step down is not allowed. Always assign attenuation step to 0 */ + recoveryAction = adrv9025_TxPaProtectionTxAttenStepBfSet(device, + baseAddress, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + 0, + "Error while setting Pa txAttenStep field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set Gain Step Down Enable bit. Gain step down is not allowed. Always assign this bit to 0 */ + recoveryAction = adrv9025_TxPaProtectionGainStepDownEnBfSet(device, + baseAddress, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + txPaProtectCfg[i].gainStepDownEn, + "Error while setting Pa gainStepDownEn field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set Average Power Threshold */ + recoveryAction = adrv9025_TxPaProtectionAvgThresholdBfSet(device, + baseAddress, + txPaProtectCfg[i].powerThreshold); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + txPaProtectCfg[i].powerThreshold, + "Error while setting Pa powerThreshold field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set Peak Count value */ + recoveryAction = adrv9025_TxPaProtectionPeakCountBfSet(device, + baseAddress, + txPaProtectCfg[i].peakCount); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + txPaProtectCfg[i].peakCount, + "Error while setting Pa peakCount field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set Peak Threshold */ + adrv9025_TxPaProtectionPeakThresholdBfSet(device, + baseAddress, + txPaProtectCfg[i].peakThreshold); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + txPaProtectCfg[i].peakThreshold, + "Error while setting Pa peakThreshold field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set Input Selection */ + adrv9025_TxPaProtectionInputSelBfSet(device, + baseAddress, + (uint8_t)txPaProtectCfg[i].inputSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + txPaProtectCfg[i].inputSel, + "Error while setting Pa protection input selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set Average Power Ratio Calculation Enable bit */ + adrv9025_TxPaProtectionAprEnBfSet(device, + baseAddress, + txPaProtectCfg[i].avgPeakRatioEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + txPaProtectCfg[i].avgPeakRatioEnable, + "Error while setting pa protection average peak power ratio calculation enable field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set Average Power Enable bit */ + adrv9025_TxPaProtectionAvgpowerEnBfSet(device, + baseAddress, + txPaProtectCfg[i].avgPowerEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + txPaProtectCfg[i].avgPowerEnable, + "Error while setting pa protection average power enable field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set Peak Power Enable bit */ + adrv9025_TxPaProtectionPeakpowerEnBfSet(device, + baseAddress, + txPaProtectCfg[i].peakPowerEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + txPaProtectCfg[i].peakPowerEnable, + "Error while setting pa protection peak power enable field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Clear Error Flags */ + adi_adrv9025_TxPaProtectionErrFlagsReset(device, + txChannel, + ADI_ADRV9025_TXPA_PROTECT_FLAGS_ALL); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + txPaProtectCfg, + "Error while clearing error flags"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxPaProtectionCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxPaProtectCfg_t* txPaProtectCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint16_t baseAddress = 0; + uint8_t avgDuration = 0; /*!< PA Protection Average Power Measurement Duration. */ + uint8_t peakDuration = 0; /*!< PA Protection Peak Power Measurement Duration */ + uint16_t powerThreshold = 0; /*!< PA Protection Average Power Threshold. */ + uint8_t peakCount = 0; /*!< Peak Count Causing PA Error. */ + uint16_t peakThreshold = 0; /*!< PA Protection Peak Power Threshold. */ + uint8_t rampStepDuration = 0; /*!< PA Protection Ramp Step duration. */ + uint8_t rampStepSize = 0; /*!< PA Protection Ramp Step Size */ + uint8_t rampMaxAtten = 0; /*!< PA Protection Ramp Max Attenuation. */ + uint8_t avgPowerEnable = 0; /*!< PA Protection Avg Power Enable */ + uint8_t peakPowerEnable = 0; /*!< PA Protection Peak Power Enable */ + uint8_t inputSel = 0; /*!< Pa Protection block input selection */ + uint8_t avgPeakRatioEnable = 0; /*!< Pa Protection Average to Peak Ratio Calculation Enable */ + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txPaProtectCfg); + + if ((baseAddress = adrv9025_TxAddrDecode(device, + txChannel)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get average duration for the tx channel */ + recoveryAction = adrv9025_TxPaProtectionAvrgDurBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &avgDuration); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while accessing Pa protection average field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Peak duration for the tx channel */ + recoveryAction = adrv9025_TxPaProtectionPeakDurBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &peakDuration); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while accessing Pa peak duration field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Average Power Enable bit */ + recoveryAction = adrv9025_TxPaProtectionAvgpowerEnBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &avgPowerEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + avgPowerEnable, + "Error while reading pa protection average power enable field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Peak Power Enable bit */ + recoveryAction = adrv9025_TxPaProtectionPeakpowerEnBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &peakPowerEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + peakPowerEnable, + "Error while reading pa protection peak power enable field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Average Power Threshold for the tx channel */ + recoveryAction = adrv9025_TxPaProtectionAvgThresholdBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &powerThreshold); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while accessing Pa average threshold field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Peak Count for the tx channel */ + recoveryAction = adrv9025_TxPaProtectionPeakCountBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &peakCount); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while accessing Pa peak count field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Average Power Ratio Calculation Enable bit */ + recoveryAction = adrv9025_TxPaProtectionAprEnBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &avgPeakRatioEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + avgPeakRatioEnable, + "Error while reading pa protection average peak power ratio calculation enable field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Peak Threshold for the tx channel */ + recoveryAction = adrv9025_TxPaProtectionPeakThresholdBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &peakThreshold); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while accessing Pa peak threshold field - Silicon B"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Ramp Step Duration for the tx channel */ + recoveryAction = adrv9025_TxPaProtectionRampStepDurationBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &rampStepDuration); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while accessing Pa ramp step duration field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Ramp Step Size for the tx channel */ + recoveryAction = adrv9025_TxPaProtectionRampStepSizeBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &rampStepSize); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while accessing Pa ramp step size field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Max Ramp attenuation for the tx channel */ + recoveryAction = adrv9025_TxPaProtectionRampMaxAttenuationBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &rampMaxAtten); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while accessing Pa max ramp attenuation field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Input Selection */ + recoveryAction = adrv9025_TxPaProtectionInputSelBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &inputSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + inputSel, + "Error while reading Pa protection input selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Assignment of all the readback values to the structure object*/ + txPaProtectCfg->txChannel = txChannel; + txPaProtectCfg->avgDuration = avgDuration; + txPaProtectCfg->peakDuration = peakDuration; + txPaProtectCfg->txAttenStep = 0; /* Gain step down is not allowed for Madura device. This field is not being used actively.*/ + txPaProtectCfg->gainStepDownEn = 0; /* Gain step down is not allowed for Madura device. This field is not being used actively.*/ + txPaProtectCfg->powerThreshold = powerThreshold; + txPaProtectCfg->peakCount = peakCount; + txPaProtectCfg->peakThreshold = peakThreshold; + txPaProtectCfg->rampStepDuration = rampStepDuration; + txPaProtectCfg->rampStepSize = rampStepSize; + txPaProtectCfg->rampMaxAtten = rampMaxAtten; + txPaProtectCfg->avgPowerEnable = avgPowerEnable; + txPaProtectCfg->peakPowerEnable = peakPowerEnable; + txPaProtectCfg->inputSel = (adi_adrv9025_PaProtectionInputSel_e)inputSel; + txPaProtectCfg->avgPeakRatioEnable = avgPeakRatioEnable; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxPaProtectionErrFlagsGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxPaProtectionErr_t* errorFlags) +{ + static const uint16_t AVERAGE_POWER_ADDRESS = 0x00A3; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint16_t baseAddress = 0; + uint8_t avgPowerErr = 0; + uint16_t powerErr = 0; + uint8_t peakPowerErr = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + errorFlags); + + /* obtain the base address for the Tx Channel */ + if ((baseAddress = adrv9025_TxAddrDecode(device, + txChannel)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Write a random byte to average power error to trigger the update, bf function is not available for this byte set */ + recoveryAction = adi_adrv9025_SpiByteWrite(device, + baseAddress + AVERAGE_POWER_ADDRESS, + 0x00); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while writing spi byte, average power error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Average Power Err for the tx channel */ + recoveryAction = adrv9025_TxPaProtectionAvgpowerErrorBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &avgPowerErr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while accessing Pa error field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Power Err for the tx channel */ + recoveryAction = adrv9025_TxPaProtectionErrorPowerBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &powerErr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while accessing Pa error field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get Peak Power Err for the tx channel */ + recoveryAction = adrv9025_TxPaProtectionPeakpowerErrorBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &peakPowerErr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while accessing Pa error field - Silicon B"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Assignment of the readback values to the structure object */ + errorFlags->avgPowerErr = avgPowerErr; + errorFlags->powerErr = powerErr; + errorFlags->peakPowerErr = peakPowerErr; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxPaProtectionStatusGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxPaProtectStatus_t* status) +{ + static uint16_t AVERAGE_POWER_ADDRESS = 0x00A3; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint16_t avgPower = 0; + uint16_t avgPeakRatio = 0; + uint16_t avgErrorPower = 0; + uint16_t baseAddress = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + status); + + /* obtain the base address for the Tx Channel */ + if ((baseAddress = adrv9025_TxAddrDecode(device, + txChannel)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Write a random byte to average power error to trigger the update, bf function is not available for this byte set */ + recoveryAction = adi_adrv9025_SpiByteWrite(device, + baseAddress + AVERAGE_POWER_ADDRESS, + 0x00); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while writing spi byte, average power error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get average power status for the tx channel. */ + recoveryAction = adrv9025_TxPaProtectionAveragePowerBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &avgPower); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while accessing Pa average power status field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get average peak ratio status for the tx channel. */ + recoveryAction = adrv9025_TxPaProtectionAveragePeakRatioBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &avgPeakRatio); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while accessing Pa average peak ratio status field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Get error average power for the tx channel */ + recoveryAction = adrv9025_TxPaProtectionErrorPowerBfGet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + &avgErrorPower); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while accessing error average power status field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Assignment of the readback values to the structure. */ + status->avgPower = avgPower; + status->avgPeakRatio = avgPeakRatio; + status->avgErrorPower = avgErrorPower; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxPaProtectionErrFlagsReset(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxPaProtectErrFlags_e errorFlags) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint16_t baseAddress = 0; + uint8_t resetValue = 1; + + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* obtain the base address for the Tx Channel */ + if ((baseAddress = adrv9025_TxAddrDecode(device, + txChannel)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check whether to clear average power error for the tx channel, if yes reset it */ + if ((errorFlags & ADI_ADRV9025_TXPA_PROTECT_FLAGS_AVG_POWER_ERR) == ADI_ADRV9025_TXPA_PROTECT_FLAGS_AVG_POWER_ERR) + { + recoveryAction = adrv9025_TxPaProtectionAvgpowerErrorClearBfSet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + resetValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while clearing average power error field"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check whether to clear peak power error for the tx channel, if yes reset it */ + if ((errorFlags & ADI_ADRV9025_TXPA_PROTECT_FLAGS_PEAK_POWER_ERR) == ADI_ADRV9025_TXPA_PROTECT_FLAGS_PEAK_POWER_ERR) + { + recoveryAction = adrv9025_TxPaProtectionPeakpowerErrorClearBfSet(device, + (adrv9025_BfTxChanAddr_e)baseAddress, + resetValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while clearing peak power error field - Silicon B"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxAttenSpi2PinCtrlCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxAttenSpi2PinCfg_t txAttenSpi2PinCfg[], + uint8_t numTxAttenSpi2PinConfigs) +{ + static const adrv9025_FeatureID_e THIS_FEATURE_ID = ADRV9025_FEATURE_TX_ATTEN_CTRL_PIN; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t i = 0; + uint8_t j = 0; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + int32_t sharedResourceArr[ADI_ADRV9025_NUM_GPIOS_IN_TX_ATTEN_CTRL_SPI2_PIN_FEATURE] = {0}; + uint8_t resourceAcquisitionStatus = ADI_FAILURE; + uint8_t resourceReleaseStatus = ADI_FAILURE; + uint8_t currentTxAttenCtrlSpi2Pin = 0; + uint32_t spi2GpioPinMask = 0; + uint32_t channelLoop = 0; + + static const uint32_t SPI2_GPIO_OFFSET = 3; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txAttenSpi2PinCfg); + + /* check configs is > 0 */ + if (numTxAttenSpi2PinConfigs == 0) + { + /* no valid configs */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + numTxAttenSpi2PinConfigs, + "Invalid number of configs"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Loop through the number of configurations passed */ + for (i = 0; i < numTxAttenSpi2PinConfigs; i++) + { + if (txAttenSpi2PinCfg[i].txAttenSpi2Pin > ADI_ADRV9025_SPI2_TXATTEN_GPIO18) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenSpi2PinCfg, + "Invalid configuration found"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + channelLoop = txAttenSpi2PinCfg[i].txChannelMask; + for (j = 0; j < ADI_ADRV9025_MAX_TXCHANNELS; j++) + { + if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX1)) + { + txChannelBaseAddr = ADRV9025_BF_TX_CH0; + channelLoop = channelLoop & ~ADI_ADRV9025_TX1; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX2)) + { + txChannelBaseAddr = ADRV9025_BF_TX_CH1; + channelLoop = channelLoop & ~ADI_ADRV9025_TX2; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX3)) + { + txChannelBaseAddr = ADRV9025_BF_TX_CH2; + channelLoop = channelLoop & ~ADI_ADRV9025_TX3; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX4)) + { + txChannelBaseAddr = ADRV9025_BF_TX_CH3; + channelLoop = channelLoop & ~ADI_ADRV9025_TX4; + } + /* error condition break loop and report error */ + else if (channelLoop == 0) + { + /* All channels setup */ + break; + } + /* error condition break loop and report error */ + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenPinCfg[i].txChannelMask, + "Error while accessing selected Tx channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Read Tx Attenuation Spi2 GPIO select */ + recoveryAction = adrv9025_TxSpi2TxAttenGpioSelectBfGet(device, + txChannelBaseAddr, + ¤tTxAttenCtrlSpi2Pin); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read Attenuation Spi2 GPIO select register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (currentTxAttenCtrlSpi2Pin > ADI_ADRV9025_SPI2_TXATTEN_DISABLE) + { + /* Attempt to Release Attenuation Ctrl Spi2 GPIO since it is a shared resource. + * This is to ensure that this feature is not accidentally releasing the GPIO + * which is actively in use by another feature */ + sharedResourceArr[0] = (uint8_t)currentTxAttenCtrlSpi2Pin + SPI2_GPIO_OFFSET; + recoveryAction = adrv9025_SharedResourcesRelease(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + ADI_ADRV9025_NUM_GPIOS_IN_TX_ATTEN_CTRL_SPI2_PIN_FEATURE, + THIS_FEATURE_ID, + &resourceReleaseStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to release GPIO shared resouce for GPIO attenuation Spi2 Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceReleaseStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceReleaseStatus, + "Error while attempting to release GPIO shared resouce for GPIO gain ctrl Increment/Decrement Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Set released GPIO pins as inputs since unused pins are supposed to be inputs*/ + spi2GpioPinMask = ((uint32_t)0x00000001 << ((uint8_t)currentTxAttenCtrlSpi2Pin + SPI2_GPIO_OFFSET)); + recoveryAction = adi_adrv9025_GpioInputDirSet(device, + (spi2GpioPinMask)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while attempting to set GPIO Spi2 Pin inputs"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Tx attenuation Ctrl Spi2 Pint select */ + currentTxAttenCtrlSpi2Pin = 0; + adrv9025_TxSpi2TxAttenGpioSelectBfSet(device, + txChannelBaseAddr, + currentTxAttenCtrlSpi2Pin); + recoveryAction = adrv9025_TxAttenSpi2CtrlPinReportError(device, + &sharedResourceArr[0], + recoveryAction, + "Error while attempting to set GPIO for attenuation Spi2"); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txAttenPinCfg, + "Error while attempting to set GPIO Tx attenuation Spi2 pin control"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (txAttenSpi2PinCfg[i].txAttenSpi2Pin > ADI_ADRV9025_SPI2_TXATTEN_DISABLE) + { + /* Attempt to Acquire Gain Ctrl Increment GPIO since it is a shared resource. This is to ensure that this feature is not accidentally acquiring the GPIO + which is actively in use by another feature */ + sharedResourceArr[0] = (uint32_t)txAttenSpi2PinCfg[i].txAttenSpi2Pin + SPI2_GPIO_OFFSET; + recoveryAction = adrv9025_SharedResourcesAcquire(device, + ADRV9025_SHARED_RESOURCE_GPIO, + &sharedResourceArr[0], + ADI_ADRV9025_NUM_GPIOS_IN_TX_ATTEN_CTRL_SPI2_PIN_FEATURE, + THIS_FEATURE_ID, + &resourceAcquisitionStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to acquire GPIO shared resouce for GPIO Attenuation Spi2 Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resourceAcquisitionStatus == ADI_FAILURE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + resourceAcquisitionStatus, + "Error while attempting to acquire GPIO shared resouce for GPIO Attenuation ctrl Spi2 Pins"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Set ADRV9025 GPIO Directions for Gain ctrl GPIO Spi2 pins*/ + spi2GpioPinMask = ((uint32_t)0x00000001 << ((uint8_t)txAttenSpi2PinCfg[i].txAttenSpi2Pin + SPI2_GPIO_OFFSET)); + adi_adrv9025_GpioInputDirSet(device, + (spi2GpioPinMask)); + recoveryAction = adrv9025_TxAttenSpi2CtrlPinReportError(device, + &sharedResourceArr[0], + recoveryAction, + "Error while attempting to set GPIO direction"); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txAttenSpi2PinCfg, + "Error while attempting to set GPIO pin control"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Set Tx attenuation Ctrl Spi2 GPIO select */ + adrv9025_TxSpi2TxAttenGpioSelectBfSet(device, + txChannelBaseAddr, + txAttenSpi2PinCfg[i].txAttenSpi2Pin); + recoveryAction = adrv9025_TxAttenSpi2CtrlPinReportError(device, + &sharedResourceArr[0], + recoveryAction, + "Error while attempting to set GPIO for attenuation Spi2"); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txAttenPinCfg, + "Error while attempting to set GPIO Tx attenuation Spi2 pin control"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxAttenSpi2PinCtrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_TxAttenSpi2PinCfg_t* txAttenSpi2PinCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + uint8_t currentTxAttenSpi2CtrlPin = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txAttenSpi2PinCfg); + + switch (txChannel) + { + case ADI_ADRV9025_TX1: + txChannelBaseAddr = ADRV9025_BF_TX_CH0; + break; + case ADI_ADRV9025_TX2: + txChannelBaseAddr = ADRV9025_BF_TX_CH1; + break; + case ADI_ADRV9025_TX3: + txChannelBaseAddr = ADRV9025_BF_TX_CH2; + break; + case ADI_ADRV9025_TX4: + txChannelBaseAddr = ADRV9025_BF_TX_CH3; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenSpi2PinCfg[i].txChannelMask, + "Error while accessing selected Tx channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Read Tx Attenuation Spi2 GPIO select */ + recoveryAction = adrv9025_TxSpi2TxAttenGpioSelectBfGet(device, + txChannelBaseAddr, + ¤tTxAttenSpi2CtrlPin); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read Attenuation Spi2 GPIO select register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + txAttenSpi2PinCfg->txAttenSpi2Pin = (adi_adrv9025_Spi2TxAttenGpioSel_e)currentTxAttenSpi2CtrlPin; + txAttenSpi2PinCfg->txChannelMask = txChannel; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxLoSourceGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_LoSel_e* txLoSource) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check Rx data format config pointer is not NULL*/ + ADI_NULL_PTR_RETURN(&device->common, + txLoSource); + +#if ADI_ADRV9025_RX_RANGE_CHECK > 0 + recoveryAction = adrv9025_TxLoSourceGetRangeCheck(device, + txChannel, + txLoSource); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txChannel, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + recoveryAction = adrv9025_TxLoSourceGet(device, + txChannel, + txLoSource); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + txChannel, + "Failure to get Tx Lo source"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PaPllDfrmEventRampDownEnableSet(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + uint32_t irqMask, + uint8_t enable) +{ + static uint8_t PA_PROTECTION_RAMP_STEP_DURATION = 0x0A; + static uint8_t PA_PROTECTION_RAMP_MAX_ATTENUATION = 0x64; + static uint8_t PA_PROTECTION_RAMP_STEP_SIZE = 0x02; + + static const uint32_t ALL_TX_MASK = (uint32_t)ADI_ADRV9025_TX1 | (uint32_t)ADI_ADRV9025_TX2 | + (uint32_t)ADI_ADRV9025_TX3 | (uint32_t)ADI_ADRV9025_TX4; + + static const uint32_t ALL_DFRM_IRQ_MASK = (uint32_t)ADI_ADRV9025_RAMP_DOWN_ON_DFRMIRQ0 | (uint32_t)ADI_ADRV9025_RAMP_DOWN_ON_DFRMIRQ1; + + static const uint32_t ALL_PLL_UNLOCK_MASK = (uint32_t)ADI_ADRV9025_RAMP_DOWN_ON_RF1PLLUNLOCK | (uint32_t)ADI_ADRV9025_RAMP_DOWN_ON_RF2PLLUNLOCK | + (uint32_t)ADI_ADRV9025_RAMP_DOWN_ON_AUXPLLUNLOCK | (uint32_t)ADI_ADRV9025_RAMP_DOWN_ON_CLKPLLUNLOCK | + (uint32_t)ADI_ADRV9025_RAMP_DOWN_ON_SERDESPLLUNLOCK; + + static const uint32_t PLL_UNLOCK_MASK_SHIFT = 2; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t pllSelect = 0; + uint8_t dfrmIrqSelect = 0; + uint8_t pllReadBackValue = 0; + uint8_t dfrmIrqReadBackValue = 0; + uint8_t k = 0; + + adrv9025_BfTxChanAddr_e baseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /*Check that if requested Tx Channel valid*/ + if (((txChannelMask & (~ALL_TX_MASK)) != 0) || txChannelMask == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannelMask, + "Invalid Tx Channel is selected to enable/disable ramp-down. Valid values are different combinations of TX1-2-3-4."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that if requested Irq event valid*/ + if (((irqMask & (~(ALL_DFRM_IRQ_MASK | ALL_PLL_UNLOCK_MASK | (uint32_t)ADI_ADRV9025_RAMP_DOWN_ON_PA_PROT_ERROR))) != 0) || irqMask == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + irqMask, + "Invalid Irq event is selected to enable/disable ramp-down. Valid values are different combinations of DFRM IRQ 0-1/RF1-RF2-AUX-CLK-SERDES PLL UNLOCK/PA PROT ERROR."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + enable = (enable == 0) ? ADI_FALSE : ADI_TRUE; + + for (k = 0; k < ADI_ADRV9025_MAX_TXCHANNELS; k++) + { + if (ADRV9025_BF_EQUAL(txChannelMask, + ((uint32_t)1 << (uint32_t)k))) + { + if ((baseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + ((uint32_t)1 << (uint32_t)k))) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Set Ramp Step Duration */ + recoveryAction = adrv9025_TxPaProtectionRampStepDurationBfSet(device, + baseAddr, + PA_PROTECTION_RAMP_STEP_DURATION); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + PA_PROTECTION_RAMP_STEP_DURATION, + "Error while setting Pa rampStepDuration field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set Ramp Step Size */ + recoveryAction = adrv9025_TxPaProtectionRampStepSizeBfSet(device, + baseAddr, + PA_PROTECTION_RAMP_STEP_SIZE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + PA_PROTECTION_RAMP_STEP_SIZE, + "Error while setting Pa rampStepSize field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set Max Ramp Attenuation */ + recoveryAction = adrv9025_TxPaProtectionRampMaxAttenuationBfSet(device, + baseAddr, + PA_PROTECTION_RAMP_MAX_ATTENUATION); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + PA_PROTECTION_RAMP_MAX_ATTENUATION, + "Error while setting Pa rampMaxAtten field"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* 1) Pa Protection Errors Ramp Down */ + if (ADRV9025_BF_EQUAL(irqMask, + (uint32_t)ADI_ADRV9025_RAMP_DOWN_ON_PA_PROT_ERROR)) + { + recoveryAction = adrv9025_TxPaProtectionGainRampDownEnBfSet(device, + baseAddr, + enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + enable, + "Could not enable/disable ramp-down for pa protection errors"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* 2) PLL Unlock and Dfrm Irq Ramp Down */ + if ((irqMask & (ALL_DFRM_IRQ_MASK | ALL_PLL_UNLOCK_MASK)) > 0) + { + pllSelect = (uint8_t)((irqMask & ALL_PLL_UNLOCK_MASK) >> PLL_UNLOCK_MASK_SHIFT); + dfrmIrqSelect = (uint8_t)(irqMask & ALL_DFRM_IRQ_MASK); + + recoveryAction = adrv9025_TxPllUnlockMaskBfGet(device, + baseAddr, + &pllReadBackValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + pllReadBackValue, + "Could not read Pll Unlock Mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxJesdDfrmMaskBfGet(device, + baseAddr, + &dfrmIrqReadBackValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + dfrmIrqReadBackValue, + "Could not read Dfrm Irq Mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (enable == ADI_FALSE) + { + /* Set selected mask bits to ignore error */ + pllReadBackValue |= pllSelect; + dfrmIrqReadBackValue |= dfrmIrqSelect; + } + else + { + /* Clear selected mask bits to enable ramp down */ + pllReadBackValue &= (~pllSelect); + dfrmIrqReadBackValue &= (~dfrmIrqSelect); + } + + recoveryAction = adrv9025_TxPllUnlockMaskBfSet(device, + baseAddr, + pllReadBackValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + pllReadBackValue, + "Could not write Pll Unlock Mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxJesdDfrmMaskBfSet(device, + baseAddr, + dfrmIrqReadBackValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + dfrmIrqReadBackValue, + "Could not write Dfrm Irq Mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PaPllDfrmEventRampDownEnableGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannelSelect, + adi_adrv9025_PaPllDfrmRampDownEnSel_e irqSelect, + uint8_t* enable) +{ + static const uint32_t PLL_MASK_SHIFT = 2; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t pllReadBackValue = 0; + uint8_t dfrmIrqReadBackValue = 0; + uint8_t mergedReadBackValue = 0; + adrv9025_BfTxChanAddr_e baseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that if enable pointer is not NULL */ + ADI_NULL_PTR_RETURN(&device->common, + enable); + + /* Check that if requested Tx Channel is valid */ + if ((txChannelSelect != ADI_ADRV9025_TX1) && + (txChannelSelect != ADI_ADRV9025_TX2) && + (txChannelSelect != ADI_ADRV9025_TX3) && + (txChannelSelect != ADI_ADRV9025_TX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannelSelect, + "Invalid Tx Channel is selected to read ramp-down status. Valid values are TX1-2-3-4."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check that if requested Irq event is valid*/ + if ((irqSelect != ADI_ADRV9025_RAMP_DOWN_ON_DFRMIRQ0) && + (irqSelect != ADI_ADRV9025_RAMP_DOWN_ON_DFRMIRQ1) && + (irqSelect != ADI_ADRV9025_RAMP_DOWN_ON_RF1PLLUNLOCK) && + (irqSelect != ADI_ADRV9025_RAMP_DOWN_ON_RF2PLLUNLOCK) && + (irqSelect != ADI_ADRV9025_RAMP_DOWN_ON_AUXPLLUNLOCK) && + (irqSelect != ADI_ADRV9025_RAMP_DOWN_ON_CLKPLLUNLOCK) && + (irqSelect != ADI_ADRV9025_RAMP_DOWN_ON_SERDESPLLUNLOCK) && + (irqSelect != ADI_ADRV9025_RAMP_DOWN_ON_PA_PROT_ERROR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + irqSelect, + "Invalid Irq event is selected to read ramp-down status. Valid values are DFRM IRQ 0-1/RF1-RF2-AUX-CLK-SERDES PLL UNLOCK/PA-PROT-ERROR."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((baseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + (uint32_t)txChannelSelect)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannelSelect, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (irqSelect == ADI_ADRV9025_RAMP_DOWN_ON_PA_PROT_ERROR) + { + recoveryAction = adrv9025_TxPaProtectionGainRampDownEnBfGet(device, + baseAddr, + enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + irqSelect, + "Could not read ramp-down status for pa protection error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = adrv9025_TxPllUnlockMaskBfGet(device, + baseAddr, + &pllReadBackValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + pllReadBackValue, + "Could not read Pll Unlock Mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxJesdDfrmMaskBfGet(device, + baseAddr, + &dfrmIrqReadBackValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + dfrmIrqReadBackValue, + "Could not read Dfrm Irq Mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + + mergedReadBackValue = dfrmIrqReadBackValue | (pllReadBackValue << PLL_MASK_SHIFT); + mergedReadBackValue &= (uint8_t)irqSelect; + if (mergedReadBackValue > 0) + { + *enable = 0; + } + else + { + *enable = 1; + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PaPllDfrmEventGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannelSelect, + uint8_t* eventBits) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t mergedReadVal = 0; + uint8_t readVal = 0; + adrv9025_BfTxChanAddr_e baseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that if eventBits pointer is not NULL */ + ADI_NULL_PTR_RETURN(&device->common, + eventBits); + + /* Check that if requested Tx Channel is valid */ + if ((txChannelSelect != ADI_ADRV9025_TX1) && + (txChannelSelect != ADI_ADRV9025_TX2) && + (txChannelSelect != ADI_ADRV9025_TX3) && + (txChannelSelect != ADI_ADRV9025_TX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannelSelect, + "Invalid Tx Channel is selected to read pa protection event bits. Valid values are TX1-2-3-4."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((baseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + (uint32_t)txChannelSelect)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_TxPllJesdProtEventBfGet(device, + baseAddr, + &readVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while reading Pll Jesd error field - Silicon B"); + ADI_ERROR_RETURN(device->common.error.newAction); + mergedReadVal |= readVal; + mergedReadVal <<= 1; + + recoveryAction = adrv9025_TxPaProtectionPeakpowerErrorBfGet(device, + baseAddr, + &readVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while reading peak power error field - Silicon B"); + ADI_ERROR_RETURN(device->common.error.newAction); + mergedReadVal |= readVal; + mergedReadVal <<= 1; + + recoveryAction = adrv9025_TxPaProtectionAvgpowerErrorBfGet(device, + baseAddr, + &readVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while reading average power error field"); + ADI_ERROR_RETURN(device->common.error.newAction); + mergedReadVal |= readVal; + + *eventBits = mergedReadVal; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PaPllDfrmEventClear(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannelSelect, + uint8_t eventBits) +{ + static const uint8_t ALL_EVENTS = (uint8_t)ADI_ADRV9025_AVGPOWER_ERR | (uint8_t)ADI_ADRV9025_PEAKPOWER_ERR | (uint8_t)ADI_ADRV9025_PLLDFRM_ERR; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxChanAddr_e baseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that if requested Tx Channel is valid */ + if ((txChannelSelect != ADI_ADRV9025_TX1) && + (txChannelSelect != ADI_ADRV9025_TX2) && + (txChannelSelect != ADI_ADRV9025_TX3) && + (txChannelSelect != ADI_ADRV9025_TX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannelSelect, + "Invalid Tx Channel is selected to clear sticky pa protection event bits. Valid values are TX1-2-3-4."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((eventBits & (~ALL_EVENTS)) != 0) || (eventBits == 0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + eventBits, + "Invalid eventBits - Valid Values are combinations of AVGPOWER_ERR/PEAKPOWER_ERR/PLLDFRM_ERR"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((baseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + (uint32_t)txChannelSelect)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (ADRV9025_BF_EQUAL(eventBits, + (uint8_t)ADI_ADRV9025_PLLDFRM_ERR)) + { + recoveryAction = adrv9025_TxPllJesdProtClrBfSet(device, + baseAddr, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while setting clear bit for Pll Jesd error field - Silicon B"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if (ADRV9025_BF_EQUAL(eventBits, + (uint8_t)ADI_ADRV9025_PEAKPOWER_ERR)) + { + recoveryAction = adrv9025_TxPaProtectionPeakpowerErrorClearBfSet(device, + baseAddr, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while setting clear bit for peak power error field - Silicon B"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (ADRV9025_BF_EQUAL(eventBits, + (uint8_t)ADI_ADRV9025_AVGPOWER_ERR)) + { + recoveryAction = adrv9025_TxPaProtectionAvgpowerErrorClearBfSet(device, + baseAddr, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while setting clear bit for average power error field"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxAttenuationRampUpStickyModeEnable(adi_adrv9025_Device_t* device, + uint32_t channelMask, + uint8_t txPllJesdProtClrReqd, + uint8_t txPaProtectionAvgpowerErrorClearRequired, + uint8_t txPaProtectionPeakpowerErrorClearRequired) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxChanAddr_e txChannelBitfieldAddr = (adrv9025_BfTxChanAddr_e)ADRV9025_ADDR_CH0_TX; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if ((txChannelBitfieldAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + channelMask)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (txPllJesdProtClrReqd != ADI_TRUE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + TxPllJesdProtClrReqd, + "Invalid TxPllJesdProtClrReqd, txPllJesdProtClrReqd should always be ADI_TRUE"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txPaProtectionAvgpowerErrorClearRequired != ADI_TRUE) && (txPaProtectionAvgpowerErrorClearRequired != ADI_FALSE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + TxPaProtectionAvgpowerErrorClearRequired, + "Invalid TxPaProtectionAvgpowerErrorClearRequired"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txPaProtectionPeakpowerErrorClearRequired != ADI_TRUE) && (txPaProtectionPeakpowerErrorClearRequired != ADI_FALSE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + TxPaProtectionPeakpowerErrorClearRequired, + "Invalid TxPaProtectionPeakpowerErrorClearRequired"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_TxPllJesdProtClrReqdBfSet(device, + txChannelBitfieldAddr, + txPllJesdProtClrReqd); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxPaProtectionAvgpowerErrorClearRequiredBfSet(device, + txChannelBitfieldAddr, + txPaProtectionAvgpowerErrorClearRequired); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxPaProtectionPeakpowerErrorClearRequiredBfSet(device, + txChannelBitfieldAddr, + txPaProtectionPeakpowerErrorClearRequired); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SrlIrqGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + uint8_t* enable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_TX_CH0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check enable pointer is not NULL*/ + ADI_NULL_PTR_RETURN(&device->common, + enable); + + switch (txChannel) + { + case ADI_ADRV9025_TX1: + txChannelBaseAddr = ADRV9025_BF_TX_CH0; + break; + case ADI_ADRV9025_TX2: + txChannelBaseAddr = ADRV9025_BF_TX_CH1; + break; + case ADI_ADRV9025_TX3: + txChannelBaseAddr = ADRV9025_BF_TX_CH2; + break; + case ADI_ADRV9025_TX4: + txChannelBaseAddr = ADRV9025_BF_TX_CH3; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Error while accessing selected Tx channel - Supported values TX1-TX2-TX3-TX4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_TxSrlIrqBfGet(device, + txChannelBaseAddr, + enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read SRL IRQ status of selected Tx channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SrlIrqEnableSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + uint8_t enable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_TX_CH0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + switch (txChannel) + { + case ADI_ADRV9025_TX1: + txChannelBaseAddr = ADRV9025_BF_TX_CH0; + break; + case ADI_ADRV9025_TX2: + txChannelBaseAddr = ADRV9025_BF_TX_CH1; + break; + case ADI_ADRV9025_TX3: + txChannelBaseAddr = ADRV9025_BF_TX_CH2; + break; + case ADI_ADRV9025_TX4: + txChannelBaseAddr = ADRV9025_BF_TX_CH3; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Error while accessing selected Tx channel - Supported values TX1-TX2-TX3-TX4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + enable = (enable == 0) ? 0 : 1; + + recoveryAction = adrv9025_TxSrlIrqEnBfSet(device, + txChannelBaseAddr, + enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to enable/disable SRL interrupt for selected Tx channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SrlIrqEnableGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + uint8_t* enable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_TX_CH0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check enable pointer is not NULL*/ + ADI_NULL_PTR_RETURN(&device->common, + enable); + + switch (txChannel) + { + case ADI_ADRV9025_TX1: + txChannelBaseAddr = ADRV9025_BF_TX_CH0; + break; + case ADI_ADRV9025_TX2: + txChannelBaseAddr = ADRV9025_BF_TX_CH1; + break; + case ADI_ADRV9025_TX3: + txChannelBaseAddr = ADRV9025_BF_TX_CH2; + break; + case ADI_ADRV9025_TX4: + txChannelBaseAddr = ADRV9025_BF_TX_CH3; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Error while accessing selected Tx channel - Supported values TX1-TX2-TX3-TX4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_TxSrlIrqEnBfGet(device, + txChannelBaseAddr, + enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read SRL IRQ enabled status of selected Tx channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SrlStatisticsRead(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + uint8_t clearStats, + uint16_t* statisticsReadBack) +{ + static const uint8_t ARM_ERR_SHIFT = 1; + static const uint8_t clrBitPositionInPayload = 0x40; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_TX_CH0; + uint8_t statsEnabled = 0; + uint8_t extData[2] = {0}; + uint8_t srlCfgPayload = 0; + uint8_t armData[2] = {0}; + uint8_t cmdStatusByte = 0; + int32_t errHdl = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check statisticsReadBack pointer is not NULL*/ + ADI_NULL_PTR_RETURN(&device->common, + statisticsReadBack); + + switch (txChannel) + { + case ADI_ADRV9025_TX1: + txChannelBaseAddr = ADRV9025_BF_TX_CH0; + break; + case ADI_ADRV9025_TX2: + txChannelBaseAddr = ADRV9025_BF_TX_CH1; + break; + case ADI_ADRV9025_TX3: + txChannelBaseAddr = ADRV9025_BF_TX_CH2; + break; + case ADI_ADRV9025_TX4: + txChannelBaseAddr = ADRV9025_BF_TX_CH3; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Error while accessing selected Tx channel - Supported values TX1-TX2-TX3-TX4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_TxSrlStatEnBfGet(device, + txChannelBaseAddr, + &statsEnabled); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while attempting to read SRL stats enabled status of selected Tx channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (statsEnabled == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + statsEnabled, + "SRL statistics are not enabled for selected Tx channel, please enable statistics before reading. "); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + clearStats = (clearStats == 0) ? ADI_FALSE : ADI_TRUE; + + /*Read statistics from FW through mailbox */ + + /* Command ARM to return the statistics */ + srlCfgPayload = (uint8_t)txChannel; + if (clearStats == ADI_TRUE) + { + srlCfgPayload |= clrBitPositionInPayload; + } + + extData[0] = ADRV9025_CPU_OBJECTID_SRL_STATISTICS; + extData[1] = srlCfgPayload; + recoveryAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Cannot write ARM command to set SRL statistics"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_GET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_GETSRLSTATS_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_GETSRLSTATS_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte >> ARM_ERR_SHIFT) > 0) + { + recoveryAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Cannot wait Arm Command Status"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read SRL configuration from mailbox */ + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + ADI_TRUE); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Slr statistics MSB on mailboxGetBuf[0] and LSB on mailboxGetBuf[1] */ + *statisticsReadBack = ((uint16_t)armData[0] << 8) | (uint16_t)armData[1]; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SrlCfgSet(adi_adrv9025_Device_t* device, + adi_adrv9025_SlewRateLimiterCfg_t slewRateLimiterCfg) +{ + static const uint8_t MAX_SLEW_RATE_OFFSET = 0x0F; + static const uint8_t SRL_CONFIG_MODE_BITS_SHIFT = 4; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t channelLoop = 0; + uint8_t j = 0; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + uint8_t extData[2] = {0}; + uint8_t cmdStatusByte = 0; + int32_t errHdl = 0; + uint8_t srlCfgPayload = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* checking channel mask validity */ + channelLoop = slewRateLimiterCfg.txChannelMask; + if ((channelLoop == 0) || ((channelLoop & ~ADI_ADRV9025_TXALL) > 0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + slewRateLimiterCfg.txChannelMask, + "Slew rate limiter txChannelMask value is invalid."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* checking slew rate limitation */ + if ((device->devStateInfo.txSrlRateInvalidMask & ADI_ADRV9025_TXALL) > 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + device->devStateInfo.txSrlRateInvalidMask, + "Slew rate limiter rate value is invalid."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (slewRateLimiterCfg.srlOffset > MAX_SLEW_RATE_OFFSET) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + slewRateLimiterCfg.srlOffset, + "Slew rate limiter offset value is over max value which is: 0x0F"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check that the requested mode is valid */ + if ((slewRateLimiterCfg.modeSel != ADI_ADRV9025_SRL_DISABLED) && + (slewRateLimiterCfg.modeSel != ADI_ADRV9025_SRL_BASIC) && + (slewRateLimiterCfg.modeSel != ADI_ADRV9025_SRL_RAMP_DOWN) && + (slewRateLimiterCfg.modeSel != ADI_ADRV9025_SRL_RAMP_DOWN_WITH_BBIC_INTERRUPT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + slewRateLimiterCfg.modeSel, + "Invalid mode selection for Slew rate limiter. Valid modes are DISABLED/BASIC/RAMPDOWN/RAMPDOWNWITHBBICINTERRUPT."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Check that the requested mode is valid */ + if ((slewRateLimiterCfg.tableSel != ADI_ADRV9025_SRL_TABLE0) && + (slewRateLimiterCfg.tableSel != ADI_ADRV9025_SRL_TABLE1) && + (slewRateLimiterCfg.tableSel != ADI_ADRV9025_SRL_TABLE2) && + (slewRateLimiterCfg.tableSel != ADI_ADRV9025_SRL_TABLE3)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + slewRateLimiterCfg.tableSel, + "Invalid table selection for Slew rate limiter. Valid tables are TABLE0-1-2-3."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Write configuration */ + channelLoop = slewRateLimiterCfg.txChannelMask; + for (j = 0; j < ADI_ADRV9025_MAX_TXCHANNELS; j++) + { + if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX1)) + { + txChannelBaseAddr = ADRV9025_BF_TX_CH0; + channelLoop = channelLoop & ~ADI_ADRV9025_TX1; + srlCfgPayload |= ADI_ADRV9025_TX1; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX2)) + { + txChannelBaseAddr = ADRV9025_BF_TX_CH1; + channelLoop = channelLoop & ~ADI_ADRV9025_TX2; + srlCfgPayload |= ADI_ADRV9025_TX2; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX3)) + { + txChannelBaseAddr = ADRV9025_BF_TX_CH2; + channelLoop = channelLoop & ~ADI_ADRV9025_TX3; + srlCfgPayload |= ADI_ADRV9025_TX3; + } + else if (ADRV9025_BF_EQUAL(channelLoop, + ADI_ADRV9025_TX4)) + { + txChannelBaseAddr = ADRV9025_BF_TX_CH3; + channelLoop = channelLoop & ~ADI_ADRV9025_TX4; + srlCfgPayload |= ADI_ADRV9025_TX4; + } + else if (channelLoop == 0) + { + /* All channels are set up */ + break; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + slewRateLimiterCfg.txChannelMask, + "Error while accessing selected Tx channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_TxSrlTableSelBfSet(device, + txChannelBaseAddr, + (uint8_t)slewRateLimiterCfg.tableSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while writing SRL table selection for selected Tx channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxSrlSlewOffsetBfSet(device, + txChannelBaseAddr, + slewRateLimiterCfg.srlOffset); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while writing SRL offset for selected Tx channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Command ARM to set rest of the configuration for slew rate limiter of selected Tx channel */ + srlCfgPayload |= ((uint8_t)slewRateLimiterCfg.modeSel << SRL_CONFIG_MODE_BITS_SHIFT); + extData[0] = ADRV9025_CPU_OBJECTID_SRL_CONFIG; + extData[1] = srlCfgPayload; + + recoveryAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_SET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Cannot write ARM command to set SRL configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_SET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_SETSRLCONFIG_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_SETSRLCONFIG_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte >> 1) > 0) + { + recoveryAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Cannot wait Arm Command Status"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Clear payload byte for next loop */ + srlCfgPayload = 0; + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SrlCfgGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + adi_adrv9025_SlewRateLimiterCfg_t* slewRateLimiterCfg) +{ + static const uint8_t SRL_CONFIG_MODE_BITS_SHIFT = 4; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adrv9025_BfTxChanAddr_e txChannelBaseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + uint8_t extData[2] = {0}; + uint8_t armData[1] = {0}; + uint8_t cmdStatusByte = 0; + int32_t errHdl = 0; + uint8_t srlCfgPayload = 0; + uint8_t modeSel = 0; + uint8_t tableSel = 0; + uint8_t srlOffset = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check slewRateLimiterCfg pointer is not NULL*/ + ADI_NULL_PTR_RETURN(&device->common, + slewRateLimiterCfg); + + /* Check that the requested mode is valid */ + if ((txChannel != ADI_ADRV9025_TX1) && + (txChannel != ADI_ADRV9025_TX2) && + (txChannel != ADI_ADRV9025_TX3) && + (txChannel != ADI_ADRV9025_TX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + slewRateLimiterCfg.modeSel, + "Invalid Tx Channel. Valid values are Tx1/Tx2/Tx3/Tx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + txChannelBaseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + (uint32_t)txChannel); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxSrlTableSelBfGet(device, + txChannelBaseAddr, + &tableSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while reading SRL table selection for selected Tx channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_TxSrlSlewOffsetBfGet(device, + txChannelBaseAddr, + &srlOffset); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Error while reading SRL offset for selected Tx channel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Command ARM to return the currently assigned GPIO for the requested signal ID */ + srlCfgPayload = (uint8_t)txChannel; + extData[0] = ADRV9025_CPU_OBJECTID_SRL_CONFIG; + extData[1] = srlCfgPayload; + recoveryAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Cannot write ARM command to get SRL configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_GET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_GETSRLCONFIG_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_GETSRLCONFIG_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte >> 1) > 0) + { + recoveryAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_GET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Cannot wait Arm Command Status"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read SRL configuration from mailbox */ + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + ADI_TRUE); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Check whether channel mask is same for both command and readBack bytes */ + if (!ADRV9025_BF_EQUAL(armData[0], + srlCfgPayload)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + srlCfgPayload, + "There is a mismatch between channel masks sent and read back from mail box, configuration which is read, will be ignored."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + modeSel = armData[0] >> SRL_CONFIG_MODE_BITS_SHIFT; + + slewRateLimiterCfg->modeSel = (adi_adrv9025_SrlModeSel_e)modeSel; + slewRateLimiterCfg->srlOffset = srlOffset; + slewRateLimiterCfg->tableSel = (adi_adrv9025_SrlTableSel_e)tableSel; + slewRateLimiterCfg->txChannelMask = (uint32_t)txChannel; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SrlRampTimerSet(adi_adrv9025_Device_t* device, + uint32_t timerMicroSec) +{ + static const uint32_t RAMP_TIMER_MIN = 80; // 80 microseconds + static const uint32_t RAMP_TIMER_MAX = 5000000; // 5 seconds + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t timerData[5] = {0}; + uint8_t cmdStatusByte = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + if ((timerMicroSec < RAMP_TIMER_MIN) || (timerMicroSec > RAMP_TIMER_MAX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + timerMicroSec, + "Ramp timer value is out of range (80 usec -- 5000000 usec)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Writing SRL timer value to ARM */ + timerData[0] = 4; + timerData[1] = timerMicroSec & 0xFF; + timerData[2] = (timerMicroSec >> 8) & 0xFF; + timerData[3] = (timerMicroSec >> 16) & 0xFF; + timerData[4] = (timerMicroSec >> 24) & 0xFF; + /* Write to the ARM Mem */ + recoveryAction = adi_adrv9025_CpuMemWrite(device, + ADRV9025_CPU_C_ADDR_MAILBOX_SET, + &timerData[0], + sizeof(timerData), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "timerValue failed writing ARM memory"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Notify ARM: ARM Object id, byte offset LSB, offset MSB = 0, copy 2 bytes */ + timerData[0] = ADRV9025_CPU_OBJECTID_CONFIG; + timerData[1] = ADRV9025_CPU_OBJECTID_SYSTEM_INFO; + timerData[2] = 0; + timerData[3] = 0; + timerData[4] = 0; + + adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_SET_OPCODE, + &timerData[0], + 4); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "ARM command failed to set SRL timer value configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_SET_OPCODE, + &cmdStatusByte, + ADI_ADRV9025_WRITECPUCFG_TIMEOUT_US, + ADI_ADRV9025_READCPUCFG_TIMEOUT_US); + + if ((cmdStatusByte >> 1) > 0) + { + recoveryAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + ADI_ADRV9025_SRC_CPUCMD, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Cannot wait Arm Command Status"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_SrlRampTimerGet(adi_adrv9025_Device_t* device, + uint32_t* timerMicroSec) +{ + static const uint8_t ARM_MEM_READ_AUTOINCR = 1; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t timerData[4] = {0}; + uint8_t cmdStatusByte = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check timerMicroSec pointer is not NULL*/ + ADI_NULL_PTR_RETURN(&device->common, + timerMicroSec); + + /* Notify ARM for how many byte to read */ + timerData[0] = 4; + timerData[1] = 0; + timerData[2] = 0; + timerData[3] = 0; + recoveryAction = adi_adrv9025_CpuMemWrite(device, + ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &timerData[0], + 1, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "timerValue failed writing ARM memory"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Notify ARM for reading timer value */ + timerData[0] = ADRV9025_CPU_OBJECTID_CONFIG; + timerData[1] = ADRV9025_CPU_OBJECTID_SYSTEM_INFO; + timerData[2] = 0; + timerData[3] = 0; + + recoveryAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &timerData[0], + sizeof(timerData)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + timerData, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_GET_OPCODE, + &cmdStatusByte, + ADI_ADRV9025_WRITECPUCFG_TIMEOUT_US, + ADI_ADRV9025_READCPUCFG_TIMEOUT_US); + if ((cmdStatusByte >> 1) > 0) + { + recoveryAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + ADI_ADRV9025_SRC_CPUCMD, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + ADRV9025_CPU_OBJECTID_CONFIG, + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Cannot wait Arm Command Status"); + ADI_ERROR_RETURN(device->common.error.newAction); + + timerData[0] = 0; + timerData[1] = 0; + timerData[2] = 0; + timerData[3] = 0; + + /* Read the timerValue per channel */ + recoveryAction = adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &timerData[0], + sizeof(timerData), + ARM_MEM_READ_AUTOINCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "ARM command failed to read SRL timer value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Deserializing Tracking Enable/Disable status (first 4 bytes) */ + *timerMicroSec = (uint32_t)(((uint32_t)timerData[0]) | + ((uint32_t)timerData[1] << 8) | + ((uint32_t)timerData[2] << 16) | + ((uint32_t)timerData[3] << 24)); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PaProtectionRampDownEnableSet(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + uint8_t enable) +{ + static const uint32_t ALL_TX_MASK = (uint32_t)ADI_ADRV9025_TX1 | (uint32_t)ADI_ADRV9025_TX2 | + (uint32_t)ADI_ADRV9025_TX3 | (uint32_t)ADI_ADRV9025_TX4; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t k = 0; + + adrv9025_BfTxChanAddr_e baseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /*Check that if requested Tx Channel valid*/ + if (((txChannelMask & (~ALL_TX_MASK)) != 0) || txChannelMask == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannelMask, + "Invalid Tx Channel is selected to enable/disable ramp-down. Valid values are different combinations of TX1-2-3-4."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + enable = (enable == 0) ? ADI_FALSE : ADI_TRUE; + + for (k = 0; k < ADI_ADRV9025_MAX_TXCHANNELS; k++) + { + if (ADRV9025_BF_EQUAL(txChannelMask, + ((uint32_t)1 << (uint32_t)k))) + { + if ((baseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + ((uint32_t)1 << (uint32_t)k))) == (adrv9025_BfTxChanAddr_e)0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_TxPaProtectionGainRampDownEnBfSet(device, + baseAddr, + enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + enable, + "Could not enable/disable ramp-down for pa protection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PaProtectionRampDownEnableGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannelSelect, + uint8_t* enable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t readVal = 0; + adrv9025_BfTxChanAddr_e baseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that if eventBits pointer is not NULL */ + ADI_NULL_PTR_RETURN(&device->common, + enable); + + /* Check that if requested Tx Channel is valid */ + if ((txChannelSelect != ADI_ADRV9025_TX1) && + (txChannelSelect != ADI_ADRV9025_TX2) && + (txChannelSelect != ADI_ADRV9025_TX3) && + (txChannelSelect != ADI_ADRV9025_TX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannelSelect, + "Invalid Tx Channel is selected to read pa protection ramp down enable bit. Valid values are TX1-2-3-4."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((baseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + (uint32_t)txChannelSelect)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_TxPaProtectionGainRampDownEnBfGet(device, + baseAddr, + &readVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while reading pa protection ramp down enable bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *enable = readVal; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PaProtectionRampUpEnableSet(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + uint8_t enable) +{ + static const uint32_t ALL_TX_MASK = (uint32_t)ADI_ADRV9025_TX1 | (uint32_t)ADI_ADRV9025_TX2 | + (uint32_t)ADI_ADRV9025_TX3 | (uint32_t)ADI_ADRV9025_TX4; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t k = 0; + + adrv9025_BfTxChanAddr_e baseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /*Check that if requested Tx Channel valid*/ + if (((txChannelMask & (~ALL_TX_MASK)) != 0) || txChannelMask == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannelMask, + "Invalid Tx Channel is selected to enable/disable ramp-up. Valid values are different combinations of TX1-2-3-4."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + enable = (enable == 0) ? ADI_FALSE : ADI_TRUE; + + for (k = 0; k < ADI_ADRV9025_MAX_TXCHANNELS; k++) + { + if (ADRV9025_BF_EQUAL(txChannelMask, + ((uint32_t)1 << (uint32_t)k))) + { + if ((baseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + ((uint32_t)1 << (uint32_t)k))) == (adrv9025_BfTxChanAddr_e)0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_TxPaProtectionGainRampUpEnBfSet(device, + baseAddr, + enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + enable, + "Could not enable/disable ramp-up for pa protection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PaProtectionRampUpEnableGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannelSelect, + uint8_t* enable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t readVal = 0; + adrv9025_BfTxChanAddr_e baseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that if eventBits pointer is not NULL */ + ADI_NULL_PTR_RETURN(&device->common, + enable); + + /* Check that if requested Tx Channel is valid */ + if ((txChannelSelect != ADI_ADRV9025_TX1) && + (txChannelSelect != ADI_ADRV9025_TX2) && + (txChannelSelect != ADI_ADRV9025_TX3) && + (txChannelSelect != ADI_ADRV9025_TX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannelSelect, + "Invalid Tx Channel is selected to read pa protection ramp up enable bit. Valid values are TX1-2-3-4."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((baseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + (uint32_t)txChannelSelect)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_TxPaProtectionGainRampUpEnBfGet(device, + baseAddr, + &readVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while reading pa protection ramp up enable bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *enable = readVal; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxNcoShifterSet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxNcoShifterCfg_t shifterCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t extData[2] = {ADRV9025_CPU_OBJECTID_TX_NCO, 0}; + uint8_t armData[5] = {0, 0, 0, 0, 0}; + uint8_t cmdStatusByte = 0u; + int32_t errHdl = 0; + static const uint8_t ARM_ERR_CODE = 0x0E; + static const uint8_t SHIFT_ONE_BYTE = 8; + static const uint8_t SHIFT_TWO_BYTES = 16; + static const uint8_t SHIFT_THREE_BYTES = 24; + static const uint8_t SHIFT_6_BITS = 6; + static const uint8_t SHIFT_7_BITS = 7; + static const uint8_t TXCHANNELMASK = 0x0F; + static const uint32_t BYTE_0 = 0x000000FF; + static const uint32_t BYTE_1 = 0x0000FF00; + static const uint32_t BYTE_2 = 0x00FF0000; + static const uint32_t BYTE_3 = 0xFF000000; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + extData[1] = ((shifterCfg.enable) << SHIFT_7_BITS) | (((uint8_t)(shifterCfg.shifterMode)) << SHIFT_6_BITS) | (shifterCfg.txChannelMask & TXCHANNELMASK); + + shifterCfg.shiftFrequency_kHz = shifterCfg.shiftFrequency_kHz * 1000; + armData[0] = shifterCfg.shiftFrequency_kHz & BYTE_0; + armData[1] = (shifterCfg.shiftFrequency_kHz & BYTE_1) >> SHIFT_ONE_BYTE; + armData[2] = (shifterCfg.shiftFrequency_kHz & BYTE_2) >> SHIFT_TWO_BYTES; + armData[3] = (shifterCfg.shiftFrequency_kHz & BYTE_3) >> SHIFT_THREE_BYTES; + armData[4] = (uint8_t)shifterCfg.shiftGain; + + /* Write offset and size to ARM mailbox */ + recoveryAction = adi_adrv9025_CpuMemWrite(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_SET, + &armData[0], + sizeof(armData), + ADI_TRUE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + armData, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Executing Arm Command */ + recoveryAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_SET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + extData, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_SET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_SETDEFAULTCONDITION_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_SETDEFAULTCONDITION_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte & ARM_ERR_CODE) > 0) + { + recoveryAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + cmdStatusByte, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxNcoShifterGet(adi_adrv9025_Device_t *device, + adi_adrv9025_TxNcoShifterCfg_t *shifterCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t extData[2] = {ADRV9025_CPU_OBJECTID_TX_NCO, 0}; + uint8_t armData[8] = {0, 0, 0, 0, 0, 0, 0, 0}; + uint8_t cmdStatusByte = 0u; + int32_t errHdl = 0; + static const uint8_t ARM_ERR_CODE = 0x0E; + static const uint8_t AUTO_INC = 1; + static const uint8_t SHIFT_ONE_BYTE = 0x08; + static const uint8_t SHIFT_4_BITS = 0x04; + static const uint8_t SHIFT_7_BITS = 0x07; + static const uint8_t NCO_ENABLE = 0x80; + static const uint8_t NCO_MODE = 0x10; + static const uint8_t TXCHANNELMASK = 0x0F; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, shifterCfg); + + extData[1] = (shifterCfg->txChannelMask & 0x0F); + + /* Executing Arm Command */ + recoveryAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_GET_OPCODE, + &extData[0], + sizeof(extData)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + extData, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Wait for command to finish executing */ + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + (uint8_t)ADRV9025_CPU_GET_OPCODE, + &cmdStatusByte, + (uint32_t)ADI_ADRV9025_SETDEFAULTCONDITION_TIMEOUT_US, + (uint32_t)ADI_ADRV9025_SETDEFAULTCONDITION_INTERVAL_US); + + /* If cmdStatusByte is non-zero then flag an ARM error */ + if ((cmdStatusByte & ARM_ERR_CODE) > 0) + { + recoveryAction = adrv9025_CpuCmdErrorHandler(device, + ADI_ADRV9025_CPU_TYPE_C, + errHdl, + ADRV9025_CPU_CMD_ERRCODE(ADRV9025_CPU_SET_OPCODE, + extData[0], + cmdStatusByte), + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + cmdStatusByte, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read the Tx NCO Configuration */ + adi_adrv9025_CpuMemRead(device, + (uint32_t)ADRV9025_CPU_C_ADDR_MAILBOX_GET, + &armData[0], + sizeof(armData), + AUTO_INC); + ADI_ERROR_RETURN(device->common.error.newAction); + + shifterCfg->txChannelMask = armData[0] & TXCHANNELMASK; + shifterCfg->shifterMode = (adi_adrv9025_TxNcoShifterMode_e)((armData[0] & NCO_MODE) >> SHIFT_4_BITS); + shifterCfg->enable = ((armData[0] & NCO_ENABLE) >> SHIFT_7_BITS); + shifterCfg->shiftGain = (adi_adrv9025_TxNcoToneGain_e)(armData[1]); + shifterCfg->shiftFrequency_kHz = armData[7]; + shifterCfg->shiftFrequency_kHz = (shifterCfg->shiftFrequency_kHz << SHIFT_ONE_BYTE) | armData[6]; + shifterCfg->shiftFrequency_kHz = (shifterCfg->shiftFrequency_kHz << SHIFT_ONE_BYTE) | armData[5]; + shifterCfg->shiftFrequency_kHz = (shifterCfg->shiftFrequency_kHz << SHIFT_ONE_BYTE) | armData[4]; + shifterCfg->shiftFrequency_kHz = shifterCfg->shiftFrequency_kHz / 1000; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxAnalogAttenEarlyDelaySet(adi_adrv9025_Device_t* device, + uint32_t txChannelMask, + uint8_t delayValue) +{ + static const uint32_t ALL_TX_MASK = (uint32_t)ADI_ADRV9025_TX1 | (uint32_t)ADI_ADRV9025_TX2 | + (uint32_t)ADI_ADRV9025_TX3 | (uint32_t)ADI_ADRV9025_TX4; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t k = 0; + + adrv9025_BfTxChanAddr_e baseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /*Check that if requested Tx Channel valid*/ + if (((txChannelMask & ~ALL_TX_MASK) != 0) || (txChannelMask == 0)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannelMask, + "Invalid Tx Channel is selected for Tx atten early delay. Valid values are different combinations of TX1-2-3-4."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (k = 0; k < ADI_ADRV9025_MAX_TXCHANNELS; k++) + { + if (ADRV9025_BF_EQUAL(txChannelMask, + ((uint32_t)1 << (uint32_t)k))) + { + if ((baseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + ((uint32_t)1 << (uint32_t)k))) == (adrv9025_BfTxChanAddr_e)0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_TxTxAttenuationEarlyDelayCounterForAnalogBfSet(device, + baseAddr, + delayValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + enable, + "Could not set Tx analog atten early delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxAnalogAttenEarlyDelayGet(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannelSelect, + uint8_t* delayValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t readVal = 0; + adrv9025_BfTxChanAddr_e baseAddr = ADRV9025_BF_ALL_TX_CHANNELS; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that if eventBits pointer is not NULL */ + ADI_NULL_PTR_RETURN(&device->common, + delayValue); + + /* Check that if requested Tx Channel is valid */ + if ((txChannelSelect != ADI_ADRV9025_TX1) && + (txChannelSelect != ADI_ADRV9025_TX2) && + (txChannelSelect != ADI_ADRV9025_TX3) && + (txChannelSelect != ADI_ADRV9025_TX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannelSelect, + "Invalid Tx Channel is selected to read Tx analog atten early delay. Valid values are TX1-2-3-4."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((baseAddr = (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + (uint32_t)txChannelSelect)) == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adrv9025_TxTxAttenuationEarlyDelayCounterForAnalogBfGet(device, + baseAddr, + &readVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error while reading Tx analog atten early delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + *delayValue = readVal; + + return device->common.error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_utilities.c b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_utilities.c new file mode 100644 index 0000000..1f14449 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/adrv9025/public/src/adi_adrv9025_utilities.c @@ -0,0 +1,3813 @@ +/** +* \file adi_adrv9025_utilities.c +* \brief Contains Utility features related function implementation defined in +* adi_adrv9025_utilities.h +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_adrv9025_user.h" +#include "adi_adrv9025_utilities.h" +#include "adi_adrv9025_error.h" +#include "adi_adrv9025_hal.h" +#include "adi_adrv9025_rx.h" +#include "adi_adrv9025_cpu.h" +#include "adi_adrv9025_tx.h" +#include "adi_adrv9025_radioctrl.h" +#include "adi_adrv9025_data_interface.h" +#include "adi_adrv9025_cals.h" +#include "adi_adrv9025_cals_types.h" +#include "adi_adrv9025_gpio.h" +#include "adi_adrv9025_arm.h" +#include "../../private/include/adrv9025_utilities.h" +#include "../../private/include/adrv9025_init.h" +#include "../../private/include/adrv9025_tx.h" +#include "../../private/include/adrv9025_cpu.h" +#include "../../private/include/adrv9025_gpio.h" +#include "../../private/include/adrv9025_cpu_macros.h" +#include "../../private/include/adrv9025_bf_hal.h" +#include "../../private/include/adrv9025_crc32.h" + +#ifdef _RELEASE_BUILD_ + #line __LINE__ "adi_adrv9025_utilities.c" +#endif + +#define ADI_ADRV9025_CPU_C_BINARY_IMAGE_FILE_SIZE_BYTES (7*32*1024u) /* 7 blocks of 32kB memory */ +#define ADI_ADRV9025_CPU_D_BINARY_IMAGE_FILE_SIZE_BYTES (3*32*1024u) /* 3 blocks of 32kB memory */ +#define ADI_ADRV9025_STREAM_BINARY_IMAGE_FILE_SIZE_BYTES (22*1024) +#define ADI_ADRV9025_RX_GAIN_TABLE_SIZE_ROWS 256 +#define ADI_ADRV9025_TX_ATTEN_TABLE_SIZE_ROWS 1024 + +#if (OS_Windows == 64) && (_LABVIEW_INSTALLED != 0) + +int32_t adi_adrv9025_ArmImageLoad(adi_adrv9025_Device_t *device, const char *armImagePath) +{ + return adi_adrv9025_CpuImageLoad(device, armImagePath);; +} + +int32_t adi_adrv9025_CpuImageLoad(adi_adrv9025_Device_t *device, const char *fwImagePaths) +{ + static const size_t BIN_ELEMENT_SIZE = 1; + + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + FILE *fwImageFilePointer = NULL; + uint32_t fileSize = 0; + //TODO: Load in smaller chunks + static uint8_t fwBinaryImageBuffer[ADI_ADRV9025_CPU_C_BINARY_IMAGE_FILE_SIZE_BYTES]; + uint32_t i = 0; + char paths[ADRV9025_MAX_CPUS][ADRV9025_MAX_CPU_FW_PATH] = { { 0 } }; + const char *temp = NULL; + uint32_t len1 = 0u; + uint32_t len2 = 0u; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + /* the paths might contain 2 paths separated by semi colon, + * the first one should be for cpu-c and the second one, + * if exists, is for the 2nd cpu-d */ + if ((temp = strchr(fwImagePaths, ADRV9025_CPU_FW_PATH_SEP)) == NULL) + { + strncpy(paths[0], fwImagePaths, ADRV9025_MAX_CPU_FW_PATH - 1u); + paths[1][0] = 0u; + } + else + { + len1 = (uint32_t)(temp - fwImagePaths); + len2 = (uint32_t)(strlen(temp + 1u)); + strncpy(paths[0], fwImagePaths, (len1 > ADRV9025_MAX_CPU_FW_PATH) ? ADRV9025_MAX_CPU_FW_PATH : len1); + strncpy(paths[1], temp + 1u, (len2 > ADRV9025_MAX_CPU_FW_PATH) ? ADRV9025_MAX_CPU_FW_PATH : len2); + } + paths[0][ADRV9025_MAX_CPU_FW_PATH - 1u] = 0u; + paths[1][ADRV9025_MAX_CPU_FW_PATH - 1u] = 0u; + + for (i = 0; i < ADRV9025_MAX_CPUS; i++) + { + char *fwImagePath = paths[i]; + + /*Open FW binary file*/ +#ifdef __GNUC__ + fwImageFilePointer = fopen(fwImagePath, "rb"); +#else + if (fopen_s(&fwImageFilePointer, fwImagePath, "rb") != 0) + { + if (i == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fwImagePath, + "Unable to open CPU FW binary image file. Please check if the path is correct"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + continue; + } + } +#endif + + if (fwImageFilePointer == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fwImagePath, + "Invalid CPU FW binary image path encountered while attempting to load CPU FW binary image"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Determine file size*/ + if (fseek(fwImageFilePointer, 0, SEEK_END) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fwImageFilePointer, + "Unable to move file descriptor to the end of the CPU FW binary image file"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, fwImageFilePointer); + } + + fileSize = ftell(fwImageFilePointer); + + /*Check that FW binary file is not empty*/ + if (fileSize == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fwImagePath, + "Empty FW binary image file encountered while attempting to load FW binary image"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, fwImageFilePointer); + } + + /*Check that FW binary file size does not exceed maximum size*/ + if (fileSize > (((adi_adrv9025_CpuType_e)i == ADI_ADRV9025_CPU_TYPE_C) ? ADI_ADRV9025_CPU_C_BINARY_IMAGE_FILE_SIZE_BYTES : ADI_ADRV9025_CPU_D_BINARY_IMAGE_FILE_SIZE_BYTES)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fwImagePath, + "FW binary image file exceeds maximum FW binary image size"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, fwImageFilePointer); + } + + /*Check that size of the file is a multiple of 4*/ + if ((fileSize % 4) != 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fwImagePath, + "FW binary image file is expected to be a multiple of 4"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, fwImageFilePointer); + } + + /*Rewind the file pointer to beginning of the file*/ + if (fseek(fwImageFilePointer, 0, SEEK_SET) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fwImageFilePointer, + "Unable to move file descriptor to the beginning of the FW binary image file"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, fwImageFilePointer); + } + + /*Read FW binary file*/ + if (fread(&fwBinaryImageBuffer[0], BIN_ELEMENT_SIZE, fileSize, fwImageFilePointer) < fileSize) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fwImagePath, + "Fatal error while reading FW binary file. Possible memory shortage"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, fwImageFilePointer); + } + + /*Write the FW binary*/ + retVal = adi_adrv9025_CpuImageWrite(device, (adi_adrv9025_CpuType_e)i, 0, &fwBinaryImageBuffer[0], fileSize); + + /*Close FW binary file*/ + if (fclose(fwImageFilePointer) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armImagePath, + "Fatal error while trying to close FW binary file. Possible memory shortage while flushing / other I/O errors."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return retVal; +} + +int32_t adi_adrv9025_StreamImageLoad(adi_adrv9025_Device_t *device, const char *streamImagePath) +{ + static const size_t BIN_ELEMENT_SIZE = 1; + + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + FILE *streamImageFilePointer = NULL; + uint32_t fileSize = 0; + //TODO: Load in smaller chunks + static uint8_t streamBinaryImageBuffer[ADI_ADRV9025_STREAM_BINARY_IMAGE_FILE_SIZE_BYTES]; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + /*Open ARM binary file*/ +#ifdef __GNUC__ + streamImageFilePointer = fopen(streamImagePath, "rb"); +#else + if (fopen_s(&streamImageFilePointer, streamImagePath, "rb") != 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, streamImagePath, + "Unable to open stream binary image file. Please check if the path is correct"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + if (streamImageFilePointer == NULL) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, streamImagePath, + "Invalid Stream binary image path encountered while attempting to load Stream processor"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Determine file size*/ + if (fseek(streamImageFilePointer, 0, SEEK_END) < 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, streamImageFilePointer, + "Unable to move file descriptor to the end of the stream binary image file"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, streamImageFilePointer); + } + + fileSize = ftell(streamImageFilePointer); + + /*Check that Stream binary file is not empty*/ + if (fileSize == 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, streamImagePath, + "Empty Stream binary image file encountered while attempting to load the Stream processor"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, streamImageFilePointer); + } + + /*Check that Stream binary file size does not exceed maximum size*/ + if (fileSize > ADI_ADRV9025_STREAM_BINARY_IMAGE_FILE_SIZE_BYTES) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, streamImagePath, + "Stream binary image file exceeds maximum Stream binary image size"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, streamImageFilePointer); + } + + /*Check that size of the file is a multiple of 4*/ + if ((fileSize % 4) != 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, streamImagePath, + "Stream binary image file is expected to be a multiple of 4"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, streamImageFilePointer); + } + + /*Rewind the file pointer to beginning of the file*/ + if (fseek(streamImageFilePointer, 0, SEEK_SET) < 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, streamImageFilePointer, + "Unable to move file descriptor to the beginning of the stream binary image file"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, streamImageFilePointer); + } + + /*Read Stream binary file*/ + if (fread(&streamBinaryImageBuffer[0], BIN_ELEMENT_SIZE, fileSize, streamImageFilePointer) < fileSize) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, streamImagePath, + "Fatal error while reading stream binary file. Possible memory shortage"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, streamImageFilePointer); + } + + /*Write Stream binary*/ + retVal = adi_adrv9025_StreamImageWrite(device, 0, &streamBinaryImageBuffer[0], fileSize); + + /*Close Stream binary file*/ + if (fclose(streamImageFilePointer) < 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, streamImagePath, + "Fatal error while trying to close stream binary file. Possible memory shortage while flushing / other I/O errors."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + + return retVal; +} + +#else + +int32_t adi_adrv9025_ArmImageLoad(adi_adrv9025_Device_t* device, + const char* armImagePath) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, armImagePath); + + return adi_adrv9025_CpuImageLoad(device, + armImagePath); +} + +int32_t adi_adrv9025_CpuImageLoad(adi_adrv9025_Device_t* device, + const char* fwImagePaths) +{ + static const size_t BIN_ELEMENT_SIZE = 1; + + FILE* fwImageFilePointer = NULL; + uint32_t fileSize = 0; + uint32_t numFileChunks = 0; + uint32_t i = 0; + uint32_t j = 0; + uint8_t armBinaryImageBuffer[ADI_ADRV9025_CPU_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES]; + char paths[ADRV9025_MAX_CPUS][ADRV9025_MAX_CPU_FW_PATH] = {{0}}; + const char* temp = NULL; + uint32_t len1 = 0u; + uint32_t len2 = 0u; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* the paths might contain 2 paths separated by semi colon, + * the first one should be for cpu-c and the second one, + * if exists, is for the 2nd cpu-d */ + if ((temp = strchr(fwImagePaths, + ADRV9025_CPU_FW_PATH_SEP)) == NULL) + { + strncpy(paths[0], + fwImagePaths, + ADRV9025_MAX_CPU_FW_PATH - 1u); + paths[1][0] = 0u; + } + else + { + len1 = temp - fwImagePaths; + len2 = strlen(temp + 1u); + strncpy(paths[0], + fwImagePaths, + (len1 > ADRV9025_MAX_CPU_FW_PATH) ? ADRV9025_MAX_CPU_FW_PATH : len1); + strncpy(paths[1], + temp + 1u, + (len2 > ADRV9025_MAX_CPU_FW_PATH) ? ADRV9025_MAX_CPU_FW_PATH : len2); + } + paths[0][ADRV9025_MAX_CPU_FW_PATH - 1u] = 0u; + paths[1][ADRV9025_MAX_CPU_FW_PATH - 1u] = 0u; + + for (j = 0; j < ADRV9025_MAX_CPUS; j++) + { + char* fwImagePath = paths[j]; + + /*Open ARM binary file*/ +#ifdef __GNUC__ + fwImageFilePointer = fopen(fwImagePath, + "rb"); +#else + if (fopen_s(&fwImageFilePointer, fwImagePath, "rb") != 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, fwImagePath, + "Unable to open FW binary image file. Please check if the path is correct"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + if (fwImageFilePointer == NULL) + { + if (j == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fwImagePath, + "Invalid FW binary image path encountered while attempting to load FW binary image"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + continue; + } + } + + /*Determine file size*/ + if (fseek(fwImageFilePointer, + 0, + SEEK_END) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armImageFilePointer, + "Unable to move file descriptor to the end of the ARM binary image file"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + fwImageFilePointer); + } + + fileSize = ftell(fwImageFilePointer); + numFileChunks = (uint32_t)(fileSize / ADI_ADRV9025_CPU_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES); + + /*Check that FW binary file is not empty*/ + if (fileSize == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fwImagePath, + "Empty FW binary image file encountered while attempting to load FW binary image"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + fwImageFilePointer); + } + + /*Check that FW binary file size does not exceed maximum size*/ + if (fileSize > (((adi_adrv9025_CpuType_e)j == ADI_ADRV9025_CPU_TYPE_C) ? ADI_ADRV9025_CPU_C_BINARY_IMAGE_FILE_SIZE_BYTES + : ADI_ADRV9025_CPU_D_BINARY_IMAGE_FILE_SIZE_BYTES)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fwImagePath, + "FW binary image file exceeds maximum FW binary image size"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + fwImageFilePointer); + } + + /*Check that size of the file is a multiple of 4*/ + if ((fileSize % 4) != 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fwImagePath, + "FW binary image file is expected to be a multiple of 4"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + fwImageFilePointer); + } + + /*Check that size of the file is divisible into equal sized chunks*/ + if ((fileSize % ADI_ADRV9025_CPU_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES) != 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fwImagePath, + "FW binary image chunk size is expected to divide the stream file into equal chunks"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + fwImageFilePointer); + } + + /*Rewind the file pointer to beginning of the file*/ + if (fseek(fwImageFilePointer, + 0, + SEEK_SET) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armImageFilePointer, + "Unable to move file descriptor to the beginning of the FW binary image file"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + fwImageFilePointer); + } + + /*Read ARM binary file*/ + for (i = 0; i < numFileChunks; i++) + { + if (fread(&armBinaryImageBuffer[0], + BIN_ELEMENT_SIZE, + ADI_ADRV9025_CPU_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES, + fwImageFilePointer) < ADI_ADRV9025_CPU_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + armImagePath, + "Fatal error while reading ARM binary file. Possible memory shortage"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + fwImageFilePointer); + } + + /*Write the ARM binary chunk*/ + if ((adi_adrv9025_CpuImageWrite(device, + (adi_adrv9025_CpuType_e)j, + i * ADI_ADRV9025_CPU_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES, + &armBinaryImageBuffer[0], + ADI_ADRV9025_CPU_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES)) != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + fwImageFilePointer); + } + } + + /*Close ARM binary file*/ + if (fclose(fwImageFilePointer) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fwImagePath, + "Fatal error while trying to close FW binary file"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_StreamImageLoad(adi_adrv9025_Device_t* device, + const char* streamImagePath) +{ + static const size_t BIN_ELEMENT_SIZE = 1; + + FILE* streamImageFilePointer = NULL; + uint32_t fileSize = 0; + uint32_t numFileChunks = 0; + uint32_t i = 0; + uint8_t streamBinaryImageBuffer[ADI_ADRV9025_STREAM_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES]; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Open ARM binary file */ +#ifdef __GNUC__ + streamImageFilePointer = fopen(streamImagePath, + "rb"); +#else + if (fopen_s(&streamImageFilePointer, streamImagePath, "rb") != 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, armImagePath, + "Unable to open stream binary image file. Please check if the path is correct"); + ADI_ERROR_RETURN(device->common.error.newAction); +} +#endif + + if (streamImageFilePointer == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + streamImagePath, + "Invalid Stream binary image path encountered while attempting to load Stream processor"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Determine file size*/ + if (fseek(streamImageFilePointer, + 0, + SEEK_END) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + streamImageFilePointer, + "Unable to move file descriptor to the end of the stream binary image file"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + streamImageFilePointer); + } + + fileSize = ftell(streamImageFilePointer); + numFileChunks = (uint32_t)(fileSize / ADI_ADRV9025_STREAM_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES); + + /* Check that Stream binary file is not empty */ + if (fileSize == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + streamImagePath, + "Empty Stream binary image file encountered while attempting to load the Stream processor"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + streamImageFilePointer); + } + + /* Check that Stream binary file size does not exceed maximum size */ + if (fileSize > ADI_ADRV9025_STREAM_BINARY_IMAGE_FILE_SIZE_BYTES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + streamImagePath, + "Stream binary image file exceeds maximum Stream binary image size"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + streamImageFilePointer); + } + + /* Check that size of the file is divisible into equal sized chunks */ + if ((fileSize % numFileChunks) != 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + streamImagePath, + "Stream binary image chunk size is expected to divide the stream file into equal chunks"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + streamImageFilePointer); + } + + /* Check that size of the file is a multiple of 4 */ + if ((fileSize % 4) != 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + streamImagePath, + "Stream binary image file is expected to be a multiple of 4"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + streamImageFilePointer); + } + + /* Rewind the file pointer to beginning of the file */ + if (fseek(streamImageFilePointer, + 0, + SEEK_SET) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + streamImageFilePointer, + "Unable to move file descriptor to the beginning of the stream binary image file"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + streamImageFilePointer); + } + + /* Read Stream binary file */ + for (i = 0; i < numFileChunks; i++) + { + if (fread(&streamBinaryImageBuffer[0], + BIN_ELEMENT_SIZE, + ADI_ADRV9025_STREAM_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES, + streamImageFilePointer) < ADI_ADRV9025_STREAM_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + streamImagePath, + "Fatal error while reading stream binary file. Possible memory shortage"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + streamImageFilePointer); + } + + /* Write Stream binary */ + adi_adrv9025_StreamImageWrite(device, + (i * ADI_ADRV9025_STREAM_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES), + &streamBinaryImageBuffer[0], + ADI_ADRV9025_STREAM_BINARY_IMAGE_LOAD_CHUNK_SIZE_BYTES); + } + + /* Close Stream binary file */ + if (fclose(streamImageFilePointer) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + streamImagePath, + "Fatal error while trying to close stream binary file. Possible memory shortage while flushing / other I/O errors."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} +#endif + +int32_t adi_adrv9025_DmaMemoryRead(adi_adrv9025_Device_t* const device, + const uint32_t start_address, + uint8_t buffer[], + const uint32_t size) +{ + int32_t recoveryAction = ADI_COMMON_ACT_ERR_CHECK_PARAM; + + /* Validate Device */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + buffer); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Validate Arguments */ + if (size > 0U) /* Size has to be greater than zero */ + { + /* DMA Memory Read */ + recoveryAction = adrv9025_CpuDmaMemRead(device, + start_address, + &buffer[0], + size, + ADI_TRUE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + start_address, + "Unable to Read AHB Memory"); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + size, + "Invalid Array Size for Memory Read"); + } + + return recoveryAction; +} + +int32_t adi_adrv9025_RxGainTableLoad(adi_adrv9025_Device_t* device, + const char* rxGainTablePath, + uint32_t rxChannelMask) +{ + static const uint8_t NUM_COLUMNS = 7; +#define LINE_BUFFER_SIZE 128 +#define HEADER_BUFFER_SIZE 16 + + uint8_t minGainIndex = 0; + uint8_t maxGainIndex = 0; + uint8_t prevGainIndex = 0; + uint8_t gainIndex = 0; + uint8_t tiaControl = 0; + uint8_t adcControl = 0; + uint16_t lineCount = 0; + FILE* rxGainTableFilePointer = NULL; + char rxGainTableLineBuffer[LINE_BUFFER_SIZE]; + char headerStr1[HEADER_BUFFER_SIZE]; + char headerStr2[HEADER_BUFFER_SIZE]; + char headerStr3[HEADER_BUFFER_SIZE]; + char headerStr4[HEADER_BUFFER_SIZE]; + char headerStr5[HEADER_BUFFER_SIZE]; + char headerStr6[HEADER_BUFFER_SIZE]; + char headerStr7[HEADER_BUFFER_SIZE]; + static adi_adrv9025_RxGainTableRow_t rxGainTableRowBuffer[ADI_ADRV9025_RX_GAIN_TABLE_SIZE_ROWS]; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + rxGainTablePath); + + /*Open Rx Gain Table csv file*/ +#ifdef __GNUC__ + rxGainTableFilePointer = fopen(rxGainTablePath, + "r"); +#else + if (fopen_s(&rxGainTableFilePointer, rxGainTablePath, "r") != 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, rxGainTablePath, + "Unable to open Rx Gain Table csv file. Please check if the path is correct or the file is open in another program"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + if (rxGainTableFilePointer == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Invalid Rx Gain Table csv file path encountered while attempting to load Rx Gain Table"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check for empty Rx Gain Table*/ + if (fgets(rxGainTableLineBuffer, + sizeof(rxGainTableLineBuffer), + rxGainTableFilePointer) != NULL) + { +#ifdef __GNUC__ + if (sscanf(rxGainTableLineBuffer, + "%[^,],%[^,],%[^,],%[^,],%[^,],%[^,],%[^\n]", + headerStr1, + headerStr2, + headerStr3, + headerStr4, + headerStr5, + headerStr6, + headerStr7) != NUM_COLUMNS) +#else + if (sscanf_s(rxGainTableLineBuffer, "%[^,],%[^,],%[^,],%[^,],%[^,],%[^,],%[^\n]", headerStr1, (uint32_t)sizeof(headerStr1), + headerStr2, (uint32_t)sizeof(headerStr2), + headerStr3, (uint32_t)sizeof(headerStr3), + headerStr4, (uint32_t)sizeof(headerStr4), + headerStr5, (uint32_t)sizeof(headerStr5), + headerStr6, (uint32_t)sizeof(headerStr6), + headerStr7, (uint32_t)sizeof(headerStr7)) != NUM_COLUMNS) +#endif + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Invalid Rx Gain Table format encountered while attempting to load Rx Gain Table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + rxGainTableFilePointer); + } + + /*Verify that Gain Table Format is correct*/ + if (strstr(headerStr1, + "Gain Index") == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Expected Gain Index to be the first column in Rx gain table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + rxGainTableFilePointer); + } + + if (strstr(headerStr2, + "FE Control Word") == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Expected FE Control Word to be the second column in Rx gain table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + rxGainTableFilePointer); + } + + if (strstr(headerStr3, + "TIA Control") == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Expected TIA Control Word to be the third column in Rx gain table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + rxGainTableFilePointer); + } + + if (strstr(headerStr4, + "ADC Control") == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Expected ADC Control Word to be the fourth column in Rx gain table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + rxGainTableFilePointer); + } + + if (strstr(headerStr5, + "Ext Control") == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Expected TIA Control Word to be the fifth column in Rx gain table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + rxGainTableFilePointer); + } + + if (strstr(headerStr6, + "Phase Offset") == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Expected Phase Offset to be the sixth column in Rx gain table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + rxGainTableFilePointer); + } + + if (strstr(headerStr7, + "Digital Gain") == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Expected Digital Gain to be the seventh column in Rx gain table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + rxGainTableFilePointer); + } + + /*Loop until the gain table end is reached or no. of lines scanned exceeds maximum*/ + while ((fgets(rxGainTableLineBuffer, + sizeof(rxGainTableLineBuffer), + rxGainTableFilePointer) != NULL) && + (lineCount < ADI_ADRV9025_RX_GAIN_TABLE_SIZE_ROWS)) + { +#ifdef __GNUC__ + if (sscanf(rxGainTableLineBuffer, + "%hhu,%hhu,%hhu,%hhu,%hhu,%hu,%hd", + &gainIndex, + &rxGainTableRowBuffer[lineCount].rxFeGain, + &tiaControl, + &adcControl, + &rxGainTableRowBuffer[lineCount].extControl, + &rxGainTableRowBuffer[lineCount].phaseOffset, + &rxGainTableRowBuffer[lineCount].digGain) != NUM_COLUMNS) +#else + if (sscanf_s(rxGainTableLineBuffer, "%hhu,%hhu,%hhu,%hhu,%hhu,%hu,%hd", &gainIndex, + &rxGainTableRowBuffer[lineCount].rxFeGain, + &tiaControl, + &adcControl, + &rxGainTableRowBuffer[lineCount].extControl, + &rxGainTableRowBuffer[lineCount].phaseOffset, + &rxGainTableRowBuffer[lineCount].digGain) != NUM_COLUMNS) +#endif + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + lineCount, + "Insufficient entries in Rx gain table row entry"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + rxGainTableFilePointer); + } + + rxGainTableRowBuffer[lineCount].adcTiaGain = ((adcControl << 1) | tiaControl); + + if (lineCount == 0) + { + minGainIndex = gainIndex; + } + else + { + /*Check that gain indices are arranged in ascending order*/ + if (prevGainIndex != (gainIndex - 1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gainIndex, + "Gain indices not arranged in ascending order in Rx Gain Table file"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + rxGainTableFilePointer); + } + } + + prevGainIndex = gainIndex; + lineCount++; + } + + maxGainIndex = gainIndex; + + if ((adi_adrv9025_RxGainTableWrite(device, + rxChannelMask, + maxGainIndex, + &rxGainTableRowBuffer[0], + lineCount)) != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Unable to Write Rx gain table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + rxGainTableFilePointer); + } + + if ((adi_adrv9025_RxMinMaxGainIndexSet(device, + rxChannelMask, + minGainIndex, + maxGainIndex)) != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Unable to set Rx gain table min/max gain indices."); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + rxGainTableFilePointer); + } + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Empty Rx Gain Table encountered"); + /* no need for ADI_ERROR_CLOSE_RETURN here as the file will be closed below anyway */ + } + + /* Close Rx Gain Table csv file */ + if (fclose(rxGainTableFilePointer) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Fatal error while trying to close Rx Gain Table csv file. Possible memory shortage while flushing / other I/O errors."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_TxAttenTableLoad(adi_adrv9025_Device_t* device, + const char* txAttenTablePath, + uint32_t txChannelMask) +{ + static const uint8_t NUM_COLUMNS = 3; +#define LINE_BUFFER_SIZE 128 +#define HEADER_BUFFER_SIZE 16 + + uint16_t prevAttenIndex = 0; + uint16_t attenIndex = 0; + uint16_t minAttenIndex = 0; + uint16_t maxAttenIndex = 0; + uint16_t lineCount = 0; + uint16_t tableSize = 0; + FILE* txAttenTableFilePointer = NULL; + char txAttenTableLineBuffer[LINE_BUFFER_SIZE]; + char headerStr1[HEADER_BUFFER_SIZE]; + char headerStr2[HEADER_BUFFER_SIZE]; + char headerStr3[HEADER_BUFFER_SIZE]; + static adi_adrv9025_TxAttenTableRow_t txAttenTableRowBuffer[ADI_ADRV9025_TX_ATTEN_TABLE_SIZE_ROWS]; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + txAttenTablePath); + + maxAttenIndex = ADRV9025_TX_ATTEN_TABLE_MAX; + + /*Open Tx Atten Table csv file*/ +#ifdef __GNUC__ + txAttenTableFilePointer = fopen(txAttenTablePath, + "r"); +#else + if (fopen_s(&txAttenTableFilePointer, txAttenTablePath, "r") != 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, txAttenTablePath, + "Unable to open Tx Atten Table csv file. Please check if the path is correct or the file is open in another program"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + if (txAttenTableFilePointer == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenTablePath, + "Invalid Tx Atten Table csv file path encountered while attempting to load Tx Atten Table"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Check for empty Tx Atten Table*/ + if (fgets(txAttenTableLineBuffer, + sizeof(txAttenTableLineBuffer), + txAttenTableFilePointer) != NULL) + { +#ifdef __GNUC__ + if (sscanf(txAttenTableLineBuffer, + "%[^,],%[^,],%[^\n]", + headerStr1, + headerStr2, + headerStr3) != NUM_COLUMNS) +#else + if (sscanf_s(txAttenTableLineBuffer, "%[^,],%[^,],%[^\n]", headerStr1, (uint32_t)sizeof(headerStr1), + headerStr2, (uint32_t)sizeof(headerStr2), + headerStr3, (uint32_t)sizeof(headerStr3)) != NUM_COLUMNS) +#endif + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenTablePath, + "Invalid Tx Atten Table format encountered while attempting to load Tx Atten Table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + txAttenTableFilePointer); + } + + /*Verify that Gain Table Format is correct*/ + if (strstr(headerStr1, + "Tx Atten Index") == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenTablePath, + "Expected Tx Atten Index to be the first column in Tx Atten table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + txAttenTableFilePointer); + } + + if (strstr(headerStr2, + "Tx Atten Hp") == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenTablePath, + "Expected Tx Atten Hp to be the second column in Tx Atten table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + txAttenTableFilePointer); + } + + if (strstr(headerStr3, + "Tx Atten Mult") == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenTablePath, + "Expected Tx Atten Mult to be the third column in Tx Atten table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + txAttenTableFilePointer); + } + + /*Loop until the atten table end is reached or no. of lines scanned exceeds maximum*/ + while ((fgets(txAttenTableLineBuffer, + sizeof(txAttenTableLineBuffer), + txAttenTableFilePointer) != NULL) && + (lineCount < maxAttenIndex)) + { +#ifdef __GNUC__ + if (sscanf(txAttenTableLineBuffer, + "%hu,%hhu,%hu", + &attenIndex, + &txAttenTableRowBuffer[lineCount].txAttenHp, + &txAttenTableRowBuffer[lineCount].txAttenMult) != NUM_COLUMNS) +#else + if (sscanf_s(txAttenTableLineBuffer, "%hu,%hhu,%hu", &attenIndex, + &txAttenTableRowBuffer[lineCount].txAttenHp, + &txAttenTableRowBuffer[lineCount].txAttenMult) != NUM_COLUMNS) +#endif + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + lineCount, + "Insufficient entries in Tx atten table row entry"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + txAttenTableFilePointer); + } + + if (lineCount == 0) + { + minAttenIndex = attenIndex; + } + else + { + /*Check that atten indices are arranged in ascending order*/ + if (prevAttenIndex != (attenIndex - 1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + attenIndex, + "Atten indices not arranged in ascending order in Tx Atten Table file"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + txAttenTableFilePointer); + } + } + + prevAttenIndex = attenIndex; + lineCount++; + } + + tableSize = attenIndex - minAttenIndex + 1; + + if ((adi_adrv9025_TxAttenTableWrite(device, + txChannelMask, + minAttenIndex, + &txAttenTableRowBuffer[0], + tableSize)) != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenTablePath, + "Unable to write Tx Atten Table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + txAttenTableFilePointer); + } + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenTablePath, + "Empty Tx Atten Table encountered"); + /* no need for ADI_ERROR_CLOSE_RETURN here as the file will be closed below anyway */ + } + + /* Close Tx Atten Table csv file */ + if (fclose(txAttenTableFilePointer) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenTablePath, + "Fatal error while trying to close Tx Atten Table csv file. Possible memory shortage while flushing / other I/O errors."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PreMcsInit(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init, + const char* armImagePath, + const char* streamImagePath, + const char* rxGainTablePath, + const char* txAttenTablePath) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + /*TODO : Initialize adc profile with appropriate values*/ + adi_adrv9025_AdcProfiles_t adcProfile = {{0}}; + adi_adrv9025_TxAttenCfg_t txConfig = {0}; + adi_adrv9025_DacFullScale_e dacFullScale = ADI_ADRV9025_TX_DACFS_0DB; + adi_adrv9025_TxAtten_t txAtten = {0}; + uint8_t i = 0; + int32_t origLogLevel = 0; + int32_t logLevelNoSpi = 0; + uint32_t txChannels[] = { + (uint32_t)ADI_ADRV9025_TX1, + (uint32_t)ADI_ADRV9025_TX2, + (uint32_t)ADI_ADRV9025_TX3, + (uint32_t)ADI_ADRV9025_TX4 + }; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Reset Hardware */ + recoveryAction = adi_adrv9025_HwReset(device); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Reset Adrv9025 device"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Setup SPI controller, master bias, enable pin pads, Load PFIRs */ + recoveryAction = adi_adrv9025_Initialize(device, + init); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Initialize Adrv9025 device"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Disable SPI Logging */ + adi_common_LogLevelGet(&device->common, + &origLogLevel); + ADI_ERROR_RETURN(device->common.error.newAction); + + logLevelNoSpi = ADI_COMMON_LOG_MSG | ADI_COMMON_LOG_WARN | ADI_COMMON_LOG_ERR | ADI_COMMON_LOG_API; /*Disable SPI logging*/ + + adi_common_LogLevelSet(&device->common, + logLevelNoSpi); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Load Stream binary image from a .bin file */ + adi_adrv9025_StreamImageLoad(device, + streamImagePath); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Load binary image for CPU-C from a.bin file */ + adi_adrv9025_CpuImageLoad(device, + armImagePath); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Load Default Rx gain table from a .csv file for initialized channels */ + adi_adrv9025_RxGainTableLoad(device, + rxGainTablePath, + (init->rx.rxInitChannelMask & 0xFF)); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (device->devStateInfo.profilesValid & ADI_ADRV9025_TX_PROFILE_VALID) + { + /* Load Default Tx atten table from a .csv file for initialized channels */ + adi_adrv9025_TxAttenTableLoad(device, + txAttenTablePath, + init->tx.txInitChannelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Load ADC Profile */ + adrv9025_AdcProfilesInit(device, + init, + &adcProfile); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_adrv9025_CpuAdcProfilesWrite(device, + &adcProfile); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Load ARM profile */ + adi_adrv9025_CpuProfileWrite(device, + init); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ARM Bootup */ + adi_adrv9025_CpuStart(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ARM Bootup Status Check */ + adi_adrv9025_CpuStartStatusCheck(device, + ADI_ADRV9025_GETCPUBOOTUP_TIMEOUT_US); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (device->devStateInfo.profilesValid & ADI_ADRV9025_TX_PROFILE_VALID) + { + for (i = 0; i < ADI_ADRV9025_MAX_TXCHANNELS; i++) + { + /* For each tx channel enabled */ + if ((init->tx.txInitChannelMask & txChannels[i]) > 0) + { + /* For each tx channel enabled */ + if ((init->tx.txInitChannelMask & txChannels[i]) > 0) + { + txConfig.txChannelMask = txChannels[i]; + txConfig.txAttenStepSize = init->tx.txChannelCfg[i].txAttenCtrl.txAttenStepSize; + txConfig.attenMode = init->tx.txChannelCfg[i].txAttenCtrl.attenMode; + + /* These 2 fields are not being used actively */ + txConfig.disTxDataIfPllUnlock = ADI_ADRV9025_TXUNLOCK_TX_NOT_DISABLED; + txConfig.rampJesdDfrm = ADI_ADRV9025_TXUNLOCK_TX_NOT_DISABLED; + + adi_adrv9025_TxAttenCfgSet(device, + &txConfig, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (txConfig.attenMode == ADI_ADRV9025_TXATTEN_SPI_MODE) + { + txAtten.txChannelMask = txChannels[i]; + txAtten.txAttenuation_mdB = init->tx.txChannelCfg[i].txAttenCtrl.txAttenInit_mdB; + recoveryAction = adi_adrv9025_TxAttenSet(device, + &txAtten, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + dacFullScale = init->tx.txChannelCfg[i].dacFullScale; + adi_adrv9025_DacFullScaleSet(device, + (adi_adrv9025_TxChannels_e)txChannels[i], + dacFullScale); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + } + + /* Enable SPI logging */ + adi_common_LogLevelSet(&device->common, + origLogLevel); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PreMcsInit_v2(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init, + const char* armImagePath, + const char* streamImagePath, + adi_adrv9025_RxGainTableFile_t rxGainTableFileArr[], + uint8_t rxGainTableFileArrSize, + adi_adrv9025_TxAttenTableFile_t txAttenTableFileArr[], + uint8_t txAttenTableFileArrSize) + +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + //adi_adrv9025_AdcProfiles_t adcProfile = {{0}}; + uint8_t i = 0; + uint8_t wrCacheStateRestore = device->common.cacheInfo.wrCacheState; + uint8_t wrOnlyRestore = device->common.cacheInfo.wrOnly; + int32_t origLogLevel = 0; + int32_t logLevelNoSpi = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* If Write Cache is off, overwrite it to be HW_RMW to allow bf field write's during broadcast */ + if (device->common.cacheInfo.wrCacheState == (uint8_t)ADRV9025_WR_CACHE_OFF) + { + recoveryAction = adrv9025_BfWriteCacheEn(device, + ADRV9025_WR_HW_RMW_ON); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Cannot change write cache state to HW_RMW_ON"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Prevent any read operation from device during broadcast */ + device->common.cacheInfo.wrOnly = ADI_TRUE; + + /* Setup SPI controller, master bias, enable pin pads, Load PFIRs */ + recoveryAction = adi_adrv9025_Initialize(device, + init); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Initialize Adrv9025 device"); + ADI_ADRV9025_PREMCS_RESTORE_WRONLY(device->common, + wrOnlyRestore, + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Disable SPI Logging */ + adi_common_LogLevelGet(&device->common, + &origLogLevel); + ADI_ADRV9025_PREMCS_RESTORE_WRONLY(device->common, + wrOnlyRestore, + device->common.error.newAction); + ADI_ERROR_RETURN(device->common.error.newAction); + + logLevelNoSpi = ADI_COMMON_LOG_MSG | ADI_COMMON_LOG_WARN | ADI_COMMON_LOG_ERR | ADI_COMMON_LOG_API; /*Disable SPI logging*/ + + adi_common_LogLevelSet(&device->common, + logLevelNoSpi); + ADI_ADRV9025_PREMCS_RESTORE_WRONLY(device->common, + wrOnlyRestore, + device->common.error.newAction); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Load Stream binary image from a .bin file */ + recoveryAction = adi_adrv9025_StreamImageLoad(device, + streamImagePath); + ADI_ADRV9025_PREMCS_RESTORE_WRONLY(device->common, + wrOnlyRestore, + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* HW_RMW feature is enabled after stream image is loaded */ + device->common.cacheInfo.HW_RMW_Enabled = ADI_ADRV9025_HW_RMW_ENABLE; + + /* Load ARM binary image from a.bin file */ + recoveryAction = adi_adrv9025_CpuImageLoad(device, + armImagePath); + ADI_ADRV9025_PREMCS_RESTORE_WRONLY(device->common, + wrOnlyRestore, + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Load Rx gain table for requested channels */ + for (i = 0; i < rxGainTableFileArrSize; i++) + { + recoveryAction = adi_adrv9025_RxGainTableLoad(device, + rxGainTableFileArr[i].rxGainTableCsvFileName, + (rxGainTableFileArr[i].rxChannelMask & device->devStateInfo.initializedChannels)); + ADI_ADRV9025_PREMCS_RESTORE_WRONLY(device->common, + wrOnlyRestore, + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (device->devStateInfo.profilesValid & ADI_ADRV9025_TX_PROFILE_VALID) + { + /* Load Tx atten tables from a .csv file for requested channels */ + for (i = 0; i < txAttenTableFileArrSize; i++) + { + recoveryAction = adi_adrv9025_TxAttenTableLoad(device, + txAttenTableFileArr[i].txAttenTableCsvFileName, + (txAttenTableFileArr[i].txChannelMask & (device->devStateInfo.initializedChannels >> + ADI_ADRV9025_TX_INITIALIZED_CH_OFFSET))); + ADI_ADRV9025_PREMCS_RESTORE_WRONLY(device->common, + wrOnlyRestore, + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Load ADC Profiles */ + if (init->adcProfiles.RxChannel1[0] == 0) + { + recoveryAction = adrv9025_AdcProfilesInit(device, + init, + &init->adcProfiles); + ADI_ADRV9025_PREMCS_RESTORE_WRONLY(device->common, + wrOnlyRestore, + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* use ADC profiles from init structure */ + } + + recoveryAction = adi_adrv9025_CpuAdcProfilesWrite(device, + &init->adcProfiles); + + ADI_ADRV9025_PREMCS_RESTORE_WRONLY(device->common, + wrOnlyRestore, + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Load ARM profile */ + recoveryAction = adi_adrv9025_CpuProfileWrite(device, + init); + ADI_ADRV9025_PREMCS_RESTORE_WRONLY(device->common, + wrOnlyRestore, + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ARM Bootup */ + recoveryAction = adi_adrv9025_CpuStart(device); + ADI_ADRV9025_PREMCS_RESTORE_WRONLY(device->common, + wrOnlyRestore, + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Enable SPI logging */ + adi_common_LogLevelSet(&device->common, + origLogLevel); + ADI_ADRV9025_PREMCS_RESTORE_WRONLY(device->common, + wrOnlyRestore, + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Restore Bf write cache state for future usage */ + recoveryAction = adrv9025_BfWriteCacheEn(device, + (adrv9025_Bf_WrCache_State_e)wrCacheStateRestore); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Cannot restore write cache state while leaving PreMcsInit"); + ADI_ADRV9025_PREMCS_RESTORE_WRONLY(device->common, + wrOnlyRestore, + recoveryAction); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Restore wrOnly state for future usage */ + device->common.cacheInfo.wrOnly = wrOnlyRestore; + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PreMcsInit_NonBroadCast(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init) +{ + adi_adrv9025_TxAttenCfg_t txConfig = {0}; + adi_adrv9025_DacFullScale_e dacFullScale = ADI_ADRV9025_TX_DACFS_0DB; + adi_adrv9025_TxAtten_t txAtten = {0}; + + uint32_t txChannels[] = { + (uint32_t)ADI_ADRV9025_TX1, + (uint32_t)ADI_ADRV9025_TX2, + (uint32_t)ADI_ADRV9025_TX3, + (uint32_t)ADI_ADRV9025_TX4 + }; + + adi_adrv9025_RxDataFormat_t rxDataFormat = {0}; + + uint32_t rxChannels[] = { + (uint32_t)ADI_ADRV9025_RX1, + (uint32_t)ADI_ADRV9025_RX2, + (uint32_t)ADI_ADRV9025_RX3, + (uint32_t)ADI_ADRV9025_RX4, + (uint32_t)ADI_ADRV9025_ORX1, + (uint32_t)ADI_ADRV9025_ORX2, + (uint32_t)ADI_ADRV9025_ORX3, + (uint32_t)ADI_ADRV9025_ORX4 + }; + + uint8_t i = 0; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check init pointer is not null */ + ADI_NULL_PTR_RETURN(&device->common, + init); + +#if ADI_ADRV9025_INIT_RANGE_CHECK > 0 + recoveryAction = adi_adrv9025_ProfilesVerify(device, + init); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Init structure check failure"); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /* Check processor status before continuing */ + recoveryAction = adi_adrv9025_CpuStartStatusCheck(device, + ADI_ADRV9025_GETCPUBOOTUP_TIMEOUT_US); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Silicon Revision */ + recoveryAction = adi_adrv9025_DeviceRevGet(device, + &device->devStateInfo.deviceSiRev); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to read the device Silicon Rev"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Product ID */ + recoveryAction = adi_adrv9025_ProductIdGet(device, + &device->devStateInfo.deviceProductId); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to read the device Product ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (device->devStateInfo.profilesValid & ADI_ADRV9025_TX_PROFILE_VALID) + { + for (i = 0; i < ADI_ADRV9025_MAX_TXCHANNELS; i++) + { + /* For each tx channel enabled */ + if ((init->tx.txInitChannelMask & txChannels[i]) > 0) + { + txConfig.txChannelMask = txChannels[i]; + txConfig.txAttenStepSize = init->tx.txChannelCfg[i].txAttenCtrl.txAttenStepSize; + txConfig.attenMode = init->tx.txChannelCfg[i].txAttenCtrl.attenMode; + if ((txConfig.attenMode == ADI_ADRV9025_TXATTEN_GPIO_MODE) || (txConfig.attenMode == ADI_ADRV9025_TXATTEN_SPI2_MODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + attenMode, + "Attenuation mode shouldn't be either GPIO or SPI2 during init time"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* These 2 fields are not being used actively */ + txConfig.disTxDataIfPllUnlock = ADI_ADRV9025_TXUNLOCK_TX_NOT_DISABLED; + txConfig.rampJesdDfrm = ADI_ADRV9025_TXUNLOCK_TX_NOT_DISABLED; + + txConfig.simultaneousUpdateCfg.simultaneousUpdate = ADI_ADRV9025_TXATTEN_SIMULTAN_UPDATE_DISABLED; + txConfig.simultaneousUpdateCfg.gpioUpdatePin = ADI_ADRV9025_GPIO_INVALID; + txConfig.gpioModePinCfg.stepSize = 0; + txConfig.gpioModePinCfg.txAttenIncPin = ADI_ADRV9025_GPIO_INVALID; + txConfig.gpioModePinCfg.txAttenDecPin = ADI_ADRV9025_GPIO_INVALID; + + recoveryAction = adi_adrv9025_TxAttenCfgSet(device, + &txConfig, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (txConfig.attenMode == ADI_ADRV9025_TXATTEN_SPI_MODE) + { + txAtten.txChannelMask = txChannels[i]; + txAtten.txAttenuation_mdB = init->tx.txChannelCfg[i].txAttenCtrl.txAttenInit_mdB; + recoveryAction = adi_adrv9025_TxAttenSet(device, + &txAtten, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* enable the pa protection ramp up */ + recoveryAction = adrv9025_TxPaProtectionGainRampUpEnBfSet(device, + (adrv9025_BfTxChanAddr_e)adrv9025_TxAddrDecode(device, + txChannels[i]), + ADI_TRUE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_adrv9025_TxAttenuationRampUpStickyModeEnable(device, + txChannels[i], + ADI_TRUE, + ADI_TRUE, + ADI_TRUE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + dacFullScale = init->tx.txChannelCfg[i].dacFullScale; + recoveryAction = adi_adrv9025_DacFullScaleSet(device, + (adi_adrv9025_TxChannels_e)txChannels[i], + dacFullScale); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + if (device->devStateInfo.profilesValid & ADI_ADRV9025_RX_PROFILE_VALID) + { + for (i = 0; i < (sizeof(rxChannels) / sizeof(rxChannels[0])); i++) + { + if ((init->rx.rxInitChannelMask & rxChannels[i]) > 0) + { + rxDataFormat.rxChannelMask = rxChannels[i]; + rxDataFormat.externalLnaGain = init->rx.rxChannelCfg[i].profile.rxDataFormat.externalLnaGain; + rxDataFormat.tempCompensationEnable = init->rx.rxChannelCfg[i].profile.rxDataFormat.tempCompensationEnable; + rxDataFormat.formatSelect = init->rx.rxChannelCfg[i].profile.rxDataFormat.formatSelect; + rxDataFormat.floatingPointConfig.fpDataFormat = init->rx.rxChannelCfg[i].profile.rxDataFormat.floatingPointConfig.fpDataFormat; + rxDataFormat.floatingPointConfig.fpAttenSteps = init->rx.rxChannelCfg[i].profile.rxDataFormat.floatingPointConfig.fpAttenSteps; + rxDataFormat.floatingPointConfig.fpNumExpBits = init->rx.rxChannelCfg[i].profile.rxDataFormat.floatingPointConfig.fpNumExpBits; + rxDataFormat.floatingPointConfig.fpRoundMode = init->rx.rxChannelCfg[i].profile.rxDataFormat.floatingPointConfig.fpRoundMode; + rxDataFormat.floatingPointConfig.fpHideLeadingOne = init->rx.rxChannelCfg[i].profile.rxDataFormat.floatingPointConfig.fpHideLeadingOne; + rxDataFormat.floatingPointConfig.fpEncodeNan = init->rx.rxChannelCfg[i].profile.rxDataFormat.floatingPointConfig.fpEncodeNan; + rxDataFormat.integerConfigSettings.intSampleResolution = init->rx.rxChannelCfg[i].profile.rxDataFormat.integerConfigSettings.intSampleResolution; + rxDataFormat.integerConfigSettings.intEmbeddedBits = init->rx.rxChannelCfg[i].profile.rxDataFormat.integerConfigSettings.intEmbeddedBits; + rxDataFormat.integerConfigSettings.intParity = init->rx.rxChannelCfg[i].profile.rxDataFormat.integerConfigSettings.intParity; + rxDataFormat.slicerConfigSettings.intSlicerStepSize = init->rx.rxChannelCfg[i].profile.rxDataFormat.slicerConfigSettings.intSlicerStepSize; + rxDataFormat.slicerConfigSettings.extSlicerStepSize = init->rx.rxChannelCfg[i].profile.rxDataFormat.slicerConfigSettings.extSlicerStepSize; + rxDataFormat.slicerConfigSettings.rx1ExtSlicerGpioSelect = init->rx.rxChannelCfg[i].profile.rxDataFormat.slicerConfigSettings.rx1ExtSlicerGpioSelect; + rxDataFormat.slicerConfigSettings.rx2ExtSlicerGpioSelect = init->rx.rxChannelCfg[i].profile.rxDataFormat.slicerConfigSettings.rx2ExtSlicerGpioSelect; + rxDataFormat.slicerConfigSettings.rx3ExtSlicerGpioSelect = init->rx.rxChannelCfg[i].profile.rxDataFormat.slicerConfigSettings.rx3ExtSlicerGpioSelect; + rxDataFormat.slicerConfigSettings.rx4ExtSlicerGpioSelect = init->rx.rxChannelCfg[i].profile.rxDataFormat.slicerConfigSettings.rx4ExtSlicerGpioSelect; + + /* Setup the Rx formatter */ + recoveryAction = adi_adrv9025_RxDataFormatSet(device, + &rxDataFormat, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Setup Rx AGC overload protection registers */ + recoveryAction = adrv9025_RxOverloadProtectionSet(device, + (adi_adrv9025_RxChannels_e)rxChannels[i]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + /* Update desCfg */ + recoveryAction = adrv9025_JesdDesCfgSet(device, init); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_PostMcsInit(adi_adrv9025_Device_t* device, + adi_adrv9025_PostMcsInit_t* utilityInit) +{ + static const uint16_t RX_TIA_TUNER_MODE_REG_ADDR = 0x0C3E; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxEnableRegs = (((uint32_t)ADI_ADRV9025_RX1 | + (uint32_t)ADI_ADRV9025_RX2 | + (uint32_t)ADI_ADRV9025_RX3 | + (uint32_t)ADI_ADRV9025_RX4) + & device->devStateInfo.initializedChannels); + + uint8_t bufferProtectionDisable = 0x00; + adi_adrv9025_DeframerSel_e dfrmSelect = ADI_ADRV9025_DEFRAMER_0_AND_1; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, utilityInit); + + /*******************************HB2_IN BIT TOGGLE ************************************/ + /* Enable the Rx Channels to setup AGC overload thresholds */ + recoveryAction = adi_adrv9025_RxTxEnableSet(device, rxEnableRegs, (uint32_t)ADI_ADRV9025_TXOFF); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* 1ms sync delay to allow the Rx Tx enable streams to finish executing */ + recoveryAction = adi_common_hal_Wait_ms(&device->common, (uint32_t)1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Toggle force tia update bit */ + ADRV9025_SPIWRITEBYTE("ANALOG_RX_TIA_TUNER_MODE_REG", RX_TIA_TUNER_MODE_REG_ADDR, 0x01); + ADRV9025_SPIWRITEBYTE("ANALOG_RX_TIA_TUNER_MODE_REG", RX_TIA_TUNER_MODE_REG_ADDR, 0x00); + + /* Power down all Rx and Tx channels */ + recoveryAction = adi_adrv9025_RxTxEnableSet(device, (uint32_t)ADI_ADRV9025_RXOFF, (uint32_t)ADI_ADRV9025_TXOFF); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*******************************END HB2_IN BIT TOGGLE ************************************/ + + /*Initialize radio control. This is required to run before running init cals*/ + recoveryAction = adrv9025_RadioctrlInit(device, &utilityInit->radioCtrlInit); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Initialize cals*/ + recoveryAction = adrv9025_CalsInit(device, &utilityInit->initCals); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Disable Buffer Protection for both Deframers */ + recoveryAction = adi_adrv9025_DfrmBufferProtectionSet(device, bufferProtectionDisable, dfrmSelect); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_AdcProfilesInit(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init, + adi_adrv9025_AdcProfiles_t* adcProfile) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + init); + + ADI_NULL_PTR_RETURN(&device->common, + adcProfile); + +#if ADI_ADRV9025_INIT_RANGE_CHECK > 0 + recoveryAction = adi_adrv9025_ProfilesVerify(device, + init); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Init structure check failure"); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /* Load ADC Profile */ + recoveryAction = adrv9025_AdcProfilesInit(device, + init, + adcProfile); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Initialize Adc profiles"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_AuxDacCompensatedSet(adi_adrv9025_Device_t* device, + adi_adrv9025_AuxDacValueToCompensate_t* auxDacSet) +{ + static const int32_t INT_NUMERATOR_SHIFT = 15; + static const int32_t INT_DENOMINATOR_SHIFT = 24; + + /*Original values shifted by INT_NUMERATOR_SHIFT { 139.420, -9.530, -0.094, -3.290, -62.220, -103.900, -118.570, -112.420 } */ + static const int32_t b35CInt[8] = {4568515, -312279, -3080, -107807, -2038825, -3404595, -3885302, -3683779}; + + /*Original values shifted by INT_NUMERATOR_SHIFT { -0.14, 0.141, 0.094, 0.1, 0.101, 0.258, 0.279, 0.237 } */ + static const int32_t bTDInt[8] = {-4588, 4620, 3080, 3277, 3310, 8454, 9142, 7766}; + + /*Original values shifted by INT_DENOMINATOR_SHIFT { 0.359, 0.43, 0.431, 0.433, 0.462, 0.482, 0.482, 0.484 } */ + static const int32_t m35CInt[8] = {6023021, 7214203, 7230980, 7264535, 7751074, 8086618, 8086618, 8120173}; + + /*Original values shifted by INT_DENOMINATOR_SHIFT { 0.0000022, -0.000162, -0.000111, -0.00014, -0.000167, -0.000273, -0.000204, -0.00018 } */ + static const int32_t mTDInt[8] = {37, -2718, -1862, -2349, -2802, -4580, -3423, -3020}; + + static const uint16_t MAX_DAC_VOLTAGE = 1800; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t i = 0; + int32_t tempValInt = 0; + adi_adrv9025_AuxDacValue_t auxDacValueLocal = {0, 0}; + uint8_t temperatureAddr[4] = {0}; + uint8_t temperatureData[2] = {0}; + uint16_t requestedDacWord = 0; + uint32_t temperatureAdd = 0; + int32_t dacVoltageShifted = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + auxDacSet); + + if (auxDacSet->auxDacValue.dacVoltage > MAX_DAC_VOLTAGE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + dacVoltage, + "Requested DAC voltage is out of range, valid range is [0-1800mV]"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((auxDacSet->auxDacValueCompensationMode != ADI_ADRV9025_NO_COMPENSATION) && + (auxDacSet->auxDacValueCompensationMode != ADI_ADRV9025_NO_TEMP_COMPENSATION) && + (auxDacSet->auxDacValueCompensationMode != ADI_ADRV9025_COMPENSATE_WITH_INT_TEMP) && + (auxDacSet->auxDacValueCompensationMode != ADI_ADRV9025_COMPENSATE_WITH_EXT_TEMP)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + auxDacValueCompensationMode, + "Invalid compensation mode is selected for AuxDAC"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + dacVoltageShifted = (int32_t)auxDacSet->auxDacValue.dacVoltage << INT_NUMERATOR_SHIFT; + + for (i = 0; i < ADI_ADRV9025_MAX_AUXDACS; i++) + { + if ((auxDacSet->auxDacValue.auxDacMask & (uint32_t)(1 << i)) == (uint32_t)(1 << i)) + { + if (auxDacSet->auxDacValueCompensationMode != ADI_ADRV9025_NO_COMPENSATION) + { + if (auxDacSet->auxDacValueCompensationMode == ADI_ADRV9025_NO_TEMP_COMPENSATION) + { + auxDacSet->extTemperatureDegC = 35; + } + else if (auxDacSet->auxDacValueCompensationMode == ADI_ADRV9025_COMPENSATE_WITH_INT_TEMP) + { + recoveryAction = adrv9025_CpuDmaMemRead(device, + ADRV9025_CPU_ADDR_AVG_TEMP_ADDR, + temperatureAddr, + sizeof(temperatureAddr), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to read ARM memory"); + ADI_ERROR_RETURN(device->common.error.newAction); + + temperatureAdd = ((((uint32_t)temperatureAddr[3]) << 24) | (((uint32_t)temperatureAddr[2]) << 16) | (((uint32_t)temperatureAddr[1]) << 8) | + ((uint32_t)temperatureAddr[0])); + + recoveryAction = adrv9025_CpuDmaMemRead(device, + temperatureAdd, + temperatureData, + sizeof(temperatureData), + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Failed to read ARM memory"); + ADI_ERROR_RETURN(device->common.error.newAction); + + auxDacSet->extTemperatureDegC = (int16_t)(((uint16_t)temperatureData[1]) << 8) | ((uint16_t)temperatureData[0]); + } + + tempValInt = m35CInt[i] + mTDInt[i] * ((int32_t)auxDacSet->extTemperatureDegC - 35); + tempValInt = tempValInt >> (INT_DENOMINATOR_SHIFT - INT_NUMERATOR_SHIFT); + if (tempValInt == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + tempValInt, + "Zero divide detected during AuxDAC compensation"); + return device->common.error.newAction; + } + + auxDacValueLocal.dacWord = (uint16_t)((dacVoltageShifted - (b35CInt[i] + bTDInt[i] * ((int32_t)auxDacSet->extTemperatureDegC - 35))) / + tempValInt); + + recoveryAction = adrv9025_AuxDacValueSet(device, + (adi_adrv9025_AuxDacs_e)((uint8_t)(1 << i)), + auxDacValueLocal.dacWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + requestedDacWord = (uint16_t)(((uint32_t)auxDacSet->auxDacValue.dacVoltage * 4095) / 1800); + recoveryAction = adrv9025_AuxDacValueSet(device, + (adi_adrv9025_AuxDacs_e)((uint8_t)(1 << i)), + requestedDacWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_ConfigFileLoad(adi_adrv9025_Device_t* device, + const char* configFile, + adi_adrv9025_Init_t* init) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + FILE* initConifgJsonfilePtr = NULL; + char lineStr[ADRV9025_MAX_FILE_BUFFER + 1] = {0}; + int32_t currChar = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + configFile); + + ADI_NULL_PTR_RETURN(&device->common, + init); + +#if ADI_ADRV9025_INIT_RANGE_CHECK > 0 + recoveryAction = adi_adrv9025_ProfilesVerify(device, + init); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Init structure check failure"); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + initConifgJsonfilePtr = fopen(configFile, + "r"); + + if (initConifgJsonfilePtr == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + configFile, + "Invalid init config file path encountered while attempting to load ADRV9025 Init Structure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + adrv9025_JsonFindStartOfFile(device, + initConifgJsonfilePtr, + &lineStr[0], + "{", + &currChar); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + initConifgJsonfilePtr); + + adrv9025_JsonParseInitDataInterfaceSettings(device, + &init->dataInterface, + initConifgJsonfilePtr); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + initConifgJsonfilePtr); + + adrv9025_JsonParseInitClockSettings(device, + &init->clocks, + initConifgJsonfilePtr); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + initConifgJsonfilePtr); + + adrv9025_JsonParseInitGpInterruptSettings(device, + &init->gpInterrupts, + initConifgJsonfilePtr); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + initConifgJsonfilePtr); + + adrv9025_JsonParseInitRxSettings(device, + &init->rx, + initConifgJsonfilePtr); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + initConifgJsonfilePtr); + + adrv9025_JsonParseInitTxSettings(device, + &init->tx, + initConifgJsonfilePtr); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + initConifgJsonfilePtr); + + adrv9025_JsonParseInitAdcProfileSettings(device, + &init->adcProfiles, + initConifgJsonfilePtr); + if (init->adcProfiles.RxChannel1[0] != 0) + { + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + initConifgJsonfilePtr); + } + + + recoveryAction = adrv9025_JsonFindEndOfFile(device, + initConifgJsonfilePtr, + &lineStr[0], + "}", + &currChar); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Close JSON config file*/ + if (fclose(initConifgJsonfilePtr) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + initConifgJsonfilePtr, + "Fatal error while trying to close a JSON file. Possible memory shortage while flushing / other I/O errors."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} + +int32_t adi_adrv9025_UtilityInitFileLoad(adi_adrv9025_Device_t* device, + const char* utilInitFile, + adi_adrv9025_PostMcsInit_t* utilInit) +{ + FILE* initConifgJsonfilePtr = NULL; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + char lineStr[ADRV9025_MAX_FILE_BUFFER + 1] = { 0 }; + int32_t currChar = 0; + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, utilInitFile); + ADI_NULL_PTR_RETURN(&device->common, utilInit); + + + initConifgJsonfilePtr = fopen(utilInitFile, "r"); + + if (initConifgJsonfilePtr == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + configFile, + "Invalid util init config file path encountered while attempting to load ADRV9025 Util Init Structure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + adrv9025_JsonFindStartOfFile(device, + initConifgJsonfilePtr, + &lineStr[0], + "{", + &currChar); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + initConifgJsonfilePtr); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + initConifgJsonfilePtr, + &lineStr[0], + "radioCtrlInit", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + initConifgJsonfilePtr, + &lineStr[0], + "radioCtrlModeCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindStartOfObject(device, + initConifgJsonfilePtr, + &lineStr[0], + "txRadioCtrlModeCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "txEnableMode", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.radioCtrlModeCfg.txRadioCtrlModeCfg.txEnableMode); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + initConifgJsonfilePtr, + &lineStr[0], + "txChannelMask", + &currChar, + &utilInit->radioCtrlInit.radioCtrlModeCfg.txRadioCtrlModeCfg.txChannelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + initConifgJsonfilePtr, + &lineStr[0], + "txRadioCtrlModeCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindStartOfObject(device, + initConifgJsonfilePtr, + &lineStr[0], + "rxRadioCtrlModeCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "rxEnableMode", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.radioCtrlModeCfg.rxRadioCtrlModeCfg.rxEnableMode); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + initConifgJsonfilePtr, + &lineStr[0], + "rxChannelMask", + &currChar, + &utilInit->radioCtrlInit.radioCtrlModeCfg.rxRadioCtrlModeCfg.rxChannelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindEndOfObject(device, + initConifgJsonfilePtr, + &lineStr[0], + "rxRadioCtrlModeCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindStartOfObject(device, + initConifgJsonfilePtr, + &lineStr[0], + "orxRadioCtrlModeCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "orxEnableMode", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.radioCtrlModeCfg.orxRadioCtrlModeCfg.orxEnableMode); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "orxPinSelectSettlingDelay_armClkCycles", + &currChar, + &utilInit->radioCtrlInit.radioCtrlModeCfg.orxRadioCtrlModeCfg.orxPinSelectSettlingDelay_armClkCycles); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "singleChannel1PinModeOrxSel", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.radioCtrlModeCfg.orxRadioCtrlModeCfg.singleChannel1PinModeOrxSel); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "singleChannel2PinModeLowOrxSel", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.radioCtrlModeCfg.orxRadioCtrlModeCfg.singleChannel2PinModeLowOrxSel); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "singleChannel2PinModeHighOrxSel", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.radioCtrlModeCfg.orxRadioCtrlModeCfg.singleChannel2PinModeHighOrxSel); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "dualChannel2PinModeOrxSel", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.radioCtrlModeCfg.orxRadioCtrlModeCfg.dualChannel2PinModeOrxSel); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + initConifgJsonfilePtr, + &lineStr[0], + "orxRadioCtrlModeCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindEndOfObject(device, + initConifgJsonfilePtr, + &lineStr[0], + "radioCtrlModeCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + initConifgJsonfilePtr, + &lineStr[0], + "txToOrxMapping", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "orx1Map", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.txToOrxMapping.orx1Map); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "orx2Map", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.txToOrxMapping.orx2Map); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "orx3Map", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.txToOrxMapping.orx3Map); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "orx4Map", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.txToOrxMapping.orx4Map); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindEndOfObject(device, + initConifgJsonfilePtr, + &lineStr[0], + "txToOrxMapping", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindStartOfObject(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpioCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpInput0", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.streamGpioCfg.streamGpInput0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpInput1", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.streamGpioCfg.streamGpInput1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpInput2", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.streamGpioCfg.streamGpInput2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpInput3", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.streamGpioCfg.streamGpInput3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpInput4", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.streamGpioCfg.streamGpInput4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpInput5", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.streamGpioCfg.streamGpInput5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpInput6", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.streamGpioCfg.streamGpInput6); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpInput7", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.streamGpioCfg.streamGpInput7); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpInput8", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.streamGpioCfg.streamGpInput8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpInput9", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.streamGpioCfg.streamGpInput9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpInput10", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.streamGpioCfg.streamGpInput10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpInput11", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.streamGpioCfg.streamGpInput11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpInput12", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.streamGpioCfg.streamGpInput12); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpInput13", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.streamGpioCfg.streamGpInput13); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpInput14", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.streamGpioCfg.streamGpInput14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpInput15", + &currChar, + (uint8_t*)&utilInit->radioCtrlInit.streamGpioCfg.streamGpInput15); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindEndOfObject(device, + initConifgJsonfilePtr, + &lineStr[0], + "streamGpioCfg", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU64(device, + initConifgJsonfilePtr, + &lineStr[0], + "lo1PllFreq_Hz", + &currChar, + &utilInit->radioCtrlInit.lo1PllFreq_Hz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU64(device, + initConifgJsonfilePtr, + &lineStr[0], + "lo2PllFreq_Hz", + &currChar, + &utilInit->radioCtrlInit.lo2PllFreq_Hz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU64(device, + initConifgJsonfilePtr, + &lineStr[0], + "auxPllFreq_Hz", + &currChar, + &utilInit->radioCtrlInit.auxPllFreq_Hz); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindEndOfObject(device, + initConifgJsonfilePtr, + &lineStr[0], + "radioCtrlInit", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonFindStartOfObject(device, + initConifgJsonfilePtr, + &lineStr[0], + "initCals", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU32(device, + initConifgJsonfilePtr, + &lineStr[0], + "calMask", + &currChar, + &utilInit->initCals.calMask); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "channelMask", + &currChar, + &utilInit->initCals.channelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "warmBoot", + &currChar, + &utilInit->initCals.warmBoot); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindEndOfObject(device, + initConifgJsonfilePtr, + &lineStr[0], + "initCals", + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*move to calrslt file */ + recoveryAction = adrv9025_JsonParseCalRsltFileStr(device, + initConifgJsonfilePtr, + &lineStr[0], + &currChar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adrv9025_JsonParseU8(device, + initConifgJsonfilePtr, + &lineStr[0], + "checkFwVer", + &currChar, + &utilInit->checkFwVer); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adrv9025_JsonFindEndOfFile(device, + initConifgJsonfilePtr, + &lineStr[0], + "}", + &currChar); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Close JSON config file*/ + if (fclose(initConifgJsonfilePtr) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + initConifgJsonfilePtr, + "Fatal error while trying to close a JSON file. Possible memory shortage while flushing / other I/O errors."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + return recoveryAction; +} + +int32_t adi_adrv9025_ArmMemDump(adi_adrv9025_Device_t* device, + const char* binaryFilename) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_NULL_PTR_RETURN(&device->common, binaryFilename); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + adi_adrv9025_CpuMemDump(device, + ADI_ADRV9025_CPU_TYPE_C, + binaryFilename); + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuMemDump(adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + const char* binaryFilename) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + FILE* ofp; + uint32_t byteCount = 0; + uint32_t offset = 0; + uint8_t armMailboxBusy = 0; + uint8_t cmdStatusByte = 0; + uint8_t exceptionArray[4] = {0}; + uint8_t extArray[4] = {0}; + uint32_t exceptionValue = 0; + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + uint8_t binaryRead[ADI_ADRV9025_MEM_DUMP_CHUNK_SIZE + 10] = {0}; + + const uint32_t armExceptionAddr = 0x20028210; /* Exception Flag Memory */ + + ADI_NULL_PTR_RETURN(&device->common, + binaryFilename); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADRV9025_BUGINFO(__FUNCTION__); + +#ifdef ADRV9025_INIT_DEBUG + printf("open %s (%s) \n", binaryFilename, "wb"); +#endif + +#ifdef __GNUC__ + ofp = fopen(binaryFilename, + "wb"); +#else + fopen_s(&ofp, binaryFilename, "wb"); +#endif + + if (ofp == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + ofp, + "Unable to open binary image file. Please check if the path is correct"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* get the particular processor's address map */ + cpuAddr = adrv9025_CpuAddrGet(&device->devStateInfo.cpu, + cpuType); + ADI_NULL_PTR_RETURN(&device->common, + cpuAddr); + + /* Check if exception has occurred */ + recoveryAction = adi_adrv9025_CpuMemRead(device, + armExceptionAddr, + &exceptionArray[0], + 4, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Read Arm memory"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + ofp); + + exceptionValue = (uint32_t)(exceptionArray[0] | (exceptionArray[1] << 8) | (exceptionArray[2] << 16) | (exceptionArray[3] << 24)); + + if (exceptionValue == 0) + { + /* Force an exception during ARM MEM dump for more useful information */ + + recoveryAction = adi_adrv9025_CpuMailboxBusyGet(device, + ADI_ADRV9025_CPU_TYPE_C, + &armMailboxBusy); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Invalid Get for armMailboxBusy"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + ofp); + + if (armMailboxBusy == ADI_FALSE) + { + extArray[0] = ADRV9025_CPU_OBJECTID_CPU_EXCEPTION; + recoveryAction = adi_adrv9025_CpuCmdWrite(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_SET_OPCODE, + &extArray[0], + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Proccess Arm command"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + ofp); + + recoveryAction = adi_adrv9025_CpuCmdStatusWait(device, + ADI_ADRV9025_CPU_TYPE_C, + ADRV9025_CPU_SET_OPCODE, + &cmdStatusByte, + ADI_ADRV9025_WRITECPUEXCEPTION_TIMEOUT_US, + ADI_ADRV9025_WRITECPUEXCEPTION_INTERVAL_US); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Proccess Arm command"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + ofp); + + recoveryAction = adi_adrv9025_CpuMemRead(device, + armExceptionAddr, + &exceptionArray[0], + 4, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Read Arm memory"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + ofp); + + exceptionValue = (uint32_t)(exceptionArray[0] | (exceptionArray[1] << 8) | (exceptionArray[2] << 16) | (exceptionArray[3] << 24)); + if (exceptionValue == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + exceptionValue, + "Unable to force ARM to throw exception"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + /* Program Binary */ + for (offset = cpuAddr->progStartAddr; offset < cpuAddr->progEndAddr; offset += ADI_ADRV9025_MEM_DUMP_CHUNK_SIZE) + { + if (offset < (cpuAddr->progEndAddr - ADI_ADRV9025_MEM_DUMP_CHUNK_SIZE)) + { + byteCount = ADI_ADRV9025_MEM_DUMP_CHUNK_SIZE; + } + else + { + byteCount = cpuAddr->progEndAddr + 1 - offset; + } + + recoveryAction = adi_adrv9025_CpuMemRead(device, + offset, + binaryRead, + byteCount, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Read Arm memory"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + ofp); + + if (fwrite(binaryRead, + 1, + byteCount, + ofp) != byteCount) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + ofp, + "Fatal error while trying to write a binary file."); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + ofp); + } + } + + /* Data Binary */ + for (offset = cpuAddr->dataStartAddr; offset < cpuAddr->dataEndAddr; offset += ADI_ADRV9025_MEM_DUMP_CHUNK_SIZE) + { + if (offset < (cpuAddr->dataEndAddr - ADI_ADRV9025_MEM_DUMP_CHUNK_SIZE)) + { + byteCount = ADI_ADRV9025_MEM_DUMP_CHUNK_SIZE; + } + else + { + byteCount = cpuAddr->dataEndAddr + 1 - offset; + } + + recoveryAction = adi_adrv9025_CpuMemRead(device, + offset, + binaryRead, + byteCount, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Read Arm memory"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + ofp); + + if (fwrite(binaryRead, + 1, + byteCount, + ofp) != byteCount) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + ofp, + "Fatal error while trying to write a binary file."); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + ofp); + } + } + + /*Close ARM binary file*/ + if (fclose(ofp) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + ofp, + "Fatal error while trying to close a binary file. Possible memory shortage while flushing / other I/O errors."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_CpuMemDumpWithoutException(adi_adrv9025_Device_t* device, + adi_adrv9025_CpuType_e cpuType, + const char* binaryFilename) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + FILE* ofp; + uint32_t byteCount = 0; + uint32_t offset = 0; + adi_adrv9025_CpuAddr_t* cpuAddr = NULL; + + uint8_t binaryRead[ADI_ADRV9025_MEM_DUMP_CHUNK_SIZE + 10] = {0}; + + ADI_NULL_PTR_RETURN(&device->common, + binaryFilename); + +#ifdef __GNUC__ + ofp = fopen(binaryFilename, + "wb"); +#else + fopen_s(&ofp, binaryFilename, "wb"); +#endif + + if (ofp == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + ofp, + "Unable to open binary image file. Please check if the path is correct"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* get the particular processor's address map */ + cpuAddr = adrv9025_CpuAddrGet(&device->devStateInfo.cpu, + cpuType); + ADI_NULL_PTR_RETURN(&device->common, + cpuAddr); + + /* Program Binary */ + for (offset = cpuAddr->progStartAddr; offset < cpuAddr->progEndAddr; offset += ADI_ADRV9025_MEM_DUMP_CHUNK_SIZE) + { + if (offset < (cpuAddr->progEndAddr - ADI_ADRV9025_MEM_DUMP_CHUNK_SIZE)) + { + byteCount = ADI_ADRV9025_MEM_DUMP_CHUNK_SIZE; + } + else + { + byteCount = cpuAddr->progEndAddr + 1 - offset; + } + + recoveryAction = adi_adrv9025_CpuMemRead(device, + offset, + binaryRead, + byteCount, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Read Arm Program memory"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + ofp); + + if (fwrite(binaryRead, + 1, + byteCount, + ofp) != byteCount) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + ofp, + "Fatal error while trying to write program memory to binary file."); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + ofp); + } + } + + /* Data Binary */ + for (offset = cpuAddr->dataStartAddr; offset < cpuAddr->dataEndAddr; offset += ADI_ADRV9025_MEM_DUMP_CHUNK_SIZE) + { + if (offset < (cpuAddr->dataEndAddr - ADI_ADRV9025_MEM_DUMP_CHUNK_SIZE)) + { + byteCount = ADI_ADRV9025_MEM_DUMP_CHUNK_SIZE; + } + else + { + byteCount = cpuAddr->dataEndAddr + 1 - offset; + } + + recoveryAction = adi_adrv9025_CpuMemRead(device, + offset, + binaryRead, + byteCount, + ADI_ADRV9025_CPU_MEM_AUTO_INCR); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to Read Arm Data memory"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + ofp); + + if (fwrite(binaryRead, + 1, + byteCount, + ofp) != byteCount) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + ofp, + "Fatal error while trying to write data memory to binary file."); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + ofp); + } + } + + /*Close ARM binary file*/ + if (fclose(ofp) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + ofp, + "Fatal error while trying to close a binary file. Possible memory shortage while flushing / other I/O errors."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_GpIntInit(adi_adrv9025_Device_t* device, + adi_adrv9025_GpInterruptSettings_t* gpIntInit) +{ + adi_adrv9025_gpMaskSelect_e maskSelect = ADI_ADRV9025_GPINTALL; + adi_adrv9025_gp_MaskArray_t maskArray = {0}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Clear status register */ + adi_adrv9025_GPIntClearStatusRegister(device); + + /* Setup GP int masks */ + maskArray.gpInt0Mask = gpIntInit->gpIntMaskPin0; + maskArray.gpInt1Mask = gpIntInit->gpIntMaskPin1; + adi_adrv9025_GpIntMaskSet(device, + maskSelect, + &maskArray); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TxRampDownInit(adi_adrv9025_Device_t* device, + adi_adrv9025_Init_t* init) +{ + static const uint8_t CLEAR_RAMPDOWN_MASK = 0x07; + static const uint32_t VALID_RAMPDOWN_EVENTS = + ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_DFRMIRQ0 | + ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_DFRMIRQ1 | + ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_RF1PLLUNLOCK | + ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_RF2PLLUNLOCK | + ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_SERDESPLLUNLOCK | + ADI_ADRV9025_DISABLE_TX_RAMP_DOWN_ON_CLKPLLUNLOCK | + ADI_ADRV9025_TX_RAMP_DOWN_AUTOSELECT; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adi_adrv9025_TxRampDownInitCfg_t txRampDownInitCfg = {0}; + uint8_t i = 0; + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + ADI_NULL_PTR_RETURN(&device->common, + init); + +#if ADI_ADRV9025_INIT_RANGE_CHECK > 0 + recoveryAction = adi_adrv9025_ProfilesVerify(device, + init); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Init structure check failure"); + ADI_ERROR_RETURN(device->common.error.newAction); +#endif + + /* During Jesd link bring up, we're getting Dfrm Irq's. We should clear all previous Irq's before enabling ramp down */ + recoveryAction = adi_adrv9025_DfrmIrqSourceReset(device, + ADI_ADRV9025_DEFRAMER_0_AND_1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*Check that init->tx.txInitChannelMask is not zero*/ + if (init->tx.txInitChannelMask == ADI_ADRV9025_TXOFF) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + init->tx.txInitChannelMask, + "Invalid TxChannel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_ADRV9025_MAX_TXCHANNELS; i++) + { + txRampDownInitCfg.txChannel = (adi_adrv9025_TxChannels_e)((uint8_t)(1 << i)); + + if (init->tx.txInitChannelMask & txRampDownInitCfg.txChannel) + { + txRampDownInitCfg.txRampDownEvents = init->tx.txChannelCfg[i].txAttenCtrl.txRampDownEvents; + if ((txRampDownInitCfg.txRampDownEvents & VALID_RAMPDOWN_EVENTS) != txRampDownInitCfg.txRampDownEvents) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + init->tx.txChannelCfg[i].txAttenCtrl.txRampDownEvents, + "Invalid Tx Ramp Down Events Bitmask"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((txRampDownInitCfg.txChannel == ADI_ADRV9025_TX1) || (txRampDownInitCfg.txChannel == ADI_ADRV9025_TX2)) + { + txRampDownInitCfg.txLoSel = init->clocks.tx12LoSelect; + } + else + { + txRampDownInitCfg.txLoSel = init->clocks.tx34LoSelect; + } + txRampDownInitCfg.deserializerLanesEnabledDfrm0 = init->dataInterface.deframer[0].deserializerLanesEnabled; + txRampDownInitCfg.deserializerLanesEnabledDfrm1 = init->dataInterface.deframer[1].deserializerLanesEnabled; + txRampDownInitCfg.serdesPllVcoFreq_kHz = init->clocks.serdesPllVcoFreq_kHz; + + /* Clear previous ramp down events before enabling it */ + recoveryAction = adi_adrv9025_PaPllDfrmEventClear(device, + txRampDownInitCfg.txChannel, + CLEAR_RAMPDOWN_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Initialize Tx ramp down configuration */ + recoveryAction = adrv9025_TxRampDownInit(device, + &txRampDownInitCfg); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Enable TX Ramp up */ + recoveryAction = adi_adrv9025_PaProtectionRampUpEnableSet(device, + (uint32_t)txRampDownInitCfg.txChannel, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_RxGainTableChecksumRead(adi_adrv9025_Device_t* device, + const char* rxGainTablePath, + uint32_t* rxGainTableChecksum) +{ +#define RX_CHECKSUM_BUFFER_SIZE 9 + + static const uint8_t NUM_COLUMNS = 1; + static const int8_t CHECKSUM_OFFSET = -8; + + FILE* rxGainTableFilePointer = NULL; + char rxGainTableChecksumBuffer[RX_CHECKSUM_BUFFER_SIZE] = {0}; + uint32_t checksum = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_DEVICE_PTR_RETURN(rxGainTablePath); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + /* Open Rx Gain Table csv file */ +#ifdef __GNUC__ + rxGainTableFilePointer = fopen(rxGainTablePath, "r"); +#else + if (fopen_s(&rxGainTableFilePointer, rxGainTablePath, "r") != 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, rxGainTablePath, + "Unable to open Rx Gain Table csv file. Please check if the path is correct or the file is open in another program"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + if (rxGainTableFilePointer == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Invalid Rx Gain Table csv file path while attempting to load Rx Gain Table"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Rewind the file pointer to ending of the file */ + if (fseek(rxGainTableFilePointer, + CHECKSUM_OFFSET, + SEEK_END) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Unable to move file descriptor to the ending of the Rx gain table file"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + rxGainTableFilePointer); + } + + /* Get the the last line when finding its corresponding beginning */ + if (fgets(rxGainTableChecksumBuffer, + RX_CHECKSUM_BUFFER_SIZE, + rxGainTableFilePointer) != NULL) + { + /* Convert characters to int */ + if (sscanf(rxGainTableChecksumBuffer, + "%Xu", + &checksum) != NUM_COLUMNS) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "checksum value wrong in the Rx gain table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + rxGainTableFilePointer); + } + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Invalid checksum information in the Rx Gain Table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + rxGainTableFilePointer); + } + + /* Close Rx Gain Table csv file */ + if (fclose(rxGainTableFilePointer) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxGainTablePath, + "Fatal error while trying to close Rx Gain Table csv file. Possible memory shortage while flushing / other I/O errors."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *rxGainTableChecksum = checksum; + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_RxGainTableChecksumCalculate(adi_adrv9025_Device_t* device, + adi_adrv9025_RxChannels_e rxChannel, + uint32_t* rxGainTableChecksum) +{ +#define MAX_RX_GAIN_TABLE_LINES 256u +#define GAIN_TABLE_SIZE 2304u //2304 = 256 * 9, the size of Rx gain table csv row is 9 + + static const uint8_t INDEX_MASK = 0xFF; + static const uint8_t TIA_GAIN_MASK = 0x1; + static const uint8_t ADC_GAIN_MASK = 0x1; + static const uint8_t ADC_GAIN_SHIFT = 1; + static const uint8_t PHASE_OFFSET_MASK = 0xFF; + static const uint8_t PHASE_OFFSET_SHIFT = 8; + static const uint8_t DIG_GAIN_MASK = 0xFF; + static const uint8_t DIG_GAIN_SHIFT = 8; + + uint32_t recoveryAction = 0; + uint16_t numGainIndicesRead = 0; + uint32_t i = 0; + uint32_t offset = 0; + uint32_t checksum = 0; + + adi_adrv9025_RxGainTableRow_t gainTableRow[MAX_RX_GAIN_TABLE_LINES] = { { 0 } }; + uint8_t gainTableData[GAIN_TABLE_SIZE] = {0}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that the channel requested is valid */ + if ((rxChannel != ADI_ADRV9025_RX1) && + (rxChannel != ADI_ADRV9025_RX2) && + (rxChannel != ADI_ADRV9025_RX3) && + (rxChannel != ADI_ADRV9025_RX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxChannel, + "Invalid Rx Channel Requested for gain table read. Valid Rx channels include Rx1-Rx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adi_adrv9025_RxGainTableRead(device, + rxChannel, + ADI_ADRV9025_MAX_GAIN_TABLE_INDEX, + gainTableRow, + MAX_RX_GAIN_TABLE_LINES, + &numGainIndicesRead); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Rx Gain Table read failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (numGainIndicesRead != MAX_RX_GAIN_TABLE_LINES) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + numGainIndicesRead, + "Rx Gain Table read number of lines wrong"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < MAX_RX_GAIN_TABLE_LINES; i++) + { + gainTableData[offset++] = (uint8_t)(i & INDEX_MASK); + gainTableData[offset++] = (uint8_t)(gainTableRow[i].rxFeGain); + gainTableData[offset++] = (uint8_t)(gainTableRow[i].adcTiaGain & TIA_GAIN_MASK); + gainTableData[offset++] = (uint8_t)((gainTableRow[i].adcTiaGain >> ADC_GAIN_SHIFT) & ADC_GAIN_MASK); + gainTableData[offset++] = (uint8_t)(gainTableRow[i].extControl); + gainTableData[offset++] = (uint8_t)(gainTableRow[i].phaseOffset & PHASE_OFFSET_MASK); + gainTableData[offset++] = (uint8_t)((gainTableRow[i].phaseOffset >> PHASE_OFFSET_SHIFT) & PHASE_OFFSET_MASK); + gainTableData[offset++] = (uint8_t)(gainTableRow[i].digGain & DIG_GAIN_MASK); + gainTableData[offset++] = (uint8_t)((gainTableRow[i].digGain >> DIG_GAIN_SHIFT) & DIG_GAIN_MASK); + } + + if (offset != GAIN_TABLE_SIZE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + offset, + "Rx Gain Table data size wrong"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + checksum = adrv9025_Crc32ForChunk(gainTableData, + offset, + checksum, + 1); + + *rxGainTableChecksum = checksum; + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TxAttenTableChecksumRead(adi_adrv9025_Device_t* device, + const char* txAttenTablePath, + uint32_t* txAttenTableChecksum) +{ +#define TX_CHECKSUM_BUFFER_SIZE 9 + + static const uint8_t NUM_COLUMNS = 1; + static const int8_t CHECKSUM_OFFSET = -8; + + FILE* txAttenTableFilePointer = NULL; + char txAttenTableChecksumBuffer[TX_CHECKSUM_BUFFER_SIZE] = {0}; + uint32_t checksum = 0; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_DEVICE_PTR_RETURN(txAttenTablePath); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + /* Open Tx Atten Table csv file */ +#ifdef __GNUC__ + txAttenTableFilePointer = fopen(txAttenTablePath, "r"); +#else + if (fopen_s(&txAttenTableFilePointer, txAttenTablePath, "r") != 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, txAttenTablePath, + "Unable to open Tx Atten Table csv file. Please check if the path is correct or the file is open in another program"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + if (txAttenTableFilePointer == NULL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenTablePath, + "Invalid Tx Atten Table csv file path while attempting to load Tx Atten Table"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Rewind the file pointer to ending of the file */ + if (fseek(txAttenTableFilePointer, + CHECKSUM_OFFSET, + SEEK_END) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenTablePath, + "Unable to move file descriptor to the ending of the Tx atten table file"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + txAttenTableFilePointer); + } + + /* Get the the last line when finding its corresponding beginning */ + if (fgets(txAttenTableChecksumBuffer, + TX_CHECKSUM_BUFFER_SIZE, + txAttenTableFilePointer) != NULL) + { + /* Convert characters to int */ + if (sscanf(txAttenTableChecksumBuffer, + "%Xu", + &checksum) != NUM_COLUMNS) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenTablePath, + "checksum value wrong in the Tx atten table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + txAttenTableFilePointer); + } + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenTablePath, + "Invalid checksum information in the Rx Gain Table"); + ADI_ERROR_CLOSE_RETURN(device->common.error.newAction, + txAttenTableFilePointer); + } + + /* Close Rx Gain Table csv file */ + if (fclose(txAttenTableFilePointer) < 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txAttenTablePath, + "Fatal error while trying to close Tx Atten Table csv file. Possible memory shortage while flushing / other I/O errors."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *txAttenTableChecksum = checksum; + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_TxAttenTableChecksumCalculate(adi_adrv9025_Device_t* device, + adi_adrv9025_TxChannels_e txChannel, + uint32_t* txAttenTableChecksum) +{ +#define ATTEN_TABLE_SIZE 4800u //4800 = 960 * 5, the size of Tx atten table row is 5 + + static const uint8_t INDEX_MASK = 0xFF; + static const uint8_t INDEX_SHIFT = 8; + static const uint8_t ATTEN_MULT_MASK = 0xFF; + static const uint8_t ATTEN_MULT_SHIFT = 8; + + uint32_t recoveryAction = 0; + uint32_t i = 0; + uint32_t offset = 0; + uint32_t checksum = 0; + + adi_adrv9025_TxAttenTableRow_t txAttenTableRow[ADRV9025_TX_ATTEN_TABLE_MAX] = { { 0 } }; + uint8_t attenTableData[ATTEN_TABLE_SIZE] = {0}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Check that the channel requested is valid */ + if ((txChannel != ADI_ADRV9025_TX1) && + (txChannel != ADI_ADRV9025_TX2) && + (txChannel != ADI_ADRV9025_TX3) && + (txChannel != ADI_ADRV9025_TX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txChannel, + "Invalid Tx Channel Requested for atten table read. Valid Tx channels include Tx1-Tx4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adi_adrv9025_TxAttenTableRead(device, + txChannel, + 0, + txAttenTableRow, + ADRV9025_TX_ATTEN_TABLE_MAX); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Tx Atten Table read failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADRV9025_TX_ATTEN_TABLE_MAX; i++) + { + attenTableData[offset++] = (uint8_t)(i & INDEX_MASK); + attenTableData[offset++] = (uint8_t)((i >> INDEX_SHIFT) & INDEX_MASK); + attenTableData[offset++] = (uint8_t)(txAttenTableRow[i].txAttenHp); + attenTableData[offset++] = (uint8_t)(txAttenTableRow[i].txAttenMult & ATTEN_MULT_MASK); + attenTableData[offset++] = (uint8_t)((txAttenTableRow[i].txAttenMult >> ATTEN_MULT_SHIFT) & ATTEN_MULT_MASK); + } + + if (offset != ATTEN_TABLE_SIZE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + offset, + "Tx Atten Table data size wrong"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + checksum = adrv9025_Crc32ForChunk(attenTableData, + offset, + checksum, + 1); + + *txAttenTableChecksum = checksum; + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_RadioctrlInit(adi_adrv9025_Device_t *device, + adi_adrv9025_RadioctrlInit_t *radioCtrlInit) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + /* Check radioCtrlInit is not null */ + ADI_NULL_PTR_RETURN(&device->common, + radioCtrlInit); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + recoveryAction = adrv9025_RadioctrlInit(device, + radioCtrlInit); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Unable to RadioctrlInit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_adrv9025_ApiArmStreamVersionCompare(adi_adrv9025_Device_t *device, + adi_adrv9025_ApiArmStreamVersions_t *srcVersion, + uint8_t *result) +{ + const uint8_t API_VERSION_MASK = 0x1u; + const uint8_t ARM_VERSION_MASK = 0x2u; + const uint8_t STREAM_VERSION_MASK = 0x4u; + + uint32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + adi_adrv9025_ApiArmStreamVersions_t dstVersion = { {0 }}; + + /* Check device pointer is not null */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); + + /* Initial this result with 0 */ + *result = 0; + + recoveryAction = adi_adrv9025_ApiVersionGet(device, + &(dstVersion.apiVersion)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "API version get failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((srcVersion->apiVersion.majorVer != dstVersion.apiVersion.majorVer) || + (srcVersion->apiVersion.minorVer != dstVersion.apiVersion.minorVer) || + (srcVersion->apiVersion.maintenanceVer != dstVersion.apiVersion.maintenanceVer) || + (srcVersion->apiVersion.buildVer != dstVersion.apiVersion.buildVer)) + { + *result |= API_VERSION_MASK; + } + + recoveryAction = adi_adrv9025_ArmVersionGet(device, + &(dstVersion.armVersion)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "ARM version get failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((srcVersion->armVersion.majorVer != dstVersion.armVersion.majorVer) || + (srcVersion->armVersion.minorVer != dstVersion.armVersion.minorVer) || + (srcVersion->armVersion.maintVer != dstVersion.armVersion.maintVer) || + (srcVersion->armVersion.rcVer != dstVersion.armVersion.rcVer)) + { + *result |= ARM_VERSION_MASK; + } + + recoveryAction = adi_adrv9025_StreamVersionGet(device, + &(dstVersion.streamVersion)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_API_FAIL, + recoveryAction, + NULL, + "Stream version get failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((srcVersion->streamVersion.majorVer != dstVersion.streamVersion.majorVer) || + (srcVersion->streamVersion.minorVer != dstVersion.streamVersion.minorVer) || + (srcVersion->streamVersion.mainVer != dstVersion.streamVersion.mainVer) || + (srcVersion->streamVersion.buildVer != dstVersion.streamVersion.buildVer)) + { + *result |= STREAM_VERSION_MASK; + } + + return ADI_COMMON_ACT_NO_ACTION; +} + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/makefile b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/makefile new file mode 100644 index 0000000..d37793e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/makefile @@ -0,0 +1,37 @@ +LIB_ADI_FPGA9010_DEVICE = libadi_fpga9010.a +CC = gcc +ADI_FPGA9010_SRC = ./public/src +ADI_FPGA9010_PRIVATE_SRC = ./private/src +ARFLAGS = -rv +CFLAGS = -Werror -Wall -I./public/include -I../../platforms/ -I../../common/ -I../../common/adi_error -I../../common/adi_logging -I../../common/adi_hal +ADI_PLATFORM_SRC = ../../platforms +ADI_COMMON_SRC = ../../common +EXT = c + +SRC = $(wildcard $(ADI_FPGA9010_PRIVATE_SRC)/*.$(EXT)) \ + $(wildcard $(ADI_FPGA9010_SRC)/*.$(EXT)) + +OBJS = $(SRC:.$(EXT)=.o) + +all: adi_platform_lib \ + adi_common_lib \ + $(LIB_ADI_FPGA9010_DEVICE) + +.$(EXT).o: + $(CC) $(CFLAGS) -o $@ -c $< + +$(LIB_ADI_FPGA9010_DEVICE): $(OBJS) + ar $(ARFLAGS) $(LIB_ADI_FPGA9010_DEVICE) $(OBJS) + +adi_platform_lib: + $(MAKE) -C $(ADI_PLATFORM_SRC) + +adi_common_lib: + $(MAKE) -C $(ADI_COMMON_SRC) + +clean: + rm -rf $(ADI_FPGA9010_SRC)/*.o + rm -rf $(ADI_FPGA9010_PRIVATE_SRC)/*.o + rm -rf *.a + $(MAKE) -C $(ADI_PLATFORM_SRC) clean + $(MAKE) -C $(ADI_COMMON_SRC) clean diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_ads8v2.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_ads8v2.h new file mode 100644 index 0000000..47f3982 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_ads8v2.h @@ -0,0 +1,227 @@ +/** + * \file fpga9010_bf_ads8v2.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_ADS8V2_H__ +#define __FPGA9010_BF_ADS8V2_H__ + +#include "./../../private/include/fpga9010_bf_ads8v2_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_Ads8v2Ad9528ResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2Ad9528ResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2Adg918CtrlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2Adg918CtrlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2ExtTrig0DirBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2ExtTrig0DirBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2ExtTrig0OutputSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2ExtTrig0OutputSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2ExtTrig1DirBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2ExtTrig1DirBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2ExtTrig1OutputSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2ExtTrig1OutputSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2ExtTrig2DirBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2ExtTrig2DirBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2ExtTrig2OutputSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2ExtTrig2OutputSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2ExtTrig3DirBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2ExtTrig3DirBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2ExtTrig3OutputSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2ExtTrig3OutputSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2ExtTrigRxdp00CtrlSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2ExtTrigRxdp00CtrlSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2ExtTrigRxdp01CtrlSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2ExtTrigRxdp01CtrlSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2ExtTrigRxdp02CtrlSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2ExtTrigRxdp02CtrlSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2ExtTrigTddCtrlSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2ExtTrigTddCtrlSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2ExtTrigTxdp00CtrlSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2ExtTrigTxdp00CtrlSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2ExtTrigTxdp01CtrlSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2ExtTrigTxdp01CtrlSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2LedBlinkDurationBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Ads8v2LedBlinkDurationBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Ads8v2LedDelayToModeChangeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Ads8v2LedDelayToModeChangeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Ads8v2LedMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2LedMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2LedModeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2LedModeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2LedNumBlinksBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2LedNumBlinksBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2LedSwDefinedValueBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2LedSwDefinedValueBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2Pca9545ResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Ads8v2Pca9545ResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2VersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Ads8v2VersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint16_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_ADS8V2_H__ + +/* EOF: fpga9010_bf_ads8v2.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_ads8v2_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_ads8v2_types.h new file mode 100644 index 0000000..d924c7e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_ads8v2_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9010_bf_ads8v2_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_ADS8V2_TYPES_H__ +#define __FPGA9010_BF_ADS8V2_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfAds8v2ChanAddr +{ + FPGA9010_BF_ADS8V2 = 0x43040000 +} fpga9010_BfAds8v2ChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_ADS8V2_TYPES_H__ + +/* EOF: fpga9010_bf_ads8v2_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_adv_spi.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_adv_spi.h new file mode 100644 index 0000000..5454514 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_adv_spi.h @@ -0,0 +1,324 @@ +/** + * \file fpga9010_bf_axi_adv_spi.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_AXI_ADV_SPI_H__ +#define __FPGA9010_BF_AXI_ADV_SPI_H__ + +#include "./../../private/include/fpga9010_bf_axi_adv_spi_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_AxiAdvSpiAdvFeat3wireTriPointBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiAdvFeat3wireTriPointBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiAdvFeatClockDivBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, +uint8_t channelId, uint16_t bfValue); +int32_t fpga9010_AxiAdvSpiAdvFeatClockDivBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, +uint8_t channelId, uint16_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiAdvFeatCphaBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiAdvFeatCphaBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiAdvFeatCpolBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiAdvFeatCpolBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiAdvFeatEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiAdvFeatEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiAdvFeatFourWireBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiAdvFeatFourWireBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiAdvFeatLsbFirstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiAdvFeatLsbFirstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiAdvFeatMisoSampleSlipBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiAdvFeatMisoSampleSlipBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiCphaBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiCphaBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiCpolBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiCpolBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiDrrFullBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiDrrFullBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiDrrFullIenBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiDrrFullIenBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiDrrOverrunBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiDrrOverrunBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiDrrOverrunIenBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiDrrOverrunIenBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiDtrEmptyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiDtrEmptyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiDtrEmptyIenBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiDtrEmptyIenBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiGieBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiGieBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiLoopBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiLoopBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiLsbFirstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiLsbFirstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiManSsEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiManSsEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiMasterBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiMasterBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiModfBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiModfFlagBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiModfIenBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiModfIenBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiMstrInhibitBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiMstrInhibitBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint32_t bfValue); + + +int32_t fpga9010_AxiAdvSpiRxDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiRxEmptyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiRxFifoOccupancyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiRxFifoResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + + +int32_t fpga9010_AxiAdvSpiRxFullBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiSlaveSelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_AxiAdvSpiSlaveSelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiSpeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiSpeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiTxDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + + +int32_t fpga9010_AxiAdvSpiTxEmptyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiTxFifoHalfEmptyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiTxFifoHalfEmptyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiTxFifoHalfEmptyIenBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiAdvSpiTxFifoHalfEmptyIenBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiTxFifoOccupancyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiTxFifoResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + + +int32_t fpga9010_AxiAdvSpiTxFullBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiAdvSpiModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint16_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_AXI_ADV_SPI_H__ + +/* EOF: fpga9010_bf_axi_adv_spi.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_adv_spi_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_adv_spi_types.h new file mode 100644 index 0000000..d0e252a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_adv_spi_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9010_bf_axi_adv_spi_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_AXI_ADV_SPI_TYPES_H__ +#define __FPGA9010_BF_AXI_ADV_SPI_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfAxiAdvSpiChanAddr +{ + FPGA9010_BF_AXI_ADV_SPI = 0x44A00000 +} fpga9010_BfAxiAdvSpiChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_AXI_ADV_SPI_TYPES_H__ + +/* EOF: fpga9010_bf_axi_adv_spi_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_memory_pager.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_memory_pager.h new file mode 100644 index 0000000..6a14091 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_memory_pager.h @@ -0,0 +1,59 @@ +/** + * \file fpga9010_bf_axi_memory_pager.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_AXI_MEMORY_PAGER_H__ +#define __FPGA9010_BF_AXI_MEMORY_PAGER_H__ + +#include "./../../private/include/fpga9010_bf_axi_memory_pager_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_AxiMemoryPagerModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiMemoryPagerChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiMemoryPagerModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiMemoryPagerChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_AxiMemoryPagerPageIdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiMemoryPagerChanAddr_e baseAddr, + uint64_t bfValue); +int32_t fpga9010_AxiMemoryPagerPageIdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiMemoryPagerChanAddr_e baseAddr, + uint64_t *bfValue); + + +int32_t fpga9010_AxiMemoryPagerPageSizeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiMemoryPagerChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_AxiMemoryPagerPageSizeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiMemoryPagerChanAddr_e baseAddr, + uint32_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_AXI_MEMORY_PAGER_H__ + +/* EOF: fpga9010_bf_axi_memory_pager.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_memory_pager_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_memory_pager_types.h new file mode 100644 index 0000000..2f4174c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_memory_pager_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9010_bf_axi_memory_pager_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_AXI_MEMORY_PAGER_TYPES_H__ +#define __FPGA9010_BF_AXI_MEMORY_PAGER_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfAxiMemoryPagerChanAddr +{ + FPGA9010_BF_MEMORY_PAGE = 0x43042000 +} fpga9010_BfAxiMemoryPagerChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_AXI_MEMORY_PAGER_TYPES_H__ + +/* EOF: fpga9010_bf_axi_memory_pager_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_tokelau.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_tokelau.h new file mode 100644 index 0000000..a81e76e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_tokelau.h @@ -0,0 +1,305 @@ +/** + * \file fpga9010_bf_axi_tokelau.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_AXI_TOKELAU_H__ +#define __FPGA9010_BF_AXI_TOKELAU_H__ + +#include "./../../private/include/fpga9010_bf_axi_tokelau_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_AxiTokelauAd9528ResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauAd9528ResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauAdrv9010ResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauAdrv9010ResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauDesignIdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpInterrupt0BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpInterrupt0DetCounterBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpInterrupt0DetEdgeLevelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpInterrupt0DetEdgeLevelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpInterrupt0DetPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpInterrupt0DetPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpInterrupt1BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpInterrupt1DetCounterBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpInterrupt1DetEdgeLevelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpInterrupt1DetEdgeLevelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpInterrupt1DetPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpInterrupt1DetPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioEnSpi2BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpioEnSpi2BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioEnTokJtagBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpioEnTokJtagBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioEnTxToOrxBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_AxiTokelauGpioEnTxToOrxBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioInputBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioOutputBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_AxiTokelauGpioOutputBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioSelTx1ToOrx1BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpioSelTx1ToOrx1BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioSelTx1ToOrx2BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpioSelTx1ToOrx2BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioSelTx2ToOrx1BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpioSelTx2ToOrx1BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioSelTx2ToOrx2BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpioSelTx2ToOrx2BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioSelTx3ToOrx3BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpioSelTx3ToOrx3BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioSelTx3ToOrx4BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpioSelTx3ToOrx4BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioSelTx4ToOrx3BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpioSelTx4ToOrx3BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioSelTx4ToOrx4BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpioSelTx4ToOrx4BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioTriggerSrcRxdp00BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpioTriggerSrcRxdp00BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioTriggerSrcRxdp01BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpioTriggerSrcRxdp01BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioTriggerSrcRxdp02BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpioTriggerSrcRxdp02BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioTriggerSrcTxdp00BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpioTriggerSrcTxdp00BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioTriggerSrcTxdp01BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauGpioTriggerSrcTxdp01BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauGpioTristateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_AxiTokelauGpioTristateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_AxiTokelauResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauScratchPadBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_AxiTokelauScratchPadBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_AxiTokelauTestInputBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauTestInputBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauTestOutputBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauTestOutputBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauTestTristateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_AxiTokelauTestTristateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_AxiTokelauVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint16_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_AXI_TOKELAU_H__ + +/* EOF: fpga9010_bf_axi_tokelau.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_tokelau_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_tokelau_types.h new file mode 100644 index 0000000..48bdfda --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_axi_tokelau_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9010_bf_axi_tokelau_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_AXI_TOKELAU_TYPES_H__ +#define __FPGA9010_BF_AXI_TOKELAU_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfAxiTokelauChanAddr +{ + FPGA9010_BF_AXI_TOKELAU = 0x43041000 +} fpga9010_BfAxiTokelauChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_AXI_TOKELAU_TYPES_H__ + +/* EOF: fpga9010_bf_axi_tokelau_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_capture_control.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_capture_control.h new file mode 100644 index 0000000..040f514 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_capture_control.h @@ -0,0 +1,67 @@ +/** + * \file fpga9010_bf_dp_capture_control.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_DP_CAPTURE_CONTROL_H__ +#define __FPGA9010_BF_DP_CAPTURE_CONTROL_H__ + +#include "./../../private/include/fpga9010_bf_dp_capture_control_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_DpCaptureControlDatapathActiveBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpCaptureControlDatapathActiveBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpCaptureControlModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpCaptureControlModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpCaptureControlChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_DpCaptureControlPassTokenBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpCaptureControlPassTokenBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpCaptureControlResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpCaptureControlResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_DP_CAPTURE_CONTROL_H__ + +/* EOF: fpga9010_bf_dp_capture_control.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_capture_control_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_capture_control_types.h new file mode 100644 index 0000000..7b5d2a3 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_capture_control_types.h @@ -0,0 +1,36 @@ +/** + * \file fpga9010_bf_dp_capture_control_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_DP_CAPTURE_CONTROL_TYPES_H__ +#define __FPGA9010_BF_DP_CAPTURE_CONTROL_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfDpCaptureControlChanAddr +{ + FPGA9010_BF_DP_CAPTURE_CONTROL_RX = 0x43100000, + FPGA9010_BF_DP_CAPTURE_CONTROL_TX = 0x43200000 +} fpga9010_BfDpCaptureControlChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_DP_CAPTURE_CONTROL_TYPES_H__ + +/* EOF: fpga9010_bf_dp_capture_control_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_rx_dma.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_rx_dma.h new file mode 100644 index 0000000..14bf925 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_rx_dma.h @@ -0,0 +1,135 @@ +/** + * \file fpga9010_bf_dp_rx_dma.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_DP_RX_DMA_H__ +#define __FPGA9010_BF_DP_RX_DMA_H__ + +#include "./../../private/include/fpga9010_bf_dp_rx_dma_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_DpRxDmaActiveBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpRxDmaCompleteBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpRxDmaEnableEnhancedModeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpRxDmaEnableEnhancedModeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpRxDmaEnableSgBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpRxDmaEnableSgBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpRxDmaHaltCompleteBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpRxDmaLengthBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_DpRxDmaLengthBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_DpRxDmaOverflowBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpRxDmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpRxDmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpRxDmaRunStopBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpRxDmaRunStopBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpRxDmaSgFirstDescriptorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_DpRxDmaSgFirstDescriptorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_DpRxDmaSgLastDescriptorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_DpRxDmaSgLastDescriptorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_DpRxDmaSimpleStartAddrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_DpRxDmaSimpleStartAddrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_DpRxDmaValidDataWidthStreamBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpRxDmaValidDataWidthStreamBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpRxDmaVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpRxDmaVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint16_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_DP_RX_DMA_H__ + +/* EOF: fpga9010_bf_dp_rx_dma.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_rx_dma_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_rx_dma_types.h new file mode 100644 index 0000000..2119e99 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_rx_dma_types.h @@ -0,0 +1,37 @@ +/** + * \file fpga9010_bf_dp_rx_dma_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_DP_RX_DMA_TYPES_H__ +#define __FPGA9010_BF_DP_RX_DMA_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfDpRxDmaChanAddr +{ + FPGA9010_BF_DP_DMA_RX_0 = 0x43101000, + FPGA9010_BF_DP_DMA_RX_1 = 0x43102000, + FPGA9010_BF_DP_DMA_RX_2 = 0x43105000 +} fpga9010_BfDpRxDmaChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_DP_RX_DMA_TYPES_H__ + +/* EOF: fpga9010_bf_dp_rx_dma_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tollgate.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tollgate.h new file mode 100644 index 0000000..1a893fe --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tollgate.h @@ -0,0 +1,75 @@ +/** + * \file fpga9010_bf_dp_tollgate.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_DP_TOLLGATE_H__ +#define __FPGA9010_BF_DP_TOLLGATE_H__ + +#include "./../../private/include/fpga9010_bf_dp_tollgate_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_DpTollgateEdgeLevelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_DpTollgateEdgeLevelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_DpTollgateHighRisingLowFallingBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_DpTollgateHighRisingLowFallingBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_DpTollgateModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpTollgateModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_DpTollgateResetTollgateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpTollgateResetTollgateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpTollgateTriggerSelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_DpTollgateTriggerSelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint32_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_DP_TOLLGATE_H__ + +/* EOF: fpga9010_bf_dp_tollgate.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tollgate_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tollgate_types.h new file mode 100644 index 0000000..6c80fa0 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tollgate_types.h @@ -0,0 +1,39 @@ +/** + * \file fpga9010_bf_dp_tollgate_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_DP_TOLLGATE_TYPES_H__ +#define __FPGA9010_BF_DP_TOLLGATE_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfDpTollgateChanAddr +{ + FPGA9010_BF_DP_TOLLGATE_RX_0 = 0x43103000, + FPGA9010_BF_DP_TOLLGATE_RX_1 = 0x43104000, + FPGA9010_BF_DP_TOLLGATE_RX_2 = 0x43106000, + FPGA9010_BF_DP_TOLLGATE_TX_0 = 0x43202000, + FPGA9010_BF_DP_TOLLGATE_TX_1 = 0x43205000 +} fpga9010_BfDpTollgateChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_DP_TOLLGATE_TYPES_H__ + +/* EOF: fpga9010_bf_dp_tollgate_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tx_dma.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tx_dma.h new file mode 100644 index 0000000..2ed362a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tx_dma.h @@ -0,0 +1,143 @@ +/** + * \file fpga9010_bf_dp_tx_dma.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_DP_TX_DMA_H__ +#define __FPGA9010_BF_DP_TX_DMA_H__ + +#include "./../../private/include/fpga9010_bf_dp_tx_dma_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_DpTxDmaActiveBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpTxDmaCompleteBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpTxDmaContinuousBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpTxDmaContinuousBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpTxDmaEnableEnhancedModeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpTxDmaEnableEnhancedModeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpTxDmaEnableSgBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpTxDmaEnableSgBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpTxDmaHaltCompleteBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpTxDmaLengthBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_DpTxDmaLengthBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_DpTxDmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpTxDmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpTxDmaRunStopBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpTxDmaRunStopBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpTxDmaSgLastDescriptorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_DpTxDmaSgLastDescriptorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_DpTxDmaSimpleStartAddrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_DpTxDmaSimpleStartAddrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_DpTxDmaSqFirstDescriptorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_DpTxDmaSqFirstDescriptorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_DpTxDmaUnderflowBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpTxDmaValidDataWidthStreamBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpTxDmaValidDataWidthStreamBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpTxDmaVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpTxDmaVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint16_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_DP_TX_DMA_H__ + +/* EOF: fpga9010_bf_dp_tx_dma.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tx_dma_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tx_dma_types.h new file mode 100644 index 0000000..e3adc2c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tx_dma_types.h @@ -0,0 +1,36 @@ +/** + * \file fpga9010_bf_dp_tx_dma_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_DP_TX_DMA_TYPES_H__ +#define __FPGA9010_BF_DP_TX_DMA_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfDpTxDmaChanAddr +{ + FPGA9010_BF_DP_DMA_TX_0 = 0x43201000, + FPGA9010_BF_DP_DMA_TX_1 = 0x43204000 +} fpga9010_BfDpTxDmaChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_DP_TX_DMA_TYPES_H__ + +/* EOF: fpga9010_bf_dp_tx_dma_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tx_sof_select.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tx_sof_select.h new file mode 100644 index 0000000..bf37815 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tx_sof_select.h @@ -0,0 +1,67 @@ +/** + * \file fpga9010_bf_dp_tx_sof_select.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_DP_TX_SOF_SELECT_H__ +#define __FPGA9010_BF_DP_TX_SOF_SELECT_H__ + +#include "./../../private/include/fpga9010_bf_dp_tx_sof_select_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_DpTxSofSelectDelayBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpTxSofSelectDelayBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpTxSofSelectModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpTxSofSelectModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxSofSelectChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_DpTxSofSelectResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpTxSofSelectResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_DpTxSofSelectSelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_DpTxSofSelectSelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_DP_TX_SOF_SELECT_H__ + +/* EOF: fpga9010_bf_dp_tx_sof_select.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tx_sof_select_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tx_sof_select_types.h new file mode 100644 index 0000000..bf61494 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_dp_tx_sof_select_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9010_bf_dp_tx_sof_select_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_DP_TX_SOF_SELECT_TYPES_H__ +#define __FPGA9010_BF_DP_TX_SOF_SELECT_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfDpTxSofSelectChanAddr +{ + FPGA9010_BF_DP_TX_SOF_SELECT = 0x43203000 +} fpga9010_BfDpTxSofSelectChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_DP_TX_SOF_SELECT_TYPES_H__ + +/* EOF: fpga9010_bf_dp_tx_sof_select_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_hal.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_hal.h new file mode 100644 index 0000000..c5e18d9 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_hal.h @@ -0,0 +1,46 @@ + +#ifndef FPGA9010_BF_HAL_H_ +#define FPGA9010_BF_HAL_H_ + +#include +#include +#include "adi_common_hal.h" +#include "adi_fpga9010.h" +#include "./../../private/include/fpga9010_bf_hal_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + + +#define BF_LOG_LEVEL 0xF + + +#define ADRV9010_BF_WRCACHE_ARRAY_SIZE 15 +#define ADRV9010_BF_WRCACHE_ARRAY_TRIP_SIZE ADRV9010_BF_WRCACHE_ARRAY_SIZE -2 + +#define ADRV9010_BF_RDCACHE_ARRAY_SIZE 15 +#define ADRV9010_BF_RDCACHE_ARRAY_TRIP_SIZE ADRV9010_BF_RDCACHE_ARRAY_SIZE -2 + + +//int32_t fpga9010_BfWriteCacheEn(adi_fpga9010_Device_t *device, adrv9010_Bf_WrCache_State_e wrCacheState); +//int32_t fpga9010_BfReadCacheEn(adi_fpga9010_Device_t *device, adrv9010_Bf_RdCache_State_e wrCacheState); +int32_t fpga9010_BfReadCacheInit(adi_fpga9010_Device_t *device); +int32_t fpga9010_BfWriteCacheInit(adi_fpga9010_Device_t *device); + +int32_t fpga9010_BfRegisterWrite(adi_fpga9010_Device_t *device, uint32_t addr, uint32_t regVal); +int32_t fpga9010_BfRegisterRead(adi_fpga9010_Device_t *device, uint32_t addr, uint32_t *regVal); + +int32_t fpga9010_BfFieldWrite(adi_fpga9010_Device_t *device, uint32_t addr, uint32_t fieldVal, uint32_t mask, uint8_t startBit); +int32_t fpga9010_BfFieldRead(adi_fpga9010_Device_t *device, uint32_t addr, uint32_t *fieldVal, uint32_t mask, uint8_t startBit); + +int32_t fpga9010_BfReadAssembleData(adi_fpga9010_Device_t *device, uint32_t *rxBfData, uint8_t numRdBfData, uint64_t *rdData); +int32_t fpga9010_BfWriteCacheFlush(adi_fpga9010_Device_t *device); +int32_t fpga9010_BfReadCacheFlush(adi_fpga9010_Device_t *device, uint64_t *rdData, uint16_t *numRxBitFields); + +#ifdef __cplusplus +} +#endif + +#endif /* ADRV9010_BF_HAL_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_hal_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_hal_types.h new file mode 100644 index 0000000..e79d269 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_hal_types.h @@ -0,0 +1,51 @@ +/** +* \brief Contains BitField definitions to support ADRV9010 transceiver device. +* +*/ + +/** +* Disclaimer Legal Disclaimer +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9010 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef __ADRV9010_BF_HAL_TYPES_H__ +#define __ADRV9010_BF_HAL_TYPES_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + + +typedef enum adrv9010_Bf_Error +{ + ADRV9010_BF_NO_ACTION = 10, /*!< BitField function successful. No error Detected */ + ADRV9010_BF_SPI_FAIL, /*!< HAL SPI operation failure. SPI controller Down */ + ADRV9010_BF_CACHE_OVERFLOW /*!< The bitField Cache has exceeded the cache size */ +} adrv9010_Bf_Error_e; + + +typedef enum adrv9010_Bf_WrCache_State +{ + ADRV9010_WR_CACHE_OFF = 0x0, + ADRV9010_WR_HW_RMW_ON = 0x1, + ADRV9010_WR_BF_CACHE_ON = 0x2, + ADRV9010_WR_GLB_CACHE_ON = 0x4, + ADRV9010_WR_GBL_MERGE_ON = 0x8 +} adrv9010_Bf_WrCache_State_e; + + +typedef enum adrv9010_Bf_RdCache_State +{ + ADRV9010_RD_CACHE_OFF = 0x0, + ADRV9010_RD_BF_CACHE_ON = 0x1, + ADRV9010_RD_GLB_CACHE_ON = 0x2 +} adrv9010_Bf_RdCache_State_e; + +#ifdef __cplusplus +} +#endif + +#endif // __ADRV9010_BF_HAL_TYPES_H__ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_phy_tokelau_ads8.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_phy_tokelau_ads8.h new file mode 100644 index 0000000..1312b9f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_phy_tokelau_ads8.h @@ -0,0 +1,3405 @@ +/** + * \file fpga9010_bf_jesd204_phy_tokelau_ads8.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_JESD204_PHY_TOKELAU_ADS8_H__ +#define __FPGA9010_BF_JESD204_PHY_TOKELAU_ADS8_H__ + +#include "./../../private/include/fpga9010_bf_jesd204_phy_tokelau_ads8_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0CpllLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0CpllPdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0CpllPdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0CpllRefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0CpllRefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0GtpowergoodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0GtpowergoodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0LoopbackBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0LoopbackBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0Rx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0Rx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxBufResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxBufResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxCdrlockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxCdrlockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxCommaDetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxCommaDetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmHoldBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmHoldBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmOverrideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmOverrideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsErrCntRstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsErrCntRstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0Tx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0Tx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxDiffControlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxDiffControlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPostcursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPostcursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPrbsInjErrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPrbsInjErrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPrecursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPrecursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1CpllLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1CpllPdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1CpllPdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1CpllRefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1CpllRefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1GtpowergoodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1GtpowergoodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1LoopbackBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1LoopbackBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1Rx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1Rx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxBufResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxBufResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxCdrlockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxCdrlockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxCommaDetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxCommaDetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmHoldBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmHoldBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmOverrideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmOverrideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsErrCntRstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsErrCntRstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1Tx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1Tx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxDiffControlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxDiffControlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPostcursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPostcursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPrbsInjErrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPrbsInjErrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPrecursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPrecursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2CpllLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2CpllPdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2CpllPdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2CpllRefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2CpllRefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2GtpowergoodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2GtpowergoodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2LoopbackBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2LoopbackBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2Rx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2Rx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxBufResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxBufResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxCdrlockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxCdrlockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxCommaDetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxCommaDetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmHoldBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmHoldBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmOverrideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmOverrideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsErrCntRstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsErrCntRstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2Tx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2Tx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxDiffControlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxDiffControlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPostcursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPostcursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPrbsInjErrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPrbsInjErrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPrecursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPrecursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3CpllLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3CpllPdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3CpllPdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3CpllRefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3CpllRefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3GtpowergoodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3GtpowergoodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3LoopbackBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3LoopbackBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3Rx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3Rx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxBufResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxBufResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxCdrlockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxCdrlockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxCommaDetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxCommaDetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmHoldBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmHoldBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmOverrideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmOverrideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsErrCntRstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsErrCntRstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3Tx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3Tx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxDiffControlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxDiffControlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPostcursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPostcursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPrbsInjErrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPrbsInjErrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPrecursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPrecursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4CpllLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4CpllPdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4CpllPdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4CpllRefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4CpllRefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4GtpowergoodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4GtpowergoodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4LoopbackBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4LoopbackBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4Rx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4Rx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxBufResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxBufResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxCdrlockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxCdrlockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxCommaDetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxCommaDetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmHoldBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmHoldBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmOverrideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmOverrideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsErrCntRstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsErrCntRstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4Tx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4Tx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxDiffControlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxDiffControlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPostcursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPostcursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPrbsInjErrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPrbsInjErrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPrecursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPrecursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5CpllLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5CpllPdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5CpllPdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5CpllRefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5CpllRefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5GtpowergoodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5GtpowergoodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5LoopbackBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5LoopbackBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5Rx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5Rx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxBufResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxBufResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxCdrlockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxCdrlockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxCommaDetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxCommaDetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmHoldBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmHoldBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmOverrideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmOverrideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsErrCntRstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsErrCntRstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5Tx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5Tx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxDiffControlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxDiffControlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPostcursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPostcursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPrbsInjErrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPrbsInjErrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPrecursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPrecursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6CpllLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6CpllPdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6CpllPdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6CpllRefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6CpllRefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6GtpowergoodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6GtpowergoodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6LoopbackBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6LoopbackBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6Rx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6Rx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxBufResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxBufResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxCdrlockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxCdrlockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxCommaDetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxCommaDetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmHoldBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmHoldBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmOverrideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmOverrideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsErrCntRstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsErrCntRstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6Tx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6Tx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxDiffControlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxDiffControlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPostcursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPostcursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPrbsInjErrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPrbsInjErrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPrecursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPrecursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7CpllLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7CpllPdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7CpllPdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7CpllRefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7CpllRefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7GtpowergoodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7GtpowergoodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7LoopbackBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7LoopbackBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7Rx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7Rx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxBufResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxBufResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxCdrlockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxCdrlockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxCommaDetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxCommaDetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmHoldBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmHoldBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmOverrideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmOverrideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsErrCntRstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsErrCntRstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7Tx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7Tx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxDiffControlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxDiffControlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPostcursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPostcursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPrbsInjErrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPrbsInjErrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPrecursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPrecursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8MmcmRefclkSelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8MmcmRefclkSelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8ModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8ModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0LockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0PdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0PdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0RefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0RefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0ResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0ResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1LockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1PdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1PdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1RefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1RefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1ResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1ResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0LockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0PdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0PdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0RefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0RefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0ResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0ResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1LockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1PdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1PdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1RefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1RefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1ResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1ResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_JESD204_PHY_TOKELAU_ADS8_H__ + +/* EOF: fpga9010_bf_jesd204_phy_tokelau_ads8.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_phy_tokelau_ads8_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_phy_tokelau_ads8_types.h new file mode 100644 index 0000000..9942aa6 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_phy_tokelau_ads8_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9010_bf_jesd204_phy_tokelau_ads8_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_JESD204_PHY_TOKELAU_ADS8_TYPES_H__ +#define __FPGA9010_BF_JESD204_PHY_TOKELAU_ADS8_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfJesd204PhyTokelauAds8ChanAddr +{ + FPGA9010_BF_TOKELAU_JESD_PHY = 0x43400000 +} fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_JESD204_PHY_TOKELAU_ADS8_TYPES_H__ + +/* EOF: fpga9010_bf_jesd204_phy_tokelau_ads8_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_rx_lane_xbar.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_rx_lane_xbar.h new file mode 100644 index 0000000..588928e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_rx_lane_xbar.h @@ -0,0 +1,307 @@ +/** + * \file fpga9010_bf_jesd204_rx_lane_xbar.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_JESD204_RX_LANE_XBAR_H__ +#define __FPGA9010_BF_JESD204_RX_LANE_XBAR_H__ + +#include "./../../private/include/fpga9010_bf_jesd204_rx_lane_xbar_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_Jesd204RxLaneXbarLane0SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane0SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane10SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane10SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane11SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane11SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane12SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane12SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane13SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane13SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane14SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane14SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane15SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane15SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane16SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane16SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane17SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane17SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane18SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane18SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane19SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane19SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane1SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane1SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane20SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane20SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane21SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane21SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane22SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane22SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane23SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane23SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane24SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane24SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane25SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane25SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane26SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane26SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane27SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane27SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane28SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane28SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane29SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane29SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane2SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane2SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane30SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane30SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane31SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane31SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane3SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane3SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane4SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane4SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane5SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane5SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane6SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane6SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane7SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane7SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane8SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane8SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLane9SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLane9SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarLaneResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_Jesd204RxLaneXbarLaneResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204RxLaneXbarModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint16_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_JESD204_RX_LANE_XBAR_H__ + +/* EOF: fpga9010_bf_jesd204_rx_lane_xbar.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_rx_lane_xbar_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_rx_lane_xbar_types.h new file mode 100644 index 0000000..ea1e890 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_rx_lane_xbar_types.h @@ -0,0 +1,37 @@ +/** + * \file fpga9010_bf_jesd204_rx_lane_xbar_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_JESD204_RX_LANE_XBAR_TYPES_H__ +#define __FPGA9010_BF_JESD204_RX_LANE_XBAR_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfJesd204RxLaneXbarChanAddr +{ + FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0 = 0x43405000, + FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1 = 0x43406000, + FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2 = 0x4340B000 +} fpga9010_BfJesd204RxLaneXbarChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_JESD204_RX_LANE_XBAR_TYPES_H__ + +/* EOF: fpga9010_bf_jesd204_rx_lane_xbar_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_sysref_control.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_sysref_control.h new file mode 100644 index 0000000..bea4179 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_sysref_control.h @@ -0,0 +1,112 @@ +/** + * \file fpga9010_bf_jesd204_sysref_control.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_JESD204_SYSREF_CONTROL_H__ +#define __FPGA9010_BF_JESD204_SYSREF_CONTROL_H__ + +#include "./../../private/include/fpga9010_bf_jesd204_sysref_control_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_Jesd204SysrefControlExtSysrefPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204SysrefControlExtSysrefPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204SysrefControlExtSysrefRequestBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204SysrefControlExtSysrefRequestBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204SysrefControlExtSysrefSampleEdgeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204SysrefControlExtSysrefSampleEdgeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204SysrefControlIntSysrefEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204SysrefControlIntSysrefEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204SysrefControlIntSysrefFreerunBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204SysrefControlIntSysrefFreerunBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204SysrefControlIntSysrefGenPeriodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_Jesd204SysrefControlIntSysrefGenPeriodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204SysrefControlIntSysrefRequestBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204SysrefControlIntSysrefRequestBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204SysrefControlModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204SysrefControlModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204SysrefControlOutputEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_Jesd204SysrefControlOutputEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204SysrefControlSysrefReceivedBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_JESD204_SYSREF_CONTROL_H__ + +/* EOF: fpga9010_bf_jesd204_sysref_control.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_sysref_control_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_sysref_control_types.h new file mode 100644 index 0000000..0917778 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_sysref_control_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9010_bf_jesd204_sysref_control_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_JESD204_SYSREF_CONTROL_TYPES_H__ +#define __FPGA9010_BF_JESD204_SYSREF_CONTROL_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfJesd204SysrefControlChanAddr +{ + FPGA9010_BF_JESD204_SYSREF_CONTROL = 0x43402000 +} fpga9010_BfJesd204SysrefControlChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_JESD204_SYSREF_CONTROL_TYPES_H__ + +/* EOF: fpga9010_bf_jesd204_sysref_control_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_tx_lane_xbar.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_tx_lane_xbar.h new file mode 100644 index 0000000..656b88c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_tx_lane_xbar.h @@ -0,0 +1,307 @@ +/** + * \file fpga9010_bf_jesd204_tx_lane_xbar.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_JESD204_TX_LANE_XBAR_H__ +#define __FPGA9010_BF_JESD204_TX_LANE_XBAR_H__ + +#include "./../../private/include/fpga9010_bf_jesd204_tx_lane_xbar_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_Jesd204TxLaneXbarLane0SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane0SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane10SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane10SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane11SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane11SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane12SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane12SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane13SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane13SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane14SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane14SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane15SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane15SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane16SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane16SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane17SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane17SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane18SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane18SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane19SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane19SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane1SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane1SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane20SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane20SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane21SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane21SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane22SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane22SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane23SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane23SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane24SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane24SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane25SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane25SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane26SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane26SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane27SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane27SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane28SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane28SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane29SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane29SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane2SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane2SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane30SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane30SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane31SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane31SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane3SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane3SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane4SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane4SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane5SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane5SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane6SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane6SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane7SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane7SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane8SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane8SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLane9SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLane9SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarLaneResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_Jesd204TxLaneXbarLaneResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204TxLaneXbarModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint16_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_JESD204_TX_LANE_XBAR_H__ + +/* EOF: fpga9010_bf_jesd204_tx_lane_xbar.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_tx_lane_xbar_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_tx_lane_xbar_types.h new file mode 100644 index 0000000..d1bf5eb --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204_tx_lane_xbar_types.h @@ -0,0 +1,36 @@ +/** + * \file fpga9010_bf_jesd204_tx_lane_xbar_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_JESD204_TX_LANE_XBAR_TYPES_H__ +#define __FPGA9010_BF_JESD204_TX_LANE_XBAR_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfJesd204TxLaneXbarChanAddr +{ + FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0 = 0x43407000, + FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1 = 0x4340C000 +} fpga9010_BfJesd204TxLaneXbarChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_JESD204_TX_LANE_XBAR_TYPES_H__ + +/* EOF: fpga9010_bf_jesd204_tx_lane_xbar_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204b_sync_xbar.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204b_sync_xbar.h new file mode 100644 index 0000000..228930d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204b_sync_xbar.h @@ -0,0 +1,115 @@ +/** + * \file fpga9010_bf_jesd204b_sync_xbar.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_JESD204B_SYNC_XBAR_H__ +#define __FPGA9010_BF_JESD204B_SYNC_XBAR_H__ + +#include "./../../private/include/fpga9010_bf_jesd204b_sync_xbar_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_Jesd204bSyncXbarModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204bSyncXbarModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_Jesd204bSyncXbarSyncInPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204bSyncXbarSyncInPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204bSyncXbarSyncOut0SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204bSyncXbarSyncOut0SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204bSyncXbarSyncOut1SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204bSyncXbarSyncOut1SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204bSyncXbarSyncOut2SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204bSyncXbarSyncOut2SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204bSyncXbarSyncOut3SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204bSyncXbarSyncOut3SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204bSyncXbarSyncOut4SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204bSyncXbarSyncOut4SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204bSyncXbarSyncOut5SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204bSyncXbarSyncOut5SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204bSyncXbarSyncOut6SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204bSyncXbarSyncOut6SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_Jesd204bSyncXbarSyncOut7SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_Jesd204bSyncXbarSyncOut7SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_JESD204B_SYNC_XBAR_H__ + +/* EOF: fpga9010_bf_jesd204b_sync_xbar.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204b_sync_xbar_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204b_sync_xbar_types.h new file mode 100644 index 0000000..a55c564 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_jesd204b_sync_xbar_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9010_bf_jesd204b_sync_xbar_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_JESD204B_SYNC_XBAR_TYPES_H__ +#define __FPGA9010_BF_JESD204B_SYNC_XBAR_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfJesd204bSyncXbarChanAddr +{ + FPGA9010_BF_JESD204B_SYNC_XBAR = 0x43401000 +} fpga9010_BfJesd204bSyncXbarChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_JESD204B_SYNC_XBAR_TYPES_H__ + +/* EOF: fpga9010_bf_jesd204b_sync_xbar_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_orx_pin_encode_tokelau.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_orx_pin_encode_tokelau.h new file mode 100644 index 0000000..81cbb22 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_orx_pin_encode_tokelau.h @@ -0,0 +1,115 @@ +/** + * \file fpga9010_bf_orx_pin_encode_tokelau.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_ORX_PIN_ENCODE_TOKELAU_H__ +#define __FPGA9010_BF_ORX_PIN_ENCODE_TOKELAU_H__ + +#include "./../../private/include/fpga9010_bf_orx_pin_encode_tokelau_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_OrxPinEncodeTokelauFastSwitchingEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_OrxPinEncodeTokelauFastSwitchingEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_OrxPinEncodeTokelauMode1aOrxSelectHighBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_OrxPinEncodeTokelauMode1aOrxSelectHighBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_OrxPinEncodeTokelauMode1aOrxSelectLowBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_OrxPinEncodeTokelauMode1aOrxSelectLowBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_OrxPinEncodeTokelauMode3OrxSelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_OrxPinEncodeTokelauMode3OrxSelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_OrxPinEncodeTokelauModeSelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_OrxPinEncodeTokelauModeSelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_OrxPinEncodeTokelauOrxEnableHighTimeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_OrxPinEncodeTokelauOrxEnableHighTimeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_OrxPinEncodeTokelauOrxEnableLowTimeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_OrxPinEncodeTokelauOrxEnableLowTimeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_OrxPinEncodeTokelauOrxSelectSetupTimeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_OrxPinEncodeTokelauOrxSelectSetupTimeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_OrxPinEncodeTokelauResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_OrxPinEncodeTokelauResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_OrxPinEncodeTokelauVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_OrxPinEncodeTokelauVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_ORX_PIN_ENCODE_TOKELAU_H__ + +/* EOF: fpga9010_bf_orx_pin_encode_tokelau.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_orx_pin_encode_tokelau_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_orx_pin_encode_tokelau_types.h new file mode 100644 index 0000000..b726a49 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_orx_pin_encode_tokelau_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9010_bf_orx_pin_encode_tokelau_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_ORX_PIN_ENCODE_TOKELAU_TYPES_H__ +#define __FPGA9010_BF_ORX_PIN_ENCODE_TOKELAU_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfOrxPinEncodeTokelauChanAddr +{ + FPGA9010_BF_TDD_ORX_PIN_ENCODE = 0x43318000 +} fpga9010_BfOrxPinEncodeTokelauChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_ORX_PIN_ENCODE_TOKELAU_TYPES_H__ + +/* EOF: fpga9010_bf_orx_pin_encode_tokelau_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_orxpinencodetokelau_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_orxpinencodetokelau_types.h new file mode 100644 index 0000000..ecb2a40 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_orxpinencodetokelau_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9010_bf_orxpinencodetokelau_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_ORXPINENCODETOKELAU_TYPES_H__ +#define __FPGA9010_BF_ORXPINENCODETOKELAU_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfOrxPinEncodetokelauChanAddr +{ + FPGA9010_BF_TDD_ORX_PIN_ENCODE = 0x43318000 +} fpga9010_BfOrx pin encode tokelauChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_ORXPINENCODETOKELAU_TYPES_H__ + +/* EOF: fpga9010_bf_orxpinencodetokelau_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_dp_ctrl.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_dp_ctrl.h new file mode 100644 index 0000000..01504a0 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_dp_ctrl.h @@ -0,0 +1,59 @@ +/** + * \file fpga9010_bf_tdd_dp_ctrl.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_TDD_DP_CTRL_H__ +#define __FPGA9010_BF_TDD_DP_CTRL_H__ + +#include "./../../private/include/fpga9010_bf_tdd_dp_ctrl_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_TddDpCtrlEnableBitBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddDpCtrlChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_TddDpCtrlEnableBitBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddDpCtrlChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_TddDpCtrlStartValueBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddDpCtrlChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_TddDpCtrlStartValueBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddDpCtrlChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_TddDpCtrlVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddDpCtrlChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_TddDpCtrlVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddDpCtrlChanAddr_e baseAddr, + uint16_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_TDD_DP_CTRL_H__ + +/* EOF: fpga9010_bf_tdd_dp_ctrl.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_dp_ctrl_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_dp_ctrl_types.h new file mode 100644 index 0000000..69f65c9 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_dp_ctrl_types.h @@ -0,0 +1,39 @@ +/** + * \file fpga9010_bf_tdd_dp_ctrl_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_TDD_DP_CTRL_TYPES_H__ +#define __FPGA9010_BF_TDD_DP_CTRL_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfTddDpCtrlChanAddr +{ + FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_0 = 0x43315000, + FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_1 = 0x43316000, + FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_0 = 0x43317000, + FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_2 = 0x43319000, + FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_1 = 0x4331A000 +} fpga9010_BfTddDpCtrlChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_TDD_DP_CTRL_TYPES_H__ + +/* EOF: fpga9010_bf_tdd_dp_ctrl_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_enable_ctrl.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_enable_ctrl.h new file mode 100644 index 0000000..2f5c3c0 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_enable_ctrl.h @@ -0,0 +1,123 @@ +/** + * \file fpga9010_bf_tdd_enable_ctrl.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_TDD_ENABLE_CTRL_H__ +#define __FPGA9010_BF_TDD_ENABLE_CTRL_H__ + +#include "./../../private/include/fpga9010_bf_tdd_enable_ctrl_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_TddEnableCtrlEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_TddEnableCtrlEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_TddEnableCtrlEndValueBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_TddEnableCtrlEndValueBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_TddEnableCtrlFramesActiveBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_TddEnableCtrlFramesActiveBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_TddEnableCtrlFramesInactiveBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_TddEnableCtrlFramesInactiveBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_TddEnableCtrlFramesOffsetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_TddEnableCtrlFramesOffsetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_TddEnableCtrlManualEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_TddEnableCtrlManualEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_TddEnableCtrlSecEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_TddEnableCtrlSecEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_TddEnableCtrlSecEndValueBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_TddEnableCtrlSecEndValueBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_TddEnableCtrlSecStartValueBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_TddEnableCtrlSecStartValueBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_TddEnableCtrlStartValueBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_TddEnableCtrlStartValueBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_TddEnableCtrlVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_TddEnableCtrlVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint16_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_TDD_ENABLE_CTRL_H__ + +/* EOF: fpga9010_bf_tdd_enable_ctrl.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_enable_ctrl_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_enable_ctrl_types.h new file mode 100644 index 0000000..3cf16ee --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_enable_ctrl_types.h @@ -0,0 +1,58 @@ +/** + * \file fpga9010_bf_tdd_enable_ctrl_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_TDD_ENABLE_CTRL_TYPES_H__ +#define __FPGA9010_BF_TDD_ENABLE_CTRL_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfTddEnableCtrlChanAddr +{ + FPGA9010_BF_TDD_ENABLE_CONTROL_RX1 = 0x43301000, + FPGA9010_BF_TDD_ENABLE_CONTROL_RX2 = 0x43302000, + FPGA9010_BF_TDD_ENABLE_CONTROL_RX3 = 0x43303000, + FPGA9010_BF_TDD_ENABLE_CONTROL_RX4 = 0x43304000, + FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1 = 0x43305000, + FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2 = 0x43306000, + FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3 = 0x43307000, + FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4 = 0x43308000, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX1 = 0x43309000, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX2 = 0x4330A000, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX3 = 0x4330B000, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX4 = 0x4330C000, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1 = 0x4330D000, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1 = 0x4330E000, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2 = 0x4330F000, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2 = 0x43310000, + FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1 = 0x43311000, + FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2 = 0x43312000, + FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3 = 0x43313000, + FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4 = 0x43314000, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3 = 0x4331B000, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3 = 0x4331C000, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4 = 0x4331D000, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4 = 0x4331E000 +} fpga9010_BfTddEnableCtrlChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_TDD_ENABLE_CTRL_TYPES_H__ + +/* EOF: fpga9010_bf_tdd_enable_ctrl_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_frame_cnt.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_frame_cnt.h new file mode 100644 index 0000000..181e999 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_frame_cnt.h @@ -0,0 +1,83 @@ +/** + * \file fpga9010_bf_tdd_frame_cnt.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_TDD_FRAME_CNT_H__ +#define __FPGA9010_BF_TDD_FRAME_CNT_H__ + +#include "./../../private/include/fpga9010_bf_tdd_frame_cnt_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_TddFrameCntEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_TddFrameCntEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_TddFrameCntEndValueBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_TddFrameCntEndValueBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_TddFrameCntLoopCountBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_TddFrameCntLoopCountBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_TddFrameCntLoopCountEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_TddFrameCntLoopCountEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_TddFrameCntTriggerBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_TddFrameCntTriggerBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_TddFrameCntVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_TddFrameCntVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint16_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_TDD_FRAME_CNT_H__ + +/* EOF: fpga9010_bf_tdd_frame_cnt.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_frame_cnt_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_frame_cnt_types.h new file mode 100644 index 0000000..d2efaf4 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_tdd_frame_cnt_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9010_bf_tdd_frame_cnt_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_TDD_FRAME_CNT_TYPES_H__ +#define __FPGA9010_BF_TDD_FRAME_CNT_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfTddFrameCntChanAddr +{ + FPGA9010_BF_TDD_FRAME_COUNTER = 0x43300000 +} fpga9010_BfTddFrameCntChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_TDD_FRAME_CNT_TYPES_H__ + +/* EOF: fpga9010_bf_tdd_frame_cnt_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_clock_wizard.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_clock_wizard.h new file mode 100644 index 0000000..50c1745 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_clock_wizard.h @@ -0,0 +1,288 @@ +/** + * \file fpga9010_bf_xilinx_clock_wizard.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_XILINX_CLOCK_WIZARD_H__ +#define __FPGA9010_BF_XILINX_CLOCK_WIZARD_H__ + +#include "./../../private/include/fpga9010_bf_xilinx_clock_wizard_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_XilinxClockWizardClkfboutFracBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_XilinxClockWizardClkfboutFracBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkfboutMultBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxClockWizardClkfboutMultBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkfboutPhaseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardClkfboutPhaseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout0DivideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout0DivideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout0DutyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout0DutyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout0FracBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout0FracBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout0PhaseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout0PhaseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout1DivideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout1DivideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout1DutyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout1DutyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout1PhaseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout1PhaseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout2DivideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout2DivideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout2DutyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout2DutyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout2PhaseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout2PhaseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout3DivideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout3DivideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout3DutyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout3DutyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout3PhaseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout3PhaseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout4DivideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout4DivideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout4DutyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout4DutyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout4PhaseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout4PhaseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout5DivideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout5DivideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout5DutyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout5DutyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout5PhaseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout5PhaseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout6DivideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout6DivideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout6DutyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout6DutyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardClkout6PhaseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardClkout6PhaseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardDivclkDivideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxClockWizardDivclkDivideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardErrorStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardInterruptEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardInterruptEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardInterruptStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); +int32_t fpga9010_XilinxClockWizardInterruptStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardLoadBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxClockWizardLoadBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardLockedBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardSaddrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxClockWizardSaddrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxClockWizardSoftwareResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_XILINX_CLOCK_WIZARD_H__ + +/* EOF: fpga9010_bf_xilinx_clock_wizard.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_clock_wizard_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_clock_wizard_types.h new file mode 100644 index 0000000..24c39b4 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_clock_wizard_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9010_bf_xilinx_clock_wizard_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_XILINX_CLOCK_WIZARD_TYPES_H__ +#define __FPGA9010_BF_XILINX_CLOCK_WIZARD_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfXilinxClockWizardChanAddr +{ + FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD = 0x43403000 +} fpga9010_BfXilinxClockWizardChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_XILINX_CLOCK_WIZARD_TYPES_H__ + +/* EOF: fpga9010_bf_xilinx_clock_wizard_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_jesd204b.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_jesd204b.h new file mode 100644 index 0000000..77d52a9 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_jesd204b.h @@ -0,0 +1,486 @@ +/** + * \file fpga9010_bf_xilinx_jesd204b.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_XILINX_JESD204B_H__ +#define __FPGA9010_BF_XILINX_JESD204B_H__ + +#include "./../../private/include/fpga9010_bf_xilinx_jesd204b_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_XilinxJesd204bCfgFBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bCfgFBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bCfgKBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bCfgKBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bCfgLaneIdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bCfgLaneIdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bCfgSubclassvBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bCfgSubclassvBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bDisErrOnSyncBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bDisErrOnSyncBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaAdjcntBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaAdjcntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaAdjdirBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaAdjdirBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaBidBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaBidBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaCfBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaCfBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaCsBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaCsBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaDidBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaDidBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaFBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaFchkBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaFchkBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaHdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaHdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaJesdvBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaKBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaLBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaLidBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaMBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaMBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaMultiframesBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaMultiframesBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaNBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaNBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaNpBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaNpBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaPhadjBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaPhadjBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaRes1BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaRes1BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaRes2BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaRes2BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaSBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaSBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaScrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaSubclassBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bIlaSupportEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bIlaSupportEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLaneAlignAlarmBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLanesInUseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bLanesInUseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkDebugStatusLane0BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkDebugStatusLane1BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkDebugStatusLane2BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkDebugStatusLane3BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkDebugStatusLane4BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkDebugStatusLane5BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkDebugStatusLane6BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkDebugStatusLane7BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkErrCntBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint32_t bfValue); +int32_t fpga9010_XilinxJesd204bLinkErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint32_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkErrCntrsEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bLinkErrCntrsEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkErrorStatusLane0BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkErrorStatusLane1BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkErrorStatusLane2BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkErrorStatusLane3BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkErrorStatusLane4BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkErrorStatusLane5BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkErrorStatusLane6BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bLinkErrorStatusLane7BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bResetFixedBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bResetFixedBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bResetSelfClearingBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bResetSelfClearingBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bRxBufAdjBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint16_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bRxBufferDelayBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint16_t bfValue); +int32_t fpga9010_XilinxJesd204bRxBufferDelayBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint16_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bRxBufferOvrfAlarmBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bScramblingEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bScramblingEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bSyncStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bSysrefAlwaysBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bSysrefAlwaysBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bSysrefCapturedBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bSysrefDelayBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bSysrefDelayBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bSysrefLmfcAlarmBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bSysrefRequiredOnResyncBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bSysrefRequiredOnResyncBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bTestModeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bTestModeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bTestModeErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint32_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bTestModeIlaCntBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint32_t bfValue); +int32_t fpga9010_XilinxJesd204bTestModeIlaCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint32_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bTestModeMfCntBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint32_t bfValue); +int32_t fpga9010_XilinxJesd204bTestModeMfCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, +uint8_t channelId, uint32_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bVersionRevisionBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204bWatchdogTimerDisableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204bWatchdogTimerDisableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_XILINX_JESD204B_H__ + +/* EOF: fpga9010_bf_xilinx_jesd204b.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_jesd204b_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_jesd204b_types.h new file mode 100644 index 0000000..d619cab --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_jesd204b_types.h @@ -0,0 +1,39 @@ +/** + * \file fpga9010_bf_xilinx_jesd204b_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_XILINX_JESD204B_TYPES_H__ +#define __FPGA9010_BF_XILINX_JESD204B_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfXilinxJesd204bChanAddr +{ + FPGA9010_BF_JESD204B_DEFRAMER_0 = 0x43408000, + FPGA9010_BF_JESD204B_DEFRAMER_1 = 0x43409000, + FPGA9010_BF_JESD204B_FRAMER_0 = 0x4340A000, + FPGA9010_BF_JESD204B_DEFRAMER_2 = 0x4340D000, + FPGA9010_BF_JESD204B_FRAMER_1 = 0x4340E000 +} fpga9010_BfXilinxJesd204bChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_XILINX_JESD204B_TYPES_H__ + +/* EOF: fpga9010_bf_xilinx_jesd204b_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_jesd204c.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_jesd204c.h new file mode 100644 index 0000000..f55fa44 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_jesd204c.h @@ -0,0 +1,321 @@ +/** + * \file fpga9010_bf_xilinx_jesd204c.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_XILINX_JESD204C_H__ +#define __FPGA9010_BF_XILINX_JESD204C_H__ + +#include "./../../private/include/fpga9010_bf_xilinx_jesd204c_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C"{ +#endif + + +int32_t fpga9010_XilinxJesd204cBufferLevelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, +uint8_t channelId, uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cBufferOverflowBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cCfgMbInEmbBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cCfgMbInEmbBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cCfgSubclassvBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cCfgSubclassvBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cCoreIsTxBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cEnableCmdInterfaceBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cEnableCmdInterfaceBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cEnableDataInterfaceBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cEnableDataInterfaceBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqBlockSyncErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqCrcErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqEnBlockSyncErrorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cIrqEnBlockSyncErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqEnCrcErrorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cIrqEnCrcErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqEnFecErrorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cIrqEnFecErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqEnGlobalBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cIrqEnGlobalBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqEnLossMbLockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cIrqEnLossMbLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqEnLossSyncHeaderLockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cIrqEnLossSyncHeaderLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqEnMbErrorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cIrqEnMbErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqEnOverflowErrorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cIrqEnOverflowErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqEnSysrefErrorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cIrqEnSysrefErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqEnSysrefReceivedBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cIrqEnSysrefReceivedBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqFecErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqLossMbLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqLossSyncHeaderLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqMbErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqOverflowErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqPendingBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqSysrefErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cIrqSysrefReceivedBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cLane64b66bAlignBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cLaneEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cLaneEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cLaneMbAlignBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cMbLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cMetaModeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cMetaModeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cNumberOfLanesInCoreBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cResetFixedBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cResetFixedBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cRxBufferDelayBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cRxBufferDelayBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cRxErrorCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, +uint8_t channelId, uint32_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cRxMbThBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cRxMbThBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cSyncHeaderLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cSysrefCapturedBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cSysrefDelayBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cSysrefDelayBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cSysrefErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cTestModeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); +int32_t fpga9010_XilinxJesd204cTestModeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + + +int32_t fpga9010_XilinxJesd204cVersionRevisionBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_XILINX_JESD204C_H__ + +/* EOF: fpga9010_bf_xilinx_jesd204c.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_jesd204c_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_jesd204c_types.h new file mode 100644 index 0000000..f21408d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_bf_xilinx_jesd204c_types.h @@ -0,0 +1,39 @@ +/** + * \file fpga9010_bf_xilinx_jesd204c_types.h Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9010_BF_XILINX_JESD204C_TYPES_H__ +#define __FPGA9010_BF_XILINX_JESD204C_TYPES_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum fpga9010_BfXilinxJesd204cChanAddr +{ + FPGA9010_BF_JESD204C_DEFRAMER_0 = 0x43410000, + FPGA9010_BF_JESD204C_DEFRAMER_1 = 0x43411000, + FPGA9010_BF_JESD204C_DEFRAMER_2 = 0x43412000, + FPGA9010_BF_JESD204C_FRAMER_0 = 0x43413000, + FPGA9010_BF_JESD204C_FRAMER_1 = 0x43414000 +} fpga9010_BfXilinxJesd204cChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9010_BF_XILINX_JESD204C_TYPES_H__ + +/* EOF: fpga9010_bf_xilinx_jesd204c_types.h */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_jesd.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_jesd.h new file mode 100644 index 0000000..a68547d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_jesd.h @@ -0,0 +1,381 @@ +/** +* \file fpga9010_jesd.h +* \brief Contains private JESD related function prototypes for fpga9010_jesd.c +* +* FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ +*/ +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _FPGA9010_JESD_H_ +#define _FPGA9010_JESD_H_ + +#include "adi_fpga9010_user.h" +#include "adi_fpga9010_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief JESD204B implementation for adi_fpga9010_DeframerCfgSet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param deframerCfg a pointer to an adi_fpga9010_DeframerCfg_t structure that contains the deframer configuration settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204BDeframerCfgSet(adi_fpga9010_Device_t *device, uint32_t deframerSelMask, adi_fpga9010_DeframerCfg_t *deframerCfg); + +/** +* \brief JESD204B implementation for adi_fpga9010_DeframerCfgGet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param deframerSel an adi_fpga9010_DeframerSel_e enum value selecting which deframer to read +* \param deframerCfg a pointer to an empty adi_fpga9010_DeframerCfg_t structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204BDeframerCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e deframerSel, adi_fpga9010_DeframerCfg_t *deframerCfg); + +/** +* \brief JESD204B implementation for adi_fpga9010_FramerCfgSet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param framerCfg pointer to an adi_fpga9010_FramerCfg_t structure that contains the deserializer configuration settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204BFramerCfgSet(adi_fpga9010_Device_t *device, uint8_t framerSelMask, adi_fpga9010_FramerCfg_t *framerCfg); + +/** +* \brief JESD204B implementation for adi_fpga9010_FramerCfgGet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSel an adi_fpga9010_FramerSel_e enum value selecting a single framer +* \param framerCfg pointer to an empty adi_fpga9010_FramerCfg_t structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204BFramerCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e framerSel, adi_fpga9010_FramerCfg_t *framerCfg); + +/** +* \brief JESD204B helper function for FramerResetGet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param resetBits uint8_t pointer for the reset bits of the selected deframers that will correspond with their adi_fpga9010_FramerSel_e bit locations +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204BFramerResetGet(adi_fpga9010_Device_t *device, uint32_t framerSelMask, uint8_t *resetBits); + +/** +* \brief JESD204B helper function for FramerReset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204BFramerReset(adi_fpga9010_Device_t *device, uint8_t framerSelMask); + +/** +* \brief JESD204B helper function for DeframerReset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204BDeframerReset(adi_fpga9010_Device_t *device, uint8_t deframerSelMask); + +/** +* \brief JESD204B helper function for DeframerDisable. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204BDeframerDisable(adi_fpga9010_Device_t *device, uint8_t deframerSelMask); + +/** +* \brief JESD204B helper function for FramerDisable. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204BFramerDisable(adi_fpga9010_Device_t *device, uint8_t framerSelMask); + +/** +* \brief JESD204B helper function for DeframerStatusGet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param status uint8_t pointer for the Sync status bits of the selected deframers that will correspond with their adi_fpga9010_DeframerSel_e bit locations +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204BDeframerStatusGet(adi_fpga9010_Device_t *device, uint8_t deframerSelMask, uint8_t *status); + +/** +* \brief JESD204C implementation for adi_fpga9010_DeframerCfgSet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param deframerCfg a pointer to an adi_fpga9010_DeframerCfg_t structure that contains the deframer configuration settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204CDeframerCfgSet(adi_fpga9010_Device_t *device, uint32_t deframerSelMask, adi_fpga9010_DeframerCfg_t *deframerCfg); + +/** +* \brief JESD204C implementation for adi_fpga9010_DeframerCfgGet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device pointer to the FPGA9010 device data structure. +* \param deframerSel an adi_fpga9010_DeframerSel_e enum value selecting which deframer to read +* \param deframerCfg a pointer to an empty adi_fpga9010_DeframerCfg_t structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204CDeframerCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e deframerSel, adi_fpga9010_DeframerCfg_t *deframerCfg); + + +/** +* \brief JESD204C implementation for adi_fpga9010_FramerCfgSet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param framerCfg pointer to an adi_fpga9010_FramerCfg_t structure that contains the deserializer configuration settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204CFramerCfgSet(adi_fpga9010_Device_t *device, uint32_t framerSelMask, adi_fpga9010_FramerCfg_t *framerCfg); + +/** +* \brief JESD204C implementation for adi_fpga9010_FramerCfgGet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSel an adi_fpga9010_FramerSel_e enum value selecting a single framer +* \param framerCfg pointer to an empty adi_fpga9010_FramerCfg_t structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204CFramerCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e framerSel, adi_fpga9010_FramerCfg_t *framerCfg); + +/** +* \brief JESD204C helper function for FramerResetGet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param resetBits uint8_t pointer to reset bits of the selected deframers which will correspond with their adi_fpga9010_FramerSel_e bit locations +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204CFramerResetGet(adi_fpga9010_Device_t *device, uint32_t framerSelMask, uint8_t *resetBits); + +/** +* \brief JESD204C helper function for FramerReset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204CFramerReset(adi_fpga9010_Device_t *device, uint8_t framerSelMask); + +/** +* \brief JESD204C helper function for DeframerReset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204CDeframerReset(adi_fpga9010_Device_t *device, uint8_t deframerSelMask); + +/** +* \brief JESD204C helper function for DeframerDisable. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204CDeframerDisable(adi_fpga9010_Device_t *device, uint8_t deframerSelMask); + +/** +* \brief JESD204C helper function for FramerDisable. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204CFramerDisable(adi_fpga9010_Device_t *device, uint8_t framerSelMask); + +/** +* \brief JESD204C helper function for DeframerStatusGet. The status bit for each link will be a logical +* and of mb_lock & sync_header_lock bitfield values. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param status uint8_t pointer for the Sync status bits of the selected deframers that will correspond with their adi_fpga9010_DeframerSel_e bit locations +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_Jesd204CDeframerStatusGet(adi_fpga9010_Device_t *device, uint8_t deframerSelMask, uint8_t *status); + +#ifdef __cplusplus +} +#endif + +#endif /* _FPGA9010_JESD_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_tdd.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_tdd.h new file mode 100644 index 0000000..a190a14 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/include/fpga9010_tdd.h @@ -0,0 +1,66 @@ +/** +* \file fpga9010_tdd.h +* \brief Contains private tdd related function prototypes for fpga9010_tdd.h +* +* FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ +*/ +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _FPGA9010_TDD_H_ +#define _FPGA9010_TDD_H_ + +#include "adi_fpga9010_user.h" +#include "adi_fpga9010_tdd_types.h" +#include "adi_fpga9010_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Initializes the FPGA TDD Enable Control module with the values passed in from the structure +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param module is a pointer to structure type adi_fpga9010_TddTiming_t which contains all +* TDD Enable Control module parameters. This structure must be pre-loaded before use and is checked for a +* null pointer if not initialized and an error will be thrown. +* \param baseAddress The base address of the module to be loaded in FPGA memory. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_TddEnableControlModuleSet(adi_fpga9010_Device_t *device, adi_fpga9010_TddTiming_t *module, uint32_t baseAddress); + +/** +* \brief Reads the FPGA TDD Enable Control module into the structure passed into the function +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param module is a pointer to an empty structure type adi_fpga9010_TddTiming_t. +* \param baseAddress The base address of the module to be loaded in FPGA memory. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_TddEnableControlModuleGet(adi_fpga9010_Device_t *device, adi_fpga9010_TddTiming_t *module, uint32_t baseAddress); + +#ifdef __cplusplus +} +#endif + +#endif /* _FPGA9010_TDD_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_ads8v2.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_ads8v2.c new file mode 100644 index 0000000..6cf5eca --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_ads8v2.c @@ -0,0 +1,3161 @@ +/** + * \file fpga9010_bf_ads8v2.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_ads8v2.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief AD9528 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2Ad9528ResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2Ad9528ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2Ad9528ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief AD9528 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2Ad9528ResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2Ad9528ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Select Line for ADS8v1 Clock Switches + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2Adg918CtrlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2Adg918CtrlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2Adg918CtrlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x14), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Select Line for ADS8v1 Clock Switches + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2Adg918CtrlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2Adg918CtrlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x14), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief External Trigger 0 Direction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrig0DirBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2ExtTrig0DirBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrig0DirBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x18), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External Trigger 0 Direction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrig0DirBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrig0DirBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x18), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief External Trigger 0 Output Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrig0OutputSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2ExtTrig0OutputSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrig0OutputSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x18), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External Trigger 0 Output Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrig0OutputSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrig0OutputSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x18), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief External Trigger 1 Direction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrig1DirBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2ExtTrig1DirBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrig1DirBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x18), (uint32_t)bfValue, 0x100, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External Trigger 1 Direction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrig1DirBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrig1DirBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x18), &rxBfData[0], 0x100, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief External Trigger 1 Output Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrig1OutputSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2ExtTrig1OutputSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrig1OutputSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x18), (uint32_t)bfValue, 0x7000, 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External Trigger 1 Output Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrig1OutputSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrig1OutputSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x18), &rxBfData[0], 0x7000, 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief External Trigger 2 Direction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrig2DirBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2ExtTrig2DirBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrig2DirBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x18), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External Trigger 2 Direction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrig2DirBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrig2DirBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x18), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief External Trigger 2 Output Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrig2OutputSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2ExtTrig2OutputSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrig2OutputSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x18), (uint32_t)bfValue, 0x700000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External Trigger 2 Output Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrig2OutputSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrig2OutputSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x18), &rxBfData[0], 0x700000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief External Trigger 3 Direction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrig3DirBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2ExtTrig3DirBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrig3DirBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x18), (uint32_t)bfValue, 0x1000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External Trigger 3 Direction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrig3DirBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrig3DirBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x18), &rxBfData[0], 0x1000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief External Trigger 3 Output Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrig3OutputSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2ExtTrig3OutputSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrig3OutputSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x18), (uint32_t)bfValue, 0x70000000, 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External Trigger 3 Output Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrig3OutputSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrig3OutputSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x18), &rxBfData[0], 0x70000000, 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief External Trigger Source for Receive Data Path 00 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrigRxdp00CtrlSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2ExtTrigRxdp00CtrlSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrigRxdp00CtrlSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x1C), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External Trigger Source for Receive Data Path 00 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrigRxdp00CtrlSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrigRxdp00CtrlSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief External Trigger Source for Receive Data Path 01 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrigRxdp01CtrlSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2ExtTrigRxdp01CtrlSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrigRxdp01CtrlSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x1C), (uint32_t)bfValue, 0x300, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External Trigger Source for Receive Data Path 01 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrigRxdp01CtrlSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrigRxdp01CtrlSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x300, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief External Trigger Source for Receive Data Path 02 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrigRxdp02CtrlSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2ExtTrigRxdp02CtrlSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrigRxdp02CtrlSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x1C), (uint32_t)bfValue, 0x3000, 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External Trigger Source for Receive Data Path 02 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrigRxdp02CtrlSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrigRxdp02CtrlSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x3000, 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief External Trigger Source for TDD State Machine Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrigTddCtrlSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2ExtTrigTddCtrlSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrigTddCtrlSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x1C), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External Trigger Source for TDD State Machine Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrigTddCtrlSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrigTddCtrlSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief External Trigger Source for Transmit Data Path 00 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrigTxdp00CtrlSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2ExtTrigTxdp00CtrlSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrigTxdp00CtrlSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x1C), (uint32_t)bfValue, 0x30000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External Trigger Source for Transmit Data Path 00 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrigTxdp00CtrlSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrigTxdp00CtrlSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x30000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief External Trigger Source for Transmit Data Path 01 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrigTxdp01CtrlSrcBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2ExtTrigTxdp01CtrlSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrigTxdp01CtrlSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x1C), (uint32_t)bfValue, 0x300000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External Trigger Source for Transmit Data Path 01 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2ExtTrigTxdp01CtrlSrcBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2ExtTrigTxdp01CtrlSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x300000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief LED Blinking Mode Blink Duration + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2LedBlinkDurationBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2LedBlinkDurationBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2LedBlinkDurationBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0xC), (uint32_t)bfValue, 0xFFFF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief LED Blinking Mode Blink Duration + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2LedBlinkDurationBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2LedBlinkDurationBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xC), &rxBfData[0], 0xFFFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief LED Mode Change Delay in Milliseconds + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2LedDelayToModeChangeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2LedDelayToModeChangeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2LedDelayToModeChangeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0xFFFF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief LED Mode Change Delay in Milliseconds + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2LedDelayToModeChangeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2LedDelayToModeChangeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0xFFFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief LED Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2LedMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 63U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2LedMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2LedMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x10), (uint32_t)bfValue, 0x3F00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief LED Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2LedMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2LedMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x10), &rxBfData[0], 0x3F00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief LED Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2LedModeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2LedModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2LedModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief LED Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2LedModeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2LedModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief LED Blinking Mode Number of Blinks + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2LedNumBlinksBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2LedNumBlinksBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2LedNumBlinksBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0xC), (uint32_t)bfValue, 0xF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief LED Blinking Mode Number of Blinks + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2LedNumBlinksBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2LedNumBlinksBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xC), &rxBfData[0], 0xF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief LED Software Define Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2LedSwDefinedValueBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 63U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2LedSwDefinedValueBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2LedSwDefinedValueBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x10), (uint32_t)bfValue, 0x3F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief LED Software Define Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2LedSwDefinedValueBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2LedSwDefinedValueBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x10), &rxBfData[0], 0x3F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief PCA9545 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2Pca9545ResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Ads8v2Pca9545ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2Pca9545ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief PCA9545 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2Pca9545ResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2Pca9545ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2VersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2VersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAds8v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Ads8v2VersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAds8v2ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_ADS8V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Ads8v2VersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_ads8v2.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_axi_adv_spi.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_axi_adv_spi.c new file mode 100644 index 0000000..e56410c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_axi_adv_spi.c @@ -0,0 +1,5340 @@ +/** + * \file fpga9010_bf_axi_adv_spi.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_axi_adv_spi.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Advanced Feature Three Wire Tristate Point + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiAdvFeat3wireTriPointBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiAdvFeat3wireTriPointBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiAdvFeat3wireTriPointBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_AxiAdvSpiAdvFeat3wireTriPointBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x80 + channelId*4), (uint32_t)bfValue, 0xFF00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Advanced Feature Three Wire Tristate Point + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiAdvFeat3wireTriPointBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiAdvFeat3wireTriPointBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_AxiAdvSpiAdvFeat3wireTriPointBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80 + channelId*4), &rxBfData[0], 0xFF00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Advanced Feature Clock Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiAdvFeatClockDivBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiAdvFeatClockDivBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiAdvFeatClockDivBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_AxiAdvSpiAdvFeatClockDivBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x80 + channelId*4), (uint32_t)bfValue, 0xFFFF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Advanced Feature Clock Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiAdvFeatClockDivBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiAdvFeatClockDivBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_AxiAdvSpiAdvFeatClockDivBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80 + channelId*4), &rxBfData[0], 0xFFFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Advanced Feature Clock Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiAdvFeatCphaBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiAdvFeatCphaBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiAdvFeatCphaBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_AxiAdvSpiAdvFeatCphaBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x80 + channelId*4), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Advanced Feature Clock Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiAdvFeatCphaBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiAdvFeatCphaBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_AxiAdvSpiAdvFeatCphaBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80 + channelId*4), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Advanced Feature Clock Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiAdvFeatCpolBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiAdvFeatCpolBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiAdvFeatCpolBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_AxiAdvSpiAdvFeatCpolBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x80 + channelId*4), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Advanced Feature Clock Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiAdvFeatCpolBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiAdvFeatCpolBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_AxiAdvSpiAdvFeatCpolBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80 + channelId*4), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Advanced Feature Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiAdvFeatEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiAdvFeatEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiAdvFeatEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_AxiAdvSpiAdvFeatEnableBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x80 + channelId*4), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Advanced Feature Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiAdvFeatEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiAdvFeatEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_AxiAdvSpiAdvFeatEnableBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80 + channelId*4), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Advanced Feature Four Wire Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiAdvFeatFourWireBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiAdvFeatFourWireBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiAdvFeatFourWireBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_AxiAdvSpiAdvFeatFourWireBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x80 + channelId*4), (uint32_t)bfValue, 0x10, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Advanced Feature Four Wire Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiAdvFeatFourWireBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiAdvFeatFourWireBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_AxiAdvSpiAdvFeatFourWireBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80 + channelId*4), &rxBfData[0], 0x10, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Advanced Feature LSB First + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiAdvFeatLsbFirstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiAdvFeatLsbFirstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiAdvFeatLsbFirstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_AxiAdvSpiAdvFeatLsbFirstBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x80 + channelId*4), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Advanced Feature LSB First + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiAdvFeatLsbFirstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiAdvFeatLsbFirstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_AxiAdvSpiAdvFeatLsbFirstBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80 + channelId*4), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Advanced Feature MISO Sample Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiAdvFeatMisoSampleSlipBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiAdvFeatMisoSampleSlipBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiAdvFeatMisoSampleSlipBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_AxiAdvSpiAdvFeatMisoSampleSlipBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x80 + channelId*4), (uint32_t)bfValue, 0x20, 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Advanced Feature MISO Sample Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiAdvFeatMisoSampleSlipBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiAdvFeatMisoSampleSlipBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_AxiAdvSpiAdvFeatMisoSampleSlipBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80 + channelId*4), &rxBfData[0], 0x20, 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiCphaBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiCphaBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiCphaBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x60), (uint32_t)bfValue, 0x10, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiCphaBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiCphaBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x60), &rxBfData[0], 0x10, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiCpolBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiCpolBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiCpolBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x60), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiCpolBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiCpolBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x60), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Data Receive Register/FIFO Full + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiDrrFullBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiDrrFullBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiDrrFullBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x20), (uint32_t)bfValue, 0x10, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Data Receive Register/FIFO Full + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiDrrFullBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiDrrFullBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x20), &rxBfData[0], 0x10, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Data Receive Register/FIFO Full IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiDrrFullIenBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiDrrFullIenBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiDrrFullIenBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x28), (uint32_t)bfValue, 0x10, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Data Receive Register/FIFO Full IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiDrrFullIenBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiDrrFullIenBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x28), &rxBfData[0], 0x10, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Data Receive Register/FIFO Overrun + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiDrrOverrunBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiDrrOverrunBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiDrrOverrunBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x20), (uint32_t)bfValue, 0x20, 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Data Receive Register/FIFO Overrun + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiDrrOverrunBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiDrrOverrunBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x20), &rxBfData[0], 0x20, 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Data Receive Register/FIFO Overrun IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiDrrOverrunIenBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiDrrOverrunIenBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiDrrOverrunIenBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x28), (uint32_t)bfValue, 0x20, 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Data Receive Register/FIFO Overrun IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiDrrOverrunIenBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiDrrOverrunIenBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x28), &rxBfData[0], 0x20, 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Data Transmit Register/FIFO Empty + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiDtrEmptyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiDtrEmptyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiDtrEmptyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x20), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Data Transmit Register/FIFO Empty + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiDtrEmptyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiDtrEmptyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x20), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Data Transmit Register/FIFO Empty IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiDtrEmptyIenBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiDtrEmptyIenBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiDtrEmptyIenBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x28), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Data Transmit Register/FIFO Empty IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiDtrEmptyIenBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiDtrEmptyIenBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x28), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Global Interrupt Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiGieBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiGieBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiGieBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x1C), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Global Interrupt Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiGieBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiGieBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Loopback Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiLoopBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiLoopBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiLoopBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x60), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Loopback Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiLoopBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiLoopBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x60), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief LSB First + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiLsbFirstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiLsbFirstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiLsbFirstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x60), (uint32_t)bfValue, 0x200, 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief LSB First + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiLsbFirstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiLsbFirstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x60), &rxBfData[0], 0x200, 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Manual Slave Select Assertion Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiManSsEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiManSsEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiManSsEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x60), (uint32_t)bfValue, 0x80, 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Manual Slave Select Assertion Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiManSsEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiManSsEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x60), &rxBfData[0], 0x80, 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Master Mode Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiMasterBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiMasterBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiMasterBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x60), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Master Mode Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiMasterBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiMasterBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x60), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Mode Fault Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiModfBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiModfBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x20), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Mode Fault Error Flag + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiModfFlagBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiModfFlagBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x10, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Mode Fault Error IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiModfIenBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiModfIenBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiModfIenBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x28), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Mode Fault Error IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiModfIenBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiModfIenBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x28), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Master Transaction Inhibit + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiMstrInhibitBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiMstrInhibitBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiMstrInhibitBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x60), (uint32_t)bfValue, 0x100, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Master Transaction Inhibit + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiMstrInhibitBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiMstrInhibitBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x60), &rxBfData[0], 0x100, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x40), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Receive Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiRxDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiRxDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x6C), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Receive Empty Flag + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiRxEmptyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiRxEmptyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Receive FIFO Occupancy + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiRxFifoOccupancyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiRxFifoOccupancyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x78), &rxBfData[0], 0x1FF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief RX FIFO Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiRxFifoResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiRxFifoResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiRxFifoResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x60), (uint32_t)bfValue, 0x40, 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Receive Full Flag + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiRxFullBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiRxFullBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Slave Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiSlaveSelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiSlaveSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiSlaveSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x70), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Slave Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiSlaveSelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiSlaveSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x70), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief SPI System Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiSpeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiSpeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiSpeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x60), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief SPI System Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiSpeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiSpeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x60), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Transmit Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiTxDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiTxDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiTxDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x68), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Transmit Empty Flag + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiTxEmptyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiTxEmptyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Transmit FIFO Half Empty + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiTxFifoHalfEmptyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiTxFifoHalfEmptyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiTxFifoHalfEmptyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x20), (uint32_t)bfValue, 0x40, 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Transmit FIFO Half Empty + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiTxFifoHalfEmptyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiTxFifoHalfEmptyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x20), &rxBfData[0], 0x40, 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Transmit FIFO Half Empty IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiTxFifoHalfEmptyIenBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiTxFifoHalfEmptyIenBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiTxFifoHalfEmptyIenBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x28), (uint32_t)bfValue, 0x40, 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Transmit FIFO Half Empty IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiTxFifoHalfEmptyIenBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiTxFifoHalfEmptyIenBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x28), &rxBfData[0], 0x40, 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Transmit FIFO Occupancy + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiTxFifoOccupancyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiTxFifoOccupancyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x74), &rxBfData[0], 0x1FF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief TX FIFO Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiTxFifoResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiAdvSpiTxFifoResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiTxFifoResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x60), (uint32_t)bfValue, 0x20, 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Transmit Full Flag + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiTxFullBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiTxFullBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiAdvSpiModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiAdvSpiChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiAdvSpiModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_axi_adv_spi.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_axi_memory_pager.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_axi_memory_pager.c new file mode 100644 index 0000000..ca50a8f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_axi_memory_pager.c @@ -0,0 +1,420 @@ +/** + * \file fpga9010_bf_axi_memory_pager.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_axi_memory_pager.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiMemoryPagerChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiMemoryPagerModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiMemoryPagerChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_MEMORY_PAGE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiMemoryPagerModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiMemoryPagerChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiMemoryPagerModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiMemoryPagerChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_MEMORY_PAGE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiMemoryPagerModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Page Identification + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiMemoryPagerChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint64_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiMemoryPagerPageIdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiMemoryPagerChanAddr_e baseAddr, + uint64_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 18446744073709551615U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiMemoryPagerPageIdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_MEMORY_PAGE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiMemoryPagerPageIdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field 8 bits */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0xC), (uint32_t)bfValue); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field 8 bits */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x8), (uint32_t)(bfValue >> 0)); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Page Identification + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiMemoryPagerChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint64_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiMemoryPagerPageIdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiMemoryPagerChanAddr_e baseAddr, + uint64_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_MEMORY_PAGE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiMemoryPagerPageIdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field 8 bits */ + fpga9010_BfRegisterRead(device, (baseAddr + 0xC), &rxBfData[0x0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field 8 bits */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x8), &rxBfData[0x1]); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x2, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint64_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Size of the Page + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiMemoryPagerChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiMemoryPagerPageSizeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiMemoryPagerChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiMemoryPagerPageSizeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_MEMORY_PAGE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiMemoryPagerPageSizeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x4), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Size of the Page + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiMemoryPagerChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiMemoryPagerPageSizeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiMemoryPagerChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_MEMORY_PAGE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiMemoryPagerPageSizeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x4), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_axi_memory_pager.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_axi_tokelau.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_axi_tokelau.c new file mode 100644 index 0000000..9639e0c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_axi_tokelau.c @@ -0,0 +1,4325 @@ +/** + * \file fpga9010_bf_axi_tokelau.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_axi_tokelau.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief AD9528 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauAd9528ResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauAd9528ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauAd9528ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief AD9528 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauAd9528ResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauAd9528ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief ADRV9010 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauAdrv9010ResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauAdrv9010ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauAdrv9010ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief ADRV9010 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauAdrv9010ResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauAdrv9010ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Identifies as Tokelau on ADS8v2 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauDesignIdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauDesignIdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief GP Interrupt 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpInterrupt0BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpInterrupt0BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x34), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief GP Interrupt 0 Detection Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpInterrupt0DetCounterBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpInterrupt0DetCounterBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x38), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GP Interrupt 0 Detection Edge or Level + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpInterrupt0DetEdgeLevelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpInterrupt0DetEdgeLevelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpInterrupt0DetEdgeLevelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x30), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GP Interrupt 0 Detection Edge or Level + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpInterrupt0DetEdgeLevelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpInterrupt0DetEdgeLevelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x30), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GP Interrupt 0 Detection Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpInterrupt0DetPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpInterrupt0DetPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpInterrupt0DetPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x30), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GP Interrupt 0 Detection Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpInterrupt0DetPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpInterrupt0DetPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x30), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief GP Interrupt 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpInterrupt1BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpInterrupt1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x44), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief GP Interrupt 1 Detection Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpInterrupt1DetCounterBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpInterrupt1DetCounterBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x48), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GP Interrupt 1 Detection Edge or Level + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpInterrupt1DetEdgeLevelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpInterrupt1DetEdgeLevelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpInterrupt1DetEdgeLevelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x40), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GP Interrupt 1 Detection Edge or Level + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpInterrupt1DetEdgeLevelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpInterrupt1DetEdgeLevelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x40), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GP Interrupt 1 Detection Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpInterrupt1DetPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpInterrupt1DetPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpInterrupt1DetPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x40), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GP Interrupt 1 Detection Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpInterrupt1DetPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpInterrupt1DetPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x40), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Control Enable SPI2 Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioEnSpi2BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioEnSpi2BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioEnSpi2BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x100), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Control Enable SPI2 Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioEnSpi2BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioEnSpi2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x100), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Control Enable Tokelau JTAG + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioEnTokJtagBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioEnTokJtagBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioEnTokJtagBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x100), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Control Enable Tokelau JTAG + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioEnTokJtagBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioEnTokJtagBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x100), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Control Enable TX to ORX Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioEnTxToOrxBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 524287U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioEnTxToOrxBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioEnTxToOrxBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x100), (uint32_t)bfValue, 0x7FFFF000, 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Control Enable TX to ORX Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioEnTxToOrxBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioEnTxToOrxBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x100), &rxBfData[0], 0x7FFFF000, 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Input + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioInputBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioInputBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x104), &rxBfData[0], 0x7FFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Output + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioOutputBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 524287U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioOutputBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioOutputBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x108), (uint32_t)bfValue, 0x7FFFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Output + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioOutputBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioOutputBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x108), &rxBfData[0], 0x7FFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Selection for TX1 to ORX1 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioSelTx1ToOrx1BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioSelTx1ToOrx1BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioSelTx1ToOrx1BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x80), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Selection for TX1 to ORX1 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioSelTx1ToOrx1BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioSelTx1ToOrx1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Selection for TX1 to ORX2 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioSelTx1ToOrx2BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioSelTx1ToOrx2BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioSelTx1ToOrx2BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x80), (uint32_t)bfValue, 0x1F00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Selection for TX1 to ORX2 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioSelTx1ToOrx2BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioSelTx1ToOrx2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80), &rxBfData[0], 0x1F00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Selection for TX2 to ORX1 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioSelTx2ToOrx1BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioSelTx2ToOrx1BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioSelTx2ToOrx1BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x80), (uint32_t)bfValue, 0x1F0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Selection for TX2 to ORX1 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioSelTx2ToOrx1BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioSelTx2ToOrx1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80), &rxBfData[0], 0x1F0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Selection for TX2 to ORX2 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioSelTx2ToOrx2BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioSelTx2ToOrx2BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioSelTx2ToOrx2BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x80), (uint32_t)bfValue, 0x1F000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Selection for TX2 to ORX2 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioSelTx2ToOrx2BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioSelTx2ToOrx2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80), &rxBfData[0], 0x1F000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Selection for TX3 to ORX3 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioSelTx3ToOrx3BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioSelTx3ToOrx3BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioSelTx3ToOrx3BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x84), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Selection for TX3 to ORX3 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioSelTx3ToOrx3BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioSelTx3ToOrx3BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x84), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Selection for TX3 to ORX4 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioSelTx3ToOrx4BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioSelTx3ToOrx4BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioSelTx3ToOrx4BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x84), (uint32_t)bfValue, 0x1F00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Selection for TX3 to ORX4 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioSelTx3ToOrx4BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioSelTx3ToOrx4BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x84), &rxBfData[0], 0x1F00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Selection for TX4 to ORX3 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioSelTx4ToOrx3BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioSelTx4ToOrx3BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioSelTx4ToOrx3BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x84), (uint32_t)bfValue, 0x1F0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Selection for TX4 to ORX3 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioSelTx4ToOrx3BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioSelTx4ToOrx3BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x84), &rxBfData[0], 0x1F0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Selection for TX4 to ORX4 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioSelTx4ToOrx4BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioSelTx4ToOrx4BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioSelTx4ToOrx4BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x84), (uint32_t)bfValue, 0x1F000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Selection for TX4 to ORX4 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioSelTx4ToOrx4BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioSelTx4ToOrx4BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x84), &rxBfData[0], 0x1F000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Trigger Source for RXDP 00 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioTriggerSrcRxdp00BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioTriggerSrcRxdp00BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioTriggerSrcRxdp00BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x20), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Trigger Source for RXDP 00 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioTriggerSrcRxdp00BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioTriggerSrcRxdp00BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x20), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Trigger Source for RXDP 01 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioTriggerSrcRxdp01BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioTriggerSrcRxdp01BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioTriggerSrcRxdp01BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x20), (uint32_t)bfValue, 0x1F00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Trigger Source for RXDP 01 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioTriggerSrcRxdp01BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioTriggerSrcRxdp01BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x20), &rxBfData[0], 0x1F00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Trigger Source for RXDP 02 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioTriggerSrcRxdp02BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioTriggerSrcRxdp02BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioTriggerSrcRxdp02BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x20), (uint32_t)bfValue, 0x1F0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Trigger Source for RXDP 02 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioTriggerSrcRxdp02BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioTriggerSrcRxdp02BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x20), &rxBfData[0], 0x1F0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Trigger Source for TXDP 00 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioTriggerSrcTxdp00BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioTriggerSrcTxdp00BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioTriggerSrcTxdp00BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x24), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Trigger Source for TXDP 00 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioTriggerSrcTxdp00BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioTriggerSrcTxdp00BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x24), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Trigger Source for TXDP 01 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioTriggerSrcTxdp01BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioTriggerSrcTxdp01BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioTriggerSrcTxdp01BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x24), (uint32_t)bfValue, 0x1F00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Trigger Source for TXDP 01 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioTriggerSrcTxdp01BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioTriggerSrcTxdp01BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x24), &rxBfData[0], 0x1F00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief GPIO Tristate + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioTristateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 524287U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauGpioTristateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioTristateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x10C), (uint32_t)bfValue, 0x7FFFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief GPIO Tristate + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauGpioTristateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauGpioTristateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x10C), &rxBfData[0], 0x7FFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Scratch Pad + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauScratchPadBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauScratchPadBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauScratchPadBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x8), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Scratch Pad + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauScratchPadBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauScratchPadBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x8), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Test Pin Input + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauTestInputBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauTestInputBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauTestInputBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x10), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Test Pin Input + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauTestInputBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauTestInputBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x10), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Test Pin Output + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauTestOutputBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauTestOutputBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauTestOutputBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x10), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Test Pin Output + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauTestOutputBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauTestOutputBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x10), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Test Pin Tristate + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauTestTristateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_AxiTokelauTestTristateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauTestTristateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x10), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Test Pin Tristate + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauTestTristateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauTestTristateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x10), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfAxiTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_AxiTokelauVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfAxiTokelauChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_AXI_TOKELAU)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_AxiTokelauVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_axi_tokelau.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_dp_capture_control.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_dp_capture_control.c new file mode 100644 index 0000000..8f67ee3 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_dp_capture_control.c @@ -0,0 +1,549 @@ +/** + * \file fpga9010_bf_dp_capture_control.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_dp_capture_control.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Data Path Active + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpCaptureControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpCaptureControlDatapathActiveBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpCaptureControlDatapathActiveBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_CAPTURE_CONTROL_RX) && + (baseAddr != FPGA9010_BF_DP_CAPTURE_CONTROL_TX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpCaptureControlDatapathActiveBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Data Path Active + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpCaptureControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpCaptureControlDatapathActiveBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_CAPTURE_CONTROL_RX) && + (baseAddr != FPGA9010_BF_DP_CAPTURE_CONTROL_TX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpCaptureControlDatapathActiveBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpCaptureControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpCaptureControlModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_CAPTURE_CONTROL_RX) && + (baseAddr != FPGA9010_BF_DP_CAPTURE_CONTROL_TX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpCaptureControlModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpCaptureControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpCaptureControlModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpCaptureControlChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_CAPTURE_CONTROL_RX) && + (baseAddr != FPGA9010_BF_DP_CAPTURE_CONTROL_TX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpCaptureControlModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Pass Token + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpCaptureControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpCaptureControlPassTokenBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpCaptureControlPassTokenBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_CAPTURE_CONTROL_RX) && + (baseAddr != FPGA9010_BF_DP_CAPTURE_CONTROL_TX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpCaptureControlPassTokenBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Pass Token + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpCaptureControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpCaptureControlPassTokenBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_CAPTURE_CONTROL_RX) && + (baseAddr != FPGA9010_BF_DP_CAPTURE_CONTROL_TX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpCaptureControlPassTokenBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpCaptureControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpCaptureControlResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpCaptureControlResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_CAPTURE_CONTROL_RX) && + (baseAddr != FPGA9010_BF_DP_CAPTURE_CONTROL_TX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpCaptureControlResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpCaptureControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpCaptureControlResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_CAPTURE_CONTROL_RX) && + (baseAddr != FPGA9010_BF_DP_CAPTURE_CONTROL_TX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpCaptureControlResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_dp_capture_control.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_dp_rx_dma.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_dp_rx_dma.c new file mode 100644 index 0000000..b497c0e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_dp_rx_dma.c @@ -0,0 +1,1627 @@ +/** + * \file fpga9010_bf_dp_rx_dma.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_dp_rx_dma.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + + +/** + * \brief Transfer Active + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaActiveBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaActiveBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xC), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Transfer Complete + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaCompleteBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaCompleteBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xC), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Enable Enhanced Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaEnableEnhancedModeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpRxDmaEnableEnhancedModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaEnableEnhancedModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Enable Enhanced Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaEnableEnhancedModeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaEnableEnhancedModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Enable Scatter Gather Transfer + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaEnableSgBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpRxDmaEnableSgBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaEnableSgBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Enable Scatter Gather Transfer + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaEnableSgBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaEnableSgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Halt Complete + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaHaltCompleteBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaHaltCompleteBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xC), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Transfer Length + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaLengthBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpRxDmaLengthBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaLengthBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x18), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Transfer Length + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaLengthBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaLengthBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x18), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Overflow + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaOverflowBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaOverflowBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xC), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpRxDmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Run Stop + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaRunStopBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpRxDmaRunStopBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaRunStopBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Run Stop + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaRunStopBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaRunStopBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Scatter-Gather First Descriptor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaSgFirstDescriptorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpRxDmaSgFirstDescriptorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaSgFirstDescriptorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x20), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Scatter-Gather First Descriptor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaSgFirstDescriptorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaSgFirstDescriptorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x20), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Scatter-Gather Last Descriptor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaSgLastDescriptorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpRxDmaSgLastDescriptorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaSgLastDescriptorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x28), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Scatter-Gather Last Descriptor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaSgLastDescriptorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaSgLastDescriptorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x28), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Simple Transfer Start Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaSimpleStartAddrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpRxDmaSimpleStartAddrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaSimpleStartAddrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x10), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Simple Transfer Start Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaSimpleStartAddrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaSimpleStartAddrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x10), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Valid Data Width of Stream Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaValidDataWidthStreamBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpRxDmaValidDataWidthStreamBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaValidDataWidthStreamBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0xF00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Valid Data Width of Stream Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaValidDataWidthStreamBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaValidDataWidthStreamBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0xF00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpRxDmaVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpRxDmaChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9010_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpRxDmaVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_dp_rx_dma.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_dp_tollgate.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_dp_tollgate.c new file mode 100644 index 0000000..1df54c9 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_dp_tollgate.c @@ -0,0 +1,712 @@ +/** + * \file fpga9010_bf_dp_tollgate.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_dp_tollgate.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Edge or Level Trigger + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTollgateEdgeLevelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTollgateEdgeLevelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTollgateEdgeLevelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0xC), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Edge or Level Trigger + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTollgateEdgeLevelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTollgateEdgeLevelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0xC), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief High Rising or Low Falling + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTollgateHighRisingLowFallingBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTollgateHighRisingLowFallingBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTollgateHighRisingLowFallingBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x10), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief High Rising or Low Falling + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTollgateHighRisingLowFallingBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTollgateHighRisingLowFallingBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x10), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTollgateModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTollgateModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTollgateModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTollgateModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Reset Tollgate + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTollgateResetTollgateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTollgateResetTollgateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTollgateResetTollgateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Reset Tollgate + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTollgateResetTollgateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTollgateResetTollgateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Trigger Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTollgateTriggerSelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTollgateTriggerSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTollgateTriggerSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x8), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Trigger Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTollgateTriggerSelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTollgateChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9010_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTollgateTriggerSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x8), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_dp_tollgate.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_dp_tx_dma.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_dp_tx_dma.c new file mode 100644 index 0000000..2bf67f7 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_dp_tx_dma.c @@ -0,0 +1,1736 @@ +/** + * \file fpga9010_bf_dp_tx_dma.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_dp_tx_dma.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + + +/** + * \brief Transfer Active + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaActiveBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaActiveBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xC), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Transfer Complete + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaCompleteBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaCompleteBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xC), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Continuous Operation + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaContinuousBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTxDmaContinuousBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaContinuousBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Continuous Operation + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaContinuousBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaContinuousBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Enable Enhanced Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaEnableEnhancedModeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTxDmaEnableEnhancedModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaEnableEnhancedModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Enable Enhanced Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaEnableEnhancedModeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaEnableEnhancedModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Enable Scatter Gather Transfer + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaEnableSgBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTxDmaEnableSgBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaEnableSgBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Enable Scatter Gather Transfer + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaEnableSgBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaEnableSgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Halt Complete + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaHaltCompleteBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaHaltCompleteBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xC), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Transfer Length + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaLengthBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTxDmaLengthBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaLengthBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x18), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Transfer Length + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaLengthBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaLengthBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x18), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTxDmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Run Stop + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaRunStopBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTxDmaRunStopBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaRunStopBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Run Stop + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaRunStopBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaRunStopBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Scatter-Gather Last Descriptor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaSgLastDescriptorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTxDmaSgLastDescriptorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaSgLastDescriptorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x28), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Scatter-Gather Last Descriptor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaSgLastDescriptorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaSgLastDescriptorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x28), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Simple Transfer Start Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaSimpleStartAddrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTxDmaSimpleStartAddrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaSimpleStartAddrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x10), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Simple Transfer Start Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaSimpleStartAddrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaSimpleStartAddrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x10), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Scatter-Gather First Descriptor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaSqFirstDescriptorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTxDmaSqFirstDescriptorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaSqFirstDescriptorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x20), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Scatter-Gather First Descriptor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaSqFirstDescriptorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaSqFirstDescriptorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x20), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Underflow + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaUnderflowBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaUnderflowBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xC), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Valid Data Width of Stream Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaValidDataWidthStreamBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTxDmaValidDataWidthStreamBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaValidDataWidthStreamBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0xF00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Valid Data Width of Stream Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaValidDataWidthStreamBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaValidDataWidthStreamBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0xF00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxDmaVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxDmaChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9010_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxDmaVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_dp_tx_dma.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_dp_tx_sof_select.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_dp_tx_sof_select.c new file mode 100644 index 0000000..3f8f6ac --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_dp_tx_sof_select.c @@ -0,0 +1,541 @@ +/** + * \file fpga9010_bf_dp_tx_sof_select.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_dp_tx_sof_select.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxSofSelectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxSofSelectDelayBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 63U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTxSofSelectDelayBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TX_SOF_SELECT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxSofSelectDelayBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x3F00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxSofSelectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxSofSelectDelayBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TX_SOF_SELECT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxSofSelectDelayBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x3F00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxSofSelectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxSofSelectModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TX_SOF_SELECT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxSofSelectModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxSofSelectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxSofSelectModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxSofSelectChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TX_SOF_SELECT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxSofSelectModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxSofSelectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxSofSelectResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTxSofSelectResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TX_SOF_SELECT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxSofSelectResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxSofSelectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxSofSelectResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TX_SOF_SELECT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxSofSelectResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxSofSelectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxSofSelectSelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_DpTxSofSelectSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TX_SOF_SELECT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxSofSelectSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfDpTxSofSelectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_DpTxSofSelectSelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_DP_TX_SOF_SELECT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_DpTxSofSelectSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_dp_tx_sof_select.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_hal.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_hal.c new file mode 100644 index 0000000..e06bce8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_hal.c @@ -0,0 +1,763 @@ +/** +* \file fpga9010_bf_hal.c +* \brief Contains ADI Transceiver Hardware Abstraction functions +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +*/ + +/** +* Disclaimer Legal Disclaimer +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9010 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_common_hal.h" +#include "adi_fpga9010.h" +#include "adi_fpga9010_hal.h" +#include "adi_common_error.h" +#include "./../../private/include/fpga9010_bf_hal.h" + + + +/** +* \brief ensures the cache is empty. if not it writes the cache to the part. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep_end +* +* \param device Pointer to the ADRV9010 device data structure. +* +* \retval ADRV9010_ Recovery action for log reset +* \retval ADRV9010_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9010_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_BfReadCacheInit(adi_fpga9010_Device_t *device) +{ + UNUSED_PARA(device); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; +// uint16_t numRdBytes = 0; +// uint64_t rdData = 0; +// int32_t halError = ADI_COMMON_HAL_OK; + +// ADI_NULL_DEVICE_PTR_RETURN(device); +// +// ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); +// +// if (device->common.cacheInfo.rdCacheState == ADRV9010_RD_BF_CACHE_ON) +// { +// recoveryAction = fpga9010_BfReadCacheFlush(device, &rdData, &numRdBytes); +// ADI_ERROR_RETURN(device->common.error.newAction); +// /* if Global Caching is being used, no further flushing should be performed +// * utill the user calls bf flush*/ +// } + return recoveryAction; +} + +/** +* \brief ensures the cache is empty. if not it writes the cache to the part. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep_end +* +* \param device Pointer to the ADRV9010 device data structure. +* +* \retval ADRV9010_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9010_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9010_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_BfWriteCacheInit(adi_fpga9010_Device_t *device) +{ + UNUSED_PARA(device); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; +// int32_t halError = ADI_COMMON_HAL_OK; + +// ADI_NULL_DEVICE_PTR_RETURN(device); +// +// ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); +// +// /* skip cacheInit if Global level Cache is on.*/ +// if (device->common.cacheInfo.wrCacheState == ADRV9010_WR_BF_CACHE_ON) +// { +// /*Ensures the cache is empty if bitField Level Caching is on*/ +// +// recoveryAction = fpga9010_BfWriteCacheFlush(device); +// ADI_ERROR_RETURN(device->common.error.newAction); +// /* if using bitField level caching re-enable caching after each flush*/ +// device->common.cacheInfo.wrFlushEn = ADI_ENABLE; +// } +// else +// { +// /* disable flushing within the bitfield function when global +// caching is being used*/ +// device->common.cacheInfo.wrFlushEn = ADI_DISABLE; +// } + + return recoveryAction; +} + + + +/** +* \brief Used to read a register. +* Merges the write if merging is on +* Caches the write if caching is on, +* Immediately writes the value if caching is off. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep{ADRV9010_BF_WRCACHE_ARRAY_TRIP_SIZE} +* \dep{SPIARRAYSIZE} +* \dep_end +* +* \param device Pointer to the ADRV9010 device data structure +* \param addr The address of the Register to read. +* \param regVal The value to be written to the register. +* +* \retval ADRV9010_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9010_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9010_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_BfRegisterWrite(adi_fpga9010_Device_t *device, + uint32_t addr, + uint32_t regVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); +// +// //TODO add array size check +// +// if (device->common.cacheInfo.wrCacheState == ADRV9010_WR_GBL_MERGE_ON) +// { +// /* Write merging is on, so the cache is searched to see if address is in the cache*/ +// for (i = 0; i < device->common.cacheInfo.wrCacheIdx; i++) +// { +// /* The cache is packed in the form AABBMMDD +// where AA is MSB Addr, BB is the LSB addr, +// MM is the mask and DD is the Data */ +// //TODO fix this +// //if the address part of the cache word = wanted address +// if ((uint16_t)(device->common.cacheInfo.wrCache[i] >> SPI_ADDR_SIZE) == addr) +// { +// //TODO: Warn of overwriteing data +// //TODO: add warning as error in Error Handler. +// addrFoundInCache = ADI_TRUE; +// halError = ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); +// recoveryAction = ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_ADIHAL, halError, ADI_COMMON_ACT_WARN_RESET_LOG, halError, "Log failure"); +// /* preserve the address but clear the data. */ +// +// //TODO: make a test to check this +// device->common.cacheInfo.wrCache[i] &= 0xFFFFFF00; +// device->common.cacheInfo.wrCache[i] |= (((uint32_t)0xFF << SPI_MASK_SIZE) | regVal); +// } +// } +// } +// +// if ((device->common.cacheInfo.wrCacheState != ADRV9010_WR_CACHE_OFF) && +// (addrFoundInCache == ADI_FALSE)) +// { +// /* Write caching is turned on and the bitField has not been merged*/ +// tmp_wrCacheIdx = device->common.cacheInfo.wrCacheIdx; +// if ((tmp_wrCacheIdx++) >= ADRV9010_BF_WRCACHE_ARRAY_TRIP_SIZE) +// { +// /* if cache is full then flush cache and add next instruction. +// should not be a problem flushing a write cache. +// */ +// device->common.cacheInfo.wrFlushEn = ADI_ENABLE; +// recoveryAction = fpga9010_BfWriteCacheFlush(device); +// ADI_ERROR_RETURN(device->common.error.newAction); +// device->common.cacheInfo.wrFlushEn = ADI_DISABLE; +// } +// +// device->common.cacheInfo.wrCache[device->common.cacheInfo.wrCacheIdx++] = ((uint32_t)addr << SPI_ADDR_SIZE) | (uint32_t)0xFF << SPI_MASK_SIZE | regVal; +// } +// +// if (device->common.cacheInfo.wrCacheState == ADRV9010_WR_CACHE_OFF) +// { +// /* Write caching is not being used, so do an immediate write */ +// if (device->common.devHalInfo != NULL) +// { +// recoveryAction = adi_fpga9010_hal_SpiByteWrite(device, addr, regVal); +// ADI_ERROR_RETURN(device->common.error.newAction); +// } +// } + adi_fpga9010_RegisterWrite(device, addr, regVal); + ADI_ERROR_RETURN(device->common.error.newAction); + return recoveryAction; +} + + +/** +* \brief Used to read a register. +* Caches the read if caching is on, immediately reads the value with caching off. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep{ADRV9010_BF_RDCACHE_ARRAY_TRIP_SIZE} +* \dep{SPIARRAYSIZE} +* \dep_end +* +* \param device Pointer to the ADRV9010 device data structure +* \param addr The address of the Register to read. +* \param regVal The value of the register just read. +* \param endOfBf when using read caching the upper nibble of this field indicates the end of bitfield with the Value F. +* +* \retval ADRV9010_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9010_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9010_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_BfRegisterRead(adi_fpga9010_Device_t *device, + uint32_t addr, + uint32_t *regVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + + ADI_NULL_PTR_RETURN(&device->common, regVal); +// +// +//int32_t fpga9010_BfRegisterRead(adi_fpga9010_Device_t *device, +// uint32_t addr, +// uint32_t *regVal, +// uint8_t endOfBf) +// +// if (device->common.cacheInfo.rdCacheState > ADRV9010_RD_CACHE_OFF) +// { +// /* Read Caching is turned on */ +// int tmp_rdCacheIdx = device->common.cacheInfo.rdCacheIdx; +// if ((tmp_rdCacheIdx++) >= ADRV9010_BF_RDCACHE_ARRAY_TRIP_SIZE) +// { +// /* if the cache is full then raise an error*/ +// ADI_ERROR_REPORT(&device->common.error, ADI_COMMON_ERRSRC_DEVICEBF, +// ADRV9010_BF_CACHE_OVERFLOW, +// ADI_COMMON_ACT_ERR_CHECK_PARAM, +// NULL, +// "Rx Cache size exceeded error"); +// ADI_ERROR_RETURN(device->common.error.newAction); +// } +// /* set bits [31:16] of the cache to the 16 bit address +// set bits [15:8] of cache to the 8 bit mask address +// set bits [7:0] of cache to the 8 bit endOfBf. +// endOfBf contains two 4 bit fields. +// [7:4] is 0xF or 0x0 and masks a end of bitField data value. +// [3:0] is the register startBit ie where the value resides in the register. +// */ +// device->common.cacheInfo.rdCache[device->common.cacheInfo.rdCacheIdx++] = ((uint32_t)addr << SPI_ADDR_SIZE) | +// ((uint32_t)0xFF << SPI_DATA_SIZE) | +// endOfBf; +// } +// else +// { +// // recoveryAction = adi_fpga9010_hal_SpiByteRead(device, addr, regVal); + + //int32_t adi_fpga9010_RegisterRead(adi_fpga9010_Device_t *device, uint32_t offset, uint32_t *data) + //ToDo replace theis with fieldRead. + + adi_fpga9010_RegisterRead(device, addr, regVal); + ADI_ERROR_RETURN(device->common.error.newAction); +// } + return recoveryAction; +} + +/** +* \brief Used to write to a sub part of a register. +* Caches the write if caching is on, immediately writes the value with caching off. +* Uses the HW_RMW function if the HW_RMW is enabled otherwise used a spi transaction to read the register +* and a spi write transaction to write the modified byte back to the register. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep{ADRV9010_BF_WRCACHE_ARRAY_TRIP_SIZE} +* \dep{SPIARRAYSIZE} +* \dep_end +* +* \param device Pointer to the ADRV9010 device data structure +* \param addr The Register address that contains the field. +* \param fieldVal The value of the field to be written. +* \param mask The mask to use when inserting the data into the register. +* \param startBit The location of the first bit of the field within the register. +* when using read caching the upper nibble of this field indicates the end of bitfield with the Value F. +* This value is used to shift the value so that it aligns with the location of the field within the register. +* +* \retval ADRV9010_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9010_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9010_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_BfFieldWrite(adi_fpga9010_Device_t *device, + uint32_t addr, + uint32_t fieldVal, + uint32_t mask, + uint8_t startBit) +{ + uint32_t regVal = ((fieldVal << startBit) & mask); + + uint32_t registerVal = 0; + uint32_t newRegVal = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +//TODO: remove this if not used +// if (device->common.cacheInfo.wrCacheState > ADRV9010_WR_HW_RMW_ON) +// { +// /* if caching is turned on*/ +// if (device->common.cacheInfo.wrCacheState == ADRV9010_WR_GBL_MERGE_ON) +// { +// /* if merging of multiple register writes with the same address is turned on*/ +// for (i = 0; i < device->common.cacheInfo.wrCacheIdx; i++) +// { +// /* search the cache for addr in the cache +// * if found merge field val and the mask into the original values*/ +// if ((uint16_t)(device->common.cacheInfo.wrCache[i] >> SPI_ADDR_SIZE) == addr) +// { +// addrFoundInCache = 1; +// cachemask = (uint8_t)(device->common.cacheInfo.wrCache[i] | 0xFF00); +// newMask = cachemask | mask; +// cacheVal = (uint8_t)(device->common.cacheInfo.wrCache[i]); +// newVal = cacheVal | regVal; +// /* clear org mask and data. */ +// +// device->common.cacheInfo.wrCache[i] &= 0xFFFF0000; +// device->common.cacheInfo.wrCache[i] |= ((uint32_t)newMask << 8) | newVal; +// } +// } +// } +// if ((device->common.cacheInfo.wrCacheState > ADRV9010_WR_CACHE_OFF) & !addrFoundInCache) +// { +// /* if caching is on or +// * merging is on but addr was not found in the cache +// * add the wr instruction to the cache. */ +// tmp_wrCacheIdx = device->common.cacheInfo.wrCacheIdx; +// if ((tmp_wrCacheIdx++) >= ADRV9010_BF_WRCACHE_ARRAY_TRIP_SIZE) +// { +// recoveryAction = fpga9010_BfWriteCacheFlush(device); +// ADI_ERROR_RETURN(device->common.error.newAction); +// } +// device->common.cacheInfo.wrCache[device->common.cacheInfo.wrCacheIdx++] = ((uint32_t)addr << SPI_ADDR_SIZE) | +// ((uint32_t)mask << 8) | +// regVal; +// } +// } +// else +// { +// /* Immediate Read modify write using HW_RMW function */ +// if (device->common.cacheInfo.wrCacheState == ADRV9010_WR_HW_RMW_ON && +// (device->common.cacheInfo.HW_RMW_Enabled > 0)) +// { +// if (device->common.cacheInfo.wrCacheIdx >= ADRV9010_BF_WRCACHE_ARRAY_TRIP_SIZE) +// { +// //it is possible the cache may cause the spi buffer to exceed its size +// //given this is a write operation it should be ok to flush and empty the buffrer +// recoveryAction = fpga9010_BfWriteCacheFlush(device); +// ADI_ERROR_RETURN(device->common.error.newAction); +// } +// recoveryAction = adi_fpga9010_hal_SpiByteWrite(device, addr, newRegVal); +// ADI_ERROR_RETURN(device->common.error.newAction); +// } +// else +// { + /* Immediate Standard read Modify Write using separate read + and writespi transactions. */ + adi_fpga9010_RegisterRead(device, addr, ®isterVal); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* modify the register value*/ + newRegVal = (registerVal & ~mask) | regVal; + + /* write to the register with modified value*/ + adi_fpga9010_RegisterWrite(device, addr, newRegVal); + ADI_ERROR_RETURN(device->common.error.newAction); +// } +// } + return (device->common.error.newAction); +} + +/** +* \brief Used to read a sub part of a register +* caches the read if caching is on, immediately read the value with caching off +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep{ADRV9010_BF_RDCACHE_ARRAY_TRIP_SIZE} +* \dep{SPIARRAYSIZE} +* \dep_end +* +* \param device Pointer to the ADRV9010 device data structure +* \param addr The Register address that contains the field. +* \param fieldVal The value of the field to be written. +* \param mask The mask to use when inserting the data into the register. +* \param startBit The location of the first bit of the field within the register. +* +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_BfFieldRead(adi_fpga9010_Device_t *device, + uint32_t addr, + uint32_t *fieldVal, + uint32_t mask, + uint8_t startBit) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + + ADI_NULL_PTR_RETURN(&device->common, fieldVal); + + //TODO: remove this if not used +// +// if (device->common.cacheInfo.rdCacheState > ADRV9010_RD_CACHE_OFF) +// { +// //adds spi call to cache +// int rdCacheIdx = device->common.cacheInfo.rdCacheIdx; +// if ((rdCacheIdx++) >= ADRV9010_BF_RDCACHE_ARRAY_TRIP_SIZE) +// { +// ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, +// ADI_COMMON_ERR_INV_PARAM, +// ADI_COMMON_ACT_ERR_CHECK_PARAM, +// NULL, +// "Rx Cache size exceeded error"); +// +// ADI_ERROR_RETURN(device->common.error.newAction); +// } +// device->common.cacheInfo.rdCache[device->common.cacheInfo.rdCacheIdx++] = ((uint32_t)addr << SPI_ADDR_SIZE) | +// ((uint32_t)mask << SPI_MASK_SIZE) | +// startBit; +// } +// else +// { +// /* Implements immediate spi transaction call only used when caching is turned off. */ + //recoveryAction = adi_fpga9010_hal_SpiFieldRead(device, addr, fieldVal, mask, startBit); + + startBit = startBit & 0x3F; /* remove the End Of BitField Marker */ + + recoveryAction = adi_fpga9010_RegisterFieldRead(device, addr, fieldVal, mask, startBit); + +// ADI_ERROR_RETURN(device->common.error.newAction); +// } + + return recoveryAction; +} + +/** +* \brief Used by the bitField API to ensure the cache is flushed when using BitField Caching +* and to assemble the register bytes when caching is not used. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep_end +* +* \param device Pointer to the ADRV9010 device data structure +* \param rxBfData The raw data read from the registers prior to concatenation. +* \param numRxBfData The number of elements used in the rxBfData. +* \param rxData The assembled bitfield value. +* +* \retval ADI_FPGA90109010_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_FPGA90109010_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA90109010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_FPGA90109010_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_BfReadAssembleData(adi_fpga9010_Device_t *device, + uint32_t *rxBfData, + uint8_t numRxBfData, + uint64_t *rxData) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t i = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + + ADI_NULL_PTR_RETURN(&device->common, rxBfData); + ADI_NULL_PTR_RETURN(&device->common, rxData); +//TODO: remove this if not used +// +// if (device->common.cacheInfo.rdCacheState == ADRV9010_RD_BF_CACHE_ON) +// { +// recoveryAction = fpga9010_BfReadCacheFlush(device, rxData, &numRxBitFields); +// ADI_ERROR_RETURN(device->common.error.newAction); +// } +// else if (device->common.cacheInfo.rdCacheState == ADRV9010_RD_CACHE_OFF) +// { +// /* Caching is not used so then assembly the bitFiled register values +// into a bitField Value. The max bitField Value is 64bits long. +// so rdData could be shifted 2 times to concatenate a 64 bit value.*/ + for (i = 0; i < numRxBfData; i++) + { + /* shift rxData to the left to make room for the next lower byte + in the bitField*/ + *rxData = (*rxData << 32) | (uint64_t)rxBfData[i]; + } +// } + return recoveryAction; +} + + +/** +* \brief Used to send multiple spi register reads in one spi transaction. +* multiple register data and sub register data is concatenated and shifted appropriately. +* +* \dep_begin +* \dep{ADRV9010_BF_RDCACHE_ARRAY_SIZE} +* \dep{SPIARRAYSIZE} +* \dep_end +* +* \param device Pointer to the ADRV9010 device data structure +* \param rdData The bytefield data being returned in the order it was read. +* \param numRdBitFields The number of bitfields being returned +* +* \retval ADRV9010_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9010_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9010_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_BfReadCacheFlush(adi_fpga9010_Device_t *device, + uint64_t *rdData, + uint16_t *numRdBitFields) +{ + UNUSED_PARA(device); + UNUSED_PARA(rdData); + UNUSED_PARA(numRdBitFields); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; +//TODO: remove this if not used +// uint32_t bfValue = 0; +// uint32_t i = 0; +// uint16_t addr = 0; +// uint16_t rdAddr[ADRV9010_BF_RDCACHE_ARRAY_SIZE] = { 0 }; +// +// uint8_t regVal = 0; +// uint8_t mask = 0; +// uint8_t startBit = 0; +// uint8_t endOfBitfield = 0; +// +// uint8_t regData[ADRV9010_BF_RDCACHE_ARRAY_SIZE] = { 0 }; +// int32_t halError = ADI_COMMON_HAL_OK; + +// ADI_NULL_DEVICE_PTR_RETURN(device); +// +// ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); +// +// ADI_NULL_PTR_RETURN(&device->common,(&device->common.error, rdData); +// ADI_NULL_PTR_RETURN(&device->common,(&device->common.error, numRdBitFields); +// +// *numRdBitFields = 0; +// +// if (device->common.cacheInfo.rdCacheIdx > ADRV9010_BF_RDCACHE_ARRAY_SIZE) +// { +// ADI_ERROR_REPORT(&device->common, 2, ADI_COMMON_ERRSRC_DEVICEBF, +// ADI_ADRV9010_ACT_ERR_FLUSH_CACHE, +// NULL, +// "Rd Cache index exceeded the spi cache Size "); +// ADI_ERROR_RETURN(device->common.error.newAction); +// } +// /* the rdData supplied by the calling function is smaller then the rdCacheIdx*/ +// if (device->common.cacheInfo.rdCacheIdx > sizeof(rdData)) +// { +// ADI_ERROR_REPORT(&device->common, 2, ADI_COMMON_ERRSRC_DEVICEBF, +// ADI_ADRV9010_ACT_ERR_FLUSH_CACHE, +// NULL, +// "Rd Cache index exceeded the user supplied rdData "); +// ADI_ERROR_RETURN(device->common.error.newAction); +// } +// +// /* pack all the read data into one array*/ +// for (i = 0; i < device->common.cacheInfo.rdCacheIdx; i++) +// { +// /* extract the address (cache[31-16]) from each of the 32 bit words in the cache +// into a address array suitable for ADRV9010HAL_spiReadBytes*/ +// rdAddr[i] = device->common.cacheInfo.rdCache[i] >> SPI_ADDR_SIZE; +// } +// +// /* send the array and receive an array of register values */ +// adi_fpga9010_hal_SpiBytesRead(device, &rdAddr[0], ®Data[0], device->common.cacheInfo.rdCacheIdx); +// ADI_ERROR_RETURN(device->common.error.newAction); +// +// /* depack the array of register values into an array of bitField values*/ +// for (i = 0; i < device->common.cacheInfo.rdCacheIdx; i++) +// { +// /* for each of the register values in the cache (if any) +// combine the data into a bitfield value*/ +// +// mask = (uint8_t)(device->common.cacheInfo.rdCache[i] >> 8); +// startBit = (uint8_t)(device->common.cacheInfo.rdCache[i]); +// +// /*The last byte in the bit field is marked by setting the upper +// nible of the startBit to F, this allows the lower nible to +// handle the byte with values from 0 to 7. +// This marker is added within the get bitfield function. +// */ +// endOfBitfield = startBit > 0xF; +// +// if (endOfBitfield) +// { +// startBit = startBit & 0xF; +// } +// regVal = regData[i]; +// +// bfValue = (bfValue << 8) | ((regVal & mask) >> startBit); +// +// device->common.cacheInfo.rdCache[i] = '\0'; +// +// if (endOfBitfield) +// { +// rdData[(*numRdBitFields)++] = bfValue; +// bfValue = 0; +// } +// } +// device->common.cacheInfo.rdCacheIdx = 0; +// device->common.cacheInfo.rdCache[device->common.cacheInfo.rdCacheIdx] = '\0'; + return recoveryAction; +} + +/** +* \brief Used to send multiple spi register writes in one spi transaction. +* if the spi buffer size is exceeded the data will be sent in buffer size blocks. +* Only full bytes are written ie there are no RMW operations +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep{ADRV9010_BF_WRCACHE_ARRAY_SIZE} +* \dep_end +* +* \param device Pointer to the ADRV9010 device data structure +* +* \retval ADRV9010_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9010_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9010_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9010_BfWriteCacheFlush(adi_fpga9010_Device_t *device) +{ + UNUSED_PARA(device); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; +//TODO: remove this if not used +// uint32_t i = 0; +// uint16_t wrAddr[ADRV9010_BF_WRCACHE_ARRAY_SIZE] = { 0 }; +// uint8_t wrData[ADRV9010_BF_WRCACHE_ARRAY_SIZE] = { 0 }; +// int32_t halError = ADI_COMMON_HAL_OK; + +// ADI_NULL_DEVICE_PTR_RETURN(device); +// +// ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); +// +// if (device->common.cacheInfo.wrCacheIdx > ADRV9010_BF_WRCACHE_ARRAY_SIZE) +// { +// ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, +// ADRV9010_BF_CACHE_OVERFLOW, +// ADI_ADRV9010_ACT_ERR_FLUSH_CACHE, +// NULL, +// "Wr Cache index exceeded the spi cache Size "); +// ADI_ERROR_RETURN(device->common.error.newAction); +// } +// +// if (device->common.cacheInfo.wrFlushEn == ADI_ENABLE) +// { +// /* convert the cache into two arrays spiWriteBytes can use*/ +// for (i = 0; i < device->common.cacheInfo.wrCacheIdx; i++) +// { +// wrAddr[i] = (uint16_t)((device->common.cacheInfo.wrCache[i] >> SPI_ADDR_SIZE) & 0xFFFF); +// wrData[i] = (uint8_t)(device->common.cacheInfo.wrCache[i] & 0xFF); +// device->common.cacheInfo.wrCache[i] = '\0'; +// } +// /* write the cache to the part */ +// recoveryAction = adi_fpga9010_hal_SpiBytesWrite(device, &wrAddr[0], +// &wrData[0], +// device->common.cacheInfo.wrCacheIdx); +// ADI_ERROR_RETURN(device->common.error.newAction); +// +// device->common.cacheInfo.wrCacheIdx = 0; +// device->common.cacheInfo.wrCache[device->common.cacheInfo.wrCacheIdx] = '\0'; +// } +// device->common.cacheInfo.wrFlushEn = ADI_ENABLE; + + return recoveryAction; +} + + +/** +* \brief allows the user to set the Write cache state. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep_end +* +* \param device Pointer to the ADRV9010 device data structure. +* \param wrCacheState the cache state to be set. +* +* \retval ADRV9010_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9010_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9010_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +//int32_t fpga9010_BfWriteCacheEn(adi_fpga9010_Device_t *device, +// fpga9010_Bf_WrCache_State_e wrCacheState) +//{ +// int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; +// int32_t halError = ADI_COMMON_HAL_OK; + +// ADI_NULL_DEVICE_PTR_RETURN(device); +// +// ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); +// +// device->common.cacheInfo.wrCacheState = wrCacheState; +// return recoveryAction; +//} + +/** +* \brief allows the user to set the read cache state. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep_end +* +* \param device Pointer to the ADRV9010 device data structure. +* \param rdCacheState the cache state to be set. +* +* \retval ADRV9010_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9010_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9010_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +//int32_t fpga9010_BfReadCacheEn(adi_fpga9010_Device_t *device, +// fpga9010_Bf_RdCache_State_e rdCacheState) +//{ +// int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; +// int32_t halError = ADI_COMMON_HAL_OK; + +// ADI_NULL_DEVICE_PTR_RETURN(device); +// +// ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); +// +// device->common.cacheInfo.rdCacheState = rdCacheState; +// return recoveryAction; +//} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_jesd204_phy_tokelau_ads8.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_jesd204_phy_tokelau_ads8.c new file mode 100644 index 0000000..e3c35c0 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_jesd204_phy_tokelau_ads8.c @@ -0,0 +1,53653 @@ +/** + * \file fpga9010_bf_jesd204_phy_tokelau_ads8.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2019 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_jesd204_phy_tokelau_ads8.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + + +/** + * \brief Channel 0 Channel PLL Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0CpllLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0CpllLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x110), &rxBfData[0], 0x4000000, 0xDA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0CpllPdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0CpllPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0CpllPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x110), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0CpllPdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0CpllPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x110), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0CpllRefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0CpllRefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0CpllRefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x110), (uint32_t)bfValue, 0x70000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0CpllRefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0CpllRefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x110), &rxBfData[0], 0x70000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 511U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x140), (uint32_t)bfValue, 0x1FF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x140), &rxBfData[0], 0x1FF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x140), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x140), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x14C), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x14C), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x14C), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x140), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x140), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x144), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x144), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x148), (uint32_t)bfValue, 0xFFFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x148), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x148), (uint32_t)bfValue, 0xFFFF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x148), &rxBfData[0], 0xFFFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x140), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x140), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0GtpowergoodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0GtpowergoodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0GtpowergoodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x104), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0GtpowergoodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0GtpowergoodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x104), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0LoopbackBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0LoopbackBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0LoopbackBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x120), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0LoopbackBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0LoopbackBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x120), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0Rx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0Rx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0Rx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x114), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0Rx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0Rx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x114), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxBufResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxBufResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxBufResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x100), (uint32_t)bfValue, 0x100000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxBufResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxBufResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x100), &rxBfData[0], 0x100000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x104), (uint32_t)bfValue, 0x700000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x104), &rxBfData[0], 0x700000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxCdrlockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxCdrlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxCdrlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x104), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxCdrlockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxCdrlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x104), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxCommaDetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxCommaDetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxCommaDetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x104), (uint32_t)bfValue, 0x1000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxCommaDetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxCommaDetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x104), &rxBfData[0], 0x1000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x114), (uint32_t)bfValue, 0x100, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x114), &rxBfData[0], 0x100, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmHoldBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x114), (uint32_t)bfValue, 0x200, 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmHoldBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x114), &rxBfData[0], 0x200, 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmOverrideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x114), (uint32_t)bfValue, 0x400, 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmOverrideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmOverrideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x114), &rxBfData[0], 0x400, 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x100), (uint32_t)bfValue, 0x40000, 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x100), &rxBfData[0], 0x40000, 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x100), (uint32_t)bfValue, 0x80000, 0x13); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x100), &rxBfData[0], 0x80000, 0xD3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x110), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x110), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x100), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x100), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 GT RX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x104), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x114), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x114), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x114), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x114), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Receiver PRBS Error Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x124), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsErrCntRstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsErrCntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsErrCntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x120), (uint32_t)bfValue, 0x100000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsErrCntRstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsErrCntRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x120), &rxBfData[0], 0x100000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x120), (uint32_t)bfValue, 0xF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x120), &rxBfData[0], 0xF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x114), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x114), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x100), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x100), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 GT RX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0RxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0RxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x104), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0Tx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0Tx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0Tx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x118), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0Tx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0Tx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x118), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x104), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x104), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxDiffControlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxDiffControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxDiffControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x118), (uint32_t)bfValue, 0xF000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxDiffControlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxDiffControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x118), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x100), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x100), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x110), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x110), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x100), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x100), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 GT TX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x104), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x118), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x118), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPostcursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPostcursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPostcursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x118), (uint32_t)bfValue, 0x1F00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPostcursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPostcursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x118), &rxBfData[0], 0x1F00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x118), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x118), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPrbsInjErrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPrbsInjErrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPrbsInjErrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x120), (uint32_t)bfValue, 0x10000000, 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPrbsInjErrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPrbsInjErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x120), &rxBfData[0], 0x10000000, 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x120), (uint32_t)bfValue, 0xF000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x120), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPrecursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPrecursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPrecursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x118), (uint32_t)bfValue, 0x1F0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxPrecursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxPrecursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x118), &rxBfData[0], 0x1F0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x118), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x118), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 0 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x100), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x100), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 0 GT TX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel0TxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel0TxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x104), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Channel PLL Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1CpllLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1CpllLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x210), &rxBfData[0], 0x4000000, 0xDA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1CpllPdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1CpllPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1CpllPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x210), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1CpllPdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1CpllPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x210), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1CpllRefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1CpllRefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1CpllRefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x210), (uint32_t)bfValue, 0x70000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1CpllRefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1CpllRefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x210), &rxBfData[0], 0x70000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 511U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x240), (uint32_t)bfValue, 0x1FF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x240), &rxBfData[0], 0x1FF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x240), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x240), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x24C), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x24C), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x24C), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x240), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x240), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x244), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x244), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x248), (uint32_t)bfValue, 0xFFFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x248), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x248), (uint32_t)bfValue, 0xFFFF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x248), &rxBfData[0], 0xFFFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x240), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x240), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1GtpowergoodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1GtpowergoodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1GtpowergoodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x204), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1GtpowergoodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1GtpowergoodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x204), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1LoopbackBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1LoopbackBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1LoopbackBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x220), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1LoopbackBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1LoopbackBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x220), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1Rx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1Rx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1Rx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x214), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1Rx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1Rx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x214), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxBufResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxBufResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxBufResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x200), (uint32_t)bfValue, 0x100000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxBufResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxBufResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x200), &rxBfData[0], 0x100000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x204), (uint32_t)bfValue, 0x700000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x204), &rxBfData[0], 0x700000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxCdrlockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxCdrlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxCdrlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x204), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxCdrlockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxCdrlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x204), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxCommaDetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxCommaDetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxCommaDetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x204), (uint32_t)bfValue, 0x1000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxCommaDetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxCommaDetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x204), &rxBfData[0], 0x1000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x214), (uint32_t)bfValue, 0x100, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x214), &rxBfData[0], 0x100, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmHoldBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x214), (uint32_t)bfValue, 0x200, 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmHoldBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x214), &rxBfData[0], 0x200, 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmOverrideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x214), (uint32_t)bfValue, 0x400, 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmOverrideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmOverrideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x214), &rxBfData[0], 0x400, 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x200), (uint32_t)bfValue, 0x40000, 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x200), &rxBfData[0], 0x40000, 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x200), (uint32_t)bfValue, 0x80000, 0x13); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x200), &rxBfData[0], 0x80000, 0xD3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x210), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x210), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x200), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x200), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 GT RX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x204), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x214), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x214), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x214), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x214), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Receiver PRBS Error Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x224), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsErrCntRstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsErrCntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsErrCntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x220), (uint32_t)bfValue, 0x100000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsErrCntRstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsErrCntRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x220), &rxBfData[0], 0x100000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x220), (uint32_t)bfValue, 0xF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x220), &rxBfData[0], 0xF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x214), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x214), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x200), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x200), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 GT RX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1RxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1RxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x204), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1Tx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1Tx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1Tx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x218), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1Tx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1Tx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x218), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x204), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x204), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxDiffControlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxDiffControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxDiffControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x218), (uint32_t)bfValue, 0xF000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxDiffControlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxDiffControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x218), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x200), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x200), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x210), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x210), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x200), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x200), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 GT TX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x204), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x218), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x218), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPostcursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPostcursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPostcursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x218), (uint32_t)bfValue, 0x1F00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPostcursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPostcursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x218), &rxBfData[0], 0x1F00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x218), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x218), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPrbsInjErrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPrbsInjErrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPrbsInjErrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x220), (uint32_t)bfValue, 0x10000000, 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPrbsInjErrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPrbsInjErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x220), &rxBfData[0], 0x10000000, 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x220), (uint32_t)bfValue, 0xF000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x220), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPrecursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPrecursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPrecursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x218), (uint32_t)bfValue, 0x1F0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxPrecursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxPrecursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x218), &rxBfData[0], 0x1F0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x218), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x218), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 1 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x200), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x200), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 1 GT TX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel1TxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel1TxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x204), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Channel PLL Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2CpllLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2CpllLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x310), &rxBfData[0], 0x4000000, 0xDA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2CpllPdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2CpllPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2CpllPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x310), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2CpllPdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2CpllPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x310), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2CpllRefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2CpllRefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2CpllRefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x310), (uint32_t)bfValue, 0x70000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2CpllRefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2CpllRefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x310), &rxBfData[0], 0x70000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 511U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x340), (uint32_t)bfValue, 0x1FF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x340), &rxBfData[0], 0x1FF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x340), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x340), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x34C), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x34C), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x34C), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x340), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x340), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x344), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x344), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x348), (uint32_t)bfValue, 0xFFFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x348), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x348), (uint32_t)bfValue, 0xFFFF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x348), &rxBfData[0], 0xFFFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x340), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x340), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2GtpowergoodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2GtpowergoodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2GtpowergoodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x304), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2GtpowergoodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2GtpowergoodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x304), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2LoopbackBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2LoopbackBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2LoopbackBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x320), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2LoopbackBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2LoopbackBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x320), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2Rx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2Rx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2Rx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x314), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2Rx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2Rx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x314), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxBufResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxBufResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxBufResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x300), (uint32_t)bfValue, 0x100000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxBufResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxBufResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x300), &rxBfData[0], 0x100000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x304), (uint32_t)bfValue, 0x700000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x304), &rxBfData[0], 0x700000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxCdrlockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxCdrlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxCdrlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x304), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxCdrlockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxCdrlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x304), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxCommaDetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxCommaDetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxCommaDetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x304), (uint32_t)bfValue, 0x1000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxCommaDetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxCommaDetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x304), &rxBfData[0], 0x1000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x314), (uint32_t)bfValue, 0x100, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x314), &rxBfData[0], 0x100, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmHoldBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x314), (uint32_t)bfValue, 0x200, 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmHoldBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x314), &rxBfData[0], 0x200, 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmOverrideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x314), (uint32_t)bfValue, 0x400, 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmOverrideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmOverrideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x314), &rxBfData[0], 0x400, 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x300), (uint32_t)bfValue, 0x40000, 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x300), &rxBfData[0], 0x40000, 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x300), (uint32_t)bfValue, 0x80000, 0x13); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x300), &rxBfData[0], 0x80000, 0xD3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x310), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x310), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x300), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x300), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 GT RX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x304), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x314), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x314), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x314), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x314), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Receiver PRBS Error Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x324), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsErrCntRstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsErrCntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsErrCntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x320), (uint32_t)bfValue, 0x100000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsErrCntRstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsErrCntRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x320), &rxBfData[0], 0x100000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x320), (uint32_t)bfValue, 0xF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x320), &rxBfData[0], 0xF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x314), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x314), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x300), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x300), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 GT RX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2RxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2RxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x304), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2Tx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2Tx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2Tx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x318), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2Tx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2Tx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x318), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x304), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x304), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxDiffControlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxDiffControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxDiffControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x318), (uint32_t)bfValue, 0xF000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxDiffControlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxDiffControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x318), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x300), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x300), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x310), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x310), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x300), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x300), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 GT TX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x304), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x318), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x318), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPostcursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPostcursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPostcursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x318), (uint32_t)bfValue, 0x1F00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPostcursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPostcursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x318), &rxBfData[0], 0x1F00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x318), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x318), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPrbsInjErrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPrbsInjErrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPrbsInjErrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x320), (uint32_t)bfValue, 0x10000000, 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPrbsInjErrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPrbsInjErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x320), &rxBfData[0], 0x10000000, 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x320), (uint32_t)bfValue, 0xF000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x320), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPrecursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPrecursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPrecursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x318), (uint32_t)bfValue, 0x1F0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxPrecursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxPrecursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x318), &rxBfData[0], 0x1F0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x318), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x318), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 2 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x300), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x300), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 2 GT TX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel2TxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel2TxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x304), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Channel PLL Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3CpllLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3CpllLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x410), &rxBfData[0], 0x4000000, 0xDA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3CpllPdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3CpllPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3CpllPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x410), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3CpllPdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3CpllPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x410), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3CpllRefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3CpllRefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3CpllRefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x410), (uint32_t)bfValue, 0x70000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3CpllRefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3CpllRefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x410), &rxBfData[0], 0x70000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 511U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x440), (uint32_t)bfValue, 0x1FF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x440), &rxBfData[0], 0x1FF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x440), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x440), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x44C), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x44C), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x44C), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x440), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x440), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x444), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x444), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x448), (uint32_t)bfValue, 0xFFFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x448), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x448), (uint32_t)bfValue, 0xFFFF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x448), &rxBfData[0], 0xFFFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x440), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x440), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3GtpowergoodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3GtpowergoodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3GtpowergoodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x404), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3GtpowergoodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3GtpowergoodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x404), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3LoopbackBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3LoopbackBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3LoopbackBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x420), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3LoopbackBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3LoopbackBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x420), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3Rx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3Rx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3Rx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x414), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3Rx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3Rx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x414), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxBufResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxBufResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxBufResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x400), (uint32_t)bfValue, 0x100000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxBufResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxBufResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x400), &rxBfData[0], 0x100000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x404), (uint32_t)bfValue, 0x700000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x404), &rxBfData[0], 0x700000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxCdrlockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxCdrlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxCdrlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x404), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxCdrlockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxCdrlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x404), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxCommaDetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxCommaDetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxCommaDetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x404), (uint32_t)bfValue, 0x1000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxCommaDetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxCommaDetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x404), &rxBfData[0], 0x1000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x414), (uint32_t)bfValue, 0x100, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x414), &rxBfData[0], 0x100, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmHoldBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x414), (uint32_t)bfValue, 0x200, 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmHoldBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x414), &rxBfData[0], 0x200, 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmOverrideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x414), (uint32_t)bfValue, 0x400, 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmOverrideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmOverrideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x414), &rxBfData[0], 0x400, 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x400), (uint32_t)bfValue, 0x40000, 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x400), &rxBfData[0], 0x40000, 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x400), (uint32_t)bfValue, 0x80000, 0x13); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x400), &rxBfData[0], 0x80000, 0xD3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x410), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x410), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x400), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x400), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 GT RX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x404), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x414), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x414), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x414), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x414), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Receiver PRBS Error Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x424), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsErrCntRstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsErrCntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsErrCntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x420), (uint32_t)bfValue, 0x100000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsErrCntRstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsErrCntRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x420), &rxBfData[0], 0x100000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x420), (uint32_t)bfValue, 0xF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x420), &rxBfData[0], 0xF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x414), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x414), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x400), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x400), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 GT RX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3RxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3RxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x404), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3Tx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3Tx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3Tx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x418), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3Tx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3Tx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x418), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x404), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x404), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxDiffControlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxDiffControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxDiffControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x418), (uint32_t)bfValue, 0xF000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxDiffControlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxDiffControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x418), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x400), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x400), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x410), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x410), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x400), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x400), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 GT TX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x404), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x418), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x418), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPostcursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPostcursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPostcursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x418), (uint32_t)bfValue, 0x1F00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPostcursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPostcursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x418), &rxBfData[0], 0x1F00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x418), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x418), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPrbsInjErrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPrbsInjErrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPrbsInjErrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x420), (uint32_t)bfValue, 0x10000000, 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPrbsInjErrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPrbsInjErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x420), &rxBfData[0], 0x10000000, 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x420), (uint32_t)bfValue, 0xF000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x420), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPrecursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPrecursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPrecursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x418), (uint32_t)bfValue, 0x1F0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxPrecursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxPrecursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x418), &rxBfData[0], 0x1F0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x418), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x418), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 3 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x400), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x400), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 3 GT TX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel3TxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel3TxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x404), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Channel PLL Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4CpllLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4CpllLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x510), &rxBfData[0], 0x4000000, 0xDA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4CpllPdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4CpllPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4CpllPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x510), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4CpllPdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4CpllPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x510), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4CpllRefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4CpllRefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4CpllRefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x510), (uint32_t)bfValue, 0x70000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4CpllRefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4CpllRefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x510), &rxBfData[0], 0x70000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 511U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x540), (uint32_t)bfValue, 0x1FF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x540), &rxBfData[0], 0x1FF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x540), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x540), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x54C), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x54C), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x54C), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x540), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x540), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x544), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x544), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x548), (uint32_t)bfValue, 0xFFFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x548), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x548), (uint32_t)bfValue, 0xFFFF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x548), &rxBfData[0], 0xFFFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x540), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x540), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4GtpowergoodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4GtpowergoodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4GtpowergoodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x504), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4GtpowergoodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4GtpowergoodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x504), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4LoopbackBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4LoopbackBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4LoopbackBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x520), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4LoopbackBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4LoopbackBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x520), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4Rx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4Rx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4Rx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x514), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4Rx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4Rx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x514), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxBufResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxBufResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxBufResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x500), (uint32_t)bfValue, 0x100000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxBufResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxBufResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x500), &rxBfData[0], 0x100000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x504), (uint32_t)bfValue, 0x700000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x504), &rxBfData[0], 0x700000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxCdrlockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxCdrlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxCdrlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x504), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxCdrlockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxCdrlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x504), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxCommaDetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxCommaDetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxCommaDetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x504), (uint32_t)bfValue, 0x1000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxCommaDetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxCommaDetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x504), &rxBfData[0], 0x1000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x514), (uint32_t)bfValue, 0x100, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x514), &rxBfData[0], 0x100, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmHoldBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x514), (uint32_t)bfValue, 0x200, 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmHoldBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x514), &rxBfData[0], 0x200, 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmOverrideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x514), (uint32_t)bfValue, 0x400, 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmOverrideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmOverrideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x514), &rxBfData[0], 0x400, 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x500), (uint32_t)bfValue, 0x40000, 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x500), &rxBfData[0], 0x40000, 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x500), (uint32_t)bfValue, 0x80000, 0x13); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x500), &rxBfData[0], 0x80000, 0xD3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x510), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x510), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x500), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x500), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 GT RX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x504), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x514), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x514), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x514), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x514), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Receiver PRBS Error Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x524), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsErrCntRstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsErrCntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsErrCntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x520), (uint32_t)bfValue, 0x100000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsErrCntRstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsErrCntRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x520), &rxBfData[0], 0x100000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x520), (uint32_t)bfValue, 0xF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x520), &rxBfData[0], 0xF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x514), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x514), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x500), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x500), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 GT RX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4RxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4RxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x504), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4Tx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4Tx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4Tx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x518), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4Tx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4Tx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x518), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x504), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x504), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxDiffControlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxDiffControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxDiffControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x518), (uint32_t)bfValue, 0xF000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxDiffControlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxDiffControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x518), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x500), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x500), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x510), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x510), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x500), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x500), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 GT TX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x504), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x518), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x518), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPostcursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPostcursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPostcursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x518), (uint32_t)bfValue, 0x1F00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPostcursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPostcursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x518), &rxBfData[0], 0x1F00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x518), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x518), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPrbsInjErrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPrbsInjErrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPrbsInjErrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x520), (uint32_t)bfValue, 0x10000000, 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPrbsInjErrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPrbsInjErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x520), &rxBfData[0], 0x10000000, 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x520), (uint32_t)bfValue, 0xF000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x520), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPrecursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPrecursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPrecursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x518), (uint32_t)bfValue, 0x1F0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxPrecursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxPrecursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x518), &rxBfData[0], 0x1F0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x518), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x518), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 4 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x500), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x500), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 4 GT TX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel4TxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel4TxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x504), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Channel PLL Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5CpllLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5CpllLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x610), &rxBfData[0], 0x4000000, 0xDA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5CpllPdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5CpllPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5CpllPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x610), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5CpllPdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5CpllPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x610), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5CpllRefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5CpllRefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5CpllRefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x610), (uint32_t)bfValue, 0x70000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5CpllRefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5CpllRefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x610), &rxBfData[0], 0x70000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 511U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x640), (uint32_t)bfValue, 0x1FF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x640), &rxBfData[0], 0x1FF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x640), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x640), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64C), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64C), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64C), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x640), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x640), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x644), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x644), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x648), (uint32_t)bfValue, 0xFFFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x648), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x648), (uint32_t)bfValue, 0xFFFF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x648), &rxBfData[0], 0xFFFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x640), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x640), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5GtpowergoodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5GtpowergoodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5GtpowergoodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x604), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5GtpowergoodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5GtpowergoodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x604), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5LoopbackBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5LoopbackBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5LoopbackBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x620), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5LoopbackBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5LoopbackBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x620), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5Rx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5Rx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5Rx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x614), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5Rx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5Rx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x614), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxBufResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxBufResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxBufResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x600), (uint32_t)bfValue, 0x100000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxBufResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxBufResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x600), &rxBfData[0], 0x100000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x604), (uint32_t)bfValue, 0x700000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x604), &rxBfData[0], 0x700000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxCdrlockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxCdrlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxCdrlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x604), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxCdrlockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxCdrlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x604), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxCommaDetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxCommaDetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxCommaDetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x604), (uint32_t)bfValue, 0x1000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxCommaDetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxCommaDetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x604), &rxBfData[0], 0x1000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x614), (uint32_t)bfValue, 0x100, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x614), &rxBfData[0], 0x100, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmHoldBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x614), (uint32_t)bfValue, 0x200, 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmHoldBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x614), &rxBfData[0], 0x200, 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmOverrideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x614), (uint32_t)bfValue, 0x400, 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmOverrideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmOverrideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x614), &rxBfData[0], 0x400, 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x600), (uint32_t)bfValue, 0x40000, 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x600), &rxBfData[0], 0x40000, 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x600), (uint32_t)bfValue, 0x80000, 0x13); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x600), &rxBfData[0], 0x80000, 0xD3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x610), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x610), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x600), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x600), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 GT RX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x604), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x614), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x614), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x614), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x614), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Receiver PRBS Error Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x624), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsErrCntRstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsErrCntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsErrCntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x620), (uint32_t)bfValue, 0x100000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsErrCntRstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsErrCntRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x620), &rxBfData[0], 0x100000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x620), (uint32_t)bfValue, 0xF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x620), &rxBfData[0], 0xF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x614), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x614), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x600), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x600), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 GT RX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5RxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5RxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x604), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5Tx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5Tx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5Tx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x618), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5Tx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5Tx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x618), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x604), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x604), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxDiffControlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxDiffControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxDiffControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x618), (uint32_t)bfValue, 0xF000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxDiffControlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxDiffControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x618), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x600), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x600), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x610), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x610), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x600), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x600), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 GT TX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x604), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x618), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x618), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPostcursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPostcursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPostcursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x618), (uint32_t)bfValue, 0x1F00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPostcursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPostcursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x618), &rxBfData[0], 0x1F00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x618), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x618), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPrbsInjErrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPrbsInjErrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPrbsInjErrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x620), (uint32_t)bfValue, 0x10000000, 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPrbsInjErrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPrbsInjErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x620), &rxBfData[0], 0x10000000, 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x620), (uint32_t)bfValue, 0xF000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x620), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPrecursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPrecursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPrecursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x618), (uint32_t)bfValue, 0x1F0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxPrecursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxPrecursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x618), &rxBfData[0], 0x1F0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x618), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x618), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 5 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x600), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x600), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 5 GT TX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel5TxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel5TxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x604), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Channel PLL Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6CpllLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6CpllLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x710), &rxBfData[0], 0x4000000, 0xDA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6CpllPdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6CpllPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6CpllPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x710), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6CpllPdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6CpllPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x710), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6CpllRefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6CpllRefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6CpllRefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x710), (uint32_t)bfValue, 0x70000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6CpllRefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6CpllRefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x710), &rxBfData[0], 0x70000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 511U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x740), (uint32_t)bfValue, 0x1FF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x740), &rxBfData[0], 0x1FF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x740), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x740), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x74C), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x74C), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x74C), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x740), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x740), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x744), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x744), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x748), (uint32_t)bfValue, 0xFFFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x748), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x748), (uint32_t)bfValue, 0xFFFF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x748), &rxBfData[0], 0xFFFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x740), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x740), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6GtpowergoodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6GtpowergoodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6GtpowergoodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x704), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6GtpowergoodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6GtpowergoodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x704), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6LoopbackBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6LoopbackBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6LoopbackBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x720), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6LoopbackBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6LoopbackBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x720), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6Rx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6Rx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6Rx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x714), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6Rx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6Rx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x714), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxBufResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxBufResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxBufResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x700), (uint32_t)bfValue, 0x100000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxBufResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxBufResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x700), &rxBfData[0], 0x100000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x704), (uint32_t)bfValue, 0x700000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x704), &rxBfData[0], 0x700000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxCdrlockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxCdrlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxCdrlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x704), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxCdrlockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxCdrlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x704), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxCommaDetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxCommaDetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxCommaDetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x704), (uint32_t)bfValue, 0x1000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxCommaDetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxCommaDetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x704), &rxBfData[0], 0x1000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x714), (uint32_t)bfValue, 0x100, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x714), &rxBfData[0], 0x100, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmHoldBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x714), (uint32_t)bfValue, 0x200, 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmHoldBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x714), &rxBfData[0], 0x200, 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmOverrideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x714), (uint32_t)bfValue, 0x400, 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmOverrideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmOverrideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x714), &rxBfData[0], 0x400, 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x700), (uint32_t)bfValue, 0x40000, 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x700), &rxBfData[0], 0x40000, 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x700), (uint32_t)bfValue, 0x80000, 0x13); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x700), &rxBfData[0], 0x80000, 0xD3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x710), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x710), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x700), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x700), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 GT RX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x704), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x714), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x714), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x714), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x714), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Receiver PRBS Error Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x724), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsErrCntRstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsErrCntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsErrCntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x720), (uint32_t)bfValue, 0x100000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsErrCntRstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsErrCntRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x720), &rxBfData[0], 0x100000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x720), (uint32_t)bfValue, 0xF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x720), &rxBfData[0], 0xF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x714), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x714), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x700), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x700), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 GT RX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6RxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6RxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x704), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6Tx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6Tx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6Tx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x718), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6Tx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6Tx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x718), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x704), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x704), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxDiffControlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxDiffControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxDiffControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x718), (uint32_t)bfValue, 0xF000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxDiffControlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxDiffControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x718), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x700), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x700), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x710), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x710), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x700), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x700), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 GT TX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x704), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x718), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x718), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPostcursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPostcursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPostcursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x718), (uint32_t)bfValue, 0x1F00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPostcursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPostcursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x718), &rxBfData[0], 0x1F00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x718), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x718), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPrbsInjErrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPrbsInjErrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPrbsInjErrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x720), (uint32_t)bfValue, 0x10000000, 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPrbsInjErrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPrbsInjErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x720), &rxBfData[0], 0x10000000, 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x720), (uint32_t)bfValue, 0xF000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x720), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPrecursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPrecursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPrecursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x718), (uint32_t)bfValue, 0x1F0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxPrecursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxPrecursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x718), &rxBfData[0], 0x1F0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x718), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x718), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 6 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x700), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x700), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 6 GT TX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel6TxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel6TxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x704), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Channel PLL Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7CpllLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7CpllLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x810), &rxBfData[0], 0x4000000, 0xDA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7CpllPdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7CpllPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7CpllPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x810), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7CpllPdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7CpllPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x810), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7CpllRefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7CpllRefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7CpllRefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x810), (uint32_t)bfValue, 0x70000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7CpllRefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7CpllRefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x810), &rxBfData[0], 0x70000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 511U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x840), (uint32_t)bfValue, 0x1FF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x840), &rxBfData[0], 0x1FF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x840), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x840), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x84C), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x84C), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x84C), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x840), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x840), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x844), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x844), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x848), (uint32_t)bfValue, 0xFFFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x848), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x848), (uint32_t)bfValue, 0xFFFF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x848), &rxBfData[0], 0xFFFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x840), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x840), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7GtpowergoodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7GtpowergoodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7GtpowergoodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x804), (uint32_t)bfValue, 0x80000000, 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7GtpowergoodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7GtpowergoodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x804), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7LoopbackBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7LoopbackBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7LoopbackBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x820), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7LoopbackBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7LoopbackBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x820), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7Rx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7Rx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7Rx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x814), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7Rx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7Rx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x814), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxBufResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxBufResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxBufResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x800), (uint32_t)bfValue, 0x100000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxBufResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxBufResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x800), &rxBfData[0], 0x100000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x804), (uint32_t)bfValue, 0x700000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x804), &rxBfData[0], 0x700000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxCdrlockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxCdrlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxCdrlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x804), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxCdrlockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxCdrlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x804), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxCommaDetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxCommaDetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxCommaDetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x804), (uint32_t)bfValue, 0x1000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxCommaDetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxCommaDetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x804), &rxBfData[0], 0x1000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x814), (uint32_t)bfValue, 0x100, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x814), &rxBfData[0], 0x100, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmHoldBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x814), (uint32_t)bfValue, 0x200, 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmHoldBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x814), &rxBfData[0], 0x200, 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmOverrideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x814), (uint32_t)bfValue, 0x400, 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmOverrideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmOverrideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x814), &rxBfData[0], 0x400, 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x800), (uint32_t)bfValue, 0x40000, 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x800), &rxBfData[0], 0x40000, 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x800), (uint32_t)bfValue, 0x80000, 0x13); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x800), &rxBfData[0], 0x80000, 0xD3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x810), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x810), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x800), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x800), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 GT RX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x804), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x814), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x814), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x814), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x814), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Receiver PRBS Error Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x824), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsErrCntRstBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsErrCntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsErrCntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x820), (uint32_t)bfValue, 0x100000, 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsErrCntRstBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsErrCntRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x820), &rxBfData[0], 0x100000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x820), (uint32_t)bfValue, 0xF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x820), &rxBfData[0], 0xF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x814), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x814), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x800), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x800), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 GT RX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7RxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7RxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x804), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7Tx8b10bEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7Tx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7Tx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x818), (uint32_t)bfValue, 0x8, 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7Tx8b10bEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7Tx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x818), &rxBfData[0], 0x8, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxBufStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x804), (uint32_t)bfValue, 0x30, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxBufStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x804), &rxBfData[0], 0x30, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxDiffControlBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxDiffControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxDiffControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x818), (uint32_t)bfValue, 0xF000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxDiffControlBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxDiffControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x818), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPcsResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x800), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPcsResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x800), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPllClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x810), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPllClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x810), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPmaResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x800), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPmaResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x800), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 GT TX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPmaResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x804), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x818), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x818), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPostcursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPostcursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPostcursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x818), (uint32_t)bfValue, 0x1F00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPostcursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPostcursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x818), &rxBfData[0], 0x1F00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPowerdownBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x818), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPowerdownBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x818), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPrbsInjErrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPrbsInjErrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPrbsInjErrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x820), (uint32_t)bfValue, 0x10000000, 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPrbsInjErrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPrbsInjErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x820), &rxBfData[0], 0x10000000, 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPrbsSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x820), (uint32_t)bfValue, 0xF000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPrbsSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x820), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPrecursorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPrecursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPrecursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x818), (uint32_t)bfValue, 0x1F0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxPrecursorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxPrecursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x818), &rxBfData[0], 0x1F0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxRateBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x818), (uint32_t)bfValue, 0x70, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxRateBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x818), &rxBfData[0], 0x70, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Channel 7 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x800), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x800), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Channel 7 GT TX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Channel7TxResetDoneBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Channel7TxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x804), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief MMCM Reference Clock Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8MmcmRefclkSelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8MmcmRefclkSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8MmcmRefclkSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief MMCM Reference Clock Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8MmcmRefclkSelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8MmcmRefclkSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8ModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8ModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8ModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8ModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad 0 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 511U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x940), (uint32_t)bfValue, 0x1FF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad 0 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x940), &rxBfData[0], 0x1FF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad 0 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x940), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad 0 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x940), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Quad 0 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x94C), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Quad 0 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x94C), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Quad 0 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x94C), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad 0 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x944), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad 0 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x944), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad 0 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x948), (uint32_t)bfValue, 0xFFFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad 0 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x948), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad 0 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x948), (uint32_t)bfValue, 0xFFFF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad 0 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x948), &rxBfData[0], 0xFFFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad 0 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x940), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad 0 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x940), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Quad PLL 0 Lock for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0LockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0LockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x910), &rxBfData[0], 0x8000, 0xCF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad PLL 0 Powerdown for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0PdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0PdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0PdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x910), (uint32_t)bfValue, 0x200, 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad PLL 0 Powerdown for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0PdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0PdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x910), &rxBfData[0], 0x200, 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad PLL 0 Reference Clock Selection for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0RefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0RefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0RefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x910), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad PLL 0 Reference Clock Selection for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0RefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0RefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x910), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad PLL 0 Reset for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0ResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x910), (uint32_t)bfValue, 0x100, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad PLL 0 Reset for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0ResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x910), &rxBfData[0], 0x100, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Quad PLL 1 Lock for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1LockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1LockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x910), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad PLL 1 Powerdown for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1PdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1PdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1PdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x910), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad PLL 1 Powerdown for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1PdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1PdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x910), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad PLL 1 Reference Clock Selection for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1RefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1RefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1RefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x910), (uint32_t)bfValue, 0x70000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad PLL 1 Reference Clock Selection for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1RefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1RefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x910), &rxBfData[0], 0x70000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad PLL 1 Reset for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1ResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x910), (uint32_t)bfValue, 0x1000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad PLL 1 Reset for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1ResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x910), &rxBfData[0], 0x1000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad 1 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpAddressBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 511U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0xA40), (uint32_t)bfValue, 0x1FF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad 1 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpAddressBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xA40), &rxBfData[0], 0x1FF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad 1 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0xA40), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad 1 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xA40), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Quad 1 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xA4C), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Quad 1 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpReadDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xA4C), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Quad 1 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpReadyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xA4C), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad 1 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpTimeoutBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0xA44), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad 1 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpTimeoutBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0xA44), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad 1 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteDataBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0xA48), (uint32_t)bfValue, 0xFFFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad 1 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteDataBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xA48), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad 1 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteDataMaskBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0xA48), (uint32_t)bfValue, 0xFFFF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad 1 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteDataMaskBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xA48), &rxBfData[0], 0xFFFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad 1 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0xA40), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad 1 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xA40), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Quad PLL 0 Lock for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0LockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0LockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xA10), &rxBfData[0], 0x8000, 0xCF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad PLL 0 Powerdown for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0PdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0PdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0PdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0xA10), (uint32_t)bfValue, 0x200, 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad PLL 0 Powerdown for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0PdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0PdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xA10), &rxBfData[0], 0x200, 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad PLL 0 Reference Clock Selection for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0RefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0RefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0RefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0xA10), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad PLL 0 Reference Clock Selection for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0RefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0RefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xA10), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad PLL 0 Reset for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0ResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0xA10), (uint32_t)bfValue, 0x100, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad PLL 0 Reset for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0ResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xA10), &rxBfData[0], 0x100, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Quad PLL 1 Lock for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1LockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1LockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xA10), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad PLL 1 Powerdown for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1PdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1PdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1PdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0xA10), (uint32_t)bfValue, 0x2000000, 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad PLL 1 Powerdown for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1PdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1PdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xA10), &rxBfData[0], 0x2000000, 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad PLL 1 Reference Clock Selection for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1RefClkSelBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1RefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1RefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0xA10), (uint32_t)bfValue, 0x70000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad PLL 1 Reference Clock Selection for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1RefClkSelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1RefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xA10), &rxBfData[0], 0x70000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Quad PLL 1 Reset for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1ResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0xA10), (uint32_t)bfValue, 0x1000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Quad PLL 1 Reset for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1ResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TOKELAU_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xA10), &rxBfData[0], 0x1000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_jesd204_phy_tokelau_ads8.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_jesd204_rx_lane_xbar.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_jesd204_rx_lane_xbar.c new file mode 100644 index 0000000..cec5f5c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_jesd204_rx_lane_xbar.c @@ -0,0 +1,4607 @@ +/** + * \file fpga9010_bf_jesd204_rx_lane_xbar.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_jesd204_rx_lane_xbar.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Lane 0 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane0SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane0SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane0SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x10), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 0 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane0SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane0SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x10), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 10 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane10SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane10SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane10SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x38), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 10 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane10SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane10SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x38), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 11 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane11SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane11SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane11SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x3C), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 11 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane11SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane11SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x3C), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 12 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane12SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane12SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane12SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x40), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 12 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane12SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane12SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x40), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 13 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane13SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane13SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane13SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x44), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 13 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane13SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane13SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x44), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 14 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane14SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane14SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane14SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x48), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 14 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane14SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane14SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x48), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 15 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane15SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane15SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane15SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4C), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 15 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane15SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane15SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4C), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 16 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane16SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane16SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane16SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x50), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 16 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane16SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane16SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x50), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 17 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane17SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane17SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane17SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x54), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 17 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane17SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane17SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x54), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 18 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane18SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane18SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane18SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x58), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 18 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane18SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane18SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x58), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 19 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane19SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane19SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane19SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x5C), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 19 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane19SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane19SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x5C), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 1 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane1SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane1SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane1SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x14), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 1 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane1SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane1SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x14), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 20 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane20SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane20SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane20SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x60), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 20 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane20SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane20SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x60), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 21 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane21SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane21SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane21SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x64), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 21 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane21SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane21SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 22 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane22SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane22SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane22SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x68), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 22 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane22SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane22SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x68), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 23 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane23SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane23SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane23SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x6C), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 23 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane23SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane23SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x6C), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 24 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane24SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane24SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane24SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x70), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 24 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane24SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane24SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x70), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 25 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane25SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane25SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane25SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x74), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 25 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane25SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane25SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x74), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 26 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane26SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane26SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane26SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x78), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 26 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane26SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane26SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x78), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 27 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane27SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane27SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane27SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x7C), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 27 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane27SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane27SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x7C), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 28 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane28SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane28SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane28SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x80), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 28 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane28SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane28SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 29 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane29SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane29SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane29SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x84), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 29 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane29SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane29SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x84), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 2 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane2SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane2SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane2SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x18), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 2 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane2SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane2SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x18), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 30 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane30SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane30SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane30SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x88), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 30 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane30SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane30SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x88), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 31 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane31SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane31SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane31SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8C), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 31 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane31SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane31SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8C), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 3 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane3SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane3SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane3SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x1C), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 3 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane3SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane3SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 4 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane4SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane4SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane4SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x20), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 4 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane4SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane4SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x20), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 5 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane5SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane5SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane5SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x24), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 5 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane5SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane5SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x24), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 6 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane6SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane6SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane6SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x28), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 6 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane6SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane6SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x28), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 7 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane7SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane7SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane7SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x2C), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 7 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane7SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane7SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x2C), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 8 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane8SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane8SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane8SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x30), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 8 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane8SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane8SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x30), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 9 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane9SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLane9SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane9SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x34), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 9 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLane9SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLane9SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x34), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLaneResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204RxLaneXbarLaneResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLaneResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x4), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarLaneResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarLaneResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x4), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204RxLaneXbarModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204RxLaneXbarModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_jesd204_rx_lane_xbar.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_jesd204_sysref_control.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_jesd204_sysref_control.c new file mode 100644 index 0000000..f2c5cbc --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_jesd204_sysref_control.c @@ -0,0 +1,1259 @@ +/** + * \file fpga9010_bf_jesd204_sysref_control.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_jesd204_sysref_control.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief External SYSREF Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlExtSysrefPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204SysrefControlExtSysrefPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlExtSysrefPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x20000, 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External SYSREF Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlExtSysrefPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlExtSysrefPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x20000, 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief External SYSREF Request + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlExtSysrefRequestBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204SysrefControlExtSysrefRequestBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlExtSysrefRequestBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x40000, 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External SYSREF Request + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlExtSysrefRequestBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlExtSysrefRequestBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x40000, 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief External SYSREF Sample Edge + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlExtSysrefSampleEdgeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204SysrefControlExtSysrefSampleEdgeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlExtSysrefSampleEdgeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief External SYSREF Sample Edge + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlExtSysrefSampleEdgeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlExtSysrefSampleEdgeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Internal SYSREF Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlIntSysrefEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204SysrefControlIntSysrefEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlIntSysrefEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Internal SYSREF Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlIntSysrefEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlIntSysrefEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Internal SYSREF Free Run + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlIntSysrefFreerunBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204SysrefControlIntSysrefFreerunBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlIntSysrefFreerunBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Internal SYSREF Free Run + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlIntSysrefFreerunBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlIntSysrefFreerunBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Internal SYSREF Generator Period + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlIntSysrefGenPeriodBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204SysrefControlIntSysrefGenPeriodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlIntSysrefGenPeriodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0xC), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Internal SYSREF Generator Period + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlIntSysrefGenPeriodBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlIntSysrefGenPeriodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0xC), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Internal SYSREF Request + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlIntSysrefRequestBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204SysrefControlIntSysrefRequestBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlIntSysrefRequestBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Internal SYSREF Request + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlIntSysrefRequestBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlIntSysrefRequestBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief SYSREF Output Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlOutputEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204SysrefControlOutputEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlOutputEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x10), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief SYSREF Output Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlOutputEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlOutputEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x10), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief SYSREF Received + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204SysrefControlSysrefReceivedBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204SysrefControlSysrefReceivedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_jesd204_sysref_control.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_jesd204_tx_lane_xbar.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_jesd204_tx_lane_xbar.c new file mode 100644 index 0000000..008cb8d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_jesd204_tx_lane_xbar.c @@ -0,0 +1,4539 @@ +/** + * \file fpga9010_bf_jesd204_tx_lane_xbar.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_jesd204_tx_lane_xbar.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Lane 0 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane0SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane0SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane0SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x10), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 0 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane0SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane0SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x10), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 10 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane10SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane10SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane10SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x38), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 10 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane10SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane10SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x38), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 11 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane11SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane11SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane11SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x3C), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 11 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane11SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane11SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x3C), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 12 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane12SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane12SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane12SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x40), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 12 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane12SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane12SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x40), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 13 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane13SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane13SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane13SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x44), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 13 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane13SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane13SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x44), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 14 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane14SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane14SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane14SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x48), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 14 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane14SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane14SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x48), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 15 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane15SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane15SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane15SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4C), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 15 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane15SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane15SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4C), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 16 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane16SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane16SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane16SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x50), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 16 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane16SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane16SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x50), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 17 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane17SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane17SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane17SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x54), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 17 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane17SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane17SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x54), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 18 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane18SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane18SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane18SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x58), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 18 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane18SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane18SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x58), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 19 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane19SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane19SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane19SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x5C), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 19 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane19SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane19SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x5C), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 1 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane1SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane1SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane1SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x14), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 1 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane1SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane1SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x14), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 20 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane20SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane20SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane20SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x60), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 20 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane20SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane20SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x60), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 21 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane21SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane21SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane21SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x64), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 21 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane21SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane21SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 22 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane22SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane22SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane22SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x68), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 22 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane22SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane22SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x68), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 23 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane23SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane23SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane23SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x6C), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 23 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane23SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane23SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x6C), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 24 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane24SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane24SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane24SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x70), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 24 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane24SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane24SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x70), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 25 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane25SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane25SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane25SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x74), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 25 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane25SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane25SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x74), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 26 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane26SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane26SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane26SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x78), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 26 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane26SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane26SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x78), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 27 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane27SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane27SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane27SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x7C), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 27 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane27SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane27SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x7C), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 28 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane28SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane28SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane28SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x80), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 28 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane28SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane28SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 29 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane29SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane29SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane29SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x84), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 29 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane29SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane29SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x84), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 2 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane2SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane2SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane2SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x18), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 2 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane2SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane2SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x18), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 30 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane30SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane30SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane30SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x88), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 30 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane30SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane30SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x88), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 31 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane31SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane31SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane31SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8C), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 31 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane31SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane31SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8C), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 3 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane3SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane3SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane3SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x1C), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 3 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane3SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane3SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 4 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane4SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane4SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane4SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x20), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 4 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane4SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane4SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x20), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 5 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane5SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane5SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane5SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x24), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 5 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane5SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane5SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x24), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 6 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane6SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane6SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane6SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x28), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 6 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane6SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane6SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x28), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 7 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane7SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane7SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane7SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x2C), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 7 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane7SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane7SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x2C), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 8 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane8SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane8SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane8SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x30), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 8 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane8SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane8SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x30), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane 9 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane9SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLane9SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane9SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x34), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane 9 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLane9SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLane9SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x34), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLaneResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204TxLaneXbarLaneResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLaneResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x4), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarLaneResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarLaneResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x4), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204TxLaneXbarModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204TxLaneXbarModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_jesd204_tx_lane_xbar.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_jesd204b_sync_xbar.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_jesd204b_sync_xbar.c new file mode 100644 index 0000000..363622f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_jesd204b_sync_xbar.c @@ -0,0 +1,1327 @@ +/** + * \file fpga9010_bf_jesd204b_sync_xbar.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_jesd204b_sync_xbar.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarModuleVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarModuleVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Sync Input Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncInPolarityBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204bSyncXbarSyncInPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncInPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Sync Input Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncInPolarityBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncInPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Sync 0 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncOut0SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut0SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut0SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x10), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Sync 0 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncOut0SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut0SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x10), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Sync 1 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncOut1SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut1SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut1SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x14), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Sync 1 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncOut1SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut1SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x14), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Sync 2 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncOut2SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut2SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut2SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x18), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Sync 2 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncOut2SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut2SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x18), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Sync 3 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncOut3SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut3SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut3SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x1C), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Sync 3 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncOut3SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut3SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Sync 4 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncOut4SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut4SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut4SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x20), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Sync 4 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncOut4SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut4SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x20), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Sync 5 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncOut5SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut5SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut5SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x24), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Sync 5 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncOut5SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut5SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x24), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Sync 6 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncOut6SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut6SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut6SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x28), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Sync 6 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncOut6SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut6SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x28), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Sync 7 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncOut7SelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut7SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut7SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x2C), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Sync 7 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_Jesd204bSyncXbarSyncOut7SelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_Jesd204bSyncXbarSyncOut7SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x2C), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_jesd204b_sync_xbar.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_orx_pin_encode_tokelau.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_orx_pin_encode_tokelau.c new file mode 100644 index 0000000..fdd950a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_orx_pin_encode_tokelau.c @@ -0,0 +1,1327 @@ +/** + * \file fpga9010_bf_orx_pin_encode_tokelau.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_orx_pin_encode_tokelau.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Enable Fast Switching Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauFastSwitchingEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_OrxPinEncodeTokelauFastSwitchingEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauFastSwitchingEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x10, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Enable Fast Switching Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauFastSwitchingEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauFastSwitchingEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x10, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Mode 1A ORX Select High + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauMode1aOrxSelectHighBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_OrxPinEncodeTokelauMode1aOrxSelectHighBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauMode1aOrxSelectHighBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0xC00, 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Mode 1A ORX Select High + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauMode1aOrxSelectHighBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauMode1aOrxSelectHighBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0xC00, 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Mode 1A ORX Select Low + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauMode1aOrxSelectLowBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_OrxPinEncodeTokelauMode1aOrxSelectLowBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauMode1aOrxSelectLowBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x300, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Mode 1A ORX Select Low + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauMode1aOrxSelectLowBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauMode1aOrxSelectLowBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x300, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Mode 3 ORX Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauMode3OrxSelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_OrxPinEncodeTokelauMode3OrxSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauMode3OrxSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x3000, 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Mode 3 ORX Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauMode3OrxSelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauMode3OrxSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x3000, 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Mode Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauModeSelectBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_OrxPinEncodeTokelauModeSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauModeSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0xF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Mode Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauModeSelectBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauModeSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0xF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Minimum ORX Enable High Time + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauOrxEnableHighTimeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_OrxPinEncodeTokelauOrxEnableHighTimeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauOrxEnableHighTimeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x14), (uint32_t)bfValue, 0xFFFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Minimum ORX Enable High Time + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauOrxEnableHighTimeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauOrxEnableHighTimeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x14), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Minimum ORX Enable Low Time + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauOrxEnableLowTimeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_OrxPinEncodeTokelauOrxEnableLowTimeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauOrxEnableLowTimeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x18), (uint32_t)bfValue, 0xFFFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Minimum ORX Enable Low Time + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauOrxEnableLowTimeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauOrxEnableLowTimeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x18), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief ORX Select Setup Time + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauOrxSelectSetupTimeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_OrxPinEncodeTokelauOrxSelectSetupTimeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauOrxSelectSetupTimeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x10), (uint32_t)bfValue, 0xFFFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief ORX Select Setup Time + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauOrxSelectSetupTimeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauOrxSelectSetupTimeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x10), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_OrxPinEncodeTokelauResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauResetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_OrxPinEncodeTokelauVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_OrxPinEncodeTokelauVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_orx_pin_encode_tokelau.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_tdd_dp_ctrl.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_tdd_dp_ctrl.c new file mode 100644 index 0000000..0af22df --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_tdd_dp_ctrl.c @@ -0,0 +1,434 @@ +/** + * \file fpga9010_bf_tdd_dp_ctrl.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_tdd_dp_ctrl.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Enable Bit for the Datapath Control Module + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddDpCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddDpCtrlEnableBitBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddDpCtrlChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddDpCtrlEnableBitBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_0) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_1) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_0) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_2) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddDpCtrlEnableBitBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Enable Bit for the Datapath Control Module + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddDpCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddDpCtrlEnableBitBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddDpCtrlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_0) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_1) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_0) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_2) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddDpCtrlEnableBitBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Start Value for Datapath Control Module + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddDpCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddDpCtrlStartValueBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddDpCtrlChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddDpCtrlStartValueBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_0) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_1) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_0) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_2) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddDpCtrlStartValueBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x4), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Start Value for Datapath Control Module + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddDpCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddDpCtrlStartValueBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddDpCtrlChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_0) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_1) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_0) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_2) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddDpCtrlStartValueBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x4), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddDpCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddDpCtrlVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddDpCtrlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_0) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_1) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_0) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_2) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddDpCtrlVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddDpCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddDpCtrlVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddDpCtrlChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_0) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_1) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_0) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_2) && + (baseAddr != FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddDpCtrlVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_tdd_dp_ctrl.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_tdd_enable_ctrl.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_tdd_enable_ctrl.c new file mode 100644 index 0000000..fb53fd9 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_tdd_enable_ctrl.c @@ -0,0 +1,1964 @@ +/** + * \file fpga9010_bf_tdd_enable_ctrl.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_tdd_enable_ctrl.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Enable Bit + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddEnableCtrlEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0xC), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Enable Bit + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xC), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief End Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlEndValueBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddEnableCtrlEndValueBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlEndValueBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x8), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief End Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlEndValueBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlEndValueBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x8), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Active Frames + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlFramesActiveBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddEnableCtrlFramesActiveBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlFramesActiveBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x20), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Active Frames + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlFramesActiveBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlFramesActiveBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x20), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Inactive Frames + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlFramesInactiveBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddEnableCtrlFramesInactiveBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlFramesInactiveBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x24), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Inactive Frames + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlFramesInactiveBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlFramesInactiveBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x24), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Frames Offset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlFramesOffsetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddEnableCtrlFramesOffsetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlFramesOffsetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x1C), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Frames Offset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlFramesOffsetBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlFramesOffsetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x1C), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Manual TDD Enable Signal + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlManualEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddEnableCtrlManualEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlManualEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x28), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Manual TDD Enable Signal + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlManualEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlManualEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x28), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Secondary Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlSecEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddEnableCtrlSecEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlSecEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x18), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Secondary Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlSecEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlSecEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x18), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Secondary End Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlSecEndValueBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddEnableCtrlSecEndValueBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlSecEndValueBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x14), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Secondary End Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlSecEndValueBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlSecEndValueBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x14), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Secondary Start Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlSecStartValueBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddEnableCtrlSecStartValueBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlSecStartValueBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x10), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Secondary Start Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlSecStartValueBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlSecStartValueBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x10), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Start Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlStartValueBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddEnableCtrlStartValueBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlStartValueBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x4), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Start Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlStartValueBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlStartValueBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x4), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddEnableCtrlVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddEnableCtrlChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddEnableCtrlVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_tdd_enable_ctrl.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_tdd_frame_cnt.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_tdd_frame_cnt.c new file mode 100644 index 0000000..a4e6a90 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_tdd_frame_cnt.c @@ -0,0 +1,803 @@ +/** + * \file fpga9010_bf_tdd_frame_cnt.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_tdd_frame_cnt.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Enable Bit + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddFrameCntEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddFrameCntEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddFrameCntEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Enable Bit + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddFrameCntEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddFrameCntEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief End Value Indicates the End of Frame Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddFrameCntEndValueBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddFrameCntEndValueBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddFrameCntEndValueBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x4), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief End Value Indicates the End of Frame Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddFrameCntEndValueBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddFrameCntEndValueBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x4), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Loop Count for the Frame Counter to Roll Over + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddFrameCntLoopCountBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddFrameCntLoopCountBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddFrameCntLoopCountBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0xC), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Loop Count for the Frame Counter to Roll Over + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddFrameCntLoopCountBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddFrameCntLoopCountBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0xC), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Loop Count Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddFrameCntLoopCountEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddFrameCntLoopCountEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddFrameCntLoopCountEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x10), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Loop Count Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddFrameCntLoopCountEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddFrameCntLoopCountEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x10), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Trigger Bit + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddFrameCntTriggerBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_TddFrameCntTriggerBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddFrameCntTriggerBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Trigger Bit + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddFrameCntTriggerBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddFrameCntTriggerBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddFrameCntVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddFrameCntVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_TddFrameCntVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfTddFrameCntChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_TddFrameCntVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFFFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_tdd_frame_cnt.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_xilinx_clock_wizard.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_xilinx_clock_wizard.c new file mode 100644 index 0000000..2c1fbd5 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_xilinx_clock_wizard.c @@ -0,0 +1,4146 @@ +/** + * \file fpga9010_bf_xilinx_clock_wizard.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_xilinx_clock_wizard.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Feedback Clock Multiplier Fractional Portion + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkfboutFracBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1023U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkfboutFracBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkfboutFracBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x200), (uint32_t)bfValue, 0x3FF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Feedback Clock Multiplier Fractional Portion + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkfboutFracBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkfboutFracBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x200), &rxBfData[0], 0x3FF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Feedback Clock Multiplier + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkfboutMultBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkfboutMultBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkfboutMultBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x200), (uint32_t)bfValue, 0xFF00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Feedback Clock Multiplier + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkfboutMultBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkfboutMultBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x200), &rxBfData[0], 0xFF00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Feedback Clock Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkfboutPhaseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkfboutPhaseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkfboutPhaseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x204), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Feedback Clock Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkfboutPhaseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkfboutPhaseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x204), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 0 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout0DivideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout0DivideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout0DivideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x208), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 0 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout0DivideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout0DivideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x208), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 0 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout0DutyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout0DutyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout0DutyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x210), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 0 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout0DutyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout0DutyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x210), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 0 Fractional Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout0FracBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1023U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout0FracBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout0FracBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x208), (uint32_t)bfValue, 0x3FF00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 0 Fractional Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout0FracBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout0FracBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x208), &rxBfData[0], 0x3FF00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 0 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout0PhaseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout0PhaseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout0PhaseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x20C), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 0 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout0PhaseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout0PhaseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x20C), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 1 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout1DivideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout1DivideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout1DivideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x214), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 1 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout1DivideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout1DivideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x214), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 1 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout1DutyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout1DutyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout1DutyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x21C), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 1 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout1DutyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout1DutyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x21C), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 1 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout1PhaseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout1PhaseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout1PhaseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x218), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 1 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout1PhaseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout1PhaseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x218), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 2 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout2DivideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout2DivideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout2DivideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x220), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 2 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout2DivideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout2DivideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x220), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 2 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout2DutyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout2DutyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout2DutyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x228), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 2 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout2DutyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout2DutyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x228), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 2 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout2PhaseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout2PhaseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout2PhaseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x224), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 2 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout2PhaseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout2PhaseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x224), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 3 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout3DivideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout3DivideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout3DivideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x22C), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 3 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout3DivideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout3DivideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x22C), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 3 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout3DutyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout3DutyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout3DutyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x234), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 3 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout3DutyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout3DutyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x234), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 3 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout3PhaseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout3PhaseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout3PhaseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x230), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 3 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout3PhaseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout3PhaseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x230), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 4 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout4DivideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout4DivideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout4DivideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x238), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 4 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout4DivideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout4DivideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x238), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 4 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout4DutyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout4DutyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout4DutyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x240), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 4 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout4DutyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout4DutyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x240), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 4 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout4PhaseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout4PhaseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout4PhaseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x23C), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 4 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout4PhaseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout4PhaseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x23C), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 5 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout5DivideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout5DivideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout5DivideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x244), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 5 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout5DivideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout5DivideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x244), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 5 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout5DutyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout5DutyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout5DutyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x24C), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 5 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout5DutyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout5DutyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x24C), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 5 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout5PhaseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout5PhaseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout5PhaseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x248), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 5 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout5PhaseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout5PhaseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x248), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 6 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout6DivideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout6DivideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout6DivideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x250), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 6 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout6DivideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout6DivideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x250), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 6 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout6DutyBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout6DutyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout6DutyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x258), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 6 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout6DutyBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout6DutyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x258), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Clock Output 6 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout6PhaseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardClkout6PhaseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout6PhaseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x254), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Clock Output 6 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardClkout6PhaseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardClkout6PhaseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x254), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief DIVCLK Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardDivclkDivideBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardDivclkDivideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardDivclkDivideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x200), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief DIVCLK Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardDivclkDivideBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardDivclkDivideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x200), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Error Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardErrorStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardErrorStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x8), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Interrupt Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardInterruptEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardInterruptEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardInterruptEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x10), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardInterruptEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardInterruptEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x10), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Interrupt Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardInterruptStatusBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardInterruptStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardInterruptStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0xC), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardInterruptStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardInterruptStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0xC), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Load Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardLoadBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardLoadBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardLoadBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x25C), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Load Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardLoadBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardLoadBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x25C), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Locked + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardLockedBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardLockedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief SADDR + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardSaddrBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardSaddrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardSaddrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x25C), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief SADDR + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardSaddrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardSaddrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x25C), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Software Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxClockWizardSoftwareResetBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxClockWizardSoftwareResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxClockWizardSoftwareResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x0), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_xilinx_clock_wizard.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_xilinx_jesd204b.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_xilinx_jesd204b.c new file mode 100644 index 0000000..9abf444 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_xilinx_jesd204b.c @@ -0,0 +1,8508 @@ +/** + * \file fpga9010_bf_xilinx_jesd204b.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_xilinx_jesd204b.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Octets per Frame (F) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bCfgFBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bCfgFBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bCfgFBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x20), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Octets per Frame (F) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bCfgFBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bCfgFBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x20), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Frames per Multiframe (K) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bCfgKBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bCfgKBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bCfgKBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x24), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Frames per Multiframe (K) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bCfgKBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bCfgKBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x24), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief ID of Lane N + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bCfgLaneIdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bCfgLaneIdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bCfgLaneIdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bCfgLaneIdBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x400 + channelId*4), (uint32_t)bfValue, 0x1F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief ID of Lane N + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bCfgLaneIdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bCfgLaneIdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bCfgLaneIdBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x400 + channelId*4), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Subclass Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bCfgSubclassvBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bCfgSubclassvBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bCfgSubclassvBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x2C), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Subclass Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bCfgSubclassvBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bCfgSubclassvBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x2C), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Disable Error Reporting Using SYNC Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bDisErrOnSyncBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bDisErrOnSyncBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bDisErrOnSyncBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x34), (uint32_t)bfValue, 0x100, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Disable Error Reporting Using SYNC Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bDisErrOnSyncBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bDisErrOnSyncBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x34), &rxBfData[0], 0x100, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief ADJCNT (Phase Adjust Request) [Subclass 2 Only] + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaAdjcntBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaAdjcntBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaAdjcntBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaAdjcntBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x81C + channelId*64), (uint32_t)bfValue, 0xF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief ADJCNT (Phase Adjust Request) [Subclass 2 Only] + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaAdjcntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaAdjcntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaAdjcntBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x81C + channelId*64), &rxBfData[0], 0xF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief ADJDIR (Adjust Direction) [Subclass 2 Only] + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaAdjdirBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaAdjdirBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaAdjdirBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaAdjdirBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x81C + channelId*64), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief ADJDIR (Adjust Direction) [Subclass 2 Only] + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaAdjdirBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaAdjdirBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaAdjdirBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x81C + channelId*64), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief BID (Bank ID) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaBidBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaBidBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaBidBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaBidBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x80C + channelId*64), (uint32_t)bfValue, 0xF00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief BID (Bank ID) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaBidBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaBidBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaBidBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80C + channelId*64), &rxBfData[0], 0xF00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief CF (Control Words per Frame) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaCfBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaCfBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaCfBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaCfBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x814 + channelId*64), (uint32_t)bfValue, 0x1F000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief CF (Control Words per Frame) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaCfBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaCfBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaCfBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x814 + channelId*64), &rxBfData[0], 0x1F000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief CS (Control Bits per Sample) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaCsBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaCsBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaCsBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaCsBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x810 + channelId*64), (uint32_t)bfValue, 0x3000000, 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief CS (Control Bits per Sample) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaCsBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaCsBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaCsBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x810 + channelId*64), &rxBfData[0], 0x3000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief DID (Device ID) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaDidBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaDidBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaDidBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaDidBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x80C + channelId*64), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief DID (Device ID) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaDidBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaDidBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaDidBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80C + channelId*64), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief F (Octets per Frame) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaFBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaFBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaFBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x804 + channelId*64), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief FCHK (Checksum) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaFchkBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaFchkBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaFchkBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaFchkBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x818 + channelId*64), (uint32_t)bfValue, 0xFF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief FCHK (Checksum) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaFchkBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaFchkBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaFchkBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x818 + channelId*64), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief HD (High Density Format) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaHdBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaHdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaHdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaHdBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x814 + channelId*64), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief HD (High Density Format) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaHdBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaHdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaHdBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x814 + channelId*64), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief JESDV (JESD204 Version) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaJesdvBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaJesdvBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaJesdvBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x800 + channelId*64), &rxBfData[0], 0x700, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief K (Frames per Multiframe) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaKBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaKBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaKBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x808 + channelId*64), &rxBfData[0], 0x1F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief L (Lanes per Link) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaLBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaLBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaLBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80C + channelId*64), &rxBfData[0], 0x1F000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief LID (Lane ID) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaLidBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaLidBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaLidBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x80C + channelId*64), &rxBfData[0], 0x1F0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief M (Converters per Device) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaMBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaMBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaMBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaMBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x810 + channelId*64), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief M (Converters per Device) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaMBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaMBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaMBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x810 + channelId*64), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Multiframes in the Transmitted ILAS + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaMultiframesBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaMultiframesBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaMultiframesBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x14), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Multiframes in the Transmitted ILAS + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaMultiframesBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaMultiframesBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x14), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief N (Converter Resolution) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaNBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaNBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaNBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaNBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x810 + channelId*64), (uint32_t)bfValue, 0x1F00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief N (Converter Resolution) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaNBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaNBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaNBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x810 + channelId*64), &rxBfData[0], 0x1F00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief N' (Totals Bits per Sample) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaNpBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaNpBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaNpBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaNpBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x810 + channelId*64), (uint32_t)bfValue, 0x1F0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief N' (Totals Bits per Sample) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaNpBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaNpBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaNpBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x810 + channelId*64), &rxBfData[0], 0x1F0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief PHADJ (Phase Adjust Request) [Subclass 2 Only] + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaPhadjBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaPhadjBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaPhadjBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaPhadjBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x81C + channelId*64), (uint32_t)bfValue, 0x100, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief PHADJ (Phase Adjust Request) [Subclass 2 Only] + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaPhadjBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaPhadjBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaPhadjBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x81C + channelId*64), &rxBfData[0], 0x100, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief RES1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaRes1BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaRes1BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaRes1BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaRes1BfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x818 + channelId*64), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief RES1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaRes1BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaRes1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaRes1BfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x818 + channelId*64), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief RES2 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaRes2BfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaRes2BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaRes2BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaRes2BfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x818 + channelId*64), (uint32_t)bfValue, 0xFF00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief RES2 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaRes2BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaRes2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaRes2BfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x818 + channelId*64), &rxBfData[0], 0xFF00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief S (Samples per Converter per Frame) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaSBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaSBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaSBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaSBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x814 + channelId*64), (uint32_t)bfValue, 0x1F00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief S (Samples per Converter per Frame) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaSBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaSBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaSBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x814 + channelId*64), &rxBfData[0], 0x1F00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief SCR (Scrambling Enable) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaScrBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaScrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaScrBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x814 + channelId*64), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief SUBCLASS + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaSubclassBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaSubclassBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bIlaSubclassBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x800 + channelId*64), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief ILA Support Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaSupportEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bIlaSupportEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaSupportEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x8), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief ILA Support Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bIlaSupportEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bIlaSupportEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x8), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Lane Alignment Error Detected Alarm + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLaneAlignAlarmBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLaneAlignAlarmBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x80000000, 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lanes in Use + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLanesInUseBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bLanesInUseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLanesInUseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x28), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lanes in Use + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLanesInUseBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLanesInUseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x28), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Link Debug Status Lane 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkDebugStatusLane0BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkDebugStatusLane0BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x3C), &rxBfData[0], 0xF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Link Debug Status Lane 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkDebugStatusLane1BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkDebugStatusLane1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x3C), &rxBfData[0], 0xF0, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Link Debug Status Lane 2 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkDebugStatusLane2BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkDebugStatusLane2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x3C), &rxBfData[0], 0xF00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Link Debug Status Lane 3 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkDebugStatusLane3BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkDebugStatusLane3BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x3C), &rxBfData[0], 0xF000, 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Link Debug Status Lane 4 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkDebugStatusLane4BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkDebugStatusLane4BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x3C), &rxBfData[0], 0xF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Link Debug Status Lane 5 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkDebugStatusLane5BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkDebugStatusLane5BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x3C), &rxBfData[0], 0xF00000, 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Link Debug Status Lane 6 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkDebugStatusLane6BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkDebugStatusLane6BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x3C), &rxBfData[0], 0xF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Link Debug Status Lane 7 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkDebugStatusLane7BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkDebugStatusLane7BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x3C), &rxBfData[0], 0xF0000000, 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Link Error Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkErrCntBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bLinkErrCntBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkErrCntBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bLinkErrCntBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x824 + channelId*64), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Link Error Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bLinkErrCntBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x824 + channelId*64), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Link Error Counters Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkErrCntrsEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bLinkErrCntrsEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkErrCntrsEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x34), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Link Error Counters Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkErrCntrsEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkErrCntrsEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x34), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Link Error Status, Lane 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkErrorStatusLane0BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkErrorStatusLane0BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Link Error Status, Lane 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkErrorStatusLane1BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkErrorStatusLane1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x38, 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Link Error Status, Lane 2 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkErrorStatusLane2BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkErrorStatusLane2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x1C0, 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Link Error Status, Lane 3 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkErrorStatusLane3BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkErrorStatusLane3BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0xE00, 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Link Error Status, Lane 4 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkErrorStatusLane4BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkErrorStatusLane4BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x7000, 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Link Error Status, Lane 5 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkErrorStatusLane5BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkErrorStatusLane5BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x38000, 0xCF); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Link Error Status, Lane 6 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkErrorStatusLane6BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkErrorStatusLane6BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x1C0000, 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Link Error Status, Lane 7 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bLinkErrorStatusLane7BfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bLinkErrorStatusLane7BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0xE00000, 0xD5); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Reset, Fixed + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bResetFixedBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bResetFixedBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bResetFixedBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Reset, Fixed + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bResetFixedBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bResetFixedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Reset, Self Clearing + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bResetSelfClearingBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bResetSelfClearingBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bResetSelfClearingBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Reset, Self Clearing + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bResetSelfClearingBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bResetSelfClearingBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief RX Buffer Adjust + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bRxBufAdjBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bRxBufAdjBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bRxBufAdjBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x830 + channelId*64), &rxBfData[0], 0x3FF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} +/** + * \brief RX Buffer Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bRxBufferDelayBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint16_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1023U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bRxBufferDelayBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bRxBufferDelayBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x30), (uint32_t)bfValue, 0x3FF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief RX Buffer Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bRxBufferDelayBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint16_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bRxBufferDelayBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x30), &rxBfData[0], 0x3FF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief RX Buffer Overflow Alarm + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bRxBufferOvrfAlarmBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bRxBufferOvrfAlarmBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x20000000, 0xDD); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Scrambling Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bScramblingEnBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bScramblingEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bScramblingEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0xC), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Scrambling Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bScramblingEnBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bScramblingEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0xC), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief SYNC Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bSyncStatusBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bSyncStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x38), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief SYSREF Always + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bSysrefAlwaysBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bSysrefAlwaysBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bSysrefAlwaysBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x10), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief SYSREF Always + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bSysrefAlwaysBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bSysrefAlwaysBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x10), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief SYSREF Captured (Subclass 1 Only) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bSysrefCapturedBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bSysrefCapturedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x38), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief SYSREF Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bSysrefDelayBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bSysrefDelayBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bSysrefDelayBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x10), (uint32_t)bfValue, 0xF00, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief SYSREF Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bSysrefDelayBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bSysrefDelayBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x10), &rxBfData[0], 0xF00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief SYSREF LMFC Alarm (Subclass 1 Only) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bSysrefLmfcAlarmBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bSysrefLmfcAlarmBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x1C), &rxBfData[0], 0x40000000, 0xDE); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief SYSREF Required on Re-Sync + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bSysrefRequiredOnResyncBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bSysrefRequiredOnResyncBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bSysrefRequiredOnResyncBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x10), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief SYSREF Required on Re-Sync + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bSysrefRequiredOnResyncBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bSysrefRequiredOnResyncBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x10), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Test Mode Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bTestModeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bTestModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bTestModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x18), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Test Mode Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bTestModeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bTestModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x18), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Test Mode Error Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bTestModeErrCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bTestModeErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bTestModeErrCntBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x820 + channelId*64), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Test Mode ILA Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bTestModeIlaCntBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bTestModeIlaCntBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bTestModeIlaCntBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bTestModeIlaCntBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x828 + channelId*64), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Test Mode ILA Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bTestModeIlaCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bTestModeIlaCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bTestModeIlaCntBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x828 + channelId*64), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Test Mode Multiframe Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bTestModeMfCntBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bTestModeMfCntBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bTestModeMfCntBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bTestModeMfCntBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Single Register */ + fpga9010_BfRegisterWrite(device, (baseAddr + 0x82C + channelId*64), ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Test Mode Multiframe Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bTestModeMfCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bTestModeMfCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204bTestModeMfCntBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x82C + channelId*64), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Version Major + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Version Minor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Revision + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bVersionRevisionBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bVersionRevisionBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Watchdog Timer Disable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bWatchdogTimerDisableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204bWatchdogTimerDisableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bWatchdogTimerDisableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4), (uint32_t)bfValue, 0x10000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Watchdog Timer Disable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204bWatchdogTimerDisableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204bWatchdogTimerDisableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_xilinx_jesd204b.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_xilinx_jesd204c.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_xilinx_jesd204c.c new file mode 100644 index 0000000..a6931d8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_bf_xilinx_jesd204c.c @@ -0,0 +1,4603 @@ +/** + * \file fpga9010_bf_xilinx_jesd204c.c Automatically generated file with generator ver 0.0.0.1. + * + * \brief Contains BitField functions to support FPGA9010 transceiver device. + * + * FPGA9010 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9010_bf_xilinx_jesd204c.h" +#include "./../../private/include/fpga9010_bf_hal.h" +#include "adi_common_error.h" + + +/** + * \brief Buffer Fill Level + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cBufferLevelBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t channelId, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cBufferLevelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204cBufferLevelBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x400 + channelId*128), &rxBfData[0], 0x3F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Buffer Overflow Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cBufferOverflowBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cBufferOverflowBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x60), &rxBfData[0], 0x400, 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Multi-blocks in Extended Multi-blocks + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cCfgMbInEmbBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cCfgMbInEmbBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cCfgMbInEmbBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x30), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Multi-blocks in Extended Multi-blocks + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cCfgMbInEmbBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cCfgMbInEmbBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x30), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Subclass Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cCfgSubclassvBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cCfgSubclassvBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cCfgSubclassvBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x34), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Subclass Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cCfgSubclassvBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cCfgSubclassvBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x34), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Core is TX + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cCoreIsTxBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cCoreIsTxBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0x10000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Enable Command Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cEnableCmdInterfaceBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cEnableCmdInterfaceBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cEnableCmdInterfaceBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x24), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Enable Command Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cEnableCmdInterfaceBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cEnableCmdInterfaceBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x24), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Enable Data Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cEnableDataInterfaceBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cEnableDataInterfaceBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cEnableDataInterfaceBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x24), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Enable Data Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cEnableDataInterfaceBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cEnableDataInterfaceBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x24), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Status Block Sync Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqBlockSyncErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqBlockSyncErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x68), &rxBfData[0], 0x40, 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Status CRC Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqCrcErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqCrcErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x68), &rxBfData[0], 0x100, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Interrupt Enable Block Sync Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnBlockSyncErrorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cIrqEnBlockSyncErrorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnBlockSyncErrorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x64), (uint32_t)bfValue, 0x40, 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Enable Block Sync Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnBlockSyncErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnBlockSyncErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x40, 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Interrupt Enable CRC Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnCrcErrorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cIrqEnCrcErrorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnCrcErrorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x64), (uint32_t)bfValue, 0x100, 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Enable CRC Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnCrcErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnCrcErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x100, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Interrupt Enable FEC Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnFecErrorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cIrqEnFecErrorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnFecErrorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x64), (uint32_t)bfValue, 0x200, 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Enable FEC Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnFecErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnFecErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x200, 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Global Interrupt Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnGlobalBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cIrqEnGlobalBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnGlobalBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x64), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Global Interrupt Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnGlobalBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnGlobalBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Interrupt Enable Loss of Multi-block Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnLossMbLockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cIrqEnLossMbLockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnLossMbLockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x64), (uint32_t)bfValue, 0x20, 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Enable Loss of Multi-block Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnLossMbLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnLossMbLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x20, 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Interrupt Enable Loss of 64b66b Sync Header Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnLossSyncHeaderLockBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cIrqEnLossSyncHeaderLockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnLossSyncHeaderLockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x64), (uint32_t)bfValue, 0x10, 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Enable Loss of 64b66b Sync Header Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnLossSyncHeaderLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnLossSyncHeaderLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x10, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Interrupt Enable Multi-block Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnMbErrorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cIrqEnMbErrorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnMbErrorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x64), (uint32_t)bfValue, 0x80, 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Enable Multi-block Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnMbErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnMbErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x80, 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Interrupt Enable Overflow Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnOverflowErrorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cIrqEnOverflowErrorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnOverflowErrorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x64), (uint32_t)bfValue, 0x400, 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Enable Overflow Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnOverflowErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnOverflowErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x400, 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Interrupt Enable SYSREF Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnSysrefErrorBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cIrqEnSysrefErrorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnSysrefErrorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x64), (uint32_t)bfValue, 0x4, 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Enable SYSREF Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnSysrefErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnSysrefErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Interrupt Enable SYSREF Received + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnSysrefReceivedBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cIrqEnSysrefReceivedBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnSysrefReceivedBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x64), (uint32_t)bfValue, 0x2, 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Enable SYSREF Received + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqEnSysrefReceivedBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqEnSysrefReceivedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x64), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Status FEC Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqFecErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqFecErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x68), &rxBfData[0], 0x200, 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Status Loss of Multi-block Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqLossMbLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqLossMbLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x68), &rxBfData[0], 0x20, 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Status Loss of 64b66b Sync Header Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqLossSyncHeaderLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqLossSyncHeaderLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x68), &rxBfData[0], 0x10, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Status Multi-block Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqMbErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqMbErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x68), &rxBfData[0], 0x80, 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Status Overflow Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqOverflowErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqOverflowErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x68), &rxBfData[0], 0x400, 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Pending + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqPendingBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqPendingBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x60), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Status SYSREF Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqSysrefErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqSysrefErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x68), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Interrupt Status SYSREF Received + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cIrqSysrefReceivedBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cIrqSysrefReceivedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x68), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Lane Indicator 64b66b Sync Header Aligned + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cLane64b66bAlignBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cLane64b66bAlignBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x54), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Lane Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cLaneEnableBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cLaneEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cLaneEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x40), (uint32_t)bfValue, 0xFF, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Lane Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cLaneEnableBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cLaneEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x40), &rxBfData[0], 0xFF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Lane Indicator Multi-block Aligned + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cLaneMbAlignBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cLaneMbAlignBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x54), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Multi-block Lock Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cMbLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cMbLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x60), &rxBfData[0], 0x20, 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Meta Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cMetaModeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cMetaModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cMetaModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x38), (uint32_t)bfValue, 0x3, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Meta Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cMetaModeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cMetaModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x38), &rxBfData[0], 0x3, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Number of Lanes in Core + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cNumberOfLanesInCoreBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cNumberOfLanesInCoreBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4), &rxBfData[0], 0xF, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Reset, Fixed + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cResetFixedBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cResetFixedBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cResetFixedBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x20), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Reset, Fixed + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cResetFixedBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cResetFixedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x20), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief RX Buffer Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cRxBufferDelayBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 63U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cRxBufferDelayBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cRxBufferDelayBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x44), (uint32_t)bfValue, 0x3F, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief RX Buffer Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cRxBufferDelayBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cRxBufferDelayBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x44), &rxBfData[0], 0x3F, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Receive Error Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cRxErrorCntBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t channelId, + uint32_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cRxErrorCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + +#if FPGA9010_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9010_XilinxJesd204cRxErrorCntBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read to Single Register */ + fpga9010_BfRegisterRead(device, (baseAddr + 0x410 + channelId*128), &rxBfData[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Multi-block Lock Threshold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cRxMbThBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cRxMbThBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cRxMbThBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x4C), (uint32_t)bfValue, 0x7, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Multi-block Lock Threshold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cRxMbThBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cRxMbThBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x4C), &rxBfData[0], 0x7, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Sync Header Lock Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cSyncHeaderLockBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cSyncHeaderLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x60), &rxBfData[0], 0x10, 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief SYSREF Captured + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cSysrefCapturedBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cSysrefCapturedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x60), &rxBfData[0], 0x2, 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief SYSREF Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cSysrefDelayBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cSysrefDelayBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cSysrefDelayBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x50), (uint32_t)bfValue, 0xF0000, 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief SYSREF Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cSysrefDelayBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cSysrefDelayBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x50), &rxBfData[0], 0xF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief SYSREF Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cSysrefErrorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cSysrefErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x60), &rxBfData[0], 0x4, 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} +/** + * \brief Test Mode Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cTestModeBfSet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9010_XilinxJesd204cTestModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_VALUE_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cTestModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + fpga9010_BfFieldWrite(device, (baseAddr + 0x48), (uint32_t)bfValue, 0x1, 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return(device->common.error.newAction); +} + +/** + * \brief Test Mode Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cTestModeBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cTestModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x48), &rxBfData[0], 0x1, 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Version Major + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cVersionMajorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF000000, 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Version Minor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cVersionMinorBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF0000, 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/** + * \brief Revision + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9010_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9010_XilinxJesd204cVersionRevisionBfGet(adi_fpga9010_Device_t *device, + fpga9010_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t *bfValue) +{ + + uint32_t rxBfData[8] = { 0 }; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + +#if FPGA9010_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9010_BITFIELD_NULL_CHECK */ + +#if FPGA9010_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9010_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9010_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9010_XilinxJesd204cVersionRevisionBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9010_BITFIELD_ADDR_CHECK */ + + fpga9010_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + fpga9010_BfFieldRead(device, (baseAddr + 0x0), &rxBfData[0], 0xFF00, 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + fpga9010_BfReadAssembleData(device, &rxBfData[0x0], 0x1, &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t) data; + + return(device->common.error.newAction); +} + +/* EOF: fpga9010_bf_xilinx_jesd204c.c */ + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_jesd.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_jesd.c new file mode 100644 index 0000000..a395ce5 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_jesd.c @@ -0,0 +1,1760 @@ +/** + * \file: fpga9010_jesd.c + * + * \brief Contains private jesd related functions + * + * FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9010_user.h" +#include "adi_fpga9010.h" +#include "adi_fpga9010_error.h" +#include "../../public/include/adi_fpga9010_jesd.h" +#include "../../private/include/fpga9010_jesd.h" +#include "../../private/include/fpga9010_bf_xilinx_jesd204b.h" +#include "../../private/include/fpga9010_bf_xilinx_jesd204c.h" + +int32_t fpga9010_Jesd204BDeframerCfgSet(adi_fpga9010_Device_t *device, uint32_t deframerSelMask, adi_fpga9010_DeframerCfg_t *deframerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, deframerCfg); + + if ((deframerSelMask < ADI_FPGA9010_DEFRAMER_0) || (deframerSelMask > ADI_FPGA9010_DEFRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, deframerSelMask, "Invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((deframerSelMask & ADI_FPGA9010_DEFRAMER_0) == ADI_FPGA9010_DEFRAMER_0) + { + /* set ILA multiframes to 4 multiframes */ + recoveryAction = fpga9010_XilinxJesd204bIlaMultiframesBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_0, 3); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set deframer ila_multiframes"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Configure lane xbar */ + adi_fpga9010_RxLaneXBarCfgSet(device, ADI_FPGA9010_DEFRAMER_0, deframerCfg->laneXbar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure ILA support */ + recoveryAction = fpga9010_XilinxJesd204bIlaSupportEnBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_0, deframerCfg->ilaSupportEn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Deframer 0 ILA support"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure scrambling */ + recoveryAction = fpga9010_XilinxJesd204bScramblingEnBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_0, deframerCfg->scramblingEn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 0 scrambling"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure SYSREF settings */ + recoveryAction = fpga9010_XilinxJesd204bSysrefAlwaysBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_0, deframerCfg->sysRefAlways); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 0 SYSREF always"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204bSysrefDelayBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_0, deframerCfg->sysRefDelay); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 0 SYSREF delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204bSysrefRequiredOnResyncBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_0, deframerCfg->sysRefRequiredOnResync); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 0 SYSREF required on resync"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure octets per frame (F) */ + recoveryAction = fpga9010_XilinxJesd204bCfgFBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_0, deframerCfg->cfgF - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 0 F"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure frames per multiframe (K) */ + recoveryAction = fpga9010_XilinxJesd204bCfgKBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_0, deframerCfg->cfgK - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 0 K"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure lanes in use */ + recoveryAction = fpga9010_XilinxJesd204bLanesInUseBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_0, deframerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 0 lanes in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure subclass */ + recoveryAction = fpga9010_XilinxJesd204bCfgSubclassvBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_0, deframerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 0 subclass"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure RX buffer delay */ + recoveryAction = fpga9010_XilinxJesd204bRxBufferDelayBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_0, deframerCfg->rxBufferDly); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 0 RX buffer delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure error reporting on sync disable */ + recoveryAction = fpga9010_XilinxJesd204bDisErrOnSyncBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_0, deframerCfg->errReportingDisable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 0 error reporting on sync disable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* disable watchdog timer & set the self-clearing reset bit */ + recoveryAction = fpga9010_XilinxJesd204bWatchdogTimerDisableBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_0, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error disabling Deframer 0 watchdog timer"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((deframerSelMask & ADI_FPGA9010_DEFRAMER_1) == ADI_FPGA9010_DEFRAMER_1) + { + /* set ILA multiframes to 4 multiframes */ + recoveryAction = fpga9010_XilinxJesd204bIlaMultiframesBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_1, 3); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set deframer ila_multiframes"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Configure lane xbar */ + adi_fpga9010_RxLaneXBarCfgSet(device, ADI_FPGA9010_DEFRAMER_1, deframerCfg->laneXbar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure ILA support */ + recoveryAction = fpga9010_XilinxJesd204bIlaSupportEnBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_1, deframerCfg->ilaSupportEn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Deframer 2 ILA support"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure scrambling */ + recoveryAction = fpga9010_XilinxJesd204bScramblingEnBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_1, deframerCfg->scramblingEn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 scrambling"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure SYSREF settings */ + recoveryAction = fpga9010_XilinxJesd204bSysrefAlwaysBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_1, deframerCfg->sysRefAlways); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 SYSREF always"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204bSysrefDelayBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_1, deframerCfg->sysRefDelay); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 SYSREF delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204bSysrefRequiredOnResyncBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_1, deframerCfg->sysRefRequiredOnResync); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 SYSREF required on resync"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure octets per frame (F) */ + recoveryAction = fpga9010_XilinxJesd204bCfgFBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_1, deframerCfg->cfgF - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 F"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure frames per multiframe (K) */ + recoveryAction = fpga9010_XilinxJesd204bCfgKBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_1, deframerCfg->cfgK - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 K"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure lanes in use */ + recoveryAction = fpga9010_XilinxJesd204bLanesInUseBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_1, deframerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 lanes in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure subclass */ + recoveryAction = fpga9010_XilinxJesd204bCfgSubclassvBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_1, deframerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 subclass"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure RX buffer delay */ + recoveryAction = fpga9010_XilinxJesd204bRxBufferDelayBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_1, deframerCfg->rxBufferDly); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 RX buffer delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure error reporting on sync disable */ + recoveryAction = fpga9010_XilinxJesd204bDisErrOnSyncBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_1, deframerCfg->errReportingDisable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 error reporting on sync disable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* disable watchdog timer & set the self-clearing reset bit */ + recoveryAction = fpga9010_XilinxJesd204bWatchdogTimerDisableBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_1, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error disabling Deframer 2 watchdog timer"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((deframerSelMask & ADI_FPGA9010_DEFRAMER_2) == ADI_FPGA9010_DEFRAMER_2) + { + /* set ILA multiframes to 4 multiframes */ + recoveryAction = fpga9010_XilinxJesd204bIlaMultiframesBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_2, 3); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set deframer ila_multiframes"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Configure lane xbar */ + adi_fpga9010_RxLaneXBarCfgSet(device, ADI_FPGA9010_DEFRAMER_2, deframerCfg->laneXbar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure ILA support */ + recoveryAction = fpga9010_XilinxJesd204bIlaSupportEnBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_2, deframerCfg->ilaSupportEn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Deframer 2 ILA support"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure scrambling */ + recoveryAction = fpga9010_XilinxJesd204bScramblingEnBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_2, deframerCfg->scramblingEn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 scrambling"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure SYSREF settings */ + recoveryAction = fpga9010_XilinxJesd204bSysrefAlwaysBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_2, deframerCfg->sysRefAlways); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 SYSREF always"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204bSysrefDelayBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_2, deframerCfg->sysRefDelay); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 SYSREF delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204bSysrefRequiredOnResyncBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_2, deframerCfg->sysRefRequiredOnResync); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 SYSREF required on resync"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure octets per frame (F) */ + recoveryAction = fpga9010_XilinxJesd204bCfgFBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_2, deframerCfg->cfgF - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 F"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure frames per multiframe (K) */ + recoveryAction = fpga9010_XilinxJesd204bCfgKBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_2, deframerCfg->cfgK - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 K"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure lanes in use */ + recoveryAction = fpga9010_XilinxJesd204bLanesInUseBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_2, deframerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 lanes in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure subclass */ + recoveryAction = fpga9010_XilinxJesd204bCfgSubclassvBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_2, deframerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 subclass"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure RX buffer delay */ + recoveryAction = fpga9010_XilinxJesd204bRxBufferDelayBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_2, deframerCfg->rxBufferDly); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 RX buffer delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure error reporting on sync disable */ + recoveryAction = fpga9010_XilinxJesd204bDisErrOnSyncBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_2, deframerCfg->errReportingDisable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Deframer 2 error reporting on sync disable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* disable watchdog timer & set the self-clearing reset bit */ + recoveryAction = fpga9010_XilinxJesd204bWatchdogTimerDisableBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_2, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error disabling Deframer 2 watchdog timer"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t fpga9010_Jesd204BDeframerCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e deframerSel, adi_fpga9010_DeframerCfg_t *deframerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204bChanAddr_e deframerBase = FPGA9010_BF_JESD204B_DEFRAMER_0; + uint8_t byteRead = 0; + int8_t i = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, deframerCfg); + + /* Set correct addresses for the deframer selected */ + if (deframerSel == ADI_FPGA9010_DEFRAMER_0) + { + deframerBase = FPGA9010_BF_JESD204B_DEFRAMER_0; + } + else if (deframerSel == ADI_FPGA9010_DEFRAMER_1) + { + deframerBase = FPGA9010_BF_JESD204B_DEFRAMER_1; + } + else if (deframerSel == ADI_FPGA9010_DEFRAMER_2) + { + deframerBase = FPGA9010_BF_JESD204B_DEFRAMER_2; + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, deframerSel, "Invalid deframer selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* lane xbar */ + adi_fpga9010_RxLaneXBarCfgGet(device, deframerSel, &deframerCfg->laneXbar[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ILA support */ + recoveryAction = fpga9010_XilinxJesd204bIlaSupportEnBfGet(device, deframerBase, &deframerCfg->ilaSupportEn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting RX ILA support"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* scrambling */ + recoveryAction = fpga9010_XilinxJesd204bScramblingEnBfGet(device, deframerBase, &deframerCfg->scramblingEn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX scrambling"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* SYSREF settings */ + recoveryAction = fpga9010_XilinxJesd204bSysrefAlwaysBfGet(device, deframerBase, &deframerCfg->sysRefAlways); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX SYSREF always"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204bSysrefDelayBfGet(device, deframerBase, &deframerCfg->sysRefDelay); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX SYSREF delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204bSysrefRequiredOnResyncBfGet(device, deframerBase, &deframerCfg->sysRefRequiredOnResync); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX SYSREF required on resync"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* octets per frame (F) */ + recoveryAction = fpga9010_XilinxJesd204bCfgFBfGet(device, deframerBase, &byteRead); + deframerCfg->cfgF = byteRead + 1; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX F"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* frames per multiframe (K) */ + recoveryAction = fpga9010_XilinxJesd204bCfgKBfGet(device, deframerBase, &byteRead); + deframerCfg->cfgK = byteRead + 1; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX K"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* lanes in use */ + recoveryAction = fpga9010_XilinxJesd204bLanesInUseBfGet(device, deframerBase, &deframerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX lanes in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* subclass */ + recoveryAction = fpga9010_XilinxJesd204bCfgSubclassvBfGet(device, deframerBase, &deframerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX subclass"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* rxBufferDelay */ + recoveryAction = fpga9010_XilinxJesd204bRxBufferDelayBfGet(device, deframerBase, &deframerCfg->rxBufferDly); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX buffer delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* error reporting disable on sync */ + recoveryAction = fpga9010_XilinxJesd204bDisErrOnSyncBfGet(device, deframerBase, &deframerCfg->errReportingDisable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX error reporting disable on sync"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Reading ILA data per lane*/ + for (i = 0; i < ADI_FPGA9010_NUM_LANES; i++) + { + /* bank ID */ + recoveryAction = fpga9010_XilinxJesd204bIlaBidBfGet(device, deframerBase, i, &deframerCfg->bankId[i]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX bank ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* lane ID */ + recoveryAction = fpga9010_XilinxJesd204bCfgLaneIdBfGet(device, deframerBase, i, &deframerCfg->cfgLaneId[i]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX lane ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ilaS */ + recoveryAction = fpga9010_XilinxJesd204bIlaSBfGet(device, deframerBase, i, &byteRead); + deframerCfg->ilaS[i] = byteRead + 1; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX ilaS"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ilaM */ + recoveryAction = fpga9010_XilinxJesd204bIlaMBfGet(device, deframerBase, i, &byteRead); + deframerCfg->ilaM[i] = byteRead + 1; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX ilaM"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ilaN */ + recoveryAction = fpga9010_XilinxJesd204bIlaNBfGet(device, deframerBase, i, &byteRead); + deframerCfg->ilaN[i] = byteRead + 1; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX ilaM"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ilaNp */ + recoveryAction = fpga9010_XilinxJesd204bIlaNpBfGet(device, deframerBase, i, &byteRead); + deframerCfg->ilaNp[i] = byteRead + 1; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX ilaM"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* rxBufferAdj */ + recoveryAction = fpga9010_XilinxJesd204bRxBufAdjBfGet(device, deframerBase, i, &deframerCfg->rxBufferAdj[i]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading RX buffer adj"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t fpga9010_Jesd204BFramerCfgSet(adi_fpga9010_Device_t *device, uint8_t linkSelMask, adi_fpga9010_FramerCfg_t *framerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, framerCfg); + + if ((linkSelMask < ADI_FPGA9010_FRAMER_0) || (linkSelMask > ADI_FPGA9010_FRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, linkSelMask, "Invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Configure one or both framers */ + if ((linkSelMask & ADI_FPGA9010_FRAMER_0) == ADI_FPGA9010_FRAMER_0) + { + /* Configure lane xbar */ + adi_fpga9010_TxLaneXBarCfgSet(device, ADI_FPGA9010_FRAMER_0, framerCfg->laneXbar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure ILA support */ + recoveryAction = fpga9010_XilinxJesd204bIlaSupportEnBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, framerCfg->ilaSupportEn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Framer 0 ILA support"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure scrambling */ + recoveryAction = fpga9010_XilinxJesd204bScramblingEnBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, framerCfg->scramblingEn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 scrambling"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure SYSREF settings */ + recoveryAction = fpga9010_XilinxJesd204bSysrefAlwaysBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, framerCfg->sysRefAlways); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 SYSREF always"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204bSysrefDelayBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, framerCfg->sysRefDelay); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 SYSREF delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204bSysrefRequiredOnResyncBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, framerCfg->sysRefRequiredOnResync); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 SYSREF required on resync"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure ILA multiframes */ + recoveryAction = fpga9010_XilinxJesd204bIlaMultiframesBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, (uint8_t)(framerCfg->ilaMultiFrames - 1)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 ILA multiframes"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure octets per frame (F) */ + recoveryAction = fpga9010_XilinxJesd204bCfgFBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, (uint8_t)(framerCfg->cfgF - 1)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 F"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure frames per multiframe (K) */ + recoveryAction = fpga9010_XilinxJesd204bCfgKBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, framerCfg->cfgK - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 K"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure lanes in use */ + recoveryAction = fpga9010_XilinxJesd204bLanesInUseBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, framerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 lanes in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure subclass */ + recoveryAction = fpga9010_XilinxJesd204bCfgSubclassvBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, framerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 subclass"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* For ILA configuration registers, TX uses lane 0 register addresses for setup */ + /* configure Bank ID */ + recoveryAction = fpga9010_XilinxJesd204bIlaBidBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, 0, framerCfg->bankId); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 bank ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure Device ID */ + recoveryAction = fpga9010_XilinxJesd204bIlaDidBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, 0, framerCfg->deviceId); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 device ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure control bits per sample (CS)*/ + recoveryAction = fpga9010_XilinxJesd204bIlaCsBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, 0, framerCfg->ilaCs); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 control bits per sample (CS)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure total bits per sample (Np) */ + recoveryAction = fpga9010_XilinxJesd204bIlaNpBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, 0, framerCfg->ilaNp - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 total bits per sample (Np)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure converter resolution (N) */ + recoveryAction = fpga9010_XilinxJesd204bIlaNBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, 0, framerCfg->ilaN - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 converter resolution (N)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure converters per device (M) */ + recoveryAction = fpga9010_XilinxJesd204bIlaMBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, 0, framerCfg->ilaM - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 converters per device (M)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure control words per frame (CF) */ + recoveryAction = fpga9010_XilinxJesd204bIlaCfBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, 0, framerCfg->ilaCf); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 control words per frame (CF)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure high density format (HD) */ + recoveryAction = fpga9010_XilinxJesd204bIlaHdBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, 0, framerCfg->ilaHd); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 high density format (HD)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure samples per converter per frame (S) */ + recoveryAction = fpga9010_XilinxJesd204bIlaSBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, 0, framerCfg->ilaS - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 0 samples per converter per frame (S) "); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* disable watchdog timer & set the self-clearing reset bit */ + recoveryAction = fpga9010_XilinxJesd204bWatchdogTimerDisableBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error disabling Framer 0 watchdog timer"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((linkSelMask & ADI_FPGA9010_FRAMER_1) == ADI_FPGA9010_FRAMER_1) + { + /* Configure lane xbar */ + adi_fpga9010_TxLaneXBarCfgSet(device, ADI_FPGA9010_FRAMER_1, framerCfg->laneXbar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure ILA support */ + recoveryAction = fpga9010_XilinxJesd204bIlaSupportEnBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, framerCfg->ilaSupportEn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Framer 1 ILA support"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure scrambling */ + recoveryAction = fpga9010_XilinxJesd204bScramblingEnBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, framerCfg->scramblingEn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 scrambling"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure SYSREF settings */ + recoveryAction = fpga9010_XilinxJesd204bSysrefAlwaysBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, framerCfg->sysRefAlways); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 SYSREF always"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204bSysrefDelayBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, framerCfg->sysRefDelay); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 SYSREF delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204bSysrefRequiredOnResyncBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, framerCfg->sysRefRequiredOnResync); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 SYSREF required on resync"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure ILA multiframes */ + recoveryAction = fpga9010_XilinxJesd204bIlaMultiframesBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, (uint8_t)(framerCfg->ilaMultiFrames - 1)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 ILA multiframes"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure octets per frame (F) */ + recoveryAction = fpga9010_XilinxJesd204bCfgFBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, (uint8_t)(framerCfg->cfgF - 1)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 F"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure frames per multiframe (K) */ + recoveryAction = fpga9010_XilinxJesd204bCfgKBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, framerCfg->cfgK - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 K"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure lanes in use */ + recoveryAction = fpga9010_XilinxJesd204bLanesInUseBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, framerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 lanes in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure subclass */ + recoveryAction = fpga9010_XilinxJesd204bCfgSubclassvBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, framerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 subclass"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* For ILA configuration registers, TX uses lane 0 register addresses for setup */ + /* configure Bank ID */ + recoveryAction = fpga9010_XilinxJesd204bIlaBidBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, 0, framerCfg->bankId); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 bank ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure Device ID */ + recoveryAction = fpga9010_XilinxJesd204bIlaDidBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, 0, framerCfg->deviceId); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 device ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure control bits per sample (CS)*/ + recoveryAction = fpga9010_XilinxJesd204bIlaCsBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, 0, framerCfg->ilaCs); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 control bits per sample (CS)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure total bits per sample (Np) */ + recoveryAction = fpga9010_XilinxJesd204bIlaNpBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, 0, framerCfg->ilaNp - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 total bits per sample (Np)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure converter resolution (N) */ + recoveryAction = fpga9010_XilinxJesd204bIlaNBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, 0, framerCfg->ilaN - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 converter resolution (N)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure converters per device (M) */ + recoveryAction = fpga9010_XilinxJesd204bIlaMBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, 0, framerCfg->ilaM - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 converters per device (M)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure control words per frame (CF) */ + recoveryAction = fpga9010_XilinxJesd204bIlaCfBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, 0, framerCfg->ilaCf); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 control words per frame (CF)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure high density format (HD) */ + recoveryAction = fpga9010_XilinxJesd204bIlaHdBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, 0, framerCfg->ilaHd); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 high density format (HD)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure samples per converter per frame (S) */ + recoveryAction = fpga9010_XilinxJesd204bIlaSBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, 0, framerCfg->ilaS - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error configuring Framer 1 samples per converter per frame (S) "); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* disable watchdog timer & set the self-clearing reset bit */ + recoveryAction = fpga9010_XilinxJesd204bWatchdogTimerDisableBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error disabling Framer 1 watchdog timer"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t fpga9010_Jesd204BFramerCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e framerSel, adi_fpga9010_FramerCfg_t *framerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204bChanAddr_e framerBase = FPGA9010_BF_JESD204B_DEFRAMER_0; + uint8_t byteRead = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, framerCfg); + + /* Set correct addresses for the framer selected */ + if (framerSel == ADI_FPGA9010_FRAMER_0) + { + framerBase = FPGA9010_BF_JESD204B_FRAMER_0; + } + else if (framerSel == ADI_FPGA9010_FRAMER_1) + { + framerBase = FPGA9010_BF_JESD204B_FRAMER_1; + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, framerSel, "Invalid framer selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* lane xbar */ + adi_fpga9010_TxLaneXBarCfgGet(device, framerSel, &framerCfg->laneXbar[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ILA support */ + recoveryAction = fpga9010_XilinxJesd204bIlaSupportEnBfGet(device, framerBase, &framerCfg->ilaSupportEn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading ILA support"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* scrambling */ + recoveryAction = fpga9010_XilinxJesd204bScramblingEnBfGet(device, framerBase, &framerCfg->scramblingEn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading scrambling"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* SYSREF settings */ + recoveryAction = fpga9010_XilinxJesd204bSysrefAlwaysBfGet(device, framerBase, &framerCfg->sysRefAlways); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading SYSREF always"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204bSysrefDelayBfGet(device, framerBase, &framerCfg->sysRefDelay); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading SYSREF delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204bSysrefRequiredOnResyncBfGet(device, framerBase, &framerCfg->sysRefRequiredOnResync); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading SYSREF required on resync"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ILA multiframes */ + recoveryAction = fpga9010_XilinxJesd204bIlaMultiframesBfGet(device, framerBase, &byteRead); + framerCfg->ilaMultiFrames = (uint16_t)byteRead + 1; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading ILA multiframes"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* octets per frame (F) */ + recoveryAction = fpga9010_XilinxJesd204bCfgFBfGet(device, framerBase, &byteRead); + framerCfg->cfgF = (uint16_t)byteRead + 1; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading F"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* frames per multiframe (K) */ + recoveryAction = fpga9010_XilinxJesd204bCfgKBfGet(device, framerBase, &byteRead); + framerCfg->cfgK = byteRead + 1; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading K"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* lanes in use */ + recoveryAction = fpga9010_XilinxJesd204bLanesInUseBfGet(device, framerBase, &framerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading lanes in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* subclass */ + recoveryAction = fpga9010_XilinxJesd204bCfgSubclassvBfGet(device, framerBase, &framerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading subclass"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* For ILA configuration registers, TX uses lane 0 register addresses for setup */ + /* Bank ID */ + recoveryAction = fpga9010_XilinxJesd204bIlaBidBfGet(device, framerBase, 0, &framerCfg->bankId); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading bank ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Device ID */ + recoveryAction = fpga9010_XilinxJesd204bIlaDidBfGet(device, framerBase, 0, &framerCfg->deviceId); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading device ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* control bits per sample (CS)*/ + recoveryAction = fpga9010_XilinxJesd204bIlaCsBfGet(device, framerBase, 0, &framerCfg->ilaCs); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading control bits per sample (CS)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* total bits per sample (Np) */ + recoveryAction = fpga9010_XilinxJesd204bIlaNpBfGet(device, framerBase, 0, &byteRead); + framerCfg->ilaNp = byteRead + 1; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading total bits per sample (Np)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* converter resolution (N) */ + recoveryAction = fpga9010_XilinxJesd204bIlaNBfGet(device, framerBase, 0, &byteRead); + framerCfg->ilaN = byteRead + 1; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading converter resolution (N)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* converters per device (M) */ + recoveryAction = fpga9010_XilinxJesd204bIlaMBfGet(device, framerBase, 0, &byteRead); + framerCfg->ilaM = byteRead + 1; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading converters per device (M)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* control words per frame (CF) */ + recoveryAction = fpga9010_XilinxJesd204bIlaCfBfGet(device, framerBase, 0, &framerCfg->ilaCf); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading control words per frame (CF)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* high density format (HD) */ + recoveryAction = fpga9010_XilinxJesd204bIlaHdBfGet(device, framerBase, 0, &framerCfg->ilaHd); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading high density format (HD)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* samples per converter per frame (S) */ + recoveryAction = fpga9010_XilinxJesd204bIlaSBfGet(device, framerBase, 0, &byteRead); + framerCfg->ilaS = byteRead + 1; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading samples per converter per frame (S) "); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t fpga9010_Jesd204BFramerResetGet(adi_fpga9010_Device_t *device, uint32_t framerSelMask, uint8_t *resetBits) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t resetGet = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, resetBits); + + if ((framerSelMask < ADI_FPGA9010_FRAMER_0) || (framerSelMask > ADI_FPGA9010_FRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, framerSelMask, "Invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *resetBits = 0x00; + + if ((framerSelMask & ADI_FPGA9010_FRAMER_0) == ADI_FPGA9010_FRAMER_0) + { + recoveryAction = fpga9010_XilinxJesd204bResetSelfClearingBfGet(device, FPGA9010_BF_JESD204B_FRAMER_0, &resetGet); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading Framer 0 reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *resetBits |= (resetGet & 0x01) << 0; + } + if ((framerSelMask & ADI_FPGA9010_FRAMER_1) == ADI_FPGA9010_FRAMER_1) + { + recoveryAction = fpga9010_XilinxJesd204bResetSelfClearingBfGet(device, FPGA9010_BF_JESD204B_FRAMER_1, &resetGet); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading Framer 1 reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *resetBits |= (resetGet & 0x01) << 1; + } + + return recoveryAction; +} + +int32_t fpga9010_Jesd204BFramerReset(adi_fpga9010_Device_t *device, uint8_t framerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204bChanAddr_e instanceAddress = FPGA9010_BF_JESD204B_FRAMER_0; + uint32_t i = 0; + uint32_t j = 0; + adi_fpga9010_FramerSel_e framerSel = ADI_FPGA9010_FRAMER_0; + uint8_t resetBit = 1; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if ((framerSelMask < ADI_FPGA9010_FRAMER_0) || (framerSelMask > ADI_FPGA9010_FRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, framerSelMask, "Invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_FRAMERS; i++) + { + framerSel = (adi_fpga9010_FramerSel_e)((uint8_t)(1 << i)); + + switch (framerSel) + { + case ADI_FPGA9010_FRAMER_0: + instanceAddress = FPGA9010_BF_JESD204B_FRAMER_0; + break; + case ADI_FPGA9010_FRAMER_1: + instanceAddress = FPGA9010_BF_JESD204B_FRAMER_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)framerSel & framerSelMask) > 0) + { + resetBit = 1; + + recoveryAction = fpga9010_XilinxJesd204bResetFixedBfSet(device, instanceAddress, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error clearing Framer 0 fixed reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204bResetSelfClearingBfSet(device, instanceAddress, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Framer 0 self-clearing reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Give the framer 50ms to reset itself */ + for (j = 0; j < 5; j++) + { + if ((resetBit & 0x1) > 0) + { + recoveryAction = fpga9010_XilinxJesd204bResetSelfClearingBfGet(device, instanceAddress, &resetBit); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading Framer 0 self-clearing reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_common_hal_Wait_ms(&device->common, 10); + } + else + { + break; + } + } + + if ((resetBit & 0x1) > 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_LINK_LAYER_RESET_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Framer 0 self-clearing bit did not clear"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return recoveryAction; +} + +int32_t fpga9010_Jesd204BFramerDisable(adi_fpga9010_Device_t *device, uint8_t framerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if ((framerSelMask < ADI_FPGA9010_FRAMER_0) || (framerSelMask > ADI_FPGA9010_FRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, framerSelMask, "Invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((framerSelMask & ADI_FPGA9010_FRAMER_0) == ADI_FPGA9010_FRAMER_0) + { + recoveryAction = fpga9010_XilinxJesd204bResetFixedBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Framer 0 fixed reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((framerSelMask & ADI_FPGA9010_FRAMER_1) == ADI_FPGA9010_FRAMER_1) + { + recoveryAction = fpga9010_XilinxJesd204bResetFixedBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Framer 1 fixed reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t fpga9010_Jesd204BDeframerReset(adi_fpga9010_Device_t *device, uint8_t deframerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204bChanAddr_e instanceAddress = FPGA9010_BF_JESD204B_DEFRAMER_0; + uint32_t i = 0; + uint32_t j = 0; + adi_fpga9010_DeframerSel_e deframerSel = ADI_FPGA9010_DEFRAMER_0; + uint8_t resetBit = 1; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if ((deframerSelMask < ADI_FPGA9010_DEFRAMER_0) || (deframerSelMask > ADI_FPGA9010_DEFRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, deframerSelMask, "Invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_DEFRAMERS; i++) + { + deframerSel = (adi_fpga9010_DeframerSel_e)((uint8_t)(1 << i)); + + switch (deframerSel) + { + case ADI_FPGA9010_DEFRAMER_0: + instanceAddress = FPGA9010_BF_JESD204B_DEFRAMER_0; + break; + case ADI_FPGA9010_DEFRAMER_1: + instanceAddress = FPGA9010_BF_JESD204B_DEFRAMER_1; + break; + case ADI_FPGA9010_DEFRAMER_2: + instanceAddress = FPGA9010_BF_JESD204B_DEFRAMER_2; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)deframerSel & deframerSelMask) > 0) + { + recoveryAction = fpga9010_XilinxJesd204bResetFixedBfSet(device, instanceAddress, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error clearing Deframer fixed reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204bResetSelfClearingBfSet(device, instanceAddress, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Deframer self-clearing reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Give the deframer 50ms to reset itself */ + for (j = 0; j < 5; j++) + { + if ((resetBit & 0x1) > 0) + { + recoveryAction = fpga9010_XilinxJesd204bResetSelfClearingBfGet(device, instanceAddress, &resetBit); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading Deframer self-clearing reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_common_hal_Wait_ms(&device->common, 10); + } + else + { + break; + } + } + + if ((resetBit & 0x1) > 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_LINK_LAYER_RESET_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Deframer self-clearing bit did not clear"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return recoveryAction; +} + +int32_t fpga9010_Jesd204BDeframerDisable(adi_fpga9010_Device_t *device, uint8_t deframerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if ((deframerSelMask < ADI_FPGA9010_DEFRAMER_0) || (deframerSelMask > ADI_FPGA9010_DEFRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, deframerSelMask, "Invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((deframerSelMask & ADI_FPGA9010_DEFRAMER_0) == ADI_FPGA9010_DEFRAMER_0) + { + recoveryAction = fpga9010_XilinxJesd204bResetFixedBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_0, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Deframer 0 fixed reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((deframerSelMask & ADI_FPGA9010_DEFRAMER_1) == ADI_FPGA9010_DEFRAMER_1) + { + recoveryAction = fpga9010_XilinxJesd204bResetFixedBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_1, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Deframer 1 fixed reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((deframerSelMask & ADI_FPGA9010_DEFRAMER_2) == ADI_FPGA9010_DEFRAMER_2) + { + recoveryAction = fpga9010_XilinxJesd204bResetFixedBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_2, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Deframer 2 fixed reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t fpga9010_Jesd204BDeframerStatusGet(adi_fpga9010_Device_t *device, uint8_t deframerSelMask, uint8_t *status) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t statusGet = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, status); + + if ((deframerSelMask < ADI_FPGA9010_DEFRAMER_0) || (deframerSelMask > ADI_FPGA9010_DEFRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, deframerSelMask, "Invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *status = 0x00; + + if ((deframerSelMask & ADI_FPGA9010_DEFRAMER_0) == ADI_FPGA9010_DEFRAMER_0) + { + recoveryAction = fpga9010_XilinxJesd204bSyncStatusBfGet(device, FPGA9010_BF_JESD204B_DEFRAMER_0, &statusGet); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading Deframer 0 reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *status |= (statusGet & 0x01) << 0; + } + if ((deframerSelMask & ADI_FPGA9010_DEFRAMER_1) == ADI_FPGA9010_DEFRAMER_1) + { + recoveryAction = fpga9010_XilinxJesd204bSyncStatusBfGet(device, FPGA9010_BF_JESD204B_DEFRAMER_1, &statusGet); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading Deframer 1 reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *status |= (statusGet & 0x01) << 1; + } + if ((deframerSelMask & ADI_FPGA9010_DEFRAMER_2) == ADI_FPGA9010_DEFRAMER_2) + { + recoveryAction = fpga9010_XilinxJesd204bSyncStatusBfGet(device, FPGA9010_BF_JESD204B_DEFRAMER_2, &statusGet); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error reading Deframer 2 reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *status |= (statusGet & 0x01) << 2; + } + + return recoveryAction; +} + +int32_t fpga9010_Jesd204CDeframerCfgSet(adi_fpga9010_Device_t *device, uint32_t deframerSelMask, adi_fpga9010_DeframerCfg_t *deframerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_0; + uint32_t i = 0; + adi_fpga9010_DeframerSel_e deframerSel = ADI_FPGA9010_DEFRAMER_0; + uint32_t firstUnusedLaneNum = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, deframerCfg); + + if ((deframerSelMask < ADI_FPGA9010_DEFRAMER_0) || (deframerSelMask > ADI_FPGA9010_DEFRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, deframerSelMask, "Invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (deframerCfg->lanesInUse == 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, deframerCfg->lanesInUse, "lanesInUse must be greater than 0."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find the first unused lane. Starting from this lane fill the remainder of the lane xbar with the + last good phy lane. This is a bug in the JESD204C Xilinx Rx link layer module */ + for (i = 0; i < ADI_FPGA9010_NUM_LANES; i++) + { + if ((deframerCfg->lanesInUse & (1 << i)) == 0) + { + firstUnusedLaneNum = i; + break; + } + } + + for (i = firstUnusedLaneNum; i < ADI_FPGA9010_NUM_LANES; i++) + { + deframerCfg->laneXbar[i] = deframerCfg->laneXbar[firstUnusedLaneNum - 1]; + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_DEFRAMERS; i++) + { + deframerSel = (adi_fpga9010_DeframerSel_e)((uint8_t)(1 << i)); + + switch (deframerSel) + { + case ADI_FPGA9010_DEFRAMER_0: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_0; + deframerCfg->lanesInUse = 0xF; + break; + case ADI_FPGA9010_DEFRAMER_1: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_1; + deframerCfg->lanesInUse = 0xF; + break; + case ADI_FPGA9010_DEFRAMER_2: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_2; + deframerCfg->lanesInUse = 0x3; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)deframerSel & deframerSelMask) > 0) + { + /* Configure lane xbar */ + adi_fpga9010_RxLaneXBarCfgSet(device, (adi_fpga9010_DeframerSel_e)deframerSel, deframerCfg->laneXbar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cCfgMbInEmbBfSet(device, instanceAddress, deframerCfg->cfgE); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set cfgE."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cMetaModeBfSet(device, instanceAddress, deframerCfg->ctrlMetaMode); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set meta mode."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cRxBufferDelayBfSet(device, instanceAddress, deframerCfg->ctrlRxBufAdv); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set buffer advance bitfield."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cRxMbThBfSet(device, instanceAddress, deframerCfg->ctrlRxMBlockTh - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set MB lock threshold."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cLaneEnableBfSet(device, instanceAddress, deframerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set lanes enabled."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9010_Jesd204cLinkLayerIrqEnSet(device, (uint8_t)deframerSel, deframerCfg->ctrlIrq); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t fpga9010_Jesd204CDeframerCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e deframerSel, adi_fpga9010_DeframerCfg_t *deframerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204cChanAddr_e deframerBase = FPGA9010_BF_JESD204C_DEFRAMER_0; + uint8_t registerValue = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, deframerCfg); + + /* Set correct addresses for the deframer selected */ + if (deframerSel == ADI_FPGA9010_DEFRAMER_0) + { + deframerBase = FPGA9010_BF_JESD204C_DEFRAMER_0; + } + else if (deframerSel == ADI_FPGA9010_DEFRAMER_1) + { + deframerBase = FPGA9010_BF_JESD204C_DEFRAMER_1; + } + else if (deframerSel == ADI_FPGA9010_DEFRAMER_2) + { + deframerBase = FPGA9010_BF_JESD204C_DEFRAMER_2; + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, deframerSel, "Invalid deframer selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* lane xbar */ + recoveryAction = adi_fpga9010_RxLaneXBarCfgGet(device, deframerSel, &deframerCfg->laneXbar[0]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, deframerCfg->laneXbar, "Error reading RX Lane XBar"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cEnableCmdInterfaceBfGet(device, deframerBase, &deframerCfg->enableCmdInterface); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to get cmd interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cEnableDataInterfaceBfGet(device, deframerBase, &deframerCfg->enableDataInterface); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to get data interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cCfgMbInEmbBfGet(device, deframerBase, &deframerCfg->cfgE); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to get cfgE."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cMetaModeBfGet(device, deframerBase, &deframerCfg->ctrlMetaMode); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to get meta mode."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cRxBufferDelayBfGet(device, deframerBase, &deframerCfg->ctrlRxBufAdv); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to get buffer advance bitfield."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cRxMbThBfGet(device, deframerBase, ®isterValue); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to get MB lock threshold."); + ADI_ERROR_RETURN(device->common.error.newAction); + deframerCfg->ctrlRxMBlockTh = registerValue + 1; + + recoveryAction = fpga9010_XilinxJesd204cLaneEnableBfGet(device, deframerBase, &deframerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to get lanes enabled."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9010_Jesd204cLinkLayerIrqEnGet(device, (uint8_t)deframerSel, &deframerCfg->ctrlIrq); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t fpga9010_Jesd204CFramerCfgSet(adi_fpga9010_Device_t *device, uint32_t framerSelMask, adi_fpga9010_FramerCfg_t *framerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_0; + uint32_t i = 0; + adi_fpga9010_FramerSel_e framerSel = ADI_FPGA9010_FRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, framerCfg); + + if ((framerSelMask < ADI_FPGA9010_FRAMER_0) || (framerSelMask > ADI_FPGA9010_FRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, framerSelMask, "Invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_FRAMERS; i++) + { + framerSel = (adi_fpga9010_FramerSel_e)((uint8_t)(1 << i)); + + switch (framerSel) + { + case ADI_FPGA9010_FRAMER_0: + instanceAddress = FPGA9010_BF_JESD204C_FRAMER_0; + break; + case ADI_FPGA9010_FRAMER_1: + instanceAddress = FPGA9010_BF_JESD204C_FRAMER_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)framerSel & framerSelMask) > 0) + { + /* Configure lane xbar */ + adi_fpga9010_TxLaneXBarCfgSet(device, (adi_fpga9010_FramerSel_e)framerSel, framerCfg->laneXbar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cCfgMbInEmbBfSet(device, instanceAddress, framerCfg->cfgE); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set cfgE."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cMetaModeBfSet(device, instanceAddress, framerCfg->ctrlMetaMode); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set meta mode."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cLaneEnableBfSet(device, instanceAddress, framerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to get lanes enabled."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9010_Jesd204cLinkLayerIrqEnSet(device, (uint8_t)(framerSel << ADI_FPGA9010_NUM_OF_DEFRAMERS), framerCfg->ctrlIrq); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t fpga9010_Jesd204CFramerCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e framerSel, adi_fpga9010_FramerCfg_t *framerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204cChanAddr_e framerBase = FPGA9010_BF_JESD204C_FRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, framerCfg); + + /* Set correct addresses for the framer selected */ + if (framerSel == ADI_FPGA9010_FRAMER_0) + { + framerBase = FPGA9010_BF_JESD204C_FRAMER_0; + } + else if (framerSel == ADI_FPGA9010_FRAMER_1) + { + framerBase = FPGA9010_BF_JESD204C_FRAMER_1; + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, framerSel, "Invalid framer selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* lane xbar */ + recoveryAction = adi_fpga9010_TxLaneXBarCfgGet(device, framerSel, &framerCfg->laneXbar[0]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, framerCfg->laneXbar, "Error reading TX Lane XBar"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cEnableCmdInterfaceBfGet(device, framerBase, &framerCfg->enableCmdInterface); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to get cmd interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cEnableDataInterfaceBfGet(device, framerBase, &framerCfg->enableDataInterface); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to get data interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cCfgMbInEmbBfGet(device, framerBase, &framerCfg->cfgE); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to get cfgE."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cMetaModeBfGet(device, framerBase, &framerCfg->ctrlMetaMode); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to get meta mode."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cLaneEnableBfGet(device, framerBase, &framerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to get lanes enabled."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9010_Jesd204cLinkLayerIrqEnGet(device, (uint8_t)(framerSel << ADI_FPGA9010_NUM_OF_DEFRAMERS), &framerCfg->ctrlIrq); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t fpga9010_Jesd204CFramerResetGet(adi_fpga9010_Device_t *device, uint32_t framerSelMask, uint8_t *resetBits) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t resetGet = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, resetBits); + + if ((framerSelMask < ADI_FPGA9010_FRAMER_0) || (framerSelMask > ADI_FPGA9010_FRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, framerSelMask, "Invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *resetBits = 0x00; + + if ((framerSelMask & ADI_FPGA9010_FRAMER_0) == ADI_FPGA9010_FRAMER_0) + { + recoveryAction = fpga9010_XilinxJesd204cResetFixedBfGet(device, FPGA9010_BF_JESD204C_FRAMER_0, &resetGet); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading Framer 0 reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *resetBits |= (resetGet & 0x01) << 0; + } + if ((framerSelMask & ADI_FPGA9010_FRAMER_1) == ADI_FPGA9010_FRAMER_1) + { + recoveryAction = fpga9010_XilinxJesd204cResetFixedBfGet(device, FPGA9010_BF_JESD204C_FRAMER_1, &resetGet); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading Framer 1 reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *resetBits |= (resetGet & 0x01) << 1; + } + + return recoveryAction; +} + +int32_t fpga9010_Jesd204CFramerReset(adi_fpga9010_Device_t *device, uint8_t framerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9010_BF_JESD204C_FRAMER_0; + uint32_t i = 0; + uint32_t j = 0; + adi_fpga9010_FramerSel_e framerSel = ADI_FPGA9010_FRAMER_0; + uint8_t resetBit = 1; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if ((framerSelMask < ADI_FPGA9010_FRAMER_0) || (framerSelMask > ADI_FPGA9010_FRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, framerSelMask, "Invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_FRAMERS; i++) + { + framerSel = (adi_fpga9010_FramerSel_e)((uint8_t)(1 << i)); + + switch (framerSel) + { + case ADI_FPGA9010_FRAMER_0: + instanceAddress = FPGA9010_BF_JESD204C_FRAMER_0; + break; + case ADI_FPGA9010_FRAMER_1: + instanceAddress = FPGA9010_BF_JESD204C_FRAMER_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)framerSel & framerSelMask) > 0) + { + resetBit = 1; + + recoveryAction = fpga9010_XilinxJesd204cResetFixedBfSet(device, instanceAddress, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting Framer reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cResetFixedBfSet(device, instanceAddress, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error clearing Framer reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Give the framer 50ms to reset itself */ + for (j = 0; j < 5; j++) + { + if ((resetBit & 0x1) > 0) + { + recoveryAction = fpga9010_XilinxJesd204cResetFixedBfGet(device, instanceAddress, &resetBit); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading Framer reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_common_hal_Wait_ms(&device->common, 10); + } + else + { + break; + } + } + + if ((resetBit & 0x1) > 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Framer did not reset correctly"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return recoveryAction; +} + +int32_t fpga9010_Jesd204CFramerDisable(adi_fpga9010_Device_t *device, uint8_t framerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9010_BF_JESD204C_FRAMER_0; + uint32_t i = 0; + adi_fpga9010_FramerSel_e framerSel = ADI_FPGA9010_FRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if ((framerSelMask < ADI_FPGA9010_FRAMER_0) || (framerSelMask > ADI_FPGA9010_FRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, framerSelMask, "Invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_FRAMERS; i++) + { + framerSel = (adi_fpga9010_FramerSel_e)((uint8_t)(1 << i)); + + switch (framerSel) + { + case ADI_FPGA9010_FRAMER_0: + instanceAddress = FPGA9010_BF_JESD204C_FRAMER_0; + break; + case ADI_FPGA9010_FRAMER_1: + instanceAddress = FPGA9010_BF_JESD204C_FRAMER_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)framerSel & framerSelMask) > 0) + { + /* These two bitfields are tied to the LEDs on the ADS8. Zero out to ensure the LEDs are turned off */ + recoveryAction = fpga9010_XilinxJesd204cEnableCmdInterfaceBfSet(device, instanceAddress, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set cmd interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cEnableDataInterfaceBfSet(device, instanceAddress, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set data interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cResetFixedBfSet(device, instanceAddress, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting Framer 0 reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t fpga9010_Jesd204CDeframerReset(adi_fpga9010_Device_t *device, uint8_t deframerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_0; + uint32_t i = 0; + uint32_t j = 0; + adi_fpga9010_DeframerSel_e deframerSel = ADI_FPGA9010_DEFRAMER_0; + uint8_t resetBit = 1; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if ((deframerSelMask < ADI_FPGA9010_DEFRAMER_0) || (deframerSelMask > ADI_FPGA9010_DEFRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, deframerSelMask, "Invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_DEFRAMERS; i++) + { + deframerSel = (adi_fpga9010_DeframerSel_e)((uint8_t)(1 << i)); + + switch (deframerSel) + { + case ADI_FPGA9010_DEFRAMER_0: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_0; + break; + case ADI_FPGA9010_DEFRAMER_1: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_1; + break; + case ADI_FPGA9010_DEFRAMER_2: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_2; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)deframerSel & deframerSelMask) > 0) + { + recoveryAction = fpga9010_XilinxJesd204cResetFixedBfSet(device, instanceAddress, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting Deframer reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cResetFixedBfSet(device, instanceAddress, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error clearing Deframer reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Give the deframer 50ms to reset itself */ + for (j = 0; j < 5; j++) + { + if ((resetBit & 0x1) > 0) + { + recoveryAction = fpga9010_XilinxJesd204cResetFixedBfGet(device, instanceAddress, &resetBit); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading Deframer reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_common_hal_Wait_ms(&device->common, 10); + } + else + { + break; + } + } + + if ((resetBit & 0x1) > 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Deframer did not reset correctly"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return recoveryAction; +} + +int32_t fpga9010_Jesd204CDeframerDisable(adi_fpga9010_Device_t *device, uint8_t deframerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_0; + uint32_t i = 0; + adi_fpga9010_DeframerSel_e deframerSel = ADI_FPGA9010_DEFRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if ((deframerSelMask < ADI_FPGA9010_DEFRAMER_0) || (deframerSelMask > ADI_FPGA9010_DEFRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, deframerSelMask, "Invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_DEFRAMERS; i++) + { + deframerSel = (adi_fpga9010_DeframerSel_e)((uint8_t)(1 << i)); + + switch (deframerSel) + { + case ADI_FPGA9010_DEFRAMER_0: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_0; + break; + case ADI_FPGA9010_DEFRAMER_1: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_1; + break; + case ADI_FPGA9010_DEFRAMER_2: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_2; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)deframerSel & deframerSelMask) > 0) + { + /* These two bitfields are tied to the LEDs on the ADS8. Zero out to ensure the LEDs are turned off */ + recoveryAction = fpga9010_XilinxJesd204cEnableCmdInterfaceBfSet(device, instanceAddress, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set cmd interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cEnableDataInterfaceBfSet(device, instanceAddress, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set data interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cResetFixedBfSet(device, instanceAddress, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting Deframer reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t fpga9010_Jesd204CDeframerStatusGet(adi_fpga9010_Device_t *device, uint8_t deframerSelMask, uint8_t *status) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t syncHeaderStatusGet = 0; + uint8_t mbLockStatusGet = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, status); + + if ((deframerSelMask < ADI_FPGA9010_DEFRAMER_0) || (deframerSelMask > ADI_FPGA9010_DEFRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, deframerSelMask, "Invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *status = 0x00; + + if ((deframerSelMask & ADI_FPGA9010_DEFRAMER_0) == ADI_FPGA9010_DEFRAMER_0) + { + recoveryAction = fpga9010_XilinxJesd204cMbLockBfGet(device, FPGA9010_BF_JESD204C_DEFRAMER_0, &mbLockStatusGet); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading Deframer 0 mb lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_XilinxJesd204cSyncHeaderLockBfGet(device, FPGA9010_BF_JESD204C_DEFRAMER_0, &syncHeaderStatusGet); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading Deframer 0 loss sync header lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *status |= (mbLockStatusGet & syncHeaderStatusGet) << 0; + } + if ((deframerSelMask & ADI_FPGA9010_DEFRAMER_1) == ADI_FPGA9010_DEFRAMER_1) + { + recoveryAction = fpga9010_XilinxJesd204cMbLockBfGet(device, FPGA9010_BF_JESD204C_DEFRAMER_1, &mbLockStatusGet); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading Deframer 1 mb lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_XilinxJesd204cSyncHeaderLockBfGet(device, FPGA9010_BF_JESD204C_DEFRAMER_1, &syncHeaderStatusGet); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading Deframer 1 loss sync header lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *status |= (mbLockStatusGet & syncHeaderStatusGet) << 1; + } + if ((deframerSelMask & ADI_FPGA9010_DEFRAMER_2) == ADI_FPGA9010_DEFRAMER_2) + { + recoveryAction = fpga9010_XilinxJesd204cMbLockBfGet(device, FPGA9010_BF_JESD204C_DEFRAMER_2, &mbLockStatusGet); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading Deframer 2 mb lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_XilinxJesd204cSyncHeaderLockBfGet(device, FPGA9010_BF_JESD204C_DEFRAMER_2, &syncHeaderStatusGet); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading Deframer 2 loss sync header lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *status |= (mbLockStatusGet & syncHeaderStatusGet) << 2; + } + + return recoveryAction; +} + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_tdd.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_tdd.c new file mode 100644 index 0000000..07c7512 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/private/src/fpga9010_tdd.c @@ -0,0 +1,155 @@ +/** + * \file: fpga9010_tdd.c + * + * \brief Contains private tdd related functions + * + * FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9010_user.h" +#include "adi_fpga9010.h" +#include "adi_fpga9010_error.h" +#include "../../private/include/fpga9010_tdd.h" +#include "../../private/include/fpga9010_bf_tdd_dp_ctrl.h" +#include "../../private/include/fpga9010_bf_tdd_dp_ctrl_types.h" +#include "../../private/include/fpga9010_bf_tdd_enable_ctrl.h" +#include "../../private/include/fpga9010_bf_tdd_enable_ctrl_types.h" +#include "../../private/include/fpga9010_bf_tdd_frame_cnt.h" +#include "../../private/include/fpga9010_bf_tdd_frame_cnt_types.h" + +int32_t fpga9010_TddEnableControlModuleSet(adi_fpga9010_Device_t *device, adi_fpga9010_TddTiming_t *module, uint32_t baseAddress) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, module); + + if (module->offPtr != module->onPtr) + { + recoveryAction = fpga9010_TddEnableCtrlEnableBfSet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, 0x01); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddEnableCtrlStartValueBfSet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, module->onPtr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddEnableCtrlEndValueBfSet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, module->offPtr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module end bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = fpga9010_TddEnableCtrlEnableBfSet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, 0x00); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddEnableCtrlStartValueBfSet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, 0x00); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddEnableCtrlEndValueBfSet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, 0x00); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module end bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (module->secondaryOffPtr != module->secondaryOnPtr) + { + recoveryAction = fpga9010_TddEnableCtrlSecEnableBfSet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, 0x01); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddEnableCtrlSecStartValueBfSet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, module->secondaryOnPtr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddEnableCtrlSecEndValueBfSet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, module->secondaryOffPtr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module end bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = fpga9010_TddEnableCtrlSecEnableBfSet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, 0x00); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddEnableCtrlSecStartValueBfSet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, 0x00); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddEnableCtrlSecEndValueBfSet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, 0x00); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module end bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = fpga9010_TddEnableCtrlFramesOffsetBfSet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, module->offsetFrames); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddEnableCtrlFramesInactiveBfSet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, module->inactiveFrames); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddEnableCtrlFramesActiveBfSet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, module->activeFrames); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t fpga9010_TddEnableControlModuleGet(adi_fpga9010_Device_t *device, adi_fpga9010_TddTiming_t *module, uint32_t baseAddress) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, module); + + recoveryAction = fpga9010_TddEnableCtrlStartValueBfGet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, &module->onPtr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddEnableCtrlEndValueBfGet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, &module->offPtr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module end bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddEnableCtrlSecStartValueBfGet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, &module->secondaryOnPtr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddEnableCtrlSecEndValueBfGet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, &module->secondaryOffPtr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module end bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + + recoveryAction = fpga9010_TddEnableCtrlFramesOffsetBfGet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, &module->offsetFrames); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddEnableCtrlFramesInactiveBfGet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, &module->inactiveFrames); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddEnableCtrlFramesActiveBfGet(device, (fpga9010_BfTddEnableCtrlChanAddr_e)baseAddress, &module->activeFrames); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010.h new file mode 100644 index 0000000..27dd11f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010.h @@ -0,0 +1,240 @@ +/** +* \file adi_fpga9010.h +* \brief Contains top level fpga9010 related function prototypes for +* adi_fpga9010.c +* +* FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_H_ +#define _ADI_FPGA9010_H_ + +#include "adi_fpga9010_types.h" +#include "adi_fpga9010_error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Performs a Hardware Initialization for FPGA Device. +* +* \pre This function may be called after device->common.devHalInfo has been initialized with +* user values +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to FPGA device data structure +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +*/ +int32_t adi_fpga9010_HwOpen(adi_fpga9010_Device_t *device); + +/** +* \brief Performs a hardware shutdown for FPGA Device. +* +* \pre This function may be called after device->common.devHalInfo has been initialized with +* user values +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to FPGA device data structure +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +*/ +int32_t adi_fpga9010_HwClose(adi_fpga9010_Device_t *device); + +/** +* \brief Reads the Major, Minor, & Design ID bitfields and stores these values +* in the device->devStateInfo structure. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_VersionRead(adi_fpga9010_Device_t *device); + +/** +* \brief Unimplemented. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param detectedRefClock_kHz FPGA high speed serial reference clock frequency returned in this parameter in kHz. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RefClockFreqRead(adi_fpga9010_Device_t *device, uint32_t *detectedRefClock_kHz); + +/** +* \brief Unimplemented. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RegisterReset(adi_fpga9010_Device_t *device); + +/** +* \brief Unimplemented. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param IpToReset is a bit mask comprised of fpgaIpBlockResets_t enum types which select the FPGA IP blocks +* to be reset +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_IpReset(adi_fpga9010_Device_t *device, uint32_t IpToReset); + +/** +* \brief Dynamic Reconfiguration Port (DRP) read helper function. After a successful +* DRP read the rdMask value is applied to the register address value and the value +* written to the address pointed to by rdWord. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param addr is a uint32_t DRP address word +* \param drp selects the DRP interface to read from based on the adi_fpga_DrpInterface_e enum type +* \param rdWord is uint32_t pointer to the register read value +* \param rdMask is applied to the word read from the DRP register +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_DrpRead(adi_fpga9010_Device_t *device, adi_fpga9010_DrpAddress_e addr, uint8_t drp, uint16_t *rdWord, adi_fpga9010_DrpMask_e rdMask); + +/** +* \brief Dynamic Reconfiguration Port (DRP) write helper function. The addr, wrWord, and wrMask are written to the +* appropriate DRP bitfields based on the drp parameter. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param addr is a uint32_t DRP address word +* \param drp selects the DRP interface to write to based on the adi_fpga_DrpInterface_e enum type +* \param wrWord is a uint32_t register write value +* \param wrMask is written to a DRP configuration register and is applied internally +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_DrpWrite(adi_fpga9010_Device_t *device, adi_fpga9010_DrpAddress_e addr, uint8_t drp, uint16_t wrWord, adi_fpga9010_DrpMask_e wrMask); + +/** +* \brief Initializes the FPGA based on the settings in initSettings. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param initSettings initialisation settings for fpga. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_InitSet(adi_fpga9010_Device_t *device, adi_fpga9010_Init_t *initSettings); + +/** +* \brief Populates the initSettings structure based on the values read back from the FPGA. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param initsettings initialisation settings for fpga. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_InitGet(adi_fpga9010_Device_t *device, adi_fpga9010_Init_t *initsettings); + + +/** +* \brief Initializes the FPGA9010 device based on the desired device settings. +* +* This function initializes the ADRV9010 device, digital clocks, JESD204b settings . +* It leaves the FPGA9010 in a state ready to run +* +* \pre This function is the very first API to be called by the user to configure the FPGA9010 +* after all dependent data structures have been initialized +* +* \dep_begin +* \dep{device (all members)} +* \dep{init (all members)} +* \dep_end +* +* \param device Pointer to FPGA9010 device data structure +* \param fpgaInit Pointer to FPGA9010 initialization settings structures +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +*/ +int32_t adi_fpga9010_Initialize(adi_fpga9010_Device_t *device, adi_fpga9010_Init_t *fpgaInit); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_axi_adv_spi.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_axi_adv_spi.h new file mode 100644 index 0000000..9751aff --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_axi_adv_spi.h @@ -0,0 +1,35 @@ +/** +* \file adi_fpga9010_axi_adv_spi.h +* \brief Contains top level fpga9010 related function prototypes for +* adi_fpga9010.c +* +* FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_axi_adv_spi_H_ +#define _ADI_FPGA9010_axi_adv_spi_H_ + +#include "adi_fpga9010_axi_adv_spi_types.h" +#include +#include "adi_fpga9010.h" +//#include "adi_common_macros.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +int32_t adi_fpga9010_AxiAdvSpiCfgSet(adi_fpga9010_Device_t *device, adi_fpga9010_AxiAdvSpiFeatConfig_t *advSpiCfg, uint8_t slaveSelect); +int32_t adi_fpga9010_AxiAdvSpiChipSelectAll(adi_fpga9010_Device_t *device, uint8_t enable); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_axi_adv_spi_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_axi_adv_spi_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_axi_adv_spi_types.h new file mode 100644 index 0000000..f9050b8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_axi_adv_spi_types.h @@ -0,0 +1,135 @@ +/** +* \file adi_fpga9010.h +* \brief Contains top level fpga9010 related function prototypes for +* adi_fpga9010.c +* +* FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_AXI_ADV_SPI_TYPES_H_ +#define _ADI_FPGA9010_AXI_ADV_SPI_TYPES_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + typedef struct adi_fpga9010_AxiAdvSpiVersion + { + uint8_t module_version_major; /*!< Global Interrupt Enable. Allows passing all individually enabled interrupts to the interrupt controller. When set to: 0 = Disabled. 1 = Enabled.*/ + uint16_t module_version_minor; /*!< Global Interrupt Enable. Allows passing all individually enabled interrupts to the interrupt controller. When set to: 0 = Disabled. 1 = Enabled.*/ + } adi_fpga9010_AxiAdvSpiVersion_t; + +// typedef struct adi_fpga9010_AxiAdvSpiDgier +// { +// uint8_t gie; /*!< Global Interrupt Enable. Allows passing all individually enabled interrupts to the interrupt controller. When set to: 0 = Disabled. 1 = Enabled.*/ +// } adi_fpga9010_AxiAdvSpiDgier_t; + + + typedef struct adi_fpga9010_AxiAdvSpiIpisr + { + uint8_t tx_fifo_half_empty; /*!< Transmit FIFO Half Empty.*/ + uint8_t drr_overrun; /*!< Data Receive Register/FIFO Overrun.*/ + uint8_t drr_full; /*!< Data Receive Register/FIFO Full.*/ + uint8_t dtr_empty; /*!< Data Transmit Register/FIFO Empty. */ + uint8_t modf; /*!< Mode Fault Error. */ + } adi_fpga9010_AxiAdvSpiIpisr_t; + + typedef struct adi_fpga9010_AxiAdvSpiIpier + { + uint8_t tx_fifo_half_empty_ien; /*!< Transmit FIFO Half Empty IRQ Enable. 0 = Disabled. 1 = Enabled..*/ + uint8_t drr_overrun; /*!< Data Receive Register/FIFO Overrun IRQ Enable. 0 = Disabled. 1 = Enabled.*/ + uint8_t drr_full; /*!< Data Receive Register/FIFO Full IRQ Enable. 0 = Disabled. 1 = Enabled.*/ + uint8_t dtr_empty_ien; /*!< Data Transmit Register/FIFO Empty IRQ Enable. 0 = Disabled. 1 = Enabled. */ + uint8_t modf_ien; /*!< Mode Fault Error IRQ Enable. 0 = Disabled. 1 = Enabled. */ + } adi_fpga9010_AxiAdvSpiIpier_t; + + + + /** + * \brief Data structure to hold SPI settings for all system device types + */ + typedef struct adi_fpga9010_AxiAdvSpiSpicr + { + uint8_t lsbFirst; /*!< 1 = MSB First, 0 = LSB First Bit order for SPI transaction. Default = 0 (msbFirst*/ + uint8_t mstr_inhibit; /*!< This bit inhibits master transactions. This bit has no effect on slave operation. Default = 1 (Disabled)*/ + uint8_t man_ss_en; /*!< Manual Slave Select Assertion Enable. Default = 1 (Disabled)*/ + uint8_t rx_fifo_reset; /*!< RX FIFO Reset. When written to 1, this bit forces a reset of the receive FIFO to the empty condition. Default = 0 (Disabled)*/ + uint8_t tx_fifo_reset; /*!< TX FIFO Reset. When written to 1, this bit forces a reset of the transmit FIFO to the empty condition. Default = 0 (Disabled)*/ + uint8_t cpha; /*!< Clock Phase. Setting this bit defines the default clock phase. */ + uint8_t cpol; /*!< Clock Polarity. When set to: 0 = Active-High clock; SCK idles Low. 1 = Active-Low clock; SCK idles High. */ + uint8_t master; /*!< Master Mode Select. When set to: 0 = Active-High clock; SCK idles Low. 1 = Active-Low clock; SCK idles High. */ + uint8_t spe; /*!< 1= SPI System Enable. */ + uint8_t loop; /*!< 0= Normal Operation; 1=The transmitter output is internally connected to the receiver input */ + } adi_fpga9010_AxiAdvSpiSpicr_t; + +/** + * \brief Data structure to hold SPI settings for all system device types + */ + typedef struct adi_fpga9010_AxiAdvSpiSpisr + { + uint8_t modf_flag; /*!< Mode Fault Error Flag.*/ + uint8_t tx_full; /*!< Transmit Full Flag. This bit is set high when the transmit FIFO is full.*/ + uint8_t tx_empty; /*!< Transmit Empty Flag. This bit is set high when the transmit FIFO is empty.*/ + uint8_t rx_full; /*!< Receive Full Flag. This bit is set high when the receive FIFO is full.*/ + uint8_t rx_empty; /*!< Receive Empty Flag. This bit is set high when the receive FIFO is empty.*/ + } adi_fpga9010_AxiAdvSpiSpisr_t; + + typedef struct adi_fpga9010_AxiAdvSpiFeatConfig + { + uint16_t clockDiv; /*!< Advanced Feature Set Clock Divider.*/ + uint8_t threeWireTriPoint; /*!< Advanced Feature Set Three Wire Tristate Point.*/ + uint8_t misoSampleSlip; /*!< Advanced Feature Set MISO Sample Slip.*/ + uint8_t fourWire; /*!< Advanced Feature Set Four Wire Mode.*/ + uint8_t lsbFirst; /*!< Advanced Feature Set LSB First.*/ + uint8_t cpha; /*!< Advanced Feature Set Clock Phase.*/ + uint8_t cpol; /*!< Advanced Feature Set Clock Polarity.*/ + uint8_t enable; /*!< Advanced Feature Set Enable.*/ + } adi_fpga9010_AxiAdvSpiFeatConfig_t; + + + +// typedef struct adi_fpga9010_AxiAdvSpiSpidtr +// { +// uint8_t tx_data; /*!< Transmit Data. Data to be pushed into the TX Data FIFO.*/ +// } adi_fpga9010_AxiAdvSpiSpidtr_t; + +// typedef struct adi_fpga9010_AxiAdvSpiSpidrr +// { +// uint8_t rx_data; /*!< Transmit Data. Data to be pushed into the TX Data FIFO.*/ +// } adi_fpga9010_AxiAdvSpiSpidrr_t; + + +// typedef struct adi_fpga9010_AxiAdvSpiSpissr +// { +// uint32_t slave_select; /*!< Slave Select. Active-Low, one-hot encoded slave select vector.*/ +// } adi_fpga9010_AxiAdvSpiSpissr_t; + +// typedef struct adi_fpga9010_AxiAdvSpiTxFIFOocy +// { +// uint8_t tx_fifo_occupancy; /*!< Transmit FIFO Occupancy. This field indicates the number of elements that are currently in the transmit FIFO..*/ +// } adi_fpga9010_AxiAdvSpiTxFIFOocy_t; + + typedef struct adi_fpga9010_axiAdvSpiSettings + { + adi_fpga9010_AxiAdvSpiVersion_t spiModVersion; /*!< axi_adv_spi module version */ + adi_fpga9010_AxiAdvSpiIpisr_t spiIntStatus; /*!< The IP Interrupt Status Register */ + adi_fpga9010_AxiAdvSpiIpier_t spiIntEnable; /*!< Interrupt Enable Register */ + adi_fpga9010_AxiAdvSpiSpicr_t spiCtrlRegSettings; /*!< SPI settings data structure */ + adi_fpga9010_AxiAdvSpiSpisr_t SpiStatus; /*!< Holds settings for CLKPLL and reference clock */ + adi_fpga9010_AxiAdvSpiFeatConfig_t advFeatSS[32]; /*!< Advanced Feature Configuration Register for Slave Select 0-31. */ + } adi_fpga9010_axiAdvSpiSettings_t; + + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_AXI_ADV_SPI_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_clk.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_clk.h new file mode 100644 index 0000000..60357c9 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_clk.h @@ -0,0 +1,186 @@ +/** + * \file: adi_fpga9010_jesd.h + * + * \brief Contains top level tx fpga9010 related prototypes + * + * FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_CLK_H_ +#define _ADI_FPGA9010_CLK_H_ + +#include +#include "adi_fpga9010_types.h" +#include "adi_fpga9010_clk_types.h" + +#ifdef __cplusplus +extern "C" { +#endif +/** +* \brief writes the configuration to the FPGA MMCM via the Dynamic Reconfiguration Port (DRP) +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param mmcmSel selection of the mmcm device to config +* \param mmcm is a adi_fpga_MmcmCfg_t used to configure the mmcm +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_MmcmSet(adi_fpga9010_Device_t *device, adi_fpga9010_MmcmSel_e mmcmSel, adi_fpga9010_MmcmCfg_t *mmcm); + +/** +* \brief reads the configuration to the FPGA MMCM clock tile via the Dynamic Reconfiguration Port (DRP) +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param mmcmSel selection of the mmcm device to config +* \param mmcm is a adi_fpga_MmcmCfg_t used to configure the mmcm +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_MmcmGet(adi_fpga9010_Device_t *device, adi_fpga9010_MmcmSel_e mmcmSel, adi_fpga9010_MmcmCfg_t *mmcm); + +/** +* \brief Returns the value of the MMCM lock bit +* +* \dep_begin +* \dep{device} +* \dep{mmcm} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param mmcmSel selection of the mmcm device to config, rx or tx +* \param lockBit Pointer to return lock bit value +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_MmcmLockGet(adi_fpga9010_Device_t *device, adi_fpga9010_MmcmSel_e mmcmSel, uint8_t *lockBit); + +/** +* \brief Peforms a soft reset on the selected MMCM. The reset is self-clearing. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param mmcmSel selection of the mmcm device to config +* \param mmcm is a adi_fpga_MmcmCfg_t used to configure the mmcm +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_MmcmResetSet(adi_fpga9010_Device_t *device, adi_fpga9010_MmcmSel_e mmcmSel); + +/** +* \brief writes the configuration to the FPGA QPLL via the Dynamic Reconfiguration Port (DRP) +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param quadMask selection of the Qpll device to config +* \param qPll is a adi_fpga9010_QpllCfg_t used to configure the Qpll +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_QpllSet(adi_fpga9010_Device_t *device, uint8_t quadMask, adi_fpga9010_QpllCfg_t *qPll); + +/** +* \brief reads the configuration to the FPGA QPLL via the Dynamic Reconfiguration Port (DRP) +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param quadSel one of adi_fpga9010_QPLL_Quad_e enum values +* \param bandSel one of adi_fpga9010_LaneClkSel_e enum values +* \param qPll is a adi_fpga9010_QpllCfg_t used to configure the Qpll +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_QpllGet(adi_fpga9010_Device_t *device, adi_fpga9010_Qpll_Quad_e quadSel, adi_fpga9010_LaneClkSel_e bandSel, adi_fpga9010_QpllCfg_t *qPll); + + + +/** +* \brief Returns the valueo of the QPLL lock bit pointed to by the quadMask and bandSel +* +* \dep_begin +* \dep{device} +* \dep{qPll->band} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param quadSel selecting either 0 for quad 0 or 1 for quad 1 +* \param bandSel selecting either 0 for qpll0 or 1 for qpll1 +* \param lockBit will be set with the lock bit bitfield value, either 0 or 1 +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_QpllLockGet(adi_fpga9010_Device_t *device, uint8_t quadSel, uint8_t bandSel, uint8_t *lockBit); + +/** +* \brief Reads the power good bit for each lane +* +* This function will return a mask indicating the status of each channel's power good bit +* +* Dependencies +* - device->common.devHalInfo +* +* \param device is structure pointer to AD9528 clock device structure +* \param quadSel 0 for quad 0; 1 for quad 1 +* \param powerGood status an 8-bit mask of each channels power good bit, bit 7 = channel 7's power good, etc. +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +*/ +int32_t adi_fpga9010_LanePowerGoodGet(adi_fpga9010_Device_t *device, uint8_t quadSel, uint8_t *powerGood); //todo: move this to jesd.h + + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_CLK_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_clk_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_clk_types.h new file mode 100644 index 0000000..f1afc9c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_clk_types.h @@ -0,0 +1,82 @@ +/*! +* \file adi_fpga9010_types.h +* \brief Contains ADRV9010 API configuration and run-time type definitions +* +* ADRV9010 API Version: $ADI_FPGA9010_API_VERSION$ +* +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_CLK_TYPES_H_ +#define _ADI_FPGA9010_CLK_TYPES_H_ + +#include + +#define ADI_FPGA9010_NUM_MMCM_OUTPUT_CLOCKS 7 +#define ADI_FPGA9010_PHY_NUM_CHANNELS 8 + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum adi_fpga9010_Qpll_Band +{ + ADI_FPGA9010_QPLL_BAND0 = 0x0, + ADI_FPGA9010_QPLL_BAND1 = 0x1 +} adi_fpga9010_Qpll_Band_e; + + +typedef enum adi_fpga9010_QpllClkSel +{ + ADI_FPGA9010_QPLL_GTREFCLK0 = 0x1, + ADI_FPGA9010_QPLL_GTREFCLK1 = 0x2, + ADI_FPGA9010_QPLL_GTNORTHREFCLK0 = 0x3, + ADI_FPGA9010_QPLL_GTNORTHREFCLK1 = 0x4, + ADI_FPGA9010_QPLL_GTSOUTHREFCLK0 = 0x5, + ADI_FPGA9010_QPLL_GTSOUTHREFCLK1 = 0x6, + ADI_FPGA9010_QPLL_GTGREFCLK = 0x7 + +} adi_fpga9010_QpllClkSel_e; + + +typedef enum adi_fpga9010_MmcmSel +{ + ADI_FPGA9010_CORE_MMCM +} adi_fpga9010_MmcmSel_e; + +typedef struct adi_fpga9010_QpllCfg +{ + uint8_t quadSelect; /*! Apply these settings to the selected quads (0x3 for both; 0x2 for quad 1; 0x1 for quad 0) */ + adi_fpga9010_LaneClkSel_e band; /*! GTX QPLL upper or lower band VCO select, */ + adi_fpga9010_QpllClkSel_e refClkSelect[2]; /*! GTX QPLL Ref Clk select */ + uint16_t mVal; /*! reference clock divisor value, */ + uint16_t nVal; /*! loop divisor value, */ + uint32_t qpllVco_kHz; /*! GTX QPLL upper or lower band VCO select, */ + uint16_t lpf; /*! Value determined by FPGA reference clock & lane rate */ + uint16_t cfg4; /*! Value determined by FPGA reference clock & lane rate */ + uint16_t cp; /*! Value determined by FPGA reference clock & lane rate */ + uint16_t lockCfg; /*! Value determined by FPGA reference clock & lane rate */ + uint16_t lockCfgG3; /*! Value determined by FPGA reference clock & lane rate */ +} adi_fpga9010_QpllCfg_t; + + +typedef struct adi_fpga9010_MmcmCfg +{ + uint8_t mVal; + uint8_t dVal; + uint8_t outputClkDiv[7]; + uint32_t outputClkFreq_kHz[7]; +} adi_fpga9010_MmcmCfg_t; + + + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_CLK_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_error.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_error.h new file mode 100644 index 0000000..65adde6 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_error.h @@ -0,0 +1,50 @@ +/** +* \file adi_fpga9010_error.h +* \brief AD9528 ERROR header file +* +* Extension of adi_common_error +* +* API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADI API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_FPGA9010_ERROR_H_ +#define _ADI_FPGA9010_ERROR_H_ + +#include "adi_common_error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Extending Common error for FPGA9010 */ +#define ADI_FPGA9010_ERR_INV_NULL_INIT_PARAM 0x3001 +#define ADI_FPGA9010_ERR_DRP_ERROR 0x3002 +#define ADI_FPGA9010_ERR_CHANNEL_POWER_GOOD_FAILURE 0x3003 +#define ADI_FPGA9010_ERR_API_FAIL 0x3004 +#define ADI_FPGA9010_ERR_NUMBER_OF_ERRORS 0x3005 +#define ADI_FPGA9010_ERR_REGISTER_IO_FAIL 0x3006 +#define ADI_FPGA9010_ERR_DATA_RX_MOVER_WAIT_TIMEOUT 0x3007 /*!< API NG - Timeout occurred during Rx transaction */ +#define ADI_FPGA9010_ERR_LINK_LAYER_RESET_FAIL 0x3008 +#define ADI_FPGA9010_ERR_INVALID_FPGA_IMAGE 0x3009 + +/* Extending Common Actions for FPGA9010 */ +#define ADI_FPGA9010_ACT_WARN_RESET_GPIO (3) /*!< API OK - GPIO Not working */ +#define ADI_FPGA9010_ACT_ERR_FLUSH_CACHE (15) /*!< API NG - Bitfield CACHE requires flushing */ +#define ADI_FPGA9010_ACT_ERR_NULL_POINTER (16) /*!< API NG - Null pointer has been detected */ +#define ADI_FPGA9010_ACT_INV_TX_DATA_MOVER_TRIGGER (17) /*!< API NG - An invalid tx data mover trigger selected */ +#define ADI_FPGA9010_ACT_INV_TDD_ASSERT_SELECT (18) /*!< API NG - Invalid bits were selected when asserting TDD pins */ +#define ADI_FPGA9010_ACT_INV_RX_DATA_MOVER_SETUP (19) /*!< API NG - An invalid rx move type selected */ +#define ADI_FPGA9010_ACT_INV_RX_DATA_MOVER_TRIGGER (20) /*!< API NG - An invalid rx data mover trigger selected */ +#define ADI_FPGA9010_ACT_INV_RX_DATA_MOVER_ENABLE (21) /*!< API NG - An invalid rx data mover trigger selected */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_ERROR_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_gpio.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_gpio.h new file mode 100644 index 0000000..c7d21ad --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_gpio.h @@ -0,0 +1,213 @@ +/** +* \file adi_fpga9010_gpio.h +* \brief Contains top level fpga9010 related function prototypes for +* adi_fpga9010_gpio.c +* +* FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ +*/ +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_GPIO_H_ +#define _ADI_FPGA9010_GPIO_H_ + +#include "adi_fpga9010_gpio_types.h" +#include "adi_fpga9010_tdd_types.h" +#include "adi_fpga9010.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** +* \brief Writes the values to the GPIO output register. +* +* This function will write contents of wrData to the the GPIO output register +* +* \param device Pointer to the FPGA9010 data structure +* \param wrData The user provided variable containing the output register values. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9010_GpioWrite(adi_fpga9010_Device_t *device, uint32_t wrData); + +/** +* \brief reads the values on the GPIO input register. +* +* This function will read the GPIO input register and put the value into the +* the user provided rdData variable. +* +* \param device Pointer to the FPGA9010 data structure +* \param rdData The user provided variable containing the input register values. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9010_GpioRead(adi_fpga9010_Device_t *device, uint32_t *rdData); + +/** +* \brief Sets the gpioMode. +* +* This function will set the Gpio Mode. +* Valid Modes are +* gpioMode[2:0] | GPIO direction +* ----------------|------------------- +* 000 | normal +* 001 | Jtag +* 010 | spi2 +* +* \param device Pointer to the FPGA9010 data structure +* \param gpioMode The user provided variable containing the mode to set. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9010_GpioModeSet(adi_fpga9010_Device_t *device, adi_fpga9010_GpioModes_e gpioMode); + +/** +* \brief Gets the gpioMode. +* +* This function will read the Gpio Mode. +* Valid Modes are +* gpioMode[2:0] | GPIO direction +* ----------------|------------------- +* 000 | normal +* 001 | Jtag +* 010 | spi2 +* +* \param device Pointer to the FPGA9010 data structure +* \param gpioMode The user provided variable into which the mode value will be written. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9010_GpioModeGet(adi_fpga9010_Device_t *device, adi_fpga9010_GpioModes_e *gpioMode); + +/** +* \brief Sets the gpio input direction pins. +* +* This function will mask all other gpio bits and only set the bits that are high +* in the pinSelMask variable. +* +* \param device Pointer to the FPGA9010 data structure +* \param pinSelMask The user provided variable containing the mapping of bits +* to be set as input pins. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9010_GpioInputDirSet(adi_fpga9010_Device_t *device, uint32_t pinSelMask); + +/** +* \brief Gets the gpio input direction pins. +* +* \param device Pointer to the FPGA9010 data structure +* \param pinSelMask The user provided variable which will contain the mapping of bits +* set as Input pins, a high means the pin is an input. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9010_GpioInputDirGet(adi_fpga9010_Device_t *device, uint32_t *pinDirMask); + +/** +* \brief Sets the gpio output directction pins. +* +* This function will mask all other gpio bits and and only set the bits that are high +* in the pinSelMask variable. +* +* \param device Pointer to the FPGA9010 data structure +* \param pinSelMask The user provided variable containing the mapping of bits +* to be set as Output pins . +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ + int32_t adi_fpga9010_GpioOutputDirSet(adi_fpga9010_Device_t *device, uint32_t pinDirMask); + +/** +* \brief Gets the gpio output directction pins. +* +* \param device Pointer to the FPGA9010 data structure +* \param pinSelMask The user provided variable which will contain the mapping of bits +* set as Output pins, a high means the pin is an Output. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9010_GpioOutputDirGet(adi_fpga9010_Device_t *device, uint32_t *pinDirMask); + +/** +* \brief Gets the output Enable register. +* similar functionality to adi_fpga9010_GpioInputDirGet but with a different signiture +* +* This function will get gpio output enable register value +* +* \param pinSelMask The user provided variable containing the input/output mapping of bits. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9010_GpioOeGet(adi_fpga9010_Device_t *device, uint32_t *pinSelMask); + +/** +* \brief Sets the output Enable register. +* similar functionality to adi_fpga9010_GpioInputDirSet but with a different signiture +* +* This function will set gpio pins to either input or output depending on the gpioPinType variable. +* the pinSelMask is used to mask all other gpio bits and +* only set the bits that are high in the pinSelMask. +* +* \param device Pointer to the FPGA9010 data structure +* \param gpioPinType The variable containing the direction in which to set the pins. +* \param pinSelMask The user provided variable containing the mapping of bits to set. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9010_GpioOeSet(adi_fpga9010_Device_t *device, adi_fpga9010_GpioPinType_e gpioPinType, uint32_t pinSelMask); + +/** +* \brief Maps the selected TDD module enable signal to the selected GPIO pin. +* +* \param device Pointer to the FPGA9010 data structure +* \param tddModuleSel The selected TDD module. +* \param gpioSel Which GPIO the tddModuleSel enable signal will be routed to. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9010_TddGpioSet(adi_fpga9010_Device_t *device, adi_fpga9010_TddModule_e tddModuleSel, adi_fpga9010_GpioPinSel_e gpioSel); + +/** +* \brief Returns which GPIO is mapped to the selected TDD module. +* +* \param device Pointer to the FPGA9010 data structure +* \param tddModuleSel The selected TDD module. +* \param gpioSel A pointer to adi_fpga9010_GpioPinSel_e that will hold the GPIO for the selected TDD module. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9010_TddGpioGet(adi_fpga9010_Device_t *device, adi_fpga9010_TddModule_e tddModuleSel, adi_fpga9010_GpioPinSel_e *gpioSel); + +/** +* \brief Clears all TDD GPIO settings. +* +* \param device Pointer to the FPGA9010 data structure +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9010_TddGpioAllClear(adi_fpga9010_Device_t *device); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_GPIO_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_gpio_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_gpio_types.h new file mode 100644 index 0000000..afe499a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_gpio_types.h @@ -0,0 +1,72 @@ +/*! +* \file adi_adrv9010_gpio_types.h +* \brief Contains FPGA9010 GPIO enum and struct definitions +* +* ADRV9010 API Version: $ADI_FPGA9010_API_VERSION$ +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + + +#ifndef _ADI_FPGA9010_GPIO_TYPES_H_ +#define _ADI_FPGA9010_GPIO_TYPES_H_ + + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADI_FPGA9010_GPIO_PINS 19 +#define ADI_FPGA9010_GPIO_MAX_VALUE 0x7FFFF + +typedef enum adi_fpga9010_GpioModes +{ + ADI_FPGA9010_GPIO_MODE_NONE = 0x0, + ADI_FPGA9010_GPIO_MODE_JTAG, + ADI_FPGA9010_GPIO_MODE_SPI2, + ADI_FPGA9010_GPIO_MODE_TDD +} adi_fpga9010_GpioModes_e; + +typedef enum adi_fpga9010_GpioPinType +{ + ADI_FPGA9010_GPIO_PIN_OUTPUT = 0x0, + ADI_FPGA9010_GPIO_PIN_INPUT = 0x1 +} adi_fpga9010_GpioPinType_e; + +typedef enum adi_fpga9010_GpioPinSel +{ + ADI_FPGA9010_GPIO_00 = 0, /*!< Select GPIO_00*/ + ADI_FPGA9010_GPIO_01, /*!< Select GPIO_01*/ + ADI_FPGA9010_GPIO_02, /*!< Select GPIO_02*/ + ADI_FPGA9010_GPIO_03, /*!< Select GPIO_03*/ + ADI_FPGA9010_GPIO_04, /*!< Select GPIO_04*/ + ADI_FPGA9010_GPIO_05, /*!< Select GPIO_05*/ + ADI_FPGA9010_GPIO_06, /*!< Select GPIO_06*/ + ADI_FPGA9010_GPIO_07, /*!< Select GPIO_07*/ + ADI_FPGA9010_GPIO_08, /*!< Select GPIO_08*/ + ADI_FPGA9010_GPIO_09, /*!< Select GPIO_09*/ + ADI_FPGA9010_GPIO_10, /*!< Select GPIO_10*/ + ADI_FPGA9010_GPIO_11, /*!< Select GPIO_11*/ + ADI_FPGA9010_GPIO_12, /*!< Select GPIO_12*/ + ADI_FPGA9010_GPIO_13, /*!< Select GPIO_13*/ + ADI_FPGA9010_GPIO_14, /*!< Select GPIO_14*/ + ADI_FPGA9010_GPIO_15, /*!< Select GPIO_15*/ + ADI_FPGA9010_GPIO_16, /*!< Select GPIO_16*/ + ADI_FPGA9010_GPIO_17, /*!< Select GPIO_17*/ + ADI_FPGA9010_GPIO_18, /*!< Select GPIO_18*/ + ADI_FPGA9010_GPIO_INVALID /*!< Invalid GPIO*/ + +} adi_fpga9010_GpioPinSel_e; + + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_GPIO_TYPES_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_hal.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_hal.h new file mode 100644 index 0000000..a4bbf45 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_hal.h @@ -0,0 +1,143 @@ +/** +* \file adi_fpga9010_hal.h +* \brief Contains ADI Transceiver Hardware Abstraction functions +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ +#ifndef _ADI_FPGA9010_HAL_H_ +#define _ADI_FPGA9010_HAL_H_ + +#include +#include +#include "adi_fpga9010_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Performs a read of a single 32-bit register +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param addr Address of the register to be read. Must be on a word boundary +* \param data Pointer where the register value will be assigned +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RegisterRead(adi_fpga9010_Device_t *device, uint32_t addr, uint32_t *data); + +/** +* \brief Performs a write of a single 32-bit register +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param addr Address of the register to be written. Must be on a word boundary +* \param data The data to write +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RegisterWrite(adi_fpga9010_Device_t *device, uint32_t addr, uint32_t data); + +/** +* \brief Performs bit field read +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param addr Address of the register where the field resides +* \param fieldVal A pointer to store the value in the field +* \param mask A bit-wise mask that determines which bits are part of the field +* \param startBit The bit location in the addr where the field starts +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RegisterFieldRead(adi_fpga9010_Device_t *device, const uint32_t addr, uint32_t *fieldVal, uint32_t mask, uint8_t startBit); + +/** +* \brief Performs bit field write +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param addr Address of the register where the field resides +* \param fieldVal The value to write to the field +* \param mask A bit-wise mask that determines which bits are part of the field +* \param startBit The bit location in the addr where the field starts +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RegisterFieldWrite(adi_fpga9010_Device_t *device, const uint32_t addr, uint32_t fieldVal, uint32_t mask, uint8_t startBit); + +/** +* \brief Performs a RAM memory read +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param ramAddress Address to begin the read from +* \param data An array to hold the values read back from RAM. Must have enough space to store 'length' elements +* \param length The number of words to read starting from ramAddress +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RamRead(adi_fpga9010_Device_t *device, const uint32_t ramAddress, uint32_t data[], uint32_t length); + +/** +* \brief Performs a RAM memory write +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param ramAddress Address to begin writing to +* \param data An array that holds the values to write to RAM +* \param length The number of words to write starting at ramAddress +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RamWrite(adi_fpga9010_Device_t *device, const uint32_t ramAddress, uint32_t data[], uint32_t length); + + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_HAL_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_jesd.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_jesd.h new file mode 100644 index 0000000..3103944 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_jesd.h @@ -0,0 +1,730 @@ +/** + * \file: adi_fpga9010_jesd.h + * + * \brief Contains top level tx fpga9010 related prototypes + * + * FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_JESD_H_ +#define _ADI_FPGA9010_JESD_H_ + +#include "adi_fpga9010_types.h" +#include "adi_fpga9010_jesd_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t adi_fpga9010_SerializerCfgSet(adi_fpga9010_Device_t *device, uint8_t laneSelMask, adi_fpga9010_SerializerCfg_t *serializerCfg); + +/** +* \brief reads the configuration to one or more FPGA JESD204B Serializer +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param laneSel an adi_fpga9010_LaneSel_e enum value +* \param serializerCfg contains the serializer configuration setting +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_SerializerCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_LaneSel_e laneSel, adi_fpga9010_SerializerCfg_t *serializerCfg); + +/** +* \brief Sets the reset bit for both rx & tx channel in the selected lanes +* Used as part of PHY bring up +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param laneSelMask an adi_fpga9010_LaneSel_e enum value +* \param resetVal either 0 or 1. Value to be written to the reset bit (1 to reset; 0 to release reset) +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_SerializerResetSet(adi_fpga9010_Device_t *device, uint8_t laneSelMask, uint8_t resetVal); + +/** +* \brief Returns the tx reset done for all eight PHY lanes +* Note: channels must have stable clock input for Reset Done to be set +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txResetDone pointer that will be assigned each lanes tx reset done bit +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_SerializerResetDoneGet(adi_fpga9010_Device_t *device, uint8_t *txResetDone); + +/** +* \brief Sets the lane cpll power down bit +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param laneSelMask mask to select which channels to apply pdVal +* \param pdVal either 0 or 1. Value to be written to the cpll power down bit (1 to reset; 0 to release reset) +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_LaneCpllPdSet(adi_fpga9010_Device_t *device, uint8_t laneSelMask, uint8_t pdVal); + +/** +* \brief writes the configuration of one or more FPGA JESD204B Deserializers +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param laneSelMask an or'd combination of one or more adi_fpga9010_LaneSel_e enum values +* \param deserializerCfg contains the deserializer configuration setting +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_DeserializerCfgSet(adi_fpga9010_Device_t *device, uint8_t laneSelMask, adi_fpga9010_DeserializerCfg_t *deserializerCfg); + +/** +* \brief reads the configuration to one or more FPGA JESD204B Deserializer +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param laneSel an adi_fpga9010_LaneSel_e enum value +* \param deserializerCfg contains the deserializer configuration setting +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_DeserializerCfgGet(adi_fpga9010_Device_t *device, const adi_fpga9010_LaneSel_e laneSel, adi_fpga9010_DeserializerCfg_t *deserializerCfg); + +/** +* \brief Sets the reset bit for both rx channel in the selected lanes +* Used as part of PHY bring up +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param laneSelMask an adi_fpga9010_LaneSel_e enum value +* \param resetVal either 0 or 1. Value to be written to the reset bit (1 to reset; 0 to release reset) +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_DeserializerResetSet(adi_fpga9010_Device_t *device, uint8_t laneSelMask, uint8_t resetVal); + +/** +* \brief Returns the rx reset done for all eight lanes +* Note: channels must have stable clock input for Reset Done to be set +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxResetDone pointer that will be assigned each lanes rx reset done bit +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_DeserializerResetDoneGet(adi_fpga9010_Device_t *device, uint8_t *rxResetDone); + +/** +* \brief This function writes the adi_fpga9010_DeframerCfg_t structure to the framer modules + * selected in the deframerSelMask, where the bit location corresponds to the rx link number. + * This function is used in the link bringup sequence just prior to reset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param deframerCfg contains the deserializer configuration setting +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ + int32_t adi_fpga9010_DeframerCfgSet(adi_fpga9010_Device_t *device, uint32_t deframerSelMask, adi_fpga9010_DeframerCfg_t *deframerCfg); + + /** + * \brief Reads the configuration for a single deframer module and populates the empty adi_fpga9010_DeframerCfg_t + * structure pointed to by deframerCfg. + * + * \dep_begin + * \dep{device} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param deframerSel an adi_fpga9010_LinkSel_e enum value + * \param deframerCfg contains the deframer configuration setting + * + * \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + * + */ + int32_t adi_fpga9010_DeframerCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e deframerSel, adi_fpga9010_DeframerCfg_t *deframerCfg); + + /** + * \brief Unimplemented + * + * \dep_begin + * \dep{device} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param deframerSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values + * \param resetBits the reset bits of the selected deframers will correspond with their adi_fpga9010_DeframerSel_e bit locations + * + * \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + * + */ + int32_t adi_fpga9010_DeframerResetGet(adi_fpga9010_Device_t *device, uint32_t deframerSelMask, uint8_t *resetBits); + + /** + * \brief This function writes the adi_fpga9010_FramerCfg_t structure to the framer modules + * selected in the framerSelMask, where the bit location corresponds to the tx link number. + * This function is used in the link bringup sequence just prior to reset. + * + * \dep_begin + * \dep{device} + * \dep_end + * + * \param device Pointer to the FPGA9010 device data structure. + * \param framerSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values + * \param framerCfg contains the deserializer configuration setting + * + * \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + * + */ +int32_t adi_fpga9010_FramerCfgSet(adi_fpga9010_Device_t *device, uint8_t framerSelMask, adi_fpga9010_FramerCfg_t *framerCfg); + +/** +* \brief Reads the configuration for a single framer module and populates the empty adi_fpga9010_FramerCfg_t +* structure pointed to by framerCfg. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSel an adi_fpga9010_FramerSel_e enum value selecting a single framer +* \param framerCfg pointer to an empty adi_fpga9010_FramerCfg_t structure +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_FramerCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e framerSel, adi_fpga9010_FramerCfg_t *framerCfg); + +/** +* \brief Reads the reset bit for the selected framers in framerSelMask and sets the corresponding bit +* in resetBits. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param resetBits the reset bits of the selected deframers will correspond with their adi_fpga9010_FramerSel_e bit locations +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_FramerResetGet(adi_fpga9010_Device_t *device, uint32_t framerSelMask, uint8_t *resetBits); + +/** +* \brief Sets the configuration for the first eight outputs of the Lane XBar for the selected link using +* framerSel. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSel adi_fpga9010_FramerSel_e enum value to select the laneXBar +* \param laneXBar an eight element array holding the PHY lane assignments for each output lane +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxLaneXBarCfgSet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e framerSel, uint8_t *laneXBar); + +/** +* \brief Sets the configuration for the first eight outputs of the Lane XBar +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param deframerSel adi_fpga9010_DeframerSel_e enum value to select which deframer +* \param laneXBar an eight element array holding the PHY lane assignments for each output lane +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxLaneXBarCfgSet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e deframerSel, uint8_t *laneXBar); + +/** +* \brief Reads the configuration for the first eight outputs of the Lane XBar for the selected link using +* framerSel and stores them in the eight-element laneXBar array. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSel adi_fpga9010_FramerSel_e enum value to select which framer +* \param laneXBar an eight element array where the lane assignments will be written to +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxLaneXBarCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e framerSel, uint8_t *laneXBar); + +/** +* \brief Gets the configuration for the first eight outputs of the Lane XBar +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param deframerSel adi_fpga9010_DeframerSel_e enum value to select which deframer +* \param laneXBar an eight element array where the lane assignments will be written to +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxLaneXBarCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e deframerSel, uint8_t *laneXBar); + +/** +* \brief This function goes through the reset sequence for the selected framers in +* framerSelMask, where the bit location corresponds to the tx link number. This +* function should be called after adi_fpga9010_FramerCfgSet as part of link bringup. +* After this function the framer is ready for sysref signal. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_FramerReset(adi_fpga9010_Device_t *device, uint8_t framerSelMask); + +/** +* \brief This function disables all framers selected through the framerSelMask by setting +* the fixed reset bit. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_FramerDisable(adi_fpga9010_Device_t *device, uint8_t framerSelMask); + +/** +* \brief Enables the FPGA JESD204B Rx deframer +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_DeframerReset(adi_fpga9010_Device_t *device, uint8_t deframerSelMask); + +/** +* \brief Disables the FPGA JESD204B Rx deframer +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_DeframerDisable(adi_fpga9010_Device_t *device, uint8_t deframerSelMask); + +/** +* \brief For JESD204B returns the Sync status bit for the selected deframers in deframerSelMask. +* For JESD204C The status bit for each link will be a logical +* and of mb_lock & sync_header_lock bitfield values. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param status the Sync status bits of the selected deframers will correspond with their adi_fpga9010_DeframerSel_e bit locations +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_DeframerStatusGet(adi_fpga9010_Device_t *device, uint8_t deframerSelMask, uint8_t *status); + +/** +* \brief sets the loopback value for the selected lanes +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param laneSelMask to enable prbs on a lane set the corresponding bit to 1 +* \param loopbackValue sets the loopback mode, eg 2 for near-end PCS loopback +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_ChannelLoopbackEnable(adi_fpga9010_Device_t *device, uint8_t laneSelMask, uint8_t loopbackValue); + +/** +* \brief sets the DFE LPM Override value for the selected lanes +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param laneSelMask to enable prbs on a lane set the corresponding bit to 1 +* \param value sets the DFE LPM Override value (1 to override, 0 to disable override) +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_ChannelDfeLpmOverrideSet(adi_fpga9010_Device_t *device, uint8_t laneSelMask, uint8_t value); + +/** +* \brief Sets the configuration for the sync crossbar +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param polarity The sync xbar polarity. +* \param inputSyncSel an array of eight 3-bit values indicating the input sync selection for each sync crossbar output +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_SyncXBarCfgSet(adi_fpga9010_Device_t *device, uint8_t polarity, uint8_t *inputSyncSel); + +/** +* \brief Reads the configuration for the sync crossbar +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param polarity Pointer to the sync xbar polarity. +* \param inputSyncSel an array of eight uin8_t types. Will be filled with the 3-bit values from the input select registers +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_SyncXBarCfgGet(adi_fpga9010_Device_t *device, uint8_t *polarity, uint8_t *inputSyncSel); + +/** +* \brief Setup the FPGA JESD204 reference clock and SYSREF settings +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param sysRefCfg FPGA JESD204B clock structure settings for the reference clock +* frequency and SYSREF configuration +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_SysRefControlSet(adi_fpga9010_Device_t *device, adi_fpga9010_SysRefClkCfg_t *sysRefCfg); + +/** +* \brief Enable or disable Sysref for the selected Framers and Deframers +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param deframerSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param enable ADI_ENABLE or ADI_DISABLE to enable or disable respectively +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_SysRefEnableSet(adi_fpga9010_Device_t *device, uint8_t framerSelMask, uint8_t deframerSelMask, uint8_t enable); + +/** +* \brief Reads the FPGA JESD204 reference clock and SYSREF settings +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param sysRefCfg FPGA JESD204B clock structure settings for the reference clock +* frequency and SYSREF configuration +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_SysRefControlGet(adi_fpga9010_Device_t *device, adi_fpga9010_SysRefClkCfg_t *sysRefCfg); + +/** +* \brief Requests a SYSREF to be issued +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_SysRefRequest(adi_fpga9010_Device_t *device); + +/** +* \brief This function will set the interrupt enabled register in the JESD204C link layer. The parameter +* interruptBitMask is an or'd combination of the adi_fpga9010_Jesd204cIrq_e enum. +* The linkSelMask parameter is a bitmask that encapsulates the Rx & Tx links, ie: +* +* linkSelMask | Link +* ----------------------|------------------------------------ +* Bit 0 | RX Link 0 +* Bit 1 | RX Link 1 +* Bit 2 | RX Link 2 +* Bit 3 | TX Link 0 +* Bit 4 | TX Link 1 +* +* For the Set function, any number of links can be set with the same interruptBitMask value. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param interruptBitMask uint16_t bitmask of adi_fpga9010_Jesd204cIrq_e indicating the IRQs to be enabled/disabled. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_Jesd204cLinkLayerIrqEnSet(adi_fpga9010_Device_t *device, uint8_t linkSelMask, uint16_t interruptBitMask); + +/** +* \brief This function will read the interrupt enabled register in the JESD204C link layer. The parameter +* interruptBitMask will be a bitmask indicating which IRQs are enabled. It is structured off the +* adi_fpga9010_Jesd204cIrq_e enum. +* The linkSel parameter is a bitmask that encapsulates the Rx & Tx links, ie: +* +* linkSel | Link +* ----------------------|------------------------------------ +* Bit 0 | RX Link 0 +* Bit 1 | RX Link 1 +* Bit 2 | RX Link 2 +* Bit 3 | TX Link 0 +* Bit 4 | TX Link 1 +* + For the Get functions, only one bit can be set in linkSel per function call. + +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param linkSelMask a bitmask to choose between Rx & Tx links +* \param interruptBitMask uint16_t pointer that will contain which IRQs are enabled/disabled. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_Jesd204cLinkLayerIrqEnGet(adi_fpga9010_Device_t *device, uint8_t linkSelMask, uint16_t *interruptBitMask); + +/** +* \brief This function will read the interrupt status register in the JESD204C link layer. The parameter +* interruptBitMask will be a bitmask indicating which IRQs have been triggered. It is structured off the +* adi_fpga9010_Jesd204cIrq_e enum. +* The linkSel parameter is a bitmask that encapsulates the Rx & Tx links, ie: +* +* linkSel | Link +* ----------------------|------------------------------------ +* Bit 0 | RX Link 0 +* Bit 1 | RX Link 1 +* Bit 2 | RX Link 2 +* Bit 3 | TX Link 0 +* Bit 4 | TX Link 1 +* + For the Get functions, only one bit can be set in linkSel per function call. + +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param linkSel a bitmask to choose a single Rx or Tx link +* \param interruptBitMask uint16_t pointer that will contain which IRQs are triggered with a 1 in their respective bit location. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_Jesd204cLinkLayerIrqStatusGet(adi_fpga9010_Device_t *device, uint8_t linkSel, uint16_t *interruptBitMask); + +/** +* \brief Enables or disables the Command and Data interface of the Deframer's selected through the deframerSelMask bitmask. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param cmdEnable ADI_ENABLE or ADI_DISABLE to enable and disable the command interface +* \param dataEnable ADI_ENABLE or ADI_DISABLE to enable and disable the data interface +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_Jesd204CDeframerCmdDataSet(adi_fpga9010_Device_t *device, uint32_t deframerSelMask, uint8_t cmdEnable, uint8_t dataEnable); + +/** +* \brief Enables or disables the Command and Data interface of the Framer's selected through the framerSelMask bitmask. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param cmdEnable ADI_ENABLE or ADI_DISABLE to enable and disable the command interface +* \param dataEnable ADI_ENABLE or ADI_DISABLE to enable and disable the data interface +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_Jesd204CFramerCmdDataSet(adi_fpga9010_Device_t *device, uint32_t framerSelMask, uint8_t cmdEnable, uint8_t dataEnable); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_JESD_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_jesd_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_jesd_types.h new file mode 100644 index 0000000..a2b0ae5 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_jesd_types.h @@ -0,0 +1,315 @@ +/*! +* \file adi_fpga9010_jesd_types.h +* \brief Contains FPGA9010 JESD enum and struct definitions +* +* ADRV9010 API Version: $ADI_FPGA9010_API_VERSION$ +* +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_JESD_TYPES_H_ +#define _ADI_FPGA9010_JESD_TYPES_H_ + + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADI_FPGA9010_NUM_LANES 8 +#define ADI_FPGA9010_NUM_OF_DEFRAMERS 3 +#define ADI_FPGA9010_NUM_OF_FRAMERS 2 + +#define ADI_FPGA9010_2P02_GHZ 2027520 +#define ADI_FPGA9010_2P53_GHZ 2534400 +#define ADI_FPGA9010_3_GHZ 3041280 +#define ADI_FPGA9010_4P05_GHZ 4055040 +#define ADI_FPGA9010_4P91_GHZ 4915200 +#define ADI_FPGA9010_5_GHZ 5068800 +#define ADI_FPGA9010_6P08_GHZ 6082560 +#define ADI_FPGA9010_6P14_GHZ 6144000 +#define ADI_FPGA9010_7_GHZ 7372800 +#define ADI_FPGA9010_8_GHZ 8110080 +#define ADI_FPGA9010_9P2_GHZ 9216000 +#define ADI_FPGA9010_9_GHZ 9830400 +#define ADI_FPGA9010_10_GHZ 10137600 +#define ADI_FPGA9010_11_GHZ 11059200 +#define ADI_FPGA9010_12P16_GHZ 12165120 +#define ADI_FPGA9010_12P28_GHZ 12288000 +#define ADI_FPGA9010_14_GHZ 14745600 +#define ADI_FPGA9010_16_GHZ 16220160 + +#define ADI_FPGA9010_61P44_MHZ 61440 +#define ADI_FPGA9010_122P88_MHZ 122880 +#define ADI_FPGA9010_153P6_MHZ 153600 +#define ADI_FPGA9010_184P32_MHZ 184320 +#define ADI_FPGA9010_245P76_MHZ 245760 +#define ADI_FPGA9010_307P2_MHZ 307200 +#define ADI_FPGA9010_491P52_MHZ 491520 + +/** +* \brief Enumerated list of DRP mask values +*/ +typedef enum adi_fpga9010_DrpMask +{ + ADI_FPGA9010_TXCLK25DIV_MASK = 0xF800, + ADI_FPGA9010_TXPHDLY_CFG1_MASK = 0xFFFF, + ADI_FPGA9010_TXPI_CFG3_MASK = 0x0040, + ADI_FPGA9010_TX_PROGDIV_CFG_MASK = 0xFFFF, + ADI_FPGA9010_RXCLK25DIV_MASK = 0x00F8, + ADI_FPGA9010_PMA_RSV1_MASK = 0xFFFF, + ADI_FPGA9010_RXCDR_CFG2_MASK = 0xFFFF, + ADI_FPGA9010_RXDFE_GC_CFG1_MASK = 0xFFFF, + ADI_FPGA9010_RXPI_CFG4_MASK = 0x0200, + ADI_FPGA9010_RXPI_CFG5_MASK = 0x0100, + ADI_FPGA9010_RX_EN_HI_LR_MASK = 0x0400, + ADI_FPGA9010_RX_WIDEMODE_CDR_MASK = 0x0004, + ADI_FPGA9010_RX_PROGDIV_CFG_MASK = 0xFFFF, + ADI_FPGA9010_QPLL_N_MASK = 0x00FF, + ADI_FPGA9010_QPLL_M_MASK = 0x0F80, + ADI_FPGA9010_QPLL_LPF_MASK = 0x03FF, + ADI_FPGA9010_QPLL_CFG4_MASK = 0xFFFF, + ADI_FPGA9010_QPLL_CP_MASK = 0x03FF, + ADI_FPGA9010_QPLL_FBDIV_MASK = 0x00FF, + ADI_FPGA9010_QPLL_LOCK_CFG_MASK = 0xFFFF, + ADI_FPGA9010_QPLL_LOCK_CFG_G3_MASK = 0x03FF, + ADI_FPGA9010_QPLL_REFCLK_DIV_MASK = 0x0F80 +} adi_fpga9010_DrpMask_e; + +/** +* \brief Enumerated list of DRP mask values +*/ +typedef enum adi_fpga9010_DrpAddress +{ + ADI_FPGA9010_TXCLK25DIV_ADDRESS = 0x007A, + ADI_FPGA9010_TXPHDLY_CFG1_ADDRESS = 0x006F, + ADI_FPGA9010_TXPI_CFG3_ADDRESS = 0x009C, + ADI_FPGA9010_TX_PROGDIV_CFG_ADDRESS = 0x003E, + ADI_FPGA9010_RXCLK25DIV_ADDRESS = 0x006D, + ADI_FPGA9010_PMA_RSV1_ADDRESS = 0x0095, + ADI_FPGA9010_RXCDR_CFG2_ADDRESS = 0x0010, + ADI_FPGA9010_RXDFE_GC_CFG1_ADDRESS = 0x00A0, + ADI_FPGA9010_RXPI_CFG4_ADDRESS = 0x009D, + ADI_FPGA9010_RXPI_CFG5_ADDRESS = 0x009D, + ADI_FPGA9010_RX_EN_HI_LR_ADDRESS = 0x0052, + ADI_FPGA9010_RX_WIDEMODE_CDR_ADDRESS = 0x0066, + ADI_FPGA9010_RX_PROGDIV_CFG_ADDRESS = 0x00C6, + ADI_FPGA9010_QPLLCLK0_N_ADDRESS = 0x0014, + ADI_FPGA9010_QPLLCLK0_M_ADDRESS = 0x0018, + ADI_FPGA9010_QPLLCLK0_LPF_ADDRESS = 0x0019, + ADI_FPGA9010_QPLLCLK0_CFG4_ADDRESS = 0x0030, + ADI_FPGA9010_QPLLCLK0_CP_ADDRESS = 0x0016, + ADI_FPGA9010_QPLLCLK0_FBDIV_ADDRESS = 0x0014, + ADI_FPGA9010_QPLLCLK0_LOCK_CFG_ADDRESS = 0x0012, + ADI_FPGA9010_QPLLCLK0_LOCK_CFG_G3_ADDRESS = 0x001D, + ADI_FPGA9010_QPLLCLK0_REFCLK_DIV_ADDRESS = 0x0018, + ADI_FPGA9010_QPLLCLK1_N_ADDRESS = 0x0094, + ADI_FPGA9010_QPLLCLK1_M_ADDRESS = 0x0098, + ADI_FPGA9010_QPLLCLK1_CFG4_ADDRESS = 0x00B0, + ADI_FPGA9010_QPLLCLK1_CP_ADDRESS = 0x0096, + ADI_FPGA9010_QPLLCLK1_LOCK_CFG_ADDRESS = 0x0092, + ADI_FPGA9010_QPLLCLK1_LOCK_CFG_G3_ADDRESS = 0x009D, + ADI_FPGA9010_QPLLCLK1_LPF_ADDRESS = 0x0099 +} adi_fpga9010_DrpAddress_e; + +/** +* \brief Enumerated list of clk sources available to the Serializer/deserializer +*/ +typedef enum adi_fpga9010_LaneClkSel +{ + ADI_FPGA9010_CPLL = 0x0, + ADI_FPGA9010_QPLLCLK0 = 0x3, + ADI_FPGA9010_QPLLCLK1 = 0x2 +} adi_fpga9010_LaneClkSel_e; + + /** +* \brief Enumerated list of clk sources available to the Serializer/deserializer +*/ +typedef enum adi_fpga9010_Qpll_Quad +{ + ADI_FPGA9010_QPLL_QUAD0 = 0x1, + ADI_FPGA9010_QPLL_QUAD1 = 0x2 +} adi_fpga9010_Qpll_Quad_e; + +/** +* \brief Enumerated list of Gth Serializer/deserializer each is identified by a separate bit +*/ +typedef enum adi_fpga9010_LaneSel +{ + ADI_FPGA9010_LANE_0 = 0x1, /*!Gth serializer/deserializer Lane 1 */ + ADI_FPGA9010_LANE_1 = 0x2, /*!Gth serializer/deserializer Lane 2 */ + ADI_FPGA9010_LANE_2 = 0x4, /*!Gth serializer/deserializer Lane 3 */ + ADI_FPGA9010_LANE_3 = 0x8, /*!Gth serializer/deserializer Lane 4 */ + ADI_FPGA9010_LANE_4 = 0x10, /*!Gth serializer/deserializer Lane 5 */ + ADI_FPGA9010_LANE_5 = 0x20, /*!Gth serializer/deserializer Lane 6 */ + ADI_FPGA9010_LANE_6 = 0x40, /*!Gth serializer/deserializer Lane 7 */ + ADI_FPGA9010_LANE_7 = 0x80 /*!Gth serializer/deserializer Lane 8 */ +} adi_fpga9010_LaneSel_e; + +/** +* \brief Enumerated list of JESD204C interrupts each identified by a separate bit +*/ +typedef enum adi_fpga9010_Jesd204cIrq +{ + ADI_FPGA9010_GLOBAL = 0x1, /*!Global Interrupt Enable*/ + ADI_FPGA9010_SYSREF_RECEIVED = 0x2, /*!Interrupt Enable SYSREF Received*/ + ADI_FPGA9010_SYSREF_ERROR = 0X4, /*!Interrupt Enable SYSREF Error*/ + ADI_FPGA9010_LOSS_SYNC_HEADER_LOCK = 0x10, /*!Interrupt Enable Loss of 64b66b Sync Header Lock*/ + ADI_FPGA9010_LOSS_MB_LOCK = 0x20, /*!Interrupt Enable Loss of Multi-block Lock*/ + ADI_FPGA9010_BLOCK_SYNC_ERROR = 0x40, /*!Interrupt Enable Block Sync Error*/ + ADI_FPGA9010_MB_ERROR = 0x80, /*!Interrupt Enable Multi-block Error*/ + ADI_FPGA9010_CRC_ERROR = 0x100, /*!Interrupt Enable CRC Error*/ + ADI_FPGA9010_FEC_ERROR = 0x200, /*!Interrupt Enable FEC Error*/ + ADI_FPGA9010_OVERFLOW_ERROR = 0x400 /*!Interrupt Enable Overflow Error*/ +}adi_fpga9010_Jesd204cIrq_e; + +/** +* \brief Enumerated list of Gth Serializer/deserializer each is identified by a separate bit +*/ +typedef struct adi_fpga9010_SerializerCfg +{ + uint8_t chnl; /*! Identifies the lane to be configured by these settings 0..7 */ + uint8_t cpllRefClkSel; /*! Only needed for Cpll which is not used */ + adi_fpga9010_LaneClkSel_e txPllClkSel; /*! Selects the PLL to drive the transmitter data path. valid values from adi_fpga9010_PllClkSel_e */ + /* Rx Configs &TxConfigs */ + uint8_t rate; /*! Sets the final divider for the Channel receiver. The settings are: 000: Use RXOUT_DIV attributes 001: Divide by 1 010: Divide by 2 011: Divide by 4 100: Divide by 8 101: Divide by 16 110: Divide by 1 111: Divide by 1 */ + uint8_t encoder8b10bEnable; /*! 1: enable the 8b10b encoder in the Channel 0 transmitter - this is needed for JESD204B operation. 0: bypass the 8b10b encoder - this is needed for JESD204C operation.*/ + uint8_t polarity; /*! When set to 1, the corresponding transmit channel is inverted. When cleared to 0, the channel is not inverted. */ + uint8_t powerDown; /*! 00: P0 (normal operation) 01: P0s (low recovery time power down) 10: P1 (longer recovery time; Receiver Detection still on) 11: P2 (lowest power state) Attributes can control the transition times between these power-down states. */ + /* Tx Config */ + uint8_t precursor; /*! Transmitter post-cursor TX pre-emphasis control */ + uint8_t postcursor; /*! Transmitter post-cursor TX pre-emphasis control. */ + uint8_t diffCtrl; /*! Driver Swing/ Amplitude Control. */ + uint16_t txClk25Div; /*! RefClk / 25 - 1 written to DRP registers */ + uint16_t txPiCfg3; /*! JESD204B & JESD204C DRP config register. Value based on QPLL clock frequency and lane rate */ + uint16_t txPhdlyCfg1; /*! JESD204C DRP config register. Value based on QPLL clock frequency and lane rate */ + uint16_t txProgdivCfg; /*! JESD204C DRP config register. Value based on QPLL clock frequency and lane rate */ + +} adi_fpga9010_SerializerCfg_t; + +typedef struct adi_fpga9010_DeserializerCfg +{ + uint8_t chnl; /*!Identifies the lane to be configured by these settings. 0..7 */ + adi_fpga9010_LaneClkSel_e rxPllClkSel; /*! Selects the PLL to drive the receiver data path valid values from adi_fpga_qpllClkSel */ + //Rx Configs &TxConfigs; + uint8_t rate; /*! This bit field sets the final divider for the Channel receiver. valid values form adi_fpga9010_QpllFDVals_e. */ + uint8_t encoder8b10bEnable; /*! 1: enable the 8b10b encoder in the Channel 0 transmitter - this is needed for JESD204B operation. 0: bypass the 8b10b encoder - this is needed for JESD204C operation.*/ + uint8_t polarity; /*! When set to 1, the corresponding transmit channel is inverted. When cleared to 0, the channel is not inverted. */ + uint8_t powerDown; /*! 00: P0 (normal operation) 01: P0s (low recovery time power down) 10: P1 (longer recovery time; Receiver Detection still on) 11: P2 (lowest power state) Attributes can control the transition times between these power-down states.*/ + //Rx Config + uint8_t rxDfeLpmEn; /*! Controls a receive channel's rx_dfelpm_en signal. When set to 1, the LPM equalizer is enabled. When cleared to 0, the DFE equalizer is enabled.. */ + uint8_t cdrSetting; /*! TBD */ + uint16_t rxClk25Div; /*! RefClk / 25 - 1 written to DRP registers */ + uint16_t pmaRsv1; /*! JESD204B & JESD204C DRP config register. Value based on QPLL clock frequency and lane rate */ + uint16_t rxCdrCfg2; /*! JESD204B & JESD204C DRP config register. Value based on QPLL clock frequency and lane rate */ + uint16_t rxDfeGcCfg1; /*! JESD204B & JESD204C DRP config register. Value based on QPLL clock frequency and lane rate */ + uint16_t rxPiCfg4; /*! JESD204B & JESD204C DRP config register. Value based on QPLL clock frequency and lane rate */ + uint16_t rxPiCfg5; /*! JESD204B & JESD204C DRP config register. Value based on QPLL clock frequency and lane rate */ + uint16_t rxEnHiLr; /*! JESD204B & JESD204C DRP config register. Value based on QPLL clock frequency and lane rate */ + uint16_t rxWidemodeCdr; /*! JESD204B & JESD204C DRP config register. Value based on QPLL clock frequency and lane rate */ + uint16_t rxProgdivCfg; /*! JESD204C DRP config register. Value based on QPLL clock frequency and lane rate */ +} adi_fpga9010_DeserializerCfg_t; + +/** +* \brief Enum to select desired FPGA deframer +*/ +typedef enum adi_fpga9010_DeframerSel +{ + ADI_FPGA9010_DEFRAMER_0 = 1, /*< Deframer 0 selected */ + ADI_FPGA9010_DEFRAMER_1 = 2, /*< Deframer 1 selected */ + ADI_FPGA9010_DEFRAMER_2 = 4, /*< Deframer 2 selected */ + ADI_FPGA9010_DEFRAMER_ALL = 7 /*< All deframers selected */ +} adi_fpga9010_DeframerSel_e; + +/** +* \brief Enum to select desired FPGA framer +*/ +typedef enum adi_fpga9010_FramerSel +{ + ADI_FPGA9010_FRAMER_0 = 1, /*< Framer 0 selected */ + ADI_FPGA9010_FRAMER_1 = 2, /*< Framer 1 selected */ + ADI_FPGA9010_FRAMER_ALL = 3 /*< All framers selected */ +} adi_fpga9010_FramerSel_e; + +typedef struct adi_fpga9010_DeframerCfg +{ + /* Common Data */ + uint8_t laneXbar[ADI_FPGA9010_NUM_LANES]; /*! Indices correspond to Lane XBar outputs. Values correspond to Lane XBar inputs */ + uint8_t sysRefDelay; /*! Add additional delay to SYSREF re-alignment of LMFC counter 1111 = 15 core_clk cycles */ + uint8_t subclassV; /*! JESD204b sublcass: Subclass 2 = 0x10 Subclass 1 = 0x01 Subclass 0 = 0x00. JESD204c subclass: 0 = Subclass 0; 1 = Subclass 1 */ + uint8_t lanesInUse; /*! Each bit corresponds to a single lane, when set to 1 lane is active. Due to Lane XBars will always fill from bit 0 */ + + /* JESD204B */ + uint8_t bankId[ADI_FPGA9010_NUM_LANES]; /*! JESD204b Configuration Bank ID extension to Device ID. Read only, captured by ILA sequence */ + uint8_t cfgLaneId[ADI_FPGA9010_NUM_LANES]; /*! Read only, captured by ILA sequence */ + uint8_t scramblingEn; /*! Set to 1 to enable scrambling. Clear to disable */ + uint16_t cfgF; /*! Octets per frame. Register programmed with value - 1 */ + uint8_t cfgK; /*! Frames per multiframe. Register programmed with value - 1 */ + uint8_t ilaNp[ADI_FPGA9010_NUM_LANES]; /*! N' (Totals bits per Sample) */ + uint8_t ilaN[ADI_FPGA9010_NUM_LANES]; /*! N Converter Resolution */ + uint8_t ilaS[ADI_FPGA9010_NUM_LANES]; /*! Number of samples per converter per frame. Read only, captured by ILA sequence. Register programmed with value - 1 */ + uint8_t ilaM[ADI_FPGA9010_NUM_LANES]; /*! Number of converters per device. Read only, captured by ILA sequence. Register programmed with value - 1 */ + uint16_t rxBufferDly; /*! Used with RX Buffer Adjust to minimize latency */ + uint16_t rxBufferAdj[ADI_FPGA9010_NUM_LANES]; /*! Used with RX Buffer Delay to minimize latency. Read only, captured by ILA sequence */ + uint8_t errReportingDisable; /*! Disable Error Reporting Using SYNC Interface */ + uint8_t ilaSupportEn; /*! ILA Support Enable */ + uint8_t sysRefAlways; /*! SYSREF Always 1 = Core re-aligns LMFC counter on all SYSREF events */ + uint8_t sysRefRequiredOnResync; /*! 1 = A SYSREF event is required following a Link Re-Sync event */ + + /* JESD204C */ + uint8_t enableCmdInterface; /*! 1 = Enables AXI4-Stream Cmd interface; 0 = Cmd words will be zeroed */ + uint8_t enableDataInterface; /*! 1 = Enables AXI4-Stream Data interface; 0 = Link will be transmitting scrambled zeros */ + uint8_t cfgE; /*! CTRL_MB_IN_EMB- Number of multi-blocks in an extended multi-block. Programmed with actual value (0 is invalid) */ + uint8_t ctrlMetaMode; /*! 0 = Cmd; 1 = CRC; 2 = FEC [TBD] */ + uint8_t ctrlRxBufAdv; /*! Advance the release of the receiver buffer by N 64-bit words */ + uint8_t ctrlRxMBlockTh; /*! MB lock threshold */ + uint16_t ctrlIrq; /*! Bit mask to enable/disable individual interrupts. Bit 0 is Global Interrupt Enable */ + +} adi_fpga9010_DeframerCfg_t; + +typedef struct adi_fpga9010_FramerCfg +{ + /* Common data */ + uint8_t laneXbar[ADI_FPGA9010_NUM_LANES]; /*! Indices correspond to Lane XBar outputs. Values correspond to Lane XBar inputs */ + uint8_t sysRefDelay; /*! Add additional delay to SYSREF re-alignment of LMFC counter 1111 = 15 core_clk cycles */ + uint8_t subclassV; /*! JESD204b sublcass: Subclass 2 = 0x10 Subclass 1 = 0x01 Subclass 0 = 0x00. JESD204c subclass: 0 = Subclass 0; 1 = Subclass 1 */ + uint8_t lanesInUse; /*! Each bit corresponds to a single lane, when set to 1 lane is active. Due to Lane XBars will always fill from bit 0 */ + + /* JESD204B */ + uint8_t deviceId; /*! JESD204b Configuration Device ID. Sets value for all lanes */ + uint8_t bankId; /*! JESD204b Configuration Bank ID extension to Device ID. Sets value for all lanes */ + uint8_t scramblingEn; /*! Set to 1 to enable scrambling. Clear to disable */ + uint16_t ilaMultiFrames; /*! Multiframes in the Transmitted ILAS. Register programmed with value - 1 */ + uint16_t cfgF; /*! Octets per frame. Register programmed with value - 1 */ + uint8_t cfgK; /*! Frames per multiframe. Register programmed with value - 1 */ + uint8_t ilaM; /*! Number of converters per device. Sets value for all lanes. Register programmed with value - 1 */ + uint8_t ilaN; /*! Converter resolution. Sets value for all lanes. Register programmed with value - 1 */ + uint8_t ilaCs; /*! Control bits per sample. Sets value for all lanes */ + uint8_t ilaNp; /*! Total bits per sampele. Sets value for all lanes. Register programmed with value - 1 */ + uint8_t ilaS; /*! Samples per converter per frame. Sets value for all lanes. Register programmed with value - 1 */ + uint8_t ilaCf; /*! Control words per frame. Sets value for all lanes */ + uint8_t ilaHd; /*! High density format. Sets value for all lanes */ + uint8_t ilaSupportEn; /*! ILA Support Enable */ + uint8_t sysRefAlways; /*! SYSREF Always 1 = Core re-aligns LMFC counter on all SYSREF events */ + uint8_t sysRefRequiredOnResync; /*! 1 = A SYSREF event is required following a Link Re-Sync event */ + + /* JESD204C */ + uint8_t enableCmdInterface; /*! 1 = Enables AXI4-Stream Cmd interface; 0 = Cmd words will be zeroed */ + uint8_t enableDataInterface; /*! 1 = Enables AXI4-Stream Data interface; 0 = Link will be transmitting scrambled zeros */ + uint8_t cfgE; /*! CTRL_MB_IN_EMB- Number of multi-blocks in an extended multi-block. Programmed with actual value (0 is invalid) */ + uint8_t ctrlMetaMode; /*! 0 = Cmd; 1 = CRC; 2 = FEC [TBD] */ + uint16_t ctrlIrq; /*! Bit mask to enable/disable individual interrupts. Bit 0 is Global Interrupt Enable */ + +} adi_fpga9010_FramerCfg_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_JESD_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_prbs.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_prbs.h new file mode 100644 index 0000000..e03d188 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_prbs.h @@ -0,0 +1,115 @@ +/** +* \file adi_fpga9010.h +* \brief Contains top level fpga9010 related function prototypes for +* adi_fpga9010.c +* +* FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ +*/ +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_PRBS_H_ +#define _ADI_FPGA9010_PRBS_H_ + +#include "adi_fpga9010_prbs_types.h" +#include "adi_fpga9010_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Enable PRBS generator on the selected TX lanes with the desired PRBS mode +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param laneSelMask to enable prbs on a lane set the corresponding bit to 1 +* \param prbsSel 4 bit value selecting the prbs mode +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_PrbsSerializerEnable(adi_fpga9010_Device_t *device, uint8_t laneSelMask, uint8_t prbsSel); + +/** +* \brief Enable PRBS checker on the selected lanes RX with the desired PRBS mode +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param laneSelMask to enable prbs on a lane set the corresponding bit to 1 +* \param prbsSel 4 bit value selecting the prbs mode +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_PrbsDeserializerEnable(adi_fpga9010_Device_t *device, uint8_t laneSelMask, uint8_t prbsSel); + +/** +* \brief Inject errors on the selected TX lanes +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param laneSelMask to enable prbs on a lane set the corresponding bit to 1 +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_PrbsSerializerErrorInject(adi_fpga9010_Device_t *device, uint8_t laneSelMask); + +/** +* \brief Reads FPGA deserializer PRBS error counts on all lanes +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param errCounts an array of uint32_t of length 8. Will be set with the error count per lane +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_PrbsErrorCountRead(adi_fpga9010_Device_t *device, uint32_t *errCounts); + +/** +* \brief Clears the error counter on the selected RX lanes +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param laneSelMask to enable prbs on a lane set the corresponding bit to 1 +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_PrbsErrorClear(adi_fpga9010_Device_t *device, uint8_t laneSelMask); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_PRBS_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_prbs_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_prbs_types.h new file mode 100644 index 0000000..2c1d447 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_prbs_types.h @@ -0,0 +1,35 @@ +/*! +* \file adi_adrv9010_tx_types.h +* \brief Contains FPGA9010 PRBS enum and struct definitions +* +* ADRV9010 API Version: $ADI_FPGA9010_API_VERSION$ +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + + +#ifndef _ADI_FPGA9010_PRBS_TYPES_H_ +#define _ADI_FPGA9010_PRBS_TYPES_H_ + + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum adi_fpga_prbsLaneSel +{ + ADI_FPGA9010_PRBS_DUMMYPIN = 0 /*!< TODO: fix this */ + +} adi_fpga_prbsLaneSel_e; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_PRBS_TYPES_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_rx.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_rx.h new file mode 100644 index 0000000..97505d4 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_rx.h @@ -0,0 +1,434 @@ +/** + * \file: adi_fpga9010_rx.h + * + * \brief Contains top level rx fpga9010 related prototypes + * + * FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_RX_H_ +#define _ADI_FPGA9010_RX_H_ + +#include "adi_fpga9010_rx_types.h" +#include "adi_fpga9010.h" + +/* 0x2AAAAA80, 2G /3, then reduced to a 64byte boundary */ +#define RX_DMA_SIZE 715827840 + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief This function writes the adi_fpga9010_RxTollgateCfg_t structure to the tollgate +* modules selected in the rxDatamoverSelMask. This function could be used as part +* of an rx capture setup procedure if more than just the trigger select should be +* configured. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param tollGateCfg contains the tollgate configuration setting structure +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxTollgateSet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, adi_fpga9010_RxTollgateCfg_t *tollGateCfg); + +/** +* \brief Reads the configuration for a single tollgate module and populates the empty +* adi_fpga9010_RxTollgateCfg_t structure passed in to the function. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDatamoverSel an adi_fpga9010_DeframerSel_e enum value selecting a single datamover +* \param tollGateCfg an empty structure that will be written with the selected tollgate's configuration values +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxTollgateGet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e rxDatamoverSel, adi_fpga9010_RxTollgateCfg_t *tollGateCfg); + +/** +* \brief This function writes the reset bit to the tollgate +* modules selected in the rxDatamoverSelMask. The reset bit is not self-clearing +* so a full reset will require a call to this function to write a 1 then another +* call to write a 0 for normal operation. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param resetVal the reset value (1 for reset; 0 for normal operation) +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxTollgateResetSet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, uint8_t resetVal); + +/** +* \brief This function reads the reset bit to the tollgate +* modules selected in the rxDatamoverSelMask. It zeros the resetVal parameter +* and copies each module's reset value to the bit location given by the +* adi_fpga9010_DeframerSel_e enum. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param resetVal a combination of all the selected tollgate modules' reset value +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxTollgateResetGet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, uint16_t *resetVal); + +/** +* \brief This function writes the trigger select to the tollgate +* modules selected in the rxDatamoverSelMask. This function could be used as part +* of an rx capture setup procedure. It puts the tollgate in reset, configures the +* trigger, then releases the reset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param triggerSelect Select from adi_fpga_TrigSources_e enum +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxTollgateTriggerSet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, adi_fpga9010_RxTollgateTrigSources_e triggerSelect); + +/** +* \brief Reads the trigger bitfield for a single tollgate module and populates the empty +* pointer passed in to the function. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDatamoverSel an adi_fpga9010_DeframerSel_e enum value selecting a single datamover +* \param triggerSelect pointer to an adi_fpga9010_RxTollgateTrigSources_e enum to hold the readback value +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxTollgateTriggerGet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e rxDatamoverSel, adi_fpga9010_RxTollgateTrigSources_e *triggerSelect); + +/** +* \brief This function writes the adi_fpga9010_RxDmaCfg_t structure to the DMA +* modules selected in the rxDatamoverSelMask. This function could be used as part +* of an rx capture setup procedure. The LastDescriptor bitfield and RunStop bits +* are not written during this function call. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param rxDmaCfg contains the dma configuration settings to apply to all selected DMA modules +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxDmaSet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, adi_fpga9010_RxDmaCfg_t *rxDmaCfg); + +/** +* \brief This function writes the static members of the adi_fpga9010_RxDmaCfg_t structure to the DMA +* modules selected in the rxDatamoverSelMask. This function is used when the fpga +* boots up. The DMAs are not ready for capture after this function. +* The LastDescriptor, RunStop, and Length bitfields are not written +* during this function call. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param rxDmaCfg contains the dma configuration settings to apply to all selected DMA modules +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxDmaInit(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, adi_fpga9010_RxDmaCfg_t *rxDmaCfg); + +/** +* \brief Reads the configuration for a single DMA module and populates the empty +* adi_fpga9010_RxDmaCfg_t structure passed in to the function. This function reads +* Read-Write & Read-Only bitfields, including status bits. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDatamoverSel an adi_fpga9010_DeframerSel_e enum value selecting a single datamover +* \param rxDmaCfg contains the dma configuration setting +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxDmaGet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e rxDatamoverSel, adi_fpga9010_RxDmaCfg_t *rxDmaCfg); + +/** +* \brief This function writes the reset bit to the dma +* modules selected in the rxDatamoverSelMask. The reset bit is self-clearing +* so there is no need to clear after setting. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param resetVal set to 1 to reset module +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxDmaResetSet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, uint8_t reset); + +/** +* \brief This function writes the run-stop bit to the dma +* modules selected in the rxDatamoverSelMask. This can be used during the middle of a transfer +* to gracefully halt the DMA. In this case the module must be halted after halting. +* More commonly used prior to an rx capture to start the DMAs before +* triggering. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param runStop set to 1 to begin transfer; 0 to halt transfer +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxDmaRunStopSet(adi_fpga9010_Device_t *device, uint32_t rxDataMoverSelMask, uint8_t runStop); + +/** +* \brief This function writes the length bitfield to the dma +* modules selected in the rxDatamoverSelMask. This should be done prior to performing a capture. +* The length indicates the number of bytes the DMA will run for after triggering. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param numBytes the number of bytes to transfer +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxDmaLengthSet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, uint32_t numBytes); + +/** +* \brief Unimplemented +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_INV_RX_DATA_MOVER_ENABLE An invalid rx data mover trigger selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxDatamoverEnableSet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask); + +/** +* \brief This function will configure all the selected Datachains in the rxDataMoverSelMask. +* A Datachain consists of the Capture Control, Tollgate, & DMA modules. The tollgate trigger +* is configured using adi_fpga9010_RxTollgateTriggerSet, +* the DMA is reset then configured using adi_fpga9010_RxDmaSet, +* the DMA is started by setting the run-stop bit using adi_fpga9010_RxDmaRunStopSet, +* and finally the token passing is initiated in the Capture Control module. This function +* is used in rx captures and is the final step before triggering. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param triggerSelect Select from adi_fpga_TrigSources_e enum +* \param rxDmaCfg contains the dma configuration settings to apply to all selected DMA modules +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxDataChainConfigure(adi_fpga9010_Device_t *device, uint32_t rxDataMoverSelMask, adi_fpga9010_RxTollgateTrigSources_e triggerSelect, adi_fpga9010_RxDmaCfg_t *rxDmaCfg); + +/** +* \brief This function clears and resets all Datachains to prepare for a new capture or as part +* of a tear down routine. The Capture Controls are reset and deactivated, the DMAs are halted +* and will return errors if halted ungracefully, and the Tollgates are held in reset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxDataChainReset(adi_fpga9010_Device_t *device); + +/** +* \brief Unimplemented +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_INV_RX_DATA_MOVER_ENABLE An invalid rx data mover trigger selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxDatamoverEnableGet(adi_fpga9010_Device_t *device, uint32_t *rxDatamoverSelMask); + +/** +* \brief Writes a 1 to the Capture Control modules Datapath Active bitfield. A capture will then occur +* based on the Tollgate trigger selections. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxCaptureStart(adi_fpga9010_Device_t *device); + +/** +* \brief Called after adi_fpga9010_RxCaptureStart to block program execution until the capture completes +* or the timeMsDelay expires. The function waits for the Active bitfield in the Capture Control +* module to clear. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param timeMsDelay is uint32_t type which conveys the wait time in milliseconds, i.e. 200 = 200 ms +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_DATA_RX_MOVER_WAIT_TIMEOUT Timeout occurred during Rx transaction +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxCaptureWait(adi_fpga9010_Device_t *device, uint32_t timeMsDelay); + + +/** +* \brief Unimplemented +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDatamoverSel the selected datamover to read +* \param data the user provided array into which the data is placed. +* \param dataSize the size of the data array. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_DATA_RX_MOVER_WAIT_TIMEOUT Timeout occurred during Rx transaction +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_RxDataGet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e rxDatamoverSel, int32_t data[], uint32_t *dataSize); + + /** +* \brief Unimplemented +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param rxDataMoverSelMask an or'd combination of one or more adi_fpga9010_DeframerSel_e enum values +* \param numSamples the number of samples to be written from part to the memory. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_DATA_RX_MOVER_WAIT_TIMEOUT Timeout occurred during Rx transaction +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ + int32_t adi_fpga9010_RxSamplesSet(adi_fpga9010_Device_t *device, uint32_t rxDataMoverSelMask, uint32_t numSamples); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_RX_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_rx_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_rx_types.h new file mode 100644 index 0000000..8f01567 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_rx_types.h @@ -0,0 +1,75 @@ +/*! +* \file adi_fpga9010_rx_types.h +* \brief Contains FPGA9010 rx enum and struct definitions +* +* ADRV9010 API Version: $ADI_FPGA9010_API_VERSION$ +* +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_RX_TYPES_H_ +#define _ADI_FPGA9010_RX_TYPES_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADI_FPGA9010_NUM_OF_RX_DATAMOVERS 3 + +/** +* \brief Enumerated list of fpga Rx Tollgata trigger sources +*/ +typedef enum adi_fpga9010_RxTollgateTrigSources +{ + ADI_FPGA9010_IMM_TRIG = 0x1, /*!Immediate trigger. */ + ADI_FPGA9010_EXT_TRIG = 0x2, /*!External Trigger external SMA. */ + ADI_FPGA9010_TDD_SM = 0x4, /*!TDD State Machine. */ + ADI_FPGA9010_ARM_ACK = 0x8, /*!GPIO. */ + ADI_FPGA9010_TX1_SOF = 0x10, /*!TX1 Start of File Flag from transmit to indicate start of transmit tone.*/ + ADI_FPGA9010_TX2_SOF = 0x20, /*!TX2 Start of File Flag from transmit to indicate start of transmit tone. */ + ADI_FPGA9010_TX3_SOF = 0x40, /*!TX3 Start of File Flag from transmit to indicate start of transmit tone. */ + ADI_FPGA9010_TX4_SOF = 0x80 /*!TX4 Start of File Flag from transmit to indicate start of transmit tone. */ +} adi_fpga9010_RxTollgateTrigSources_e; + +/** +* \brief Data structure to hold the Fpga Data mover tollgate Configuration +*/ +typedef struct adi_fpga9010_RxTollgateCfg +{ + uint32_t tollGateEdgeOrLvl; /*!1 indicates that the trigger input is edge detected. 0 indicates that the trigger input is level sensitive. */ + uint32_t tollGateHiRiseOrLoFall; /*!1 indicates either high level or rising edge. 0 indicates either low level or falling edge. */ + uint8_t tollgateReset; /*!Set to 1 resets the Tollgate. Clear to 0 allows for normal operation.. */ + adi_fpga9010_RxTollgateTrigSources_e tollGateTrigSource; /*!Selects the trigger input that is used to open the Tollgate. multiple triggers Supported */ +} adi_fpga9010_RxTollgateCfg_t; + +/** +* \brief Data structure to hold the Fpga Data mover dma Configuration +*/ +typedef struct adi_fpga9010_RxDmaCfg +{ + uint8_t enableEnhancedMode; /*!When set to 1, the enhanced mode of the selected transfer is performed. When cleared to 0, the traditional mode of the selected transfer is performed. */ + uint8_t enableSg; /*!When set to 1, the DMA performs a scatter-gather transfer. When cleared to 0, the DMA performs a simple transfer. */ + uint32_t simpleStartAddr; /*!indicates the starting address in memory where the data should be written.*/ + uint32_t length; /*!Identifies the number of bytes to transfer in the simple mode and enhanced scatter-gather mode. */ + uint8_t validDataWidthStream; /*!This field indicates what the width of valid data is on the stream interface. This field is used to pack/unpack the data from the memory.*/ + uint32_t sgFirstDescriptor; /*!Contains the location of the first descriptor used in both scatter-gather modes. */ + uint32_t sgLastDescriptor; /*!Contains the location of the last descriptor used in both scatter-gather modes. */ + uint8_t runStop; /*! When set to 1, the DMA begins the transfer. When cleared to 0, any active transfer is gracefully halted. When halted, the module needs to be reset after the halt completes.*/ + uint8_t active; /*! When this bit is 1, the DMA is actively transferring data. Read-only */ + uint8_t complete; /*! When this bit is 1, the transfer has completed successfully. This bit will clear when run_stop is cleared to '0'. Read-only */ + uint8_t haltComplete; /*! When this bit is 1, the halt that was previously issued has completed. This module must be reset after a halt completes. Read-only */ + uint8_t overflow; /*! When this bit is 1, an overflow has occurred on the FIFO. This is a sticky bit. Write a 1 to this bit to clear it. Read-only */ +} adi_fpga9010_RxDmaCfg_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_RX_TYPES_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_tdd.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_tdd.h new file mode 100644 index 0000000..4f00591 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_tdd.h @@ -0,0 +1,225 @@ +/** +* \file adi_fpga9010.h +* \brief Contains top level fpga9010 related function prototypes for +* adi_fpga9010_tdd.c +* +* FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ +*/ +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_TDD_H_ +#define _ADI_FPGA9010_TDD_H_ + +#include "adi_fpga9010_tdd_types.h" +#include "adi_fpga9010_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Initializes the FPGA TDD state machine +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param fpgaTddStateMachine is a pointer to structure type fpgaTddStateMachine_t which contains all +* TDD state machine parameters. This structure must be pre-loaded before use and is checked for a +* null pointer if not initialized and an error will be thrown. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TddInit(adi_fpga9010_Device_t *device, adi_fpga9010_TddStateMachine_t *fpgaTddStateMachine); + +/** +* \brief Reads the FPGA TDD state machine from the FPGA modules and loads the values into the structure +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param fpgaTddStateMachine is a pointer to an empty structure type fpgaTddStateMachine_t. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TddInitGet(adi_fpga9010_Device_t *device, adi_fpga9010_TddStateMachine_t *fpgaTddStateMachine); + +/** +* \brief Enables the TDD state machine by setting the Frame Counter module enable bit +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TddEnable(adi_fpga9010_Device_t *device); + +/** +* \brief Disables the TDD state machine by clearing the Frame Counter enable bit +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TddDisable(adi_fpga9010_Device_t *device); + + +int32_t adi_fpga9010_TddDataGate(adi_fpga9010_Device_t *device); + +/** +* \brief Manually asserts the TDD enable pins indicated in the fpgaTddEnables parameter +* using the following bitmapping: +* +* fpgaTddEnables[bit] | TDD Enable signal +* ---------------------|------------------------ +* 0 | Rx1 +* 1 | Rx2 +* 2 | Rx3 +* 3 | Rx4 +* 4 | Orx1 +* 5 | Orx2 +* 6 | Orx3 +* 7 | Orx4 +* 8 | Tx1 +* 9 | Tx2 +* 10 | Tx3 +* 11 | Tx4 +* 12 | Ext1 +* 13 | Ext2 +* 14 | Ext3 +* 15 | Ext4 +* 16 | Tx1 to Orx1 +* 17 | Tx2 to Orx1 +* 18 | Tx1 to Orx2 +* 19 | Tx2 to Orx2 +* 20 | Tx3 to Orx3 +* 21 | Tx4 to Orx3 +* 22 | Tx3 to Orx4 +* 23 | Tx4 to Orx4 +* +* This is a manual control used for debug and is overridden +* anytime the TDD state machine is enabled. The function will +* NOT disable all TDD modules prior to asserting the enables, it +* is incumbent on the user to disable TDD prior to using manual +* enable assertion. The value of the bit for each TDD enable module +* is what will be written to the manual assert value. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param fpgaTddEnables is a uint32_t bit field which contains the TDD enable +* bits for assertion. +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* \retval ADI_FPGA9010_ACT_INV_TDD_ASSERT_SELECT Invalid bits were selected when asserting TDD pins +* +*/ +int32_t adi_fpga9010_TddEnablesAssertSet(adi_fpga9010_Device_t *device, uint32_t fpgaTddEnables); + +/** +* \brief This function will read back the manual enable assert value that is currently written in each +* Enable Control module. Note: If TDD is not properly disabled, the manual enable value might not +* correspond with the actual pin logic state. +* +* fpgaTddEnables[bit] | TDD Enable signal +* ---------------------|------------------------ +* 0 | Rx1 +* 1 | Rx2 +* 2 | Rx3 +* 3 | Rx4 +* 4 | Orx1 +* 5 | Orx2 +* 6 | Orx3 +* 7 | Orx4 +* 8 | Tx1 +* 9 | Tx2 +* 10 | Tx3 +* 11 | Tx4 +* 12 | Ext1 +* 13 | Ext2 +* 14 | Ext3 +* 15 | Ext4 +* 16 | Tx1 to Orx1 +* 17 | Tx2 to Orx1 +* 18 | Tx1 to Orx2 +* 19 | Tx2 to Orx2 +* 20 | Tx3 to Orx3 +* 21 | Tx4 to Orx3 +* 22 | Tx3 to Orx4 +* 23 | Tx4 to Orx4 +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param fpgaTddEnables is a uint32_t bit field which will hold the TDD enable +* bits currently set in the module. +* +* \retval ADI_FPGA9010_ACT_NO_ACTION Function completed successfully, no action required +* \retval ADI_FPGA9010_ACT_INV_TDD_ASSERT_SELECT Invalid bits were selected when asserting TDD pins +* +*/ +int32_t adi_fpga9010_TddEnablesAssertGet(adi_fpga9010_Device_t *device, uint32_t *fpgaTddEnables); + +/** +* \brief This function will setup the Orx Pin Encode module with the values passed in +* through the orxPinEncodeCfg structure. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param orxPinEncodeCfg Pointer to a filled out adi_fpga9010_OrxPinEncodeCfg_t structure +* +* \retval ADI_FPGA9010_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TddOrxPinCfgSet(adi_fpga9010_Device_t *device, adi_fpga9010_OrxPinEncodeCfg_t *orxPinEncodeCfg); + +/** +* \brief This function will read the Orx Pin Encode module and write the values to the +* orxPinEncodeCfg structure passed in. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param orxPinEncodeCfg Pointer to a adi_fpga9010_OrxPinEncodeCfg_t structure to be filled with current module values +* +* \retval ADI_FPGA9010_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TddOrxPinCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_OrxPinEncodeCfg_t *orxPinEncodeCfg); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_TDD_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_tdd_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_tdd_types.h new file mode 100644 index 0000000..14d8ff9 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_tdd_types.h @@ -0,0 +1,139 @@ +/*! +* \file adi_fpga9010_tdd_types.h +* \brief Contains FPGA9010 TDD enum and struct definitions +* +* ADRV9010 API Version: 6.4.0.14 +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_TDD_TYPES_H_ +#define _ADI_FPGA9010_TDD_TYPES_H_ + +#include +//#include "adi_fpga_tdd_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Enumumerated list of the Orx Pin Encode modes +*/ +typedef enum adi_fpga9010_OrxPinEncodeModes +{ + ADI_FPGA9010_ORXPINENCODE_MODE1 = 0, /* 3 pin mode (ORx_Enable and ORx_Select[1:0] pins) */ + ADI_FPGA9010_ORXPINENCODE_MODE1A = 1, /* 2 pin mode (ORx_Enable and ORx_Select pins) */ + ADI_FPGA9010_ORXPINENCODE_MODE2 = 2, /* 4 pin mode (2 ORx_Enable pins and 2 ORx Select pins) */ + ADI_FPGA9010_ORXPINENCODE_MODE3 = 3, /* 1 pin mode (ORx selection is accomplished via SPI bits) */ + ADI_FPGA9010_ORXPINENCODE_MODE4 = 4 /* 2 pin mode (ORx selection is accomplished via SPI bits) */ +}adi_fpga9010_OrxPinEncodeModes_e; + +/** +* \brief Structure to hold the FPGA TDD Timing parameters. Located in the TDD Enable +* Control FPGA module. Includes primary & secondary region parameters. +*/ +typedef struct adi_fpga9010_TddTiming +{ + uint32_t onPtr; /*!< On pointer (start value) for TDD primary region */ + uint32_t offPtr; /*!< Off pointer (start value) for TDD primary region */ + uint32_t secondaryOnPtr; /*!< On pointer (start value) for TDD secondary region */ + uint32_t secondaryOffPtr; /*!< Off pointer (start value) for TDD secondary region */ + uint32_t offsetFrames; /*!< Offset frame value for primary & secondary region */ + uint32_t activeFrames; /*!< Active frame value for primary & secondary region */ + uint32_t inactiveFrames; /*!< Inactive frame value for primary & secondary region */ +} adi_fpga9010_TddTiming_t; + +/** +* \brief Structure to hold the FPGA TDD Datapath parameters. Located in the TDD Datapath +* Control FPGA module. +*/ +typedef struct adi_fpga9010_TddDatapathControl +{ + uint8_t enable; /*!< Set this value to 1 to enable this datapath. Otherwise, set to 0 */ + uint32_t startValue; /*!< Start Value for Datapath Control Module. Effectively the Datapath Delay value */ +} adi_fpga9010_TddDatapathControl_t; + +/** +* \brief Structure to hold the FPGA TDD state machine parameters +*/ +typedef struct adi_fpga9010_TddStateMachine +{ + uint32_t loopCount; /*!< Set this value to > 1 to enable looping */ + uint8_t syncExtTrig; /*!< Set this value to 1 to enable external triggering. Otherwise, set to 0 */ + uint32_t frameCount; /*!< Number of Tx LaneRate /40 clock cycles in the desired frame time */ + + adi_fpga9010_TddTiming_t rx1EnableControl; + adi_fpga9010_TddTiming_t rx2EnableControl; + adi_fpga9010_TddTiming_t rx3EnableControl; + adi_fpga9010_TddTiming_t rx4EnableControl; + + adi_fpga9010_TddTiming_t orx1EnableControl; + adi_fpga9010_TddTiming_t orx2EnableControl; + adi_fpga9010_TddTiming_t orx3EnableControl; + adi_fpga9010_TddTiming_t orx4EnableControl; + + adi_fpga9010_TddTiming_t tx1EnableControl; + adi_fpga9010_TddTiming_t tx2EnableControl; + adi_fpga9010_TddTiming_t tx3EnableControl; + adi_fpga9010_TddTiming_t tx4EnableControl; + + adi_fpga9010_TddTiming_t tx1ToOrx1EnableControl; + adi_fpga9010_TddTiming_t tx2ToOrx1EnableControl; + adi_fpga9010_TddTiming_t tx1ToOrx2EnableControl; + adi_fpga9010_TddTiming_t tx2ToOrx2EnableControl; + adi_fpga9010_TddTiming_t tx3ToOrx3EnableControl; + adi_fpga9010_TddTiming_t tx4ToOrx3EnableControl; + adi_fpga9010_TddTiming_t tx3ToOrx4EnableControl; + adi_fpga9010_TddTiming_t tx4ToOrx4EnableControl; + + adi_fpga9010_TddTiming_t extTrig1; + adi_fpga9010_TddTiming_t extTrig2; + adi_fpga9010_TddTiming_t extTrig3; + adi_fpga9010_TddTiming_t extTrig4; + + adi_fpga9010_TddDatapathControl_t rxDatapath0; + adi_fpga9010_TddDatapathControl_t rxDatapath1; + adi_fpga9010_TddDatapathControl_t rxDatapath2; + adi_fpga9010_TddDatapathControl_t txDatapath0; + adi_fpga9010_TddDatapathControl_t txDatapath1; + +} adi_fpga9010_TddStateMachine_t; + +typedef enum adi_fpga9010_TddGpioModule +{ + ADI_FPGA9010_ENABLE1CONTROL, + ADI_FPGA9010_ENABLE2CONTROL, + ADI_FPGA9010_ENABLE3CONTROL, + ADI_FPGA9010_ENABLE4CONTROL, + ADI_FPGA9010_SELECT1CONTROL, + ADI_FPGA9010_SELECT2CONTROL, + ADI_FPGA9010_SELECT3CONTROL, + ADI_FPGA9010_SELECT4CONTROL + +} adi_fpga9010_TddModule_e; + +/** +* \brief Structure to hold the FPGA TDD Orx Pin Encode module parameters +*/ +typedef struct adi_fpga9010_OrxPinEncodeCfg +{ + adi_fpga9010_OrxPinEncodeModes_e modeSelect; /*!< Selects the ORX Pin mode encoding. */ + uint8_t fastSwitchingEnable; /*!< Enables fast switching when changing ORX Select. When set to 1, ORX Select is allowed to change with ORX Enable high. When set to 0, ORX Enable is brought low before switching the ORX Select bits. */ + uint8_t mode1aOrxSelectLow; /*!< When in Mode 1A, this bit field identifies which ORX channel is enabled when the ORX Select pin is low. The valid values are:0b00 - ORX1; 0b01 - ORX2; 0b10 - ORX3; 0b11 - ORX4; */ + uint8_t mode1aOrxSelectHigh; /*!< When in Mode 1A, this bit field identifies which ORX channel is enabled when the ORX Select pin is high. The valid values are:0b00 - ORX1; 01 - ORX2; 0b10 - ORX3; 0b11 - ORX4; */ + uint8_t mode3OrxSelect; /*!< When in Mode 3, this bit field identifies the ORX channel that is enabled. The valid values are:0b00 - ORX1; 01 - ORX2; 0b10 - ORX3; 0b11 - ORX4; */ + uint16_t orxSelectSetupTime; /*!< This bit field sets the amount of time, in TDD State Machine clock periods, that the state machine waits after setting the ORX Select pins before raising ORX Enable. If the state machine is configured to allow fast switching, this setup time is performed before ORX Enable raises. Once high, the ORX Select is switched immediately. Should be written value minus 1. */ + uint16_t orxEnableHighTime; /*!< Sets the minimum amount of time that ORX Enable is high in 10s of nanoseconds. Should be written value minus 1. */ + uint16_t orxEnableLowTime; /*!< Sets the minimum amount of time that ORX Enable is low in 10s of nanoseconds. Should be written value minus 1. */ +}adi_fpga9010_OrxPinEncodeCfg_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_TDD_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_tx.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_tx.h new file mode 100644 index 0000000..fe24f65 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_tx.h @@ -0,0 +1,471 @@ +/** + * \file: adi_fpga9010_tx.h + * + * \brief Contains top level tx fpga9010 related prototypes + * + * FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_TX_H_ +#define _ADI_FPGA9010_TX_H_ + +#include "adi_fpga9010_tx_types.h" +#include "adi_fpga9010_types.h" + +#define TX_DMA_SIZE 0x40000000 + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief This function writes the adi_fpga9010_TxTollgateCfg_t structure to the tollgate +* modules selected in the txDataMoverSelMask. This function could be used as part +* of a transmit setup procedure if more than just the trigger select should be +* configured. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDataMoverSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param tollGateCfg contains the transport configuration setting structure +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxTollgateSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, adi_fpga9010_TxTollgateCfg_t *tollGateCfg); + +/** +* \brief Reads the configuration for a single tollgate module and populates the empty +* adi_fpga9010_TxTollgateCfg_t structure passed in to the function. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDataMoverSel an adi_fpga9010_FramerSel_e enum value selecting a single datamover +* \param tollGateCfg an empty structure that will be written with the selected tollgate's configuration values +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_INV_TX_DATA_MOVER_TOLLGATE_SETUP An invalid tx datamover selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxTollgateGet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e txDataMoverSel, adi_fpga9010_TxTollgateCfg_t *tollGateCfg); + +/** +* \brief This function writes the reset bit to the tollgate +* modules selected in the txDatamoverSelMask. The reset bit is not self-clearing +* so a full reset will require a call to this function to write a 1 then another +* call to write a 0 for normal operation. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDataMoverSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param resetVal the reset value (1 for reset; 0 for normal operation) +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_INV_TX_DATA_MOVER_TOLLGATE_SETUP An invalid tx datamover selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxTollgateResetSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, uint8_t resetVal); + +/** +* \brief This function reads the reset bit to the tollgate +* modules selected in the txDatamoverSelMask. It zeros the resetVal parameter +* and copies each module's reset value to the bit location given by the +* adi_fpga9010_FramerSel_e enum. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDataMoverSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param resetVal each corresponds to that datamover's tollgate reset bit +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_INV_TX_DATA_MOVER_TOLLGATE_SETUP An invalid tx datamover selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxTollgateResetGet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, uint8_t *resetVal); + + +/** +* \brief This function writes the adi_fpga9010_TxDmaCfg_t structure to the DMA +* modules selected in the txDatamoverSelMask. This function could be used as part +* of an transmit setup procedure. The LastDescriptor bitfield and RunStop bits +* are not written during this function call. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDataMoverSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param txDmaCfg is the number of samples to transmit +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_INV_TX_DATA_MOVER_DMA_SETUP An invalid tx datamover selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxDmaSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, adi_fpga9010_TxDmaCfg_t *txDmaCfg); + +/** +* \brief Reads the configuration for a single DMA module and populates the empty +* adi_fpga9010_TxDmaCfg_t structure passed in to the function. This function reads +* Read-Write & Read-Only bitfields, including status bits. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDataMoverSel anadi_fpga9010_FramerSel_e enum values +* \param dmaCfg Pointer to return the adi_fpga9010_TxDmaCfg_t data structure. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_INV_TX_DATA_MOVER_DMA_SETUP An invalid tx datamover selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxDmaGet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e txDataMoverSel, adi_fpga9010_TxDmaCfg_t *dmaCfg); + + +/** +* \brief writes the tramsmit mode for one or more Tx data movers +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDataMoverSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param txmode can be one of adi_fpga9010_TxDatamoverMode_e +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_INV_TX_DATA_MOVER_SETUP An invalid tx datamover selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +//int32_t adi_fpga9010_TxModeSetup(adi_fpga9010_Device_t *device, adi_fpga_TramsmitMode_t transmitMode); +int32_t adi_fpga9010_TxModeSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, adi_fpga9010_TxDatamoverMode_e txmode); + +/** +* \brief reads the tramsmit mode for all Tx data movers +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param transmitModeMask can be one of adi_fpga9010_TxDatamoverMode_e +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_INV_TX_DATA_MOVER_SETUP An invalid tx datamover selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxModeGet(adi_fpga9010_Device_t *device, uint8_t *transmitModeMask); + +/** +* \brief writes the trigger source for one or more Tx data movers +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDataMoverSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param triggerSelect can be a combination of adi_fpga_TrigSources_e +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* \retval ADI_FPGA9010_ACT_INV_TX_DATA_MOVER_TRIGGER An invalid trigger type selected +* +*/ +int32_t adi_fpga9010_TxTollgateTriggerSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, adi_fpga9010_TxTollgateTrigSources_e triggerSelect); + +/** +* \brief reads the trigger source for all Tx data movers +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDataMoverSel one of adi_fpga9010_FramerSel_e enum values +* \param triggerSelect can be a combination of adi_fpga_TrigSources_e +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* \retval ADI_FPGA9010_ACT_INV_TX_DATA_MOVER_TRIGGER An invalid trigger type selected +* +*/ +int32_t adi_fpga9010_TxTollgateTriggerGet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e txDataMoverSel, adi_fpga9010_TxTollgateTrigSources_e *triggerSelect); + +/** +* \brief Unimplemented +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDataMoverSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_INV_TX_DATA_MOVER_TRIGGER An invalid trigger type selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ + +int32_t adi_fpga9010_TxDatamoverEnableSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask); +/** +* \brief Unimplemented +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDataMoverSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxDatamoverEnableGet(adi_fpga9010_Device_t *device, uint32_t *txDataMoverSelMask); + +/** +* \brief Writes a 1 to the Capture Control modules Datapath Active bitfield. A capture will then occur +* based on the Tollgate trigger selections. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxDataStart(adi_fpga9010_Device_t *device); + +/** +* \brief Stops all enabled FPGA Tx data movers +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxDataStop(adi_fpga9010_Device_t *device); + +/** +* \brief Unimplemented +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDataMoverSel the selected datamover to write to +* \param data the user provided array of data to write to the fpga. +* \param dataSize the size of the data array. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_DATA_RX_MOVER_WAIT_TIMEOUT Timeout occurred during Rx transaction +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxDataSet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e txDataMoverSel, int32_t data[], uint32_t dataSize); + +/** +* \brief Unimplemented +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDataMoverSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param numSamples the number of samples to be written from memory to the part. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9010_ACT_DATA_RX_MOVER_WAIT_TIMEOUT Timeout occurred during Rx transaction +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxSamplesSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, uint32_t numSamples); + +/** +* \brief This function writes the reset bit to the dma +* modules selected in the txDatamoverSelMask. The reset bit is self-clearing +* so there is no need to clear after setting. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDatamoverSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param resetVal set to 1 to reset module +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxDmaResetSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, uint8_t reset); + +/** +* \brief This function writes the run-stop bit to the dma +* modules selected in the txDatamoverSelMask. This can be used during the middle of a transfer +* to gracefully halt the DMA. In this case the module must be halted after halting. +* More commonly used prior to a transmit to start the DMAs before +* triggering. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDatamoverSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param runStop set to 1 to begin transfer; 0 to halt transfer +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxDmaRunStopSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, uint8_t runStop); + +/** +* \brief This function writes the length bitfield to the dma +* modules selected in the txDatamoverSelMask. This should be done prior to performing a transmit. +* The length indicates the number of bytes the DMA will run for after triggering. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDatamoverSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param numBytes the number of bytes to transfer +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxDmaLengthSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, uint32_t numBytes); + +/** +* \brief This function will configure all the selected Datachains in the txDataMoverSelMask. +* A Datachain consists of the Capture Control, Tollgate, & DMA modules. The tollgate trigger +* is configured using adi_fpga9010_TxTollgateTriggerSet, +* the DMA is reset then configured using adi_fpga9010_TxDmaSet, +* the DMA is started by setting the run-stop bit using adi_fpga9010_TxDmaRunStopSet, +* and finally the token passing is initiated in the Capture Control module. This function +* is used in transmit sequences and is the final step before triggering. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDatamoverSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param triggerSelect Select from adi_fpga9010_TxTollgateTrigSources_e enum +* \param txDmaCfg contains the dma configuration settings to apply to all selected DMA modules +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxDataChainConfigure(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, adi_fpga9010_TxTollgateTrigSources_e triggerSelect, adi_fpga9010_TxDmaCfg_t *txDmaCfg); + +/** +* \brief This function clears and resets all Datachains to prepare for a new transmit or as part +* of a tear down routine. The Capture Controls are reset and deactivated, the DMAs are halted +* and will return errors if halted ungracefully, and the Tollgates are held in reset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxDataChainReset(adi_fpga9010_Device_t *device); + +/** +* \brief This function writes the static members of the adi_fpga9010_TxDmaCfg_t structure to the DMA +* modules selected in the txDatamoverSelMask. This function is used when the fpga +* boots up. The DMAs are not ready for transmit after this function. +* The LastDescriptor, RunStop, and Length bitfields are not written +* during this function call. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param txDatamoverSelMask an or'd combination of one or more adi_fpga9010_FramerSel_e enum values +* \param txDmaCfg contains the dma configuration settings to apply to all selected DMA modules +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_TxDmaInit(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, adi_fpga9010_TxDmaCfg_t *txDmaCfg); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_TX_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_tx_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_tx_types.h new file mode 100644 index 0000000..0a42044 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_tx_types.h @@ -0,0 +1,77 @@ +/*! +* \file adi_adrv9010_tx_types.h +* \brief Contains FPGA9010 tx enum and struct definitions +* +* ADRV9010 API Version: $ADI_FPGA9010_API_VERSION$ +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_TX_TYPES_H_ +#define _ADI_FPGA9010_TX_TYPES_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADI_FPGA9010_NUM_OF_TX_DATAMOVERS 2 + +typedef enum adi_fpga9010_TxDatamoverMode +{ + ADI_FPGA9010_TXMODE_SNGL = 0, + ADI_FPGA9010_TXMODE_CONT = 1 +} adi_fpga9010_TxDatamoverMode_e; + +/** +* \brief Enumerated list of fpga Tx Tollgata trigger sources +*/ +typedef enum adi_fpga9010_TxTollgateTrigSources +{ + ADI_FPGA9010_TX_IMM_TRIG = 0x1, /*!Immediate trigger. */ + ADI_FPGA9010_TX_EXT_TRIG = 0x2, /*!External Trigger external SMA. */ + ADI_FPGA9010_TX_TDD_SM = 0x4, /*!TDD State Machine. */ + ADI_FPGA9010_TX_ARM_ACK = 0x8 /*!GPIO. */ +} adi_fpga9010_TxTollgateTrigSources_e; + +/** +* \brief Data structure to hold the Fpga Data mover tollgate Configuration +*/ +typedef struct adi_fpga9010_TxTollgateCfg +{ + uint32_t tollGateEdgeOrLvl; /*!1 indicates that the trigger input is edge detected. 0 indicates that the trigger input is level sensitive. */ + uint32_t tollGateHiRiseOrLoFall; /*!1 indicates either high level or rising edge. 0 indicates either low level or falling edge. */ + uint8_t tollgateReset; /*!Set to 1 resets the Tollgate. Clear to 0 allows for normal operation.. */ + adi_fpga9010_TxTollgateTrigSources_e tollGateTrigSource; /*!Selects the trigger input that is used to open the Tollgate. multiple triggers Supported */ +} adi_fpga9010_TxTollgateCfg_t; + +/** +* \brief Data structure to hold the Fpga Data mover dma Configuration +*/ +typedef struct adi_fpga9010_TxDmaCfg +{ + uint8_t enableEnhancedMode; /*!When set to 1, the enhanced mode of the selected transfer is performed. When cleared to 0, the traditional mode of the selected transfer is performed. */ + uint8_t enableSg; /*!When set to 1, the DMA performs a scatter-gather transfer. When cleared to 0, the DMA performs a simple transfer. */ + uint32_t simpleStartAddr; /*!indicates the starting address in memory where the data should be written.*/ + uint32_t length; /*!Identifies the number of bytes to transfer in the simple mode and enhanced scatter-gather mode. */ + uint8_t validDataWidthStream; /*!This field indicates what the width of valid data is on the stream interface. This field is used to pack/unpack the data from the memory.*/ + uint32_t sgFirstDescriptor; /*!Contains the location of the first descriptor used in both scatter-gather modes. */ + uint32_t sgLastDescriptor; /*!Contains the location of the last descriptor used in both scatter-gather modes. */ + uint8_t runStop; /*! When set to 1, the DMA begins the transfer. When cleared to 0, any active transfer is gracefully halted. When halted, the module needs to be reset after the halt completes.*/ + uint8_t continuous; /*! When set to 1, the DMA will restart the transfer. When cleared to 0, the DMA performs one transfer and stops.*/ + uint8_t active; /*! When this bit is 1, the DMA is actively transferring data. Read-only */ + uint8_t complete; /*! When this bit is 1, the transfer has completed successfully. This bit will clear when run_stop is cleared to '0'. Read-only */ + uint8_t haltComplete; /*! When this bit is 1, the halt that was previously issued has completed. This module must be reset after a halt completes. Read-only */ + uint8_t underflow; /*! When this bit is 1, an overflow has occurred on the FIFO. This is a sticky bit. Write a 1 to this bit to clear it. Read-only */ +} adi_fpga9010_TxDmaCfg_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_TX_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_types.h new file mode 100644 index 0000000..2296832 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_types.h @@ -0,0 +1,135 @@ +/*! +* \file adi_fpga9010_types.h +* \brief Contains ADRV9010 API configuration and run-time type definitions +* +* ADRV9010 API Version: $ADI_FPGA9010_API_VERSION$ +* +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_TYPES_H_ +#define _ADI_FPGA9010_TYPES_H_ + + +#include +#include "adi_common.h" +#include "adi_fpga9010_tx_types.h" +#include "adi_fpga9010_rx_types.h" +#include "adi_fpga9010_jesd_types.h" +#include "adi_fpga9010_clk_types.h" +#include "adi_fpga9010_gpio_types.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADI_FPGA9010_MIN_VERSION 0x00000B +#define ADI_FPGA9010_JESD204B_DEVICEID 0xC9 +#define ADI_FPGA9010_JESD204C_DEVICEID 0xCA +#define ADI_FPGA9010_DRP_TIMEOUT_MS 200 + +typedef enum adi_fpga9010_PinDir +{ + ADI_FPGA9010_PIN_DIR_IN = 0, + ADI_FPGA9010_PIN_DIR_OUT = 1 +} adi_fpga9010_PinDir_e; + +/** +* \brief Data structure to hold digital clock settings +*/ +typedef struct adi_fpga9010_ClockSettings +{ + adi_fpga9010_MmcmCfg_t coreMmcm; + adi_fpga9010_QpllCfg_t qpll; +} adi_fpga9010_ClockSettings_t; + +typedef struct adi_fpga9010_SysRefClkCfg +{ + uint32_t internalSysRefGeneratorFrequency; /*!< The number of device clock cycles to generate internal SYSREF pulse */ + uint8_t internalSysrefEnable; /*!< Set this to 1 to enable internal SYSREF */ + uint8_t externalSysrefSampleEdge; /*!< Set this to 1 to sample external SYSREF on rising edge; 0 for falling edge */ + uint8_t externalSysrefPolarity; /*!< Set to 1 to invert external SYSREF polarity */ +} adi_fpga9010_SysRefClkCfg_t; + +typedef enum adi_fpga9010_DrpInterface +{ + ADI_FPGA9010_PHY_CH0, + ADI_FPGA9010_PHY_CH1, + ADI_FPGA9010_PHY_CH2, + ADI_FPGA9010_PHY_CH3, + ADI_FPGA9010_PHY_CH4, + ADI_FPGA9010_PHY_CH5, + ADI_FPGA9010_PHY_CH6, + ADI_FPGA9010_PHY_CH7, + ADI_FPGA9010_PHY_QUAD0, + ADI_FPGA9010_PHY_QUAD1 +} adi_fpga9010_DrpInterface_e; + +/** +* \brief The data path includes the serializer/deserializer, framers/deframers, transport, tollgate and DMA +*/ +typedef struct adi_fpga9010_DatapathCfg +{ + adi_fpga9010_SerializerCfg_t serializerCfg[ADI_FPGA9010_NUM_LANES]; /*!< Holds configuration for the tx GTH serializer 1..8 */ + adi_fpga9010_DeserializerCfg_t deserializerCfg[ADI_FPGA9010_NUM_LANES]; /*!< Holds configuration for the rx GTH deserializer 1..8 */ + adi_fpga9010_FramerCfg_t framerCfg[ADI_FPGA9010_NUM_OF_FRAMERS]; /*!< Holds configuration for the tx framers 1,2 */ + adi_fpga9010_DeframerCfg_t deframerCfg[ADI_FPGA9010_NUM_OF_DEFRAMERS]; /*!< Holds configuration for the Rx deframers 1,2,3 */ + adi_fpga9010_RxDmaCfg_t rxDmaCfg[ADI_FPGA9010_NUM_OF_DEFRAMERS]; /*!< Holds configuration for the rx digital data paths 1..16 */ + adi_fpga9010_TxDmaCfg_t txDmaCfg[ADI_FPGA9010_NUM_OF_FRAMERS]; /*!< Holds configuration for the tx digital data paths 1..8*/ + adi_fpga9010_RxTollgateCfg_t rxTollgateCfg; /*!< Holds configuration for the 16 rx tollgates all are configured identically*/ + adi_fpga9010_TxTollgateCfg_t txTollgateCfg; /*!< Holds configuration for the 8 tx tollgates all are configured identically*/ + uint32_t rxDatamoverMask; /*! Logical or of the datamover enums to be configured */ + uint32_t txDatamoverMask; /*! Logical or of the datamover enums to be configured */ + uint8_t syncBSel[ADI_FPGA9010_NUM_OF_DEFRAMERS + ADI_FPGA9010_NUM_OF_FRAMERS]; /*! The location in the array corresponds to sync xbar output. Values determine which input is used for that output */ + uint8_t syncBPolarity; /*! The polarity for the sync xbar polarity. Each bit corresponds to a single input */ + uint8_t pcbSerLaneSwap[ADI_FPGA9010_NUM_LANES]; /*!< Indices correspond to serializer lane numbers. Values are lane number after applying PCB swap */ + uint8_t pcbDesLaneSwap[ADI_FPGA9010_NUM_LANES]; /*!< Indices correspond to deserializer lane numbers. Values are lane number after applying PCB swap */ +} adi_fpga9010_DatapathCfg_t; + +/** +* \brief Data structure to hold ADRV9010 device instance initialization settings +*/ +typedef struct adi_fpga9010_Init +{ + adi_fpga9010_ClockSettings_t clocks; /*!< Holds settings for CLKPLL and reference clock */ + adi_fpga9010_DatapathCfg_t datapath; /*!< Holds the Datapath / JESD204B/C data link and digital datapath settings */ + adi_fpga9010_SysRefClkCfg_t sysref; /*!< Holds the data for the external or internal Sysref */ +} adi_fpga9010_Init_t; + +typedef struct adi_fpga9010_Info +{ + uint8_t designId; /*!< FPGA9010 design ID read during FPGA9010_initialize */ + uint16_t versionMinor; /*!< FPGA9010 minor version read during FPGA9010_initialize */ + uint8_t versionMajor; /*!< FPGA9010 major version read during FPGA9010_initialize */ + uint32_t swTest; /*!< Software testmode signal */ + uint32_t tddStateMachineClk_kHz; /*!< Frequency the TDD state machine is set to. Default is fastest lane rate / 40 */ + + uint32_t linkLayerDataWidth; /*!< 40 (bits per lane) for JESD204B; 66 for JESD204C */ + uint32_t encodingLowValue; /*!< 8 (from 8b10b) for JESD204B; 64 for JESD204C */ + uint32_t encodingHighValue; /*!< 10 (from 8b10b) for JESD204B; 66 for JESD204C */ + uint32_t dmaDataWidth; /*!< Num of bits per word written to RAM from DMA: 32 bits for JESD204B; 64 bits for JESD204C */ + + adi_fpga9010_GpioModes_e gpioPinMode[ADI_FPGA9010_GPIO_PINS]; /*!< The current mode each GPIO pin is assigned */ +} adi_fpga9010_Info_t; + +/** +* \brief Data structure to hold FPGA9010 device instance settings +*/ +typedef struct adi_fpga9010_Device +{ + adi_common_Device_t common; /*!< Common layer structure */ + adi_fpga9010_Info_t devStateInfo; /*!< ADRV9010 run time state information container */ + uint32_t memoryPageSize; /*!< The current page size used when reading/writing RAM */ +} adi_fpga9010_Device_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_user.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_user.h new file mode 100644 index 0000000..b14872f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_user.h @@ -0,0 +1,44 @@ +/** +* \file adi_fpga9010_user.h +* \brief Contains top level fpga9010 related function prototypes for +* adi_fpga9010.c +* +* FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_USER_H_ +#define _ADI_FPGA9010_USER_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + ***************************************** + * FPGA Interface Macros + ****************************************** + */ + +#ifndef ADI_FPGA9010_VERBOSE + #define ADI_FPGA9010_VERBOSE 1 /*Use strings 0 not use, 1 use */ +#endif /* !ADI_FPGA9010_VERBOSE */ + +#ifndef ADI_FPGA9010_VARIABLE_USAGE +#define ADI_FPGA9010_VARIABLE_USAGE 1 /*Use strings 0 not use, 1 use */ +#endif /* !ADI_FPGA9010_VARIABLE_USAGE */ + +#ifndef ADI_FPGA9010_LOGGING +#define ADI_FPGA9010_LOGGING 0x7F /*LogLevel Set to API, Messages, Warnings, Error*/ +#endif /* !ADI_FPGA9010_LOGGING */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_USER_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_utilities.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_utilities.h new file mode 100644 index 0000000..8242467 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_utilities.h @@ -0,0 +1,121 @@ +/** +* \file adi_fpga9010_utilities.h +* \brief Contains top level fpga9010 related function prototypes for +* adi_fpga9010_utilities.c +* +* FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_UTILITIES_H_ +#define _ADI_FPGA9010_UTILITIES_H_ + +#include "adi_fpga9010_types.h" +#include "adi_fpga9010_utilities_types.h" +#include "adi_common_log.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Platform FPGA command to calculate the FPGA SERDES QPLL settings +* +* \dep_begin +* \dep{device} +* \dep{divisors} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param refClk_kHz The input clock rate in kHz +* \param fastestLaneRate_kHz The fastest lane rate in kHz +* \param qplls A pointer to a QPLL configuration structure +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_CalculateQpllSettings(adi_fpga9010_Device_t *device, const uint32_t refClk_kHz, const uint32_t fastestLaneRate_kHz, adi_fpga9010_QpllCfg_t *qplls); + +/** +* \brief Platform FPGA helper function to setup the QPLL lane rate divisors +* +* \dep_begin +* \dep{device} +* \dep{divisors} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param qpllVcoFreq_kHz Output of the QPLL in kHz +* \param desiredLaneRate_kHz desired lane rate in kHz +* \param dVal divisors value +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_CalculateQpllDivisor(adi_fpga9010_Device_t *device, uint32_t qpllVcoFreq_kHz, const uint32_t desiredLaneRate_kHz, uint8_t *dVal); + +/** +* \brief Platform FPGA command calculate the Mmcm settings +* +* FPGA implementation constraint: RX MMCM Channel 6 is the refClk for TX MMCM. This means +* RX MMCM channel 6 output frequency must be set to refClk and RX MMCM must be configured +* and locked prior to the TX MMCM +* +* \dep_begin +* \dep{device} +* \dep{mmcmConfig->clkFreq_kHz} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param refClk_kHz The input clock rate in kHz +* \param mmcmConfig Pointer to the adi_fpga9010_MmcmCfg_t data structure +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_CalculateMmcmSettings(adi_fpga9010_Device_t *device, const uint32_t refClk_kHz, adi_fpga9010_MmcmCfg_t *mmcmConfig); + +/** +* \brief Platform FPGA command calculate the Mmcm settings +* +* Fills the given init structure with values whyich should cover the majority of use cases. +* The values are based on a few essential values given by the fpgaCfg structure +* +* \dep_begin +* \dep{device} +* \dep{mmcmConfig->clkFreq_kHz} +* \dep_end +* +* \param device Pointer to the FPGA9010 device data structure. +* \param fpgaCfg contains the essential values in order to configure the fpga +* \param fpgaInit the resulting structure which can be modified if required or +* passed to adi_fpga9010_Initialize to initialise the part +* +* \retval ADI_FPGA9010_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9010_InitConfig(adi_fpga9010_Device_t *device, adi_fpga9010_SetupFpgaCfg_t *fpgaCfg, adi_fpga9010_Init_t *fpgaInit); + +int32_t adi_fpga9010_FpgaConfigurationPrint(adi_fpga9010_Device_t *device); + +int32_t adi_fpga9010_FpgaDatapathCfgPrint(adi_fpga9010_Device_t *device); + + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_UTILITIES_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_utilities_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_utilities_types.h new file mode 100644 index 0000000..9ff20db --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/include/adi_fpga9010_utilities_types.h @@ -0,0 +1,68 @@ +/*! +* \file adi_adrv9010_utilities_types.h +* \brief Contains FPGA9010 utilities enum and struct definitions +* +* ADRV9010 API Version: $ADI_FPGA9010_API_VERSION$ +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9010_UTILITIES_TYPES_H_ +#define _ADI_FPGA9010_UTILITIES_TYPES_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct adi_fpga9010_DesLaneXbar +{ + uint8_t lane0FramerOutSel; /*!< Framer output to route to Physical Lane 0 (valid 0-7) */ + uint8_t lane1FramerOutSel; /*!< Framer output to route to Physical Lane 1 (valid 0-7) */ + uint8_t lane2FramerOutSel; /*!< Framer output to route to Physical Lane 2 (valid 0-7) */ + uint8_t lane3FramerOutSel; /*!< Framer output to route to Physical Lane 3 (valid 0-7) */ + uint8_t lane4FramerOutSel; /*!< Framer output to route to Physical Lane 4 (valid 0-7) */ + uint8_t lane5FramerOutSel; /*!< Framer output to route to Physical Lane 5 (valid 0-7) */ + uint8_t lane6FramerOutSel; /*!< Framer output to route to Physical Lane 6 (valid 0-7) */ + uint8_t lane7FramerOutSel; /*!< Framer output to route to Physical Lane 7 (valid 0-7) */ +} adi_fpga9010_DesLaneXbar_t; + +typedef struct adi_fpga9010_DataLinkCfg +{ + uint32_t iqRate_kHz; + uint8_t jesd204M; + uint8_t lanesEnabled; + uint16_t jesd204K; + uint8_t scramble; + uint8_t jesd204S; + uint8_t jesd204Np; + uint8_t jesd204E; + uint16_t datamoversUsed; + uint8_t deviceId; + adi_fpga9010_DesLaneXbar_t serializerLaneCrossbar; /*!< Lane crossbar to map framer lane outputs to physical lanes */ +} adi_fpga9010_DataLinkCfg_t; + +typedef struct adi_fpga9010_SetupFpgaCfg +{ + uint32_t deviceClk_kHz; + adi_fpga9010_DataLinkCfg_t deframerlink0; // Rx + adi_fpga9010_DataLinkCfg_t deframerlink1; // ORx + adi_fpga9010_DataLinkCfg_t deframerlink2; // Not in FPGA at the moment + + adi_fpga9010_DataLinkCfg_t framerlink0; // Tx + adi_fpga9010_DataLinkCfg_t framerlink1; // Not in FPGA at the moment + uint8_t realIf; +} adi_fpga9010_SetupFpgaCfg_t; + + + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9010_UTILITIES_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010.c new file mode 100644 index 0000000..f51d274 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010.c @@ -0,0 +1,1231 @@ + +/*! +* \file adi_fpga9010.c +* \brief Contains FPGA9010 API configuration and run-time type definitions +* +* ADRV9010 API Version: 6.4.0.14 +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + * + */ + +#include "adi_fpga9010_user.h" +#include "adi_fpga9010.h" +#include "adi_fpga9010_error.h" +#include "../../private/include/fpga9010_bf_axi_tokelau.h" +#include "../../private/include/fpga9010_bf_jesd204_phy_tokelau_ads8.h" +#include "../../private/include/fpga9010_bf_dp_capture_control.h" +#include "../../private/include/fpga9010_bf_jesd204_rx_lane_xbar.h" +#include "../../private/include/fpga9010_bf_jesd204_tx_lane_xbar.h" +#include "../../private/include/fpga9010_bf_xilinx_jesd204b.h" +#include "../../private/include/fpga9010_bf_xilinx_jesd204b.h" + +#include "adi_fpga9010_jesd.h" +#include "adi_fpga9010_rx.h" +#include "adi_fpga9010_tx.h" +#include "adi_fpga9010_clk.h" +#include "adi_fpga9010_utilities.h" +#include "adi_fpga9010_hal.h" +#include "adi_fpga9010_tdd.h" + +//kluge +#include "adi_platform.h" + +int32_t adi_fpga9010_HwOpen(adi_fpga9010_Device_t *device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + adi_common_LogLevelSet(&device->common, ADI_FPGA9010_LOGGING); + if (device->common.error.errCode != ADI_COMMON_HAL_OK) + { + switch (device->common.error.errCode) + { + case ADI_COMMON_HAL_LOGGING_FAIL: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + device->common.error.errCode, + ADI_COMMON_ACT_WARN_RESET_LOG, + NULL, + "Logging error"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_COMMON_HAL_LOGGGING_LEVEL_FAIL: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + device->common.error.errCode, + ADI_COMMON_ACT_WARN_RESET_LOG, + NULL, + "Logging Level error"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_COMMON_HAL_GEN_SW: /* fall through */ + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Param error"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + } + + adi_common_hal_HwOpen(&device->common); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Param error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_HwClose(adi_fpga9010_Device_t *device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + + //LOG_FUNCTION_ENTRY_REPORT(ADI_COMMON_LOG_API); + + recoveryAction = adi_common_hal_HwClose(&device->common); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Param error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_VersionRead(adi_fpga9010_Device_t *device) +{ + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + fpga9010_AxiTokelauDesignIdBfGet(device, FPGA9010_BF_AXI_TOKELAU, &device->devStateInfo.designId); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_AxiTokelauVersionMajorBfGet(device, FPGA9010_BF_AXI_TOKELAU, &device->devStateInfo.versionMajor); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_AxiTokelauVersionMinorBfGet(device, FPGA9010_BF_AXI_TOKELAU, &device->devStateInfo.versionMinor); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RefClockFreqRead(adi_fpga9010_Device_t *device, uint32_t *detectedRefClock_kHz) +{ + UNUSED_PARA(detectedRefClock_kHz); + //TODO: implement this + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + return (device->common.error.newAction); +} + + +int32_t adi_fpga9010_RegisterReset(adi_fpga9010_Device_t *device) +{ + //TODO: implement this + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + return (device->common.error.newAction); +} + + +int32_t adi_fpga9010_IpReset(adi_fpga9010_Device_t *device, uint32_t IpToResetMask) +{ + UNUSED_PARA(IpToResetMask); + //TODO: implement this + //normally use a int32_t as a mask for this but there are likely to be too many for a uint64_t so use struct + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_DrpRead(adi_fpga9010_Device_t *device, adi_fpga9010_DrpAddress_e addr, uint8_t drp, uint16_t *rdWord, adi_fpga9010_DrpMask_e rdMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t i = 0; + uint8_t drpReady = 0; + uint8_t drpError = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + switch (drp) + { + case ADI_FPGA9010_PHY_CH0: + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + case ADI_FPGA9010_PHY_CH1: + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + case ADI_FPGA9010_PHY_CH2: + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + case ADI_FPGA9010_PHY_CH3: + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + case ADI_FPGA9010_PHY_CH4: + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + case ADI_FPGA9010_PHY_CH5: + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + case ADI_FPGA9010_PHY_CH6: + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + case ADI_FPGA9010_PHY_CH7: + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + case ADI_FPGA9010_PHY_QUAD0: + + /*Write address, clear write_enable bit then set enable bit*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad0DrpAddressBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (uint16_t)addr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, addr, "Invalid DRP addr"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteEnableBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to DRP write enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad0DrpEnableBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error enabling DRP transaction"); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_FPGA9010_DRP_TIMEOUT_MS; i++) + { + /* kluge to get drp read functionality working. after fpga has been updated to prevent the entire drp_read_data + * register from clearing when reading just the drp_ready bit remove this code and uncomment out the bf function below + */ + uint32_t debugData = 0; + adi_hal_BbicRegisterRead(device->common.devHalInfo, 0x4340094c, &debugData); + + drpReady = (debugData >> 16) & 0x1; + *rdWord = debugData & 0xFFFF; + //fpga9010_Jesd204PhyTokelauAds8Quad0DrpReadyBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &drpReady); + //ADI_ERROR_RETURN(device->common.error.newAction); + + if (drpReady) + { + break; + } + else + { + //todo: platform wait 1ms + } + } + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad0DrpErrorBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &drpError); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading DRP error bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((drpReady == 0) || (drpError == 1)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_DRP_ERROR, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Quad DRP error: requires full reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* kluged- see comment above */ + //fpga9010_Jesd204PhyTokelauAds8Quad0DrpReadDataBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, rdWord); + //ADI_ERROR_RETURN(device->common.error.newAction); + *rdWord = *rdWord & (uint16_t)rdMask; + } + + break; + + case ADI_FPGA9010_PHY_QUAD1: + + /*Write address, clear write_enable bit then set enable bit*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad1DrpAddressBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (uint16_t)addr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, addr, "Invalid DRP addr"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteEnableBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to DRP write enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad1DrpEnableBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error enabling DRP transaction"); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_FPGA9010_DRP_TIMEOUT_MS; i++) + { + /* kluge to get drp read functionality working. after fpga has been updated to prevent the entire drp_read_data + * register from clearing when reading just the drp_ready bit remove this code and uncomment out the bf function below + */ + uint32_t debugData = 0; + adi_hal_BbicRegisterRead(device->common.devHalInfo, 0x43400a4c, &debugData); + drpReady = (debugData >> 16) & 0x1; + *rdWord = debugData & 0xFFFF; + //fpga9010_Jesd204PhyTokelauAds8Quad1DrpReadyBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &drpReady); + //ADI_ERROR_RETURN(device->common.error.newAction); + + if (drpReady) + { + break; + } + else + { + //todo: platform wait 1ms + } + } + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad1DrpErrorBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &drpError); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading DRP error bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((drpReady == 0) || (drpError == 1)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_DRP_ERROR, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Quad DRP error: requires full reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* kluged- see comment above */ + //fpga9010_Jesd204PhyTokelauAds8Quad1DrpReadDataBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, rdWord); + //ADI_ERROR_RETURN(device->common.error.newAction); + *rdWord = *rdWord & (uint16_t)rdMask; + } + + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Invalid DRP selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_DrpWrite(adi_fpga9010_Device_t *device, adi_fpga9010_DrpAddress_e addr, uint8_t drp, uint16_t wrWord, adi_fpga9010_DrpMask_e wrMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t i = 0; + uint8_t drpReady = 0; + uint8_t drpError = 0; + + typedef struct { + int32_t(*DrpWriteDataBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint16_t); + int32_t(*DrpWriteDataMaskBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint16_t); + int32_t(*DrpAddressBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint16_t); + int32_t(*DrpWriteEnableBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + int32_t(*DrpEnableBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + int32_t(*DrpReadyBfGet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + int32_t(*DrpErrorBfGet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + } fpgaDrpWriteBf_t; + + fpgaDrpWriteBf_t fpgaDrpWriteFct[] = { + { + .DrpWriteDataBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0DrpEnableBfSet, + .DrpReadyBfGet = fpga9010_Jesd204PhyTokelauAds8Channel0DrpReadyBfGet, + .DrpErrorBfGet = fpga9010_Jesd204PhyTokelauAds8Channel0DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1DrpEnableBfSet, + .DrpReadyBfGet = fpga9010_Jesd204PhyTokelauAds8Channel1DrpReadyBfGet, + .DrpErrorBfGet = fpga9010_Jesd204PhyTokelauAds8Channel1DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2DrpEnableBfSet, + .DrpReadyBfGet = fpga9010_Jesd204PhyTokelauAds8Channel2DrpReadyBfGet, + .DrpErrorBfGet = fpga9010_Jesd204PhyTokelauAds8Channel2DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3DrpEnableBfSet, + .DrpReadyBfGet = fpga9010_Jesd204PhyTokelauAds8Channel3DrpReadyBfGet, + .DrpErrorBfGet = fpga9010_Jesd204PhyTokelauAds8Channel3DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4DrpEnableBfSet, + .DrpReadyBfGet = fpga9010_Jesd204PhyTokelauAds8Channel4DrpReadyBfGet, + .DrpErrorBfGet = fpga9010_Jesd204PhyTokelauAds8Channel4DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5DrpEnableBfSet, + .DrpReadyBfGet = fpga9010_Jesd204PhyTokelauAds8Channel5DrpReadyBfGet, + .DrpErrorBfGet = fpga9010_Jesd204PhyTokelauAds8Channel5DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6DrpEnableBfSet, + .DrpReadyBfGet = fpga9010_Jesd204PhyTokelauAds8Channel6DrpReadyBfGet, + .DrpErrorBfGet = fpga9010_Jesd204PhyTokelauAds8Channel6DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7DrpEnableBfSet, + .DrpReadyBfGet = fpga9010_Jesd204PhyTokelauAds8Channel7DrpReadyBfGet, + .DrpErrorBfGet = fpga9010_Jesd204PhyTokelauAds8Channel7DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9010_Jesd204PhyTokelauAds8Quad0DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Quad0DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Quad0DrpEnableBfSet, + .DrpReadyBfGet = fpga9010_Jesd204PhyTokelauAds8Quad0DrpReadyBfGet, + .DrpErrorBfGet = fpga9010_Jesd204PhyTokelauAds8Quad0DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9010_Jesd204PhyTokelauAds8Quad1DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Quad1DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Quad1DrpEnableBfSet, + .DrpReadyBfGet = fpga9010_Jesd204PhyTokelauAds8Quad1DrpReadyBfGet, + .DrpErrorBfGet = fpga9010_Jesd204PhyTokelauAds8Quad1DrpErrorBfGet + } + }; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (drp > ADI_FPGA9010_PHY_QUAD1) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Invalid DRP selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Write data bitfields */ + if (fpgaDrpWriteFct[drp].DrpWriteDataBfSet != NULL) + { + recoveryAction = fpgaDrpWriteFct[drp].DrpWriteDataBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, wrWord); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, wrWord, "Invalid DRP data word"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Write mask bitfields */ + if (fpgaDrpWriteFct[drp].DrpWriteDataMaskBfSet != NULL) + { + recoveryAction = fpgaDrpWriteFct[drp].DrpWriteDataMaskBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (uint16_t)wrMask); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, wrMask, "Invalid DRP data mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Write address */ + if (fpgaDrpWriteFct[drp].DrpAddressBfSet != NULL) + { + recoveryAction = fpgaDrpWriteFct[drp].DrpAddressBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (uint16_t)addr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, addr, "Invalid DRP addr"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Write enable bit */ + if (fpgaDrpWriteFct[drp].DrpWriteEnableBfSet != NULL) + { + recoveryAction = fpgaDrpWriteFct[drp].DrpWriteEnableBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to DRP write enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Set enable bit */ + if (fpgaDrpWriteFct[drp].DrpEnableBfSet != NULL) + { + recoveryAction = fpgaDrpWriteFct[drp].DrpEnableBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error enabling DRP transaction"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Looping and wait for channel ready */ + drpReady = 0; + for (i = 0; i < ADI_FPGA9010_DRP_TIMEOUT_MS; i++) + { + if (fpgaDrpWriteFct[drp].DrpReadyBfGet != NULL) + { + recoveryAction = fpgaDrpWriteFct[drp].DrpReadyBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &drpReady); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading DRP ready bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (drpReady) + { + break; + } + else + { + adi_common_hal_Wait_ms(&device->common, 1); + } + } + + drpError = 0; + if (fpgaDrpWriteFct[drp].DrpErrorBfGet != NULL) + { + recoveryAction = fpgaDrpWriteFct[drp].DrpErrorBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &drpError); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading DRP error bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* If not ready or error occurred then report error. */ + if ((drpReady == 0) || (drpError == 1)) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_DRP_ERROR, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Quad DRP error: requires full reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_InitSet(adi_fpga9010_Device_t *device, adi_fpga9010_Init_t *initSettings) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t i = 0; + uint8_t helperMask8bit = 0; + uint8_t deserializerChannelMask = 0; + uint8_t serializerChannelMask = 0; + uint8_t lockBit = 0; + uint8_t resetDone = 0; + uint32_t deframer0LaneXbarReset = 0; + uint32_t deframer1LaneXbarReset = 0; + uint32_t deframer2LaneXbarReset = 0; + uint32_t framer0LaneXbarReset = 0; + uint32_t framer1LaneXbarReset = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, initSettings); + + /* reset lane xbars. Do this first to prevent any deframer settings from affecting the PHY */ + recoveryAction = fpga9010_Jesd204RxLaneXbarLaneResetBfSet(device, FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0, 0xFFFFFFFF); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting Rx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_Jesd204RxLaneXbarLaneResetBfSet(device, FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1, 0xFFFFFFFF); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting Rx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_Jesd204RxLaneXbarLaneResetBfSet(device, FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2, 0xFFFFFFFF); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting Rx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_Jesd204TxLaneXbarLaneResetBfSet(device, FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0, 0xFFFFFFFF); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting Tx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_Jesd204TxLaneXbarLaneResetBfSet(device, FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1, 0xFFFFFFFF); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting Tx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*************************************************************************************************************************************** + * Physical layer + ***************************************************************************************************************************************/ + /* Place all PHY channels in reset */ + adi_fpga9010_DeserializerResetSet(device, 0xFF, 1); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9010_SerializerResetSet(device, 0xFF, 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* qpll setup */ + adi_fpga9010_QpllSet(device, initSettings->clocks.qpll.quadSelect, &initSettings->clocks.qpll); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* serializer/deserializer channel setup */ + for (i = 0; i < ADI_FPGA9010_NUM_LANES; i++) + { + helperMask8bit = (0x01 << i); + if (initSettings->datapath.serializerCfg[i].powerDown == 0) + { + adi_fpga9010_SerializerCfgSet(device, helperMask8bit, &initSettings->datapath.serializerCfg[i]); + ADI_ERROR_RETURN(device->common.error.newAction); + serializerChannelMask |= (0x01 << i); + } + if (initSettings->datapath.deserializerCfg[i].powerDown == 0) + { + adi_fpga9010_DeserializerCfgSet(device, helperMask8bit, &initSettings->datapath.deserializerCfg[i]); + ADI_ERROR_RETURN(device->common.error.newAction); + deserializerChannelMask |= (0x01 << i); + } + } + + /* release the desired channels from reset based on the power down bits */ + adi_fpga9010_DeserializerResetSet(device, deserializerChannelMask, 0); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9010_SerializerResetSet(device, serializerChannelMask, 0); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* check for qpll locks */ + if ((initSettings->clocks.qpll.quadSelect & ADI_FPGA9010_QPLL_QUAD0) > 0) + { + lockBit = 0; + adi_fpga9010_QpllLockGet(device, ADI_FPGA9010_QPLL_QUAD0, initSettings->clocks.qpll.band, &lockBit); + if (lockBit != 1) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_RESET_INTERFACE, ADI_FPGA9010_QPLLCLK0, "Error Quad0 Qpll not locked"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + if ((initSettings->clocks.qpll.quadSelect & ADI_FPGA9010_QPLL_QUAD1) > 0) + { + lockBit = 0; + adi_fpga9010_QpllLockGet(device, ADI_FPGA9010_QPLL_QUAD1, initSettings->clocks.qpll.band, &lockBit); + if (lockBit != 1) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_RESET_INTERFACE, ADI_FPGA9010_QPLLCLK1, "Error Quad1 Qpll not locked"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* check PHY layer has finished reset routine */ + adi_fpga9010_DeserializerResetDoneGet(device, &resetDone); + ADI_ERROR_RETURN(device->common.error.newAction); + if (resetDone != deserializerChannelMask) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_RESET_INTERFACE, NULL, "Deserializer channels have not reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + adi_fpga9010_SerializerResetDoneGet(device, &resetDone); + ADI_ERROR_RETURN(device->common.error.newAction); + if (resetDone != serializerChannelMask) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_RESET_INTERFACE, NULL, "Serializer channels have not reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*************************************************************************************************************************************** + * MMCM + ***************************************************************************************************************************************/ + /* Disable TDD FSM before calling MmcmSet */ + recoveryAction = adi_fpga9010_TddDisable(device); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_API_FAIL, recoveryAction, NULL, "Error disabling TDD during FPGA init"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* RX must be setup prior to TX since the final output of RX feeds TX mmcm*/ + recoveryAction = adi_fpga9010_MmcmSet(device, ADI_FPGA9010_CORE_MMCM, &initSettings->clocks.coreMmcm); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, initSettings->clocks.coreMmcm, "Error setting up Core MMCM"); + ADI_ERROR_RETURN(device->common.error.newAction); + + lockBit = 0; + adi_fpga9010_MmcmLockGet(device, ADI_FPGA9010_CORE_MMCM, &lockBit); + if (lockBit != 1) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_RESET_INTERFACE, ADI_FPGA9010_CORE_MMCM, "Error Core MMCM not locked"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*************************************************************************************************************************************** + * Lane Xbars + ***************************************************************************************************************************************/ + + /* build up the link layer's lane xbar resets based on which phy lanes they're using */ + /* can't use dserializerChannelMask here because we need to reset based on which channels go to which + * link layer. the dserializerChannelMask shows us all the channels that are active, not how they map onto the link layers */ + for (i = 0; i < ADI_FPGA9010_NUM_LANES; i++) + { + /* The reset bit location maps to the PHY lane # for tx & rx. */ + /* For rx, the value in the laneXBar array is used to + * determine the PHY lane #*/ + if (((initSettings->datapath.deframerCfg[0].lanesInUse >> i) & 0x01) == 0x01) + { + deframer0LaneXbarReset |= (0x01 << initSettings->datapath.deframerCfg[0].laneXbar[i]); + } + + if (((initSettings->datapath.deframerCfg[1].lanesInUse >> i) & 0x01) == 0x01) + { + deframer1LaneXbarReset |= (0x01 << initSettings->datapath.deframerCfg[1].laneXbar[i]); + } + + if (((initSettings->datapath.deframerCfg[2].lanesInUse >> i) & 0x01) == 0x01) + { + deframer2LaneXbarReset |= (0x01 << initSettings->datapath.deframerCfg[2].laneXbar[i]); + } + + /* For tx, the index of the laneXBar maps to the PHY lane #. + * If the laneXBar value is not the initial value (0x1F) that means this index corresponds to a PHY lane + * connected to this framer */ + if (initSettings->datapath.framerCfg[0].laneXbar[i] != 0x1F) + { + framer0LaneXbarReset |= (0x01 << i); + } + if (initSettings->datapath.framerCfg[1].laneXbar[i] != 0x1F) + { + framer1LaneXbarReset |= (0x01 << i); + } + } + + deframer0LaneXbarReset = ~deframer0LaneXbarReset; + deframer1LaneXbarReset = ~deframer1LaneXbarReset; + deframer2LaneXbarReset = ~deframer2LaneXbarReset; + framer0LaneXbarReset = ~framer0LaneXbarReset; + framer1LaneXbarReset = ~framer1LaneXbarReset; + + /* Remove the reset on the lanes in use in lane xbars */ + recoveryAction = fpga9010_Jesd204RxLaneXbarLaneResetBfSet(device, FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0, deframer0LaneXbarReset); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting Rx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_Jesd204RxLaneXbarLaneResetBfSet(device, FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1, deframer1LaneXbarReset); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting Rx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_Jesd204RxLaneXbarLaneResetBfSet(device, FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2, deframer2LaneXbarReset); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting Rx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_Jesd204TxLaneXbarLaneResetBfSet(device, FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0, framer0LaneXbarReset); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting Tx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_Jesd204TxLaneXbarLaneResetBfSet(device, FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1, framer1LaneXbarReset); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting Tx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*************************************************************************************************************************************** + * Link layer + ***************************************************************************************************************************************/ + /* Disable all framers/deframers */ + adi_fpga9010_DeframerDisable(device, ADI_FPGA9010_DEFRAMER_ALL); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_FramerDisable(device, ADI_FPGA9010_FRAMER_ALL); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* deframers & framers setup (only configure those that are in use) */ + if (initSettings->datapath.deframerCfg[0].lanesInUse != 0) + { + adi_fpga9010_DeframerCfgSet(device, ADI_FPGA9010_DEFRAMER_0, &initSettings->datapath.deframerCfg[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Hold unused deframer in reset (reset bit in FPGA is read by PerformTx to know if link is used) */ + recoveryAction = fpga9010_XilinxJesd204bResetFixedBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_0, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error holding used FPGA deframer0 in reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (initSettings->datapath.deframerCfg[1].lanesInUse != 0) + { + adi_fpga9010_DeframerCfgSet(device, ADI_FPGA9010_DEFRAMER_1, &initSettings->datapath.deframerCfg[1]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Hold unused deframer in reset (reset bit in FPGA is read by PerformTx to know if link is used) */ + recoveryAction = fpga9010_XilinxJesd204bResetFixedBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_1, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error holding used FPGA deframer1 in reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (initSettings->datapath.deframerCfg[2].lanesInUse != 0) + { + adi_fpga9010_DeframerCfgSet(device, ADI_FPGA9010_DEFRAMER_2, &initSettings->datapath.deframerCfg[2]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Hold unused deframer in reset (reset bit in FPGA is read by PerformTx to know if link is used) */ + recoveryAction = fpga9010_XilinxJesd204bResetFixedBfSet(device, FPGA9010_BF_JESD204B_DEFRAMER_2, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error holding used FPGA deframer2 in reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (initSettings->datapath.framerCfg[0].lanesInUse != 0) + { + adi_fpga9010_FramerCfgSet(device, ADI_FPGA9010_FRAMER_0, &initSettings->datapath.framerCfg[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Hold unused deframer in reset (reset bit in FPGA is read by PerformTx to know if link is used) */ + recoveryAction = fpga9010_XilinxJesd204bResetFixedBfSet(device, FPGA9010_BF_JESD204B_FRAMER_0, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error holding used FPGA framer0 in reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (initSettings->datapath.framerCfg[1].lanesInUse != 0) + { + adi_fpga9010_FramerCfgSet(device, ADI_FPGA9010_FRAMER_1, &initSettings->datapath.framerCfg[1]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Hold unused deframer in reset (reset bit in FPGA is read by PerformTx to know if link is used) */ + recoveryAction = fpga9010_XilinxJesd204bResetFixedBfSet(device, FPGA9010_BF_JESD204B_FRAMER_1, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error holding used FPGA framer1 in reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*************************************************************************************************************************************** + * Sync XBar + ***************************************************************************************************************************************/ + adi_fpga9010_SyncXBarCfgSet(device, initSettings->datapath.syncBPolarity, &initSettings->datapath.syncBSel[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*************************************************************************************************************************************** + * Sysref + ***************************************************************************************************************************************/ + adi_fpga9010_SysRefControlSet(device, &initSettings->sysref); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*************************************************************************************************************************************** + * Set the static information in DMAs + ***************************************************************************************************************************************/ + adi_fpga9010_RxDmaInit(device, ADI_FPGA9010_DEFRAMER_0, &initSettings->datapath.rxDmaCfg[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_RxDmaInit(device, ADI_FPGA9010_DEFRAMER_1, &initSettings->datapath.rxDmaCfg[1]); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_RxDmaInit(device, ADI_FPGA9010_DEFRAMER_2, &initSettings->datapath.rxDmaCfg[2]); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_TxDmaInit(device, ADI_FPGA9010_FRAMER_0, &initSettings->datapath.txDmaCfg[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_TxDmaInit(device, ADI_FPGA9010_FRAMER_1, &initSettings->datapath.txDmaCfg[1]); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*************************************************************************************************************************************** + * Reset datapaths + ***************************************************************************************************************************************/ + adi_fpga9010_RxDataChainReset(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_TxDataChainReset(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_InitGet(adi_fpga9010_Device_t *device, adi_fpga9010_Init_t *initSettings) +{ + uint8_t i = 0; + uint8_t laneSel = 1; + uint16_t dataMoverSel = 1; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, initSettings); + + + for (i=0; i< 8; i++) + { + // int32_t adi_fpga9010_SerializerCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_LaneSel_e laneSel, adi_fpga9010_SerializerCfg_t *serializerCfg) + adi_fpga9010_SerializerCfgGet(device, (adi_fpga9010_LaneSel_e)laneSel, &initSettings->datapath.serializerCfg[i]); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_DeserializerCfgGet(device, (adi_fpga9010_LaneSel_e)laneSel, &initSettings->datapath.deserializerCfg[i]); + ADI_ERROR_RETURN(device->common.error.newAction); + laneSel = laneSel << 1; + } + + // get the framer configurations + adi_fpga9010_FramerCfgGet(device, ADI_FPGA9010_FRAMER_0, &initSettings->datapath.framerCfg[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + // get the 2 deframer configurations + adi_fpga9010_DeframerCfgGet(device, ADI_FPGA9010_DEFRAMER_0, &initSettings->datapath.deframerCfg[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_DeframerCfgGet(device, ADI_FPGA9010_DEFRAMER_1, &initSettings->datapath.deframerCfg[1]); + ADI_ERROR_RETURN(device->common.error.newAction); + + + // get the 8 txdataMover configurations + dataMoverSel = 1; + for (i = 0; i < ADI_FPGA9010_NUM_OF_TX_DATAMOVERS; i++) + { + adi_fpga9010_TxDmaGet(device, (adi_fpga9010_FramerSel_e)dataMoverSel, &initSettings->datapath.txDmaCfg[i]); + ADI_ERROR_RETURN(device->common.error.newAction); + dataMoverSel = dataMoverSel << 1; + } + + //get the 16 rxdataMover configurations + dataMoverSel = 1; + for (i = 0; i < ADI_FPGA9010_NUM_OF_RX_DATAMOVERS; i++) + { + adi_fpga9010_RxDmaGet(device, (adi_fpga9010_DeframerSel_e)dataMoverSel, &initSettings->datapath.rxDmaCfg[i]); + ADI_ERROR_RETURN(device->common.error.newAction); + dataMoverSel = dataMoverSel << 1; + } + + //the configuration of all tollgates must be the same so we only need to store one of each + adi_fpga9010_TxTollgateGet(device, ADI_FPGA9010_FRAMER_0, &initSettings->datapath.txTollgateCfg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_RxTollgateGet(device, ADI_FPGA9010_DEFRAMER_0, &initSettings->datapath.rxTollgateCfg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + + +int32_t adi_fpga9010_Initialize(adi_fpga9010_Device_t *device, adi_fpga9010_Init_t *fpgaInit) +{ + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; +// uint32_t refClk_kHz = 245760; +// uint32_t fastestLaneRate_kHz = 1228800; + uint8_t lockBit = 0; + uint8_t resetDone = 0; + // uint8_t phyLayerMask = 0; + + uint8_t laneSelMask = 0x55; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + //todo fpgaInit is null and will be for some time + //ADI_NULL_PTR_RETURN(&device->common, fpgaInit); + + adi_fpga9010_InitSet(device, fpgaInit); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*check the qplls & mmcm for lock */ + lockBit = 0; + recoveryAction = adi_fpga9010_MmcmLockGet(device, ADI_FPGA9010_CORE_MMCM, &lockBit); + if (lockBit == 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, recoveryAction, lockBit, "Error RX MMCM not locked"); + } + ADI_ERROR_RETURN(device->common.error.newAction); + + /* quad 0 */ + lockBit = 0; + recoveryAction = adi_fpga9010_QpllLockGet(device, 0, fpgaInit->clocks.qpll.band, &lockBit); + if (lockBit == 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, recoveryAction, lockBit, "Error QPLL0 not locked"); + } + ADI_ERROR_RETURN(device->common.error.newAction); + + /* quad 1 */ + lockBit = 0; + recoveryAction = adi_fpga9010_QpllLockGet(device, 1, fpgaInit->clocks.qpll.band, &lockBit); + if (lockBit == 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, recoveryAction, lockBit, "Error QPLL1 not locked"); + } + ADI_ERROR_RETURN(device->common.error.newAction); + + //PHY reset done bits getting set? + recoveryAction = adi_fpga9010_DeserializerResetDoneGet(device, &resetDone); + if (resetDone!= laneSelMask) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, recoveryAction, resetDone, "Error Deserializer not reset"); + } + ADI_ERROR_RETURN(device->common.error.newAction); + + resetDone = 0; + recoveryAction = adi_fpga9010_SerializerResetDoneGet(device, &resetDone); + if (resetDone != laneSelMask) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, recoveryAction, resetDone, "Error Deserializer not reset"); + } + ADI_ERROR_RETURN(device->common.error.newAction); + return (device->common.error.newAction); +} + +//int32_t adi_fpga9010_Initialize(adi_fpga9010_Device_t *device, adi_fpga9010_Init_t *fpgaInit) +//{ +// +// int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; +// uint32_t refClk_kHz = 245760; +// uint32_t fastestLaneRate_kHz = 1228800; +// uint32_t i = 0; +// uint32_t j = 0; +// +// ADI_NULL_DEVICE_PTR_RETURN(device); +// +//#if ADI_FPGA9010_VERBOSE > 0 +// ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +//#endif +// +// ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +// //todo fpgaInit is null and will be for some time +// //ADI_NULL_PTR_RETURN(&device->common, fpgaInit); +// +// uint8_t lockBit = 0; +// uint8_t resetDone = 0; +// uint8_t laneSelMask; +// +// refClk_kHz = 245760; +// fastestLaneRate_kHz = 1228800; +// laneSelMask = 0x55; +// +// recoveryAction = adi_fpga9010_CalculateQpllSettings(device, refClk_kHz, fastestLaneRate_kHz, &fpgaInit->clocks.qpll); +// ADI_ERROR_RETURN(device->common.error.newAction); +// +// for (i = 0; i < ADI_FPGA9010_NUM_MMCM_OUTPUT_CLOCKS - 1; i++) +// { +// fpgaInit->clocks.rxMmcm.outputClkFreq_kHz[i] = refClk_kHz * 3; +// fpgaInit->clocks.txMmcm.outputClkFreq_kHz[i] = refClk_kHz * 3; +// } +// /* Force channel 6 to refClk because of the FPGA implementation constraint */ +// fpgaInit->clocks.rxMmcm.outputClkFreq_kHz[ADI_FPGA9010_NUM_MMCM_OUTPUT_CLOCKS - 1] = refClk_kHz; +// /* Force channel 6 on the tx one also because it's conveneient */ +// fpgaInit->clocks.txMmcm.outputClkFreq_kHz[ADI_FPGA9010_NUM_MMCM_OUTPUT_CLOCKS - 1] = refClk_kHz; +// +// recoveryAction = adi_fpga9010_CalculateMmcmSettings(device, refClk_kHz, &fpgaInit->clocks.rxMmcm); +// ADI_ERROR_RETURN(device->common.error.newAction); +// recoveryAction = adi_fpga9010_CalculateMmcmSettings(device, refClk_kHz, &fpgaInit->clocks.txMmcm); +// ADI_ERROR_RETURN(device->common.error.newAction); +// +// /*default serializer/deserializer values */ +// for (i = 0; i < 8; i++) +// { +// fpgaInit->datapath.deserializerCfg[i].rxPllClkSel = ADI_FPGA9010_QPLLCLK0; +// fpgaInit->datapath.deserializerCfg[i].rate = 1; +// fpgaInit->datapath.deserializerCfg[i].polarity = 0; +// fpgaInit->datapath.deserializerCfg[i].encoder8b10bEnable = 1; +// fpgaInit->datapath.deserializerCfg[i].usrClk2Div = 1; +// fpgaInit->datapath.deserializerCfg[i].powerDown = 0; +// fpgaInit->datapath.deserializerCfg[i].rxDfeLpmEn = 1; +// +// fpgaInit->datapath.serializerCfg[i].cpllRefClkSel = 0x01; +// fpgaInit->datapath.serializerCfg[i].txPllClkSel = ADI_FPGA9010_QPLLCLK0; +// fpgaInit->datapath.serializerCfg[i].rate = 1; +// fpgaInit->datapath.serializerCfg[i].polarity = 0; +// fpgaInit->datapath.serializerCfg[i].encoder8b10bEnable = 1; +// fpgaInit->datapath.serializerCfg[i].precursor = 0; +// fpgaInit->datapath.serializerCfg[i].postcursor = 0; +// fpgaInit->datapath.serializerCfg[i].diffCtrl = 4; +// fpgaInit->datapath.serializerCfg[i].usrClk2Div = 1; +// fpgaInit->datapath.serializerCfg[i].powerDown = 0; +// } +// +// /* default deframer values */ +// for (i = 0; i < 3; i++) +// { +// for (j = 0; j < ADI_FPGA9010_NUM_LANES; j++) +// { +// fpgaInit->datapath.deframerCfg[i].laneXbar[j] = j; +// } +// fpgaInit->datapath.deframerCfg[i].scramblingEn = 0; +// fpgaInit->datapath.deframerCfg[i].cfgF = 1; +// fpgaInit->datapath.deframerCfg[i].cfgK = 0x1F; +// fpgaInit->datapath.deframerCfg[i].subclassV = 2; +// fpgaInit->datapath.deframerCfg[i].rxBufferDly = 0; +// fpgaInit->datapath.deframerCfg[i].errReportingDisable = 0; +// fpgaInit->datapath.deframerCfg[i].ilaSupportEn = 0; +// fpgaInit->datapath.deframerCfg[i].lanesInUse = 0x00; +// fpgaInit->datapath.deframerCfg[i].sysRefAlways = 0; +// fpgaInit->datapath.deframerCfg[i].sysRefDelay = 0; +// fpgaInit->datapath.deframerCfg[i].sysRefRequiredOnResync = 0; +// fpgaInit->datapath.deframerCfg[i].mode = 0; +// } +// +// /* default deframer values */ +// for (i = 0; i < 2; i++) +// { +// for (j = 0; j < ADI_FPGA9010_NUM_LANES; j++) +// { +// fpgaInit->datapath.framerCfg[i].laneXbar[j] = j; +// } +// fpgaInit->datapath.framerCfg[i].deviceId = 0; +// fpgaInit->datapath.framerCfg[i].bankId = 1; +// fpgaInit->datapath.framerCfg[i].scramblingEn = 1; +// fpgaInit->datapath.framerCfg[i].ilaMultiFrames = 4; +// fpgaInit->datapath.framerCfg[i].cfgF = 1; +// fpgaInit->datapath.framerCfg[i].cfgK = 1; +// fpgaInit->datapath.framerCfg[i].ilaM = 0; +// fpgaInit->datapath.framerCfg[i].ilaN = 0; +// fpgaInit->datapath.framerCfg[i].ilaCs = 0; +// fpgaInit->datapath.framerCfg[i].ilaNp = 0; +// fpgaInit->datapath.framerCfg[i].ilaS = 0; +// fpgaInit->datapath.framerCfg[i].ilaCf = 0; +// fpgaInit->datapath.framerCfg[i].ilaHd = 0; +// fpgaInit->datapath.framerCfg[i].subclassV = 0; +// fpgaInit->datapath.framerCfg[i].ilaSupportEn = 0; +// fpgaInit->datapath.framerCfg[i].sysRefAlways = 0; +// fpgaInit->datapath.framerCfg[i].sysRefDelay = 0; +// fpgaInit->datapath.framerCfg[i].sysRefRequiredOnResync = 0; +// fpgaInit->datapath.framerCfg[i].lanesInUse = 0x00; +// } +// +// /* set rx datamovers */ +// for (i = 0; i < 16; i++) +// { +// fpgaInit->datapath.rxdmCfg[i].dmaCfg.dataPathEnhancedModeEn = 0; +// fpgaInit->datapath.rxdmCfg[i].dmaCfg.dataPathScatterGatherEn = 0; +// fpgaInit->datapath.rxdmCfg[i].dmaCfg.dataPathStartAddr = i * 0x1000000; //16MB each +// fpgaInit->datapath.rxdmCfg[i].dmaCfg.dataPathLength = 0; +// fpgaInit->datapath.rxdmCfg[i].dmaCfg.dataPathSGFirstDesc = 0; +// fpgaInit->datapath.rxdmCfg[i].dmaCfg.dataPathSGLastDesc = 0; +// +// fpgaInit->datapath.rxdmCfg[i].tplCfg.linkCfgF = 1; +// fpgaInit->datapath.rxdmCfg[i].tplCfg.linkCfgNP = 1; +// fpgaInit->datapath.rxdmCfg[i].tplCfg.linkCfgL = 1; +// fpgaInit->datapath.rxdmCfg[i].tplCfg.linkCfgS = 1; +// fpgaInit->datapath.rxdmCfg[i].tplCfg.linkConfigJesdV = 1; +// fpgaInit->datapath.rxdmCfg[i].tplCfg.linkConfigM = 1; +// fpgaInit->datapath.rxdmCfg[i].tplCfg.linkConfigLinkId = 1; +// fpgaInit->datapath.rxdmCfg[i].tplCfg.linkConfigConvId = 1; +// } +// +// /* set tx datamovers */ +// for (i = 0; i < 8; i++) +// { +// fpgaInit->datapath.txdmCfg[i].dmaCfg.dataPathEnhancedModeEn = 0; +// fpgaInit->datapath.txdmCfg[i].dmaCfg.dataPathScatterGatherEn = 0; +// fpgaInit->datapath.txdmCfg[i].dmaCfg.dataPathStartAddr = (i + 16) * 0x1000000; //16MB each +// fpgaInit->datapath.txdmCfg[i].dmaCfg.dataPathLength = 0; +// fpgaInit->datapath.txdmCfg[i].dmaCfg.dataPathSGFirstDesc = 0; +// fpgaInit->datapath.txdmCfg[i].dmaCfg.dataPathSGLastDesc = 0; +// +// fpgaInit->datapath.txdmCfg[i].tplCfg.linkCfgF = 1; +// fpgaInit->datapath.txdmCfg[i].tplCfg.linkCfgNP = 1; +// fpgaInit->datapath.txdmCfg[i].tplCfg.linkCfgL = 1; +// fpgaInit->datapath.txdmCfg[i].tplCfg.linkCfgS = 1; +// fpgaInit->datapath.txdmCfg[i].tplCfg.linkConfigJesdV = 1; +// fpgaInit->datapath.txdmCfg[i].tplCfg.linkConfigM = 1; +// fpgaInit->datapath.txdmCfg[i].tplCfg.linkConfigLinkId = 1; +// fpgaInit->datapath.txdmCfg[i].tplCfg.linkConfigConvId = 1; +// } +// +// /* tollgates */ +// fpgaInit->datapath.rxTollgateCfg.tollGateEdgeOrLvl = 1; +// fpgaInit->datapath.rxTollgateCfg.tollGateHiRiseOrLoFall = 1; +// fpgaInit->datapath.rxTollgateCfg.tollgateReset = 1; +// fpgaInit->datapath.rxTollgateCfg.tollGateTrigSource = ADI_FPGA9010_IMM_TRIG; +// +// fpgaInit->datapath.txTollgateCfg.tollGateEdgeOrLvl = 1; +// fpgaInit->datapath.txTollgateCfg.tollGateHiRiseOrLoFall = 1; +// fpgaInit->datapath.txTollgateCfg.tollgateReset = 1; +// fpgaInit->datapath.txTollgateCfg.tollGateTrigSource = ADI_FPGA9010_TX_IMM_TRIG; +// +// //place all tx & rx channels in reset +// recoveryAction = adi_fpga9010_DeserializerResetSet(device, 0xFF, 1); +// ADI_ERROR_RETURN(device->common.error.newAction); +// recoveryAction = adi_fpga9010_SerializerResetSet(device, 0xFF, 1); +// ADI_ERROR_RETURN(device->common.error.newAction); +// +// recoveryAction = adi_fpga9010_InitSet(device, fpgaInit); +// ADI_ERROR_RETURN(device->common.error.newAction); +// +// //release channel reset +// recoveryAction = adi_fpga9010_DeserializerResetSet(device, laneSelMask, 0); +// ADI_ERROR_RETURN(device->common.error.newAction); +// recoveryAction = adi_fpga9010_SerializerResetSet(device, laneSelMask, 0); +// ADI_ERROR_RETURN(device->common.error.newAction); +// +// /*check the qplls & mmcm for lock */ +// lockBit = 0; +// recoveryAction = adi_fpga9010_MmcmLockGet(device, ADI_FPGA9010_RX_MMCM, &lockBit); +// if (lockBit == 0) +// { +// ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, recoveryAction, lockBit, "Error RX MMCM not locked"); +// } +// ADI_ERROR_RETURN(device->common.error.newAction); +// +// lockBit = 0; +// recoveryAction = adi_fpga9010_MmcmLockGet(device, ADI_FPGA9010_TX_MMCM, &lockBit); +// if (lockBit == 0) +// { +// ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, recoveryAction, lockBit, "Error TX MMCM not locked"); +// } +// ADI_ERROR_RETURN(device->common.error.newAction); +// +// /* quad 0 */ +// lockBit = 0; +// recoveryAction = adi_fpga9010_QpllLockGet(device, 0, fpgaInit->clocks.qpll.band, &lockBit); +// if (lockBit == 0) +// { +// ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, recoveryAction, lockBit, "Error QPLL0 not locked"); +// } +// ADI_ERROR_RETURN(device->common.error.newAction); +// +// /* quad 1 */ +// lockBit = 0; +// recoveryAction = adi_fpga9010_QpllLockGet(device, 1, fpgaInit->clocks.qpll.band, &lockBit); +// if (lockBit == 0) +// { +// ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, recoveryAction, lockBit, "Error QPLL1 not locked"); +// } +// ADI_ERROR_RETURN(device->common.error.newAction); +// +// //PHY reset done bits getting set? +// recoveryAction = adi_fpga9010_DeserializerResetDoneGet(device, &resetDone); +// if (resetDone != laneSelMask) +// { +// ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, recoveryAction, resetDone, "Error Deserializer not reset"); +// } +// ADI_ERROR_RETURN(device->common.error.newAction); +// +// resetDone = 0; +// recoveryAction = adi_fpga9010_SerializerResetDoneGet(device, &resetDone); +// if (resetDone != laneSelMask) +// { +// ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, recoveryAction, resetDone, "Error Deserializer not reset"); +// } +// ADI_ERROR_RETURN(device->common.error.newAction); +// return (device->common.error.newAction); +//} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_axi_adv_spi.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_axi_adv_spi.c new file mode 100644 index 0000000..02ffa26 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_axi_adv_spi.c @@ -0,0 +1,95 @@ + +/*! +* \file adi_fpga9010_axi_adv_spi.c +* \brief Contains FPGA9010 AXI Advanced SPI function implementations +* +* ADRV9010 API Version: 6.4.0.14 +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9010_axi_adv_spi.h" +#include "adi_fpga9010_axi_adv_spi_types.h" +#include "../../private/include/fpga9010_bf_axi_adv_spi.h" + +int32_t adi_fpga9010_AxiAdvSpiCfgSet(adi_fpga9010_Device_t *device, adi_fpga9010_AxiAdvSpiFeatConfig_t *advSpiCfg, uint8_t slaveSelect) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t registerValue = 0; + /* starting address is slaveSelect0's address. Multiply parameter by 4 since it's byte-addressing and each SS gets a full register */ + uint32_t registerAddress = 0x44A00080 + (slaveSelect * 4); + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, advSpiCfg); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + /* Build up the registerValue */ + registerValue |= ((uint32_t)advSpiCfg->enable & 0x1) << 0; + registerValue |= ((uint32_t)advSpiCfg->cpol & 0x1) << 1; + registerValue |= ((uint32_t)advSpiCfg->cpha & 0x1) << 2; + registerValue |= ((uint32_t)advSpiCfg->lsbFirst & 0x1) << 3; + registerValue |= ((uint32_t)advSpiCfg->fourWire & 0x1) << 4; + registerValue |= ((uint32_t)advSpiCfg->misoSampleSlip & 0x1) << 5; + registerValue |= ((uint32_t)advSpiCfg->threeWireTriPoint & 0xFF) << 8; + registerValue |= ((uint32_t)advSpiCfg->clockDiv & 0xFFFF) << 16; + + recoveryAction = adi_hal_BbicRegisterWrite(device->common.devHalInfo, registerAddress, registerValue); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, advSpiCfg, "Error configuring Advanced SPI"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_fpga9010_AxiAdvSpiChipSelectAll(adi_fpga9010_Device_t *device, uint8_t enable) +{ + /* Manual Slave Select Assertion Enable Bit */ + static const uint32_t MAN_SS_EN = 0x00000080; + + /* Tokelau Device/s slave select indices*/ + /* TODO: This variable should be calculated at Board Discover in future */ + static const uint32_t TOK_CS = 0x00000001; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /*Address of SPICR*/ + uint32_t spicrAddress = 0x44A00060; + + /*Address of SPISSR*/ + uint32_t spissrAddress = 0x44A00070; + + uint32_t spicrValue = 0; + + recoveryAction = adi_hal_BbicRegisterRead(device->common.devHalInfo, spicrAddress, &spicrValue); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, spicrAddress, "Error reading spicrAddress"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (enable == ADI_TRUE) + { + /* Select all Tokelau devices */ + recoveryAction = adi_hal_BbicRegisterWrite(device->common.devHalInfo, spissrAddress, ~TOK_CS); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, spissrAddress, "Error selecting all Tokelau devices"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Enable manual select mode */ + recoveryAction = adi_hal_BbicRegisterWrite(device->common.devHalInfo, spicrAddress, (spicrValue | MAN_SS_EN)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, spicrAddress, "Error writing spicrAddress"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Disable manual select mode */ + recoveryAction = adi_hal_BbicRegisterWrite(device->common.devHalInfo, spicrAddress, (spicrValue & (~MAN_SS_EN))); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, spicrAddress, "Error writing spicrAddress"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_clk.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_clk.c new file mode 100644 index 0000000..25d6fd0 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_clk.c @@ -0,0 +1,897 @@ +/** + * \file: adi_fpga9010_clk.c + * + * \brief Contains top level fpga9010 related functions + * + * FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9010_user.h" +#include "adi_fpga9010_clk.h" +#include "adi_fpga9010.h" +#include "../../private/include/fpga9010_bf_xilinx_clock_wizard.h" +#include "../../private/include/fpga9010_bf_jesd204_phy_tokelau_ads8.h" + +int32_t adi_fpga9010_MmcmSet(adi_fpga9010_Device_t *device, adi_fpga9010_MmcmSel_e mmcmSel, adi_fpga9010_MmcmCfg_t *mmcm) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr = FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + /* Set base address for the correct Clock Wizard module */ + if (mmcmSel == ADI_FPGA9010_CORE_MMCM) + { + baseAddr = FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD; + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, mmcmSel, "Invalid MMCM selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Reset the clock wizard */ + recoveryAction = fpga9010_XilinxClockWizardSoftwareResetBfSet(device, baseAddr, 0xA); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error resetting clock wizard"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write the configuration registers */ + recoveryAction = fpga9010_XilinxClockWizardClkfboutMultBfSet(device, baseAddr, mmcm->mVal); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, mmcm->mVal, "Error setting clock wizard M value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxClockWizardDivclkDivideBfSet(device, baseAddr, mmcm->dVal); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, mmcm->dVal, "Error setting clock wizard D value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxClockWizardClkout0DivideBfSet(device, baseAddr, mmcm->outputClkDiv[0]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, mmcm->outputClkDiv[0], "Error setting clock wizard channel 0 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxClockWizardClkout1DivideBfSet(device, baseAddr, mmcm->outputClkDiv[1]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, mmcm->outputClkDiv[1], "Error setting clock wizard channel 1 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxClockWizardClkout2DivideBfSet(device, baseAddr, mmcm->outputClkDiv[2]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, mmcm->outputClkDiv[2], "Error setting clock wizard channel 2 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxClockWizardClkout3DivideBfSet(device, baseAddr, mmcm->outputClkDiv[3]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, mmcm->outputClkDiv[3], "Error setting clock wizard channel 3 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxClockWizardClkout4DivideBfSet(device, baseAddr, mmcm->outputClkDiv[4]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, mmcm->outputClkDiv[4], "Error setting clock wizard channel 4 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxClockWizardClkout5DivideBfSet(device, baseAddr, mmcm->outputClkDiv[5]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, mmcm->outputClkDiv[5], "Error setting clock wizard channel 5 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxClockWizardClkout6DivideBfSet(device, baseAddr, mmcm->outputClkDiv[6]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, mmcm->outputClkDiv[6], "Error setting clock wizard channel 6 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set the saddr bitfield to indicate current configuration register values are for dynamic reconfiguration*/ + recoveryAction = fpga9010_XilinxClockWizardSaddrBfSet(device, baseAddr, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting clock wizard saddr"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set load bitfield to start the dynamic reconfiguration process*/ + recoveryAction = fpga9010_XilinxClockWizardLoadBfSet(device, baseAddr, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error starting clock wizard dynamic reconfiguration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_MmcmGet(adi_fpga9010_Device_t *device, adi_fpga9010_MmcmSel_e mmcmSel, adi_fpga9010_MmcmCfg_t *mmcm) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr = FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + /* Set base address for the correct Clock Wizard module */ + if (mmcmSel == ADI_FPGA9010_CORE_MMCM) + { + baseAddr = FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD; + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, mmcmSel, "Invalid MMCM selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Read the configuration registers */ + recoveryAction = fpga9010_XilinxClockWizardClkfboutMultBfGet(device, baseAddr, &mmcm->mVal); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading clock wizard M value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxClockWizardDivclkDivideBfGet(device, baseAddr, &mmcm->dVal); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading clock wizard D value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxClockWizardClkout0DivideBfGet(device, baseAddr, &mmcm->outputClkDiv[0]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading clock wizard channel 0 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxClockWizardClkout1DivideBfGet(device, baseAddr, &mmcm->outputClkDiv[1]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading clock wizard channel 1 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxClockWizardClkout2DivideBfGet(device, baseAddr, &mmcm->outputClkDiv[2]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading clock wizard channel 2 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxClockWizardClkout3DivideBfGet(device, baseAddr, &mmcm->outputClkDiv[3]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading clock wizard channel 3 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxClockWizardClkout4DivideBfGet(device, baseAddr, &mmcm->outputClkDiv[4]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading clock wizard channel 4 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxClockWizardClkout5DivideBfGet(device, baseAddr, &mmcm->outputClkDiv[5]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading clock wizard channel 5 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxClockWizardClkout6DivideBfGet(device, baseAddr, &mmcm->outputClkDiv[6]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading clock wizard channel 6 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_MmcmResetSet(adi_fpga9010_Device_t *device, adi_fpga9010_MmcmSel_e mmcmSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr = FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + /* Set base address for the correct Clock Wizard module */ + if (mmcmSel == ADI_FPGA9010_CORE_MMCM) + { + baseAddr = FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD; + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, mmcmSel, "Invalid MMCM selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Reset the clock wizard */ + recoveryAction = fpga9010_XilinxClockWizardSoftwareResetBfSet(device, baseAddr, 0xA); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error resetting clock wizard"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_MmcmLockGet(adi_fpga9010_Device_t *device, adi_fpga9010_MmcmSel_e mmcmSel, uint8_t *lockBit) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxClockWizardChanAddr_e baseAddr = FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, lockBit); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + /* Set base address for the correct Clock Wizard module */ + if (mmcmSel == ADI_FPGA9010_CORE_MMCM) + { + baseAddr = FPGA9010_BF_JESD204_CORE_CLOCK_WIZARD; + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, mmcmSel, "Invalid MMCM selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Load bit returns to 0 after reconfiguring and locked */ + recoveryAction = fpga9010_XilinxClockWizardLockedBfGet(device, baseAddr, lockBit); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading clock wizard lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; + +} + +int32_t adi_fpga9010_QpllSet(adi_fpga9010_Device_t *device, uint8_t quadMask, adi_fpga9010_QpllCfg_t *qPll) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint16_t mDrpVal = 0; + uint16_t nDrpVal = 0; + uint8_t powerGood = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, qPll); + + switch (qPll->mVal) + { + case 1: + mDrpVal = 0x0800; + break; + case 2: + mDrpVal = 0x0000; + break; + case 3: + mDrpVal = 0x0080; + break; + case 4: + mDrpVal = 0x0100; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, qPll->mVal, "Invalid M val"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + nDrpVal = qPll->nVal - 2; + + /* Range checks */ + if (qPll->band > ADI_FPGA9010_QPLLCLK0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, qPll->band, "Invalid band"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Quad 0*/ + if ((quadMask & 0x1) == 0x1) + { + /* set ref clk for qpll*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0RefClkSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, qPll->refClkSelect[0]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting ref clk for quad 0 qppl 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1RefClkSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, qPll->refClkSelect[0]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting ref clk for quad 0 qppl 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (qPll->band == ADI_FPGA9010_QPLLCLK0) + { + /* Power up this qpll*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0PdBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error powering up quad 0 qppl 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Power down the other qpll in this quad*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1PdBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error powering down quad 0 qppl 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set the reset bit of the correct qpll*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0ResetBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error resetting quad 0 qpll 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lpf value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK0_LPF_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD0, qPll->lpf, ADI_FPGA9010_QPLL_LPF_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 0 qpll 0 lpf value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write cfg4 value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK0_CFG4_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD0, qPll->cfg4, ADI_FPGA9010_QPLL_CFG4_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 0 qpll 0 cfg4 value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write cp value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK0_CP_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD0, qPll->cp, ADI_FPGA9010_QPLL_CP_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 0 qpll 0 cp value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lock cfg value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK0_LOCK_CFG_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD0, qPll->lockCfg, ADI_FPGA9010_QPLL_LOCK_CFG_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 0 qpll 0 lock cfg value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lock cfg g3 value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK0_LOCK_CFG_G3_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD0, qPll->lockCfgG3, ADI_FPGA9010_QPLL_LOCK_CFG_G3_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 0 qpll 0 lock cfg g3 value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write n and m values through DRP transactions*/ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK0_N_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD0, nDrpVal, ADI_FPGA9010_QPLL_N_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 0 qpll 0 N value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK0_M_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD0, mDrpVal, ADI_FPGA9010_QPLL_M_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 0 qpll 0 M value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Ensure power good is set for all channels*/ + recoveryAction = adi_fpga9010_LanePowerGoodGet(device, 0, &powerGood); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error trying to read power good signals from quad 0 channels"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (powerGood != 0x0F) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ACT_ERR_RESET_FULL, ADI_FPGA9010_ERR_CHANNEL_POWER_GOOD_FAILURE, NULL, "One of more quad 0 channels reporting invalid power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Clear the reset bit of the correct qpll*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0ResetBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error trying to reset qpll 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + } + else + { + /* Power up this qpll*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1PdBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error powering up quad 0 qppl 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Power down the other qpll in this quad*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0PdBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error powering down quad 0 qppl 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set the reset bit */ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1ResetBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error resetting quad 0 qpll 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lpf value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK1_LPF_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD0, qPll->lpf, ADI_FPGA9010_QPLL_LPF_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 0 qpll 1 lpf value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write cfg4 value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK1_CFG4_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD0, qPll->cfg4, ADI_FPGA9010_QPLL_CFG4_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 0 qpll 1 cfg4 value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write cp value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK1_CP_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD0, qPll->cp, ADI_FPGA9010_QPLL_CP_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 0 qpll 1 cp value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lock cfg value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK1_LOCK_CFG_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD0, qPll->lockCfg, ADI_FPGA9010_QPLL_LOCK_CFG_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 0 qpll 1 lock cfg value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lock cfg g3 value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK1_LOCK_CFG_G3_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD0, qPll->lockCfgG3, ADI_FPGA9010_QPLL_LOCK_CFG_G3_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 0 qpll 1 lock cfg g3 value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write n and m values through DRP transactions*/ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK1_N_ADDRESS, ADI_FPGA9010_PHY_QUAD0, nDrpVal, ADI_FPGA9010_QPLL_N_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 0 qpp 1 N value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK1_M_ADDRESS, ADI_FPGA9010_PHY_QUAD0, mDrpVal, ADI_FPGA9010_QPLL_M_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 0 qpll 1 M value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Ensure power good is set for all channels*/ + recoveryAction = adi_fpga9010_LanePowerGoodGet(device, 0, &powerGood); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error trying to read power good signals from quad 0 channels"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (powerGood != 0x0F) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ACT_ERR_RESET_FULL, ADI_FPGA9010_ERR_CHANNEL_POWER_GOOD_FAILURE, NULL, "One of more quad 0 channels reporting invalid power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Clear the reset bit*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1ResetBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error taking quad 0 qpll 1 out of reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + } + /* Quad 1*/ + if ((quadMask & 0x2) == 0x2) + { + /* set ref clk for qpll*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0RefClkSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, qPll->refClkSelect[1]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting ref clk for quad 1 qppl 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1RefClkSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, qPll->refClkSelect[1]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting ref clk for quad 1 qppl 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (qPll->band == ADI_FPGA9010_QPLLCLK0) + { + /* Power up this qpll*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0PdBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error powering up quad 1 qppl 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Power down the other qpll in this quad*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1PdBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error powering down quad 1 qppl 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set the reset bit*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0ResetBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error resetting quad 1 qpll 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lpf value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK0_LPF_ADDRESS, ADI_FPGA9010_PHY_QUAD0, qPll->lpf, ADI_FPGA9010_QPLL_LPF_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 1 qpll 0 lpf value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write cfg4 value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK0_CFG4_ADDRESS, ADI_FPGA9010_PHY_QUAD0, qPll->cfg4, ADI_FPGA9010_QPLL_CFG4_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 1 qpll 0 cfg4 value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write cp value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK0_CP_ADDRESS, ADI_FPGA9010_PHY_QUAD0, qPll->cp, ADI_FPGA9010_QPLL_CP_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 1 qpll 0 cp value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lock cfg value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK0_LOCK_CFG_ADDRESS, ADI_FPGA9010_PHY_QUAD0, qPll->lockCfg, ADI_FPGA9010_QPLL_LOCK_CFG_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 1 qpll 0 lock cfg value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lock cfg g3 value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK0_LOCK_CFG_G3_ADDRESS, ADI_FPGA9010_PHY_QUAD0, qPll->lockCfgG3, ADI_FPGA9010_QPLL_LOCK_CFG_G3_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 1 qpll 0 lock cfg g3 value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write n and m values through DRP transactions*/ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK0_N_ADDRESS, ADI_FPGA9010_PHY_QUAD1, nDrpVal, ADI_FPGA9010_QPLL_N_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 1 qpp 0 N value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK0_M_ADDRESS, ADI_FPGA9010_PHY_QUAD1, mDrpVal, ADI_FPGA9010_QPLL_M_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 1 qpll 0 M value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Ensure power good is set for all channels*/ + recoveryAction = adi_fpga9010_LanePowerGoodGet(device, 1, &powerGood); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error trying to read power good signals from quad 0 channels"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (powerGood != 0xF0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ACT_ERR_RESET_FULL, ADI_FPGA9010_ERR_CHANNEL_POWER_GOOD_FAILURE, NULL, "One of more quad 1 channels reporting invalid power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Clear reset bit */ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0ResetBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error trying to reset qpll 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Power up this qpll*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1PdBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error powering up quad 1 qppl 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Power down the other qpll in this quad*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0PdBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error powering down quad 1 qppl 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set the reset bit*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1ResetBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error resetting quad 1 qpll 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lpf value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK1_LPF_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD1, qPll->lpf, ADI_FPGA9010_QPLL_LPF_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 1 qpll 1 lpf value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write cfg4 value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK1_CFG4_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD1, qPll->cfg4, ADI_FPGA9010_QPLL_CFG4_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 1 qpll 1 cfg4 value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write cp value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK1_CP_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD1, qPll->cp, ADI_FPGA9010_QPLL_CP_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 1 qpll 1 cp value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lock cfg value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK1_LOCK_CFG_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD1, qPll->lockCfg, ADI_FPGA9010_QPLL_LOCK_CFG_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 1 qpll 0 lock cfg value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lock cfg g3 value */ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK1_LOCK_CFG_G3_ADDRESS, (uint8_t)ADI_FPGA9010_PHY_QUAD1, qPll->lockCfgG3, ADI_FPGA9010_QPLL_LOCK_CFG_G3_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 1 qpll 1 lock cfg g3 value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write n and m values through DRP transactions*/ + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK1_N_ADDRESS, ADI_FPGA9010_PHY_QUAD1, nDrpVal, ADI_FPGA9010_QPLL_N_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 1 qpp 1 N value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9010_DrpWrite(device, ADI_FPGA9010_QPLLCLK1_M_ADDRESS, ADI_FPGA9010_PHY_QUAD1, mDrpVal, ADI_FPGA9010_QPLL_M_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error writing to quad 1 qpll 1 M value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Ensure power good is set for all channels*/ + recoveryAction = adi_fpga9010_LanePowerGoodGet(device, 1, &powerGood); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error trying to read power good signals from quad 0 channels"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (powerGood != 0xF0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ACT_ERR_RESET_FULL, ADI_FPGA9010_ERR_CHANNEL_POWER_GOOD_FAILURE, NULL, "One of more quad 1 channels reporting invalid power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Clear reset bit*/ + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1ResetBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error trying to reset qpll 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +//int32_t adi_fpga9010_QpllGet(adi_fpga9010_Device_t *device, adi_fpga9010_QpllSel_e qpllSel, adi_fpga9010_QpllCfg_t *qPll) +int32_t adi_fpga9010_QpllGet(adi_fpga9010_Device_t *device, adi_fpga9010_Qpll_Quad_e quadSel, adi_fpga9010_LaneClkSel_e bandSel, adi_fpga9010_QpllCfg_t *qPll) +{ + int recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint16_t mDrpVal = 0; + uint16_t nDrpVal = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, qPll); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + if (quadSel == ADI_FPGA9010_QPLL_QUAD0) + { + if (bandSel == ADI_FPGA9010_QPLLCLK0) + { + /* Read n and m values through DRP transactions*/ + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK0_N_ADDRESS, ADI_FPGA9010_PHY_QUAD0, &nDrpVal, ADI_FPGA9010_QPLL_N_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Unable to read quad 0 qppl 0 N value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK0_M_ADDRESS, ADI_FPGA9010_PHY_QUAD0, &mDrpVal, ADI_FPGA9010_QPLL_M_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Unable to read quad 0 qppl 0 M value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lpf value */ + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK0_LPF_ADDRESS, ADI_FPGA9010_PHY_QUAD0, &qPll->lpf, ADI_FPGA9010_QPLL_LPF_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading to quad 0 qpll 0 lpf value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write cfg4 value */ + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK0_CFG4_ADDRESS, ADI_FPGA9010_PHY_QUAD0, &qPll->cfg4, ADI_FPGA9010_QPLL_CFG4_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading to quad 0 qpll 0 cfg4 value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write cp value */ + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK0_CP_ADDRESS, ADI_FPGA9010_PHY_QUAD0, &qPll->cp, ADI_FPGA9010_QPLL_CP_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading to quad 0 qpll 0 cp value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lock cfg value */ + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK0_LOCK_CFG_ADDRESS, ADI_FPGA9010_PHY_QUAD0, &qPll->lockCfg, ADI_FPGA9010_QPLL_LOCK_CFG_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading to quad 0 qpll 0 lock cfg value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lock cfg g3 value */ + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK0_LOCK_CFG_G3_ADDRESS, ADI_FPGA9010_PHY_QUAD0, &qPll->lockCfgG3, ADI_FPGA9010_QPLL_LOCK_CFG_G3_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading to quad 0 qpll 0 lock cfg g3 value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (bandSel == ADI_FPGA9010_QPLLCLK1) + { + /* Read n and m values through DRP transactions*/ + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK1_N_ADDRESS, ADI_FPGA9010_PHY_QUAD0, &nDrpVal, ADI_FPGA9010_QPLL_N_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Unable to read quad 0 qppl 1 N value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK1_M_ADDRESS, ADI_FPGA9010_PHY_QUAD0, &mDrpVal, ADI_FPGA9010_QPLL_M_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Unable to read quad 0 qppl 1 M value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Invalid qpll band selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else if (quadSel == ADI_FPGA9010_QPLL_QUAD1) + { + if (bandSel == ADI_FPGA9010_QPLLCLK0) + { + /* Read n and m values through DRP transactions*/ + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK0_N_ADDRESS, ADI_FPGA9010_PHY_QUAD1, &nDrpVal, ADI_FPGA9010_QPLL_N_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Unable to read quad 1 qppl 0 N value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK0_M_ADDRESS, ADI_FPGA9010_PHY_QUAD1, &mDrpVal, ADI_FPGA9010_QPLL_M_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Unable to read quad 1 qppl 0 M value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lpf value */ + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK0_LPF_ADDRESS, ADI_FPGA9010_PHY_QUAD0, &qPll->lpf, ADI_FPGA9010_QPLL_LPF_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading to quad 1 qpll 0 lpf value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write cfg4 value */ + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK0_CFG4_ADDRESS, ADI_FPGA9010_PHY_QUAD0, &qPll->cfg4, ADI_FPGA9010_QPLL_CFG4_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading to quad 1 qpll 0 cfg4 value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write cp value */ + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK0_CP_ADDRESS, ADI_FPGA9010_PHY_QUAD0, &qPll->cp, ADI_FPGA9010_QPLL_CP_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading to quad 1 qpll 0 cp value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lock cfg value */ + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK0_LOCK_CFG_ADDRESS, ADI_FPGA9010_PHY_QUAD0, &qPll->lockCfg, ADI_FPGA9010_QPLL_LOCK_CFG_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading to quad 1 qpll 0 lock cfg value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lock cfg g3 value */ + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK0_LOCK_CFG_G3_ADDRESS, ADI_FPGA9010_PHY_QUAD0, &qPll->lockCfgG3, ADI_FPGA9010_QPLL_LOCK_CFG_G3_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading to quad 1 qpll 0 lock cfg g3 value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (bandSel == ADI_FPGA9010_QPLLCLK1) + { + /* Read n and m values through DRP transactions*/ + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK1_N_ADDRESS, ADI_FPGA9010_PHY_QUAD1, &nDrpVal, ADI_FPGA9010_QPLL_N_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Unable to read quad 1 qppl 1 N value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9010_DrpRead(device, ADI_FPGA9010_QPLLCLK1_M_ADDRESS, ADI_FPGA9010_PHY_QUAD1, &mDrpVal, ADI_FPGA9010_QPLL_M_MASK); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Unable to read quad 1 qppl 1 M value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Invalid qpll band selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Invalid qpll Quad selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + switch (mDrpVal) + { + case 0x0800: + qPll->mVal = 1; + break; + case 0x0000: + qPll->mVal = 2; + break; + case 0x0080: + qPll->mVal = 3; + break; + case 0x0100: + qPll->mVal = 4; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEHAL, ADI_FPGA9010_ERR_DRP_ERROR, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Invalid M val reported from DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + switch (nDrpVal) + { + case 0x000E: + qPll->nVal = 16; + break; + case 0x0012: + nDrpVal = 20; + break; + case 0x001E: + nDrpVal = 32; + break; + case 0x0026: + nDrpVal = 40; + break; + case 0x003A: + nDrpVal = 60; + break; + case 0x003E: + nDrpVal = 64; + break; + case 0x0040: + nDrpVal = 66; + break; + case 0x0049: + nDrpVal = 75; + break; + case 0x004E: + nDrpVal = 80; + break; + case 0x0052: + nDrpVal = 84; + break; + case 0x005A: + nDrpVal = 90; + break; + case 0x005E: + nDrpVal = 96; + break; + case 0x0062: + nDrpVal = 100; + break; + case 0x006E: + nDrpVal = 112; + break; + case 0x0076: + nDrpVal = 120; + break; + case 0x007B: + nDrpVal = 125; + break; + case 0x0094: + nDrpVal = 150; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEHAL, ADI_FPGA9010_ERR_DRP_ERROR, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Invalid N val reported from DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + return recoveryAction; +} + +int32_t adi_fpga9010_QpllLockGet(adi_fpga9010_Device_t *device, uint8_t quadSel, uint8_t bandSel, uint8_t *lockBit) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, lockBit); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + if (quadSel == ADI_FPGA9010_QPLL_QUAD0) + { + if (bandSel == ADI_FPGA9010_QPLLCLK0) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad0Qpll0LockBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, lockBit); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read quad 0 qpll0 lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad0Qpll1LockBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, lockBit); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read quad 0 qpll 1 lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + } + else if (quadSel == ADI_FPGA9010_QPLL_QUAD1) + { + if (bandSel == ADI_FPGA9010_QPLLCLK0) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad1Qpll0LockBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, lockBit); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read quad 1 qpll0 lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Quad1Qpll1LockBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, lockBit); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read quad 1 qpll 1 lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, quadSel, "Invalid quad selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; + +} + +int32_t adi_fpga9010_LanePowerGoodGet(adi_fpga9010_Device_t *device, uint8_t quadSel, uint8_t *powerGood) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t bfReturn = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, powerGood); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + /* Range checks */ + if (quadSel > 1) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, quadSel, "Invalid quad selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *powerGood = 0; + + if (quadSel == 0) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel0GtpowergoodBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &bfReturn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read channel 0 power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + *powerGood |= (bfReturn & 0x01) << 0; + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel1GtpowergoodBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &bfReturn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read channel 1 power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + *powerGood |= (bfReturn & 0x01) << 1; + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel2GtpowergoodBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &bfReturn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read channel 2 power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + *powerGood |= (bfReturn & 0x01) << 2; + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel3GtpowergoodBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &bfReturn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read channel 3 power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + *powerGood |= (bfReturn & 0x01) << 3; + } + else + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel4GtpowergoodBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &bfReturn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read channel 4 power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + *powerGood |= (bfReturn & 0x01) << 4; + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel5GtpowergoodBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &bfReturn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read channel 5 power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + *powerGood |= (bfReturn & 0x01) << 5; + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel6GtpowergoodBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &bfReturn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read channel 6 power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + *powerGood |= (bfReturn & 0x01) << 6; + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel7GtpowergoodBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &bfReturn); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read channel 7 power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + *powerGood |= (bfReturn & 0x01) << 7; + } + + return recoveryAction; + +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_gpio.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_gpio.c new file mode 100644 index 0000000..7841fd0 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_gpio.c @@ -0,0 +1,468 @@ + +/** + * \file: adi_fpga9010_jesd.c + * + * \brief Contains top level tx fpga9010 related functions + * + * FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9010_user.h" +#include "adi_fpga9010_gpio.h" +#include "adi_fpga9010.h" +#include "../../private/include/fpga9010_bf_axi_tokelau.h" + + +int32_t adi_fpga9010_GpioModeSet(adi_fpga9010_Device_t *device, adi_fpga9010_GpioModes_e gpioMode) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t enable = 1; + uint8_t disable = 0; + uint8_t i = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); + + + if (gpioMode == ADI_FPGA9010_GPIO_MODE_NONE) + { + recoveryAction = fpga9010_AxiTokelauGpioEnSpi2BfSet(device, FPGA9010_BF_AXI_TOKELAU, disable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not disable spi2 mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_AxiTokelauGpioEnTokJtagBfSet(device, FPGA9010_BF_AXI_TOKELAU, disable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not disable jtag mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_FPGA9010_GPIO_PINS; i++) + { + device->devStateInfo.gpioPinMode[i] = ADI_FPGA9010_GPIO_MODE_NONE; + } + } + + if (gpioMode == ADI_FPGA9010_GPIO_MODE_JTAG) + { + recoveryAction = fpga9010_AxiTokelauGpioEnTokJtagBfSet(device, FPGA9010_BF_AXI_TOKELAU, enable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not enable jtag mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_FPGA9010_GPIO_PINS; i++) + { + device->devStateInfo.gpioPinMode[i] = ADI_FPGA9010_GPIO_MODE_JTAG; + } + } + + if (gpioMode == ADI_FPGA9010_GPIO_MODE_SPI2) + { + recoveryAction = fpga9010_AxiTokelauGpioEnSpi2BfSet(device, FPGA9010_BF_AXI_TOKELAU, enable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not enable spi2 mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* GPIO[3:0] are used for SPI2 mode */ + device->devStateInfo.gpioPinMode[0] = ADI_FPGA9010_GPIO_MODE_SPI2; + device->devStateInfo.gpioPinMode[1] = ADI_FPGA9010_GPIO_MODE_SPI2; + device->devStateInfo.gpioPinMode[2] = ADI_FPGA9010_GPIO_MODE_SPI2; + device->devStateInfo.gpioPinMode[3] = ADI_FPGA9010_GPIO_MODE_SPI2; + } + + return recoveryAction; +} + +int32_t adi_fpga9010_GpioModeGet(adi_fpga9010_Device_t *device, adi_fpga9010_GpioModes_e *gpioMode) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t jtagStatus; + uint8_t spi2Status; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, gpioMode); + + recoveryAction = fpga9010_AxiTokelauGpioEnSpi2BfGet(device, FPGA9010_BF_AXI_TOKELAU, &spi2Status); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read spi2 mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_AxiTokelauGpioEnTokJtagBfGet(device, FPGA9010_BF_AXI_TOKELAU, &jtagStatus); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read jtag mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + *gpioMode = ADI_FPGA9010_GPIO_MODE_NONE ; + + if (spi2Status > 0) + { + *gpioMode = ADI_FPGA9010_GPIO_MODE_SPI2; + } + + if (jtagStatus > 0) + { + //Jtag mode overrides spi2 mode + *gpioMode = ADI_FPGA9010_GPIO_MODE_JTAG; + } + + return recoveryAction; +} + +int32_t adi_fpga9010_GpioInputDirSet(adi_fpga9010_Device_t *device, uint32_t pinSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t orgPinSelMask = 0; + uint32_t newPinSelMask = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); + + if (pinSelMask > ADI_FPGA9010_GPIO_MAX_VALUE) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, pinSelMask, "pinSelMask cannot exceed max value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = fpga9010_AxiTokelauGpioTristateBfGet(device, FPGA9010_BF_AXI_TOKELAU, &orgPinSelMask); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read GPIO tristate state"); + ADI_ERROR_RETURN(device->common.error.newAction); + + newPinSelMask = orgPinSelMask | pinSelMask; + + recoveryAction = fpga9010_AxiTokelauGpioTristateBfSet(device, FPGA9010_BF_AXI_TOKELAU, newPinSelMask); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write GPIO tristate value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_GpioInputDirGet(adi_fpga9010_Device_t *device, uint32_t *pinSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, pinSelMask); + + recoveryAction = fpga9010_AxiTokelauGpioTristateBfGet(device, FPGA9010_BF_AXI_TOKELAU, pinSelMask); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read GPIO tristate state"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_GpioOutputDirSet(adi_fpga9010_Device_t *device, uint32_t pinSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t orgPinSelMask = 0; + uint32_t newPinSelMask = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); + + if (pinSelMask > ADI_FPGA9010_GPIO_MAX_VALUE) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, pinSelMask, "pinSelMask cannot exceed max value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = fpga9010_AxiTokelauGpioTristateBfGet(device, FPGA9010_BF_AXI_TOKELAU, &orgPinSelMask); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read GPIO tristate state"); + ADI_ERROR_RETURN(device->common.error.newAction); + + newPinSelMask = ~(~orgPinSelMask | pinSelMask); + + recoveryAction = fpga9010_AxiTokelauGpioTristateBfSet(device, FPGA9010_BF_AXI_TOKELAU, newPinSelMask); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write GPIO tristate value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_GpioOutputDirGet(adi_fpga9010_Device_t *device, uint32_t *pinSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + uint32_t mask = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, pinSelMask); + + recoveryAction = fpga9010_AxiTokelauGpioTristateBfGet(device, FPGA9010_BF_AXI_TOKELAU, &mask); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read GPIO tristate state"); + ADI_ERROR_RETURN(device->common.error.newAction); + + //an output pin is represented as a 0 in the diredction register. + *pinSelMask = ~mask & ADI_FPGA9010_GPIO_MAX_VALUE; + + return recoveryAction; +} + +int32_t adi_fpga9010_GpioOeSet(adi_fpga9010_Device_t *device, adi_fpga9010_GpioPinType_e gpioPinType, uint32_t pinSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t orgPinSelMask = 0; + uint32_t newPinSelMask = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); + + if (pinSelMask > ADI_FPGA9010_GPIO_MAX_VALUE) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, pinSelMask, "pinSelMask cannot exceed max value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = fpga9010_AxiTokelauGpioTristateBfGet(device, FPGA9010_BF_AXI_TOKELAU, &orgPinSelMask); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read GPIO tristate state"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (gpioPinType == ADI_FPGA9010_GPIO_PIN_OUTPUT) + { + //output pins are 0 + newPinSelMask = orgPinSelMask & ~pinSelMask; + } + else + { + //input pins are 1 + newPinSelMask = orgPinSelMask | pinSelMask; + } + + recoveryAction = fpga9010_AxiTokelauGpioTristateBfSet(device, FPGA9010_BF_AXI_TOKELAU, newPinSelMask); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write GPIO tristate value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_GpioOeGet(adi_fpga9010_Device_t *device, uint32_t *pinSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, pinSelMask); + + recoveryAction = fpga9010_AxiTokelauGpioTristateBfGet(device, FPGA9010_BF_AXI_TOKELAU, pinSelMask); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read GPIO tristate value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_GpioWrite(adi_fpga9010_Device_t *device, uint32_t wrData) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); + + recoveryAction = fpga9010_AxiTokelauGpioOutputBfSet(device, FPGA9010_BF_AXI_TOKELAU, wrData); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write GPIO pin value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_GpioRead(adi_fpga9010_Device_t *device, uint32_t *rdData) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, rdData); + + recoveryAction = fpga9010_AxiTokelauGpioInputBfGet(device, FPGA9010_BF_AXI_TOKELAU, rdData); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not read GPIO pin value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_TddGpioSet(adi_fpga9010_Device_t *device, adi_fpga9010_TddModule_e tddModuleSel, adi_fpga9010_GpioPinSel_e gpioSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t txToOrxEnMask = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); + + if (gpioSel < ADI_FPGA9010_GPIO_00 || gpioSel > ADI_FPGA9010_GPIO_18) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, gpioSel, "Invalid GPIO selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (device->devStateInfo.gpioPinMode[(uint32_t)gpioSel] != ADI_FPGA9010_GPIO_MODE_NONE) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, gpioSel, "GPIO selected is currently in use."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + device->devStateInfo.gpioPinMode[(uint32_t)gpioSel] = ADI_FPGA9010_GPIO_MODE_TDD; + + switch (tddModuleSel) + { + case ADI_FPGA9010_ENABLE1CONTROL: + recoveryAction = fpga9010_AxiTokelauGpioSelTx1ToOrx1BfSet(device, FPGA9010_BF_AXI_TOKELAU, gpioSel); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not set Enable1 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9010_ENABLE2CONTROL: + recoveryAction = fpga9010_AxiTokelauGpioSelTx2ToOrx1BfSet(device, FPGA9010_BF_AXI_TOKELAU, gpioSel); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not set Enable2 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9010_ENABLE3CONTROL: + recoveryAction = fpga9010_AxiTokelauGpioSelTx1ToOrx2BfSet(device, FPGA9010_BF_AXI_TOKELAU, gpioSel); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not set Enable3 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9010_ENABLE4CONTROL: + recoveryAction = fpga9010_AxiTokelauGpioSelTx2ToOrx2BfSet(device, FPGA9010_BF_AXI_TOKELAU, gpioSel); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not set Enable4 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9010_SELECT1CONTROL: + recoveryAction = fpga9010_AxiTokelauGpioSelTx3ToOrx3BfSet(device, FPGA9010_BF_AXI_TOKELAU, gpioSel); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not set Select1 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9010_SELECT2CONTROL: + recoveryAction = fpga9010_AxiTokelauGpioSelTx4ToOrx3BfSet(device, FPGA9010_BF_AXI_TOKELAU, gpioSel); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not set Select2 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9010_SELECT3CONTROL: + recoveryAction = fpga9010_AxiTokelauGpioSelTx3ToOrx4BfSet(device, FPGA9010_BF_AXI_TOKELAU, gpioSel); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not set Select3 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9010_SELECT4CONTROL: + recoveryAction = fpga9010_AxiTokelauGpioSelTx4ToOrx4BfSet(device, FPGA9010_BF_AXI_TOKELAU, gpioSel); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not set Select4 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, gpioSel, "Invalid TDD module selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + txToOrxEnMask |= (1 << (uint32_t)gpioSel); + + recoveryAction = fpga9010_AxiTokelauGpioEnTxToOrxBfSet(device, FPGA9010_BF_AXI_TOKELAU, txToOrxEnMask); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not set Tx to ORx enable bitfield."); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_TddGpioGet(adi_fpga9010_Device_t *device, adi_fpga9010_TddModule_e tddModuleSel, adi_fpga9010_GpioPinSel_e *gpioSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, gpioSel); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); + + switch (tddModuleSel) + { + case ADI_FPGA9010_ENABLE1CONTROL: + recoveryAction = fpga9010_AxiTokelauGpioSelTx1ToOrx1BfGet(device, FPGA9010_BF_AXI_TOKELAU, (uint8_t *)gpioSel); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not get Enable1 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9010_ENABLE2CONTROL: + recoveryAction = fpga9010_AxiTokelauGpioSelTx2ToOrx1BfGet(device, FPGA9010_BF_AXI_TOKELAU, (uint8_t *)gpioSel); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not get Enable2 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9010_ENABLE3CONTROL: + recoveryAction = fpga9010_AxiTokelauGpioSelTx1ToOrx2BfGet(device, FPGA9010_BF_AXI_TOKELAU, (uint8_t *)gpioSel); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not get Enable3 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9010_ENABLE4CONTROL: + recoveryAction = fpga9010_AxiTokelauGpioSelTx2ToOrx2BfGet(device, FPGA9010_BF_AXI_TOKELAU, (uint8_t *)gpioSel); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not get Enable4 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9010_SELECT1CONTROL: + recoveryAction = fpga9010_AxiTokelauGpioSelTx3ToOrx3BfGet(device, FPGA9010_BF_AXI_TOKELAU, (uint8_t *)gpioSel); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not get Select1 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9010_SELECT2CONTROL: + recoveryAction = fpga9010_AxiTokelauGpioSelTx4ToOrx3BfGet(device, FPGA9010_BF_AXI_TOKELAU, (uint8_t *)gpioSel); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not get Select2 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9010_SELECT3CONTROL: + recoveryAction = fpga9010_AxiTokelauGpioSelTx3ToOrx4BfGet(device, FPGA9010_BF_AXI_TOKELAU, (uint8_t *)gpioSel); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not get Select3 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9010_SELECT4CONTROL: + recoveryAction = fpga9010_AxiTokelauGpioSelTx4ToOrx4BfGet(device, FPGA9010_BF_AXI_TOKELAU, (uint8_t *)gpioSel); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not get Select4 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, gpioSel, "Invalid TDD module selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_TddGpioAllClear(adi_fpga9010_Device_t *device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t i = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); + + for (i = 0; i < ADI_FPGA9010_GPIO_PINS; i++) + { + if (device->devStateInfo.gpioPinMode[i] == ADI_FPGA9010_GPIO_MODE_TDD) + { + device->devStateInfo.gpioPinMode[i] = ADI_FPGA9010_GPIO_MODE_NONE; + } + } + + recoveryAction = adi_hal_BbicRegisterWrite(device->common.devHalInfo, 0x43041080, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Error clearing gpio_sel_tx_to_orx_0 register."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_hal_BbicRegisterWrite(device->common.devHalInfo, 0x43041084, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, recoveryAction, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Error clearing gpio_sel_tx_to_orx_1 register."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_AxiTokelauGpioEnTxToOrxBfSet(device, FPGA9010_BF_AXI_TOKELAU, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, device->common.error.errCode, recoveryAction, NULL, "Could not clear Tx to ORx enable bitfield."); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_hal.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_hal.c new file mode 100644 index 0000000..3f69cf1 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_hal.c @@ -0,0 +1,232 @@ +/** +* \file adi_fpga9010_hal.c +* \brief Contains ADI Transceiver Hardware Abstraction functions +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +*/ + +/* Intermediate platform HAL layer maintained by Analog Devices */ + +#include "adi_fpga9010_user.h" +#include "adi_fpga9010_hal.h" +#include "adi_fpga9010_error.h" +#include "adi_platform.h" +#include "../../private/include/fpga9010_bf_axi_memory_pager.h" + + + +int32_t adi_fpga9010_RegisterFieldRead(adi_fpga9010_Device_t *device, + const uint32_t addr, + uint32_t *fieldVal, + uint32_t mask, + uint8_t startBit) +{ + uint32_t rdData = 0; + uint32_t regVal = 0; + //uint8_t i = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + ADI_NULL_PTR_RETURN(&device->common, fieldVal); + + adi_fpga9010_RegisterRead(device, addr, &rdData); + ADI_ERROR_RETURN(device->common.error.newAction); + + regVal = rdData; + *fieldVal = (regVal & mask) >> startBit; + + return (device->common.error.newAction); +} + + + +int32_t adi_fpga9010_RegisterFieldWrite(adi_fpga9010_Device_t *device, const uint32_t addr, uint32_t fieldVal, uint32_t mask, uint8_t startBit) +{ + UNUSED_PARA(startBit); + + uint32_t registerVal = 0; + uint32_t newRegVal = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + adi_fpga9010_RegisterRead(device, addr, ®isterVal); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* modify the register value*/ + newRegVal = (registerVal & ~mask) | fieldVal; + + /* write to the register with modified value*/ + adi_fpga9010_RegisterWrite(device, addr, newRegVal); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RegisterRead(adi_fpga9010_Device_t *device, uint32_t addr, uint32_t *data) +{ + int32_t halError = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + halError = adi_hal_BbicRegisterRead(device->common.devHalInfo, addr, data); + ADI_ERROR_REPORT(&device->common, 2, (adi_common_ErrSources_e)halError, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "FPGA AXI Reg Read error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + + +int32_t adi_fpga9010_RegisterWrite(adi_fpga9010_Device_t *device, uint32_t addr, uint32_t data) +{ + int32_t halError = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + halError = adi_hal_BbicRegisterWrite(device->common.devHalInfo, addr, data); + ADI_ERROR_REPORT(&device->common, 2, (adi_common_ErrSources_e)halError, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "FPGA Reg write error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + + +/** +* \brief used to page receive data from within the microzed. +* The Ads8 memory is 4GB and the microzed memory is 256Mb. +* To read all the Ads8 memory 16 pages would be necessary. +* memory reading is consecutive. +* +* each converter is assigned memory +* +*/ +int32_t adi_fpga9010_RamRead(adi_fpga9010_Device_t *device, const uint32_t ramAddress, uint32_t data[], uint32_t length) +{ + //todo add loop for length > memory page size + uint32_t remainingLength = length; + uint32_t endAddr = ramAddress + (length * sizeof(uint32_t)); + uint32_t currRamAddress = ramAddress; + uint32_t currLength = 0; + uint32_t dataOffset = 0; + + //ADS8 memory = 4GB divided by pagesize withb a max page size of 256MB + // offset into a page accessed via devuio1 + uint32_t offsetAddr = ramAddress & (device->memoryPageSize - 1); /* Mask off the upper bits in the addr addressed by Page ID */ + uint64_t pageSizeMask = ~((uint64_t)(device->memoryPageSize - 1)); /* Mask off the lower bits */ + uint64_t pageId = ((uint64_t)ramAddress & pageSizeMask); + uint64_t nextPageBoundary = pageId + device->memoryPageSize; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + if (ramAddress % sizeof(uint32_t) != 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, ramAddress, "RAM address must be word aligned"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + fpga9010_AxiMemoryPagerPageSizeBfSet(device, FPGA9010_BF_MEMORY_PAGE, (device->memoryPageSize - 1)); + ADI_ERROR_RETURN(device->common.error.newAction); + + do + { + fpga9010_AxiMemoryPagerPageIdBfSet(device, FPGA9010_BF_MEMORY_PAGE, pageId); + ADI_ERROR_RETURN(device->common.error.newAction); + + currLength = (uint32_t)((endAddr > nextPageBoundary) ? (nextPageBoundary - currRamAddress) / sizeof(uint32_t) : remainingLength); /* If we cross a page boundary, only send the difference */ + + adi_hal_BbicRegistersRead(device->common.devHalInfo, offsetAddr, &data[dataOffset], currLength); + + ADI_ERROR_RETURN(device->common.error.newAction); + + remainingLength -= currLength; + offsetAddr = 0; /* Except for the first access, every access will start at offset 0 */ + currRamAddress += currLength * sizeof(uint32_t); /* Move to where the next access will point to in RAM */ + pageId += ((uint64_t)currRamAddress & pageSizeMask); /* Move to the next page */ + dataOffset += currLength; /* Move to the next block in the data array */ + nextPageBoundary += device->memoryPageSize; + } while (remainingLength > 0); + + return (device->common.error.newAction); +} + + +/** +* \brief used to page write data within the microzed. +* The Ads8 memory is 4GB and the microzed memory is 256Mb. +* To write to all the Ads8 memory 16 pages would be necessary. +* memory reading is consecutive. +* +* each converter is assigned memory +* +*/ +int32_t adi_fpga9010_RamWrite(adi_fpga9010_Device_t *device, const uint32_t ramAddress, uint32_t data[], uint32_t length) +{ + //todo add loop for length > memory page size + uint32_t remainingLength = length; + uint32_t endAddr = ramAddress + (length * sizeof(uint32_t)); + uint32_t currRamAddress = ramAddress; + uint32_t currLength = 0; + uint32_t dataOffset = 0; + + //ADS8 memory = 4GB divided by pagesize withb a max page size of 256MB + // offset into a page accessed via devuio1 + uint32_t offsetAddr = ramAddress & (device->memoryPageSize - 1); /* Mask off the upper bits in the addr addressed by Page ID */ + uint64_t pageSizeMask = ~((uint64_t)(device->memoryPageSize - 1)); /* Mask off the lower bits */ + uint64_t pageId = ((uint64_t)ramAddress & pageSizeMask); + uint64_t nextPageBoundary = pageId + device->memoryPageSize; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + if (ramAddress % sizeof(uint32_t) != 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, ramAddress, "RAM address must be word aligned"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + fpga9010_AxiMemoryPagerPageSizeBfSet(device, FPGA9010_BF_MEMORY_PAGE, (device->memoryPageSize - 1)); + ADI_ERROR_RETURN(device->common.error.newAction); + + do + { + fpga9010_AxiMemoryPagerPageIdBfSet(device, FPGA9010_BF_MEMORY_PAGE, pageId); + ADI_ERROR_RETURN(device->common.error.newAction); + + currLength = (uint32_t)((endAddr > nextPageBoundary) ? (nextPageBoundary - currRamAddress) / sizeof(uint32_t) : remainingLength); /* If we cross a page boundary, only send the difference */ + + adi_hal_BbicRegistersWrite(device->common.devHalInfo, offsetAddr, &data[dataOffset], currLength); + + ADI_ERROR_RETURN(device->common.error.newAction); + + remainingLength -= currLength; + offsetAddr = 0; /* Except for the first access, every access will start at offset 0 */ + currRamAddress += currLength * sizeof(uint32_t); /* Move to where the next access will point to in RAM */ + pageId += ((uint64_t)currRamAddress & pageSizeMask); /* Move to the next page */ + dataOffset += currLength; /* Move to the next block in the data array */ + nextPageBoundary += device->memoryPageSize; + } while (remainingLength > 0); + + return (device->common.error.newAction); +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_jesd.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_jesd.c new file mode 100644 index 0000000..0f79db6 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_jesd.c @@ -0,0 +1,2648 @@ +/** + * \file: adi_fpga9010_jesd.c + * + * \brief Contains top level tx fpga9010 related functions + * + * FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9010_user.h" +#include "adi_fpga9010_jesd.h" +#include "adi_fpga9010.h" +#include "../../private/include/fpga9010_bf_jesd204_rx_lane_xbar.h" +#include "../../private/include/fpga9010_bf_jesd204_tx_lane_xbar.h" +#include "../../private/include/fpga9010_bf_xilinx_jesd204b.h" +#include "../../private/include/fpga9010_bf_jesd204_phy_tokelau_ads8.h" +#include "../../private/include/fpga9010_bf_xilinx_jesd204c.h" +#include "../../private/include/fpga9010_bf_jesd204b_sync_xbar.h" +#include "../../private/include/fpga9010_bf_jesd204_sysref_control.h" +#include "../../private/include/fpga9010_bf_jesd204_phy_tokelau_ads8.h" + +#include "../../private/include/fpga9010_jesd.h" + +int32_t adi_fpga9010_SerializerCfgSet(adi_fpga9010_Device_t *device, uint8_t laneSelMask, adi_fpga9010_SerializerCfg_t *serializerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t txRateEncodedValue = 0; + int32_t i = 0; + int32_t selectBit = 0; + + char serializerErrStr[][64] = { + "Error setting channel 0 cpll ref clk", + "Error setting channel 0 tx pll clk sel", + "Error setting channel 0 tx rate (final divider)", + "Error setting channel 0 tx polarity", + "Error setting channel 0 tx precursor", + "Error setting channel 0 tx postcursor", + "Error setting channel 0 tx diffCtrl", + "Error setting channel 0 tx encoder8b10bEnable", + "Error setting channel 0 tx powerDown" + }; + uint32_t laneNumPos = 22; + + typedef struct { + int32_t (*CpllRefClkSelBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + int32_t (*TxPllClkSelBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + int32_t (*TxRateBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + int32_t (*TxPolarityBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + int32_t (*TxPrecursorBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + int32_t (*TxPostcursorBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + int32_t (*TxDiffControlBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + int32_t (*Tx8b10bEnableBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + int32_t (*TxPowerdownBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + } fpgaSerializerSet_t; + + fpgaSerializerSet_t serializerSetFct[] = { + { + .CpllRefClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0CpllRefClkSelBfSet, + .TxPllClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0TxPllClkSelBfSet, + .TxRateBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0TxRateBfSet, + .TxPolarityBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0TxPolarityBfSet, + .TxPrecursorBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0TxPrecursorBfSet, + .TxPostcursorBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0TxPostcursorBfSet, + .TxDiffControlBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0TxDiffControlBfSet, + .Tx8b10bEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0Tx8b10bEnableBfSet, + .TxPowerdownBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0TxPowerdownBfSet + }, + { + .CpllRefClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1CpllRefClkSelBfSet, + .TxPllClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1TxPllClkSelBfSet, + .TxRateBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1TxRateBfSet, + .TxPolarityBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1TxPolarityBfSet, + .TxPrecursorBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1TxPrecursorBfSet, + .TxPostcursorBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1TxPostcursorBfSet, + .TxDiffControlBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1TxDiffControlBfSet, + .Tx8b10bEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1Tx8b10bEnableBfSet, + .TxPowerdownBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1TxPowerdownBfSet + }, + { + .CpllRefClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2CpllRefClkSelBfSet, + .TxPllClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2TxPllClkSelBfSet, + .TxRateBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2TxRateBfSet, + .TxPolarityBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2TxPolarityBfSet, + .TxPrecursorBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2TxPrecursorBfSet, + .TxPostcursorBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2TxPostcursorBfSet, + .TxDiffControlBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2TxDiffControlBfSet, + .Tx8b10bEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2Tx8b10bEnableBfSet, + .TxPowerdownBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2TxPowerdownBfSet + }, + { + .CpllRefClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3CpllRefClkSelBfSet, + .TxPllClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3TxPllClkSelBfSet, + .TxRateBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3TxRateBfSet, + .TxPolarityBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3TxPolarityBfSet, + .TxPrecursorBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3TxPrecursorBfSet, + .TxPostcursorBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3TxPostcursorBfSet, + .TxDiffControlBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3TxDiffControlBfSet, + .Tx8b10bEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3Tx8b10bEnableBfSet, + .TxPowerdownBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3TxPowerdownBfSet + }, + { + .CpllRefClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4CpllRefClkSelBfSet, + .TxPllClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4TxPllClkSelBfSet, + .TxRateBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4TxRateBfSet, + .TxPolarityBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4TxPolarityBfSet, + .TxPrecursorBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4TxPrecursorBfSet, + .TxPostcursorBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4TxPostcursorBfSet, + .TxDiffControlBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4TxDiffControlBfSet, + .Tx8b10bEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4Tx8b10bEnableBfSet, + .TxPowerdownBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4TxPowerdownBfSet + }, + { + .CpllRefClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5CpllRefClkSelBfSet, + .TxPllClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5TxPllClkSelBfSet, + .TxRateBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5TxRateBfSet, + .TxPolarityBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5TxPolarityBfSet, + .TxPrecursorBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5TxPrecursorBfSet, + .TxPostcursorBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5TxPostcursorBfSet, + .TxDiffControlBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5TxDiffControlBfSet, + .Tx8b10bEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5Tx8b10bEnableBfSet, + .TxPowerdownBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5TxPowerdownBfSet + }, + { + .CpllRefClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6CpllRefClkSelBfSet, + .TxPllClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6TxPllClkSelBfSet, + .TxRateBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6TxRateBfSet, + .TxPolarityBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6TxPolarityBfSet, + .TxPrecursorBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6TxPrecursorBfSet, + .TxPostcursorBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6TxPostcursorBfSet, + .TxDiffControlBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6TxDiffControlBfSet, + .Tx8b10bEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6Tx8b10bEnableBfSet, + .TxPowerdownBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6TxPowerdownBfSet + }, + { + .CpllRefClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7CpllRefClkSelBfSet, + .TxPllClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7TxPllClkSelBfSet, + .TxRateBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7TxRateBfSet, + .TxPolarityBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7TxPolarityBfSet, + .TxPrecursorBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7TxPrecursorBfSet, + .TxPostcursorBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7TxPostcursorBfSet, + .TxDiffControlBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7TxDiffControlBfSet, + .Tx8b10bEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7Tx8b10bEnableBfSet, + .TxPowerdownBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7TxPowerdownBfSet + } + }; + + uint32_t strIdx = 0; + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, serializerCfg); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + switch (serializerCfg->rate) + { + case 0: + txRateEncodedValue = 0; + break; + case 1: + txRateEncodedValue = 1; + break; + case 2: + txRateEncodedValue = 2; + break; + case 4: + txRateEncodedValue = 3; + break; + case 8: + txRateEncodedValue = 4; + break; + case 16: + txRateEncodedValue = 5; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, serializerCfg->rate, "Invalid tx rate (final divider) value"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + for (i = 0; i < ADI_FPGA9010_NUM_LANES; i++) + { + if (laneSelMask == 0) + { + break; /* Already processed all mask bits. */ + } + + selectBit = 1 << i; /* process each bit from right most to left most. */ + + if ((laneSelMask & selectBit) == 0) + { + continue; /* If current bit mask is not set then go to next bit mask */ + } + + laneSelMask &= ~selectBit; /* mark off the select bit that is currently processing. */ + + /* set cpll ref clk */ + strIdx = 0; + if (serializerSetFct[i].CpllRefClkSelBfSet != NULL) + { + recoveryAction = serializerSetFct[i].CpllRefClkSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, serializerCfg->cpllRefClkSel); + serializerErrStr[strIdx][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* set channel clk */ + strIdx++; + if (serializerSetFct[i].TxPllClkSelBfSet != NULL) + { + recoveryAction = serializerSetFct[i].TxPllClkSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, serializerCfg->txPllClkSel); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* set channel final divider */ + strIdx++; + if (serializerSetFct[i].TxRateBfSet != NULL) + { + recoveryAction = serializerSetFct[i].TxRateBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, txRateEncodedValue); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* set polarity */ + strIdx++; + if (serializerSetFct[i].TxPolarityBfSet != NULL) + { + recoveryAction = serializerSetFct[i].TxPolarityBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, serializerCfg->polarity); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* set precursor */ + strIdx++; + if (serializerSetFct[i].TxPrecursorBfSet != NULL) + { + recoveryAction = serializerSetFct[i].TxPrecursorBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, serializerCfg->precursor); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* set postcursor */ + strIdx++; + if (serializerSetFct[i].TxPostcursorBfSet != NULL) + { + recoveryAction = serializerSetFct[i].TxPostcursorBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, serializerCfg->postcursor); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* set differential control */ + strIdx++; + if (serializerSetFct[i].TxDiffControlBfSet != NULL) + { + recoveryAction = serializerSetFct[i].TxDiffControlBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, serializerCfg->diffCtrl); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* set 8b10b enable */ + strIdx++; + if (serializerSetFct[i].Tx8b10bEnableBfSet != NULL) + { + recoveryAction = serializerSetFct[i].Tx8b10bEnableBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, serializerCfg->encoder8b10bEnable); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + strIdx++; + + /* Write to DRP to set tx clkDiv25 */ + /* Manually shift the data so it falls within the mask bits*/ + adi_fpga9010_DrpWrite(device, ADI_FPGA9010_TXCLK25DIV_ADDRESS, i, serializerCfg->txClk25Div, ADI_FPGA9010_TXCLK25DIV_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_DrpWrite(device, ADI_FPGA9010_TXPI_CFG3_ADDRESS, i, serializerCfg->txPiCfg3, ADI_FPGA9010_TXPI_CFG3_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (device->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + adi_fpga9010_DrpWrite(device, ADI_FPGA9010_TXPHDLY_CFG1_ADDRESS, i, serializerCfg->txPhdlyCfg1, ADI_FPGA9010_TXPHDLY_CFG1_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_DrpWrite(device, ADI_FPGA9010_TX_PROGDIV_CFG_ADDRESS, i, serializerCfg->txProgdivCfg, ADI_FPGA9010_TX_PROGDIV_CFG_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* bring channel out of power down */ + if (serializerSetFct[i].TxPowerdownBfSet != NULL) + { + recoveryAction = serializerSetFct[i].TxPowerdownBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, serializerCfg->powerDown); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9010_SerializerCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_LaneSel_e laneSel, adi_fpga9010_SerializerCfg_t *serializerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t txPllClkSelReadBack = 0; + uint8_t txRateEncodedValue = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, serializerCfg); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + char serializerErrStr[][64] = { + "Error reading channel 0 cpll ref clk", + "Error reading channel 0 tx pll clk sel", + "Error reading channel 0 tx rate (final divider)", + "Error reading channel 0 tx polarity", + "Error reading channel 0 tx precursor", + "Error reading channel 0 tx postcursor", + "Error reading channel 0 tx diffCtrl", + "Error reading channel 0 tx encoder8b10bEnable", + "Error reading channel 0 tx powerDown" + }; + uint32_t laneNumPos = 22; + + typedef struct { + int32_t(*CpllRefClkSelBf) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + int32_t(*TxPllClkSelBf) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + int32_t(*TxRateBf) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + int32_t(*TxPolarityBf) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + int32_t(*TxPrecursorBf) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + int32_t(*TxPostcursorBf) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + int32_t(*TxDiffControlBf) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + int32_t(*Tx8b10bEnableBf) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + int32_t(*TxPowerdownBf) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + } fpgaSerializerGet_t; + + fpgaSerializerGet_t serializerGetFct[] = { + { + .CpllRefClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel0CpllRefClkSelBfGet, + .TxPllClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel0TxPllClkSelBfGet, + .TxRateBf = fpga9010_Jesd204PhyTokelauAds8Channel0TxRateBfGet, + .TxPolarityBf = fpga9010_Jesd204PhyTokelauAds8Channel0TxPolarityBfGet, + .TxPrecursorBf = fpga9010_Jesd204PhyTokelauAds8Channel0TxPrecursorBfGet, + .TxPostcursorBf = fpga9010_Jesd204PhyTokelauAds8Channel0TxPostcursorBfGet, + .TxDiffControlBf = fpga9010_Jesd204PhyTokelauAds8Channel0TxDiffControlBfGet, + .Tx8b10bEnableBf = fpga9010_Jesd204PhyTokelauAds8Channel0Tx8b10bEnableBfGet, + .TxPowerdownBf = fpga9010_Jesd204PhyTokelauAds8Channel0TxPowerdownBfGet + }, + { + .CpllRefClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel1CpllRefClkSelBfGet, + .TxPllClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel1TxPllClkSelBfGet, + .TxRateBf = fpga9010_Jesd204PhyTokelauAds8Channel1TxRateBfGet, + .TxPolarityBf = fpga9010_Jesd204PhyTokelauAds8Channel1TxPolarityBfGet, + .TxPrecursorBf = fpga9010_Jesd204PhyTokelauAds8Channel1TxPrecursorBfGet, + .TxPostcursorBf = fpga9010_Jesd204PhyTokelauAds8Channel1TxPostcursorBfGet, + .TxDiffControlBf = fpga9010_Jesd204PhyTokelauAds8Channel1TxDiffControlBfGet, + .Tx8b10bEnableBf = fpga9010_Jesd204PhyTokelauAds8Channel1Tx8b10bEnableBfGet, + .TxPowerdownBf = fpga9010_Jesd204PhyTokelauAds8Channel1TxPowerdownBfGet + }, + { + .CpllRefClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel2CpllRefClkSelBfGet, + .TxPllClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel2TxPllClkSelBfGet, + .TxRateBf = fpga9010_Jesd204PhyTokelauAds8Channel2TxRateBfGet, + .TxPolarityBf = fpga9010_Jesd204PhyTokelauAds8Channel2TxPolarityBfGet, + .TxPrecursorBf = fpga9010_Jesd204PhyTokelauAds8Channel2TxPrecursorBfGet, + .TxPostcursorBf = fpga9010_Jesd204PhyTokelauAds8Channel2TxPostcursorBfGet, + .TxDiffControlBf = fpga9010_Jesd204PhyTokelauAds8Channel2TxDiffControlBfGet, + .Tx8b10bEnableBf = fpga9010_Jesd204PhyTokelauAds8Channel2Tx8b10bEnableBfGet, + .TxPowerdownBf = fpga9010_Jesd204PhyTokelauAds8Channel2TxPowerdownBfGet + }, + { + .CpllRefClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel3CpllRefClkSelBfGet, + .TxPllClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel3TxPllClkSelBfGet, + .TxRateBf = fpga9010_Jesd204PhyTokelauAds8Channel3TxRateBfGet, + .TxPolarityBf = fpga9010_Jesd204PhyTokelauAds8Channel3TxPolarityBfGet, + .TxPrecursorBf = fpga9010_Jesd204PhyTokelauAds8Channel3TxPrecursorBfGet, + .TxPostcursorBf = fpga9010_Jesd204PhyTokelauAds8Channel3TxPostcursorBfGet, + .TxDiffControlBf = fpga9010_Jesd204PhyTokelauAds8Channel3TxDiffControlBfGet, + .Tx8b10bEnableBf = fpga9010_Jesd204PhyTokelauAds8Channel3Tx8b10bEnableBfGet, + .TxPowerdownBf = fpga9010_Jesd204PhyTokelauAds8Channel3TxPowerdownBfGet + }, + { + .CpllRefClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel4CpllRefClkSelBfGet, + .TxPllClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel4TxPllClkSelBfGet, + .TxRateBf = fpga9010_Jesd204PhyTokelauAds8Channel4TxRateBfGet, + .TxPolarityBf = fpga9010_Jesd204PhyTokelauAds8Channel4TxPolarityBfGet, + .TxPrecursorBf = fpga9010_Jesd204PhyTokelauAds8Channel4TxPrecursorBfGet, + .TxPostcursorBf = fpga9010_Jesd204PhyTokelauAds8Channel4TxPostcursorBfGet, + .TxDiffControlBf = fpga9010_Jesd204PhyTokelauAds8Channel4TxDiffControlBfGet, + .Tx8b10bEnableBf = fpga9010_Jesd204PhyTokelauAds8Channel4Tx8b10bEnableBfGet, + .TxPowerdownBf = fpga9010_Jesd204PhyTokelauAds8Channel4TxPowerdownBfGet + }, + { + .CpllRefClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel5CpllRefClkSelBfGet, + .TxPllClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel5TxPllClkSelBfGet, + .TxRateBf = fpga9010_Jesd204PhyTokelauAds8Channel5TxRateBfGet, + .TxPolarityBf = fpga9010_Jesd204PhyTokelauAds8Channel5TxPolarityBfGet, + .TxPrecursorBf = fpga9010_Jesd204PhyTokelauAds8Channel5TxPrecursorBfGet, + .TxPostcursorBf = fpga9010_Jesd204PhyTokelauAds8Channel5TxPostcursorBfGet, + .TxDiffControlBf = fpga9010_Jesd204PhyTokelauAds8Channel5TxDiffControlBfGet, + .Tx8b10bEnableBf = fpga9010_Jesd204PhyTokelauAds8Channel5Tx8b10bEnableBfGet, + .TxPowerdownBf = fpga9010_Jesd204PhyTokelauAds8Channel5TxPowerdownBfGet + }, + { + .CpllRefClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel6CpllRefClkSelBfGet, + .TxPllClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel6TxPllClkSelBfGet, + .TxRateBf = fpga9010_Jesd204PhyTokelauAds8Channel6TxRateBfGet, + .TxPolarityBf = fpga9010_Jesd204PhyTokelauAds8Channel6TxPolarityBfGet, + .TxPrecursorBf = fpga9010_Jesd204PhyTokelauAds8Channel6TxPrecursorBfGet, + .TxPostcursorBf = fpga9010_Jesd204PhyTokelauAds8Channel6TxPostcursorBfGet, + .TxDiffControlBf = fpga9010_Jesd204PhyTokelauAds8Channel6TxDiffControlBfGet, + .Tx8b10bEnableBf = fpga9010_Jesd204PhyTokelauAds8Channel6Tx8b10bEnableBfGet, + .TxPowerdownBf = fpga9010_Jesd204PhyTokelauAds8Channel6TxPowerdownBfGet + }, + { + .CpllRefClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel7CpllRefClkSelBfGet, + .TxPllClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel7TxPllClkSelBfGet, + .TxRateBf = fpga9010_Jesd204PhyTokelauAds8Channel7TxRateBfGet, + .TxPolarityBf = fpga9010_Jesd204PhyTokelauAds8Channel7TxPolarityBfGet, + .TxPrecursorBf = fpga9010_Jesd204PhyTokelauAds8Channel7TxPrecursorBfGet, + .TxPostcursorBf = fpga9010_Jesd204PhyTokelauAds8Channel7TxPostcursorBfGet, + .TxDiffControlBf = fpga9010_Jesd204PhyTokelauAds8Channel7TxDiffControlBfGet, + .Tx8b10bEnableBf = fpga9010_Jesd204PhyTokelauAds8Channel7Tx8b10bEnableBfGet, + .TxPowerdownBf = fpga9010_Jesd204PhyTokelauAds8Channel7TxPowerdownBfGet + } + }; + uint32_t laneIdx = 0; + + switch (laneSel) + { + case ADI_FPGA9010_LANE_0: + laneIdx = 0; + break; + case ADI_FPGA9010_LANE_1: + laneIdx = 1; + break; + case ADI_FPGA9010_LANE_2: + laneIdx = 2; + break; + case ADI_FPGA9010_LANE_3: + laneIdx = 3; + break; + case ADI_FPGA9010_LANE_4: + laneIdx = 4; + break; + case ADI_FPGA9010_LANE_5: + laneIdx = 5; + break; + case ADI_FPGA9010_LANE_6: + laneIdx = 6; + break; + case ADI_FPGA9010_LANE_7: + laneIdx = 7; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, laneSelMask, "Invalid lane selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + /* Get cpll ref clk */ + if (serializerGetFct[laneIdx].CpllRefClkSelBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].CpllRefClkSelBf(device, FPGA9010_BF_TOKELAU_JESD_PHY, &serializerCfg->cpllRefClkSel); + serializerErrStr[0][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get channel clk */ + if (serializerGetFct[laneIdx].TxPllClkSelBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].TxPllClkSelBf(device, FPGA9010_BF_TOKELAU_JESD_PHY, &txPllClkSelReadBack); + serializerErrStr[1][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[1]); + ADI_ERROR_RETURN(device->common.error.newAction); + serializerCfg->txPllClkSel = (adi_fpga9010_LaneClkSel_e) txPllClkSelReadBack; + } + + /* Get channel final divider */ + if (serializerGetFct[laneIdx].TxRateBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].TxRateBf(device, FPGA9010_BF_TOKELAU_JESD_PHY, &txRateEncodedValue); + serializerErrStr[2][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[2]); + ADI_ERROR_RETURN(device->common.error.newAction); + if (txRateEncodedValue > 5) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Invalid tx rate (final divider) value read from FPGA"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + serializerCfg->rate = (1 << txRateEncodedValue) / 2; + } + + /* Get polarity */ + if (serializerGetFct[laneIdx].TxPolarityBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].TxPolarityBf(device, FPGA9010_BF_TOKELAU_JESD_PHY, &serializerCfg->polarity); + serializerErrStr[3][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[3]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get precursor */ + if (serializerGetFct[laneIdx].TxPrecursorBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].TxPrecursorBf(device, FPGA9010_BF_TOKELAU_JESD_PHY, &serializerCfg->precursor); + serializerErrStr[4][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[4]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get postcursor */ + if (serializerGetFct[laneIdx].TxPostcursorBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].TxPostcursorBf(device, FPGA9010_BF_TOKELAU_JESD_PHY, &serializerCfg->postcursor); + serializerErrStr[5][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[5]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get differential control */ + if (serializerGetFct[laneIdx].TxDiffControlBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].TxDiffControlBf(device, FPGA9010_BF_TOKELAU_JESD_PHY, &serializerCfg->diffCtrl); + serializerErrStr[6][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[6]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get 8b10b enable */ + if (serializerGetFct[laneIdx].Tx8b10bEnableBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].Tx8b10bEnableBf(device, FPGA9010_BF_TOKELAU_JESD_PHY, &serializerCfg->encoder8b10bEnable); + serializerErrStr[7][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[7]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get power down status */ + if (serializerGetFct[laneIdx].TxPowerdownBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].TxPowerdownBf(device, FPGA9010_BF_TOKELAU_JESD_PHY, &serializerCfg->powerDown); + serializerErrStr[8][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[8]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_SerializerResetSet(adi_fpga9010_Device_t *device, uint8_t laneSelMask, uint8_t resetVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + char serializerErrStr[][64] = { + "Error resetting channel 0 tx" + }; + uint32_t laneNumPos = 24; + + typedef struct { + int32_t(*TxResetBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + } fpgaTxResetSet_t; + + fpgaTxResetSet_t txResetSetFct[] = { + { .TxResetBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0TxResetBfSet }, + { .TxResetBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1TxResetBfSet }, + { .TxResetBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2TxResetBfSet }, + { .TxResetBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3TxResetBfSet }, + { .TxResetBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4TxResetBfSet }, + { .TxResetBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5TxResetBfSet }, + { .TxResetBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6TxResetBfSet }, + { .TxResetBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7TxResetBfSet } + }; + int32_t i = 0; + int32_t selectBit = 0; + int32_t loopCnt = sizeof(txResetSetFct) / sizeof(fpgaTxResetSet_t); + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + for (i = 0; i < loopCnt; i++) + { + if (laneSelMask == 0) + { + break; /* Already processed all mask bits. */ + } + + selectBit = 1 << i; /* process each bit from right most to left most. */ + + if ((laneSelMask & selectBit) == 0) + { + continue; /* If current bit mask is not set then go to next bit mask */ + } + + laneSelMask &= ~selectBit; /* mark off the select bit that is currently processing. */ + + if (txResetSetFct[i].TxResetBfSet != NULL) + { + recoveryAction = txResetSetFct[i].TxResetBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (resetVal & 0x01)); + serializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9010_SerializerResetDoneGet(adi_fpga9010_Device_t *device, uint8_t *txResetDone) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t resetDoneReadBack = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, txResetDone); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + *txResetDone = 0; + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel0TxResetDoneBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &resetDoneReadBack); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading channel 0 tx reset done"); + ADI_ERROR_RETURN(device->common.error.newAction); + *txResetDone |= (resetDoneReadBack & 0x01) << 0; + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel1TxResetDoneBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &resetDoneReadBack); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading channel 1 tx reset done"); + ADI_ERROR_RETURN(device->common.error.newAction); + *txResetDone |= (resetDoneReadBack & 0x01) << 1; + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel2TxResetDoneBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &resetDoneReadBack); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading channel 2 tx reset done"); + ADI_ERROR_RETURN(device->common.error.newAction); + *txResetDone |= (resetDoneReadBack & 0x01) << 2; + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel3TxResetDoneBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &resetDoneReadBack); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading channel 3 tx reset done"); + ADI_ERROR_RETURN(device->common.error.newAction); + *txResetDone |= (resetDoneReadBack & 0x01) << 3; + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel4TxResetDoneBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &resetDoneReadBack); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading channel 4 tx reset done"); + ADI_ERROR_RETURN(device->common.error.newAction); + *txResetDone |= (resetDoneReadBack & 0x01) << 4; + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel5TxResetDoneBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &resetDoneReadBack); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading channel 5 tx reset done"); + ADI_ERROR_RETURN(device->common.error.newAction); + *txResetDone |= (resetDoneReadBack & 0x01) << 5; + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel6TxResetDoneBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &resetDoneReadBack); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading channel 6 tx reset done"); + ADI_ERROR_RETURN(device->common.error.newAction); + *txResetDone |= (resetDoneReadBack & 0x01) << 6; + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel7TxResetDoneBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &resetDoneReadBack); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading channel 7 tx reset done"); + ADI_ERROR_RETURN(device->common.error.newAction); + *txResetDone |= (resetDoneReadBack & 0x01) << 7; + + return recoveryAction; +} + +int32_t adi_fpga9010_LaneCpllPdSet(adi_fpga9010_Device_t *device, uint8_t laneSelMask, uint8_t pdVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + char serializerErrStr[][64] = { + "Error setting channel 0 cpll pd bit" + }; + uint32_t laneNumPos = 22; + + typedef struct { + int32_t(*CpllPdBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + } fpgaCpllPdBfSet_t; + + fpgaCpllPdBfSet_t cpllPdBfSetFct[] = { + { .CpllPdBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0CpllPdBfSet }, + { .CpllPdBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1CpllPdBfSet }, + { .CpllPdBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2CpllPdBfSet }, + { .CpllPdBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3CpllPdBfSet }, + { .CpllPdBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4CpllPdBfSet }, + { .CpllPdBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5CpllPdBfSet }, + { .CpllPdBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6CpllPdBfSet }, + { .CpllPdBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7CpllPdBfSet } + }; + int32_t i = 0; + int32_t selectBit = 0; + int32_t loopCnt = sizeof(cpllPdBfSetFct) / sizeof(fpgaCpllPdBfSet_t); + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + for (i = 0; i < loopCnt; i++) + { + if (laneSelMask == 0) + { + break; /* Already processed all mask bits. */ + } + + selectBit = 1 << i; /* process each bit from right most to left most. */ + + if ((laneSelMask & selectBit) == 0) + { + continue; /* If current bit mask is not set then go to next bit mask */ + } + + laneSelMask &= ~selectBit; /* mark off the select bit that is currently processing. */ + + if (cpllPdBfSetFct[i].CpllPdBfSet != NULL) + { + recoveryAction = cpllPdBfSetFct[i].CpllPdBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, pdVal); + serializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9010_DeserializerCfgSet(adi_fpga9010_Device_t *device, uint8_t laneSelMask, adi_fpga9010_DeserializerCfg_t *deserializerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxRateEncodedValue = 0; + + int32_t i = 0; + int32_t selectBit = 0; + + char deserializerErrStr[][64] = { + "Error setting channel 0 rx pll clk sel", + "Error setting channel 0 rx rate (final divider)", + "Error setting channel 0 rx polarity", + "Error setting channel 0 rx encoder8b10bEnable", + "Error setting channel 0 rx DFE/LPMr", + "Error setting channel 0 rx power down" + }; + uint32_t laneNumPos = 22; + + typedef struct { + int32_t(*RxPllClkSelBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + int32_t(*RxRateBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + int32_t(*RxPolarityBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + int32_t(*Rx8b10bEnableBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + int32_t(*RxDfeLpmEnBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + int32_t(*RxPowerdownBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + } fpgaDeserializerSet_t; + + fpgaDeserializerSet_t deserializerSetFct[] = { + { + .RxPllClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0RxPllClkSelBfSet, + .RxRateBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0RxRateBfSet, + .RxPolarityBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0RxPolarityBfSet, + .Rx8b10bEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0Rx8b10bEnableBfSet, + .RxDfeLpmEnBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmEnBfSet, + .RxPowerdownBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0RxPowerdownBfSet + }, + { + .RxPllClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1RxPllClkSelBfSet, + .RxRateBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1RxRateBfSet, + .RxPolarityBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1RxPolarityBfSet, + .Rx8b10bEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1Rx8b10bEnableBfSet, + .RxDfeLpmEnBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmEnBfSet, + .RxPowerdownBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1RxPowerdownBfSet + }, + { + .RxPllClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2RxPllClkSelBfSet, + .RxRateBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2RxRateBfSet, + .RxPolarityBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2RxPolarityBfSet, + .Rx8b10bEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2Rx8b10bEnableBfSet, + .RxDfeLpmEnBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmEnBfSet, + .RxPowerdownBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2RxPowerdownBfSet + }, + { + .RxPllClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3RxPllClkSelBfSet, + .RxRateBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3RxRateBfSet, + .RxPolarityBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3RxPolarityBfSet, + .Rx8b10bEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3Rx8b10bEnableBfSet, + .RxDfeLpmEnBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmEnBfSet, + .RxPowerdownBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3RxPowerdownBfSet + }, + { + .RxPllClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4RxPllClkSelBfSet, + .RxRateBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4RxRateBfSet, + .RxPolarityBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4RxPolarityBfSet, + .Rx8b10bEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4Rx8b10bEnableBfSet, + .RxDfeLpmEnBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmEnBfSet, + .RxPowerdownBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4RxPowerdownBfSet + }, + { + .RxPllClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5RxPllClkSelBfSet, + .RxRateBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5RxRateBfSet, + .RxPolarityBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5RxPolarityBfSet, + .Rx8b10bEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5Rx8b10bEnableBfSet, + .RxDfeLpmEnBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmEnBfSet, + .RxPowerdownBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5RxPowerdownBfSet + }, + { + .RxPllClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6RxPllClkSelBfSet, + .RxRateBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6RxRateBfSet, + .RxPolarityBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6RxPolarityBfSet, + .Rx8b10bEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6Rx8b10bEnableBfSet, + .RxDfeLpmEnBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmEnBfSet, + .RxPowerdownBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6RxPowerdownBfSet + }, + { + .RxPllClkSelBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7RxPllClkSelBfSet, + .RxRateBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7RxRateBfSet, + .RxPolarityBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7RxPolarityBfSet, + .Rx8b10bEnableBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7Rx8b10bEnableBfSet, + .RxDfeLpmEnBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmEnBfSet, + .RxPowerdownBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7RxPowerdownBfSet + } + }; + + uint32_t strIdx = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, deserializerCfg); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + switch (deserializerCfg->rate) + { + case 0: + rxRateEncodedValue = 0; + break; + case 1: + rxRateEncodedValue = 1; + break; + case 2: + rxRateEncodedValue = 2; + break; + case 4: + rxRateEncodedValue = 3; + break; + case 8: + rxRateEncodedValue = 4; + break; + case 16: + rxRateEncodedValue = 5; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, deserializerCfg->rate, "Invalid rx rate (final divider) value"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + for (i = 0; i < ADI_FPGA9010_NUM_LANES; i++) + { + if (laneSelMask == 0) + { + break; /* Already processed all mask bits. */ + } + + selectBit = 1 << i; /* process each bit from right most to left most. */ + + if ((laneSelMask & selectBit) == 0) + { + continue; /* If current bit mask is not set then go to next bit mask */ + } + + laneSelMask &= ~selectBit; /* mark off the select bit that is currently processing. */ + + /* set channel clk */ + strIdx = 0; + if (deserializerSetFct[i].RxPllClkSelBfSet != NULL) + { + recoveryAction = deserializerSetFct[i].RxPllClkSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, deserializerCfg->rxPllClkSel); + deserializerErrStr[strIdx][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)deserializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* set channel final divider */ + strIdx++; + if (deserializerSetFct[i].RxRateBfSet != NULL) + { + recoveryAction = deserializerSetFct[i].RxRateBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, rxRateEncodedValue); + deserializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)deserializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* set polarity */ + strIdx++; + if (deserializerSetFct[i].RxPolarityBfSet != NULL) + { + recoveryAction = deserializerSetFct[i].RxPolarityBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, deserializerCfg->polarity); + deserializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)deserializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* set 8b10b enable */ + strIdx++; + if (deserializerSetFct[i].Rx8b10bEnableBfSet != NULL) + { + recoveryAction = deserializerSetFct[i].Rx8b10bEnableBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, deserializerCfg->encoder8b10bEnable); + deserializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)deserializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* set dfe_lpm enable */ + strIdx++; + if (deserializerSetFct[i].RxDfeLpmEnBfSet != NULL) + { + recoveryAction = deserializerSetFct[i].RxDfeLpmEnBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, deserializerCfg->rxDfeLpmEn); + deserializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)deserializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Write to DRP to set tx clkDiv25 */ + /* Address, mask come from FPGA User Guide Appendix A */ + adi_fpga9010_DrpWrite(device, ADI_FPGA9010_RXCLK25DIV_ADDRESS, i, deserializerCfg->rxClk25Div, ADI_FPGA9010_RXCLK25DIV_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_DrpWrite(device, ADI_FPGA9010_PMA_RSV1_ADDRESS, i, deserializerCfg->pmaRsv1, ADI_FPGA9010_PMA_RSV1_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_DrpWrite(device, ADI_FPGA9010_RXCDR_CFG2_ADDRESS, i, deserializerCfg->rxCdrCfg2, ADI_FPGA9010_RXCDR_CFG2_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_DrpWrite(device, ADI_FPGA9010_RXDFE_GC_CFG1_ADDRESS, i, deserializerCfg->rxDfeGcCfg1, ADI_FPGA9010_RXDFE_GC_CFG1_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_DrpWrite(device, ADI_FPGA9010_RXPI_CFG4_ADDRESS, i, deserializerCfg->rxPiCfg4, ADI_FPGA9010_RXPI_CFG4_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_DrpWrite(device, ADI_FPGA9010_RXPI_CFG5_ADDRESS, i, deserializerCfg->rxPiCfg5, ADI_FPGA9010_RXPI_CFG5_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_DrpWrite(device, ADI_FPGA9010_RX_EN_HI_LR_ADDRESS, i, deserializerCfg->rxEnHiLr, ADI_FPGA9010_RX_EN_HI_LR_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_DrpWrite(device, ADI_FPGA9010_RX_WIDEMODE_CDR_ADDRESS, i, deserializerCfg->rxWidemodeCdr, ADI_FPGA9010_RX_WIDEMODE_CDR_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (device->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + adi_fpga9010_DrpWrite(device, ADI_FPGA9010_RX_PROGDIV_CFG_ADDRESS, i, deserializerCfg->rxProgdivCfg, ADI_FPGA9010_RX_PROGDIV_CFG_MASK); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* bring channel out of power down */ + strIdx++; + if (deserializerSetFct[i].RxPowerdownBfSet != NULL) + { + recoveryAction = deserializerSetFct[i].RxPowerdownBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, deserializerCfg->powerDown); + deserializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)deserializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9010_DeserializerCfgGet(adi_fpga9010_Device_t *device, const adi_fpga9010_LaneSel_e laneSel, adi_fpga9010_DeserializerCfg_t *deserializerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxPllClkSelReadBack = 0; + uint8_t rxRateEncodedValue = 0; + + char deserializerErrStr[][64] = { + "Error reading channel 0 rx pll clk sel", + "Error reading channel 0 rx rate (final divider)", + "Error reading channel 0 rx polarity", + "Error reading channel 0 rx encoder8b10bEnable", + "Error reading channel 0 rx DFE/LPM", + "Error reading channel 0 rx power down" + }; + uint32_t laneNumPos = 22; + + typedef struct { + int32_t(*RxPllClkSelBf) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + int32_t(*RxRateBf) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + int32_t(*RxPolarityBf) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + int32_t(*Rx8b10bEnableBf) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + int32_t(*RxDfeLpmEnBf) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + int32_t(*RxPowerdownBf) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + } fpgaDeserializerGet_t; + + fpgaDeserializerGet_t deserializerGetFct[] = { + { + .RxPllClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel0RxPllClkSelBfGet, + .RxRateBf = fpga9010_Jesd204PhyTokelauAds8Channel0RxRateBfGet, + .RxPolarityBf = fpga9010_Jesd204PhyTokelauAds8Channel0RxPolarityBfGet, + .Rx8b10bEnableBf = fpga9010_Jesd204PhyTokelauAds8Channel0Rx8b10bEnableBfGet, + .RxDfeLpmEnBf = fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmEnBfGet, + .RxPowerdownBf = fpga9010_Jesd204PhyTokelauAds8Channel0RxPowerdownBfGet + }, + { + .RxPllClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel1RxPllClkSelBfGet, + .RxRateBf = fpga9010_Jesd204PhyTokelauAds8Channel1RxRateBfGet, + .RxPolarityBf = fpga9010_Jesd204PhyTokelauAds8Channel1RxPolarityBfGet, + .Rx8b10bEnableBf = fpga9010_Jesd204PhyTokelauAds8Channel1Rx8b10bEnableBfGet, + .RxDfeLpmEnBf = fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmEnBfGet, + .RxPowerdownBf = fpga9010_Jesd204PhyTokelauAds8Channel1RxPowerdownBfGet + }, + { + .RxPllClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel2RxPllClkSelBfGet, + .RxRateBf = fpga9010_Jesd204PhyTokelauAds8Channel2RxRateBfGet, + .RxPolarityBf = fpga9010_Jesd204PhyTokelauAds8Channel2RxPolarityBfGet, + .Rx8b10bEnableBf = fpga9010_Jesd204PhyTokelauAds8Channel2Rx8b10bEnableBfGet, + .RxDfeLpmEnBf = fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmEnBfGet, + .RxPowerdownBf = fpga9010_Jesd204PhyTokelauAds8Channel2RxPowerdownBfGet + }, + { + .RxPllClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel3RxPllClkSelBfGet, + .RxRateBf = fpga9010_Jesd204PhyTokelauAds8Channel3RxRateBfGet, + .RxPolarityBf = fpga9010_Jesd204PhyTokelauAds8Channel3RxPolarityBfGet, + .Rx8b10bEnableBf = fpga9010_Jesd204PhyTokelauAds8Channel3Rx8b10bEnableBfGet, + .RxDfeLpmEnBf = fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmEnBfGet, + .RxPowerdownBf = fpga9010_Jesd204PhyTokelauAds8Channel3RxPowerdownBfGet + }, + { + .RxPllClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel4RxPllClkSelBfGet, + .RxRateBf = fpga9010_Jesd204PhyTokelauAds8Channel4RxRateBfGet, + .RxPolarityBf = fpga9010_Jesd204PhyTokelauAds8Channel4RxPolarityBfGet, + .Rx8b10bEnableBf = fpga9010_Jesd204PhyTokelauAds8Channel4Rx8b10bEnableBfGet, + .RxDfeLpmEnBf = fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmEnBfGet, + .RxPowerdownBf = fpga9010_Jesd204PhyTokelauAds8Channel4RxPowerdownBfGet + }, + { + .RxPllClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel5RxPllClkSelBfGet, + .RxRateBf = fpga9010_Jesd204PhyTokelauAds8Channel5RxRateBfGet, + .RxPolarityBf = fpga9010_Jesd204PhyTokelauAds8Channel5RxPolarityBfGet, + .Rx8b10bEnableBf = fpga9010_Jesd204PhyTokelauAds8Channel5Rx8b10bEnableBfGet, + .RxDfeLpmEnBf = fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmEnBfGet, + .RxPowerdownBf = fpga9010_Jesd204PhyTokelauAds8Channel5RxPowerdownBfGet + }, + { + .RxPllClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel6RxPllClkSelBfGet, + .RxRateBf = fpga9010_Jesd204PhyTokelauAds8Channel6RxRateBfGet, + .RxPolarityBf = fpga9010_Jesd204PhyTokelauAds8Channel6RxPolarityBfGet, + .Rx8b10bEnableBf = fpga9010_Jesd204PhyTokelauAds8Channel6Rx8b10bEnableBfGet, + .RxDfeLpmEnBf = fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmEnBfGet, + .RxPowerdownBf = fpga9010_Jesd204PhyTokelauAds8Channel6RxPowerdownBfGet + }, + { + .RxPllClkSelBf = fpga9010_Jesd204PhyTokelauAds8Channel7RxPllClkSelBfGet, + .RxRateBf = fpga9010_Jesd204PhyTokelauAds8Channel7RxRateBfGet, + .RxPolarityBf = fpga9010_Jesd204PhyTokelauAds8Channel7RxPolarityBfGet, + .Rx8b10bEnableBf = fpga9010_Jesd204PhyTokelauAds8Channel7Rx8b10bEnableBfGet, + .RxDfeLpmEnBf = fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmEnBfGet, + .RxPowerdownBf = fpga9010_Jesd204PhyTokelauAds8Channel7RxPowerdownBfGet + } + }; + uint32_t laneIdx = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, deserializerCfg); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + switch (laneSel) + { + case ADI_FPGA9010_LANE_0: + laneIdx = 0; + break; + case ADI_FPGA9010_LANE_1: + laneIdx = 1; + break; + case ADI_FPGA9010_LANE_2: + laneIdx = 2; + break; + case ADI_FPGA9010_LANE_3: + laneIdx = 3; + break; + case ADI_FPGA9010_LANE_4: + laneIdx = 4; + break; + case ADI_FPGA9010_LANE_5: + laneIdx = 5; + break; + case ADI_FPGA9010_LANE_6: + laneIdx = 6; + break; + case ADI_FPGA9010_LANE_7: + laneIdx = 7; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, laneSel, "Invalid lane selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + /* Get channel clk */ + if (deserializerGetFct[laneIdx].RxPllClkSelBf != NULL) + { + recoveryAction = deserializerGetFct[laneIdx].RxPllClkSelBf(device, FPGA9010_BF_TOKELAU_JESD_PHY, &rxPllClkSelReadBack); + deserializerCfg->rxPllClkSel = (adi_fpga9010_LaneClkSel_e) rxPllClkSelReadBack; + deserializerErrStr[0][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)deserializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get channel final divider */ + if (deserializerGetFct[laneIdx].RxRateBf != NULL) + { + recoveryAction = deserializerGetFct[laneIdx].RxRateBf(device, FPGA9010_BF_TOKELAU_JESD_PHY, &rxRateEncodedValue); + deserializerErrStr[1][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)deserializerErrStr[1]); + ADI_ERROR_RETURN(device->common.error.newAction); + if (rxRateEncodedValue > 5) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Invalid rx rate (final divider) value read from FPGA"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + deserializerCfg->rate = (1 << rxRateEncodedValue) / 2; + } + + /* Get polarity */ + if (deserializerGetFct[laneIdx].RxPolarityBf != NULL) + { + + recoveryAction = deserializerGetFct[laneIdx].RxPolarityBf(device, FPGA9010_BF_TOKELAU_JESD_PHY, &deserializerCfg->polarity); + deserializerErrStr[2][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)deserializerErrStr[2]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get 8b10b enable */ + if (deserializerGetFct[laneIdx].Rx8b10bEnableBf != NULL) + { + recoveryAction = deserializerGetFct[laneIdx].Rx8b10bEnableBf(device, FPGA9010_BF_TOKELAU_JESD_PHY, &deserializerCfg->encoder8b10bEnable); + deserializerErrStr[3][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)deserializerErrStr[3]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* set dfe_lpm enable */ + if (deserializerGetFct[laneIdx].RxDfeLpmEnBf != NULL) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmEnBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &deserializerCfg->rxDfeLpmEn); + deserializerErrStr[4][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)deserializerErrStr[4]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* bring channel out of power down */ + if (deserializerGetFct[laneIdx].RxPowerdownBf != NULL) + { + recoveryAction = deserializerGetFct[laneIdx].RxPowerdownBf(device, FPGA9010_BF_TOKELAU_JESD_PHY, &deserializerCfg->powerDown); + deserializerErrStr[5][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)deserializerErrStr[5]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_DeserializerResetSet(adi_fpga9010_Device_t *device, uint8_t laneSelMask, uint8_t resetVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + char serializerErrStr[][64] = { + "Error resetting channel 0 rx" + }; + uint32_t laneNumPos = 24; + + typedef struct { + int32_t(*RxResetBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + } fpgaRxResetBfSet_t; + + fpgaRxResetBfSet_t rxResetBfSetFct[] = { + { .RxResetBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0RxResetBfSet }, + { .RxResetBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1RxResetBfSet }, + { .RxResetBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2RxResetBfSet }, + { .RxResetBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3RxResetBfSet }, + { .RxResetBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4RxResetBfSet }, + { .RxResetBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5RxResetBfSet }, + { .RxResetBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6RxResetBfSet }, + { .RxResetBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7RxResetBfSet } + }; + int32_t i = 0; + int32_t selectBit = 0; + int32_t loopCnt = sizeof(rxResetBfSetFct) / sizeof(fpgaRxResetBfSet_t); + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + for (i = 0; i < loopCnt; i++) + { + if (laneSelMask == 0) + { + break; /* Already processed all mask bits. */ + } + + selectBit = 1 << i; /* process each bit from right most to left most. */ + + if ((laneSelMask & selectBit) == 0) + { + continue; /* If current bit mask is not set then go to next bit mask */ + } + + laneSelMask &= ~selectBit; /* mark off the select bit that is currently processing. */ + + if (rxResetBfSetFct[i].RxResetBfSet != NULL) + { + recoveryAction = rxResetBfSetFct[i].RxResetBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (resetVal & 0x01)); + serializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9010_DeserializerResetDoneGet(adi_fpga9010_Device_t *device, uint8_t *rxResetDone) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t resetDoneReadBack = 0; + char serializerErrStr[][64] = {"Error reading channel 0 rx reset done"}; + uint32_t laneNumPos = 22; + + typedef struct { + int32_t(*RxResetDoneBfGet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t *); + } fpgaRxResetDoneBfGet_t; + + fpgaRxResetDoneBfGet_t rxResetDoneBfGetFct[] = { + { .RxResetDoneBfGet = fpga9010_Jesd204PhyTokelauAds8Channel0RxResetDoneBfGet }, + { .RxResetDoneBfGet = fpga9010_Jesd204PhyTokelauAds8Channel1RxResetDoneBfGet }, + { .RxResetDoneBfGet = fpga9010_Jesd204PhyTokelauAds8Channel2RxResetDoneBfGet }, + { .RxResetDoneBfGet = fpga9010_Jesd204PhyTokelauAds8Channel3RxResetDoneBfGet }, + { .RxResetDoneBfGet = fpga9010_Jesd204PhyTokelauAds8Channel4RxResetDoneBfGet }, + { .RxResetDoneBfGet = fpga9010_Jesd204PhyTokelauAds8Channel5RxResetDoneBfGet }, + { .RxResetDoneBfGet = fpga9010_Jesd204PhyTokelauAds8Channel6RxResetDoneBfGet }, + { .RxResetDoneBfGet = fpga9010_Jesd204PhyTokelauAds8Channel7RxResetDoneBfGet } + }; + int32_t i = 0; + int32_t loopCnt = sizeof(rxResetDoneBfGetFct) / sizeof(fpgaRxResetDoneBfGet_t); + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + *rxResetDone = 0; + for (i = 0; i < loopCnt; i++) + { + if (rxResetDoneBfGetFct[i].RxResetDoneBfGet != NULL) + { + recoveryAction = rxResetDoneBfGetFct[i].RxResetDoneBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &resetDoneReadBack); + serializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + *rxResetDone |= ((resetDoneReadBack & 0x01) << i); /* shift bit result to the left then save it. */ + } + + return recoveryAction; +} + +int32_t adi_fpga9010_DeframerCfgSet(adi_fpga9010_Device_t *device, uint32_t deframerSelMask, adi_fpga9010_DeframerCfg_t *deframerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, deframerCfg); + + if (device->devStateInfo.designId == ADI_FPGA9010_JESD204B_DEVICEID) + { + recoveryAction = fpga9010_Jesd204BDeframerCfgSet(device, deframerSelMask, deframerCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + + } + else if (device->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + recoveryAction = fpga9010_Jesd204CDeframerCfgSet(device, deframerSelMask, deframerCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_DeframerCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e deframerSel, adi_fpga9010_DeframerCfg_t *deframerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, deframerCfg); + + if (device->devStateInfo.designId == ADI_FPGA9010_JESD204B_DEVICEID) + { + recoveryAction = fpga9010_Jesd204BDeframerCfgGet(device, deframerSel, deframerCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + + } + else if (device->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + recoveryAction = fpga9010_Jesd204CDeframerCfgGet(device, deframerSel, deframerCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_DeframerResetGet(adi_fpga9010_Device_t *device, uint32_t deframerSelMask, uint8_t *resetBits) +{ + UNUSED_PARA(deframerSelMask); + UNUSED_PARA(resetBits); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + //uint8_t resetGet = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + return recoveryAction; +} + +int32_t adi_fpga9010_FramerCfgSet(adi_fpga9010_Device_t *device, uint8_t framerSelMask, adi_fpga9010_FramerCfg_t *framerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, framerCfg); + + if (device->devStateInfo.designId == ADI_FPGA9010_JESD204B_DEVICEID) + { + recoveryAction = fpga9010_Jesd204BFramerCfgSet(device, framerSelMask, framerCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + + } + else if (device->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + recoveryAction = fpga9010_Jesd204CFramerCfgSet(device, framerSelMask, framerCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_FramerCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e framerSel, adi_fpga9010_FramerCfg_t *framerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, framerCfg); + + if (device->devStateInfo.designId == ADI_FPGA9010_JESD204B_DEVICEID) + { + recoveryAction = fpga9010_Jesd204BFramerCfgGet(device, framerSel, framerCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + + } + else if (device->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + recoveryAction = fpga9010_Jesd204CFramerCfgGet(device, framerSel, framerCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_FramerResetGet(adi_fpga9010_Device_t *device, uint32_t framerSelMask, uint8_t *resetBits) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, resetBits); + + if (device->devStateInfo.designId == ADI_FPGA9010_JESD204B_DEVICEID) + { + recoveryAction = fpga9010_Jesd204BFramerResetGet(device, framerSelMask, resetBits); + ADI_ERROR_RETURN(device->common.error.newAction); + + } + else if (device->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + recoveryAction = fpga9010_Jesd204CFramerResetGet(device, framerSelMask, resetBits); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_TxLaneXBarCfgSet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e framerSel, uint8_t *laneXBar) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr = FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0; + char serializerErrStr[][64] = { "Error writing Lane 0 configuration" }; + uint32_t laneNumPos = 19; + + typedef struct { + int32_t(*TxXbarLaneSelectBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, uint8_t); + } fpgaTxXbarLaneSelectBfSet_t; + + fpgaTxXbarLaneSelectBfSet_t txXbarLaneSelectBfSetFct[] = { + { .TxXbarLaneSelectBfSet = fpga9010_Jesd204TxLaneXbarLane0SelectBfSet }, + { .TxXbarLaneSelectBfSet = fpga9010_Jesd204TxLaneXbarLane1SelectBfSet }, + { .TxXbarLaneSelectBfSet = fpga9010_Jesd204TxLaneXbarLane2SelectBfSet }, + { .TxXbarLaneSelectBfSet = fpga9010_Jesd204TxLaneXbarLane3SelectBfSet }, + { .TxXbarLaneSelectBfSet = fpga9010_Jesd204TxLaneXbarLane4SelectBfSet }, + { .TxXbarLaneSelectBfSet = fpga9010_Jesd204TxLaneXbarLane5SelectBfSet }, + { .TxXbarLaneSelectBfSet = fpga9010_Jesd204TxLaneXbarLane6SelectBfSet }, + { .TxXbarLaneSelectBfSet = fpga9010_Jesd204TxLaneXbarLane7SelectBfSet } + }; + int32_t i = 0; + int32_t loopCnt = sizeof(txXbarLaneSelectBfSetFct) / sizeof(fpgaTxXbarLaneSelectBfSet_t); + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, laneXBar); + + /* Set correct addresses for the framer selected */ + if (framerSel == ADI_FPGA9010_FRAMER_0) + { + baseAddr = FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0; + } + else if (framerSel == ADI_FPGA9010_FRAMER_1) + { + baseAddr = FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1; + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, framerSel, "Invalid framer selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + for (i = 0; i < loopCnt; i++) + { + if (txXbarLaneSelectBfSetFct[i].TxXbarLaneSelectBfSet != NULL) + { + recoveryAction = txXbarLaneSelectBfSetFct[i].TxXbarLaneSelectBfSet(device, baseAddr, laneXBar[i]); + serializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9010_RxLaneXBarCfgSet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e deframerSel, uint8_t *laneXBar) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr = FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0; + char serializerErrStr[][64] = { "Error writing Lane 0 configuration" }; + uint32_t laneNumPos = 19; + + typedef struct { + int32_t(*RxXbarLaneSelectBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, uint8_t); + } fpgaRxXbarLaneSelectBfSet_t; + + fpgaRxXbarLaneSelectBfSet_t rxXbarLaneSelectBfSetFct[] = { + { .RxXbarLaneSelectBfSet = fpga9010_Jesd204RxLaneXbarLane0SelectBfSet }, + { .RxXbarLaneSelectBfSet = fpga9010_Jesd204RxLaneXbarLane1SelectBfSet }, + { .RxXbarLaneSelectBfSet = fpga9010_Jesd204RxLaneXbarLane2SelectBfSet }, + { .RxXbarLaneSelectBfSet = fpga9010_Jesd204RxLaneXbarLane3SelectBfSet }, + { .RxXbarLaneSelectBfSet = fpga9010_Jesd204RxLaneXbarLane4SelectBfSet }, + { .RxXbarLaneSelectBfSet = fpga9010_Jesd204RxLaneXbarLane5SelectBfSet }, + { .RxXbarLaneSelectBfSet = fpga9010_Jesd204RxLaneXbarLane6SelectBfSet }, + { .RxXbarLaneSelectBfSet = fpga9010_Jesd204RxLaneXbarLane7SelectBfSet } + }; + int32_t i = 0; + int32_t loopCnt = sizeof(rxXbarLaneSelectBfSetFct) / sizeof(fpgaRxXbarLaneSelectBfSet_t); + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, laneXBar); + + /* Set correct addresses for the deframer selected */ + if (deframerSel == ADI_FPGA9010_DEFRAMER_0) + { + baseAddr = FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0; + } + else if (deframerSel == ADI_FPGA9010_DEFRAMER_1) + { + baseAddr = FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1; + } + else if (deframerSel == ADI_FPGA9010_DEFRAMER_2) + { + baseAddr = FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2; + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, deframerSel, "Invalid deframer selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + for (i = 0; i < loopCnt; i++) + { + if (rxXbarLaneSelectBfSetFct[i].RxXbarLaneSelectBfSet != NULL) + { + recoveryAction = rxXbarLaneSelectBfSetFct[i].RxXbarLaneSelectBfSet(device, baseAddr, laneXBar[i]); + serializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9010_TxLaneXBarCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e framerSel, uint8_t *laneXBar) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr = FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0; + char serializerErrStr[][64] = { "Error reading Lane 0 configuration" }; + uint32_t laneNumPos = 19; + + typedef struct { + int32_t(*TxXbarLaneSelectBfGet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204TxLaneXbarChanAddr_e baseAddr, uint8_t *); + } fpgaTxXbarLaneSelectBfGet_t; + + fpgaTxXbarLaneSelectBfGet_t txXbarLaneSelectBfGetFct[] = { + { .TxXbarLaneSelectBfGet = fpga9010_Jesd204TxLaneXbarLane0SelectBfGet }, + { .TxXbarLaneSelectBfGet = fpga9010_Jesd204TxLaneXbarLane1SelectBfGet }, + { .TxXbarLaneSelectBfGet = fpga9010_Jesd204TxLaneXbarLane2SelectBfGet }, + { .TxXbarLaneSelectBfGet = fpga9010_Jesd204TxLaneXbarLane3SelectBfGet }, + { .TxXbarLaneSelectBfGet = fpga9010_Jesd204TxLaneXbarLane4SelectBfGet }, + { .TxXbarLaneSelectBfGet = fpga9010_Jesd204TxLaneXbarLane5SelectBfGet }, + { .TxXbarLaneSelectBfGet = fpga9010_Jesd204TxLaneXbarLane6SelectBfGet }, + { .TxXbarLaneSelectBfGet = fpga9010_Jesd204TxLaneXbarLane7SelectBfGet } + }; + int32_t i = 0; + int32_t loopCnt = sizeof(txXbarLaneSelectBfGetFct) / sizeof(fpgaTxXbarLaneSelectBfGet_t); + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, laneXBar); + + /* Set correct addresses for the framer selected */ + if (framerSel == ADI_FPGA9010_FRAMER_0) + { + baseAddr = FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_0; + } + else if (framerSel == ADI_FPGA9010_FRAMER_1) + { + baseAddr = FPGA9010_BF_JESD204_TX_LANE_XBAR_LINK_1; + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, framerSel, "Invalid framer selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < loopCnt; i++) + { + if (txXbarLaneSelectBfGetFct[i].TxXbarLaneSelectBfGet != NULL) + { + recoveryAction = txXbarLaneSelectBfGetFct[i].TxXbarLaneSelectBfGet(device, baseAddr, &laneXBar[i]); + serializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9010_RxLaneXBarCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e deframerSel, uint8_t *laneXBar) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr = FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0; + char serializerErrStr[][64] = { "Error reading Lane 0 configuration" }; + uint32_t laneNumPos = 19; + + typedef struct { + int32_t(*RxXbarLaneSelectBfGet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204RxLaneXbarChanAddr_e baseAddr, uint8_t *); + } fpgaRxXbarLaneSelectBfGet_t; + + fpgaRxXbarLaneSelectBfGet_t rxXbarLaneSelectBfGetFct[] = { + { .RxXbarLaneSelectBfGet = fpga9010_Jesd204RxLaneXbarLane0SelectBfGet }, + { .RxXbarLaneSelectBfGet = fpga9010_Jesd204RxLaneXbarLane1SelectBfGet }, + { .RxXbarLaneSelectBfGet = fpga9010_Jesd204RxLaneXbarLane2SelectBfGet }, + { .RxXbarLaneSelectBfGet = fpga9010_Jesd204RxLaneXbarLane3SelectBfGet }, + { .RxXbarLaneSelectBfGet = fpga9010_Jesd204RxLaneXbarLane4SelectBfGet }, + { .RxXbarLaneSelectBfGet = fpga9010_Jesd204RxLaneXbarLane5SelectBfGet }, + { .RxXbarLaneSelectBfGet = fpga9010_Jesd204RxLaneXbarLane6SelectBfGet }, + { .RxXbarLaneSelectBfGet = fpga9010_Jesd204RxLaneXbarLane7SelectBfGet } + }; + int32_t i = 0; + int32_t loopCnt = sizeof(rxXbarLaneSelectBfGetFct) / sizeof(fpgaRxXbarLaneSelectBfGet_t); + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, laneXBar); + + /* Set correct addresses for the deframer selected */ + if (deframerSel == ADI_FPGA9010_DEFRAMER_0) + { + baseAddr = FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_0; + } + else if (deframerSel == ADI_FPGA9010_DEFRAMER_1) + { + baseAddr = FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_1; + } + else if (deframerSel == ADI_FPGA9010_DEFRAMER_2) + { + baseAddr = FPGA9010_BF_JESD204_RX_LANE_XBAR_LINK_2; + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, deframerSel, "Invalid deframer selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + for (i = 0; i < loopCnt; i++) + { + if (rxXbarLaneSelectBfGetFct[i].RxXbarLaneSelectBfGet != NULL) + { + recoveryAction = rxXbarLaneSelectBfGetFct[i].RxXbarLaneSelectBfGet(device, baseAddr, &laneXBar[i]); + serializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9010_FramerReset(adi_fpga9010_Device_t *device, uint8_t framerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (device->devStateInfo.designId == ADI_FPGA9010_JESD204B_DEVICEID) + { + recoveryAction = fpga9010_Jesd204BFramerReset(device, framerSelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + } + else if (device->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + recoveryAction = fpga9010_Jesd204CFramerReset(device, framerSelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_FramerDisable(adi_fpga9010_Device_t *device, uint8_t framerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (device->devStateInfo.designId == ADI_FPGA9010_JESD204B_DEVICEID) + { + recoveryAction = fpga9010_Jesd204BFramerDisable(device, framerSelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + } + else if (device->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + recoveryAction = fpga9010_Jesd204CFramerDisable(device, framerSelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_DeframerReset(adi_fpga9010_Device_t *device, uint8_t deframerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (device->devStateInfo.designId == ADI_FPGA9010_JESD204B_DEVICEID) + { + recoveryAction = fpga9010_Jesd204BDeframerReset(device, deframerSelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + } + else if (device->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + recoveryAction = fpga9010_Jesd204CDeframerReset(device, deframerSelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_DeframerDisable(adi_fpga9010_Device_t *device, uint8_t deframerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (device->devStateInfo.designId == ADI_FPGA9010_JESD204B_DEVICEID) + { + recoveryAction = fpga9010_Jesd204BDeframerDisable(device, deframerSelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + + } + else if (device->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + recoveryAction = fpga9010_Jesd204CDeframerDisable(device, deframerSelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_DeframerStatusGet(adi_fpga9010_Device_t *device, uint8_t deframerSelMask, uint8_t *status) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (device->devStateInfo.designId == ADI_FPGA9010_JESD204B_DEVICEID) + { + recoveryAction = fpga9010_Jesd204BDeframerStatusGet(device, deframerSelMask, status); + ADI_ERROR_RETURN(device->common.error.newAction); + + } + else if (device->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + recoveryAction = fpga9010_Jesd204CDeframerStatusGet(device, deframerSelMask, status); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_ChannelLoopbackEnable(adi_fpga9010_Device_t *device, uint8_t laneSelMask, uint8_t loopbackValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + char serializerErrStr[][64] = { + "Error setting loopback for channel 0 " + }; + uint32_t laneNumPos = 35; + + typedef struct { + int32_t(*LoopbackBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + } fpgaLoopbackBfSet_t; + + fpgaLoopbackBfSet_t loopbackBfSetFct[] = { + { .LoopbackBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0LoopbackBfSet }, + { .LoopbackBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1LoopbackBfSet }, + { .LoopbackBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2LoopbackBfSet }, + { .LoopbackBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3LoopbackBfSet }, + { .LoopbackBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4LoopbackBfSet }, + { .LoopbackBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5LoopbackBfSet }, + { .LoopbackBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6LoopbackBfSet }, + { .LoopbackBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7LoopbackBfSet } + }; + int32_t i = 0; + int32_t selectBit = 0; + int32_t loopCnt = sizeof(loopbackBfSetFct) / sizeof(fpgaLoopbackBfSet_t); + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + for (i = 0; i < loopCnt; i++) + { + if (laneSelMask == 0) + { + break; /* Already processed all mask bits. */ + } + + selectBit = 1 << i; /* process each bit from right most to left most. */ + + if ((laneSelMask & selectBit) == 0) + { + continue; /* If current bit mask is not set then go to next bit mask */ + } + + laneSelMask &= ~selectBit; /* mark off the select bit that is currently processing. */ + + if (loopbackBfSetFct[i].LoopbackBfSet != NULL) + { + recoveryAction = loopbackBfSetFct[i].LoopbackBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (loopbackValue & 0x07)); + serializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9010_ChannelDfeLpmOverrideSet(adi_fpga9010_Device_t *device, uint8_t laneSelMask, uint8_t value) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + char serializerErrStr[][64] = { + "Error setting RxDfeLpmOverride for channel 0 " + }; + uint32_t laneNumPos = 43; + + typedef struct { + int32_t(*RxDfeLpmOverrideBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204PhyTokelauAds8ChanAddr_e baseAddr, uint8_t); + } fpgaRxDfeLpmOverrideBfSet_t; + + fpgaRxDfeLpmOverrideBfSet_t rxDfeLpmOverrideBfSetFct[] = { + { .RxDfeLpmOverrideBfSet = fpga9010_Jesd204PhyTokelauAds8Channel0RxDfeLpmOverrideBfSet }, + { .RxDfeLpmOverrideBfSet = fpga9010_Jesd204PhyTokelauAds8Channel1RxDfeLpmOverrideBfSet }, + { .RxDfeLpmOverrideBfSet = fpga9010_Jesd204PhyTokelauAds8Channel2RxDfeLpmOverrideBfSet }, + { .RxDfeLpmOverrideBfSet = fpga9010_Jesd204PhyTokelauAds8Channel3RxDfeLpmOverrideBfSet }, + { .RxDfeLpmOverrideBfSet = fpga9010_Jesd204PhyTokelauAds8Channel4RxDfeLpmOverrideBfSet }, + { .RxDfeLpmOverrideBfSet = fpga9010_Jesd204PhyTokelauAds8Channel5RxDfeLpmOverrideBfSet }, + { .RxDfeLpmOverrideBfSet = fpga9010_Jesd204PhyTokelauAds8Channel6RxDfeLpmOverrideBfSet }, + { .RxDfeLpmOverrideBfSet = fpga9010_Jesd204PhyTokelauAds8Channel7RxDfeLpmOverrideBfSet } + }; + int32_t i = 0; + int32_t selectBit = 0; + int32_t loopCnt = sizeof(rxDfeLpmOverrideBfSetFct) / sizeof(fpgaRxDfeLpmOverrideBfSet_t); + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + for (i = 0; i < loopCnt; i++) + { + if (laneSelMask == 0) + { + break; /* Already processed all mask bits. */ + } + + selectBit = 1 << i; /* process each bit from right most to left most. */ + + if ((laneSelMask & selectBit) == 0) + { + continue; /* If current bit mask is not set then go to next bit mask */ + } + + laneSelMask &= ~selectBit; /* mark off the select bit that is currently processing. */ + + if (rxDfeLpmOverrideBfSetFct[i].RxDfeLpmOverrideBfSet != NULL) + { + recoveryAction = rxDfeLpmOverrideBfSetFct[i].RxDfeLpmOverrideBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, value); + serializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9010_SyncXBarCfgSet(adi_fpga9010_Device_t *device, uint8_t polarity, uint8_t *inputSyncSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t maxIndex = ADI_FPGA9010_NUM_OF_DEFRAMERS + ADI_FPGA9010_NUM_OF_FRAMERS; + char serializerErrStr[][64] = { "Error setting output sync 0 configuration" }; + uint32_t laneNumPos = 26; + + typedef struct { + int32_t(*SyncXbarSyncOutSelectBfSet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, uint8_t); + } fpgaSyncXbarSyncOutSelectBfSet_t; + + fpgaSyncXbarSyncOutSelectBfSet_t syncXbarSyncOutSelectBfSetFct[] = { + { .SyncXbarSyncOutSelectBfSet = fpga9010_Jesd204bSyncXbarSyncOut0SelectBfSet }, + { .SyncXbarSyncOutSelectBfSet = fpga9010_Jesd204bSyncXbarSyncOut1SelectBfSet }, + { .SyncXbarSyncOutSelectBfSet = fpga9010_Jesd204bSyncXbarSyncOut2SelectBfSet }, + { .SyncXbarSyncOutSelectBfSet = fpga9010_Jesd204bSyncXbarSyncOut3SelectBfSet }, + { .SyncXbarSyncOutSelectBfSet = fpga9010_Jesd204bSyncXbarSyncOut4SelectBfSet }, + { .SyncXbarSyncOutSelectBfSet = fpga9010_Jesd204bSyncXbarSyncOut5SelectBfSet }, + { .SyncXbarSyncOutSelectBfSet = fpga9010_Jesd204bSyncXbarSyncOut6SelectBfSet }, + { .SyncXbarSyncOutSelectBfSet = fpga9010_Jesd204bSyncXbarSyncOut7SelectBfSet } + }; + int32_t i = 0; + int32_t loopCnt = sizeof(syncXbarSyncOutSelectBfSetFct) / sizeof(fpgaSyncXbarSyncOutSelectBfSet_t); + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, inputSyncSel); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + for (i = 0; i < loopCnt; i++) + { + if (syncXbarSyncOutSelectBfSetFct[i].SyncXbarSyncOutSelectBfSet != NULL) + { + if (maxIndex > 0) + { + recoveryAction = syncXbarSyncOutSelectBfSetFct[i].SyncXbarSyncOutSelectBfSet(device, FPGA9010_BF_JESD204B_SYNC_XBAR, inputSyncSel[i]); + serializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + maxIndex--; + } + else { + break; + } + } + } + + recoveryAction = fpga9010_Jesd204bSyncXbarSyncInPolarityBfSet(device, FPGA9010_BF_JESD204B_SYNC_XBAR, polarity); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting sync xbar polarity"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_SyncXBarCfgGet(adi_fpga9010_Device_t *device, uint8_t *polarity, uint8_t *inputSyncSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t maxIndex = ADI_FPGA9010_NUM_OF_DEFRAMERS + ADI_FPGA9010_NUM_OF_FRAMERS; + char serializerErrStr[][64] = { "Error reading output sync 0 configuration" }; + uint32_t laneNumPos = 26; + + typedef struct { + int32_t(*SyncXbarSyncOutSelectBfGet) (adi_fpga9010_Device_t *device, fpga9010_BfJesd204bSyncXbarChanAddr_e baseAddr, uint8_t *); + } fpgaSyncXbarSyncOutSelectBfGet_t; + + fpgaSyncXbarSyncOutSelectBfGet_t syncXbarSyncOutSelectBfGetFct[] = { + { .SyncXbarSyncOutSelectBfGet = fpga9010_Jesd204bSyncXbarSyncOut0SelectBfGet }, + { .SyncXbarSyncOutSelectBfGet = fpga9010_Jesd204bSyncXbarSyncOut1SelectBfGet }, + { .SyncXbarSyncOutSelectBfGet = fpga9010_Jesd204bSyncXbarSyncOut2SelectBfGet }, + { .SyncXbarSyncOutSelectBfGet = fpga9010_Jesd204bSyncXbarSyncOut3SelectBfGet }, + { .SyncXbarSyncOutSelectBfGet = fpga9010_Jesd204bSyncXbarSyncOut4SelectBfGet }, + { .SyncXbarSyncOutSelectBfGet = fpga9010_Jesd204bSyncXbarSyncOut5SelectBfGet }, + { .SyncXbarSyncOutSelectBfGet = fpga9010_Jesd204bSyncXbarSyncOut6SelectBfGet }, + { .SyncXbarSyncOutSelectBfGet = fpga9010_Jesd204bSyncXbarSyncOut7SelectBfGet } + }; + int32_t i = 0; + int32_t loopCnt = sizeof(syncXbarSyncOutSelectBfGetFct) / sizeof(fpgaSyncXbarSyncOutSelectBfGet_t); + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, inputSyncSel); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + for (i = 0; i < loopCnt; i++) + { + if (syncXbarSyncOutSelectBfGetFct[i].SyncXbarSyncOutSelectBfGet != NULL) + { + if (maxIndex > 0) + { + recoveryAction = syncXbarSyncOutSelectBfGetFct[i].SyncXbarSyncOutSelectBfGet(device, FPGA9010_BF_JESD204B_SYNC_XBAR, &inputSyncSel[i]); + serializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + maxIndex--; + } + else { + break; + } + } + } + + recoveryAction = fpga9010_Jesd204bSyncXbarSyncInPolarityBfGet(device, FPGA9010_BF_JESD204B_SYNC_XBAR, polarity); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading sync xbar polarity"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_SysRefEnableSet(adi_fpga9010_Device_t *device, uint8_t framerSelMask, uint8_t deframerSelMask, uint8_t enable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t outputEnableRegisterVal = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + recoveryAction = fpga9010_Jesd204SysrefControlOutputEnableBfGet(device, FPGA9010_BF_JESD204_SYSREF_CONTROL, &outputEnableRegisterVal); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting output enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Force only the bits we care about */ + framerSelMask = (ADI_FPGA9010_FRAMER_ALL & framerSelMask); + deframerSelMask = (ADI_FPGA9010_DEFRAMER_ALL & deframerSelMask); + + if (enable == ADI_ENABLE) + { + outputEnableRegisterVal |= (uint32_t)deframerSelMask; + outputEnableRegisterVal |= (uint32_t)framerSelMask << ADI_FPGA9010_NUM_OF_DEFRAMERS; + } + else if (enable == ADI_DISABLE) + { + outputEnableRegisterVal &= ~((uint32_t)deframerSelMask); + outputEnableRegisterVal &= ~((uint32_t)framerSelMask << ADI_FPGA9010_NUM_OF_DEFRAMERS); + } + + recoveryAction = fpga9010_Jesd204SysrefControlOutputEnableBfSet(device, FPGA9010_BF_JESD204_SYSREF_CONTROL, outputEnableRegisterVal); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting output enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_SysRefControlSet(adi_fpga9010_Device_t *device, adi_fpga9010_SysRefClkCfg_t *sysRefCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, sysRefCfg); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + recoveryAction = fpga9010_Jesd204SysrefControlExtSysrefPolarityBfSet(device, FPGA9010_BF_JESD204_SYSREF_CONTROL, sysRefCfg->externalSysrefPolarity); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting external sysref polarity"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204SysrefControlExtSysrefSampleEdgeBfSet(device, FPGA9010_BF_JESD204_SYSREF_CONTROL, sysRefCfg->externalSysrefSampleEdge); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting external sysref sample edge"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204SysrefControlIntSysrefEnableBfSet(device, FPGA9010_BF_JESD204_SYSREF_CONTROL, sysRefCfg->internalSysrefEnable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting internal sysref enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write (actual value) - 1 to register */ + recoveryAction = fpga9010_Jesd204SysrefControlIntSysrefGenPeriodBfSet(device, FPGA9010_BF_JESD204_SYSREF_CONTROL, sysRefCfg->internalSysRefGeneratorFrequency - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting internal sysref generator"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_SysRefControlGet(adi_fpga9010_Device_t *device, adi_fpga9010_SysRefClkCfg_t *sysRefCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, sysRefCfg); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + recoveryAction = fpga9010_Jesd204SysrefControlExtSysrefPolarityBfGet(device, FPGA9010_BF_JESD204_SYSREF_CONTROL, &sysRefCfg->externalSysrefPolarity); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting external sysref polarity"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204SysrefControlExtSysrefSampleEdgeBfGet(device, FPGA9010_BF_JESD204_SYSREF_CONTROL, &sysRefCfg->externalSysrefSampleEdge); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting external sysref sample edge"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204SysrefControlIntSysrefEnableBfGet(device, FPGA9010_BF_JESD204_SYSREF_CONTROL, &sysRefCfg->internalSysrefEnable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting internal sysref enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write (actual value) - 1 to register */ + recoveryAction = fpga9010_Jesd204SysrefControlIntSysrefGenPeriodBfGet(device, FPGA9010_BF_JESD204_SYSREF_CONTROL, &sysRefCfg->internalSysRefGeneratorFrequency); + sysRefCfg->internalSysRefGeneratorFrequency++; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting internal sysref generator"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_SysRefRequest(adi_fpga9010_Device_t *device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t internalSysrefEnable = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + recoveryAction = fpga9010_Jesd204SysrefControlIntSysrefEnableBfGet(device, FPGA9010_BF_JESD204_SYSREF_CONTROL, &internalSysrefEnable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading sync xbar polarity"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (internalSysrefEnable == 1) + { + recoveryAction = fpga9010_Jesd204SysrefControlIntSysrefRequestBfSet(device, FPGA9010_BF_JESD204_SYSREF_CONTROL, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting internal sysref request"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = fpga9010_Jesd204SysrefControlExtSysrefRequestBfSet(device, FPGA9010_BF_JESD204_SYSREF_CONTROL, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting external sysref request"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_Jesd204cLinkLayerIrqEnSet(adi_fpga9010_Device_t *device, uint8_t linkSelMask, uint16_t interruptBitMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_0; + int32_t i = 0; + uint8_t linkSelect = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + for (i = 0; i < (ADI_FPGA9010_NUM_OF_DEFRAMERS + ADI_FPGA9010_NUM_OF_FRAMERS); i++) + { + linkSelect = (1 << i); + + switch (linkSelect) + { + case 0x1: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_0; + break; + case 0x2: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_1; + break; + case 0x4: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_2; + break; + case 0x8: + instanceAddress = FPGA9010_BF_JESD204C_FRAMER_0; + break; + case 0x10: + instanceAddress = FPGA9010_BF_JESD204C_FRAMER_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Unsupported link selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((linkSelect & linkSelMask) > 0) + { + if ((interruptBitMask & ADI_FPGA9010_GLOBAL) > 0) + { + recoveryAction = fpga9010_XilinxJesd204cIrqEnGlobalBfSet(device, instanceAddress, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting global irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((interruptBitMask & ADI_FPGA9010_SYSREF_RECEIVED) > 0) + { + recoveryAction = fpga9010_XilinxJesd204cIrqEnSysrefReceivedBfSet(device, instanceAddress, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting sysref received irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((interruptBitMask & ADI_FPGA9010_SYSREF_ERROR) > 0) + { + recoveryAction = fpga9010_XilinxJesd204cIrqEnSysrefErrorBfSet(device, instanceAddress, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting sysref error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((interruptBitMask & ADI_FPGA9010_LOSS_SYNC_HEADER_LOCK) > 0) + { + recoveryAction = fpga9010_XilinxJesd204cIrqEnLossSyncHeaderLockBfSet(device, instanceAddress, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting loss sync header irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((interruptBitMask & ADI_FPGA9010_LOSS_MB_LOCK) > 0) + { + recoveryAction = fpga9010_XilinxJesd204cIrqEnLossMbLockBfSet(device, instanceAddress, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting loss mb lock irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((interruptBitMask & ADI_FPGA9010_BLOCK_SYNC_ERROR) > 0) + { + recoveryAction = fpga9010_XilinxJesd204cIrqEnBlockSyncErrorBfSet(device, instanceAddress, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting block sync error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((interruptBitMask & ADI_FPGA9010_MB_ERROR) > 0) + { + recoveryAction = fpga9010_XilinxJesd204cIrqEnMbErrorBfSet(device, instanceAddress, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting mb error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((interruptBitMask & ADI_FPGA9010_CRC_ERROR) > 0) + { + recoveryAction = fpga9010_XilinxJesd204cIrqEnCrcErrorBfSet(device, instanceAddress, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting crc error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((interruptBitMask & ADI_FPGA9010_FEC_ERROR) > 0) + { + recoveryAction = fpga9010_XilinxJesd204cIrqEnFecErrorBfSet(device, instanceAddress, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting fec error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((interruptBitMask & ADI_FPGA9010_OVERFLOW_ERROR) > 0) + { + recoveryAction = fpga9010_XilinxJesd204cIrqEnOverflowErrorBfSet(device, instanceAddress, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting overflow error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return recoveryAction; +} + +int32_t adi_fpga9010_Jesd204cLinkLayerIrqEnGet(adi_fpga9010_Device_t *device, uint8_t linkSel, uint16_t *interruptBitMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_0; + uint8_t interruptEnReadback = 0; + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, interruptBitMask); + + *interruptBitMask = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Logic to ensure only one bit is set in byte. */ + if ((linkSel & (linkSel - 1)) > 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Only one link is allowed to be selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + switch (linkSel) + { + case 0x1: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_0; + break; + case 0x2: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_1; + break; + case 0x4: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_2; + break; + case 0x8: + instanceAddress = FPGA9010_BF_JESD204C_FRAMER_0; + break; + case 0x10: + instanceAddress = FPGA9010_BF_JESD204C_FRAMER_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Unsupported link selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = fpga9010_XilinxJesd204cIrqEnGlobalBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting global irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= ((uint16_t)interruptEnReadback << 1); + + recoveryAction = fpga9010_XilinxJesd204cIrqEnSysrefReceivedBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting sysref received irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= ((uint16_t)interruptEnReadback << 2); + + recoveryAction = fpga9010_XilinxJesd204cIrqEnSysrefErrorBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting sysref error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= ((uint16_t)interruptEnReadback << 3); + + recoveryAction = fpga9010_XilinxJesd204cIrqEnLossSyncHeaderLockBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting loss sync header irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= ((uint16_t)interruptEnReadback << 5); + + recoveryAction = fpga9010_XilinxJesd204cIrqEnLossMbLockBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting loss mb lock irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= ((uint16_t)interruptEnReadback << 6); + + recoveryAction = fpga9010_XilinxJesd204cIrqEnBlockSyncErrorBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting block sync error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= ((uint16_t)interruptEnReadback << 7); + + recoveryAction = fpga9010_XilinxJesd204cIrqEnMbErrorBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting mb error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= ((uint16_t)interruptEnReadback << 8); + + recoveryAction = fpga9010_XilinxJesd204cIrqEnCrcErrorBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting crc error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= ((uint16_t)interruptEnReadback << 9); + + recoveryAction = fpga9010_XilinxJesd204cIrqEnFecErrorBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting fec error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= ((uint16_t)interruptEnReadback << 10); + + recoveryAction = fpga9010_XilinxJesd204cIrqEnOverflowErrorBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting overflow error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= ((uint16_t)interruptEnReadback << 11); + + return recoveryAction; +} + +int32_t adi_fpga9010_Jesd204cLinkLayerIrqStatusGet(adi_fpga9010_Device_t *device, uint8_t linkSel, uint16_t *interruptBitMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_0; + uint8_t interruptEnReadback = 0; + + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, interruptBitMask); + + *interruptBitMask = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Logic to ensure only one bit is set in byte. */ + if ((linkSel & (linkSel - 1)) > 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Only one link is allowed to be selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + switch (linkSel) + { + case 0x1: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_0; + break; + case 0x2: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_1; + break; + case 0x4: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_2; + break; + case 0x8: + instanceAddress = FPGA9010_BF_JESD204C_FRAMER_0; + break; + case 0x10: + instanceAddress = FPGA9010_BF_JESD204C_FRAMER_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Unsupported link selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = fpga9010_XilinxJesd204cIrqSysrefReceivedBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting sysref received irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= (interruptEnReadback << 2); + + recoveryAction = fpga9010_XilinxJesd204cIrqSysrefErrorBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting sysref error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= (interruptEnReadback << 3); + + recoveryAction = fpga9010_XilinxJesd204cIrqLossSyncHeaderLockBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting loss sync header irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= (interruptEnReadback << 5); + + recoveryAction = fpga9010_XilinxJesd204cIrqLossMbLockBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting loss mb lock irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= (interruptEnReadback << 6); + + recoveryAction = fpga9010_XilinxJesd204cIrqBlockSyncErrorBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting block sync error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= (interruptEnReadback << 7); + + recoveryAction = fpga9010_XilinxJesd204cIrqMbErrorBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting mb error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= (interruptEnReadback << 8); + + recoveryAction = fpga9010_XilinxJesd204cIrqCrcErrorBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting crc error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= (interruptEnReadback << 9); + + recoveryAction = fpga9010_XilinxJesd204cIrqFecErrorBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting fec error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= (interruptEnReadback << 10); + + recoveryAction = fpga9010_XilinxJesd204cIrqOverflowErrorBfGet(device, instanceAddress, &interruptEnReadback); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting overflow error irq enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + *interruptBitMask |= (interruptEnReadback << 11); + + return recoveryAction; +} + +int32_t adi_fpga9010_Jesd204CDeframerCmdDataSet(adi_fpga9010_Device_t *device, uint32_t deframerSelMask, uint8_t cmdEnable, uint8_t dataEnable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_0; + uint32_t i = 0; + adi_fpga9010_DeframerSel_e deframerSel = ADI_FPGA9010_DEFRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (deframerSelMask < 1 || deframerSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_DEFRAMERS; i++) + { + deframerSel = (adi_fpga9010_DeframerSel_e)((uint8_t)(1 << i)); + + switch (deframerSel) + { + case ADI_FPGA9010_DEFRAMER_0: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_0; + break; + case ADI_FPGA9010_DEFRAMER_1: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_1; + break; + case ADI_FPGA9010_DEFRAMER_2: + instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_2; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)deframerSel & deframerSelMask) > 0) + { + recoveryAction = fpga9010_XilinxJesd204cEnableCmdInterfaceBfSet(device, instanceAddress, cmdEnable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set cmd interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cEnableDataInterfaceBfSet(device, instanceAddress, dataEnable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set data interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9010_Jesd204CFramerCmdDataSet(adi_fpga9010_Device_t *device, uint32_t framerSelMask, uint8_t cmdEnable, uint8_t dataEnable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9010_BF_JESD204C_DEFRAMER_0; + uint32_t i = 0; + adi_fpga9010_FramerSel_e framerSel = ADI_FPGA9010_FRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (framerSelMask < 1 || framerSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_FRAMERS; i++) + { + framerSel = (adi_fpga9010_FramerSel_e)((uint8_t)(1 << i)); + + switch (framerSel) + { + case ADI_FPGA9010_FRAMER_0: + instanceAddress = FPGA9010_BF_JESD204C_FRAMER_0; + break; + case ADI_FPGA9010_FRAMER_1: + instanceAddress = FPGA9010_BF_JESD204C_FRAMER_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)framerSel & framerSelMask) > 0) + { + recoveryAction = fpga9010_XilinxJesd204cEnableCmdInterfaceBfSet(device, instanceAddress, cmdEnable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set cmd interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_XilinxJesd204cEnableDataInterfaceBfSet(device, instanceAddress, dataEnable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Unable to set data interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_prbs.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_prbs.c new file mode 100644 index 0000000..6239d82 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_prbs.c @@ -0,0 +1,311 @@ +/** + * \file: adi_fpga9010_jesd.c + * + * \brief Contains top level tx fpga9010 related functions + * + * FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9010_user.h" +#include "adi_fpga9010_prbs.h" +#include "adi_fpga9010.h" +#include "../../private/include/fpga9010_bf_jesd204_phy_tokelau_ads8.h" + +int32_t adi_fpga9010_PrbsSerializerEnable(adi_fpga9010_Device_t *device, uint8_t laneSelMask, uint8_t prbsSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + if ((laneSelMask & 0x01) == 0x01) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel0TxPrbsSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (prbsSel & 0x0F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting PRBS mode for channel 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x02) == 0x02) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel1TxPrbsSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (prbsSel & 0x0F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting PRBS mode for channel 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x04) == 0x04) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel2TxPrbsSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (prbsSel & 0x0F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting PRBS mode for channel 2"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x08) == 0x08) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel3TxPrbsSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (prbsSel & 0x0F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting PRBS mode for channel 3"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x10) == 0x10) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel4TxPrbsSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (prbsSel & 0x0F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting PRBS mode for channel 4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x20) == 0x20) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel5TxPrbsSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (prbsSel & 0x0F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting PRBS mode for channel 5"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x40) == 0x40) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel6TxPrbsSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (prbsSel & 0x0F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting PRBS mode for channel 6"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x80) == 0x80) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel7TxPrbsSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (prbsSel & 0x0F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting PRBS mode for channel 7"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_PrbsDeserializerEnable(adi_fpga9010_Device_t *device, uint8_t laneSelMask, uint8_t prbsSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + if ((laneSelMask & 0x01) == 0x01) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (prbsSel & 0x0F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting PRBS mode for channel 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x02) == 0x02) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (prbsSel & 0x0F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting PRBS mode for channel 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x04) == 0x04) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (prbsSel & 0x0F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting PRBS mode for channel 2"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x08) == 0x08) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (prbsSel & 0x0F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting PRBS mode for channel 3"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x10) == 0x10) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (prbsSel & 0x0F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting PRBS mode for channel 4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x20) == 0x20) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (prbsSel & 0x0F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting PRBS mode for channel 5"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x40) == 0x40) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (prbsSel & 0x0F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting PRBS mode for channel 6"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x80) == 0x80) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsSelBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, (prbsSel & 0x0F)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting PRBS mode for channel 7"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_PrbsSerializerErrorInject(adi_fpga9010_Device_t *device, uint8_t laneSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + if ((laneSelMask & 0x01) == 0x01) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel0TxPrbsInjErrBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error injecting an error for channel 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x02) == 0x02) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel1TxPrbsInjErrBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error injecting an error for channel 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x04) == 0x04) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel2TxPrbsInjErrBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error injecting an error for channel 2"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x08) == 0x08) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel3TxPrbsInjErrBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error injecting an error for channel 3"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x10) == 0x10) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel4TxPrbsInjErrBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error injecting an error for channel 4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x20) == 0x20) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel5TxPrbsInjErrBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error injecting an error for channel 5"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x40) == 0x40) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel6TxPrbsInjErrBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error injecting an error for channel 6"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x80) == 0x80) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel7TxPrbsInjErrBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error injecting an error for channel 7"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9010_PrbsErrorCountRead(adi_fpga9010_Device_t *device, uint32_t *errCounts) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsErrCntBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &errCounts[0]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading PRBS error count for channel 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsErrCntBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &errCounts[1]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading PRBS error count for channel 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsErrCntBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &errCounts[2]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading PRBS error count for channel 2"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsErrCntBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &errCounts[3]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading PRBS error count for channel 3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsErrCntBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &errCounts[4]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading PRBS error count for channel 4"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsErrCntBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &errCounts[5]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading PRBS error count for channel 5"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsErrCntBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &errCounts[6]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading PRBS error count for channel 6"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsErrCntBfGet(device, FPGA9010_BF_TOKELAU_JESD_PHY, &errCounts[7]); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading PRBS error count for channel 7"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_PrbsErrorClear(adi_fpga9010_Device_t *device, uint8_t laneSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + if ((laneSelMask & 0x01) == 0x01) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel0RxPrbsErrCntRstBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error clearing the error count for channel 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x02) == 0x02) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel1RxPrbsErrCntRstBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error clearing the error count for channel 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x04) == 0x04) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel2RxPrbsErrCntRstBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error clearing the error count for channel 2"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x08) == 0x08) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel3RxPrbsErrCntRstBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error clearing the error count for channel 3"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x10) == 0x10) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel4RxPrbsErrCntRstBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error clearing the error count for channel 4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x20) == 0x20) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel5RxPrbsErrCntRstBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error clearing the error count for channel 5"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x40) == 0x40) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel6RxPrbsErrCntRstBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error clearing the error count for channel 6"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x80) == 0x80) + { + recoveryAction = fpga9010_Jesd204PhyTokelauAds8Channel7RxPrbsErrCntRstBfSet(device, FPGA9010_BF_TOKELAU_JESD_PHY, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error clearing the error count for channel 7"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_rx.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_rx.c new file mode 100644 index 0000000..a7bfe1c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_rx.c @@ -0,0 +1,1014 @@ +/** + * \file: adi_fpga9010_rx.c + * + * \brief Contains top level rx fpga9010 related functions + * + * FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9010_user.h" +#include "adi_fpga9010_rx.h" +#include "adi_fpga9010.h" +#include "../../private/include/fpga9010_bf_dp_tollgate.h" +#include "../../private/include/fpga9010_bf_dp_rx_dma.h" +#include "../../private/include/fpga9010_bf_dp_capture_control.h" + +int32_t adi_fpga9010_RxTollgateSet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, adi_fpga9010_RxTollgateCfg_t *tollGateCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTollgateChanAddr_e instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_0; + uint32_t i = 0; + adi_fpga9010_DeframerSel_e dataMoverSel = ADI_FPGA9010_DEFRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, tollGateCfg); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_DEFRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_DeframerSel_e)((uint8_t)(1 << i)); + + switch(dataMoverSel) + { + case ADI_FPGA9010_DEFRAMER_0: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_0; + break; + case ADI_FPGA9010_DEFRAMER_1: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_1; + break; + case ADI_FPGA9010_DEFRAMER_2: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = fpga9010_DpTollgateEdgeLevelBfSet(device, instanceAddress, tollGateCfg->tollGateEdgeOrLvl); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to detection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTollgateHighRisingLowFallingBfSet(device, instanceAddress, tollGateCfg->tollGateHiRiseOrLoFall); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to polarity register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTollgateTriggerSelectBfSet(device, instanceAddress, (uint32_t)tollGateCfg->tollGateTrigSource); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to selection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RxTollgateGet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e rxDatamoverSel, adi_fpga9010_RxTollgateCfg_t *tollGateCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTollgateChanAddr_e baseAddress = FPGA9010_BF_DP_TOLLGATE_RX_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, tollGateCfg); + + switch (rxDatamoverSel) + { + case ADI_FPGA9010_DEFRAMER_0: + baseAddress = FPGA9010_BF_DP_TOLLGATE_RX_0; + break; + case ADI_FPGA9010_DEFRAMER_1: + baseAddress = FPGA9010_BF_DP_TOLLGATE_RX_1; + break; + case ADI_FPGA9010_DEFRAMER_2: + baseAddress = FPGA9010_BF_DP_TOLLGATE_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, rxDatamoverSel, "Invalid datamover selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + recoveryAction = fpga9010_DpTollgateEdgeLevelBfGet(device, baseAddress, &tollGateCfg->tollGateEdgeOrLvl); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to detection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTollgateHighRisingLowFallingBfGet(device, baseAddress, &tollGateCfg->tollGateHiRiseOrLoFall); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to polarity register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTollgateTriggerSelectBfGet(device, baseAddress, (uint32_t*)&tollGateCfg->tollGateTrigSource); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to selection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RxTollgateResetSet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, uint8_t resetVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTollgateChanAddr_e instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_0; + uint32_t i = 0; + adi_fpga9010_DeframerSel_e dataMoverSel = ADI_FPGA9010_DEFRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_DEFRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_DeframerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_DEFRAMER_0: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_0; + break; + case ADI_FPGA9010_DEFRAMER_1: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_1; + break; + case ADI_FPGA9010_DEFRAMER_2: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = fpga9010_DpTollgateResetTollgateBfSet(device, instanceAddress, resetVal); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to reset register"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RxTollgateResetGet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, uint16_t *resetVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTollgateChanAddr_e instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_0; + uint32_t i = 0; + adi_fpga9010_DeframerSel_e dataMoverSel = ADI_FPGA9010_DEFRAMER_0; + uint8_t resetBitRead = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, resetVal); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *resetVal = 0; + + for (i = 0; i < ADI_FPGA9010_NUM_OF_DEFRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_DeframerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_DEFRAMER_0: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_0; + break; + case ADI_FPGA9010_DEFRAMER_1: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_1; + break; + case ADI_FPGA9010_DEFRAMER_2: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = fpga9010_DpTollgateResetTollgateBfGet(device, instanceAddress, &resetBitRead); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read from reset register"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *resetVal |= (resetBitRead & 1) << i; + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RxTollgateTriggerSet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, adi_fpga9010_RxTollgateTrigSources_e triggerSelect) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTollgateChanAddr_e instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_0; + uint32_t i = 0; + adi_fpga9010_DeframerSel_e dataMoverSel = ADI_FPGA9010_DEFRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_DEFRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_DeframerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_DEFRAMER_0: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_0; + break; + case ADI_FPGA9010_DEFRAMER_1: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_1; + break; + case ADI_FPGA9010_DEFRAMER_2: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + adi_fpga9010_RxTollgateResetSet(device, rxDatamoverSelMask, 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTollgateTriggerSelectBfSet(device, (fpga9010_BfDpTollgateChanAddr_e)instanceAddress, (uint32_t)triggerSelect); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to triggerSelect bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_RxTollgateResetSet(device, rxDatamoverSelMask, 0); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RxTollgateTriggerGet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e rxDatamoverSel, adi_fpga9010_RxTollgateTrigSources_e *triggerSelect) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTollgateChanAddr_e baseAddress = FPGA9010_BF_DP_TOLLGATE_RX_0; + uint32_t triggerSelectGet = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, triggerSelect); + + switch (rxDatamoverSel) + { + case ADI_FPGA9010_DEFRAMER_0: + baseAddress = FPGA9010_BF_DP_TOLLGATE_RX_0; + break; + case ADI_FPGA9010_DEFRAMER_1: + baseAddress = FPGA9010_BF_DP_TOLLGATE_RX_1; + break; + case ADI_FPGA9010_DEFRAMER_2: + baseAddress = FPGA9010_BF_DP_TOLLGATE_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, rxDatamoverSel, "Invalid datamover selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + recoveryAction = fpga9010_DpTollgateTriggerSelectBfGet(device, baseAddress, &triggerSelectGet); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to selection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + *triggerSelect = (adi_fpga9010_RxTollgateTrigSources_e)triggerSelectGet; + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RxDmaSet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, adi_fpga9010_RxDmaCfg_t *rxDmaCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpRxDmaChanAddr_e instanceAddress = FPGA9010_BF_DP_DMA_RX_0; + uint32_t i = 0; + adi_fpga9010_DeframerSel_e dataMoverSel = ADI_FPGA9010_DEFRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, rxDmaCfg); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_DEFRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_DeframerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_DEFRAMER_0: + instanceAddress = FPGA9010_BF_DP_DMA_RX_0; + break; + case ADI_FPGA9010_DEFRAMER_1: + instanceAddress = FPGA9010_BF_DP_DMA_RX_1; + break; + case ADI_FPGA9010_DEFRAMER_2: + instanceAddress = FPGA9010_BF_DP_DMA_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* TODO: start address could be changed at runtime by this function, and this length check is not enough to ensure RAM buffers do not overlap */ + if (rxDmaCfg->length > RX_DMA_SIZE) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Rx DMA capture length is too large"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = fpga9010_DpRxDmaEnableEnhancedModeBfSet(device, instanceAddress, rxDmaCfg->enableEnhancedMode); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write enableEnhancedMode bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaEnableSgBfSet(device, instanceAddress, rxDmaCfg->enableSg); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write enableSg bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaLengthBfSet(device, instanceAddress, rxDmaCfg->length); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write length bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaSgFirstDescriptorBfSet(device, instanceAddress, rxDmaCfg->sgFirstDescriptor); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write sgFirstDescriptor bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* TODO: writing to this seems to be clearing the status register. debug later */ +/* recoveryAction = fpga9010_DpRxDmaSgLastDescriptorBfSet(device, instanceAddress, rxDmaCfg->sgLastDescriptor); + * ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write sgLastDescriptor bitfield"); + * ADI_ERROR_RETURN(device->common.error.newAction); +*/ + + recoveryAction = fpga9010_DpRxDmaSimpleStartAddrBfSet(device, instanceAddress, rxDmaCfg->simpleStartAddr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write simpleStartAddr bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaValidDataWidthStreamBfSet(device, instanceAddress, rxDmaCfg->validDataWidthStream); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write validDataWidthStream bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RxDmaInit(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, adi_fpga9010_RxDmaCfg_t *rxDmaCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpRxDmaChanAddr_e instanceAddress = FPGA9010_BF_DP_DMA_RX_0; + uint32_t i = 0; + adi_fpga9010_DeframerSel_e dataMoverSel = ADI_FPGA9010_DEFRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, rxDmaCfg); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_DEFRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_DeframerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_DEFRAMER_0: + instanceAddress = FPGA9010_BF_DP_DMA_RX_0; + break; + case ADI_FPGA9010_DEFRAMER_1: + instanceAddress = FPGA9010_BF_DP_DMA_RX_1; + break; + case ADI_FPGA9010_DEFRAMER_2: + instanceAddress = FPGA9010_BF_DP_DMA_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = fpga9010_DpRxDmaEnableEnhancedModeBfSet(device, instanceAddress, rxDmaCfg->enableEnhancedMode); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write enableEnhancedMode bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaEnableSgBfSet(device, instanceAddress, rxDmaCfg->enableSg); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write enableSg bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaSgFirstDescriptorBfSet(device, instanceAddress, rxDmaCfg->sgFirstDescriptor); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write sgFirstDescriptor bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* TODO: writing to this seems to be clearing the status register. debug later */ +/* recoveryAction = fpga9010_DpRxDmaSgLastDescriptorBfSet(device, instanceAddress, rxDmaCfg->sgLastDescriptor); + * ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write sgLastDescriptor bitfield"); + * ADI_ERROR_RETURN(device->common.error.newAction); +*/ + + recoveryAction = fpga9010_DpRxDmaSimpleStartAddrBfSet(device, instanceAddress, rxDmaCfg->simpleStartAddr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write simpleStartAddr bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaValidDataWidthStreamBfSet(device, instanceAddress, rxDmaCfg->validDataWidthStream); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write validDataWidthStream bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RxDmaGet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e rxDatamoverSel, adi_fpga9010_RxDmaCfg_t *rxDmaCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpRxDmaChanAddr_e baseAddress = FPGA9010_BF_DP_DMA_RX_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, rxDmaCfg); + + switch (rxDatamoverSel) + { + case ADI_FPGA9010_DEFRAMER_0: + baseAddress = FPGA9010_BF_DP_DMA_RX_0; + break; + case ADI_FPGA9010_DEFRAMER_1: + baseAddress = FPGA9010_BF_DP_DMA_RX_1; + break; + case ADI_FPGA9010_DEFRAMER_2: + baseAddress = FPGA9010_BF_DP_DMA_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, rxDatamoverSel, "Invalid datamover selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + recoveryAction = fpga9010_DpRxDmaActiveBfGet(device, baseAddress, &rxDmaCfg->active); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read active bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaCompleteBfGet(device, baseAddress, &rxDmaCfg->complete); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read complete bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaEnableEnhancedModeBfGet(device, baseAddress, &rxDmaCfg->enableEnhancedMode); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read enableEnhancedMode bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaEnableSgBfGet(device, baseAddress, &rxDmaCfg->enableSg); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read enableSg bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaHaltCompleteBfGet(device, baseAddress, &rxDmaCfg->haltComplete); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read haltComplete bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaLengthBfGet(device, baseAddress, &rxDmaCfg->length); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read length bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaOverflowBfGet(device, baseAddress, &rxDmaCfg->overflow); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read overflow bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaRunStopBfGet(device, baseAddress, &rxDmaCfg->runStop); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read runStop bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaSgFirstDescriptorBfGet(device, baseAddress, &rxDmaCfg->sgFirstDescriptor); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read sgFirstDescriptor bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaSgLastDescriptorBfGet(device, baseAddress, &rxDmaCfg->sgLastDescriptor); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read sgLastDescriptor bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaSimpleStartAddrBfGet(device, baseAddress, &rxDmaCfg->simpleStartAddr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read simpleStartAddr bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpRxDmaValidDataWidthStreamBfGet(device, baseAddress, &rxDmaCfg->validDataWidthStream); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read validDataWidthStream bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RxDmaResetSet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, uint8_t reset) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpRxDmaChanAddr_e instanceAddress = FPGA9010_BF_DP_DMA_RX_0; + uint32_t i = 0; + adi_fpga9010_DeframerSel_e dataMoverSel = ADI_FPGA9010_DEFRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_DEFRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_DeframerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_DEFRAMER_0: + instanceAddress = FPGA9010_BF_DP_DMA_RX_0; + break; + case ADI_FPGA9010_DEFRAMER_1: + instanceAddress = FPGA9010_BF_DP_DMA_RX_1; + break; + case ADI_FPGA9010_DEFRAMER_2: + instanceAddress = FPGA9010_BF_DP_DMA_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = fpga9010_DpRxDmaResetBfSet(device, instanceAddress, reset); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to reset register"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RxDmaRunStopSet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, uint8_t runStop) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpRxDmaChanAddr_e instanceAddress = FPGA9010_BF_DP_DMA_RX_0; + uint32_t i = 0; + adi_fpga9010_DeframerSel_e dataMoverSel = ADI_FPGA9010_DEFRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_DEFRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_DeframerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_DEFRAMER_0: + instanceAddress = FPGA9010_BF_DP_DMA_RX_0; + break; + case ADI_FPGA9010_DEFRAMER_1: + instanceAddress = FPGA9010_BF_DP_DMA_RX_1; + break; + case ADI_FPGA9010_DEFRAMER_2: + instanceAddress = FPGA9010_BF_DP_DMA_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = fpga9010_DpRxDmaRunStopBfSet(device, instanceAddress, runStop); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to reset register"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RxDmaLengthSet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask, uint32_t numBytes) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpRxDmaChanAddr_e instanceAddress = FPGA9010_BF_DP_DMA_RX_0; + uint32_t i = 0; + adi_fpga9010_DeframerSel_e dataMoverSel = ADI_FPGA9010_DEFRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_DEFRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_DeframerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_DEFRAMER_0: + instanceAddress = FPGA9010_BF_DP_DMA_RX_0; + break; + case ADI_FPGA9010_DEFRAMER_1: + instanceAddress = FPGA9010_BF_DP_DMA_RX_1; + break; + case ADI_FPGA9010_DEFRAMER_2: + instanceAddress = FPGA9010_BF_DP_DMA_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (numBytes > RX_DMA_SIZE) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Rx DMA capture length is too large"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = fpga9010_DpRxDmaLengthBfSet(device, instanceAddress, numBytes); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to length bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RxDatamoverEnableSet(adi_fpga9010_Device_t *device, uint32_t rxDatamoverSelMask) +{ + UNUSED_PARA(rxDatamoverSelMask); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + return recoveryAction; +} + +int32_t adi_fpga9010_RxDataChainConfigure(adi_fpga9010_Device_t *device, uint32_t rxDataMoverSelMask, adi_fpga9010_RxTollgateTrigSources_e triggerSelect, adi_fpga9010_RxDmaCfg_t *rxDmaCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* reset capture control */ + recoveryAction = fpga9010_DpCaptureControlResetBfSet(device, FPGA9010_BF_DP_CAPTURE_CONTROL_RX, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* set trigger */ + adi_fpga9010_RxTollgateTriggerSet(device, rxDataMoverSelMask, triggerSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*reset dmas */ + adi_fpga9010_RxDmaResetSet(device, rxDataMoverSelMask, 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure dmas */ + adi_fpga9010_RxDmaSet(device, rxDataMoverSelMask, rxDmaCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* set run_stop bit */ + adi_fpga9010_RxDmaRunStopSet(device, rxDataMoverSelMask, 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* pass token to start dma arbitration */ + recoveryAction = fpga9010_DpCaptureControlResetBfSet(device, FPGA9010_BF_DP_CAPTURE_CONTROL_RX, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_DpCaptureControlPassTokenBfSet(device, FPGA9010_BF_DP_CAPTURE_CONTROL_RX, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control PassToken bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RxDataChainReset(adi_fpga9010_Device_t *device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t active = 0; + uint8_t haltComplete = 0; + uint8_t i = 0; + static const uint8_t RX_DATA_CHAIN_RESET_MAX_COUNT = 5; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* reset */ + recoveryAction = fpga9010_DpCaptureControlDatapathActiveBfSet(device, FPGA9010_BF_DP_CAPTURE_CONTROL_RX, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to DatapathActive bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_DpCaptureControlResetBfSet(device, FPGA9010_BF_DP_CAPTURE_CONTROL_RX, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Clear DMA 0 */ + recoveryAction = fpga9010_DpRxDmaActiveBfGet(device, FPGA9010_BF_DP_DMA_RX_0, &active); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_RxDmaRunStopSet(device, ADI_FPGA9010_DEFRAMER_0, 0); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (active == 1) + { + haltComplete = 0; + for (i = 0; i < RX_DATA_CHAIN_RESET_MAX_COUNT; i++) + { + recoveryAction = fpga9010_DpRxDmaHaltCompleteBfGet(device, FPGA9010_BF_DP_DMA_RX_0, &haltComplete); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + if (haltComplete != 0) + { + break; + } + } + + if (i == RX_DATA_CHAIN_RESET_MAX_COUNT) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "RX0 DMA Halt failed."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + adi_fpga9010_RxDmaResetSet(device, ADI_FPGA9010_DEFRAMER_0, 1); + ADI_ERROR_RETURN(device->common.error.newAction); + /* End DMA 0*/ + + /* Clear DMA 1 */ + active = 0; + haltComplete = 0; + recoveryAction = fpga9010_DpRxDmaActiveBfGet(device, FPGA9010_BF_DP_DMA_RX_1, &active); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_RxDmaRunStopSet(device, ADI_FPGA9010_DEFRAMER_1, 0); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (active == 1) + { + + for (i = 0; i < RX_DATA_CHAIN_RESET_MAX_COUNT; i++) + { + recoveryAction = fpga9010_DpRxDmaHaltCompleteBfGet(device, FPGA9010_BF_DP_DMA_RX_1, &haltComplete); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + if (haltComplete != 0) + { + break; + } + } + + if (i == RX_DATA_CHAIN_RESET_MAX_COUNT) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "RX1 DMA Halt failed."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + adi_fpga9010_RxDmaResetSet(device, ADI_FPGA9010_DEFRAMER_1, 1); + ADI_ERROR_RETURN(device->common.error.newAction); + /* End DMA 1*/ + + /* Clear DMA 2 */ + active = 0; + haltComplete = 0; + recoveryAction = fpga9010_DpRxDmaActiveBfGet(device, FPGA9010_BF_DP_DMA_RX_2, &active); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_RxDmaRunStopSet(device, ADI_FPGA9010_DEFRAMER_2, 0); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (active == 1) + { + for (i = 0; i < RX_DATA_CHAIN_RESET_MAX_COUNT; i++) + { + recoveryAction = fpga9010_DpRxDmaHaltCompleteBfGet(device, FPGA9010_BF_DP_DMA_RX_2, &haltComplete); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (haltComplete != 0) + { + break; + } + } + + if (i == RX_DATA_CHAIN_RESET_MAX_COUNT) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "RX2 DMA Halt failed."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + adi_fpga9010_RxDmaResetSet(device, ADI_FPGA9010_DEFRAMER_2, 1); + ADI_ERROR_RETURN(device->common.error.newAction); + /* End DMA 2*/ + + adi_fpga9010_RxTollgateResetSet(device, ADI_FPGA9010_DEFRAMER_ALL, 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RxDatamoverEnableGet(adi_fpga9010_Device_t *device, uint32_t *rxDatamoverSelMask) +{ + UNUSED_PARA(rxDatamoverSelMask); + //TODO: implement this using adi_fpga_rxChannelSel_e + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} + +int32_t adi_fpga9010_RxCaptureStart(adi_fpga9010_Device_t *device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + recoveryAction = fpga9010_DpCaptureControlDatapathActiveBfSet(device, FPGA9010_BF_DP_CAPTURE_CONTROL_RX, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to DatapathActive bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RxCaptureWait(adi_fpga9010_Device_t *device, uint32_t timeMsDelay) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t datapathActive = 0; + uint32_t i; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + for (i = 0; i < timeMsDelay; i++) + { + recoveryAction = fpga9010_DpCaptureControlDatapathActiveBfGet(device, FPGA9010_BF_DP_CAPTURE_CONTROL_RX, &datapathActive); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read DatapathActive bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (datapathActive == 0) + { + return ADI_COMMON_ACT_NO_ACTION; + } + + adi_common_hal_Wait_us(&device->common, 1000); + } + + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_DATA_RX_MOVER_WAIT_TIMEOUT, ADI_COMMON_ACT_ERR_RESET_FEATURE, NULL, "RxCaptureWait timeout"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_RxDataGet(adi_fpga9010_Device_t *device, adi_fpga9010_DeframerSel_e rxDatamoverSel, int32_t data[], uint32_t *dataSize) +{ + UNUSED_PARA(rxDatamoverSel); + UNUSED_PARA(dataSize); + UNUSED_PARA(data); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} + +int32_t adi_fpga9010_RxSamplesSet(adi_fpga9010_Device_t *device, uint32_t rxDataMoverSelMask, uint32_t numSamples) +{ + UNUSED_PARA(rxDataMoverSelMask); + UNUSED_PARA(numSamples); + //TODO: implement this + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_tdd.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_tdd.c new file mode 100644 index 0000000..034870a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_tdd.c @@ -0,0 +1,569 @@ +/** + * \file: adi_fpga9010_tdd.c + * + * \brief Contains top level tdd fpga9010 related functions + * + * FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9010_user.h" +#include "adi_fpga9010_tdd.h" +#include "adi_fpga9010.h" +#include "../../private/include/fpga9010_tdd.h" +#include "../../private/include/fpga9010_bf_tdd_dp_ctrl.h" +#include "../../private/include/fpga9010_bf_tdd_enable_ctrl.h" +#include "../../private/include/fpga9010_bf_tdd_frame_cnt.h" +#include "../../private/include/fpga9010_bf_orx_pin_encode_tokelau.h" + +#define ADI_FPGA9010_TDDENABLECTRL_CNT 24 +#define ADI_FPGA9010_TDDDATAPATHCTRL_CNT 5 + +static const fpga9010_BfTddEnableCtrlChanAddr_e enableCtrlAddrArray[ADI_FPGA9010_TDDENABLECTRL_CNT] = +{ + FPGA9010_BF_TDD_ENABLE_CONTROL_RX1, + FPGA9010_BF_TDD_ENABLE_CONTROL_RX2, + FPGA9010_BF_TDD_ENABLE_CONTROL_RX3, + FPGA9010_BF_TDD_ENABLE_CONTROL_RX4, + FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1, + FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2, + FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3, + FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX1, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX2, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX3, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX4, + FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1, + FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2, + FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3, + FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4, + FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4 + }; + +static const fpga9010_BfTddDpCtrlChanAddr_e datapathctrlAddrArray[ADI_FPGA9010_TDDDATAPATHCTRL_CNT] = +{ + FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_0, + FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_1, + FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_2, + FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_0, + FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_1 +}; + +int32_t adi_fpga9010_TddInit(adi_fpga9010_Device_t *device, adi_fpga9010_TddStateMachine_t *fpgaTddStateMachine) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, fpgaTddStateMachine); + + /* Frame Counter module setup */ + if (fpgaTddStateMachine->loopCount > 0) + { + recoveryAction = fpga9010_TddFrameCntLoopCountEnBfSet(device, FPGA9010_BF_TDD_FRAME_COUNTER, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to loop_count_en bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = fpga9010_TddFrameCntLoopCountBfSet(device, FPGA9010_BF_TDD_FRAME_COUNTER, fpgaTddStateMachine->loopCount); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to loop_count_en bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddFrameCntTriggerBfSet(device, FPGA9010_BF_TDD_FRAME_COUNTER, fpgaTddStateMachine->syncExtTrig); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to loop_count bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddFrameCntEndValueBfSet(device, FPGA9010_BF_TDD_FRAME_COUNTER, fpgaTddStateMachine->frameCount); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to End_value bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Enable Control module setup */ + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->rx1EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_RX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->rx2EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_RX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->rx3EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_RX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->rx4EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_RX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->orx1EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->orx2EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->orx3EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->orx4EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->tx1EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->tx2EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->tx3EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->tx4EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->tx1ToOrx1EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->tx2ToOrx1EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->tx1ToOrx2EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->tx2ToOrx2EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->tx3ToOrx3EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->tx4ToOrx3EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->tx3ToOrx4EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->tx4ToOrx4EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->extTrig1, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->extTrig2, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->extTrig3, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleSet(device, &fpgaTddStateMachine->extTrig4, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Datapath control module setup */ + recoveryAction = fpga9010_TddDpCtrlEnableBitBfSet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_0, fpgaTddStateMachine->rxDatapath0.enable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_TddDpCtrlStartValueBfSet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_0, fpgaTddStateMachine->rxDatapath0.startValue); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddDpCtrlEnableBitBfSet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_1, fpgaTddStateMachine->rxDatapath1.enable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_TddDpCtrlStartValueBfSet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_1, fpgaTddStateMachine->rxDatapath1.startValue); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddDpCtrlEnableBitBfSet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_2, fpgaTddStateMachine->rxDatapath2.enable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_TddDpCtrlStartValueBfSet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_2, fpgaTddStateMachine->rxDatapath2.startValue); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddDpCtrlEnableBitBfSet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_0, fpgaTddStateMachine->txDatapath0.enable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_TddDpCtrlStartValueBfSet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_0, fpgaTddStateMachine->txDatapath0.startValue); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddDpCtrlEnableBitBfSet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_1, fpgaTddStateMachine->txDatapath1.enable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_TddDpCtrlStartValueBfSet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_1, fpgaTddStateMachine->txDatapath1.startValue); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TddInitGet(adi_fpga9010_Device_t *device, adi_fpga9010_TddStateMachine_t *fpgaTddStateMachine) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, fpgaTddStateMachine); + + recoveryAction = fpga9010_TddFrameCntLoopCountBfGet(device, FPGA9010_BF_TDD_FRAME_COUNTER, &fpgaTddStateMachine->loopCount); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to loop_count_en bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddFrameCntTriggerBfGet(device, FPGA9010_BF_TDD_FRAME_COUNTER, &fpgaTddStateMachine->syncExtTrig); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to loop_count bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddFrameCntEndValueBfGet(device, FPGA9010_BF_TDD_FRAME_COUNTER, &fpgaTddStateMachine->frameCount); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to End_value bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Enable Control module setup */ + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->rx1EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_RX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->rx2EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_RX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->rx3EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_RX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->rx4EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_RX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->orx1EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_ORX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->orx2EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_ORX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->orx3EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_ORX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->orx4EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_ORX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->tx1EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->tx2EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->tx3EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->tx4EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->tx1ToOrx1EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->tx2ToOrx1EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->tx1ToOrx2EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->tx2ToOrx2EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->tx3ToOrx3EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->tx4ToOrx3EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->tx3ToOrx4EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->tx4ToOrx4EnableControl, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->extTrig1, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_EXT1); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->extTrig2, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_EXT2); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->extTrig3, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_EXT3); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_TddEnableControlModuleGet(device, &fpgaTddStateMachine->extTrig4, (uint32_t)FPGA9010_BF_TDD_ENABLE_CONTROL_EXT4); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Datapath control module read */ + recoveryAction = fpga9010_TddDpCtrlEnableBitBfGet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_0, &fpgaTddStateMachine->rxDatapath0.enable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_TddDpCtrlStartValueBfGet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_0, &fpgaTddStateMachine->rxDatapath0.startValue); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddDpCtrlEnableBitBfGet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_1, &fpgaTddStateMachine->rxDatapath1.enable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_TddDpCtrlStartValueBfGet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_1, &fpgaTddStateMachine->rxDatapath1.startValue); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddDpCtrlEnableBitBfGet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_2, &fpgaTddStateMachine->rxDatapath2.enable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_TddDpCtrlStartValueBfGet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_RX_DP_2, &fpgaTddStateMachine->rxDatapath2.startValue); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddDpCtrlEnableBitBfGet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_0, &fpgaTddStateMachine->txDatapath0.enable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_TddDpCtrlStartValueBfGet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_0, &fpgaTddStateMachine->txDatapath0.startValue); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddDpCtrlEnableBitBfGet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_1, &fpgaTddStateMachine->txDatapath1.enable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_TddDpCtrlStartValueBfGet(device, FPGA9010_BF_TDD_DATAPATH_CONTROL_TX_DP_1, &fpgaTddStateMachine->txDatapath1.startValue); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TddEnable(adi_fpga9010_Device_t *device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + recoveryAction = fpga9010_TddFrameCntEnableBfSet(device, FPGA9010_BF_TDD_FRAME_COUNTER, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TddDisable(adi_fpga9010_Device_t *device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t i = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + recoveryAction = fpga9010_TddFrameCntEnableBfSet(device, FPGA9010_BF_TDD_FRAME_COUNTER, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddFrameCntLoopCountEnBfSet(device, FPGA9010_BF_TDD_FRAME_COUNTER, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to loop_count_en bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Disable the enable control modules */ + for (i = 0; i < ADI_FPGA9010_TDDENABLECTRL_CNT; i++) + { + recoveryAction = fpga9010_TddEnableCtrlEnableBfSet(device, enableCtrlAddrArray[i], 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Enable Control module enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_TddEnableCtrlSecEnableBfSet(device, enableCtrlAddrArray[i], 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Secondary Enable Control module enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Disable the datapath control modules */ + for (i = 0; i < ADI_FPGA9010_TDDDATAPATHCTRL_CNT; i++) + { + recoveryAction = fpga9010_TddDpCtrlEnableBitBfSet(device, datapathctrlAddrArray[i], 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TddDataGate(adi_fpga9010_Device_t *device) +{ + //TODO: implement this + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TddEnablesAssertSet(adi_fpga9010_Device_t *device, uint32_t fpgaTddEnables) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t i = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + /* Set the enable control modules */ + for (i = 0; i < ADI_FPGA9010_TDDENABLECTRL_CNT; i++) + { + recoveryAction = fpga9010_TddEnableCtrlManualEnableBfSet(device, enableCtrlAddrArray[i], (uint8_t)((fpgaTddEnables >> i) & 1)); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to manual enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TddEnablesAssertGet(adi_fpga9010_Device_t *device, uint32_t *fpgaTddEnables) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t i = 0; + uint8_t enableRead = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, fpgaTddEnables); + + *fpgaTddEnables = 0; + + /* Get the enable control modules */ + for (i = 0; i < ADI_FPGA9010_TDDENABLECTRL_CNT; i++) + { + recoveryAction = fpga9010_TddEnableCtrlManualEnableBfGet(device, enableCtrlAddrArray[i], &enableRead); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to manual enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + *fpgaTddEnables |= ((uint32_t)enableRead & 1) << i; + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TddOrxPinCfgSet(adi_fpga9010_Device_t *device, adi_fpga9010_OrxPinEncodeCfg_t *orxPinEncodeCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, orxPinEncodeCfg); + + recoveryAction = fpga9010_OrxPinEncodeTokelauModeSelectBfSet(device, FPGA9010_BF_TDD_ORX_PIN_ENCODE, orxPinEncodeCfg->modeSelect); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_OrxPinEncodeTokelauFastSwitchingEnableBfSet(device, FPGA9010_BF_TDD_ORX_PIN_ENCODE, orxPinEncodeCfg->fastSwitchingEnable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_OrxPinEncodeTokelauMode1aOrxSelectLowBfSet(device, FPGA9010_BF_TDD_ORX_PIN_ENCODE, orxPinEncodeCfg->mode1aOrxSelectLow); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_OrxPinEncodeTokelauMode1aOrxSelectHighBfSet(device, FPGA9010_BF_TDD_ORX_PIN_ENCODE, orxPinEncodeCfg->mode1aOrxSelectHigh); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_OrxPinEncodeTokelauMode3OrxSelectBfSet(device, FPGA9010_BF_TDD_ORX_PIN_ENCODE, orxPinEncodeCfg->mode3OrxSelect); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_OrxPinEncodeTokelauOrxSelectSetupTimeBfSet(device, FPGA9010_BF_TDD_ORX_PIN_ENCODE, orxPinEncodeCfg->orxSelectSetupTime - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_OrxPinEncodeTokelauOrxEnableHighTimeBfSet(device, FPGA9010_BF_TDD_ORX_PIN_ENCODE, orxPinEncodeCfg->orxEnableHighTime - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_OrxPinEncodeTokelauOrxEnableLowTimeBfSet(device, FPGA9010_BF_TDD_ORX_PIN_ENCODE, orxPinEncodeCfg->orxEnableLowTime - 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); + +} + +int32_t adi_fpga9010_TddOrxPinCfgGet(adi_fpga9010_Device_t *device, adi_fpga9010_OrxPinEncodeCfg_t *orxPinEncodeCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint16_t rawRegisterValue = 0; + uint8_t modeSelectReadback = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, orxPinEncodeCfg); + + recoveryAction = fpga9010_OrxPinEncodeTokelauModeSelectBfGet(device, FPGA9010_BF_TDD_ORX_PIN_ENCODE, &modeSelectReadback); + orxPinEncodeCfg->modeSelect = (adi_fpga9010_OrxPinEncodeModes_e)modeSelectReadback; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_OrxPinEncodeTokelauFastSwitchingEnableBfGet(device, FPGA9010_BF_TDD_ORX_PIN_ENCODE, &orxPinEncodeCfg->fastSwitchingEnable); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_OrxPinEncodeTokelauMode1aOrxSelectLowBfGet(device, FPGA9010_BF_TDD_ORX_PIN_ENCODE, &orxPinEncodeCfg->mode1aOrxSelectLow); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_OrxPinEncodeTokelauMode1aOrxSelectHighBfGet(device, FPGA9010_BF_TDD_ORX_PIN_ENCODE, &orxPinEncodeCfg->mode1aOrxSelectHigh); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_OrxPinEncodeTokelauMode3OrxSelectBfGet(device, FPGA9010_BF_TDD_ORX_PIN_ENCODE, &orxPinEncodeCfg->mode3OrxSelect); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_OrxPinEncodeTokelauOrxSelectSetupTimeBfGet(device, FPGA9010_BF_TDD_ORX_PIN_ENCODE, &rawRegisterValue); + orxPinEncodeCfg->orxSelectSetupTime = rawRegisterValue + 1; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_OrxPinEncodeTokelauOrxEnableHighTimeBfGet(device, FPGA9010_BF_TDD_ORX_PIN_ENCODE, &rawRegisterValue); + orxPinEncodeCfg->orxEnableHighTime = rawRegisterValue + 1; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_OrxPinEncodeTokelauOrxEnableLowTimeBfGet(device, FPGA9010_BF_TDD_ORX_PIN_ENCODE, &rawRegisterValue); + orxPinEncodeCfg->orxEnableLowTime = rawRegisterValue + 1; + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); + +} + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_tx.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_tx.c new file mode 100644 index 0000000..97409f8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_tx.c @@ -0,0 +1,963 @@ +/** + * \file: adi_fpga9010_tx.c + * + * \brief Contains top level tx fpga9010 related functions + * + * FPGA9010 API Version: $ADI_FPGA9010_API_VERSION$ + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9010_user.h" +#include "adi_fpga9010_tx.h" +#include "adi_fpga9010_error.h" +#include "../../private/include/fpga9010_bf_dp_tollgate.h" +#include "../../private/include/fpga9010_bf_dp_tx_dma.h" +#include "../../private/include/fpga9010_bf_dp_capture_control.h" + +int32_t adi_fpga9010_TxTollgateSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, adi_fpga9010_TxTollgateCfg_t *tollGateCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTollgateChanAddr_e instanceAddress = FPGA9010_BF_DP_TOLLGATE_RX_0; + uint32_t i = 0; + adi_fpga9010_FramerSel_e dataMoverSel = ADI_FPGA9010_FRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, tollGateCfg); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, txDataMoverSelMask, "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_FRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_FramerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_FRAMER_0: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_TX_0; + break; + case ADI_FPGA9010_FRAMER_1: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = fpga9010_DpTollgateEdgeLevelBfSet(device, instanceAddress, tollGateCfg->tollGateEdgeOrLvl); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to detection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTollgateHighRisingLowFallingBfSet(device, instanceAddress, tollGateCfg->tollGateHiRiseOrLoFall); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to polarity register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTollgateTriggerSelectBfSet(device, instanceAddress, (uint32_t)tollGateCfg->tollGateTrigSource); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to selection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TxTollgateGet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e txDataMoverSel, adi_fpga9010_TxTollgateCfg_t *tollGateCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTollgateChanAddr_e baseAddress = FPGA9010_BF_DP_TOLLGATE_TX_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, tollGateCfg); + + switch (txDataMoverSel) + { + case ADI_FPGA9010_FRAMER_0: + baseAddress = FPGA9010_BF_DP_TOLLGATE_TX_0; + break; + case ADI_FPGA9010_FRAMER_1: + baseAddress = FPGA9010_BF_DP_TOLLGATE_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, txDataMoverSel, "Invalid datamover selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + recoveryAction = fpga9010_DpTollgateEdgeLevelBfGet(device, baseAddress, &tollGateCfg->tollGateEdgeOrLvl); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to detection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTollgateHighRisingLowFallingBfGet(device, baseAddress, &tollGateCfg->tollGateHiRiseOrLoFall); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to polarity register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTollgateTriggerSelectBfGet(device, baseAddress, (uint32_t *)&tollGateCfg->tollGateTrigSource); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to selection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TxTollgateResetSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, uint8_t resetVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTollgateChanAddr_e instanceAddress = FPGA9010_BF_DP_TOLLGATE_TX_0; + uint32_t i = 0; + adi_fpga9010_FramerSel_e dataMoverSel = ADI_FPGA9010_FRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_FRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_FramerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_FRAMER_0: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_TX_0; + break; + case ADI_FPGA9010_FRAMER_1: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = fpga9010_DpTollgateResetTollgateBfSet(device, instanceAddress, resetVal); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to reset register"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TxTollgateResetGet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, uint8_t *resetVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTollgateChanAddr_e instanceAddress = FPGA9010_BF_DP_TOLLGATE_TX_0; + uint32_t i = 0; + adi_fpga9010_FramerSel_e dataMoverSel = ADI_FPGA9010_FRAMER_0; + uint8_t resetBitRead = 0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, resetVal); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *resetVal = 0; + + for (i = 0; i < ADI_FPGA9010_NUM_OF_FRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_FramerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_FRAMER_0: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_TX_0; + break; + case ADI_FPGA9010_FRAMER_1: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = fpga9010_DpTollgateResetTollgateBfGet(device, instanceAddress, &resetBitRead); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read from reset register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + *resetVal |= (resetBitRead & 0x01) << i; + } + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TxDmaSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, adi_fpga9010_TxDmaCfg_t *txDmaCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTxDmaChanAddr_e instanceAddress = FPGA9010_BF_DP_DMA_TX_0; + uint32_t i = 0; + adi_fpga9010_FramerSel_e dataMoverSel = ADI_FPGA9010_FRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, txDmaCfg); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_FRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_FramerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_FRAMER_0: + instanceAddress = FPGA9010_BF_DP_DMA_TX_0; + break; + case ADI_FPGA9010_FRAMER_1: + instanceAddress = FPGA9010_BF_DP_DMA_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* TODO: start address could be changed at runtime by this function, and this length check is not enough to ensure RAM buffers do not overlap */ + if (txDmaCfg->length > TX_DMA_SIZE) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "FPGA Tx DMA length too large for RAM buffer area"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = fpga9010_DpTxDmaEnableEnhancedModeBfSet(device, instanceAddress, txDmaCfg->enableEnhancedMode); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write enableEnhancedMode bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaEnableSgBfSet(device, instanceAddress, txDmaCfg->enableSg); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write enableSg bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaLengthBfSet(device, instanceAddress, txDmaCfg->length); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write length bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaSqFirstDescriptorBfSet(device, instanceAddress, txDmaCfg->sgFirstDescriptor); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write sgFirstDescriptor bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* todo: writing to this seems to be clearing the status register. debug later */ +// recoveryAction = fpga9010_DpTxDmaSgLastDescriptorBfSet(device, instanceAddress, txDmaCfg->sgLastDescriptor); +// ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write sgLastDescriptor bitfield"); +// ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaSimpleStartAddrBfSet(device, instanceAddress, txDmaCfg->simpleStartAddr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write simpleStartAddr bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaValidDataWidthStreamBfSet(device, instanceAddress, txDmaCfg->validDataWidthStream); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write validDataWidthStream bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaContinuousBfSet(device, instanceAddress, txDmaCfg->continuous); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write continuous bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9010_TxDmaInit(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, adi_fpga9010_TxDmaCfg_t *txDmaCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTxDmaChanAddr_e instanceAddress = FPGA9010_BF_DP_DMA_TX_0; + uint32_t i = 0; + adi_fpga9010_FramerSel_e dataMoverSel = ADI_FPGA9010_FRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, txDmaCfg); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_FRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_FramerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_FRAMER_0: + instanceAddress = FPGA9010_BF_DP_DMA_TX_0; + break; + case ADI_FPGA9010_FRAMER_1: + instanceAddress = FPGA9010_BF_DP_DMA_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = fpga9010_DpTxDmaEnableEnhancedModeBfSet(device, instanceAddress, txDmaCfg->enableEnhancedMode); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write enableEnhancedMode bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaEnableSgBfSet(device, instanceAddress, txDmaCfg->enableSg); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write enableSg bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaSqFirstDescriptorBfSet(device, instanceAddress, txDmaCfg->sgFirstDescriptor); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write sgFirstDescriptor bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* todo: writing to this seems to be clearing the status register. debug later */ +// recoveryAction = fpga9010_DpTxDmaSgLastDescriptorBfSet(device, instanceAddress, txDmaCfg->sgLastDescriptor); +// ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write sgLastDescriptor bitfield"); +// ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaSimpleStartAddrBfSet(device, instanceAddress, txDmaCfg->simpleStartAddr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write simpleStartAddr bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaValidDataWidthStreamBfSet(device, instanceAddress, txDmaCfg->validDataWidthStream); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write validDataWidthStream bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TxDmaGet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e txDataMoverSel, adi_fpga9010_TxDmaCfg_t *txDmaCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTxDmaChanAddr_e baseAddress = FPGA9010_BF_DP_DMA_TX_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, txDmaCfg); + + switch (txDataMoverSel) + { + case ADI_FPGA9010_FRAMER_0: + baseAddress = FPGA9010_BF_DP_DMA_TX_0; + break; + case ADI_FPGA9010_FRAMER_1: + baseAddress = FPGA9010_BF_DP_DMA_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, txDataMoverSel, "Invalid datamover selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + recoveryAction = fpga9010_DpTxDmaActiveBfGet(device, baseAddress, &txDmaCfg->active); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read active bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaCompleteBfGet(device, baseAddress, &txDmaCfg->complete); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read complete bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaEnableEnhancedModeBfGet(device, baseAddress, &txDmaCfg->enableEnhancedMode); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read enableEnhancedMode bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaEnableSgBfGet(device, baseAddress, &txDmaCfg->enableSg); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read enableSg bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaHaltCompleteBfGet(device, baseAddress, &txDmaCfg->haltComplete); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read haltComplete bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaLengthBfGet(device, baseAddress, &txDmaCfg->length); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read length bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaUnderflowBfGet(device, baseAddress, &txDmaCfg->underflow); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read underflow bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaRunStopBfGet(device, baseAddress, &txDmaCfg->runStop); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read runStop bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaContinuousBfGet(device, baseAddress, &txDmaCfg->continuous); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read continuous bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaSqFirstDescriptorBfGet(device, baseAddress, &txDmaCfg->sgFirstDescriptor); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read sgFirstDescriptor bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaSgLastDescriptorBfGet(device, baseAddress, &txDmaCfg->sgLastDescriptor); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read sgLastDescriptor bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaSimpleStartAddrBfGet(device, baseAddress, &txDmaCfg->simpleStartAddr); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read simpleStartAddr bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpTxDmaValidDataWidthStreamBfGet(device, baseAddress, &txDmaCfg->validDataWidthStream); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read validDataWidthStream bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TxModeSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, adi_fpga9010_TxDatamoverMode_e txMode) +{ + UNUSED_PARA(txDataMoverSelMask); + UNUSED_PARA(txMode); + //TODO: implement this + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} + +int32_t adi_fpga9010_TxModeGet(adi_fpga9010_Device_t *device, uint8_t *transmitModeMask) +{ + UNUSED_PARA(transmitModeMask); + //TODO: implement this + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} + +int32_t adi_fpga9010_TxTollgateTriggerSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, adi_fpga9010_TxTollgateTrigSources_e triggerSelect) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTollgateChanAddr_e instanceAddress = FPGA9010_BF_DP_TOLLGATE_TX_0; + uint32_t i = 0; + adi_fpga9010_FramerSel_e dataMoverSel = ADI_FPGA9010_FRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_FRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_FramerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_FRAMER_0: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_TX_0; + break; + case ADI_FPGA9010_FRAMER_1: + instanceAddress = FPGA9010_BF_DP_TOLLGATE_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + adi_fpga9010_TxTollgateResetSet(device, txDataMoverSelMask, 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + fpga9010_DpTollgateTriggerSelectBfSet(device, instanceAddress, (uint32_t)triggerSelect); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to triggerSelect bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_TxTollgateResetSet(device, txDataMoverSelMask, 0); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TxTollgateTriggerGet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e txDataMoverSel, adi_fpga9010_TxTollgateTrigSources_e *triggerSelect) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTollgateChanAddr_e baseAddress = FPGA9010_BF_DP_TOLLGATE_TX_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, triggerSelect); + + switch (txDataMoverSel) + { + case ADI_FPGA9010_FRAMER_0: + baseAddress = FPGA9010_BF_DP_TOLLGATE_TX_0; + break; + case ADI_FPGA9010_FRAMER_1: + baseAddress = FPGA9010_BF_DP_TOLLGATE_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, txDataMoverSel, "Invalid datamover selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + recoveryAction = fpga9010_DpTollgateTriggerSelectBfGet(device, baseAddress, (uint32_t *)triggerSelect); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read triggerSelect bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TxDatamoverEnableSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask) +{ + UNUSED_PARA(txDataMoverSelMask); + //TODO: implement this using adi_fpga_txChannelSel_e + //TxChannelSel_t will refer to all modules within a channel + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} + +int32_t adi_fpga9010_TxDatamoverEnableGet(adi_fpga9010_Device_t *device, uint32_t *txDataMoverSelMask) +{ + UNUSED_PARA(txDataMoverSelMask); + //TODO: implement this using adi_fpga_txChannelSel_e + //TxChannelSel_t will refer to all modules within a channel + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} + +int32_t adi_fpga9010_TxDataChainConfigure(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, adi_fpga9010_TxTollgateTrigSources_e triggerSelect, adi_fpga9010_TxDmaCfg_t *txDmaCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* reset capture control */ + recoveryAction = fpga9010_DpCaptureControlResetBfSet(device, FPGA9010_BF_DP_CAPTURE_CONTROL_TX, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* set trigger */ + adi_fpga9010_TxTollgateTriggerSet(device, txDataMoverSelMask, triggerSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*reset dmas */ + adi_fpga9010_TxDmaResetSet(device, txDataMoverSelMask, 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure dmas */ + adi_fpga9010_TxDmaSet(device, txDataMoverSelMask, txDmaCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* set run_stop bit */ + adi_fpga9010_TxDmaRunStopSet(device, txDataMoverSelMask, 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* pass token to start dma arbitration */ + recoveryAction = fpga9010_DpCaptureControlResetBfSet(device, FPGA9010_BF_DP_CAPTURE_CONTROL_TX, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_DpCaptureControlPassTokenBfSet(device, FPGA9010_BF_DP_CAPTURE_CONTROL_TX, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control PassToken bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TxDataChainReset(adi_fpga9010_Device_t *device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t active = 0; + uint8_t haltComplete = 0; + uint8_t i = 0; + static const uint8_t TX_DATA_CHAIN_RESET_MAX_COUNT = 5; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* reset */ + recoveryAction = fpga9010_DpCaptureControlDatapathActiveBfSet(device, FPGA9010_BF_DP_CAPTURE_CONTROL_TX, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to DatapathActive bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9010_DpCaptureControlResetBfSet(device, FPGA9010_BF_DP_CAPTURE_CONTROL_TX, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Clear DMA 0 */ + haltComplete = 0; + recoveryAction = fpga9010_DpTxDmaActiveBfGet(device, FPGA9010_BF_DP_DMA_TX_0, &active); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_TxDmaRunStopSet(device, ADI_FPGA9010_FRAMER_0, 0); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (active == 1) + { + haltComplete = 0; + for (i = 0; i < TX_DATA_CHAIN_RESET_MAX_COUNT; i++) + { + recoveryAction = fpga9010_DpTxDmaHaltCompleteBfGet(device, FPGA9010_BF_DP_DMA_TX_0, &haltComplete); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + if (haltComplete != 0) + { + break; + } + } + + if (i == TX_DATA_CHAIN_RESET_MAX_COUNT) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "TX0 DMA Halt failed."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + adi_fpga9010_TxDmaResetSet(device, ADI_FPGA9010_FRAMER_0, 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Clear DMA 1 */ + haltComplete = 0; + active = 0; + recoveryAction = fpga9010_DpTxDmaActiveBfGet(device, FPGA9010_BF_DP_DMA_TX_1, &active); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_TxDmaRunStopSet(device, ADI_FPGA9010_FRAMER_1, 0); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (active == 1) + { + for (i = 0; i < TX_DATA_CHAIN_RESET_MAX_COUNT; i++) + { + recoveryAction = fpga9010_DpTxDmaHaltCompleteBfGet(device, FPGA9010_BF_DP_DMA_TX_1, &haltComplete); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + if (haltComplete != 0) + { + break; + } + } + + if (i == TX_DATA_CHAIN_RESET_MAX_COUNT) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "TX1 DMA Halt failed."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + adi_fpga9010_TxDmaResetSet(device, ADI_FPGA9010_FRAMER_1, 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + adi_fpga9010_TxTollgateResetSet(device, ADI_FPGA9010_FRAMER_ALL, 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9010_TxDataStart(adi_fpga9010_Device_t *device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + recoveryAction = fpga9010_DpCaptureControlDatapathActiveBfSet(device, FPGA9010_BF_DP_CAPTURE_CONTROL_TX, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to DatapathActive bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TxDataStop(adi_fpga9010_Device_t *device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + ADI_NULL_DEVICE_PTR_RETURN(device); + + recoveryAction = fpga9010_DpTxDmaRunStopBfSet(device, FPGA9010_BF_DP_DMA_TX_0, 0); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write runStop bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9010_DpCaptureControlResetBfSet(device, FPGA9010_BF_DP_CAPTURE_CONTROL_TX, 1); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write to DatapathActive bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TxDataSet(adi_fpga9010_Device_t *device, adi_fpga9010_FramerSel_e txDataMoverSel, int32_t data[], uint32_t dataSize) +{ + UNUSED_PARA(txDataMoverSel); + UNUSED_PARA(data); + UNUSED_PARA(dataSize); + //TODO: implement this + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} + +int32_t adi_fpga9010_TxDmaResetSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, uint8_t reset) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTxDmaChanAddr_e instanceAddress = FPGA9010_BF_DP_DMA_TX_0; + uint32_t i = 0; + adi_fpga9010_FramerSel_e dataMoverSel = ADI_FPGA9010_FRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_FRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_FramerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_FRAMER_0: + instanceAddress = FPGA9010_BF_DP_DMA_TX_0; + break; + case ADI_FPGA9010_FRAMER_1: + instanceAddress = FPGA9010_BF_DP_DMA_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = fpga9010_DpTxDmaResetBfSet(device, instanceAddress, reset); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, recoveryAction, NULL, "Could not write reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TxDmaRunStopSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, uint8_t runStop) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTxDmaChanAddr_e instanceAddress = FPGA9010_BF_DP_DMA_TX_0; + uint32_t i = 0; + adi_fpga9010_FramerSel_e dataMoverSel = ADI_FPGA9010_FRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_FRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_FramerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_FRAMER_0: + instanceAddress = FPGA9010_BF_DP_DMA_TX_0; + break; + case ADI_FPGA9010_FRAMER_1: + instanceAddress = FPGA9010_BF_DP_DMA_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = fpga9010_DpTxDmaRunStopBfSet(device, instanceAddress, runStop); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, recoveryAction, NULL, "Could not write runStop bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9010_TxSamplesSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, uint32_t numSamples) +{ + UNUSED_PARA(txDataMoverSelMask); + UNUSED_PARA(numSamples); + //TODO: implement this + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} + +int32_t adi_fpga9010_TxDmaLengthSet(adi_fpga9010_Device_t *device, uint32_t txDataMoverSelMask, uint32_t numBytes) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9010_BfDpTxDmaChanAddr_e instanceAddress = FPGA9010_BF_DP_DMA_TX_0; + uint32_t i = 0; + adi_fpga9010_FramerSel_e dataMoverSel = ADI_FPGA9010_FRAMER_0; + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9010_NUM_OF_FRAMERS; i++) + { + dataMoverSel = (adi_fpga9010_FramerSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9010_FRAMER_0: + instanceAddress = FPGA9010_BF_DP_DMA_TX_0; + break; + case ADI_FPGA9010_FRAMER_1: + instanceAddress = FPGA9010_BF_DP_DMA_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (numBytes > TX_DMA_SIZE) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "FPGA Tx DMA length too large for RAM buffer area"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = fpga9010_DpTxDmaLengthBfSet(device, instanceAddress, numBytes); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, recoveryAction, NULL, "Could not write length bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return (device->common.error.newAction); +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_utilities.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_utilities.c new file mode 100644 index 0000000..fd6ebac --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/public/src/adi_fpga9010_utilities.c @@ -0,0 +1,2066 @@ + +/*! +* \file adi_fpga9010_utilities.c +* \brief Contains FPGA9010 API configuration and run-time type definitions for utitility functions +* +* ADRV9010 API Version: 6.4.0.14 +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9010 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9010_user.h" +#include "adi_fpga9010_utilities.h" +#include "adi_fpga9010_rx.h" +#include "adi_fpga9010_tx.h" + +#include "adi_common_error.h" +#include "adi_fpga9010_hal.h" + +int32_t adi_fpga9010_CalculateQpllSettings(adi_fpga9010_Device_t *device, const uint32_t refClk_kHz, const uint32_t fastestLaneRate_kHz, adi_fpga9010_QpllCfg_t *qplls) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t _N[] = { 16, 20, 32, 40, 60, 64, 66, 75, 80, 84, 90, 96, 100, 112, 120, 125, 150 }; + uint8_t _NLength = 16; + uint8_t n = 0; + uint8_t _M[] = { 1, 2, 3, 4 }; + uint8_t _MLength = 3; + uint8_t m = 0; + uint8_t _D[] = { 1, 2, 4, 8, 16 }; + uint8_t _DLength = 5; + uint8_t d = 0; + uint32_t qpllVcoFreq_kHz = 0; + uint32_t qpllVcoOutFreq_kHz = 0; + adi_fpga9010_LaneClkSel_e qpllBand = ADI_FPGA9010_QPLLCLK0; + uint8_t validConfigFound = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, qplls); + + for(m = _MLength ; m >= 0 && m <= 3 ; m--) + { + for(n = _NLength ; n >= 0 && n <= _NLength ; n--) + { + for(d = 0 ; d < _DLength ; d++) + { + qpllVcoFreq_kHz = refClk_kHz * _N[n] / _M[m]; + qpllVcoOutFreq_kHz = qpllVcoFreq_kHz / 2; + + if ((qpllVcoFreq_kHz >= 9800000) && (qpllVcoFreq_kHz <= 16300000)) + { + qpllBand = ADI_FPGA9010_QPLLCLK0; + } + else if ((qpllVcoFreq_kHz >= 8000000) && (qpllVcoFreq_kHz <= 13000000)) + { + qpllBand = ADI_FPGA9010_QPLLCLK1; + } + else + { + continue; + } + + if (qpllVcoOutFreq_kHz * 2 / _D[d] == fastestLaneRate_kHz) + { + qplls->mVal = _M[m]; + qplls->nVal = _N[n]; + qplls->band = qpllBand; + qplls->qpllVco_kHz = qpllVcoFreq_kHz; + + validConfigFound = 1; + } + } + } + } + + if (validConfigFound == 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Could not find a valid configuration for qpll"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* These are magic numbers derived from observation of the values Xilinx produces for various + * refClk_kHz and fastestLaneRate_kHz combinations. + */ + if (qplls->qpllVco_kHz < 10000000) + { + qplls->cfg4 = 0x0000; + qplls->lockCfg = 0x21E8; + qplls->lockCfgG3 = 0x21E8; + } + else if (qplls->qpllVco_kHz < 14000000) + { + qplls->cfg4 = 0x0009; + qplls->lockCfg = 0x21E8; + qplls->lockCfgG3 = 0x21E8; + } + else + { + qplls->cfg4 = 0x001B; + qplls->lockCfg = 0x25E8; + qplls->lockCfgG3 = 0x25E8; + } + + if (qplls->nVal < 80) + { + qplls->cp = 0x001F; + } + else + { + qplls->cp = 0x01FF; + } + + qplls->lpf = 0x03FC; + + return recoveryAction; +} + +int32_t adi_fpga9010_CalculateQpllDivisor(adi_fpga9010_Device_t *device, uint32_t qpllVcoFreq_kHz, const uint32_t desiredLaneRate_kHz, uint8_t *dVal) +{ + uint8_t _D[] = { 1, 2, 4, 8, 16 }; + uint8_t _DLength = 5; + uint8_t d = 0; + uint8_t desiredDVal = 1; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, dVal); + + /* Prevent divide by 0 */ + if (desiredLaneRate_kHz == 0) + { + *dVal = 1; /* Return valid divide by 1 setting */ + return recoveryAction; + + } + else + { + desiredDVal = (uint8_t)(qpllVcoFreq_kHz / desiredLaneRate_kHz); + } + + for (d = 0; d < _DLength; d++) + { + if (desiredDVal == _D[d]) + { + *dVal = _D[d]; + return recoveryAction; + } + } + + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Desired PLL divisor invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_fpga9010_CalculateMmcmSettings(adi_fpga9010_Device_t *device, const uint32_t refClk_kHz, adi_fpga9010_MmcmCfg_t *mmcmConfig) +{ + uint32_t mmcmVcoFreq_kHz = 0; + uint32_t m; + uint32_t d; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, mmcmConfig); + + for (m = 0; m < ADI_FPGA9010_NUM_MMCM_OUTPUT_CLOCKS; m++) + { + if (mmcmConfig->outputClkFreq_kHz[m] == 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Cannot have a 0 value for any output clocks in mmcm"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* find an m & d value that works for all output clocks */ + for (d = 1; d < 256; d++) + { + for (m = 255; m > 0; m--) + { + mmcmVcoFreq_kHz = refClk_kHz * m / d; + + if (mmcmVcoFreq_kHz > 1600000 || mmcmVcoFreq_kHz < 600000) + { + continue; + } + + /* with the current m & d, make sure the output clocks can be achieved within the channel divider limits */ + if (((mmcmVcoFreq_kHz % mmcmConfig->outputClkFreq_kHz[0]) == 0) && ((mmcmVcoFreq_kHz % mmcmConfig->outputClkFreq_kHz[1]) == 0) && ((mmcmVcoFreq_kHz % mmcmConfig->outputClkFreq_kHz[2]) == 0) && + ((mmcmVcoFreq_kHz % mmcmConfig->outputClkFreq_kHz[3]) == 0) && ((mmcmVcoFreq_kHz % mmcmConfig->outputClkFreq_kHz[4]) == 0) && ((mmcmVcoFreq_kHz % mmcmConfig->outputClkFreq_kHz[5]) == 0) && + ((mmcmVcoFreq_kHz % mmcmConfig->outputClkFreq_kHz[6]) == 0) && + + ((mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[0]) < 256) && ((mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[1]) < 256) && ((mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[2]) < 256) && + ((mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[3]) < 256) && ((mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[4]) < 256) && ((mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[5]) < 256) && + ((mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[6]) < 256)) + { + mmcmConfig->mVal = m; + mmcmConfig->dVal = d; + mmcmConfig->outputClkDiv[0] = mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[0]; + mmcmConfig->outputClkDiv[1] = mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[1]; + mmcmConfig->outputClkDiv[2] = mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[2]; + mmcmConfig->outputClkDiv[3] = mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[3]; + mmcmConfig->outputClkDiv[4] = mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[4]; + mmcmConfig->outputClkDiv[5] = mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[5]; + mmcmConfig->outputClkDiv[6] = mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[6]; + + return recoveryAction; + } + } + } + + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Could not find a valid configuration for mmcm"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/* Returns 1 if a PN invert is needed for the specified ADRV9010 serializer lane number, + * correcting the lane swaps on the daughtercard. Returns 0 if no invert necessary. + */ +static uint8_t fpga9010_applyPcbDesLanePnInvert(uint8_t adrv9010SerLane) +{ + uint8_t fpgaDesLanePnInvert = 0; + switch (adrv9010SerLane) + { + /* only includes daughtercard lane PN invert for ADRV9010EE01A */ + case 0: fpgaDesLanePnInvert = 1; break; + case 1: fpgaDesLanePnInvert = 1; break; + case 2: fpgaDesLanePnInvert = 1; break; + case 3: fpgaDesLanePnInvert = 1; break; + case 4: fpgaDesLanePnInvert = 1; break; + case 5: fpgaDesLanePnInvert = 1; break; + case 6: fpgaDesLanePnInvert = 1; break; + case 7: fpgaDesLanePnInvert = 1; break; + default: fpgaDesLanePnInvert = 0; break; + } + + return fpgaDesLanePnInvert; +} + +/* Returns 1 if a PN invert is needed for the specified ADRV9010 deserializer lane number, + * correcting the lane swaps on the daughtercard. Returns 0 if no invert necessary. + */ +static uint8_t fpga9010_applyPcbSerLanePnInvert(uint8_t adrv9010DesLane) +{ + uint8_t fpgaSerLanePnInvert = 0; + switch (adrv9010DesLane) + { + /* TODO: Move this up to board layer where lane swaps are set, as it is specific to the eval board, not the FPGA driver */ + /* only includes daughtercard lane PN invert for ADRV9010EE01A */ + case 0: fpgaSerLanePnInvert = 1; break; + case 1: fpgaSerLanePnInvert = 0; break; + case 2: fpgaSerLanePnInvert = 1; break; + case 3: fpgaSerLanePnInvert = 0; break; + case 4: fpgaSerLanePnInvert = 1; break; + case 5: fpgaSerLanePnInvert = 0; break; + case 6: fpgaSerLanePnInvert = 1; break; + case 7: fpgaSerLanePnInvert = 0; break; + default: fpgaSerLanePnInvert = 0; break; + + } + + return fpgaSerLanePnInvert; +} + +int32_t static fpga9010_SerializerCfg(adi_fpga9010_Device_t *device, adi_fpga9010_Init_t *fpgaInit, uint8_t laneIndex, uint8_t frmOutputIndex, uint8_t dVal, uint32_t refClk_kHz, uint8_t framerSel) +{ + uint8_t fpgaLane = fpgaInit->datapath.pcbSerLaneSwap[laneIndex]; + uint32_t laneRate = fpgaInit->clocks.qpll.qpllVco_kHz / dVal; + + fpgaInit->datapath.framerCfg[framerSel].laneXbar[fpgaLane] = frmOutputIndex; + + fpgaInit->datapath.serializerCfg[fpgaLane].cpllRefClkSel = 0x01; + fpgaInit->datapath.serializerCfg[fpgaLane].txPllClkSel = (fpgaInit->clocks.qpll.band == ADI_FPGA9010_QPLLCLK0) ? ADI_FPGA9010_QPLLCLK0 : ADI_FPGA9010_QPLLCLK1; + fpgaInit->datapath.serializerCfg[fpgaLane].rate = dVal; + fpgaInit->datapath.serializerCfg[fpgaLane].polarity = fpga9010_applyPcbSerLanePnInvert(laneIndex); + fpgaInit->datapath.serializerCfg[fpgaLane].precursor = 4; + fpgaInit->datapath.serializerCfg[fpgaLane].diffCtrl = 12; + fpgaInit->datapath.serializerCfg[fpgaLane].powerDown = 0; + fpgaInit->datapath.serializerCfg[fpgaLane].txClk25Div = ((uint16_t)((refClk_kHz + 25000) / 25000) - 1) << 11; /* 25000 here since Clk25 expects refClk in MHz. Also need to integer round */ + + if (device->devStateInfo.designId == ADI_FPGA9010_JESD204B_DEVICEID) + { + fpgaInit->datapath.serializerCfg[fpgaLane].postcursor = 12; + fpgaInit->datapath.serializerCfg[fpgaLane].encoder8b10bEnable = 1; + + if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_9_GHZ && laneRate == ADI_FPGA9010_4P91_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0040; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_9P2_GHZ && laneRate == ADI_FPGA9010_9P2_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0040; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_9_GHZ && laneRate == ADI_FPGA9010_9_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0040; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_11_GHZ && laneRate == ADI_FPGA9010_11_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0000; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_12P28_GHZ && laneRate == ADI_FPGA9010_6P14_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0000; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_12P28_GHZ && laneRate == ADI_FPGA9010_12P28_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0000; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_14_GHZ && laneRate == ADI_FPGA9010_7_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0000; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_14_GHZ && laneRate == ADI_FPGA9010_14_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0000; + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Unsupported FPGA clock configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else if (device->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + fpgaInit->datapath.serializerCfg[fpgaLane].postcursor = 16; + fpgaInit->datapath.serializerCfg[fpgaLane].encoder8b10bEnable = 0; + + if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_10_GHZ && laneRate == ADI_FPGA9010_2P53_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPhdlyCfg1 = 0x0075; + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0040; + fpgaInit->datapath.serializerCfg[fpgaLane].txProgdivCfg = 0xC388; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_10_GHZ && laneRate == ADI_FPGA9010_5_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPhdlyCfg1 = 0x0075; + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0040; + fpgaInit->datapath.serializerCfg[fpgaLane].txProgdivCfg = 0xC288; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_10_GHZ && laneRate == ADI_FPGA9010_10_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPhdlyCfg1 = 0x0075; + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0040; + fpgaInit->datapath.serializerCfg[fpgaLane].txProgdivCfg = 0xC208; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_12P16_GHZ && laneRate == ADI_FPGA9010_3_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPhdlyCfg1 = 0x0075; + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0000; + fpgaInit->datapath.serializerCfg[fpgaLane].txProgdivCfg = 0xC388; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_12P16_GHZ && laneRate == ADI_FPGA9010_6P08_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPhdlyCfg1 = 0x0075; + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0000; + fpgaInit->datapath.serializerCfg[fpgaLane].txProgdivCfg = 0xC288; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_12P16_GHZ && laneRate == ADI_FPGA9010_12P16_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPhdlyCfg1 = 0x0075; + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0000; + fpgaInit->datapath.serializerCfg[fpgaLane].txProgdivCfg = 0xC208; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_16_GHZ && laneRate == ADI_FPGA9010_2P02_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPhdlyCfg1 = 0x0075; + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0000; + fpgaInit->datapath.serializerCfg[fpgaLane].txProgdivCfg = 0xC388; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_16_GHZ && laneRate == ADI_FPGA9010_4P05_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPhdlyCfg1 = 0x0075; + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0000; + fpgaInit->datapath.serializerCfg[fpgaLane].txProgdivCfg = 0xC388; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_16_GHZ && laneRate == ADI_FPGA9010_8_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPhdlyCfg1 = 0x0075; + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0000; + fpgaInit->datapath.serializerCfg[fpgaLane].txProgdivCfg = 0xC288; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_16_GHZ && laneRate == ADI_FPGA9010_16_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPhdlyCfg1 = 0x00D5; + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0000; + fpgaInit->datapath.serializerCfg[fpgaLane].txProgdivCfg = 0xC208; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_8_GHZ && laneRate == ADI_FPGA9010_8_GHZ) + { + fpgaInit->datapath.serializerCfg[fpgaLane].txPhdlyCfg1 = 0x0075; + fpgaInit->datapath.serializerCfg[fpgaLane].txPiCfg3 = 0x0000; + fpgaInit->datapath.serializerCfg[fpgaLane].txProgdivCfg = 0xC288; + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Unsupported FPGA clock configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t static fpga9010_DeserializerCfg(adi_fpga9010_Device_t *device, adi_fpga9010_Init_t *fpgaInit, uint8_t adrv9010FramerLanexbarVal, uint8_t defInputIndex, uint8_t dVal, uint32_t refClk_kHz, uint8_t deframerSel) +{ + uint8_t fpgaLane = fpgaInit->datapath.pcbDesLaneSwap[adrv9010FramerLanexbarVal]; + uint32_t laneRate = fpgaInit->clocks.qpll.qpllVco_kHz / dVal; + + fpgaInit->datapath.deframerCfg[deframerSel].laneXbar[defInputIndex++] = fpgaInit->datapath.pcbDesLaneSwap[adrv9010FramerLanexbarVal]; + //for each deserializer used by deframer 0 setup its parameters + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPllClkSel = (fpgaInit->clocks.qpll.band == ADI_FPGA9010_QPLLCLK0) ? ADI_FPGA9010_QPLLCLK0 : ADI_FPGA9010_QPLLCLK1; + fpgaInit->datapath.deserializerCfg[fpgaLane].rate = dVal; + fpgaInit->datapath.deserializerCfg[fpgaLane].polarity = fpga9010_applyPcbDesLanePnInvert(adrv9010FramerLanexbarVal); + fpgaInit->datapath.deserializerCfg[fpgaLane].powerDown = 0; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeLpmEn = 1; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxClk25Div = ((uint16_t)((refClk_kHz + 25000) / 25000) - 1) << 3; /* 25000 here since Clk25 expects refClk in MHz. Also need to integer round */ + + if (device->devStateInfo.designId == ADI_FPGA9010_JESD204B_DEVICEID) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].encoder8b10bEnable = 1; + + if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_9_GHZ && laneRate == ADI_FPGA9010_4P91_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x0756; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7870; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0200; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0000; + + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_9_GHZ && laneRate == ADI_FPGA9010_9_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x0766; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7870; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0200; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0004; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_9P2_GHZ && laneRate == ADI_FPGA9010_9P2_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x0766; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7870; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0200; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0004; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_11_GHZ && laneRate == ADI_FPGA9010_11_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x0766; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7860; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0100; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0400; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0004; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_12P28_GHZ && laneRate == ADI_FPGA9010_6P14_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x0756; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7870; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0200; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0000; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_12P28_GHZ && laneRate == ADI_FPGA9010_12P28_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x0766; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7860; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0200; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0400; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0004; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_14_GHZ && laneRate == ADI_FPGA9010_7_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF800; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x0756; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7870; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0000; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_14_GHZ && laneRate == ADI_FPGA9010_14_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF800; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x0766; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7860; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0400; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0004; + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Unsupported FPGA clock configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else if (device->devStateInfo.designId == ADI_FPGA9010_JESD204C_DEVICEID) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].encoder8b10bEnable = 0; + + if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_10_GHZ && laneRate == ADI_FPGA9010_2P53_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x07C6; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7870; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0100; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxProgdivCfg = 0xC388; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0000; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_10_GHZ && laneRate == ADI_FPGA9010_5_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x07D6; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7870; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0100; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxProgdivCfg = 0xC288; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0000; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_10_GHZ && laneRate == ADI_FPGA9010_10_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x07E6; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7870; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0100; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0400; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxProgdivCfg = 0xC208; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0004; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_12P16_GHZ && laneRate == ADI_FPGA9010_3_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x07C6; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7870; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0100; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxProgdivCfg = 0xC388; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0000; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_12P16_GHZ && laneRate == ADI_FPGA9010_6P08_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x07D6; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7870; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0100; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxProgdivCfg = 0xC288; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0000; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_12P16_GHZ && laneRate == ADI_FPGA9010_12P16_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x07E6; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7860; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0100; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0400; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxProgdivCfg = 0xC208; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0004; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_16_GHZ && laneRate == ADI_FPGA9010_2P02_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF800; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x07B6; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7870; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxProgdivCfg = 0xC388; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0000; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_16_GHZ && laneRate == ADI_FPGA9010_4P05_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF800; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x07C6; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7870; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxProgdivCfg = 0xC388; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0000; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_16_GHZ && laneRate == ADI_FPGA9010_8_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF800; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x07D6; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7870; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxProgdivCfg = 0xC288; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0004; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_16_GHZ && laneRate == ADI_FPGA9010_16_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0x3800; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x07E6; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7860; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0400; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxProgdivCfg = 0xC208; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0004; + } + else if (fpgaInit->clocks.qpll.qpllVco_kHz == ADI_FPGA9010_8_GHZ && laneRate == ADI_FPGA9010_8_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].pmaRsv1 = 0xF800; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxCdrCfg2 = 0x07D6; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeGcCfg1 = 0x7870; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg4 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPiCfg5 = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxEnHiLr = 0x0000; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxProgdivCfg = 0xC288; + fpgaInit->datapath.deserializerCfg[fpgaLane].rxWidemodeCdr = 0x0004; + } + else + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "Unsupported FPGA clock configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t static fpga9010_FindValidUnusedClk(uint32_t defrm0CoreClk_kHz, uint32_t defrm1CoreClk_kHz, uint32_t defrm2CoreClk_kHz, uint32_t frm0CoreClk_kHz, uint32_t frm1CoreClk_kHz) +{ + if (defrm0CoreClk_kHz != 0) + { + return defrm0CoreClk_kHz; + } + else if (defrm1CoreClk_kHz != 0) + { + return defrm1CoreClk_kHz; + } + else if (defrm2CoreClk_kHz != 0) + { + return defrm2CoreClk_kHz; + } + else if (frm0CoreClk_kHz != 0) + { + return frm0CoreClk_kHz; + } + else if (frm1CoreClk_kHz != 0) + { + return frm1CoreClk_kHz; + } + else + { + return 0; + } +} + +int32_t adi_fpga9010_InitConfig(adi_fpga9010_Device_t *device, adi_fpga9010_SetupFpgaCfg_t *fpgaCfg, adi_fpga9010_Init_t *fpgaInit) +{ + int32_t i = 0; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t fastestLaneRate_kHz = 0; + uint32_t refClk_kHz = fpgaCfg->deviceClk_kHz; + + /* Lane rate declarations */ + uint32_t defrm0LaneRate_kHz = 0; + uint32_t defrm1LaneRate_kHz = 0; + uint32_t defrm2LaneRate_kHz = 0; + uint32_t frm0LaneRate_kHz = 0; + uint32_t frm1LaneRate_kHz = 0; + + /* Framer/Deframer clock rate declarations */ + uint32_t defrm0CoreClk_kHz = 0; // lanerate /40 for JESD204B, lanerate/66 for JESD204C + uint32_t defrm1CoreClk_kHz = 0; + uint32_t defrm2CoreClk_kHz = 0; + uint32_t frm0CoreClk_kHz = 0;// lanerate /40 for JESD204B, lanerate/66 for JESD204C + uint32_t frm1CoreClk_kHz = 0; + uint32_t mmcmUnusedClk_kHz = 0; + + uint8_t jesd204F = 0; + uint8_t adrv9010LanesEnabled = 0; + uint8_t dVal = 0; + + uint8_t defrm0L = 0; + uint8_t defrm1L = 0; + uint8_t defrm2L = 0; + uint8_t frm0L = 0; + uint8_t frm1L = 0; + + uint8_t adrv9010SerLaneIndex = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_NULL_DEVICE_PTR_RETURN(fpgaCfg); + ADI_NULL_PTR_RETURN(&device->common, fpgaInit); + +#if ADI_FPGA9010_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + /* Check that the parameters that could cause divide-by-0 faults */ + if (device->devStateInfo.linkLayerDataWidth == 0 || device->devStateInfo.encodingLowValue == 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, NULL, "FPGA device has not been initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (fpgaCfg->deviceClk_kHz == 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, fpgaCfg->deviceClk_kHz, "deviceClk_kHz should not be 0. Verify init structures are set"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + refClk_kHz = fpgaCfg->deviceClk_kHz; + + /* Calculate L */ + for ( i = 0; i < 8; i++) + { + defrm0L = (defrm0L + ((fpgaCfg->deframerlink0.lanesEnabled >> i) & 1)); + defrm1L = (defrm1L + ((fpgaCfg->deframerlink1.lanesEnabled >> i) & 1)); + defrm2L = (defrm2L + ((fpgaCfg->deframerlink2.lanesEnabled >> i) & 1)); + frm0L = (frm0L + ((fpgaCfg->framerlink0.lanesEnabled >> i) & 1)); + frm1L = (frm1L + ((fpgaCfg->framerlink1.lanesEnabled >> i) & 1)); + } + + /* init the mmcm settings */ + /* calculate the framer/deframer lane rates in order to determine + a Qpll rate which will support all of them.*/ + if (defrm0L != 0) + { + defrm0LaneRate_kHz = (fpgaCfg->deframerlink0.iqRate_kHz + * fpgaCfg->deframerlink0.jesd204M + * fpgaCfg->deframerlink0.jesd204Np + * device->devStateInfo.encodingHighValue) / (device->devStateInfo.encodingLowValue * defrm0L); + + defrm0CoreClk_kHz = defrm0LaneRate_kHz / device->devStateInfo.linkLayerDataWidth; + } + + if (defrm1L != 0) + { + + defrm1LaneRate_kHz = (fpgaCfg->deframerlink1.iqRate_kHz + * fpgaCfg->deframerlink1.jesd204M + * fpgaCfg->deframerlink1.jesd204Np + * device->devStateInfo.encodingHighValue) / (device->devStateInfo.encodingLowValue * defrm1L); + defrm1CoreClk_kHz = defrm1LaneRate_kHz / device->devStateInfo.linkLayerDataWidth; + } + + if (defrm2L != 0) + { + defrm2LaneRate_kHz = fpgaCfg->deframerlink2.iqRate_kHz + * fpgaCfg->deframerlink2.jesd204M + * fpgaCfg->deframerlink2.jesd204Np + * device->devStateInfo.encodingHighValue / (device->devStateInfo.encodingLowValue * defrm2L); + defrm2CoreClk_kHz = defrm2LaneRate_kHz / device->devStateInfo.linkLayerDataWidth; + } + + if (frm0L != 0) + { + frm0LaneRate_kHz = (fpgaCfg->framerlink0.iqRate_kHz + * fpgaCfg->framerlink0.jesd204M + * fpgaCfg->framerlink0.jesd204Np + * device->devStateInfo.encodingHighValue) / (device->devStateInfo.encodingLowValue * frm0L); + frm0CoreClk_kHz = frm0LaneRate_kHz / device->devStateInfo.linkLayerDataWidth; + } + + if (frm1L != 0) + { + frm1LaneRate_kHz = fpgaCfg->framerlink1.iqRate_kHz + * fpgaCfg->framerlink1.jesd204M + * fpgaCfg->framerlink1.jesd204Np + * device->devStateInfo.encodingHighValue / (device->devStateInfo.encodingLowValue * frm1L); + frm1CoreClk_kHz = frm1CoreClk_kHz / device->devStateInfo.linkLayerDataWidth; + } + + /* init the qpll settings */ + fastestLaneRate_kHz = defrm0LaneRate_kHz > defrm1LaneRate_kHz ? defrm0LaneRate_kHz : defrm1LaneRate_kHz; + fastestLaneRate_kHz = defrm2LaneRate_kHz > fastestLaneRate_kHz ? defrm2LaneRate_kHz : fastestLaneRate_kHz; + fastestLaneRate_kHz = frm0LaneRate_kHz > fastestLaneRate_kHz ? frm0LaneRate_kHz : fastestLaneRate_kHz; + fastestLaneRate_kHz = frm1LaneRate_kHz > fastestLaneRate_kHz ? frm1LaneRate_kHz : fastestLaneRate_kHz; + if (fastestLaneRate_kHz == 0) + { + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, ADI_COMMON_ACT_ERR_CHECK_PARAM, serializerCfg->txPllClkSel, "All lane rates are 0 Gbps (disabled)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adi_fpga9010_CalculateQpllSettings(device, refClk_kHz, fastestLaneRate_kHz, &fpgaInit->clocks.qpll); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + fpgaInit->clocks.qpll.quadSelect = (ADI_FPGA9010_QPLL_QUAD0 | ADI_FPGA9010_QPLL_QUAD1); /* Default to setting */ + fpgaInit->clocks.qpll.refClkSelect[0] = ADI_FPGA9010_QPLL_GTNORTHREFCLK0; + fpgaInit->clocks.qpll.refClkSelect[1] = ADI_FPGA9010_QPLL_GTREFCLK0; + + mmcmUnusedClk_kHz = fpga9010_FindValidUnusedClk(defrm0CoreClk_kHz, defrm1CoreClk_kHz, defrm2CoreClk_kHz, frm0CoreClk_kHz, frm1CoreClk_kHz); + + /* add the required mmsm setting to support the deserializers and deframers. */ + fpgaInit->clocks.coreMmcm.outputClkFreq_kHz[0] = (defrm0CoreClk_kHz == 0) ? mmcmUnusedClk_kHz : defrm0CoreClk_kHz; + fpgaInit->clocks.coreMmcm.outputClkFreq_kHz[1] = (defrm1CoreClk_kHz == 0) ? mmcmUnusedClk_kHz : defrm1CoreClk_kHz; + fpgaInit->clocks.coreMmcm.outputClkFreq_kHz[2] = (defrm2CoreClk_kHz == 0) ? mmcmUnusedClk_kHz : defrm2CoreClk_kHz; + + /* TODO: FPGA was updated to use frm0 clock for lanes 1-4, and frm1 clk for 4-7. If framer 0 uses all 8 lanes, both clocks must be set */ + fpgaInit->clocks.coreMmcm.outputClkFreq_kHz[3] = (frm0CoreClk_kHz == 0) ? ((frm1CoreClk_kHz == 0) ? mmcmUnusedClk_kHz : frm1CoreClk_kHz) : frm0CoreClk_kHz; + fpgaInit->clocks.coreMmcm.outputClkFreq_kHz[4] = (frm1CoreClk_kHz == 0) ? ((frm0CoreClk_kHz == 0) ? mmcmUnusedClk_kHz : frm0CoreClk_kHz) : frm1CoreClk_kHz; + fpgaInit->clocks.coreMmcm.outputClkFreq_kHz[5] = fastestLaneRate_kHz / device->devStateInfo.linkLayerDataWidth; /* TDD FSM frequency */ + device->devStateInfo.tddStateMachineClk_kHz = fpgaInit->clocks.coreMmcm.outputClkFreq_kHz[5]; + fpgaInit->clocks.coreMmcm.outputClkFreq_kHz[6] = mmcmUnusedClk_kHz; /* unused */ + + recoveryAction = adi_fpga9010_CalculateMmcmSettings(device, refClk_kHz, &fpgaInit->clocks.coreMmcm); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* init the serializer/deserializer settings */ + /* Power down all deserializer lanes in FPGA */ + for (i = 0; i < 8; i++) + { + fpgaInit->datapath.deserializerCfg[i].powerDown = 3; + fpgaInit->datapath.deserializerCfg[i].rate = 1; + } + + recoveryAction = adi_fpga9010_CalculateQpllDivisor(device, fpgaInit->clocks.qpll.qpllVco_kHz, defrm0LaneRate_kHz, &dVal); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9010LanesEnabled = fpgaCfg->deframerlink0.lanesEnabled; + + /* Power up used lanes */ + + uint8_t adrv9010Framer0Lanexbar[8] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; /* Each number specifies the physical ADRV9010 serializer lane */ + /*Add flexibility to handle with different lane mappings of the tranceiver LaneXbar*/ + uint8_t adrv9010Framer0LaneFramer[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + for (adrv9010SerLaneIndex = 0; adrv9010SerLaneIndex < 8; adrv9010SerLaneIndex++) + { + if ((adrv9010LanesEnabled >> adrv9010SerLaneIndex) & 0x1) + { + adrv9010Framer0Lanexbar[adrv9010SerLaneIndex] = adrv9010SerLaneIndex; + switch(adrv9010SerLaneIndex) + { + case 0: + adrv9010Framer0LaneFramer[0] = fpgaCfg->deframerlink0.serializerLaneCrossbar.lane0FramerOutSel; + break; + case 1: + adrv9010Framer0LaneFramer[1] = fpgaCfg->deframerlink0.serializerLaneCrossbar.lane1FramerOutSel; + break; + case 2: + adrv9010Framer0LaneFramer[2] = fpgaCfg->deframerlink0.serializerLaneCrossbar.lane2FramerOutSel; + break; + case 3: + adrv9010Framer0LaneFramer[3] = fpgaCfg->deframerlink0.serializerLaneCrossbar.lane3FramerOutSel; + break; + case 4: + adrv9010Framer0LaneFramer[4] = fpgaCfg->deframerlink0.serializerLaneCrossbar.lane4FramerOutSel; + break; + case 5: + adrv9010Framer0LaneFramer[5] = fpgaCfg->deframerlink0.serializerLaneCrossbar.lane5FramerOutSel; + break; + case 6: + adrv9010Framer0LaneFramer[6] = fpgaCfg->deframerlink0.serializerLaneCrossbar.lane6FramerOutSel; + break; + case 7: + adrv9010Framer0LaneFramer[7] = fpgaCfg->deframerlink0.serializerLaneCrossbar.lane7FramerOutSel; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Unsupported Serdes lane selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + uint8_t usedLaneIndex = 0; + uint8_t tempValue = 0; + for (adrv9010SerLaneIndex = 0; adrv9010SerLaneIndex < 8; adrv9010SerLaneIndex++) + { + if ((adrv9010LanesEnabled >> adrv9010SerLaneIndex) & 0x1) + { + if (adrv9010Framer0LaneFramer[adrv9010SerLaneIndex] != usedLaneIndex) + { + for (i = adrv9010SerLaneIndex; i< 8; i++) + { + if (adrv9010Framer0LaneFramer[i] == usedLaneIndex) + { + tempValue = adrv9010Framer0Lanexbar[i]; + adrv9010Framer0Lanexbar[i] = adrv9010Framer0Lanexbar[adrv9010SerLaneIndex] ; + adrv9010Framer0Lanexbar[adrv9010SerLaneIndex] = tempValue; + break; + } + } + } + usedLaneIndex++; + } + } + uint8_t defInputIndex = 0; + for (adrv9010SerLaneIndex = 0; adrv9010SerLaneIndex < 8; adrv9010SerLaneIndex++) + { + if ((adrv9010LanesEnabled >> adrv9010SerLaneIndex) & 0x1) + { + recoveryAction = fpga9010_DeserializerCfg(device, fpgaInit, adrv9010Framer0Lanexbar[adrv9010SerLaneIndex], defInputIndex++, dVal, refClk_kHz, 0); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + } + + recoveryAction = adi_fpga9010_CalculateQpllDivisor(device, fpgaInit->clocks.qpll.qpllVco_kHz, defrm1LaneRate_kHz, &dVal); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9010LanesEnabled = fpgaCfg->deframerlink1.lanesEnabled; + /* Don't reset j from loop above, continue using its value for the next valid lane. */ + uint8_t adrv9010Framer1Lanexbar[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; /*Each number specifies the physical ADRV9010 serializer lane */ + /*Add flexibility to handle with different lane mappings of the tranceiver LaneXbar*/ + uint8_t adrv9010Framer1LaneFramer[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + for (adrv9010SerLaneIndex = 0; adrv9010SerLaneIndex < 8; adrv9010SerLaneIndex++) + { + if ((adrv9010LanesEnabled >> adrv9010SerLaneIndex) & 0x1) + { + adrv9010Framer1Lanexbar[adrv9010SerLaneIndex] = adrv9010SerLaneIndex; + switch(adrv9010SerLaneIndex) + { + case 0: + adrv9010Framer1LaneFramer[0] = fpgaCfg->deframerlink1.serializerLaneCrossbar.lane0FramerOutSel; + break; + case 1: + adrv9010Framer1LaneFramer[1] = fpgaCfg->deframerlink1.serializerLaneCrossbar.lane1FramerOutSel; + break; + case 2: + adrv9010Framer1LaneFramer[2] = fpgaCfg->deframerlink1.serializerLaneCrossbar.lane2FramerOutSel; + break; + case 3: + adrv9010Framer1LaneFramer[3] = fpgaCfg->deframerlink1.serializerLaneCrossbar.lane3FramerOutSel; + break; + case 4: + adrv9010Framer1LaneFramer[4] = fpgaCfg->deframerlink1.serializerLaneCrossbar.lane4FramerOutSel; + break; + case 5: + adrv9010Framer1LaneFramer[5] = fpgaCfg->deframerlink1.serializerLaneCrossbar.lane5FramerOutSel; + break; + case 6: + adrv9010Framer1LaneFramer[6] = fpgaCfg->deframerlink1.serializerLaneCrossbar.lane6FramerOutSel; + break; + case 7: + adrv9010Framer1LaneFramer[7] = fpgaCfg->deframerlink1.serializerLaneCrossbar.lane7FramerOutSel; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Unsupported Serdes lane selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + usedLaneIndex = 0; + tempValue = 0; + for (adrv9010SerLaneIndex = 0; adrv9010SerLaneIndex < 8; adrv9010SerLaneIndex++) + { + if ((adrv9010LanesEnabled >> adrv9010SerLaneIndex) & 0x1) + { + if (adrv9010Framer1LaneFramer[adrv9010SerLaneIndex] != usedLaneIndex) + { + for (i = adrv9010SerLaneIndex; i< 8; i++) + { + if (adrv9010Framer1LaneFramer[i] == usedLaneIndex) + { + tempValue = adrv9010Framer1Lanexbar[i]; + adrv9010Framer1Lanexbar[i] = adrv9010Framer1Lanexbar[adrv9010SerLaneIndex] ; + adrv9010Framer1Lanexbar[adrv9010SerLaneIndex] = tempValue; + } + } + } + usedLaneIndex++; + } + } + defInputIndex = 0; + for (adrv9010SerLaneIndex = 0; adrv9010SerLaneIndex < 8; adrv9010SerLaneIndex++) + { + /* for each deserializer used by deframer 1 setup its parameters */ + if ((adrv9010LanesEnabled >> adrv9010SerLaneIndex) & 0x1) + { + recoveryAction = fpga9010_DeserializerCfg(device, fpgaInit, adrv9010Framer1Lanexbar[adrv9010SerLaneIndex], defInputIndex++, dVal, refClk_kHz, 1); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + recoveryAction = adi_fpga9010_CalculateQpllDivisor(device, fpgaInit->clocks.qpll.qpllVco_kHz, defrm2LaneRate_kHz, &dVal); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9010LanesEnabled = fpgaCfg->deframerlink2.lanesEnabled; + uint8_t adrv9010Framer2Lanexbar[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; /* Each number specifies the physical ADRV9010 serializer lane */ + /*Add flexibility to handle with different lane mappings of the tranceiver LaneXbar*/ + uint8_t adrv9010Framer2LaneFramer[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + + for (adrv9010SerLaneIndex = 0; adrv9010SerLaneIndex < 8; adrv9010SerLaneIndex++) + { + if ((adrv9010LanesEnabled >> adrv9010SerLaneIndex) & 0x1) + { + adrv9010Framer2Lanexbar[adrv9010SerLaneIndex] = adrv9010SerLaneIndex; + switch(adrv9010SerLaneIndex) + { + case 0: + adrv9010Framer2LaneFramer[0] = fpgaCfg->deframerlink2.serializerLaneCrossbar.lane0FramerOutSel; + break; + case 1: + adrv9010Framer2LaneFramer[1] = fpgaCfg->deframerlink2.serializerLaneCrossbar.lane1FramerOutSel; + break; + case 2: + adrv9010Framer2LaneFramer[2] = fpgaCfg->deframerlink2.serializerLaneCrossbar.lane2FramerOutSel; + break; + case 3: + adrv9010Framer2LaneFramer[3] = fpgaCfg->deframerlink2.serializerLaneCrossbar.lane3FramerOutSel; + break; + case 4: + adrv9010Framer2LaneFramer[4] = fpgaCfg->deframerlink2.serializerLaneCrossbar.lane4FramerOutSel; + break; + case 5: + adrv9010Framer2LaneFramer[5] = fpgaCfg->deframerlink2.serializerLaneCrossbar.lane5FramerOutSel; + break; + case 6: + adrv9010Framer2LaneFramer[6] = fpgaCfg->deframerlink2.serializerLaneCrossbar.lane6FramerOutSel; + break; + case 7: + adrv9010Framer2LaneFramer[7] = fpgaCfg->deframerlink2.serializerLaneCrossbar.lane7FramerOutSel; + break; + default: + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9010_ERR_API_FAIL, ADI_COMMON_ACT_ERR_RESET_FULL, NULL, "Unsupported Serdes lane selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + usedLaneIndex = 0; + tempValue = 0; + for (adrv9010SerLaneIndex = 0; adrv9010SerLaneIndex < 8; adrv9010SerLaneIndex++) + { + if ((adrv9010LanesEnabled >> adrv9010SerLaneIndex) & 0x1) + { + if (adrv9010Framer2LaneFramer[adrv9010SerLaneIndex] != usedLaneIndex) + { + for (i = adrv9010SerLaneIndex; i< 8; i++) + { + if (adrv9010Framer2LaneFramer[i] == usedLaneIndex) + { + tempValue = adrv9010Framer2Lanexbar[i]; + adrv9010Framer2Lanexbar[i] = adrv9010Framer2Lanexbar[adrv9010SerLaneIndex] ; + adrv9010Framer2Lanexbar[adrv9010SerLaneIndex] = tempValue; + } + } + } + usedLaneIndex++; + } + } + defInputIndex = 0; + for (adrv9010SerLaneIndex = 0; adrv9010SerLaneIndex < 8; adrv9010SerLaneIndex++) + { + /* for each deserializer used by deframer 4 setup its parameters */ + if ((adrv9010LanesEnabled >> adrv9010SerLaneIndex) & 0x1) + { + recoveryAction = fpga9010_DeserializerCfg(device, fpgaInit, adrv9010Framer2Lanexbar[adrv9010SerLaneIndex], defInputIndex++, dVal, refClk_kHz, 2); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Power down all FPGA serializer lanes */ + for (i = 0; i < 8; i++) + { + fpgaInit->datapath.serializerCfg[i].powerDown = 3; + fpgaInit->datapath.serializerCfg[i].rate = 1; + + /* Initialize Lane Xbar to 0x1F. 0x1F is the max the lane_x_select bitfield can take before error */ + fpgaInit->datapath.framerCfg[0].laneXbar[i] = 0x1F; + fpgaInit->datapath.framerCfg[1].laneXbar[i] = 0x1F; + } + + recoveryAction = adi_fpga9010_CalculateQpllDivisor(device, fpgaInit->clocks.qpll.qpllVco_kHz, frm0LaneRate_kHz, &dVal); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9010LanesEnabled = fpgaCfg->framerlink0.lanesEnabled; + uint8_t frmOutputIndex = 0; + for (i = 0; i < 8; i++) + { + /* for each serializer used by framer 0 setup its parameters */ + if ((adrv9010LanesEnabled >> i) & 0x1) + { + recoveryAction = fpga9010_SerializerCfg(device, fpgaInit, i, frmOutputIndex++, dVal, refClk_kHz, 0); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + recoveryAction = adi_fpga9010_CalculateQpllDivisor(device, fpgaInit->clocks.qpll.qpllVco_kHz, frm1LaneRate_kHz, &dVal); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9010LanesEnabled = fpgaCfg->framerlink1.lanesEnabled; + frmOutputIndex = 0; + for (i = 0; i < 8; i++) + { + /* for each serializer used by framer 2 setup its parameters */ + if ((adrv9010LanesEnabled >> i) & 0x1) + { + recoveryAction = fpga9010_SerializerCfg(device, fpgaInit, i, frmOutputIndex++, dVal, refClk_kHz, 1); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* init the framer/deframer settings */ + + /* set deframer 0 settings */ + if (defrm0L > 0) + { + jesd204F = (fpgaCfg->deframerlink0.jesd204Np * fpgaCfg->deframerlink0.jesd204M * fpgaCfg->deframerlink0.jesd204S) / (8 * defrm0L); + } + + /* Common */ + fpgaInit->datapath.deframerCfg[0].sysRefDelay = 0; + fpgaInit->datapath.deframerCfg[0].subclassV = 1; + fpgaInit->datapath.deframerCfg[0].lanesInUse = (defrm0L == 8) ? 0xFF : + (defrm0L == 4) ? 0x0F : + (defrm0L == 2) ? 0x03 : + (defrm0L == 1) ? 0x01 : 0; + + /* JESD204B */ + fpgaInit->datapath.deframerCfg[0].scramblingEn = fpgaCfg->deframerlink0.scramble; + fpgaInit->datapath.deframerCfg[0].cfgF = (defrm0L > 0) ? jesd204F : 0; + fpgaInit->datapath.deframerCfg[0].cfgK = (uint8_t)fpgaCfg->deframerlink0.jesd204K; + fpgaInit->datapath.deframerCfg[0].rxBufferDly = 0; + fpgaInit->datapath.deframerCfg[0].errReportingDisable = 0; + fpgaInit->datapath.deframerCfg[0].ilaSupportEn = 1; + fpgaInit->datapath.deframerCfg[0].sysRefAlways = 0; + fpgaInit->datapath.deframerCfg[0].sysRefRequiredOnResync = 0; + + /* JESD204C */ + fpgaInit->datapath.deframerCfg[0].enableCmdInterface = 0; + fpgaInit->datapath.deframerCfg[0].enableDataInterface = 1; + fpgaInit->datapath.deframerCfg[0].cfgE = fpgaCfg->deframerlink0.jesd204E; + fpgaInit->datapath.deframerCfg[0].ctrlMetaMode = 0; + fpgaInit->datapath.deframerCfg[0].ctrlRxBufAdv = 0; + fpgaInit->datapath.deframerCfg[0].ctrlRxMBlockTh = 1; + fpgaInit->datapath.deframerCfg[0].ctrlIrq = 0x3FF; /* Enable all interrupts */ + + /* set deframer 0 datamover settings */ + fpgaInit->datapath.rxDmaCfg[0].enableEnhancedMode = 0; + fpgaInit->datapath.rxDmaCfg[0].enableSg = 0; + fpgaInit->datapath.rxDmaCfg[0].simpleStartAddr = 0 * RX_DMA_SIZE; + fpgaInit->datapath.rxDmaCfg[0].length = RX_DMA_SIZE; + fpgaInit->datapath.rxDmaCfg[0].validDataWidthStream = (defrm0L * device->devStateInfo.dmaDataWidth / 32) - 1; + fpgaInit->datapath.rxDmaCfg[0].sgFirstDescriptor = 0; + fpgaInit->datapath.rxDmaCfg[0].sgLastDescriptor = 0; + fpgaInit->datapath.rxDmaCfg[0].runStop = 0; + + /* set deframer 1 settings */ + if (defrm1L > 0) + { + jesd204F = (fpgaCfg->deframerlink1.jesd204Np * fpgaCfg->deframerlink1.jesd204M * fpgaCfg->deframerlink1.jesd204S) / (8 * defrm1L); + } + + /* Common */ + fpgaInit->datapath.deframerCfg[1].sysRefDelay = 0; + fpgaInit->datapath.deframerCfg[1].subclassV = 1; + fpgaInit->datapath.deframerCfg[1].lanesInUse = (defrm1L == 8) ? 0xFF : + (defrm1L == 4) ? 0x0F : + (defrm1L == 2) ? 0x03 : + (defrm1L == 1) ? 0x01 : 0; + + /* JESD204B */ + fpgaInit->datapath.deframerCfg[1].scramblingEn = fpgaCfg->deframerlink1.scramble; + fpgaInit->datapath.deframerCfg[1].cfgF = (defrm1L > 0) ? jesd204F : 0; + fpgaInit->datapath.deframerCfg[1].cfgK = (uint8_t)fpgaCfg->deframerlink1.jesd204K ; + fpgaInit->datapath.deframerCfg[1].rxBufferDly = 0; + fpgaInit->datapath.deframerCfg[1].errReportingDisable = 0; + fpgaInit->datapath.deframerCfg[1].ilaSupportEn = 1; + fpgaInit->datapath.deframerCfg[1].sysRefAlways = 0; + fpgaInit->datapath.deframerCfg[1].sysRefRequiredOnResync = 0; + + /* JESD204C */ + fpgaInit->datapath.deframerCfg[1].enableCmdInterface = 0; + fpgaInit->datapath.deframerCfg[1].enableDataInterface = 1; + fpgaInit->datapath.deframerCfg[1].cfgE = fpgaCfg->deframerlink1.jesd204E; + fpgaInit->datapath.deframerCfg[1].ctrlMetaMode = 0; + fpgaInit->datapath.deframerCfg[1].ctrlRxBufAdv = 0; + fpgaInit->datapath.deframerCfg[1].ctrlRxMBlockTh = 1; + fpgaInit->datapath.deframerCfg[1].ctrlIrq = 0x3FF; /* Enable all interrupts */ + + /* set deframer 1 datamover settings */ + fpgaInit->datapath.rxDmaCfg[1].enableEnhancedMode = 0; + fpgaInit->datapath.rxDmaCfg[1].enableSg = 0; + fpgaInit->datapath.rxDmaCfg[1].simpleStartAddr = 1 * RX_DMA_SIZE; + fpgaInit->datapath.rxDmaCfg[1].length = RX_DMA_SIZE; + fpgaInit->datapath.rxDmaCfg[1].validDataWidthStream = (defrm1L * device->devStateInfo.dmaDataWidth / 32) - 1; + fpgaInit->datapath.rxDmaCfg[1].sgFirstDescriptor = 0; + fpgaInit->datapath.rxDmaCfg[1].sgLastDescriptor = 0; + fpgaInit->datapath.rxDmaCfg[1].runStop = 0; + + /* set deframer 2 settings */ + if (defrm2L > 0) + { + jesd204F = (fpgaCfg->deframerlink2.jesd204Np * fpgaCfg->deframerlink2.jesd204M * fpgaCfg->deframerlink2.jesd204S) / (8 * defrm2L); + } + + /* Common */ + fpgaInit->datapath.deframerCfg[2].sysRefDelay = 0; + fpgaInit->datapath.deframerCfg[2].subclassV = 1; + fpgaInit->datapath.deframerCfg[2].lanesInUse = (defrm2L == 8) ? 0xFF : + (defrm2L == 4) ? 0x0F : + (defrm2L == 2) ? 0x03 : + (defrm2L == 1) ? 0x01 : 0; + + /* JESD204B */ + fpgaInit->datapath.deframerCfg[2].scramblingEn = fpgaCfg->deframerlink2.scramble; + fpgaInit->datapath.deframerCfg[2].cfgF = (defrm2L > 0) ? jesd204F : 0; + fpgaInit->datapath.deframerCfg[2].cfgK = (uint8_t)fpgaCfg->deframerlink2.jesd204K; + fpgaInit->datapath.deframerCfg[2].rxBufferDly = 0; + fpgaInit->datapath.deframerCfg[2].errReportingDisable = 0; + fpgaInit->datapath.deframerCfg[2].ilaSupportEn = 1; + fpgaInit->datapath.deframerCfg[2].sysRefAlways = 0; + fpgaInit->datapath.deframerCfg[2].sysRefRequiredOnResync = 0; + + /* JESD204C */ + fpgaInit->datapath.deframerCfg[2].enableCmdInterface = 0; + fpgaInit->datapath.deframerCfg[2].enableDataInterface = 1; + fpgaInit->datapath.deframerCfg[2].cfgE = fpgaCfg->deframerlink2.jesd204E; + fpgaInit->datapath.deframerCfg[2].ctrlMetaMode = 0; + fpgaInit->datapath.deframerCfg[2].ctrlRxBufAdv = 0; + fpgaInit->datapath.deframerCfg[2].ctrlRxMBlockTh = 1; + fpgaInit->datapath.deframerCfg[2].ctrlIrq = 0x3FF; /* Enable all interrupts */ + + /* set deframer 2 datamover settings */ + fpgaInit->datapath.rxDmaCfg[2].enableEnhancedMode = 0; + fpgaInit->datapath.rxDmaCfg[2].enableSg = 0; + fpgaInit->datapath.rxDmaCfg[2].simpleStartAddr = 2 * RX_DMA_SIZE; + fpgaInit->datapath.rxDmaCfg[2].length = RX_DMA_SIZE; + fpgaInit->datapath.rxDmaCfg[2].validDataWidthStream = (defrm2L * device->devStateInfo.dmaDataWidth / 32) - 1; + fpgaInit->datapath.rxDmaCfg[2].sgFirstDescriptor = 0; + fpgaInit->datapath.rxDmaCfg[2].sgLastDescriptor = 0; + fpgaInit->datapath.rxDmaCfg[2].runStop = 0; + + + /* set framer 0 settings */ + if (frm0L > 0) + { + jesd204F = (fpgaCfg->framerlink0.jesd204Np * fpgaCfg->framerlink0.jesd204M * fpgaCfg->framerlink0.jesd204S) / (8 * frm0L); + } + + /* Common */ + fpgaInit->datapath.framerCfg[0].deviceId = fpgaCfg->framerlink0.deviceId; + fpgaInit->datapath.framerCfg[0].bankId = 1; + fpgaInit->datapath.framerCfg[0].subclassV = 1; + fpgaInit->datapath.framerCfg[0].sysRefDelay = 0; + fpgaInit->datapath.framerCfg[0].lanesInUse = (frm0L == 8) ? 0xFF : + (frm0L == 4) ? 0x0F : + (frm0L == 2) ? 0x03 : + (frm0L == 1) ? 0x01 : 0; + + /* JESD204B */ + fpgaInit->datapath.framerCfg[0].ilaSupportEn = 1; + fpgaInit->datapath.framerCfg[0].scramblingEn = fpgaCfg->framerlink0.scramble; + fpgaInit->datapath.framerCfg[0].ilaMultiFrames = 4; + fpgaInit->datapath.framerCfg[0].cfgF = (frm0L > 0) ? jesd204F : 0; + fpgaInit->datapath.framerCfg[0].cfgK = (uint8_t)fpgaCfg->framerlink0.jesd204K; + fpgaInit->datapath.framerCfg[0].ilaM = fpgaCfg->framerlink0.jesd204M; + fpgaInit->datapath.framerCfg[0].ilaN = fpgaCfg->framerlink0.jesd204Np; + fpgaInit->datapath.framerCfg[0].ilaCs = 0; + fpgaInit->datapath.framerCfg[0].ilaNp = fpgaCfg->framerlink0.jesd204Np; + fpgaInit->datapath.framerCfg[0].ilaS = fpgaCfg->framerlink0.jesd204S; + fpgaInit->datapath.framerCfg[0].ilaCf = 0; + fpgaInit->datapath.framerCfg[0].sysRefAlways = 0; + fpgaInit->datapath.framerCfg[0].sysRefRequiredOnResync = 0; + + /* JESD204C */ + fpgaInit->datapath.framerCfg[0].enableCmdInterface = 0; + fpgaInit->datapath.framerCfg[0].enableDataInterface = 1; + fpgaInit->datapath.framerCfg[0].cfgE = fpgaCfg->framerlink0.jesd204E; + fpgaInit->datapath.framerCfg[0].ctrlMetaMode = 0; + fpgaInit->datapath.framerCfg[0].ctrlIrq = 0x3FF; /* Enable all interrupts */ + + /* Prevent divide by 0 */ + if (fpgaCfg->framerlink0.jesd204Np == 0) + { + fpgaInit->datapath.framerCfg[0].ilaHd = 0; + } + else + { + fpgaInit->datapath.framerCfg[0].ilaHd = ((((uint16_t)(jesd204F) * 8) % fpgaCfg->framerlink0.jesd204Np) > 0) ? 1 : 0; + } + + /* set deframer 0 datamover */ + fpgaInit->datapath.txDmaCfg[0].enableEnhancedMode = 0; + fpgaInit->datapath.txDmaCfg[0].enableSg = 0; + fpgaInit->datapath.txDmaCfg[0].simpleStartAddr = 0x80000000; /* First link starts on tx RAM boundary*/ + fpgaInit->datapath.txDmaCfg[0].length = TX_DMA_SIZE - 1; /* End the first link just before the next link's memory starts */ + fpgaInit->datapath.txDmaCfg[0].validDataWidthStream = (frm0L * device->devStateInfo.dmaDataWidth / 32) - 1; + ; + fpgaInit->datapath.txDmaCfg[0].sgFirstDescriptor = 0; + fpgaInit->datapath.txDmaCfg[0].sgLastDescriptor = 0; + fpgaInit->datapath.txDmaCfg[0].runStop = 0; + fpgaInit->datapath.txDmaCfg[0].continuous = 1; + + /* set framer 1 settings */ + if (frm1L > 0) + { + jesd204F = (fpgaCfg->framerlink1.jesd204Np * fpgaCfg->framerlink1.jesd204M * fpgaCfg->framerlink1.jesd204S) / (8 * frm1L); + } + + /* Common */ + fpgaInit->datapath.framerCfg[1].deviceId = fpgaCfg->framerlink1.deviceId; + fpgaInit->datapath.framerCfg[1].bankId = 1; + fpgaInit->datapath.framerCfg[1].subclassV = 1; + fpgaInit->datapath.framerCfg[1].sysRefDelay = 0; + fpgaInit->datapath.framerCfg[1].lanesInUse = (frm1L == 8) ? 0xFF : + (frm1L == 4) ? 0x0F : + (frm1L == 2) ? 0x03 : + (frm1L == 1) ? 0x01 : 0; + + /* JESD204B */ + fpgaInit->datapath.framerCfg[1].ilaSupportEn = 1; + fpgaInit->datapath.framerCfg[1].scramblingEn = fpgaCfg->framerlink1.scramble; + fpgaInit->datapath.framerCfg[1].ilaMultiFrames = 4; + fpgaInit->datapath.framerCfg[1].cfgF = (frm1L > 0) ? jesd204F : 0; + fpgaInit->datapath.framerCfg[1].cfgK = (uint8_t)fpgaCfg->framerlink1.jesd204K ; + fpgaInit->datapath.framerCfg[1].ilaM = fpgaCfg->framerlink1.jesd204M; + fpgaInit->datapath.framerCfg[1].ilaN = fpgaCfg->framerlink1.jesd204Np; + fpgaInit->datapath.framerCfg[1].ilaCs = 0; + fpgaInit->datapath.framerCfg[1].ilaNp = fpgaCfg->framerlink1.jesd204Np; + fpgaInit->datapath.framerCfg[1].ilaS = fpgaCfg->framerlink1.jesd204S; + fpgaInit->datapath.framerCfg[1].ilaCf = 0; + fpgaInit->datapath.framerCfg[1].sysRefAlways = 0; + fpgaInit->datapath.framerCfg[1].sysRefRequiredOnResync = 0; + + /* JESD204C */ + fpgaInit->datapath.framerCfg[1].enableCmdInterface = 0; + fpgaInit->datapath.framerCfg[1].enableDataInterface = 1; + fpgaInit->datapath.framerCfg[1].cfgE = fpgaCfg->framerlink1.jesd204E; + fpgaInit->datapath.framerCfg[1].ctrlMetaMode = 0; + fpgaInit->datapath.framerCfg[1].ctrlIrq = 0x3FF; /* Enable all interrupts */ + + /* Prevent divide by 0 */ + if (fpgaCfg->framerlink1.jesd204Np == 0) + { + fpgaInit->datapath.framerCfg[1].ilaHd = 0; + } + else + { + fpgaInit->datapath.framerCfg[1].ilaHd = ((((uint16_t)(jesd204F) * 8) % fpgaCfg->framerlink1.jesd204Np) > 0) ? 1 : 0; + } + + /* set deframer 0 datamover */ + fpgaInit->datapath.txDmaCfg[1].enableEnhancedMode = 0; + fpgaInit->datapath.txDmaCfg[1].enableSg = 0; + fpgaInit->datapath.txDmaCfg[1].simpleStartAddr = 0x80000000 + TX_DMA_SIZE; /* First link starts on tx RAM boundary*/ + fpgaInit->datapath.txDmaCfg[1].length = TX_DMA_SIZE - 1; /* End the first link just before the next link's memory starts */ + fpgaInit->datapath.txDmaCfg[1].validDataWidthStream = (frm1L * device->devStateInfo.dmaDataWidth / 32) - 1; + + fpgaInit->datapath.txDmaCfg[1].sgFirstDescriptor = 0; + fpgaInit->datapath.txDmaCfg[1].sgLastDescriptor = 0; + fpgaInit->datapath.txDmaCfg[1].runStop = 0; + fpgaInit->datapath.txDmaCfg[1].continuous = 1; + + /* tollgates */ + fpgaInit->datapath.rxTollgateCfg.tollGateEdgeOrLvl = 1; + fpgaInit->datapath.rxTollgateCfg.tollGateHiRiseOrLoFall = 1; + fpgaInit->datapath.rxTollgateCfg.tollgateReset = 1; + fpgaInit->datapath.rxTollgateCfg.tollGateTrigSource = ADI_FPGA9010_IMM_TRIG; + + fpgaInit->datapath.txTollgateCfg.tollGateEdgeOrLvl = 1; + fpgaInit->datapath.txTollgateCfg.tollGateHiRiseOrLoFall = 1; + fpgaInit->datapath.txTollgateCfg.tollgateReset = 1; + fpgaInit->datapath.txTollgateCfg.tollGateTrigSource = ADI_FPGA9010_TX_IMM_TRIG; + + /* Setup SYNCB crossbars in FPGA */ + for(i = 0 ; i < (ADI_FPGA9010_NUM_OF_DEFRAMERS + ADI_FPGA9010_NUM_OF_FRAMERS) ; i++) + { + fpgaInit->datapath.syncBSel[i] = i; + } + + return recoveryAction; +} + +int32_t adi_fpga9010_FpgaConfigurationPrint(adi_fpga9010_Device_t *device) +{ + /* Read FPGA regs to verify state */ + uint32_t fpgaReg = 0; + uint32_t fpgaAddr; + uint32_t recoveryAction = 0; + int i, j, l; + + /*Physical layer*/ + fpgaAddr = 0x43400114; /* channel 0 rx control */ + for (i = 0; i < 8; i++) + { + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s\n", "********************************************"); + printf("%s\n", "INFO: FPGA Rx deserializer config per lane"); + printf("%s\n", "********************************************"); + printf("%s%d%s0x%x\n", "Rx channel_", i, "_rx_dfe_lpm_en: ", ((fpgaReg >> 8) & 0x01)); + printf("%s%d%s0x%x\n", "Rx channel_", i, "_rx_rate: ", ((fpgaReg >> 4) & 0x07)); + printf("%s%d%s0x%x\n", "Rx channel_", i, "_rx_8b10b_enable: ", ((fpgaReg >> 3) & 0x01)); + printf("%s%d%s0x%x\n", "Rx channel_", i, "_rx_polarity: ", ((fpgaReg >> 2) & 0x01)); + printf("%s%d%s0x%x\n", "Rx channel_", i, "_rx_powerdown: ", ((fpgaReg >> 0) & 0x03)); + printf("\n"); + fpgaAddr += 0x100; + } + + fpgaAddr = 0x43400118; /* channel 0 tx control */ + for (i = 0; i < 8; i++) + { + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s\n", "********************************************"); + printf("%s\n", "INFO: FPGA Tx serializer config per lane"); + printf("%s\n", "********************************************"); + printf("%s%d%s0x%x\n", "Tx channel_", i, "_tx_diff_control: ", ((fpgaReg >> 24) & 0x0F)); + printf("%s%d%s0x%x\n", "Tx channel_", i, "_tx_precursor: ", ((fpgaReg >> 16) & 0x1F)); + printf("%s%d%s0x%x\n", "Tx channel_", i, "_tx_postcursor: ", ((fpgaReg >> 8) & 0x1F)); + printf("%s%d%s0x%x\n", "Tx channel_", i, "_tx_rate: ", ((fpgaReg >> 4) & 0x07)); + printf("%s%d%s0x%x\n", "Tx channel_", i, "_tx_8b10b_enable: ", ((fpgaReg >> 3) & 0x01)); + printf("%s%d%s0x%x\n", "Tx channel_", i, "_tx_polarity: ", ((fpgaReg >> 2) & 0x01)); + printf("%s%d%s0x%x\n", "Tx channel_", i, "_tx_powerdown: ", ((fpgaReg >> 0) & 0x03)); + printf("\n"); + fpgaAddr += 0x100; + } + + /* Read FPGA CLK frequency detectors */ + printf("%s\n", "********************************************"); + printf("%s\n", "INFO: FPGA Clocks frequency detectors"); + printf("%s\n", "********************************************"); + fpgaAddr = 0x43404010; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", "rx_core_clock_0", i, ": ", fpgaReg); + fpgaAddr += 4; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", "rx_core_clock_1", i, ": ", fpgaReg); + fpgaAddr += 4; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", "rx_core_clock_2", i, ": ", fpgaReg); + fpgaAddr += 4; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", "tx_core_clock_0", i, ": ", fpgaReg); + fpgaAddr += 4; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", "tx_core_clock_1", i, ": ", fpgaReg); + fpgaAddr += 4; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", "tdd_clock", i, ": ", fpgaReg); + fpgaAddr += 4; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", "mmcm_ref_clock", i, ": ", fpgaReg); + fpgaAddr += 4; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", "tx_lane_0_clock", i, ": ", fpgaReg); + fpgaAddr += 4; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", "tx_lane_1_clock", i, ": ", fpgaReg); + + /* Read FPGA deframer 0 lane crossbars */ + printf("%s\n", "********************************************"); + printf("%s\n", "INFO: FPGA Deframer 0 lane crossbars"); + printf("%s\n", "********************************************"); + fpgaAddr = 0x43405004; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", "rx_lane_xbar_link_0::reset: ", fpgaReg); + + fpgaAddr = 0x43405010; + for (i = 0; i < 8; i++) + { + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", "rx_lane_xbar_link_0::lane_", i, "_select: ", (fpgaReg & 0x1F)); + fpgaAddr += 4; + } + + /* Read FPGA deframer 1 lane crossbars */ + printf("%s\n", "********************************************"); + printf("%s\n", "INFO: FPGA Deframer 1 lane crossbars"); + printf("%s\n", "********************************************"); + fpgaAddr = 0x43406004; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", "rx_lane_xbar_link_1::reset: ", fpgaReg); + + fpgaAddr = 0x43406010; + for (i = 0; i < 8; i++) + { + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", "rx_lane_xbar_link_1::lane_", i, "_select: ", (fpgaReg & 0x1F)); + fpgaAddr += 4; + } + + /* Read FPGA framer 0 lane crossbars */ + printf("%s\n", "********************************************"); + printf("%s\n", "INFO: FPGA Framer 0 lane crossbars"); + printf("%s\n", "********************************************"); + fpgaAddr = 0x43407004; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", "tx_lane_xbar_link_0::reset: ", fpgaReg); + + fpgaAddr = 0x43407010; + for (i = 0; i < 8; i++) + { + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", "tx_lane_xbar_link_0::lane_", i, "_select: ", (fpgaReg & 0x1F)); + fpgaAddr += 4; + } + + printf("%s\n", "********************************************"); + printf("%s\n", "INFO: FPGA Framer Config"); + printf("%s\n", "********************************************"); + fpgaAddr = 0x4340A000; + for (i = 0; i < 1; i++) + { + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 4, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::reset_self_clearing: ", fpgaReg & 0x1); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::reset_fixd: ", (fpgaReg >> 1) & 0x1); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::watchdog_timer_disable: ", (fpgaReg >> 16) & 0x1); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 8, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::ila_support_end: ", fpgaReg & 0x1); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0xC, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::scrambling_en: ", fpgaReg & 0x1); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x10, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::sysref_always: ", fpgaReg & 0x1); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::sysref_delay: ", (fpgaReg >> 8) & 0xF); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::sysref_required_on_resync: ", (fpgaReg >> 16) & 0x1); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x14, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::ila_multiframes: ", fpgaReg & 0xFF); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x18, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::test_mode: ", fpgaReg & 0x7); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x1C, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + for (j = 0; j < 8; j++) + { + printf("%s%d%s%d%s%d\n", "jesd204b_framer_", i, "::link_error_status_lane_", j, ": ", ((fpgaReg >> i * 3) & 0x3)); + } + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::rx_buffer_ovfg_alarm: ", (fpgaReg >> 29) & 0x1); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::sysref_lmfc_alarm: ", (fpgaReg >> 30) & 0x1); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::lane_align_alarm: ", (fpgaReg >> 31) & 0x1); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x20, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::cfg_f: ", fpgaReg & 0xFF); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x24, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::cfg_k: ", fpgaReg & 0x1F); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x28, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::lane_in_use: ", fpgaReg & 0xFF); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x2C, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::cfg_subclassv: ", fpgaReg & 0x3); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x30, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::rx_buffer_delay: ", fpgaReg & 0x3FF); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x34, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::link_err_cntrs_en: ", fpgaReg & 0x1); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::dis_err_on_sync: ", (fpgaReg >> 8) & 0x1); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x38, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::sync_status: ", fpgaReg & 0x1); + printf("%s%d%s%d\n", "jesd204b_framer_", i, "::sysref_captured: ", (fpgaReg >> 16) & 0x1); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x3C, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + for (j = 0; j < 8; j++) + { + printf("%s%d%s%d%s%d\n", "jesd204b_framer_", i, "::link_debug_status_lane_", j, ": ", ((fpgaReg >> i * 4) & 0xF)); + } + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x810, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("\t%s%d%s%d\n", "jesd204b_framer_", i, "::ila_m: ", fpgaReg & 0xFF); + printf("\t%s%d%s%d\n", "jesd204b_framer_", i, "::ila_n: ", (fpgaReg >> 8) & 0x1F); + printf("\t%s%d%s%d\n", "jesd204b_framer_", i, "::ila_np: ", (fpgaReg >> 16) & 0x1F); + printf("\t%s%d%s%d\n", "jesd204b_framer_", i, "::ila_cs: ", (fpgaReg >> 24) & 0x3); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x814, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("\t%s%d%s%d\n", "jesd204b_framer_", i, "::ila_scr: ", fpgaReg & 0x1); + printf("\t%s%d%s%d\n", "jesd204b_framer_", i, "::ila_s: ", (fpgaReg >> 8) & 0x1F); + printf("\t%s%d%s%d\n", "jesd204b_framer_", i, "::ila_hd: ", (fpgaReg >> 16) & 0x1); + printf("\t%s%d%s%d\n", "jesd204b_framer_", i, "::ila_cf: ", (fpgaReg >> 24) & 0x1F); + } + + printf("%s\n", "********************************************"); + printf("%s\n", "INFO: FPGA Rx DMAs & Tollgates"); + printf("%s\n", "********************************************"); + fpgaAddr = 0x43101008; + for (i = 0; i < 2; i++) + { + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::run_stop: ", (fpgaReg & 0x1)); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::enable_sg: ", ((fpgaReg >> 2) & 0x1)); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::enable_enhanced_mode: ", ((fpgaReg >> 3) & 0x1)); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::valid_data_width_stream: ", ((fpgaReg >> 8) & 0xF)); + + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 4), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::active: ", (fpgaReg & 0x1)); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::complete: ", ((fpgaReg >> 1) & 0x1)); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::halt_complete: ", ((fpgaReg >> 2) & 0x1)); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::overflow: ", ((fpgaReg >> 3) & 0x1)); + + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 8), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s0x%x\n", "dp_dma_rx_", i, "::simple_start_addr: ", fpgaReg); + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 16), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::length: ", fpgaReg); + + fpgaAddr += 0x1000; + } + fpgaAddr = 0x43103004; + for (i = 0; i < 2; i++) + { + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", "dp_tollgate_rx_", i, "::reset: ", (fpgaReg & 0x1)); + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 4), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s0x%x\n", "dp_tollgate_rx_", i, "::trigger_select: ", fpgaReg); + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 8), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s0x%x\n", "dp_tollgate_rx_", i, "::edge_level: ", fpgaReg); + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 12), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s0x%x\n", "dp_tollgate_rx_", i, "::high_rising_low_falling: ", fpgaReg); + + fpgaAddr += 0x1000; + } + + /* Read FPGA deframer 0 config */ + printf("%s\n", "********************************************"); + printf("%s\n", "INFO: FPGA Deframer Config"); + printf("%s\n", "********************************************"); + fpgaAddr = 0x43408000; + for (i = 0; i < 2; i++) + { + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 4, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::reset_self_clearing: ", fpgaReg & 0x1); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::reset_fixd: ", (fpgaReg >> 1) & 0x1); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::watchdog_timer_disable: ", (fpgaReg >> 16) & 0x1); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 8, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::ila_support_end: ", fpgaReg & 0x1); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0xC, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::scrambling_en: ", fpgaReg & 0x1); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x10, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::sysref_always: ", fpgaReg & 0x1); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::sysref_delay: ", (fpgaReg >> 8) & 0xF); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::sysref_required_on_resync: ", (fpgaReg >> 16) & 0x1); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x14, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::ila_multiframes: ", fpgaReg & 0xFF); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x18, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::test_mode: ", fpgaReg & 0x7); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x1C, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + for (j = 0; j < 8; j++) + { + printf("%s%d%s%d%s%d\n", "jesd204b_deframer_", i, "::link_error_status_lane_", j, ": ", ((fpgaReg >> i * 3) & 0x3)); + } + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::rx_buffer_ovfg_alarm: ", (fpgaReg >> 29) & 0x1); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::sysref_lmfc_alarm: ", (fpgaReg >> 30) & 0x1); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::lane_align_alarm: ", (fpgaReg >> 31) & 0x1); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x20, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::cfg_f: ", fpgaReg & 0xFF); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x24, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::cfg_k: ", fpgaReg & 0x1F); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x28, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::lane_in_use: ", fpgaReg & 0xFF); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x2C, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::cfg_subclassv: ", fpgaReg & 0x3); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x30, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::rx_buffer_delay: ", fpgaReg & 0x3FF); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x34, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::link_err_cntrs_en: ", fpgaReg & 0x1); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::dis_err_on_sync: ", (fpgaReg >> 8) & 0x1); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x38, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::sync_status: ", fpgaReg & 0x1); + printf("%s%d%s%d\n", "jesd204b_deframer_", i, "::sysref_captured: ", (fpgaReg >> 16) & 0x1); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x3C, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + for (j = 0; j < 8; j++) + { + printf("%s%d%s%d%s%d\n", "jesd204b_deframer_", i, "::link_debug_status_lane_", j, ": ", ((fpgaReg >> i * 4) & 0xF)); + } + + /* start lane specific data captured through ila */ + for (l = 0; l < 8; l++) + { + printf("\t%s\n", "********************************************"); + printf("\t%s%d\n", "INFO: ILA info for lane ", l); + printf("\t%s\n", "********************************************"); + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x800 + (0x40 * l), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("\t%s%d%s%d\n", "jesd204b_deframer_", i, "::ila_subclass: ", fpgaReg & 0x7); + printf("\t%s%d%s%d\n", "jesd204b_deframer_", i, "::ila_jesdv: ", (fpgaReg >> 8) & 0x7); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x804 + (0x40 * l), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("\t%s%d%s%d\n", "jesd204b_deframer_", i, "::ila_f: ", fpgaReg & 0xFF); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x808 + (0x40 * l), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("\t%s%d%s%d\n", "jesd204b_deframer_", i, "::ila_k: ", fpgaReg & 0x1F); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x810 + (0x40 * l), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("\t%s%d%s%d\n", "jesd204b_deframer_", i, "::ila_m: ", fpgaReg & 0xFF); + printf("\t%s%d%s%d\n", "jesd204b_deframer_", i, "::ila_n: ", (fpgaReg >> 8) & 0x1F); + printf("\t%s%d%s%d\n", "jesd204b_deframer_", i, "::ila_np: ", (fpgaReg >> 16) & 0x1F); + printf("\t%s%d%s%d\n", "jesd204b_deframer_", i, "::ila_cs: ", (fpgaReg >> 24) & 0x3); + + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr + 0x814 + (0x40 * l), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("\t%s%d%s%d\n", "jesd204b_deframer_", i, "::ila_scr: ", fpgaReg & 0x1); + printf("\t%s%d%s%d\n", "jesd204b_deframer_", i, "::ila_s: ", (fpgaReg >> 8) & 0x1F); + printf("\t%s%d%s%d\n", "jesd204b_deframer_", i, "::ila_hd: ", (fpgaReg >> 16) & 0x1); + printf("\t%s%d%s%d\n", "jesd204b_deframer_", i, "::ila_cf: ", (fpgaReg >> 24) & 0x1F); + } + fpgaAddr += 0x1000; + } + + printf("%s\n", "********************************************"); + printf("%s\n", "INFO: FPGA Tx DMAs & Tollgates"); + printf("%s\n", "********************************************"); + fpgaAddr = 0x43201008; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", "dp_dma_tx_0::run_stop: ", (fpgaReg & 0x1)); + printf("%s%u\n", "dp_dma_tx_0::continuous: ", ((fpgaReg >> 1) & 0x1)); + printf("%s%u\n", "dp_dma_tx_0::enable_sg: ", ((fpgaReg >> 2) & 0x1)); + printf("%s%u\n", "dp_dma_tx_0::enable_enhanced_mode: ", ((fpgaReg >> 3) & 0x1)); + printf("%s%u\n", "dp_dma_tx_0::valid_data_width_stream: ", ((fpgaReg >> 8) & 0xF)); + + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 4), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", "dp_dma_tx_0::active: ", (fpgaReg & 0x1)); + printf("%s%u\n", "dp_dma_tx_0::complete: ", ((fpgaReg >> 1) & 0x1)); + printf("%s%u\n", "dp_dma_tx_0::halt_complete: ", ((fpgaReg >> 2) & 0x1)); + printf("%s%u\n", "dp_dma_tx_0::underflow: ", (fpgaReg & 0x8)); + + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 8), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", "dp_dma_tx_0::simple_start_addr: ", fpgaReg); + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 16), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", "dp_dma_tx_0::length: ", fpgaReg); + + fpgaAddr = 0x43202004; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", "dp_tollgate_tx_0::reset: ", (fpgaReg & 0x1)); + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 4), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", "dp_tollgate_tx_0::trigger_select: ", fpgaReg); + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 8), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", "dp_tollgate_tx_0::edge_level: ", fpgaReg); + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 12), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", "dp_tollgate_tx_0::high_rising_low_falling: ", fpgaReg); + + printf("%s\n", "********************************************"); + printf("%s\n", "INFO: FPGA Tx Capture Control"); + printf("%s\n", "********************************************"); + fpgaAddr = 0x43200008; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", "dp_capture_control_tx::datapath_active: ", (fpgaReg & 0x1)); + printf("%s%u\n", "dp_capture_control_tx::pass_token: ", ((fpgaReg >> 1) & 0x1)); + + printf("%s\n", "********************************************"); + printf("%s\n", "INFO: FPGA Rx Capture Control"); + printf("%s\n", "********************************************"); + fpgaAddr = 0x43100008; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", "dp_capture_control_rx::datapath_active: ", (fpgaReg & 0x1)); + printf("%s%u\n", "dp_capture_control_rx::pass_token: ", ((fpgaReg >> 1) & 0x1)); + + return recoveryAction; +} + +int32_t adi_fpga9010_FpgaDatapathCfgPrint(adi_fpga9010_Device_t *device) +{ + /* Read FPGA regs to verify state */ + uint32_t fpgaReg = 0; + uint32_t fpgaAddr; + uint32_t recoveryAction = 0; + int i; + + printf("%s\n", "********************************************"); + printf("%s\n", "INFO: FPGA Rx DMAs & Tollgates"); + printf("%s\n", "********************************************"); + fpgaAddr = 0x43101008; + for (i = 0; i < 2; i++) + { + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::run_stop: ", (fpgaReg & 0x1)); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::enable_sg: ", ((fpgaReg >> 2) & 0x1)); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::enable_enhanced_mode: ", ((fpgaReg >> 3) & 0x1)); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::valid_data_width_stream: ", ((fpgaReg >> 8) & 0xF)); + + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 4), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::active: ", (fpgaReg & 0x1)); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::complete: ", ((fpgaReg >> 1) & 0x1)); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::halt_complete: ", ((fpgaReg >> 2) & 0x1)); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::overflow: ", ((fpgaReg >> 3) & 0x1)); + + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 8), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s0x%x\n", "dp_dma_rx_", i, "::simple_start_addr: ", fpgaReg); + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 16), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", "dp_dma_rx_", i, "::length: ", fpgaReg); + + fpgaAddr += 0x1000; + } + fpgaAddr = 0x43103004; + for (i = 0; i < 2; i++) + { + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", "dp_tollgate_rx_", i, "::reset: ", (fpgaReg & 0x1)); + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 4), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s0x%x\n", "dp_tollgate_rx_", i, "::trigger_select: ", fpgaReg); + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 8), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s0x%x\n", "dp_tollgate_rx_", i, "::edge_level: ", fpgaReg); + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 12), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s0x%x\n", "dp_tollgate_rx_", i, "::high_rising_low_falling: ", fpgaReg); + + fpgaAddr += 0x1000; + } + + printf("%s\n", "********************************************"); + printf("%s\n", "INFO: FPGA Tx DMAs & Tollgates"); + printf("%s\n", "********************************************"); + fpgaAddr = 0x43201008; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", "dp_dma_tx_0::run_stop: ", (fpgaReg & 0x1)); + printf("%s%u\n", "dp_dma_tx_0::continuous: ", ((fpgaReg >> 1) & 0x1)); + printf("%s%u\n", "dp_dma_tx_0::enable_sg: ", ((fpgaReg >> 2) & 0x1)); + printf("%s%u\n", "dp_dma_tx_0::enable_enhanced_mode: ", ((fpgaReg >> 3) & 0x1)); + printf("%s%u\n", "dp_dma_tx_0::valid_data_width_stream: ", ((fpgaReg >> 8) & 0xF)); + + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 4), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", "dp_dma_tx_0::active: ", (fpgaReg & 0x1)); + printf("%s%u\n", "dp_dma_tx_0::complete: ", ((fpgaReg >> 1) & 0x1)); + printf("%s%u\n", "dp_dma_tx_0::halt_complete: ", ((fpgaReg >> 2) & 0x1)); + printf("%s%u\n", "dp_dma_tx_0::underflow: ", ((fpgaReg >> 3) & 0x1)); + + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 8), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", "dp_dma_tx_0::simple_start_addr: ", fpgaReg); + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 16), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", "dp_dma_tx_0::length: ", fpgaReg); + + fpgaAddr = 0x43202004; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", "dp_tollgate_tx_0::reset: ", (fpgaReg & 0x1)); + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 4), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", "dp_tollgate_tx_0::trigger_select: ", fpgaReg); + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 8), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", "dp_tollgate_tx_0::edge_level: ", fpgaReg); + recoveryAction = adi_fpga9010_RegisterRead(device, (fpgaAddr + 12), &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", "dp_tollgate_tx_0::high_rising_low_falling: ", fpgaReg); + + printf("%s\n", "********************************************"); + printf("%s\n", "INFO: FPGA Tx Capture Control"); + printf("%s\n", "********************************************"); + fpgaAddr = 0x43200008; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", "dp_capture_control_tx::datapath_active: ", (fpgaReg & 0x1)); + printf("%s%u\n", "dp_capture_control_tx::pass_token: ", ((fpgaReg >> 1) & 0x1)); + + printf("%s\n", "********************************************"); + printf("%s\n", "INFO: FPGA Rx Capture Control"); + printf("%s\n", "********************************************"); + fpgaAddr = 0x43100008; + recoveryAction = adi_fpga9010_RegisterRead(device, fpgaAddr, &fpgaReg); + ADI_ERROR_REPORT(&device->common, device->common.error.errSource, device->common.error.errCode, recoveryAction, device->common.error.varName, device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", "dp_capture_control_rx::datapath_active: ", (fpgaReg & 0x1)); + printf("%s%u\n", "dp_capture_control_rx::pass_token: ", ((fpgaReg >> 1) & 0x1)); + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/resources/adi_fpga_mem_map.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/resources/adi_fpga_mem_map.h new file mode 100644 index 0000000..ad78384 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9010/resources/adi_fpga_mem_map.h @@ -0,0 +1,746 @@ +#ifndef _ADI_FPGA9010_MEM_MAP_H_ +#define _ADI_FPGA9010_MEM_MAP_H_ + +#include +uint32_t fpga9010_mem_map[] = { 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0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + +#endif /* _ADI_FPGA9010_MEM_MAP_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/makefile b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/makefile new file mode 100644 index 0000000..ca0758f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/makefile @@ -0,0 +1,37 @@ +LIB_ADI_FPGA9025_DEVICE = libadi_fpga9025.a +CC = gcc +ADI_FPGA9025_SRC = ./public/src +ADI_FPGA9025_PRIVATE_SRC = ./private/src +ARFLAGS = -rv +CFLAGS = -Werror -Wall -I./public/include -I../../platforms/ -I../../platforms/platform_utils -I../../common/ -I../../common/adi_error -I../../common/adi_logging -I../../common/adi_hal +ADI_PLATFORM_SRC = ../../platforms +ADI_COMMON_SRC = ../../common +EXT = c + +SRC = $(wildcard $(ADI_FPGA9025_PRIVATE_SRC)/*.$(EXT)) \ + $(wildcard $(ADI_FPGA9025_SRC)/*.$(EXT)) + +OBJS = $(SRC:.$(EXT)=.o) + +all: adi_platform_lib \ + adi_common_lib \ + $(LIB_ADI_FPGA9025_DEVICE) + +.$(EXT).o: + $(CC) $(CFLAGS) -o $@ -c $< + +$(LIB_ADI_FPGA9025_DEVICE): $(OBJS) + ar $(ARFLAGS) $(LIB_ADI_FPGA9025_DEVICE) $(OBJS) + +adi_platform_lib: + $(MAKE) -C $(ADI_PLATFORM_SRC) + +adi_common_lib: + $(MAKE) -C $(ADI_COMMON_SRC) + +clean: + rm -rf $(ADI_FPGA9025_SRC)/*.o + rm -rf $(ADI_FPGA9025_PRIVATE_SRC)/*.o + rm -rf *.a + $(MAKE) -C $(ADI_PLATFORM_SRC) clean + $(MAKE) -C $(ADI_COMMON_SRC) clean diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_ads9v2.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_ads9v2.h new file mode 100644 index 0000000..e24300f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_ads9v2.h @@ -0,0 +1,241 @@ +/** + * \file fpga9025_bf_ads9v2.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_ADS9V2_H__ +#define __FPGA9025_BF_ADS9V2_H__ + +#include "./../../private/include/fpga9025_bf_ads9v2_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_Ads9v2Ad9528ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2Ad9528ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2Ad9576ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2Ad9576ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2ExtTrig0DirBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2ExtTrig0DirBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2ExtTrig0OutputSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2ExtTrig0OutputSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2ExtTrig1DirBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2ExtTrig1DirBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2ExtTrig1OutputSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2ExtTrig1OutputSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2ExtTrig2DirBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2ExtTrig2DirBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2ExtTrig2OutputSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2ExtTrig2OutputSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2ExtTrig3DirBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2ExtTrig3DirBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2ExtTrig3OutputSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2ExtTrig3OutputSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2ExtTrigRxdp00CtrlSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2ExtTrigRxdp00CtrlSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2ExtTrigRxdp01CtrlSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2ExtTrigRxdp01CtrlSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2ExtTrigRxdp02CtrlSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2ExtTrigRxdp02CtrlSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2ExtTrigTddCtrlSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2ExtTrigTddCtrlSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2ExtTrigTxdp00CtrlSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2ExtTrigTxdp00CtrlSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2ExtTrigTxdp01CtrlSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2ExtTrigTxdp01CtrlSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2GlobalResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2GlobalResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2LedBlinkDurationBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Ads9v2LedBlinkDurationBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Ads9v2LedDelayToModeChangeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Ads9v2LedDelayToModeChangeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Ads9v2LedMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2LedMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2LedModeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2LedModeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2LedNumBlinksBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2LedNumBlinksBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2LedSwDefinedValueBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2LedSwDefinedValueBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2MgtRefclkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2MgtRefclkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2Pca9545ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Ads9v2Pca9545ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2VersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Ads9v2VersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint16_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_ADS9V2_H__ + +/* EOF: fpga9025_bf_ads9v2.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_ads9v2_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_ads9v2_types.h new file mode 100644 index 0000000..a95d9e2 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_ads9v2_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9025_bf_ads9v2_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_ADS9V2_TYPES_H__ +#define __FPGA9025_BF_ADS9V2_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfAds9v2ChanAddr +{ + FPGA9025_BF_ADS9V2 = 0x43040000 +} fpga9025_BfAds9v2ChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_ADS9V2_TYPES_H__ + +/* EOF: fpga9025_bf_ads9v2_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_adrv9025.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_adrv9025.h new file mode 100644 index 0000000..6b2faaa --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_adrv9025.h @@ -0,0 +1,297 @@ +/** + * \file fpga9025_bf_axi_adrv9025.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_AXI_ADRV9025_H__ +#define __FPGA9025_BF_AXI_ADRV9025_H__ + +#include "./../../private/include/fpga9025_bf_axi_adrv9025_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_AxiAdrv9025Ad9528ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025Ad9528ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025Adrv9025ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025Adrv9025ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025DesignIdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpInterrupt0BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpInterrupt0DetCounterBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpInterrupt0DetEdgeLevelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpInterrupt0DetEdgeLevelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpInterrupt0DetPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpInterrupt0DetPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpInterrupt1BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpInterrupt1DetCounterBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpInterrupt1DetEdgeLevelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpInterrupt1DetEdgeLevelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpInterrupt1DetPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpInterrupt1DetPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioEnArmJtagBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioEnArmJtagBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioEnSpi2BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioEnSpi2BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioEnTxToOrxBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioEnTxToOrxBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioInputBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioOutputBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioOutputBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioSelTx1ToOrx1BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioSelTx1ToOrx1BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioSelTx1ToOrx2BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioSelTx1ToOrx2BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioSelTx2ToOrx1BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioSelTx2ToOrx1BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioSelTx2ToOrx2BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioSelTx2ToOrx2BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioSelTx3ToOrx3BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioSelTx3ToOrx3BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioSelTx3ToOrx4BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioSelTx3ToOrx4BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioSelTx4ToOrx3BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioSelTx4ToOrx3BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioSelTx4ToOrx4BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioSelTx4ToOrx4BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcRxdp00BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcRxdp00BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcRxdp01BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcRxdp01BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcRxdp02BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcRxdp02BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcTxdp00BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcTxdp00BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcTxdp01BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcTxdp01BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025GpioTristateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_AxiAdrv9025GpioTristateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_AxiAdrv9025ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025ScratchPadBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_AxiAdrv9025ScratchPadBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_AxiAdrv9025TestInputBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025TestInputBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025TestOutputBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025TestOutputBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025TestTristateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdrv9025TestTristateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025VersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdrv9025VersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint16_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_AXI_ADRV9025_H__ + +/* EOF: fpga9025_bf_axi_adrv9025.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_adrv9025_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_adrv9025_types.h new file mode 100644 index 0000000..534feaa --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_adrv9025_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9025_bf_axi_adrv9025_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_AXI_ADRV9025_TYPES_H__ +#define __FPGA9025_BF_AXI_ADRV9025_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfAxiAdrv9025ChanAddr +{ + FPGA9025_BF_AXI_ADRV9025 = 0x43041000 +} fpga9025_BfAxiAdrv9025ChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_AXI_ADRV9025_TYPES_H__ + +/* EOF: fpga9025_bf_axi_adrv9025_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_adv_spi.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_adv_spi.h new file mode 100644 index 0000000..8509787 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_adv_spi.h @@ -0,0 +1,325 @@ +/** + * \file fpga9025_bf_axi_adv_spi.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_AXI_ADV_SPI_H__ +#define __FPGA9025_BF_AXI_ADV_SPI_H__ + +#include "./../../private/include/fpga9025_bf_axi_adv_spi_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_AxiAdvSpiAdvFeat3wireTriPointBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiAdvFeat3wireTriPointBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiAdvFeatClockDivBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint16_t bfValue); + +int32_t fpga9025_AxiAdvSpiAdvFeatClockDivBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint16_t* bfValue); + +int32_t fpga9025_AxiAdvSpiAdvFeatCphaBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiAdvFeatCphaBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiAdvFeatCpolBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiAdvFeatCpolBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiAdvFeatEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiAdvFeatEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiAdvFeatFourWireBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiAdvFeatFourWireBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiAdvFeatLsbFirstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiAdvFeatLsbFirstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiAdvFeatMisoSampleSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiAdvFeatMisoSampleSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiCphaBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiCphaBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiCpolBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiCpolBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiDrrFullBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiDrrFullBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiDrrFullIenBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiDrrFullIenBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiDrrOverrunBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiDrrOverrunBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiDrrOverrunIenBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiDrrOverrunIenBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiDtrEmptyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiDtrEmptyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiDtrEmptyIenBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiDtrEmptyIenBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiGieBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiGieBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiLoopBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiLoopBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiLsbFirstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiLsbFirstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiManSsEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiManSsEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiMasterBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiMasterBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiModfBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiModfFlagBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiModfIenBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiModfIenBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiMstrInhibitBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiMstrInhibitBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_AxiAdvSpiRxDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiRxEmptyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiRxFifoOccupancyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_AxiAdvSpiRxFifoResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiRxFullBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiSlaveSelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_AxiAdvSpiSlaveSelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_AxiAdvSpiSpeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiSpeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiTxDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiTxEmptyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiTxFifoHalfEmptyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiTxFifoHalfEmptyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiTxFifoHalfEmptyIenBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiTxFifoHalfEmptyIenBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiTxFifoOccupancyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_AxiAdvSpiTxFifoResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiAdvSpiTxFullBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiAdvSpiModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint16_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_AXI_ADV_SPI_H__ + +/* EOF: fpga9025_bf_axi_adv_spi.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_adv_spi_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_adv_spi_types.h new file mode 100644 index 0000000..d53e1c1 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_adv_spi_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9025_bf_axi_adv_spi_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_AXI_ADV_SPI_TYPES_H__ +#define __FPGA9025_BF_AXI_ADV_SPI_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfAxiAdvSpiChanAddr +{ + FPGA9025_BF_AXI_ADV_SPI = 0x44A00000 +} fpga9025_BfAxiAdvSpiChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_AXI_ADV_SPI_TYPES_H__ + +/* EOF: fpga9025_bf_axi_adv_spi_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_hmc.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_hmc.h new file mode 100644 index 0000000..0650e2d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_hmc.h @@ -0,0 +1,101 @@ +/** + * \file fpga9025_bf_axi_hmc.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_AXI_HMC_H__ +#define __FPGA9025_BF_AXI_HMC_H__ + +#include "./../../private/include/fpga9025_bf_axi_hmc_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_AxiHmcAxilitePageBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_AxiHmcAxilitePageBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiHmcHmc0DevRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiHmcHmc0FerrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiHmcHmc0MmcmRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiHmcHmc0PhyRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiHmcHmc0XcvrRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiHmcHmc1DevRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiHmcHmc1FerrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiHmcHmc1MmcmRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiHmcHmc1PhyRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiHmcHmc1XcvrRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_AxiHmcScratchBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_AxiHmcScratchBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_AxiHmcTimerBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_AxiHmcTimerBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_AxiHmcVersionBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint32_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_AXI_HMC_H__ + +/* EOF: fpga9025_bf_axi_hmc.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_hmc_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_hmc_types.h new file mode 100644 index 0000000..81a1d92 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_axi_hmc_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9025_bf_axi_hmc_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_AXI_HMC_TYPES_H__ +#define __FPGA9025_BF_AXI_HMC_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfAxiHmcChanAddr +{ + FPGA9025_BF_AXI_HMC = 0x43042800 +} fpga9025_BfAxiHmcChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_AXI_HMC_TYPES_H__ + +/* EOF: fpga9025_bf_axi_hmc_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_clock_freq_detect.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_clock_freq_detect.h new file mode 100644 index 0000000..1c8903f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_clock_freq_detect.h @@ -0,0 +1,113 @@ +/** + * \file fpga9025_bf_clock_freq_detect.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_CLOCK_FREQ_DETECT_H__ +#define __FPGA9025_BF_CLOCK_FREQ_DETECT_H__ + +#include "./../../private/include/fpga9025_bf_clock_freq_detect_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_ClockFreqDetectClockFreq0BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_ClockFreqDetectClockFreq1BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_ClockFreqDetectClockFreq10BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_ClockFreqDetectClockFreq11BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_ClockFreqDetectClockFreq12BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_ClockFreqDetectClockFreq13BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_ClockFreqDetectClockFreq14BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_ClockFreqDetectClockFreq15BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_ClockFreqDetectClockFreq2BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_ClockFreqDetectClockFreq3BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_ClockFreqDetectClockFreq4BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_ClockFreqDetectClockFreq5BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_ClockFreqDetectClockFreq6BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_ClockFreqDetectClockFreq7BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_ClockFreqDetectClockFreq8BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_ClockFreqDetectClockFreq9BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_ClockFreqDetectLocalResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_ClockFreqDetectLocalResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_ClockFreqDetectModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_ClockFreqDetectModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint16_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif /* __FPGA9025_BF_CLOCK_FREQ_DETECT_H__ */ + +/* EOF: fpga9025_bf_clock_freq_detect.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_clock_freq_detect_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_clock_freq_detect_types.h new file mode 100644 index 0000000..d81026b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_clock_freq_detect_types.h @@ -0,0 +1,36 @@ +/** + * \file fpga9025_bf_clock_freq_detect_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_CLOCK_FREQ_DETECT_TYPES_H__ +#define __FPGA9025_BF_CLOCK_FREQ_DETECT_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfClockFreqDetectChanAddr +{ + FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR = 0x43404000, + FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG = 0x43415000 +} fpga9025_BfClockFreqDetectChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_CLOCK_FREQ_DETECT_TYPES_H__ + +/* EOF: fpga9025_bf_clock_freq_detect_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_capture_control.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_capture_control.h new file mode 100644 index 0000000..75f84a1 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_capture_control.h @@ -0,0 +1,65 @@ +/** + * \file fpga9025_bf_dp_capture_control.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_DP_CAPTURE_CONTROL_H__ +#define __FPGA9025_BF_DP_CAPTURE_CONTROL_H__ + +#include "./../../private/include/fpga9025_bf_dp_capture_control_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_DpCaptureControlDatapathActiveBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpCaptureControlDatapathActiveBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpCaptureControlModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpCaptureControlModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpCaptureControlChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_DpCaptureControlPassTokenBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpCaptureControlPassTokenBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpCaptureControlResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpCaptureControlResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif /* __FPGA9025_BF_DP_CAPTURE_CONTROL_H__ */ + +/* EOF: fpga9025_bf_dp_capture_control.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_capture_control_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_capture_control_types.h new file mode 100644 index 0000000..76aeab5 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_capture_control_types.h @@ -0,0 +1,36 @@ +/** + * \file fpga9025_bf_dp_capture_control_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_DP_CAPTURE_CONTROL_TYPES_H__ +#define __FPGA9025_BF_DP_CAPTURE_CONTROL_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfDpCaptureControlChanAddr +{ + FPGA9025_BF_DP_CAPTURE_CONTROL_RX = 0x43100000, + FPGA9025_BF_DP_CAPTURE_CONTROL_TX = 0x43200000 +} fpga9025_BfDpCaptureControlChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_DP_CAPTURE_CONTROL_TYPES_H__ + +/* EOF: fpga9025_bf_dp_capture_control_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_rx_dma.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_rx_dma.h new file mode 100644 index 0000000..10baafd --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_rx_dma.h @@ -0,0 +1,137 @@ +/** + * \file fpga9025_bf_dp_rx_dma.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_DP_RX_DMA_H__ +#define __FPGA9025_BF_DP_RX_DMA_H__ + +#include "./../../private/include/fpga9025_bf_dp_rx_dma_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_DpRxDmaActiveBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpRxDmaCompleteBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpRxDmaEnableEnhancedModeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpRxDmaEnableEnhancedModeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpRxDmaEnableSgBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpRxDmaEnableSgBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpRxDmaHaltCompleteBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpRxDmaLengthBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_DpRxDmaLengthBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_DpRxDmaOverflowBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpRxDmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpRxDmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpRxDmaRunStopBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpRxDmaRunStopBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpRxDmaSgFirstDescriptorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_DpRxDmaSgFirstDescriptorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_DpRxDmaSgLastDescriptorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_DpRxDmaSgLastDescriptorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_DpRxDmaSimpleStartAddrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_DpRxDmaSimpleStartAddrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_DpRxDmaSimpleStartAddrMswBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_DpRxDmaSimpleStartAddrMswBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_DpRxDmaValidDataWidthStreamBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpRxDmaValidDataWidthStreamBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpRxDmaVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpRxDmaVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint16_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_DP_RX_DMA_H__ + +/* EOF: fpga9025_bf_dp_rx_dma.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_rx_dma_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_rx_dma_types.h new file mode 100644 index 0000000..c38f294 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_rx_dma_types.h @@ -0,0 +1,37 @@ +/** + * \file fpga9025_bf_dp_rx_dma_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_DP_RX_DMA_TYPES_H__ +#define __FPGA9025_BF_DP_RX_DMA_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfDpRxDmaChanAddr +{ + FPGA9025_BF_DP_DMA_RX_0 = 0x43101000, + FPGA9025_BF_DP_DMA_RX_1 = 0x43102000, + FPGA9025_BF_DP_DMA_RX_2 = 0x43105000 +} fpga9025_BfDpRxDmaChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif /* __FPGA9025_BF_DP_RX_DMA_TYPES_H__ */ + +/* EOF: fpga9025_bf_dp_rx_dma_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tollgate.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tollgate.h new file mode 100644 index 0000000..8d7a9e8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tollgate.h @@ -0,0 +1,73 @@ +/** + * \file fpga9025_bf_dp_tollgate.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_DP_TOLLGATE_H__ +#define __FPGA9025_BF_DP_TOLLGATE_H__ + +#include "./../../private/include/fpga9025_bf_dp_tollgate_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_DpTollgateEdgeLevelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_DpTollgateEdgeLevelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_DpTollgateHighRisingLowFallingBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_DpTollgateHighRisingLowFallingBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_DpTollgateModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpTollgateModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_DpTollgateResetTollgateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpTollgateResetTollgateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpTollgateTriggerSelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_DpTollgateTriggerSelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint32_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_DP_TOLLGATE_H__ + +/* EOF: fpga9025_bf_dp_tollgate.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tollgate_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tollgate_types.h new file mode 100644 index 0000000..a43a058 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tollgate_types.h @@ -0,0 +1,39 @@ +/** + * \file fpga9025_bf_dp_tollgate_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_DP_TOLLGATE_TYPES_H__ +#define __FPGA9025_BF_DP_TOLLGATE_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfDpTollgateChanAddr +{ + FPGA9025_BF_DP_TOLLGATE_RX_0 = 0x43103000, + FPGA9025_BF_DP_TOLLGATE_RX_1 = 0x43104000, + FPGA9025_BF_DP_TOLLGATE_RX_2 = 0x43106000, + FPGA9025_BF_DP_TOLLGATE_TX_0 = 0x43202000, + FPGA9025_BF_DP_TOLLGATE_TX_1 = 0x43205000 +} fpga9025_BfDpTollgateChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif /* __FPGA9025_BF_DP_TOLLGATE_TYPES_H__ */ + +/* EOF: fpga9025_bf_dp_tollgate_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tx_dma.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tx_dma.h new file mode 100644 index 0000000..77c841b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tx_dma.h @@ -0,0 +1,145 @@ +/** + * \file fpga9025_bf_dp_tx_dma.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_DP_TX_DMA_H__ +#define __FPGA9025_BF_DP_TX_DMA_H__ + +#include "./../../private/include/fpga9025_bf_dp_tx_dma_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_DpTxDmaActiveBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpTxDmaCompleteBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpTxDmaContinuousBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpTxDmaContinuousBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpTxDmaEnableEnhancedModeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpTxDmaEnableEnhancedModeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpTxDmaEnableSgBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpTxDmaEnableSgBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpTxDmaHaltCompleteBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpTxDmaLengthBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_DpTxDmaLengthBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_DpTxDmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpTxDmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpTxDmaRunStopBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpTxDmaRunStopBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpTxDmaSgLastDescriptorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_DpTxDmaSgLastDescriptorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_DpTxDmaSimpleStartAddrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_DpTxDmaSimpleStartAddrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_DpTxDmaSimpleStartAddrMswBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_DpTxDmaSimpleStartAddrMswBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_DpTxDmaSqFirstDescriptorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_DpTxDmaSqFirstDescriptorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_DpTxDmaUnderflowBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpTxDmaValidDataWidthStreamBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpTxDmaValidDataWidthStreamBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpTxDmaVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpTxDmaVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint16_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_DP_TX_DMA_H__ + +/* EOF: fpga9025_bf_dp_tx_dma.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tx_dma_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tx_dma_types.h new file mode 100644 index 0000000..6ebf4ad --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tx_dma_types.h @@ -0,0 +1,36 @@ +/** + * \file fpga9025_bf_dp_tx_dma_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_DP_TX_DMA_TYPES_H__ +#define __FPGA9025_BF_DP_TX_DMA_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfDpTxDmaChanAddr +{ + FPGA9025_BF_DP_DMA_TX_0 = 0x43201000, + FPGA9025_BF_DP_DMA_TX_1 = 0x43204000 +} fpga9025_BfDpTxDmaChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_DP_TX_DMA_TYPES_H__ + +/* EOF: fpga9025_bf_dp_tx_dma_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tx_sof_select.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tx_sof_select.h new file mode 100644 index 0000000..771d1e3 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tx_sof_select.h @@ -0,0 +1,65 @@ +/** + * \file fpga9025_bf_dp_tx_sof_select.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_DP_TX_SOF_SELECT_H__ +#define __FPGA9025_BF_DP_TX_SOF_SELECT_H__ + +#include "./../../private/include/fpga9025_bf_dp_tx_sof_select_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_DpTxSofSelectDelayBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpTxSofSelectDelayBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpTxSofSelectModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpTxSofSelectModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxSofSelectChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_DpTxSofSelectResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpTxSofSelectResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_DpTxSofSelectSelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_DpTxSofSelectSelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_DP_TX_SOF_SELECT_H__ + +/* EOF: fpga9025_bf_dp_tx_sof_select.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tx_sof_select_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tx_sof_select_types.h new file mode 100644 index 0000000..64c7c38 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_dp_tx_sof_select_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9025_bf_dp_tx_sof_select_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_DP_TX_SOF_SELECT_TYPES_H__ +#define __FPGA9025_BF_DP_TX_SOF_SELECT_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfDpTxSofSelectChanAddr +{ + FPGA9025_BF_DP_TX_SOF_SELECT = 0x43203000 +} fpga9025_BfDpTxSofSelectChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_DP_TX_SOF_SELECT_TYPES_H__ + +/* EOF: fpga9025_bf_dp_tx_sof_select_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_hal.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_hal.h new file mode 100644 index 0000000..caee077 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_hal.h @@ -0,0 +1,65 @@ +#ifndef FPGA9025_BF_HAL_H_ +#define FPGA9025_BF_HAL_H_ + +#include +#include +#include "adi_common_hal.h" +#include "adi_fpga9025.h" +#include "./../../private/include/fpga9025_bf_hal_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define BF_LOG_LEVEL 0xF + +#define ADRV9025_BF_WRCACHE_ARRAY_SIZE 15 +#define ADRV9025_BF_WRCACHE_ARRAY_TRIP_SIZE ADRV9025_BF_WRCACHE_ARRAY_SIZE -2 + +#define ADRV9025_BF_RDCACHE_ARRAY_SIZE 15 +#define ADRV9025_BF_RDCACHE_ARRAY_TRIP_SIZE ADRV9025_BF_RDCACHE_ARRAY_SIZE -2 + +/* int32_t fpga9025_BfWriteCacheEn(adi_fpga9025_Device_t *device, adrv9025_Bf_WrCache_State_e wrCacheState); */ +/* int32_t fpga9025_BfReadCacheEn(adi_fpga9025_Device_t *device, adrv9025_Bf_RdCache_State_e wrCacheState); */ +int32_t fpga9025_BfReadCacheInit(adi_fpga9025_Device_t* device); + +int32_t fpga9025_BfWriteCacheInit(adi_fpga9025_Device_t* device); + +int32_t fpga9025_BfRegisterWrite(adi_fpga9025_Device_t* device, + uint32_t addr, + uint32_t regVal); + +int32_t fpga9025_BfRegisterRead(adi_fpga9025_Device_t* device, + uint32_t addr, + uint32_t* regVal, + uint8_t endOfBf); + +int32_t fpga9025_BfFieldWrite(adi_fpga9025_Device_t* device, + uint32_t addr, + uint32_t fieldVal, + uint32_t mask, + uint8_t startBit); + +int32_t fpga9025_BfFieldRead(adi_fpga9025_Device_t* device, + uint32_t addr, + uint32_t* fieldVal, + uint32_t mask, + uint8_t startBit); + +int32_t fpga9025_BfReadAssembleData(adi_fpga9025_Device_t* device, + uint32_t* rxBfData, + uint8_t numRdBfData, + uint64_t* rdData); + +int32_t fpga9025_BfWriteCacheFlush(adi_fpga9025_Device_t* device); + +int32_t fpga9025_BfReadCacheFlush(adi_fpga9025_Device_t* device, + uint64_t* rdData, + uint16_t* numRxBitFields); + +#ifdef __cplusplus +} +#endif + +#endif /* ADRV9025_BF_HAL_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_hal_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_hal_types.h new file mode 100644 index 0000000..038b49b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_hal_types.h @@ -0,0 +1,48 @@ +/** +* \brief Contains BitField definitions to support ADRV9025 transceiver device. +* +*/ + +/** +* Disclaimer Legal Disclaimer +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef __ADRV9025_BF_HAL_TYPES_H__ +#define __ADRV9025_BF_HAL_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum adrv9025_Bf_Error +{ + ADRV9025_BF_NO_ACTION = 10, /*!< BitField function successful. No error Detected */ + ADRV9025_BF_SPI_FAIL, /*!< HAL SPI operation failure. SPI controller Down */ + ADRV9025_BF_CACHE_OVERFLOW /*!< The bitField Cache has exceeded the cache size */ +} adrv9025_Bf_Error_e; + +typedef enum adrv9025_Bf_WrCache_State +{ + ADRV9025_WR_CACHE_OFF = 0x0, + ADRV9025_WR_HW_RMW_ON = 0x1, + ADRV9025_WR_BF_CACHE_ON = 0x2, + ADRV9025_WR_GLB_CACHE_ON = 0x4, + ADRV9025_WR_GBL_MERGE_ON = 0x8 +} adrv9025_Bf_WrCache_State_e; + +typedef enum adrv9025_Bf_RdCache_State +{ + ADRV9025_RD_CACHE_OFF = 0x0, + ADRV9025_RD_BF_CACHE_ON = 0x1, + ADRV9025_RD_GLB_CACHE_ON = 0x2 +} adrv9025_Bf_RdCache_State_e; + +#ifdef __cplusplus +} +#endif + +#endif /* __ADRV9025_BF_HAL_TYPES_H__ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_ila_trigger.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_ila_trigger.h new file mode 100644 index 0000000..467ef43 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_ila_trigger.h @@ -0,0 +1,49 @@ +/** + * \file fpga9025_bf_ila_trigger.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_ILA_TRIGGER_H__ +#define __FPGA9025_BF_ILA_TRIGGER_H__ + +#include "./../../private/include/fpga9025_bf_ila_trigger_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_IlaTriggerModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfIlaTriggerChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_IlaTriggerModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfIlaTriggerChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_IlaTriggerTriggerBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfIlaTriggerChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_IlaTriggerTriggerBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfIlaTriggerChanAddr_e baseAddr, + uint32_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_ILA_TRIGGER_H__ + +/* EOF: fpga9025_bf_ila_trigger.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_ila_trigger_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_ila_trigger_types.h new file mode 100644 index 0000000..c036c77 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_ila_trigger_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9025_bf_ila_trigger_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_ILA_TRIGGER_TYPES_H__ +#define __FPGA9025_BF_ILA_TRIGGER_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfIlaTriggerChanAddr +{ + FPGA9025_BF_ILA_TRIGGER = 0x43043000 +} fpga9025_BfIlaTriggerChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_ILA_TRIGGER_TYPES_H__ + +/* EOF: fpga9025_bf_ila_trigger_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_phy_ads9.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_phy_ads9.h new file mode 100644 index 0000000..5e894d5 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_phy_ads9.h @@ -0,0 +1,3577 @@ +/** + * \file fpga9025_bf_jesd204_phy_ads9.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_JESD204_PHY_ADS9_H__ +#define __FPGA9025_BF_JESD204_PHY_ADS9_H__ + +#include "./../../private/include/fpga9025_bf_jesd204_phy_ads9_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_Jesd204PhyAds9Channel0CpllLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0CpllPdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0CpllPdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0CpllRefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0CpllRefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0GtpowergoodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0GtpowergoodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0LoopbackBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0LoopbackBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0Rx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0Rx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxBufResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxBufResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxCdrHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxCdrHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxCdrlockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxCdrlockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxCommaDetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxCommaDetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxDfeLpmEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxDfeLpmEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxDfeLpmHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxDfeLpmHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxDfeLpmOverrideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxDfeLpmOverrideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxDfeLpmResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxDfeLpmResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxGearboxSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxGearboxSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxPrbsErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxPrbsErrCntRstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxPrbsErrCntRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0RxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0Tx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0Tx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxDiffControlBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxDiffControlBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPostcursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPostcursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPrbsInjErrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPrbsInjErrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPrecursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxPrecursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel0TxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1CpllLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1CpllPdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1CpllPdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1CpllRefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1CpllRefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1GtpowergoodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1GtpowergoodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1LoopbackBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1LoopbackBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1Rx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1Rx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxBufResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxBufResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxCdrHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxCdrHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxCdrlockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxCdrlockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxCommaDetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxCommaDetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxDfeLpmEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxDfeLpmEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxDfeLpmHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxDfeLpmHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxDfeLpmOverrideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxDfeLpmOverrideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxDfeLpmResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxDfeLpmResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxGearboxSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxGearboxSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxPrbsErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxPrbsErrCntRstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxPrbsErrCntRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1RxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1Tx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1Tx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxDiffControlBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxDiffControlBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPostcursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPostcursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPrbsInjErrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPrbsInjErrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPrecursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxPrecursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel1TxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2CpllLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2CpllPdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2CpllPdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2CpllRefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2CpllRefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2GtpowergoodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2GtpowergoodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2LoopbackBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2LoopbackBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2Rx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2Rx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxBufResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxBufResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxCdrHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxCdrHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxCdrlockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxCdrlockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxCommaDetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxCommaDetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxDfeLpmEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxDfeLpmEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxDfeLpmHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxDfeLpmHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxDfeLpmOverrideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxDfeLpmOverrideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxDfeLpmResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxDfeLpmResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxGearboxSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxGearboxSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxPrbsErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxPrbsErrCntRstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxPrbsErrCntRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2RxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2Tx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2Tx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxDiffControlBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxDiffControlBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPostcursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPostcursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPrbsInjErrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPrbsInjErrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPrecursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxPrecursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel2TxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3CpllLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3CpllPdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3CpllPdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3CpllRefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3CpllRefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3GtpowergoodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3GtpowergoodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3LoopbackBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3LoopbackBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3Rx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3Rx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxBufResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxBufResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxCdrHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxCdrHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxCdrlockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxCdrlockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxCommaDetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxCommaDetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxDfeLpmEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxDfeLpmEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxDfeLpmHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxDfeLpmHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxDfeLpmOverrideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxDfeLpmOverrideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxDfeLpmResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxDfeLpmResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxGearboxSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxGearboxSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxPrbsErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxPrbsErrCntRstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxPrbsErrCntRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3RxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3Tx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3Tx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxDiffControlBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxDiffControlBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPostcursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPostcursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPrbsInjErrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPrbsInjErrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPrecursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxPrecursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel3TxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4CpllLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4CpllPdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4CpllPdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4CpllRefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4CpllRefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4GtpowergoodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4GtpowergoodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4LoopbackBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4LoopbackBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4Rx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4Rx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxBufResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxBufResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxCdrHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxCdrHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxCdrlockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxCdrlockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxCommaDetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxCommaDetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxDfeLpmEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxDfeLpmEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxDfeLpmHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxDfeLpmHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxDfeLpmOverrideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxDfeLpmOverrideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxDfeLpmResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxDfeLpmResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxGearboxSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxGearboxSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxPrbsErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxPrbsErrCntRstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxPrbsErrCntRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4RxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4Tx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4Tx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxDiffControlBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxDiffControlBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPostcursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPostcursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPrbsInjErrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPrbsInjErrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPrecursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxPrecursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel4TxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5CpllLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5CpllPdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5CpllPdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5CpllRefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5CpllRefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5GtpowergoodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5GtpowergoodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5LoopbackBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5LoopbackBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5Rx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5Rx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxBufResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxBufResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxCdrHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxCdrHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxCdrlockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxCdrlockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxCommaDetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxCommaDetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxDfeLpmEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxDfeLpmEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxDfeLpmHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxDfeLpmHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxDfeLpmOverrideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxDfeLpmOverrideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxDfeLpmResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxDfeLpmResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxGearboxSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxGearboxSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxPrbsErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxPrbsErrCntRstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxPrbsErrCntRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5RxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5Tx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5Tx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxDiffControlBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxDiffControlBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPostcursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPostcursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPrbsInjErrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPrbsInjErrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPrecursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxPrecursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel5TxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6CpllLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6CpllPdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6CpllPdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6CpllRefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6CpllRefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6GtpowergoodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6GtpowergoodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6LoopbackBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6LoopbackBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6Rx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6Rx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxBufResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxBufResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxCdrHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxCdrHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxCdrlockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxCdrlockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxCommaDetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxCommaDetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxDfeLpmEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxDfeLpmEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxDfeLpmHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxDfeLpmHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxDfeLpmOverrideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxDfeLpmOverrideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxDfeLpmResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxDfeLpmResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxGearboxSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxGearboxSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxPrbsErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxPrbsErrCntRstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxPrbsErrCntRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6RxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6Tx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6Tx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxDiffControlBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxDiffControlBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPostcursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPostcursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPrbsInjErrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPrbsInjErrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPrecursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxPrecursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel6TxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7CpllLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7CpllPdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7CpllPdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7CpllRefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7CpllRefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7GtpowergoodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7GtpowergoodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7LoopbackBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7LoopbackBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7Rx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7Rx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxBufResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxBufResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxCdrHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxCdrHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxCdrlockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxCdrlockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxCommaDetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxCommaDetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxDfeLpmEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxDfeLpmEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxDfeLpmHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxDfeLpmHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxDfeLpmOverrideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxDfeLpmOverrideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxDfeLpmResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxDfeLpmResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxGearboxSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxGearboxSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxPrbsErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxPrbsErrCntRstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxPrbsErrCntRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7RxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7Tx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7Tx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxDiffControlBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxDiffControlBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPostcursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPostcursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPrbsInjErrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPrbsInjErrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPrecursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxPrecursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Channel7TxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9MmcmRefclkSelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9MmcmRefclkSelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9ModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9ModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll0LockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll0PdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll0PdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll0RefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll0RefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll0ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll0ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll1LockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll1PdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll1PdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll1RefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll1RefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll1ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll1ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll0LockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll0PdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll0PdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll0RefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll0RefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll0ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll0ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll1LockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll1PdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll1PdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll1RefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll1RefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll1ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll1ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_JESD204_PHY_ADS9_H__ + +/* EOF: fpga9025_bf_jesd204_phy_ads9.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_phy_ads9_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_phy_ads9_types.h new file mode 100644 index 0000000..64a3240 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_phy_ads9_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9025_bf_jesd204_phy_ads9_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_JESD204_PHY_ADS9_TYPES_H__ +#define __FPGA9025_BF_JESD204_PHY_ADS9_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfJesd204PhyAds9ChanAddr +{ + FPGA9025_BF_ADS9_JESD_PHY = 0x43400000 +} fpga9025_BfJesd204PhyAds9ChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_JESD204_PHY_ADS9_TYPES_H__ + +/* EOF: fpga9025_bf_jesd204_phy_ads9_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_rx_lane_xbar.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_rx_lane_xbar.h new file mode 100644 index 0000000..0cae8d7 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_rx_lane_xbar.h @@ -0,0 +1,305 @@ +/** + * \file fpga9025_bf_jesd204_rx_lane_xbar.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_JESD204_RX_LANE_XBAR_H__ +#define __FPGA9025_BF_JESD204_RX_LANE_XBAR_H__ + +#include "./../../private/include/fpga9025_bf_jesd204_rx_lane_xbar_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_Jesd204RxLaneXbarLane0SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane0SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane10SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane10SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane11SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane11SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane12SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane12SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane13SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane13SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane14SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane14SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane15SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane15SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane16SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane16SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane17SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane17SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane18SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane18SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane19SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane19SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane1SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane1SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane20SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane20SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane21SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane21SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane22SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane22SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane23SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane23SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane24SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane24SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane25SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane25SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane26SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane26SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane27SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane27SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane28SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane28SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane29SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane29SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane2SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane2SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane30SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane30SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane31SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane31SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane3SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane3SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane4SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane4SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane5SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane5SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane6SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane6SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane7SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane7SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane8SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane8SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane9SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLane9SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLaneResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarLaneResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204RxLaneXbarModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint16_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_JESD204_RX_LANE_XBAR_H__ + +/* EOF: fpga9025_bf_jesd204_rx_lane_xbar.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_rx_lane_xbar_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_rx_lane_xbar_types.h new file mode 100644 index 0000000..4b930ed --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_rx_lane_xbar_types.h @@ -0,0 +1,37 @@ +/** + * \file fpga9025_bf_jesd204_rx_lane_xbar_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_JESD204_RX_LANE_XBAR_TYPES_H__ +#define __FPGA9025_BF_JESD204_RX_LANE_XBAR_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfJesd204RxLaneXbarChanAddr +{ + FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0 = 0x43405000, + FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1 = 0x43406000, + FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2 = 0x4340B000 +} fpga9025_BfJesd204RxLaneXbarChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_JESD204_RX_LANE_XBAR_TYPES_H__ + +/* EOF: fpga9025_bf_jesd204_rx_lane_xbar_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_sysref_control.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_sysref_control.h new file mode 100644 index 0000000..4bb47b3 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_sysref_control.h @@ -0,0 +1,109 @@ +/** + * \file fpga9025_bf_jesd204_sysref_control.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_JESD204_SYSREF_CONTROL_H__ +#define __FPGA9025_BF_JESD204_SYSREF_CONTROL_H__ + +#include "./../../private/include/fpga9025_bf_jesd204_sysref_control_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_Jesd204SysrefControlExtSysrefPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204SysrefControlExtSysrefPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204SysrefControlExtSysrefRequestBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204SysrefControlExtSysrefRequestBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204SysrefControlExtSysrefSampleEdgeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204SysrefControlExtSysrefSampleEdgeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204SysrefControlIntSysrefEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204SysrefControlIntSysrefEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204SysrefControlIntSysrefFreerunBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204SysrefControlIntSysrefFreerunBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204SysrefControlIntSysrefGenPeriodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_Jesd204SysrefControlIntSysrefGenPeriodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204SysrefControlIntSysrefRequestBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204SysrefControlIntSysrefRequestBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204SysrefControlModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204SysrefControlModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204SysrefControlOutputEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_Jesd204SysrefControlOutputEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204SysrefControlSysrefReceivedBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_JESD204_SYSREF_CONTROL_H__ + +/* EOF: fpga9025_bf_jesd204_sysref_control.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_sysref_control_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_sysref_control_types.h new file mode 100644 index 0000000..5f975e8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_sysref_control_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9025_bf_jesd204_sysref_control_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_JESD204_SYSREF_CONTROL_TYPES_H__ +#define __FPGA9025_BF_JESD204_SYSREF_CONTROL_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfJesd204SysrefControlChanAddr +{ + FPGA9025_BF_JESD204_SYSREF_CONTROL = 0x43402000 +} fpga9025_BfJesd204SysrefControlChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_JESD204_SYSREF_CONTROL_TYPES_H__ + +/* EOF: fpga9025_bf_jesd204_sysref_control_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_test_det_lat.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_test_det_lat.h new file mode 100644 index 0000000..9fd91a2 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_test_det_lat.h @@ -0,0 +1,77 @@ +/** + * \file fpga9025_bf_jesd204_test_det_lat.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_JESD204_TEST_DET_LAT_H__ +#define __FPGA9025_BF_JESD204_TEST_DET_LAT_H__ + +#include "./../../private/include/fpga9025_bf_jesd204_test_det_lat_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_Jesd204TestDetLatEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TestDetLatEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TestDetLatLatencyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204TestDetLatModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TestDetLatModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204TestDetLatRxLinkBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TestDetLatRxLinkBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TestDetLatTxLinkBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TestDetLatTxLinkBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TestDetLatValidDataWidthBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TestDetLatValidDataWidthBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_JESD204_TEST_DET_LAT_H__ + +/* EOF: fpga9025_bf_jesd204_test_det_lat.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_test_det_lat_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_test_det_lat_types.h new file mode 100644 index 0000000..3cdeb30 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_test_det_lat_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9025_bf_jesd204_test_det_lat_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_JESD204_TEST_DET_LAT_TYPES_H__ +#define __FPGA9025_BF_JESD204_TEST_DET_LAT_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfJesd204TestDetLatChanAddr +{ + FPGA9025_BF_JESD204_TEST_DET_LAT = 0x4340F000 +} fpga9025_BfJesd204TestDetLatChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_JESD204_TEST_DET_LAT_TYPES_H__ + +/* EOF: fpga9025_bf_jesd204_test_det_lat_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_tx_lane_xbar.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_tx_lane_xbar.h new file mode 100644 index 0000000..f475982 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_tx_lane_xbar.h @@ -0,0 +1,305 @@ +/** + * \file fpga9025_bf_jesd204_tx_lane_xbar.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_JESD204_TX_LANE_XBAR_H__ +#define __FPGA9025_BF_JESD204_TX_LANE_XBAR_H__ + +#include "./../../private/include/fpga9025_bf_jesd204_tx_lane_xbar_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_Jesd204TxLaneXbarLane0SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane0SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane10SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane10SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane11SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane11SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane12SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane12SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane13SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane13SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane14SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane14SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane15SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane15SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane16SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane16SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane17SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane17SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane18SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane18SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane19SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane19SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane1SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane1SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane20SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane20SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane21SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane21SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane22SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane22SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane23SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane23SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane24SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane24SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane25SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane25SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane26SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane26SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane27SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane27SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane28SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane28SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane29SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane29SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane2SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane2SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane30SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane30SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane31SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane31SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane3SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane3SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane4SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane4SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane5SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane5SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane6SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane6SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane7SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane7SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane8SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane8SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane9SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLane9SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLaneResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarLaneResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204TxLaneXbarModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint16_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_JESD204_TX_LANE_XBAR_H__ + +/* EOF: fpga9025_bf_jesd204_tx_lane_xbar.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_tx_lane_xbar_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_tx_lane_xbar_types.h new file mode 100644 index 0000000..ab00045 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204_tx_lane_xbar_types.h @@ -0,0 +1,36 @@ +/** + * \file fpga9025_bf_jesd204_tx_lane_xbar_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_JESD204_TX_LANE_XBAR_TYPES_H__ +#define __FPGA9025_BF_JESD204_TX_LANE_XBAR_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfJesd204TxLaneXbarChanAddr +{ + FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0 = 0x43407000, + FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1 = 0x4340C000 +} fpga9025_BfJesd204TxLaneXbarChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_JESD204_TX_LANE_XBAR_TYPES_H__ + +/* EOF: fpga9025_bf_jesd204_tx_lane_xbar_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204b_sync_xbar.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204b_sync_xbar.h new file mode 100644 index 0000000..58e01b8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204b_sync_xbar.h @@ -0,0 +1,129 @@ +/** + * \file fpga9025_bf_jesd204b_sync_xbar.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_JESD204B_SYNC_XBAR_H__ +#define __FPGA9025_BF_JESD204B_SYNC_XBAR_H__ + +#include "./../../private/include/fpga9025_bf_jesd204b_sync_xbar_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_Jesd204bSyncXbarModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204bSyncXbarModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncInPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncInPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOut0SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOut0SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOut1SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOut1SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOut2SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOut2SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOut3SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOut3SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOut4SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOut4SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOut5SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOut5SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOut6SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOut6SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOut7SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOut7SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOutForceOutputBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOutForceOutputBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOutForceValueBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_Jesd204bSyncXbarSyncOutForceValueBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_JESD204B_SYNC_XBAR_H__ + +/* EOF: fpga9025_bf_jesd204b_sync_xbar.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204b_sync_xbar_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204b_sync_xbar_types.h new file mode 100644 index 0000000..6879558 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_jesd204b_sync_xbar_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9025_bf_jesd204b_sync_xbar_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_JESD204B_SYNC_XBAR_TYPES_H__ +#define __FPGA9025_BF_JESD204B_SYNC_XBAR_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfJesd204bSyncXbarChanAddr +{ + FPGA9025_BF_JESD204B_SYNC_XBAR = 0x43401000 +} fpga9025_BfJesd204bSyncXbarChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_JESD204B_SYNC_XBAR_TYPES_H__ + +/* EOF: fpga9025_bf_jesd204b_sync_xbar_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_orx_pin_encode_tokelau.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_orx_pin_encode_tokelau.h new file mode 100644 index 0000000..7b7e941 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_orx_pin_encode_tokelau.h @@ -0,0 +1,113 @@ +/** + * \file fpga9025_bf_orx_pin_encode_tokelau.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_ORX_PIN_ENCODE_TOKELAU_H__ +#define __FPGA9025_BF_ORX_PIN_ENCODE_TOKELAU_H__ + +#include "./../../private/include/fpga9025_bf_orx_pin_encode_tokelau_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_OrxPinEncodeTokelauFastSwitchingEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauFastSwitchingEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauMode1aOrxSelectHighBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauMode1aOrxSelectHighBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauMode1aOrxSelectLowBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauMode1aOrxSelectLowBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauMode3OrxSelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauMode3OrxSelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauModeSelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauModeSelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauOrxEnableHighTimeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauOrxEnableHighTimeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauOrxEnableLowTimeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauOrxEnableLowTimeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauOrxSelectSetupTimeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauOrxSelectSetupTimeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_OrxPinEncodeTokelauVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_ORX_PIN_ENCODE_TOKELAU_H__ + +/* EOF: fpga9025_bf_orx_pin_encode_tokelau.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_orx_pin_encode_tokelau_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_orx_pin_encode_tokelau_types.h new file mode 100644 index 0000000..7313e64 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_orx_pin_encode_tokelau_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9025_bf_orx_pin_encode_tokelau_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_ORX_PIN_ENCODE_TOKELAU_TYPES_H__ +#define __FPGA9025_BF_ORX_PIN_ENCODE_TOKELAU_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfOrxPinEncodeTokelauChanAddr +{ + FPGA9025_BF_TDD_ORX_PIN_ENCODE = 0x43318000 +} fpga9025_BfOrxPinEncodeTokelauChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_ORX_PIN_ENCODE_TOKELAU_TYPES_H__ + +/* EOF: fpga9025_bf_orx_pin_encode_tokelau_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_dp_ctrl.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_dp_ctrl.h new file mode 100644 index 0000000..dfafe5d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_dp_ctrl.h @@ -0,0 +1,57 @@ +/** + * \file fpga9025_bf_tdd_dp_ctrl.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_TDD_DP_CTRL_H__ +#define __FPGA9025_BF_TDD_DP_CTRL_H__ + +#include "./../../private/include/fpga9025_bf_tdd_dp_ctrl_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_TddDpCtrlEnableBitBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddDpCtrlChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_TddDpCtrlEnableBitBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddDpCtrlChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_TddDpCtrlStartValueBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddDpCtrlChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_TddDpCtrlStartValueBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddDpCtrlChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_TddDpCtrlVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddDpCtrlChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_TddDpCtrlVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddDpCtrlChanAddr_e baseAddr, + uint16_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_TDD_DP_CTRL_H__ + +/* EOF: fpga9025_bf_tdd_dp_ctrl.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_dp_ctrl_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_dp_ctrl_types.h new file mode 100644 index 0000000..8ba5ab8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_dp_ctrl_types.h @@ -0,0 +1,39 @@ +/** + * \file fpga9025_bf_tdd_dp_ctrl_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_TDD_DP_CTRL_TYPES_H__ +#define __FPGA9025_BF_TDD_DP_CTRL_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfTddDpCtrlChanAddr +{ + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_0 = 0x43315000, + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_1 = 0x43316000, + FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_0 = 0x43317000, + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_2 = 0x43319000, + FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_1 = 0x4331A000 +} fpga9025_BfTddDpCtrlChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_TDD_DP_CTRL_TYPES_H__ + +/* EOF: fpga9025_bf_tdd_dp_ctrl_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_enable_ctrl.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_enable_ctrl.h new file mode 100644 index 0000000..2f89dcd --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_enable_ctrl.h @@ -0,0 +1,121 @@ +/** + * \file fpga9025_bf_tdd_enable_ctrl.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_TDD_ENABLE_CTRL_H__ +#define __FPGA9025_BF_TDD_ENABLE_CTRL_H__ + +#include "./../../private/include/fpga9025_bf_tdd_enable_ctrl_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_TddEnableCtrlEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_TddEnableCtrlEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_TddEnableCtrlEndValueBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_TddEnableCtrlEndValueBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_TddEnableCtrlFramesActiveBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_TddEnableCtrlFramesActiveBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_TddEnableCtrlFramesInactiveBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_TddEnableCtrlFramesInactiveBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_TddEnableCtrlFramesOffsetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_TddEnableCtrlFramesOffsetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_TddEnableCtrlManualEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_TddEnableCtrlManualEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_TddEnableCtrlSecEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_TddEnableCtrlSecEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_TddEnableCtrlSecEndValueBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_TddEnableCtrlSecEndValueBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_TddEnableCtrlSecStartValueBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_TddEnableCtrlSecStartValueBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_TddEnableCtrlStartValueBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_TddEnableCtrlStartValueBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_TddEnableCtrlVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_TddEnableCtrlVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint16_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_TDD_ENABLE_CTRL_H__ + +/* EOF: fpga9025_bf_tdd_enable_ctrl.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_enable_ctrl_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_enable_ctrl_types.h new file mode 100644 index 0000000..c5f78f3 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_enable_ctrl_types.h @@ -0,0 +1,58 @@ +/** + * \file fpga9025_bf_tdd_enable_ctrl_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_TDD_ENABLE_CTRL_TYPES_H__ +#define __FPGA9025_BF_TDD_ENABLE_CTRL_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfTddEnableCtrlChanAddr +{ + FPGA9025_BF_TDD_ENABLE_CONTROL_RX1 = 0x43301000, + FPGA9025_BF_TDD_ENABLE_CONTROL_RX2 = 0x43302000, + FPGA9025_BF_TDD_ENABLE_CONTROL_RX3 = 0x43303000, + FPGA9025_BF_TDD_ENABLE_CONTROL_RX4 = 0x43304000, + FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1 = 0x43305000, + FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2 = 0x43306000, + FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3 = 0x43307000, + FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4 = 0x43308000, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX1 = 0x43309000, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX2 = 0x4330A000, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX3 = 0x4330B000, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX4 = 0x4330C000, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1 = 0x4330D000, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1 = 0x4330E000, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2 = 0x4330F000, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2 = 0x43310000, + FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1 = 0x43311000, + FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2 = 0x43312000, + FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3 = 0x43313000, + FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4 = 0x43314000, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3 = 0x4331B000, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3 = 0x4331C000, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4 = 0x4331D000, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4 = 0x4331E000 +} fpga9025_BfTddEnableCtrlChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif /* __FPGA9025_BF_TDD_ENABLE_CTRL_TYPES_H__ */ + +/* EOF: fpga9025_bf_tdd_enable_ctrl_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_frame_cnt.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_frame_cnt.h new file mode 100644 index 0000000..9336942 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_frame_cnt.h @@ -0,0 +1,81 @@ +/** + * \file fpga9025_bf_tdd_frame_cnt.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_TDD_FRAME_CNT_H__ +#define __FPGA9025_BF_TDD_FRAME_CNT_H__ + +#include "./../../private/include/fpga9025_bf_tdd_frame_cnt_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_TddFrameCntEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_TddFrameCntEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_TddFrameCntEndValueBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_TddFrameCntEndValueBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_TddFrameCntLoopCountBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_TddFrameCntLoopCountBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_TddFrameCntLoopCountEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_TddFrameCntLoopCountEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_TddFrameCntTriggerBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_TddFrameCntTriggerBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_TddFrameCntVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_TddFrameCntVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint16_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif /* __FPGA9025_BF_TDD_FRAME_CNT_H__ */ + +/* EOF: fpga9025_bf_tdd_frame_cnt.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_frame_cnt_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_frame_cnt_types.h new file mode 100644 index 0000000..be526f3 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_tdd_frame_cnt_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9025_bf_tdd_frame_cnt_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_TDD_FRAME_CNT_TYPES_H__ +#define __FPGA9025_BF_TDD_FRAME_CNT_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfTddFrameCntChanAddr +{ + FPGA9025_BF_TDD_FRAME_COUNTER = 0x43300000 +} fpga9025_BfTddFrameCntChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_TDD_FRAME_CNT_TYPES_H__ + +/* EOF: fpga9025_bf_tdd_frame_cnt_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_clock_wizard.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_clock_wizard.h new file mode 100644 index 0000000..84c7966 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_clock_wizard.h @@ -0,0 +1,285 @@ +/** + * \file fpga9025_bf_xilinx_clock_wizard.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_XILINX_CLOCK_WIZARD_H__ +#define __FPGA9025_BF_XILINX_CLOCK_WIZARD_H__ + +#include "./../../private/include/fpga9025_bf_xilinx_clock_wizard_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_XilinxClockWizardClkfboutFracBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkfboutFracBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkfboutMultBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkfboutMultBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkfboutPhaseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkfboutPhaseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout0DivideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout0DivideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout0DutyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout0DutyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout0FracBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout0FracBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout0PhaseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout0PhaseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout1DivideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout1DivideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout1DutyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout1DutyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout1PhaseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout1PhaseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout2DivideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout2DivideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout2DutyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout2DutyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout2PhaseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout2PhaseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout3DivideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout3DivideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout3DutyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout3DutyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout3PhaseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout3PhaseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout4DivideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout4DivideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout4DutyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout4DutyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout4PhaseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout4PhaseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout5DivideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout5DivideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout5DutyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout5DutyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout5PhaseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout5PhaseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout6DivideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout6DivideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout6DutyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout6DutyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardClkout6PhaseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardClkout6PhaseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardDivclkDivideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxClockWizardDivclkDivideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxClockWizardErrorStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardInterruptEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardInterruptEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardInterruptStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +int32_t fpga9025_XilinxClockWizardInterruptStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue); + +int32_t fpga9025_XilinxClockWizardLoadBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxClockWizardLoadBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxClockWizardLockedBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxClockWizardSaddrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxClockWizardSaddrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxClockWizardSoftwareResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_XILINX_CLOCK_WIZARD_H__ + +/* EOF: fpga9025_bf_xilinx_clock_wizard.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_clock_wizard_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_clock_wizard_types.h new file mode 100644 index 0000000..bab84a4 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_clock_wizard_types.h @@ -0,0 +1,35 @@ +/** + * \file fpga9025_bf_xilinx_clock_wizard_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_XILINX_CLOCK_WIZARD_TYPES_H__ +#define __FPGA9025_BF_XILINX_CLOCK_WIZARD_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfXilinxClockWizardChanAddr +{ + FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD = 0x43403000 +} fpga9025_BfXilinxClockWizardChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_XILINX_CLOCK_WIZARD_TYPES_H__ + +/* EOF: fpga9025_bf_xilinx_clock_wizard_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_jesd204b.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_jesd204b.h new file mode 100644 index 0000000..4134e1c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_jesd204b.h @@ -0,0 +1,500 @@ +/** + * \file fpga9025_bf_xilinx_jesd204b.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_XILINX_JESD204B_H__ +#define __FPGA9025_BF_XILINX_JESD204B_H__ + +#include "./../../private/include/fpga9025_bf_xilinx_jesd204b_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_XilinxJesd204bCfgFBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bCfgFBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bCfgKBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bCfgKBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bCfgLaneIdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bCfgLaneIdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bCfgSubclassvBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bCfgSubclassvBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bDisErrOnSyncBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bDisErrOnSyncBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaAdjcntBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaAdjcntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaAdjdirBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaAdjdirBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaBidBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaBidBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaCfBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaCfBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaCsBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaCsBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaDidBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaDidBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaFBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaFchkBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaFchkBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaHdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaHdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaJesdvBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaKBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaLBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaLidBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaMBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaMBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaMultiframesBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaMultiframesBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaNBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaNBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaNpBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaNpBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaPhadjBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaPhadjBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaRes1BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaRes1BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaRes2BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaRes2BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaSBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaSBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaScrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaSubclassBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bIlaSupportEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bIlaSupportEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLaneAlignAlarmBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLanesInUseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bLanesInUseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkDebugStatusLane0BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkDebugStatusLane1BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkDebugStatusLane2BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkDebugStatusLane3BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkDebugStatusLane4BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkDebugStatusLane5BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkDebugStatusLane6BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkDebugStatusLane7BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkErrCntBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t bfValue); + +int32_t fpga9025_XilinxJesd204bLinkErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkErrCntrsEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bLinkErrCntrsEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkErrorStatusLane0BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkErrorStatusLane1BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkErrorStatusLane2BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkErrorStatusLane3BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkErrorStatusLane4BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkErrorStatusLane5BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkErrorStatusLane6BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bLinkErrorStatusLane7BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bResetFixedBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bResetFixedBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bResetSelfClearingBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bResetSelfClearingBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bRxBufAdjBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint16_t* bfValue); + +int32_t fpga9025_XilinxJesd204bRxBufferDelayBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint16_t bfValue); + +int32_t fpga9025_XilinxJesd204bRxBufferDelayBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint16_t* bfValue); + +int32_t fpga9025_XilinxJesd204bRxBufferOvrfAlarmBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bScramblingEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bScramblingEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bSyncStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bSysrefAlwaysBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bSysrefAlwaysBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bSysrefCapturedBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bSysrefDelayBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bSysrefDelayBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bSysrefLmfcAlarmBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bSysrefRequiredOnResyncBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bSysrefRequiredOnResyncBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bTestModeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bTestModeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bTestModeErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t* bfValue); + +int32_t fpga9025_XilinxJesd204bTestModeIlaCntBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t bfValue); + +int32_t fpga9025_XilinxJesd204bTestModeIlaCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t* bfValue); + +int32_t fpga9025_XilinxJesd204bTestModeMfCntBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t bfValue); + +int32_t fpga9025_XilinxJesd204bTestModeMfCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t* bfValue); + +int32_t fpga9025_XilinxJesd204bVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bVersionRevisionBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204bWatchdogTimerDisableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204bWatchdogTimerDisableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_XILINX_JESD204B_H__ + +/* EOF: fpga9025_bf_xilinx_jesd204b.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_jesd204b_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_jesd204b_types.h new file mode 100644 index 0000000..d3fb622 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_jesd204b_types.h @@ -0,0 +1,39 @@ +/** + * \file fpga9025_bf_xilinx_jesd204b_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_XILINX_JESD204B_TYPES_H__ +#define __FPGA9025_BF_XILINX_JESD204B_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfXilinxJesd204bChanAddr +{ + FPGA9025_BF_JESD204B_DEFRAMER_0 = 0x43408000, + FPGA9025_BF_JESD204B_DEFRAMER_1 = 0x43409000, + FPGA9025_BF_JESD204B_FRAMER_0 = 0x4340A000, + FPGA9025_BF_JESD204B_DEFRAMER_2 = 0x4340D000, + FPGA9025_BF_JESD204B_FRAMER_1 = 0x4340E000 +} fpga9025_BfXilinxJesd204bChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_XILINX_JESD204B_TYPES_H__ + +/* EOF: fpga9025_bf_xilinx_jesd204b_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_jesd204c.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_jesd204c.h new file mode 100644 index 0000000..595b431 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_jesd204c.h @@ -0,0 +1,319 @@ +/** + * \file fpga9025_bf_xilinx_jesd204c.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_XILINX_JESD204C_H__ +#define __FPGA9025_BF_XILINX_JESD204C_H__ + +#include "./../../private/include/fpga9025_bf_xilinx_jesd204c_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t fpga9025_XilinxJesd204cBufferLevelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cBufferOverflowBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cCfgMbInEmbBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cCfgMbInEmbBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cCfgSubclassvBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cCfgSubclassvBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cCoreIsTxBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cCrcErrorCountBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t channelId, + uint16_t* bfValue); + +int32_t fpga9025_XilinxJesd204cEnableCmdInterfaceBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cEnableCmdInterfaceBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cEnableDataInterfaceBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cEnableDataInterfaceBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cFecCorrectedErrorCountBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t channelId, + uint16_t* bfValue); + +int32_t fpga9025_XilinxJesd204cFecUncorrectedErrorCountBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t channelId, + uint16_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqBlockSyncErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqCrcErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnBlockSyncErrorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnBlockSyncErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnCrcErrorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnCrcErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnFecErrorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnFecErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnGlobalBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnGlobalBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnLossMbLockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnLossMbLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnLossSyncHeaderLockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnLossSyncHeaderLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnMbErrorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnMbErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnOverflowErrorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnOverflowErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnSysrefErrorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnSysrefErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnSysrefReceivedBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cIrqEnSysrefReceivedBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqFecErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqLossMbLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqLossSyncHeaderLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqMbErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqOverflowErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqPendingBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqSysrefErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cIrqSysrefReceivedBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cLane64b66bAlignBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cLaneEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cLaneEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cLaneMbAlignBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cMbLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cMetaModeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cMetaModeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cMulitblockAlignmentErrorCountBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cNumberOfLanesInCoreBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cResetFixedBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cResetFixedBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cRxBufferDelayBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cRxBufferDelayBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cRxMbThBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cRxMbThBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cSyncHeaderAlignmentErrorCountBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cSyncHeaderLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cSysrefCapturedBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cSysrefDelayBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cSysrefDelayBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cSysrefErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cTestModeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue); + +int32_t fpga9025_XilinxJesd204cTestModeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +int32_t fpga9025_XilinxJesd204cVersionRevisionBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue); + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_XILINX_JESD204C_H__ + +/* EOF: fpga9025_bf_xilinx_jesd204c.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_jesd204c_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_jesd204c_types.h new file mode 100644 index 0000000..5ec4344 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_bf_xilinx_jesd204c_types.h @@ -0,0 +1,39 @@ +/** + * \file fpga9025_bf_xilinx_jesd204c_types.h Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __FPGA9025_BF_XILINX_JESD204C_TYPES_H__ +#define __FPGA9025_BF_XILINX_JESD204C_TYPES_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum fpga9025_BfXilinxJesd204cChanAddr +{ + FPGA9025_BF_JESD204C_DEFRAMER_0 = 0x43410000, + FPGA9025_BF_JESD204C_DEFRAMER_1 = 0x43411000, + FPGA9025_BF_JESD204C_DEFRAMER_2 = 0x43412000, + FPGA9025_BF_JESD204C_FRAMER_0 = 0x43413000, + FPGA9025_BF_JESD204C_FRAMER_1 = 0x43414000 +} fpga9025_BfXilinxJesd204cChanAddr_e; + +#ifdef __cplusplus +} +#endif + +#endif // __FPGA9025_BF_XILINX_JESD204C_TYPES_H__ + +/* EOF: fpga9025_bf_xilinx_jesd204c_types.h */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_jesd.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_jesd.h new file mode 100644 index 0000000..5b99b43 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_jesd.h @@ -0,0 +1,421 @@ +/** +* \file fpga9025_jesd.h +* \brief Contains private JESD related function prototypes for fpga9025_jesd.c +* +* FPGA9025 API Version: 6.4.0.14 +*/ +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _FPGA9025_JESD_H_ +#define _FPGA9025_JESD_H_ + +#include "adi_fpga9025_user.h" +#include "adi_fpga9025_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t adi_fpga9025_SerializerCfgSet(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + adi_fpga9025_SerializerCfg_t* serializerCfg); + +int32_t adi_fpga9025_SerializerCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_LaneSel_e laneSel, + adi_fpga9025_SerializerCfg_t* serializerCfg); + +/** +* \brief JESD204B implementation for adi_fpga9025_DeframerCfgSet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9025_DeframerSel_e enum values +* \param deframerCfg a pointer to an adi_fpga9025_DeframerCfg_t structure that contains the deframer configuration settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204BDeframerCfgSet(adi_fpga9025_Device_t* device, + uint32_t deframerSelMask, + adi_fpga9025_DeframerCfg_t* deframerCfg); + +/** +* \brief JESD204B implementation for adi_fpga9025_DeframerCfgGet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSel an adi_fpga9025_DeframerSel_e enum value selecting which deframer to read +* \param deframerCfg a pointer to an empty adi_fpga9025_DeframerCfg_t structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204BDeframerCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_DeframerSel_e deframerSel, + adi_fpga9025_DeframerCfg_t* deframerCfg); + +/** +* \brief JESD204B implementation for adi_fpga9025_FramerCfgSet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9025_FramerSel_e enum values +* \param framerCfg pointer to an adi_fpga9025_FramerCfg_t structure that contains the deserializer configuration settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204BFramerCfgSet(adi_fpga9025_Device_t* device, + uint8_t framerSelMask, + adi_fpga9025_FramerCfg_t* framerCfg); + +/** +* \brief JESD204B implementation for adi_fpga9025_FramerCfgGet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSel an adi_fpga9025_FramerSel_e enum value selecting a single framer +* \param framerCfg pointer to an empty adi_fpga9025_FramerCfg_t structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204BFramerCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_FramerSel_e framerSel, + adi_fpga9025_FramerCfg_t* framerCfg); + +/** +* \brief JESD204B helper function for FramerResetGet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9025_FramerSel_e enum values +* \param resetBits uint8_t pointer for the reset bits of the selected deframers that will correspond with their adi_fpga9025_FramerSel_e bit locations +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204BFramerResetGet(adi_fpga9025_Device_t* device, + uint32_t framerSelMask, + uint8_t* resetBits); + +/** +* \brief JESD204B helper function for FramerReset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9025_FramerSel_e enum values +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204BFramerReset(adi_fpga9025_Device_t* device, + uint8_t framerSelMask); + +/** +* \brief JESD204B helper function for DeframerReset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9025_DeframerSel_e enum values +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204BDeframerReset(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask); + +/** +* \brief JESD204B helper function for DeframerDisable. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9025_DeframerSel_e enum values +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204BDeframerDisable(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask); + +/** +* \brief JESD204B helper function for FramerDisable. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9025_FramerSel_e enum values +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204BFramerDisable(adi_fpga9025_Device_t* device, + uint8_t framerSelMask); + +/** +* \brief JESD204B helper function for DeframerStatusGet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9025_DeframerSel_e enum values +* \param status uint8_t pointer for the Sync status bits of the selected deframers that will correspond with their adi_fpga9025_DeframerSel_e bit locations +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204BDeframerStatusGet(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask, + uint8_t* status); + +/** +* \brief JESD204C implementation for adi_fpga9025_DeframerCfgSet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9025_DeframerSel_e enum values +* \param deframerCfg a pointer to an adi_fpga9025_DeframerCfg_t structure that contains the deframer configuration settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204CDeframerCfgSet(adi_fpga9025_Device_t* device, + uint32_t deframerSelMask, + adi_fpga9025_DeframerCfg_t* deframerCfg); + +/** +* \brief JESD204C implementation for adi_fpga9025_DeframerCfgGet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device pointer to the FPGA9025 device data structure. +* \param deframerSel an adi_fpga9025_DeframerSel_e enum value selecting which deframer to read +* \param deframerCfg a pointer to an empty adi_fpga9025_DeframerCfg_t structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204CDeframerCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_DeframerSel_e deframerSel, + adi_fpga9025_DeframerCfg_t* deframerCfg); + +/** +* \brief JESD204C implementation for adi_fpga9025_FramerCfgSet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9025_FramerSel_e enum values +* \param framerCfg pointer to an adi_fpga9025_FramerCfg_t structure that contains the deserializer configuration settings +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204CFramerCfgSet(adi_fpga9025_Device_t* device, + uint32_t framerSelMask, + adi_fpga9025_FramerCfg_t* framerCfg); + +/** +* \brief JESD204C implementation for adi_fpga9025_FramerCfgGet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSel an adi_fpga9025_FramerSel_e enum value selecting a single framer +* \param framerCfg pointer to an empty adi_fpga9025_FramerCfg_t structure +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204CFramerCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_FramerSel_e framerSel, + adi_fpga9025_FramerCfg_t* framerCfg); + +/** +* \brief JESD204C helper function for FramerResetGet. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9025_FramerSel_e enum values +* \param resetBits uint8_t pointer to reset bits of the selected deframers which will correspond with their adi_fpga9025_FramerSel_e bit locations +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204CFramerResetGet(adi_fpga9025_Device_t* device, + uint32_t framerSelMask, + uint8_t* resetBits); + +/** +* \brief JESD204C helper function for FramerReset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9025_FramerSel_e enum values +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204CFramerReset(adi_fpga9025_Device_t* device, + uint8_t framerSelMask); + +/** +* \brief JESD204C helper function for DeframerReset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9025_DeframerSel_e enum values +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204CDeframerReset(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask); + +/** +* \brief JESD204C helper function for DeframerDisable. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9025_DeframerSel_e enum values +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204CDeframerDisable(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask); + +/** +* \brief JESD204C helper function for FramerDisable. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9025_FramerSel_e enum values +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204CFramerDisable(adi_fpga9025_Device_t* device, + uint8_t framerSelMask); + +/** +* \brief JESD204C helper function for DeframerStatusGet. The status bit for each link will be a logical +* and of mb_lock & sync_header_lock bitfield values. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9025_DeframerSel_e enum values +* \param status uint8_t pointer for the Sync status bits of the selected deframers that will correspond with their adi_fpga9025_DeframerSel_e bit locations +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_Jesd204CDeframerStatusGet(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask, + uint8_t* status); + +#ifdef __cplusplus +} +#endif + +#endif /* _FPGA9025_JESD_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_tdd.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_tdd.h new file mode 100644 index 0000000..085fb0e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_tdd.h @@ -0,0 +1,71 @@ +/** +* \file fpga9025_tdd.h +* \brief Contains private tdd related function prototypes for fpga9025_tdd.h +* +* FPGA9025 API Version: 6.4.0.14 +*/ +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _FPGA9025_TDD_H_ +#define _FPGA9025_TDD_H_ + +#include "adi_fpga9025_user.h" +#include "adi_fpga9025_tdd_types.h" +#include "adi_fpga9025_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \brief Initializes the FPGA TDD Enable Control module with the values passed in from the structure +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param module is a pointer to structure type adi_fpga_TddTiming_t which contains all +* TDD Enable Control module parameters. This structure must be pre-loaded before use and is checked for a +* null pointer if not initialized and an error will be thrown. +* \param baseAddress The base address of the module to be loaded in FPGA memory. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_TddEnableControlModuleSet(adi_fpga9025_Device_t* device, + adi_fpga_TddTiming_t* module, + uint32_t baseAddress); + +/** +* \brief Reads the FPGA TDD Enable Control module into the structure passed into the function +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param module is a pointer to an empty structure type adi_fpga_TddTiming_t. +* \param baseAddress The base address of the module to be loaded in FPGA memory. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_TddEnableControlModuleGet(adi_fpga9025_Device_t* device, + adi_fpga_TddTiming_t* module, + uint32_t baseAddress); + +#ifdef __cplusplus +} +#endif + +#endif /* _FPGA9025_TDD_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_utilities.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_utilities.h new file mode 100644 index 0000000..fb73d8d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/include/fpga9025_utilities.h @@ -0,0 +1,98 @@ +/** +* \file fpga9025_jesd.h +* \brief Contains private JESD related function prototypes for fpga9025_jesd.c +* +* FPGA9025 API Version: 6.4.0.14 +*/ +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _FPGA9025_UTILITIES_H_ +#define _FPGA9025_UTILITIES_H_ + +#include "adi_fpga9025_user.h" +#include "adi_fpga9025_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \brief Configures the Qpll DRP registers based on the clock configuration. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param refClk_kHz The input clock rate in kHz +* \param qpllVco_kHz Frequency of the QPLL Vco +* \param qpllDivideRatio 1 = Full rate, 0 = half rate +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_QpllDrpCfg(adi_fpga9025_Device_t* device, + const uint32_t refClk_kHz, + const uint32_t qpllVcoOut_kHz, + const uint8_t qpllDivideRatio); + +/** +* \brief Configures the 204B & 204C Serializer DRP registers based on the clock configuration for the specified lane. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param refClk_kHz The input clock rate in kHz +* \param laneRate The lane rate for fpgaLane +* \param qpllVco_kHz Frequency of the QPLL Vco +* \param fpgaLane The FPGA lane to apply the settings for +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_SerializerDrpCfg(adi_fpga9025_Device_t* device, + const uint32_t refClk_kHz, + const uint32_t laneRate, + const uint32_t qpllVcoOut_kHz, + const uint8_t fpgaLane); + +/** +* \brief Configures the 204B Deserializer DRP registers based on the clock configuration for the specified lane. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param refClk_kHz The input clock rate in kHz +* \param laneRate The lane rate for fpgaLane +* \param qpllVco_kHz Frequency of the QPLL Vco +* \param fpgaLane The FPGA lane to apply the settings for +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_DeserializerDrpCfg(adi_fpga9025_Device_t* device, + const uint32_t refClk_kHz, + const uint32_t laneRate, + const uint32_t qpllVcoOut_kHz, + const uint8_t fpgaLane); + +#ifdef __cplusplus +} +#endif + +#endif /* _FPGA9025_UTILITIES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_ads9v2.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_ads9v2.c new file mode 100644 index 0000000..abccb1d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_ads9v2.c @@ -0,0 +1,3787 @@ +/** + * \file fpga9025_bf_ads9v2.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_ads9v2.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief AD9528 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2Ad9528ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2Ad9528ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2Ad9528ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief AD9528 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2Ad9528ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2Ad9528ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief AD9576 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2Ad9576ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2Ad9576ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2Ad9576ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief AD9576 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2Ad9576ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2Ad9576ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief External Trigger 0 Direction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrig0DirBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2ExtTrig0DirBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrig0DirBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x18), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External Trigger 0 Direction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrig0DirBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrig0DirBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief External Trigger 0 Output Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrig0OutputSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2ExtTrig0OutputSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrig0OutputSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x18), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External Trigger 0 Output Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrig0OutputSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrig0OutputSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief External Trigger 1 Direction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrig1DirBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2ExtTrig1DirBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrig1DirBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x18), + (uint32_t)bfValue, + 0x100, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External Trigger 1 Direction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrig1DirBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrig1DirBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0x100, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief External Trigger 1 Output Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrig1OutputSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2ExtTrig1OutputSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrig1OutputSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x18), + (uint32_t)bfValue, + 0x7000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External Trigger 1 Output Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrig1OutputSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrig1OutputSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0x7000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief External Trigger 2 Direction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrig2DirBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2ExtTrig2DirBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrig2DirBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x18), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External Trigger 2 Direction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrig2DirBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrig2DirBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief External Trigger 2 Output Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrig2OutputSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2ExtTrig2OutputSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrig2OutputSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x18), + (uint32_t)bfValue, + 0x700000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External Trigger 2 Output Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrig2OutputSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrig2OutputSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0x700000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief External Trigger 3 Direction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrig3DirBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2ExtTrig3DirBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrig3DirBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x18), + (uint32_t)bfValue, + 0x1000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External Trigger 3 Direction + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrig3DirBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrig3DirBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0x1000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief External Trigger 3 Output Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrig3OutputSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2ExtTrig3OutputSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrig3OutputSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x18), + (uint32_t)bfValue, + 0x70000000, + 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External Trigger 3 Output Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrig3OutputSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrig3OutputSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0x70000000, + 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief External Trigger Source for Receive Data Path 00 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrigRxdp00CtrlSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2ExtTrigRxdp00CtrlSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrigRxdp00CtrlSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x1C), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External Trigger Source for Receive Data Path 00 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrigRxdp00CtrlSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrigRxdp00CtrlSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief External Trigger Source for Receive Data Path 01 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrigRxdp01CtrlSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2ExtTrigRxdp01CtrlSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrigRxdp01CtrlSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x1C), + (uint32_t)bfValue, + 0x300, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External Trigger Source for Receive Data Path 01 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrigRxdp01CtrlSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrigRxdp01CtrlSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x300, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief External Trigger Source for Receive Data Path 02 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrigRxdp02CtrlSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2ExtTrigRxdp02CtrlSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrigRxdp02CtrlSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x1C), + (uint32_t)bfValue, + 0x3000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External Trigger Source for Receive Data Path 02 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrigRxdp02CtrlSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrigRxdp02CtrlSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x3000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief External Trigger Source for TDD State Machine Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrigTddCtrlSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2ExtTrigTddCtrlSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrigTddCtrlSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x1C), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External Trigger Source for TDD State Machine Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrigTddCtrlSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrigTddCtrlSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief External Trigger Source for Transmit Data Path 00 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrigTxdp00CtrlSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2ExtTrigTxdp00CtrlSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrigTxdp00CtrlSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x1C), + (uint32_t)bfValue, + 0x30000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External Trigger Source for Transmit Data Path 00 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrigTxdp00CtrlSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrigTxdp00CtrlSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x30000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief External Trigger Source for Transmit Data Path 01 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrigTxdp01CtrlSrcBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2ExtTrigTxdp01CtrlSrcBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrigTxdp01CtrlSrcBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x1C), + (uint32_t)bfValue, + 0x300000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External Trigger Source for Transmit Data Path 01 Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2ExtTrigTxdp01CtrlSrcBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2ExtTrigTxdp01CtrlSrcBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x300000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Global Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2GlobalResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2GlobalResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2GlobalResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Global Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2GlobalResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2GlobalResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief LED Blinking Mode Blink Duration + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2LedBlinkDurationBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2LedBlinkDurationBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2LedBlinkDurationBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0xC), + (uint32_t)bfValue, + 0xFFFF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief LED Blinking Mode Blink Duration + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2LedBlinkDurationBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2LedBlinkDurationBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0xFFFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief LED Mode Change Delay in Milliseconds + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2LedDelayToModeChangeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2LedDelayToModeChangeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2LedDelayToModeChangeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0xFFFF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief LED Mode Change Delay in Milliseconds + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2LedDelayToModeChangeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2LedDelayToModeChangeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0xFFFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief LED Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2LedMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 63U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2LedMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2LedMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x10), + (uint32_t)bfValue, + 0x3F00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief LED Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2LedMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2LedMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0x3F00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief LED Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2LedModeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2LedModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2LedModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief LED Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2LedModeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2LedModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief LED Blinking Mode Number of Blinks + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2LedNumBlinksBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2LedNumBlinksBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2LedNumBlinksBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0xC), + (uint32_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief LED Blinking Mode Number of Blinks + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2LedNumBlinksBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2LedNumBlinksBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief LED Software Define Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2LedSwDefinedValueBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 63U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2LedSwDefinedValueBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2LedSwDefinedValueBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x10), + (uint32_t)bfValue, + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief LED Software Define Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2LedSwDefinedValueBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2LedSwDefinedValueBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0x3F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Select Line for MGT Reference Clock Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2MgtRefclkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2MgtRefclkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2MgtRefclkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x14), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Select Line for MGT Reference Clock Source + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2MgtRefclkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2MgtRefclkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x14), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief PCA9545 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2Pca9545ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Ads9v2Pca9545ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2Pca9545ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief PCA9545 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2Pca9545ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2Pca9545ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2VersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2VersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAds9v2ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Ads9v2VersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAds9v2ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9V2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Ads9v2VersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_ads9v2.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_axi_adrv9025.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_axi_adrv9025.c new file mode 100644 index 0000000..9f37ef0 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_axi_adrv9025.c @@ -0,0 +1,4788 @@ +/** + * \file fpga9025_bf_axi_adrv9025.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_axi_adrv9025.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief AD9528 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025Ad9528ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025Ad9528ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025Ad9528ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief AD9528 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025Ad9528ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025Ad9528ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief ADRV9025 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025Adrv9025ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025Adrv9025ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025Adrv9025ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief ADRV9025 Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025Adrv9025ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025Adrv9025ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Identifies as ADRV9025 on ADS9v2 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025DesignIdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025DesignIdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GP Interrupt 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpInterrupt0BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpInterrupt0BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x34), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GP Interrupt 0 Detection Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpInterrupt0DetCounterBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpInterrupt0DetCounterBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x38), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief GP Interrupt 0 Detection Edge or Level + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpInterrupt0DetEdgeLevelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpInterrupt0DetEdgeLevelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpInterrupt0DetEdgeLevelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x30), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GP Interrupt 0 Detection Edge or Level + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpInterrupt0DetEdgeLevelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpInterrupt0DetEdgeLevelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x30), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GP Interrupt 0 Detection Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpInterrupt0DetPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpInterrupt0DetPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpInterrupt0DetPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x30), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GP Interrupt 0 Detection Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpInterrupt0DetPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpInterrupt0DetPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x30), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GP Interrupt 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpInterrupt1BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpInterrupt1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x44), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GP Interrupt 1 Detection Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpInterrupt1DetCounterBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpInterrupt1DetCounterBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x48), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief GP Interrupt 1 Detection Edge or Level + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpInterrupt1DetEdgeLevelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpInterrupt1DetEdgeLevelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpInterrupt1DetEdgeLevelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x40), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GP Interrupt 1 Detection Edge or Level + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpInterrupt1DetEdgeLevelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpInterrupt1DetEdgeLevelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x40), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GP Interrupt 1 Detection Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpInterrupt1DetPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpInterrupt1DetPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpInterrupt1DetPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x40), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GP Interrupt 1 Detection Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpInterrupt1DetPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpInterrupt1DetPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x40), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Control Enable ADRV9025 JTAG + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioEnArmJtagBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioEnArmJtagBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioEnArmJtagBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x100), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Control Enable ADRV9025 JTAG + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioEnArmJtagBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioEnArmJtagBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x100), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Control Enable SPI2 Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioEnSpi2BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioEnSpi2BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioEnSpi2BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x100), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Control Enable SPI2 Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioEnSpi2BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioEnSpi2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x100), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Control Enable TX to ORX Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioEnTxToOrxBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 524287U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioEnTxToOrxBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioEnTxToOrxBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x100), + (uint32_t)bfValue, + 0x7FFFF000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Control Enable TX to ORX Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioEnTxToOrxBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioEnTxToOrxBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x100), + &rxBfData[0], + 0x7FFFF000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Input + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioInputBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioInputBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x104), + &rxBfData[0], + 0x7FFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Output + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioOutputBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 524287U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioOutputBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioOutputBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x108), + (uint32_t)bfValue, + 0x7FFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Output + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioOutputBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioOutputBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x108), + &rxBfData[0], + 0x7FFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Selection for TX1 to ORX1 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioSelTx1ToOrx1BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioSelTx1ToOrx1BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioSelTx1ToOrx1BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x80), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Selection for TX1 to ORX1 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioSelTx1ToOrx1BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioSelTx1ToOrx1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Selection for TX1 to ORX2 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioSelTx1ToOrx2BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioSelTx1ToOrx2BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioSelTx1ToOrx2BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x80), + (uint32_t)bfValue, + 0x1F00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Selection for TX1 to ORX2 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioSelTx1ToOrx2BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioSelTx1ToOrx2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80), + &rxBfData[0], + 0x1F00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Selection for TX2 to ORX1 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioSelTx2ToOrx1BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioSelTx2ToOrx1BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioSelTx2ToOrx1BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x80), + (uint32_t)bfValue, + 0x1F0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Selection for TX2 to ORX1 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioSelTx2ToOrx1BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioSelTx2ToOrx1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80), + &rxBfData[0], + 0x1F0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Selection for TX2 to ORX2 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioSelTx2ToOrx2BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioSelTx2ToOrx2BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioSelTx2ToOrx2BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x80), + (uint32_t)bfValue, + 0x1F000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Selection for TX2 to ORX2 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioSelTx2ToOrx2BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioSelTx2ToOrx2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80), + &rxBfData[0], + 0x1F000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Selection for TX3 to ORX3 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioSelTx3ToOrx3BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioSelTx3ToOrx3BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioSelTx3ToOrx3BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x84), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Selection for TX3 to ORX3 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioSelTx3ToOrx3BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioSelTx3ToOrx3BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x84), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Selection for TX3 to ORX4 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioSelTx3ToOrx4BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioSelTx3ToOrx4BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioSelTx3ToOrx4BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x84), + (uint32_t)bfValue, + 0x1F00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Selection for TX3 to ORX4 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioSelTx3ToOrx4BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioSelTx3ToOrx4BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x84), + &rxBfData[0], + 0x1F00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Selection for TX4 to ORX3 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioSelTx4ToOrx3BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioSelTx4ToOrx3BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioSelTx4ToOrx3BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x84), + (uint32_t)bfValue, + 0x1F0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Selection for TX4 to ORX3 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioSelTx4ToOrx3BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioSelTx4ToOrx3BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x84), + &rxBfData[0], + 0x1F0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Selection for TX4 to ORX4 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioSelTx4ToOrx4BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioSelTx4ToOrx4BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioSelTx4ToOrx4BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x84), + (uint32_t)bfValue, + 0x1F000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Selection for TX4 to ORX4 Mapping + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioSelTx4ToOrx4BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioSelTx4ToOrx4BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x84), + &rxBfData[0], + 0x1F000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Trigger Source for RXDP 00 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcRxdp00BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioTriggerSrcRxdp00BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioTriggerSrcRxdp00BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x20), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Trigger Source for RXDP 00 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcRxdp00BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioTriggerSrcRxdp00BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Trigger Source for RXDP 01 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcRxdp01BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioTriggerSrcRxdp01BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioTriggerSrcRxdp01BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x20), + (uint32_t)bfValue, + 0x1F00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Trigger Source for RXDP 01 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcRxdp01BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioTriggerSrcRxdp01BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x1F00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Trigger Source for RXDP 02 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcRxdp02BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioTriggerSrcRxdp02BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioTriggerSrcRxdp02BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x20), + (uint32_t)bfValue, + 0x1F0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Trigger Source for RXDP 02 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcRxdp02BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioTriggerSrcRxdp02BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x1F0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Trigger Source for TXDP 00 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcTxdp00BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioTriggerSrcTxdp00BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioTriggerSrcTxdp00BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x24), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Trigger Source for TXDP 00 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcTxdp00BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioTriggerSrcTxdp00BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x24), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Trigger Source for TXDP 01 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcTxdp01BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioTriggerSrcTxdp01BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioTriggerSrcTxdp01BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x24), + (uint32_t)bfValue, + 0x1F00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Trigger Source for TXDP 01 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioTriggerSrcTxdp01BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioTriggerSrcTxdp01BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x24), + &rxBfData[0], + 0x1F00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief GPIO Tristate + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioTristateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 524287U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025GpioTristateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioTristateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x10C), + (uint32_t)bfValue, + 0x7FFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief GPIO Tristate + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025GpioTristateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025GpioTristateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x10C), + &rxBfData[0], + 0x7FFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Scratch Pad + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025ScratchPadBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025ScratchPadBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025ScratchPadBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x8), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Scratch Pad + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025ScratchPadBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025ScratchPadBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Test Pin Input + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025TestInputBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025TestInputBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025TestInputBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x10), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Test Pin Input + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025TestInputBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025TestInputBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Test Pin Output + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025TestOutputBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025TestOutputBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025TestOutputBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x10), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Test Pin Output + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025TestOutputBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025TestOutputBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Test Pin Tristate + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025TestTristateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdrv9025TestTristateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025TestTristateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x10), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Test Pin Tristate + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025TestTristateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025TestTristateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025VersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025VersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdrv9025ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdrv9025VersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdrv9025ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADRV9025)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdrv9025VersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_axi_adrv9025.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_axi_adv_spi.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_axi_adv_spi.c new file mode 100644 index 0000000..8d8cbd9 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_axi_adv_spi.c @@ -0,0 +1,5807 @@ +/** + * \file fpga9025_bf_axi_adv_spi.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_axi_adv_spi.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Advanced Feature Three Wire Tristate Point + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiAdvFeat3wireTriPointBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiAdvFeat3wireTriPointBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiAdvFeat3wireTriPointBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_AxiAdvSpiAdvFeat3wireTriPointBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x80 + channelId * 4), + (uint32_t)bfValue, + 0xFF00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Advanced Feature Three Wire Tristate Point + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiAdvFeat3wireTriPointBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiAdvFeat3wireTriPointBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_AxiAdvSpiAdvFeat3wireTriPointBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80 + channelId * 4), + &rxBfData[0], + 0xFF00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Advanced Feature Clock Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiAdvFeatClockDivBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiAdvFeatClockDivBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiAdvFeatClockDivBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_AxiAdvSpiAdvFeatClockDivBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x80 + channelId * 4), + (uint32_t)bfValue, + 0xFFFF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Advanced Feature Clock Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiAdvFeatClockDivBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiAdvFeatClockDivBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_AxiAdvSpiAdvFeatClockDivBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80 + channelId * 4), + &rxBfData[0], + 0xFFFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Advanced Feature Clock Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiAdvFeatCphaBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiAdvFeatCphaBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiAdvFeatCphaBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_AxiAdvSpiAdvFeatCphaBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x80 + channelId * 4), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Advanced Feature Clock Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiAdvFeatCphaBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiAdvFeatCphaBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_AxiAdvSpiAdvFeatCphaBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80 + channelId * 4), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Advanced Feature Clock Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiAdvFeatCpolBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiAdvFeatCpolBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiAdvFeatCpolBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_AxiAdvSpiAdvFeatCpolBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x80 + channelId * 4), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Advanced Feature Clock Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiAdvFeatCpolBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiAdvFeatCpolBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_AxiAdvSpiAdvFeatCpolBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80 + channelId * 4), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Advanced Feature Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiAdvFeatEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiAdvFeatEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiAdvFeatEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_AxiAdvSpiAdvFeatEnableBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x80 + channelId * 4), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Advanced Feature Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiAdvFeatEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiAdvFeatEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_AxiAdvSpiAdvFeatEnableBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80 + channelId * 4), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Advanced Feature Four Wire Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiAdvFeatFourWireBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiAdvFeatFourWireBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiAdvFeatFourWireBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_AxiAdvSpiAdvFeatFourWireBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x80 + channelId * 4), + (uint32_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Advanced Feature Four Wire Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiAdvFeatFourWireBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiAdvFeatFourWireBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_AxiAdvSpiAdvFeatFourWireBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80 + channelId * 4), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Advanced Feature LSB First + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiAdvFeatLsbFirstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiAdvFeatLsbFirstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiAdvFeatLsbFirstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_AxiAdvSpiAdvFeatLsbFirstBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x80 + channelId * 4), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Advanced Feature LSB First + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiAdvFeatLsbFirstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiAdvFeatLsbFirstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_AxiAdvSpiAdvFeatLsbFirstBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80 + channelId * 4), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Advanced Feature MISO Sample Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiAdvFeatMisoSampleSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiAdvFeatMisoSampleSlipBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiAdvFeatMisoSampleSlipBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_AxiAdvSpiAdvFeatMisoSampleSlipBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x80 + channelId * 4), + (uint32_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Advanced Feature MISO Sample Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiAdvFeatMisoSampleSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiAdvFeatMisoSampleSlipBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) && + (channelId != 0x9) && + (channelId != 0xA) && + (channelId != 0xB) && + (channelId != 0xC) && + (channelId != 0xD) && + (channelId != 0xE) && + (channelId != 0xF) && + (channelId != 0x10) && + (channelId != 0x11) && + (channelId != 0x12) && + (channelId != 0x13) && + (channelId != 0x14) && + (channelId != 0x15) && + (channelId != 0x16) && + (channelId != 0x17) && + (channelId != 0x18) && + (channelId != 0x19) && + (channelId != 0x1A) && + (channelId != 0x1B) && + (channelId != 0x1C) && + (channelId != 0x1D) && + (channelId != 0x1E) && + (channelId != 0x1F) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_AxiAdvSpiAdvFeatMisoSampleSlipBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80 + channelId * 4), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiCphaBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiCphaBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiCphaBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x60), + (uint32_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiCphaBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiCphaBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x60), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiCpolBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiCpolBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiCpolBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x60), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiCpolBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiCpolBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x60), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Data Receive Register/FIFO Full + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiDrrFullBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiDrrFullBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiDrrFullBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x20), + (uint32_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Data Receive Register/FIFO Full + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiDrrFullBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiDrrFullBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Data Receive Register/FIFO Full IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiDrrFullIenBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiDrrFullIenBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiDrrFullIenBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x28), + (uint32_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Data Receive Register/FIFO Full IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiDrrFullIenBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiDrrFullIenBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x28), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Data Receive Register/FIFO Overrun + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiDrrOverrunBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiDrrOverrunBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiDrrOverrunBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x20), + (uint32_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Data Receive Register/FIFO Overrun + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiDrrOverrunBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiDrrOverrunBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Data Receive Register/FIFO Overrun IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiDrrOverrunIenBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiDrrOverrunIenBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiDrrOverrunIenBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x28), + (uint32_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Data Receive Register/FIFO Overrun IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiDrrOverrunIenBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiDrrOverrunIenBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x28), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Data Transmit Register/FIFO Empty + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiDtrEmptyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiDtrEmptyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiDtrEmptyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x20), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Data Transmit Register/FIFO Empty + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiDtrEmptyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiDtrEmptyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Data Transmit Register/FIFO Empty IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiDtrEmptyIenBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiDtrEmptyIenBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiDtrEmptyIenBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x28), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Data Transmit Register/FIFO Empty IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiDtrEmptyIenBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiDtrEmptyIenBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x28), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Global Interrupt Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiGieBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiGieBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiGieBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x1C), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Global Interrupt Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiGieBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiGieBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Loopback Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiLoopBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiLoopBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiLoopBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x60), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Loopback Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiLoopBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiLoopBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x60), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief LSB First + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiLsbFirstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiLsbFirstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiLsbFirstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x60), + (uint32_t)bfValue, + 0x200, + 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief LSB First + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiLsbFirstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiLsbFirstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x60), + &rxBfData[0], + 0x200, + 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Manual Slave Select Assertion Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiManSsEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiManSsEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiManSsEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x60), + (uint32_t)bfValue, + 0x80, + 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Manual Slave Select Assertion Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiManSsEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiManSsEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x60), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Master Mode Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiMasterBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiMasterBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiMasterBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x60), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Master Mode Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiMasterBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiMasterBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x60), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Mode Fault Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiModfBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiModfBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Mode Fault Error Flag + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiModfFlagBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiModfFlagBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Mode Fault Error IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiModfIenBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiModfIenBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiModfIenBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x28), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Mode Fault Error IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiModfIenBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiModfIenBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x28), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Master Transaction Inhibit + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiMstrInhibitBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiMstrInhibitBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiMstrInhibitBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x60), + (uint32_t)bfValue, + 0x100, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Master Transaction Inhibit + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiMstrInhibitBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiMstrInhibitBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x60), + &rxBfData[0], + 0x100, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x40), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Receive Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiRxDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiRxDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x6C), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Receive Empty Flag + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiRxEmptyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiRxEmptyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Receive FIFO Occupancy + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiRxFifoOccupancyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiRxFifoOccupancyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x78), + &rxBfData[0], + 0x1FF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief RX FIFO Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiRxFifoResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiRxFifoResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiRxFifoResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x60), + (uint32_t)bfValue, + 0x40, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Receive Full Flag + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiRxFullBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiRxFullBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Slave Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiSlaveSelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiSlaveSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiSlaveSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x70), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Slave Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiSlaveSelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiSlaveSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x70), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief SPI System Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiSpeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiSpeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiSpeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x60), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief SPI System Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiSpeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiSpeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x60), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Transmit Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiTxDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiTxDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiTxDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x68), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Transmit Empty Flag + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiTxEmptyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiTxEmptyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Transmit FIFO Half Empty + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiTxFifoHalfEmptyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiTxFifoHalfEmptyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiTxFifoHalfEmptyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x20), + (uint32_t)bfValue, + 0x40, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Transmit FIFO Half Empty + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiTxFifoHalfEmptyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiTxFifoHalfEmptyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Transmit FIFO Half Empty IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiTxFifoHalfEmptyIenBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiTxFifoHalfEmptyIenBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiTxFifoHalfEmptyIenBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x28), + (uint32_t)bfValue, + 0x40, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Transmit FIFO Half Empty IRQ Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiTxFifoHalfEmptyIenBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiTxFifoHalfEmptyIenBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x28), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Transmit FIFO Occupancy + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiTxFifoOccupancyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiTxFifoOccupancyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x74), + &rxBfData[0], + 0x1FF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief TX FIFO Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiTxFifoResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiAdvSpiTxFifoResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiTxFifoResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x60), + (uint32_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Transmit Full Flag + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiTxFullBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiTxFullBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiAdvSpiChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiAdvSpiModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiAdvSpiChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_ADV_SPI)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiAdvSpiModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_axi_adv_spi.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_axi_hmc.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_axi_hmc.c new file mode 100644 index 0000000..19895d9 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_axi_hmc.c @@ -0,0 +1,1229 @@ +/** + * \file fpga9025_bf_axi_hmc.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_axi_hmc.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief 1G cpu paging index + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcAxilitePageBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiHmcAxilitePageBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcAxilitePageBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x20), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief 1G cpu paging index + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcAxilitePageBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcAxilitePageBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Indicates device reset status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcHmc0DevRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcHmc0DevRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Indicates device errors + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcHmc0FerrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcHmc0FerrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Indicates mmcm reset status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcHmc0MmcmRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcHmc0MmcmRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Indicates phy reset status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcHmc0PhyRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcHmc0PhyRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Indicates xcvr reset status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcHmc0XcvrRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcHmc0XcvrRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Indicates device reset status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcHmc1DevRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcHmc1DevRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Indicates device errors + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcHmc1FerrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcHmc1FerrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0xC, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Indicates mmcm reset status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcHmc1MmcmRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcHmc1MmcmRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Indicates phy reset status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcHmc1PhyRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcHmc1PhyRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Indicates xcvr reset status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcHmc1XcvrRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcHmc1XcvrRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief General purpose scratch register + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcScratchBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiHmcScratchBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcScratchBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x8), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief General purpose scratch register + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcScratchBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcScratchBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief General purpose timer register + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcTimerBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_AxiHmcTimerBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcTimerBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x24), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief General purpose timer register + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcTimerBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcTimerBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x24), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Ip core version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfAxiHmcChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_AxiHmcVersionBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfAxiHmcChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_AXI_HMC)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_AxiHmcVersionBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_axi_hmc.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_clock_freq_detect.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_clock_freq_detect.c new file mode 100644 index 0000000..c53cb82 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_clock_freq_detect.c @@ -0,0 +1,1447 @@ +/** + * \file fpga9025_bf_clock_freq_detect.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_clock_freq_detect.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Clock Frequency 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectClockFreq0BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectClockFreq0BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Frequency 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectClockFreq1BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectClockFreq1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x14), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Frequency 10 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectClockFreq10BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectClockFreq10BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x38), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Frequency 11 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectClockFreq11BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectClockFreq11BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x3C), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Frequency 12 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectClockFreq12BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectClockFreq12BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x40), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Frequency 13 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectClockFreq13BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectClockFreq13BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x44), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Frequency 14 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectClockFreq14BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectClockFreq14BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x48), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Frequency 15 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectClockFreq15BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectClockFreq15BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x4C), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Frequency 2 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectClockFreq2BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectClockFreq2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Frequency 3 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectClockFreq3BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectClockFreq3BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Frequency 4 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectClockFreq4BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectClockFreq4BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Frequency 5 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectClockFreq5BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectClockFreq5BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x24), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Frequency 6 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectClockFreq6BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectClockFreq6BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x28), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Frequency 7 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectClockFreq7BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectClockFreq7BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x2C), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Frequency 8 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectClockFreq8BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectClockFreq8BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x30), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Frequency 9 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectClockFreq9BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectClockFreq9BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x34), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Local Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectLocalResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_ClockFreqDetectLocalResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectLocalResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Local Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectLocalResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectLocalResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfClockFreqDetectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_ClockFreqDetectModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfClockFreqDetectChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR) && + (baseAddr != FPGA9025_BF_CLOCK_FREQUENCY_DETECTOR_DEBUG)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_ClockFreqDetectModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_clock_freq_detect.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_dp_capture_control.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_dp_capture_control.c new file mode 100644 index 0000000..c12dacd --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_dp_capture_control.c @@ -0,0 +1,605 @@ +/** + * \file fpga9025_bf_dp_capture_control.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_dp_capture_control.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Data Path Active + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpCaptureControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpCaptureControlDatapathActiveBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpCaptureControlDatapathActiveBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_CAPTURE_CONTROL_RX) && + (baseAddr != FPGA9025_BF_DP_CAPTURE_CONTROL_TX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpCaptureControlDatapathActiveBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Data Path Active + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpCaptureControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpCaptureControlDatapathActiveBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_CAPTURE_CONTROL_RX) && + (baseAddr != FPGA9025_BF_DP_CAPTURE_CONTROL_TX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpCaptureControlDatapathActiveBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpCaptureControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpCaptureControlModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_CAPTURE_CONTROL_RX) && + (baseAddr != FPGA9025_BF_DP_CAPTURE_CONTROL_TX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpCaptureControlModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpCaptureControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpCaptureControlModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpCaptureControlChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_CAPTURE_CONTROL_RX) && + (baseAddr != FPGA9025_BF_DP_CAPTURE_CONTROL_TX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpCaptureControlModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Pass Token + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpCaptureControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpCaptureControlPassTokenBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpCaptureControlPassTokenBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_CAPTURE_CONTROL_RX) && + (baseAddr != FPGA9025_BF_DP_CAPTURE_CONTROL_TX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpCaptureControlPassTokenBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Pass Token + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpCaptureControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpCaptureControlPassTokenBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_CAPTURE_CONTROL_RX) && + (baseAddr != FPGA9025_BF_DP_CAPTURE_CONTROL_TX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpCaptureControlPassTokenBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpCaptureControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpCaptureControlResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpCaptureControlResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_CAPTURE_CONTROL_RX) && + (baseAddr != FPGA9025_BF_DP_CAPTURE_CONTROL_TX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpCaptureControlResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpCaptureControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpCaptureControlResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpCaptureControlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_CAPTURE_CONTROL_RX) && + (baseAddr != FPGA9025_BF_DP_CAPTURE_CONTROL_TX)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpCaptureControlResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_dp_capture_control.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_dp_rx_dma.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_dp_rx_dma.c new file mode 100644 index 0000000..5753033 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_dp_rx_dma.c @@ -0,0 +1,1933 @@ +/** + * \file fpga9025_bf_dp_rx_dma.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_dp_rx_dma.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Transfer Active + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaActiveBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaActiveBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Transfer Complete + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaCompleteBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaCompleteBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Enable Enhanced Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaEnableEnhancedModeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpRxDmaEnableEnhancedModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaEnableEnhancedModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Enable Enhanced Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaEnableEnhancedModeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaEnableEnhancedModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Enable Scatter Gather Transfer + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaEnableSgBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpRxDmaEnableSgBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaEnableSgBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Enable Scatter Gather Transfer + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaEnableSgBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaEnableSgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Halt Complete + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaHaltCompleteBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaHaltCompleteBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Transfer Length + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaLengthBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpRxDmaLengthBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaLengthBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x18), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Transfer Length + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaLengthBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaLengthBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Overflow + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaOverflowBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaOverflowBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpRxDmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Run Stop + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaRunStopBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpRxDmaRunStopBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaRunStopBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Run Stop + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaRunStopBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaRunStopBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Scatter-Gather First Descriptor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaSgFirstDescriptorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpRxDmaSgFirstDescriptorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaSgFirstDescriptorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x20), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Scatter-Gather First Descriptor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaSgFirstDescriptorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaSgFirstDescriptorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Scatter-Gather Last Descriptor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaSgLastDescriptorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpRxDmaSgLastDescriptorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaSgLastDescriptorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x28), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Scatter-Gather Last Descriptor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaSgLastDescriptorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaSgLastDescriptorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x28), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Simple Transfer Start Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaSimpleStartAddrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpRxDmaSimpleStartAddrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaSimpleStartAddrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x10), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Simple Transfer Start Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaSimpleStartAddrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaSimpleStartAddrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Simple Transfer Start Address Most Significant Word + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaSimpleStartAddrMswBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpRxDmaSimpleStartAddrMswBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaSimpleStartAddrMswBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x14), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Simple Transfer Start Address Most Significant Word + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaSimpleStartAddrMswBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaSimpleStartAddrMswBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x14), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Valid Data Width of Stream Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaValidDataWidthStreamBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpRxDmaValidDataWidthStreamBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaValidDataWidthStreamBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0xF00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Valid Data Width of Stream Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaValidDataWidthStreamBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaValidDataWidthStreamBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0xF00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpRxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpRxDmaVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpRxDmaChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_RX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_1) && + (baseAddr != FPGA9025_BF_DP_DMA_RX_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpRxDmaVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_dp_rx_dma.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_dp_tollgate.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_dp_tollgate.c new file mode 100644 index 0000000..733e5c7 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_dp_tollgate.c @@ -0,0 +1,773 @@ +/** + * \file fpga9025_bf_dp_tollgate.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_dp_tollgate.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Edge or Level Trigger + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTollgateEdgeLevelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTollgateEdgeLevelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTollgateEdgeLevelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0xC), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Edge or Level Trigger + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTollgateEdgeLevelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTollgateEdgeLevelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief High Rising or Low Falling + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTollgateHighRisingLowFallingBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTollgateHighRisingLowFallingBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTollgateHighRisingLowFallingBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x10), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief High Rising or Low Falling + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTollgateHighRisingLowFallingBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTollgateHighRisingLowFallingBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTollgateModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTollgateModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTollgateModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTollgateModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Reset Tollgate + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTollgateResetTollgateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTollgateResetTollgateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTollgateResetTollgateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Reset Tollgate + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTollgateResetTollgateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTollgateResetTollgateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Trigger Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTollgateTriggerSelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTollgateTriggerSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTollgateTriggerSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x8), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Trigger Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTollgateChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTollgateTriggerSelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTollgateChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_1) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_RX_2) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_0) && + (baseAddr != FPGA9025_BF_DP_TOLLGATE_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTollgateTriggerSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_dp_tollgate.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_dp_tx_dma.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_dp_tx_dma.c new file mode 100644 index 0000000..3c91d6e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_dp_tx_dma.c @@ -0,0 +1,2054 @@ +/** + * \file fpga9025_bf_dp_tx_dma.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_dp_tx_dma.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Transfer Active + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaActiveBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaActiveBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Transfer Complete + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaCompleteBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaCompleteBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Continuous Operation + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaContinuousBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTxDmaContinuousBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaContinuousBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Continuous Operation + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaContinuousBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaContinuousBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Enable Enhanced Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaEnableEnhancedModeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTxDmaEnableEnhancedModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaEnableEnhancedModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Enable Enhanced Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaEnableEnhancedModeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaEnableEnhancedModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Enable Scatter Gather Transfer + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaEnableSgBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTxDmaEnableSgBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaEnableSgBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Enable Scatter Gather Transfer + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaEnableSgBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaEnableSgBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Halt Complete + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaHaltCompleteBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaHaltCompleteBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Transfer Length + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaLengthBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTxDmaLengthBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaLengthBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x18), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Transfer Length + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaLengthBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaLengthBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTxDmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Run Stop + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaRunStopBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTxDmaRunStopBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaRunStopBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Run Stop + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaRunStopBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaRunStopBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Scatter-Gather Last Descriptor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaSgLastDescriptorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTxDmaSgLastDescriptorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaSgLastDescriptorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x28), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Scatter-Gather Last Descriptor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaSgLastDescriptorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaSgLastDescriptorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x28), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Simple Transfer Start Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaSimpleStartAddrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTxDmaSimpleStartAddrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaSimpleStartAddrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x10), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Simple Transfer Start Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaSimpleStartAddrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaSimpleStartAddrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Simple Transfer Start Address Most Significant Word + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaSimpleStartAddrMswBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTxDmaSimpleStartAddrMswBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaSimpleStartAddrMswBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x14), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Simple Transfer Start Address Most Significant Word + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaSimpleStartAddrMswBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaSimpleStartAddrMswBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x14), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Scatter-Gather First Descriptor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaSqFirstDescriptorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTxDmaSqFirstDescriptorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaSqFirstDescriptorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x20), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Scatter-Gather First Descriptor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaSqFirstDescriptorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaSqFirstDescriptorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Underflow + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaUnderflowBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaUnderflowBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Valid Data Width of Stream Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaValidDataWidthStreamBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTxDmaValidDataWidthStreamBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaValidDataWidthStreamBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0xF00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Valid Data Width of Stream Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaValidDataWidthStreamBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaValidDataWidthStreamBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0xF00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxDmaChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxDmaVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxDmaChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_DMA_TX_0) && + (baseAddr != FPGA9025_BF_DP_DMA_TX_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxDmaVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_dp_tx_dma.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_dp_tx_sof_select.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_dp_tx_sof_select.c new file mode 100644 index 0000000..6dcd24e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_dp_tx_sof_select.c @@ -0,0 +1,597 @@ +/** + * \file fpga9025_bf_dp_tx_sof_select.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_dp_tx_sof_select.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxSofSelectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxSofSelectDelayBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 63U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTxSofSelectDelayBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TX_SOF_SELECT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxSofSelectDelayBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x3F00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxSofSelectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxSofSelectDelayBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TX_SOF_SELECT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxSofSelectDelayBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x3F00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxSofSelectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxSofSelectModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TX_SOF_SELECT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxSofSelectModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxSofSelectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxSofSelectModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxSofSelectChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TX_SOF_SELECT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxSofSelectModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxSofSelectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxSofSelectResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTxSofSelectResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TX_SOF_SELECT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxSofSelectResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxSofSelectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxSofSelectResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TX_SOF_SELECT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxSofSelectResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxSofSelectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxSofSelectSelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_DpTxSofSelectSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TX_SOF_SELECT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxSofSelectSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfDpTxSofSelectChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_DpTxSofSelectSelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfDpTxSofSelectChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_DP_TX_SOF_SELECT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_DpTxSofSelectSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_dp_tx_sof_select.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_hal.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_hal.c new file mode 100644 index 0000000..d3ad558 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_hal.c @@ -0,0 +1,774 @@ +/** +* \file fpga9025_bf_hal.c +* \brief Contains ADI Transceiver Hardware Abstraction functions +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +*/ + +/** +* Disclaimer Legal Disclaimer +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_common_hal.h" +#include "adi_fpga9025.h" +#include "adi_fpga9025_hal.h" +#include "adi_common_error.h" +#include "./../../private/include/fpga9025_bf_hal.h" + +/** +* \brief ensures the cache is empty. if not it writes the cache to the part. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* +* \retval ADRV9025_ Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_BfReadCacheInit(adi_fpga9025_Device_t* device) +{ + UNUSED_PARA(device); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + // uint16_t numRdBytes = 0; + // uint64_t rdData = 0; + // int32_t halError = ADI_COMMON_HAL_OK; + + // ADI_NULL_DEVICE_PTR_RETURN(device); + // + // ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + // + // if (device->common.cacheInfo.rdCacheState == ADRV9025_RD_BF_CACHE_ON) + // { + // recoveryAction = fpga9025_BfReadCacheFlush(device, &rdData, &numRdBytes); + // ADI_ERROR_RETURN(device->common.error.newAction); + // /* if Global Caching is being used, no further flushing should be performed + // * utill the user calls bf flush*/ + // } + return recoveryAction; +} + +/** +* \brief ensures the cache is empty. if not it writes the cache to the part. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_BfWriteCacheInit(adi_fpga9025_Device_t* device) +{ + UNUSED_PARA(device); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + // int32_t halError = ADI_COMMON_HAL_OK; + + // ADI_NULL_DEVICE_PTR_RETURN(device); + // + // ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + // + // /* skip cacheInit if Global level Cache is on.*/ + // if (device->common.cacheInfo.wrCacheState == ADRV9025_WR_BF_CACHE_ON) + // { + // /*Ensures the cache is empty if bitField Level Caching is on*/ + // + // recoveryAction = fpga9025_BfWriteCacheFlush(device); + // ADI_ERROR_RETURN(device->common.error.newAction); + // /* if using bitField level caching re-enable caching after each flush*/ + // device->common.cacheInfo.wrFlushEn = ADI_ENABLE; + // } + // else + // { + // /* disable flushing within the bitfield function when global + // caching is being used*/ + // device->common.cacheInfo.wrFlushEn = ADI_DISABLE; + // } + + return recoveryAction; +} + +/** +* \brief Used to read a register. +* Merges the write if merging is on +* Caches the write if caching is on, +* Immediately writes the value if caching is off. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep{ADRV9025_BF_WRCACHE_ARRAY_TRIP_SIZE} +* \dep{SPIARRAYSIZE} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param addr The address of the Register to read. +* \param regVal The value to be written to the register. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_BfRegisterWrite(adi_fpga9025_Device_t* device, + uint32_t addr, + uint32_t regVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + // + // //TODO add array size check + // + // if (device->common.cacheInfo.wrCacheState == ADRV9025_WR_GBL_MERGE_ON) + // { + // /* Write merging is on, so the cache is searched to see if address is in the cache*/ + // for (i = 0; i < device->common.cacheInfo.wrCacheIdx; i++) + // { + // /* The cache is packed in the form AABBMMDD + // where AA is MSB Addr, BB is the LSB addr, + // MM is the mask and DD is the Data */ + // //TODO fix this + // //if the address part of the cache word = wanted address + // if ((uint16_t)(device->common.cacheInfo.wrCache[i] >> SPI_ADDR_SIZE) == addr) + // { + // //TODO: Warn of overwriteing data + // //TODO: add warning as error in Error Handler. + // addrFoundInCache = ADI_TRUE; + // halError = ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + // recoveryAction = ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_ADIHAL, halError, ADI_COMMON_ACT_WARN_RESET_LOG, halError, "Log failure"); + // /* preserve the address but clear the data. */ + // + // //TODO: make a test to check this + // device->common.cacheInfo.wrCache[i] &= 0xFFFFFF00; + // device->common.cacheInfo.wrCache[i] |= (((uint32_t)0xFF << SPI_MASK_SIZE) | regVal); + // } + // } + // } + // + // if ((device->common.cacheInfo.wrCacheState != ADRV9025_WR_CACHE_OFF) && + // (addrFoundInCache == ADI_FALSE)) + // { + // /* Write caching is turned on and the bitField has not been merged*/ + // tmp_wrCacheIdx = device->common.cacheInfo.wrCacheIdx; + // if ((tmp_wrCacheIdx++) >= ADRV9025_BF_WRCACHE_ARRAY_TRIP_SIZE) + // { + // /* if cache is full then flush cache and add next instruction. + // should not be a problem flushing a write cache. + // */ + // device->common.cacheInfo.wrFlushEn = ADI_ENABLE; + // recoveryAction = fpga9025_BfWriteCacheFlush(device); + // ADI_ERROR_RETURN(device->common.error.newAction); + // device->common.cacheInfo.wrFlushEn = ADI_DISABLE; + // } + // + // device->common.cacheInfo.wrCache[device->common.cacheInfo.wrCacheIdx++] = ((uint32_t)addr << SPI_ADDR_SIZE) | (uint32_t)0xFF << SPI_MASK_SIZE | regVal; + // } + // + // if (device->common.cacheInfo.wrCacheState == ADRV9025_WR_CACHE_OFF) + // { + // /* Write caching is not being used, so do an immediate write */ + // if (device->common.devHalInfo != NULL) + // { + // recoveryAction = adi_fpga9025_hal_SpiByteWrite(device, addr, regVal); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // } + adi_fpga9025_RegisterWrite(device, + addr, + regVal); + ADI_ERROR_RETURN(device->common.error.newAction); + return recoveryAction; +} + +/** +* \brief Used to read a register. +* Caches the read if caching is on, immediately reads the value with caching off. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep{ADRV9025_BF_RDCACHE_ARRAY_TRIP_SIZE} +* \dep{SPIARRAYSIZE} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param addr The address of the Register to read. +* \param regVal The value of the register just read. +* \param endOfBf when using read caching the upper nibble of this field indicates the end of bitfield with the Value F. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_BfRegisterRead(adi_fpga9025_Device_t* device, + uint32_t addr, + uint32_t* regVal, + uint8_t endOfBf) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + + ADI_NULL_PTR_RETURN(&device->common, + regVal); + // + // if (device->common.cacheInfo.rdCacheState > ADRV9025_RD_CACHE_OFF) + // { + // /* Read Caching is turned on */ + // int tmp_rdCacheIdx = device->common.cacheInfo.rdCacheIdx; + // if ((tmp_rdCacheIdx++) >= ADRV9025_BF_RDCACHE_ARRAY_TRIP_SIZE) + // { + // /* if the cache is full then raise an error*/ + // ADI_ERROR_REPORT(&device->common.error, ADI_COMMON_ERRSRC_DEVICEBF, + // ADRV9025_BF_CACHE_OVERFLOW, + // ADI_COMMON_ACT_ERR_CHECK_PARAM, + // NULL, + // "Rx Cache size exceeded error"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // /* set bits [31:16] of the cache to the 16 bit address + // set bits [15:8] of cache to the 8 bit mask address + // set bits [7:0] of cache to the 8 bit endOfBf. + // endOfBf contains two 4 bit fields. + // [7:4] is 0xF or 0x0 and masks a end of bitField data value. + // [3:0] is the register startBit ie where the value resides in the register. + // */ + // device->common.cacheInfo.rdCache[device->common.cacheInfo.rdCacheIdx++] = ((uint32_t)addr << SPI_ADDR_SIZE) | + // ((uint32_t)0xFF << SPI_DATA_SIZE) | + // endOfBf; + // } + // else + // { + // // recoveryAction = adi_fpga9025_hal_SpiByteRead(device, addr, regVal); + + //int32_t adi_fpga9025_RegisterRead(adi_fpga9025_Device_t *device, uint32_t offset, uint32_t *data) + //ToDo replace theis with fieldRead. + + adi_fpga9025_RegisterRead(device, + addr, + regVal); + ADI_ERROR_RETURN(device->common.error.newAction); + // } + return recoveryAction; +} + +/** +* \brief Used to write to a sub part of a register. +* Caches the write if caching is on, immediately writes the value with caching off. +* Uses the HW_RMW function if the HW_RMW is enabled otherwise used a spi transaction to read the register +* and a spi write transaction to write the modified byte back to the register. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep{ADRV9025_BF_WRCACHE_ARRAY_TRIP_SIZE} +* \dep{SPIARRAYSIZE} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param addr The Register address that contains the field. +* \param fieldVal The value of the field to be written. +* \param mask The mask to use when inserting the data into the register. +* \param startBit The location of the first bit of the field within the register. +* when using read caching the upper nibble of this field indicates the end of bitfield with the Value F. +* This value is used to shift the value so that it aligns with the location of the field within the register. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_BfFieldWrite(adi_fpga9025_Device_t* device, + uint32_t addr, + uint32_t fieldVal, + uint32_t mask, + uint8_t startBit) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + uint32_t regVal = ((fieldVal << startBit) & mask); + + uint32_t registerVal = 0; + uint32_t newRegVal = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + + //TODO: remove this if not used + // if (device->common.cacheInfo.wrCacheState > ADRV9025_WR_HW_RMW_ON) + // { + // /* if caching is turned on*/ + // if (device->common.cacheInfo.wrCacheState == ADRV9025_WR_GBL_MERGE_ON) + // { + // /* if merging of multiple register writes with the same address is turned on*/ + // for (i = 0; i < device->common.cacheInfo.wrCacheIdx; i++) + // { + // /* search the cache for addr in the cache + // * if found merge field val and the mask into the original values*/ + // if ((uint16_t)(device->common.cacheInfo.wrCache[i] >> SPI_ADDR_SIZE) == addr) + // { + // addrFoundInCache = 1; + // cachemask = (uint8_t)(device->common.cacheInfo.wrCache[i] | 0xFF00); + // newMask = cachemask | mask; + // cacheVal = (uint8_t)(device->common.cacheInfo.wrCache[i]); + // newVal = cacheVal | regVal; + // /* clear org mask and data. */ + // + // device->common.cacheInfo.wrCache[i] &= 0xFFFF0000; + // device->common.cacheInfo.wrCache[i] |= ((uint32_t)newMask << 8) | newVal; + // } + // } + // } + // if ((device->common.cacheInfo.wrCacheState > ADRV9025_WR_CACHE_OFF) & !addrFoundInCache) + // { + // /* if caching is on or + // * merging is on but addr was not found in the cache + // * add the wr instruction to the cache. */ + // tmp_wrCacheIdx = device->common.cacheInfo.wrCacheIdx; + // if ((tmp_wrCacheIdx++) >= ADRV9025_BF_WRCACHE_ARRAY_TRIP_SIZE) + // { + // recoveryAction = fpga9025_BfWriteCacheFlush(device); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // device->common.cacheInfo.wrCache[device->common.cacheInfo.wrCacheIdx++] = ((uint32_t)addr << SPI_ADDR_SIZE) | + // ((uint32_t)mask << 8) | + // regVal; + // } + // } + // else + // { + // /* Immediate Read modify write using HW_RMW function */ + // if (device->common.cacheInfo.wrCacheState == ADRV9025_WR_HW_RMW_ON && + // (device->common.cacheInfo.HW_RMW_Enabled > 0)) + // { + // if (device->common.cacheInfo.wrCacheIdx >= ADRV9025_BF_WRCACHE_ARRAY_TRIP_SIZE) + // { + // //it is possible the cache may cause the spi buffer to exceed its size + // //given this is a write operation it should be ok to flush and empty the buffrer + // recoveryAction = fpga9025_BfWriteCacheFlush(device); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // recoveryAction = adi_fpga9025_hal_SpiByteWrite(device, addr, newRegVal); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // else + // { + /* Immediate Standard read Modify Write using separate read + and writespi transactions. */ + recoveryAction = adi_fpga9025_RegisterRead(device, + addr, + ®isterVal); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* modify the register value*/ + newRegVal = (registerVal & ~mask) | regVal; + + /* write to the register with modified value*/ + recoveryAction = adi_fpga9025_RegisterWrite(device, + addr, + newRegVal); + ADI_ERROR_RETURN(device->common.error.newAction); + // } + // } + return recoveryAction; +} + +/** +* \brief Used to read a sub part of a register +* caches the read if caching is on, immediately read the value with caching off +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep{ADRV9025_BF_RDCACHE_ARRAY_TRIP_SIZE} +* \dep{SPIARRAYSIZE} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param addr The Register address that contains the field. +* \param fieldVal The value of the field to be written. +* \param mask The mask to use when inserting the data into the register. +* \param startBit The location of the first bit of the field within the register. +* +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_BfFieldRead(adi_fpga9025_Device_t* device, + uint32_t addr, + uint32_t* fieldVal, + uint32_t mask, + uint8_t startBit) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + + ADI_NULL_PTR_RETURN(&device->common, + fieldVal); + + //TODO: remove this if not used + // + // if (device->common.cacheInfo.rdCacheState > ADRV9025_RD_CACHE_OFF) + // { + // //adds spi call to cache + // int rdCacheIdx = device->common.cacheInfo.rdCacheIdx; + // if ((rdCacheIdx++) >= ADRV9025_BF_RDCACHE_ARRAY_TRIP_SIZE) + // { + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, + // ADI_COMMON_ERR_INV_PARAM, + // ADI_COMMON_ACT_ERR_CHECK_PARAM, + // NULL, + // "Rx Cache size exceeded error"); + // + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // device->common.cacheInfo.rdCache[device->common.cacheInfo.rdCacheIdx++] = ((uint32_t)addr << SPI_ADDR_SIZE) | + // ((uint32_t)mask << SPI_MASK_SIZE) | + // startBit; + // } + // else + // { + // /* Implements immediate spi transaction call only used when caching is turned off. */ + //recoveryAction = adi_fpga9025_hal_SpiFieldRead(device, addr, fieldVal, mask, startBit); + + startBit = startBit & 0x3F; /* remove the End Of BitField Marker */ + + recoveryAction = adi_fpga9025_RegisterFieldRead(device, + addr, + fieldVal, + mask, + startBit); + + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + + return recoveryAction; +} + +/** +* \brief Used by the bitField API to ensure the cache is flushed when using BitField Caching +* and to assemble the register bytes when caching is not used. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rxBfData The raw data read from the registers prior to concatenation. +* \param numRxBfData The number of elements used in the rxBfData. +* \param rxData The assembled bitfield value. +* +* \retval ADI_FPGA90259025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_FPGA90259025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA90259025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_FPGA90259025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_BfReadAssembleData(adi_fpga9025_Device_t* device, + uint32_t* rxBfData, + uint8_t numRxBfData, + uint64_t* rxData) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t i = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + + ADI_NULL_PTR_RETURN(&device->common, + rxBfData); + ADI_NULL_PTR_RETURN(&device->common, + rxData); + //TODO: remove this if not used + // + // if (device->common.cacheInfo.rdCacheState == ADRV9025_RD_BF_CACHE_ON) + // { + // recoveryAction = fpga9025_BfReadCacheFlush(device, rxData, &numRxBitFields); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // else if (device->common.cacheInfo.rdCacheState == ADRV9025_RD_CACHE_OFF) + // { + // /* Caching is not used so then assembly the bitFiled register values + // into a bitField Value. The max bitField Value is 64bits long. + // so rdData could be shifted 2 times to concatenate a 64 bit value.*/ + for (i = 0; i < numRxBfData; i++) + { + /* shift rxData to the left to make room for the next lower byte + in the bitField*/ + *rxData = (*rxData << 32) | (uint64_t)rxBfData[i]; + } + // } + return recoveryAction; +} + +/** +* \brief Used to send multiple spi register reads in one spi transaction. +* multiple register data and sub register data is concatenated and shifted appropriately. +* +* \dep_begin +* \dep{ADRV9025_BF_RDCACHE_ARRAY_SIZE} +* \dep{SPIARRAYSIZE} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* \param rdData The bytefield data being returned in the order it was read. +* \param numRdBitFields The number of bitfields being returned +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_BfReadCacheFlush(adi_fpga9025_Device_t* device, + uint64_t* rdData, + uint16_t* numRdBitFields) +{ + UNUSED_PARA(device); + UNUSED_PARA(rdData); + UNUSED_PARA(numRdBitFields); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + //TODO: remove this if not used + // uint32_t bfValue = 0; + // uint32_t i = 0; + // uint16_t addr = 0; + // uint16_t rdAddr[ADRV9025_BF_RDCACHE_ARRAY_SIZE] = { 0 }; + // + // uint8_t regVal = 0; + // uint8_t mask = 0; + // uint8_t startBit = 0; + // uint8_t endOfBitfield = 0; + // + // uint8_t regData[ADRV9025_BF_RDCACHE_ARRAY_SIZE] = { 0 }; + // int32_t halError = ADI_COMMON_HAL_OK; + + // ADI_NULL_DEVICE_PTR_RETURN(device); + // + // ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + // + // ADI_NULL_PTR_RETURN(&device->common,(&device->common.error, rdData); + // ADI_NULL_PTR_RETURN(&device->common,(&device->common.error, numRdBitFields); + // + // *numRdBitFields = 0; + // + // if (device->common.cacheInfo.rdCacheIdx > ADRV9025_BF_RDCACHE_ARRAY_SIZE) + // { + // ADI_ERROR_REPORT(&device->common, 2, ADI_COMMON_ERRSRC_DEVICEBF, + // ADI_ADRV9025_ACT_ERR_FLUSH_CACHE, + // NULL, + // "Rd Cache index exceeded the spi cache Size "); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // /* the rdData supplied by the calling function is smaller then the rdCacheIdx*/ + // if (device->common.cacheInfo.rdCacheIdx > sizeof(rdData)) + // { + // ADI_ERROR_REPORT(&device->common, 2, ADI_COMMON_ERRSRC_DEVICEBF, + // ADI_ADRV9025_ACT_ERR_FLUSH_CACHE, + // NULL, + // "Rd Cache index exceeded the user supplied rdData "); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // + // /* pack all the read data into one array*/ + // for (i = 0; i < device->common.cacheInfo.rdCacheIdx; i++) + // { + // /* extract the address (cache[31-16]) from each of the 32 bit words in the cache + // into a address array suitable for ADRV9025HAL_spiReadBytes*/ + // rdAddr[i] = device->common.cacheInfo.rdCache[i] >> SPI_ADDR_SIZE; + // } + // + // /* send the array and receive an array of register values */ + // adi_fpga9025_hal_SpiBytesRead(device, &rdAddr[0], ®Data[0], device->common.cacheInfo.rdCacheIdx); + // ADI_ERROR_RETURN(device->common.error.newAction); + // + // /* depack the array of register values into an array of bitField values*/ + // for (i = 0; i < device->common.cacheInfo.rdCacheIdx; i++) + // { + // /* for each of the register values in the cache (if any) + // combine the data into a bitfield value*/ + // + // mask = (uint8_t)(device->common.cacheInfo.rdCache[i] >> 8); + // startBit = (uint8_t)(device->common.cacheInfo.rdCache[i]); + // + // /*The last byte in the bit field is marked by setting the upper + // nible of the startBit to F, this allows the lower nible to + // handle the byte with values from 0 to 7. + // This marker is added within the get bitfield function. + // */ + // endOfBitfield = startBit > 0xF; + // + // if (endOfBitfield) + // { + // startBit = startBit & 0xF; + // } + // regVal = regData[i]; + // + // bfValue = (bfValue << 8) | ((regVal & mask) >> startBit); + // + // device->common.cacheInfo.rdCache[i] = '\0'; + // + // if (endOfBitfield) + // { + // rdData[(*numRdBitFields)++] = bfValue; + // bfValue = 0; + // } + // } + // device->common.cacheInfo.rdCacheIdx = 0; + // device->common.cacheInfo.rdCache[device->common.cacheInfo.rdCacheIdx] = '\0'; + return recoveryAction; +} + +/** +* \brief Used to send multiple spi register writes in one spi transaction. +* if the spi buffer size is exceeded the data will be sent in buffer size blocks. +* Only full bytes are written ie there are no RMW operations +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep{ADRV9025_BF_WRCACHE_ARRAY_SIZE} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t fpga9025_BfWriteCacheFlush(adi_fpga9025_Device_t* device) +{ + UNUSED_PARA(device); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + //TODO: remove this if not used + // uint32_t i = 0; + // uint16_t wrAddr[ADRV9025_BF_WRCACHE_ARRAY_SIZE] = { 0 }; + // uint8_t wrData[ADRV9025_BF_WRCACHE_ARRAY_SIZE] = { 0 }; + // int32_t halError = ADI_COMMON_HAL_OK; + + // ADI_NULL_DEVICE_PTR_RETURN(device); + // + // ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); + // + // if (device->common.cacheInfo.wrCacheIdx > ADRV9025_BF_WRCACHE_ARRAY_SIZE) + // { + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, + // ADRV9025_BF_CACHE_OVERFLOW, + // ADI_ADRV9025_ACT_ERR_FLUSH_CACHE, + // NULL, + // "Wr Cache index exceeded the spi cache Size "); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // + // if (device->common.cacheInfo.wrFlushEn == ADI_ENABLE) + // { + // /* convert the cache into two arrays spiWriteBytes can use*/ + // for (i = 0; i < device->common.cacheInfo.wrCacheIdx; i++) + // { + // wrAddr[i] = (uint16_t)((device->common.cacheInfo.wrCache[i] >> SPI_ADDR_SIZE) & 0xFFFF); + // wrData[i] = (uint8_t)(device->common.cacheInfo.wrCache[i] & 0xFF); + // device->common.cacheInfo.wrCache[i] = '\0'; + // } + // /* write the cache to the part */ + // recoveryAction = adi_fpga9025_hal_SpiBytesWrite(device, &wrAddr[0], + // &wrData[0], + // device->common.cacheInfo.wrCacheIdx); + // ADI_ERROR_RETURN(device->common.error.newAction); + // + // device->common.cacheInfo.wrCacheIdx = 0; + // device->common.cacheInfo.wrCache[device->common.cacheInfo.wrCacheIdx] = '\0'; + // } + // device->common.cacheInfo.wrFlushEn = ADI_ENABLE; + + return recoveryAction; +} + +/** +* \brief allows the user to set the Write cache state. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param wrCacheState the cache state to be set. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +//int32_t fpga9025_BfWriteCacheEn(adi_fpga9025_Device_t *device, +// fpga9025_Bf_WrCache_State_e wrCacheState) +//{ +// int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; +// int32_t halError = ADI_COMMON_HAL_OK; + +// ADI_NULL_DEVICE_PTR_RETURN(device); +// +// ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); +// +// device->common.cacheInfo.wrCacheState = wrCacheState; +// return recoveryAction; +//} + +/** +* \brief allows the user to set the read cache state. +* +* \dep_begin +* \dep{device->common.cacheInfo} +* \dep_end +* +* \param device Pointer to the ADRV9025 device data structure. +* \param rdCacheState the cache state to be set. +* +* \retval ADRV9025_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADRV9025_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADRV9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADRV9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +//int32_t fpga9025_BfReadCacheEn(adi_fpga9025_Device_t *device, +// fpga9025_Bf_RdCache_State_e rdCacheState) +//{ +// int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; +// int32_t halError = ADI_COMMON_HAL_OK; + +// ADI_NULL_DEVICE_PTR_RETURN(device); +// +// ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_BF); +// +// device->common.cacheInfo.rdCacheState = rdCacheState; +// return recoveryAction; +//} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_ila_trigger.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_ila_trigger.c new file mode 100644 index 0000000..e4cb963 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_ila_trigger.c @@ -0,0 +1,304 @@ +/** + * \file fpga9025_bf_ila_trigger.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_ila_trigger.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfIlaTriggerChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_IlaTriggerModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfIlaTriggerChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ILA_TRIGGER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_IlaTriggerModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfIlaTriggerChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_IlaTriggerModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfIlaTriggerChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ILA_TRIGGER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_IlaTriggerModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Triggers + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfIlaTriggerChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_IlaTriggerTriggerBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfIlaTriggerChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_IlaTriggerTriggerBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ILA_TRIGGER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_IlaTriggerTriggerBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x4), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Triggers + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfIlaTriggerChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_IlaTriggerTriggerBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfIlaTriggerChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ILA_TRIGGER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_IlaTriggerTriggerBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_ila_trigger.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204_phy_ads9.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204_phy_ads9.c new file mode 100644 index 0000000..aa6ac0c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204_phy_ads9.c @@ -0,0 +1,64091 @@ +/** + * \file fpga9025_bf_jesd204_phy_ads9.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2019 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_jesd204_phy_ads9.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Channel 0 Channel PLL Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0CpllLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0CpllLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x110), + &rxBfData[0], + 0x4000000, + 0xDA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0CpllPdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0CpllPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0CpllPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x110), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0CpllPdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0CpllPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x110), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0CpllRefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0CpllRefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0CpllRefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x110), + (uint32_t)bfValue, + 0x70000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0CpllRefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0CpllRefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x110), + &rxBfData[0], + 0x70000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1023U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x140), + (uint32_t)bfValue, + 0x3FF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x140), + &rxBfData[0], + 0x3FF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x140), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x140), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x14C), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x14C), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x14C), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x140), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x140), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x144), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x144), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x148), + (uint32_t)bfValue, + 0xFFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x148), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x148), + (uint32_t)bfValue, + 0xFFFF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x148), + &rxBfData[0], + 0xFFFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x140), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x140), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0GtpowergoodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0GtpowergoodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0GtpowergoodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x104), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0GtpowergoodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0GtpowergoodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x104), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0LoopbackBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0LoopbackBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0LoopbackBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x120), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0LoopbackBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0LoopbackBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x120), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0Rx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0Rx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0Rx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x114), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0Rx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0Rx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x114), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxBufResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxBufResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxBufResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x100), + (uint32_t)bfValue, + 0x100000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxBufResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxBufResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x100), + &rxBfData[0], + 0x100000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x104), + (uint32_t)bfValue, + 0x700000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x104), + &rxBfData[0], + 0x700000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive CDR Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxCdrHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxCdrHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxCdrHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x114), + (uint32_t)bfValue, + 0x1000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive CDR Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxCdrHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxCdrHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x114), + &rxBfData[0], + 0x1000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxCdrlockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxCdrlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxCdrlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x104), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxCdrlockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxCdrlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x104), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxCommaDetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxCommaDetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxCommaDetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x104), + (uint32_t)bfValue, + 0x1000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxCommaDetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxCommaDetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x104), + &rxBfData[0], + 0x1000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxDfeLpmEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxDfeLpmEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxDfeLpmEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x114), + (uint32_t)bfValue, + 0x100, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxDfeLpmEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxDfeLpmEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x114), + &rxBfData[0], + 0x100, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxDfeLpmHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxDfeLpmHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxDfeLpmHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x114), + (uint32_t)bfValue, + 0x200, + 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxDfeLpmHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxDfeLpmHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x114), + &rxBfData[0], + 0x200, + 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxDfeLpmOverrideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxDfeLpmOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxDfeLpmOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x114), + (uint32_t)bfValue, + 0x400, + 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxDfeLpmOverrideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxDfeLpmOverrideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x114), + &rxBfData[0], + 0x400, + 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxDfeLpmResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxDfeLpmResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxDfeLpmResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x100), + (uint32_t)bfValue, + 0x40000, + 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxDfeLpmResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxDfeLpmResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x100), + &rxBfData[0], + 0x40000, + 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive Gearbox Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxGearboxSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxGearboxSlipBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxGearboxSlipBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x114), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive Gearbox Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxGearboxSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxGearboxSlipBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x114), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 RX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxOutClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxOutClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x110), + (uint32_t)bfValue, + 0x7000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 RX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxOutClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x110), + &rxBfData[0], + 0x7000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x100), + (uint32_t)bfValue, + 0x80000, + 0x13); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x100), + &rxBfData[0], + 0x80000, + 0xD3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x110), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x110), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x100), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x100), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 GT RX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x104), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x114), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x114), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x114), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x114), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Receiver PRBS Error Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxPrbsErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPrbsErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x124), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxPrbsErrCntRstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPrbsErrCntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPrbsErrCntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x120), + (uint32_t)bfValue, + 0x100000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxPrbsErrCntRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPrbsErrCntRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x120), + &rxBfData[0], + 0x100000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x120), + (uint32_t)bfValue, + 0xF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x120), + &rxBfData[0], + 0xF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x114), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x114), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x100), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x100), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 GT RX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0RxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0RxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x104), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0Tx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0Tx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0Tx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x118), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0Tx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0Tx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x118), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x104), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x104), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxDiffControlBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxDiffControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxDiffControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x118), + (uint32_t)bfValue, + 0x1F000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxDiffControlBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxDiffControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x118), + &rxBfData[0], + 0x1F000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 TX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxOutClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxOutClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x110), + (uint32_t)bfValue, + 0x700, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 TX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxOutClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x110), + &rxBfData[0], + 0x700, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x100), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x100), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x110), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x110), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x100), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x100), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 GT TX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x104), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x118), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x118), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPostcursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPostcursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPostcursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x118), + (uint32_t)bfValue, + 0x1F00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPostcursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPostcursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x118), + &rxBfData[0], + 0x1F00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x118), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x118), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPrbsInjErrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPrbsInjErrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPrbsInjErrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x120), + (uint32_t)bfValue, + 0x10000000, + 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPrbsInjErrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPrbsInjErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x120), + &rxBfData[0], + 0x10000000, + 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x120), + (uint32_t)bfValue, + 0xF000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x120), + &rxBfData[0], + 0xF000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPrecursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPrecursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPrecursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x118), + (uint32_t)bfValue, + 0x1F0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxPrecursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxPrecursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x118), + &rxBfData[0], + 0x1F0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x118), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x118), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x100), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 0 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x100), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 0 GT TX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel0TxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel0TxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x104), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Channel PLL Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1CpllLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1CpllLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x210), + &rxBfData[0], + 0x4000000, + 0xDA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1CpllPdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1CpllPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1CpllPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x210), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1CpllPdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1CpllPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x210), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1CpllRefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1CpllRefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1CpllRefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x210), + (uint32_t)bfValue, + 0x70000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1CpllRefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1CpllRefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x210), + &rxBfData[0], + 0x70000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1023U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x240), + (uint32_t)bfValue, + 0x3FF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x240), + &rxBfData[0], + 0x3FF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x240), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x240), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x24C), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x24C), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x24C), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x240), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x240), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x244), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x244), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x248), + (uint32_t)bfValue, + 0xFFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x248), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x248), + (uint32_t)bfValue, + 0xFFFF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x248), + &rxBfData[0], + 0xFFFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x240), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x240), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1GtpowergoodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1GtpowergoodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1GtpowergoodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x204), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1GtpowergoodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1GtpowergoodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x204), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1LoopbackBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1LoopbackBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1LoopbackBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x220), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1LoopbackBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1LoopbackBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x220), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1Rx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1Rx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1Rx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x214), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1Rx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1Rx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x214), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxBufResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxBufResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxBufResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x200), + (uint32_t)bfValue, + 0x100000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxBufResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxBufResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x200), + &rxBfData[0], + 0x100000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x204), + (uint32_t)bfValue, + 0x700000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x204), + &rxBfData[0], + 0x700000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive CDR Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxCdrHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxCdrHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxCdrHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x214), + (uint32_t)bfValue, + 0x1000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive CDR Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxCdrHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxCdrHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x214), + &rxBfData[0], + 0x1000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxCdrlockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxCdrlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxCdrlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x204), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxCdrlockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxCdrlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x204), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxCommaDetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxCommaDetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxCommaDetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x204), + (uint32_t)bfValue, + 0x1000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxCommaDetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxCommaDetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x204), + &rxBfData[0], + 0x1000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxDfeLpmEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxDfeLpmEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxDfeLpmEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x214), + (uint32_t)bfValue, + 0x100, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxDfeLpmEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxDfeLpmEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x214), + &rxBfData[0], + 0x100, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxDfeLpmHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxDfeLpmHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxDfeLpmHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x214), + (uint32_t)bfValue, + 0x200, + 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxDfeLpmHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxDfeLpmHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x214), + &rxBfData[0], + 0x200, + 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxDfeLpmOverrideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxDfeLpmOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxDfeLpmOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x214), + (uint32_t)bfValue, + 0x400, + 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxDfeLpmOverrideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxDfeLpmOverrideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x214), + &rxBfData[0], + 0x400, + 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxDfeLpmResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxDfeLpmResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxDfeLpmResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x200), + (uint32_t)bfValue, + 0x40000, + 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxDfeLpmResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxDfeLpmResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x200), + &rxBfData[0], + 0x40000, + 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive Gearbox Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxGearboxSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxGearboxSlipBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxGearboxSlipBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x214), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive Gearbox Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxGearboxSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxGearboxSlipBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x214), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 RX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxOutClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxOutClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x210), + (uint32_t)bfValue, + 0x7000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 RX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxOutClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x210), + &rxBfData[0], + 0x7000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x200), + (uint32_t)bfValue, + 0x80000, + 0x13); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x200), + &rxBfData[0], + 0x80000, + 0xD3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x210), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x210), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x200), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x200), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 GT RX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x204), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x214), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x214), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x214), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x214), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Receiver PRBS Error Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxPrbsErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPrbsErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x224), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxPrbsErrCntRstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPrbsErrCntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPrbsErrCntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x220), + (uint32_t)bfValue, + 0x100000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxPrbsErrCntRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPrbsErrCntRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x220), + &rxBfData[0], + 0x100000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x220), + (uint32_t)bfValue, + 0xF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x220), + &rxBfData[0], + 0xF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x214), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x214), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x200), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x200), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 GT RX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1RxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1RxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x204), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1Tx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1Tx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1Tx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x218), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1Tx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1Tx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x218), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x204), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x204), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxDiffControlBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxDiffControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxDiffControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x218), + (uint32_t)bfValue, + 0x1F000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxDiffControlBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxDiffControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x218), + &rxBfData[0], + 0x1F000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 TX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxOutClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxOutClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x210), + (uint32_t)bfValue, + 0x700, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 TX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxOutClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x210), + &rxBfData[0], + 0x700, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x200), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x200), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x210), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x210), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x200), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x200), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 GT TX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x204), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x218), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x218), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPostcursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPostcursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPostcursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x218), + (uint32_t)bfValue, + 0x1F00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPostcursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPostcursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x218), + &rxBfData[0], + 0x1F00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x218), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x218), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPrbsInjErrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPrbsInjErrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPrbsInjErrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x220), + (uint32_t)bfValue, + 0x10000000, + 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPrbsInjErrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPrbsInjErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x220), + &rxBfData[0], + 0x10000000, + 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x220), + (uint32_t)bfValue, + 0xF000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x220), + &rxBfData[0], + 0xF000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPrecursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPrecursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPrecursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x218), + (uint32_t)bfValue, + 0x1F0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxPrecursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxPrecursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x218), + &rxBfData[0], + 0x1F0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x218), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x218), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x200), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 1 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x200), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 1 GT TX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel1TxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel1TxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x204), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Channel PLL Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2CpllLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2CpllLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x310), + &rxBfData[0], + 0x4000000, + 0xDA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2CpllPdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2CpllPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2CpllPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x310), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2CpllPdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2CpllPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x310), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2CpllRefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2CpllRefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2CpllRefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x310), + (uint32_t)bfValue, + 0x70000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2CpllRefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2CpllRefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x310), + &rxBfData[0], + 0x70000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1023U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x340), + (uint32_t)bfValue, + 0x3FF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x340), + &rxBfData[0], + 0x3FF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x340), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x340), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x34C), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x34C), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x34C), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x340), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x340), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x344), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x344), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x348), + (uint32_t)bfValue, + 0xFFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x348), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x348), + (uint32_t)bfValue, + 0xFFFF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x348), + &rxBfData[0], + 0xFFFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x340), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x340), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2GtpowergoodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2GtpowergoodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2GtpowergoodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x304), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2GtpowergoodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2GtpowergoodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x304), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2LoopbackBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2LoopbackBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2LoopbackBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x320), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2LoopbackBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2LoopbackBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x320), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2Rx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2Rx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2Rx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x314), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2Rx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2Rx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x314), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxBufResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxBufResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxBufResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x300), + (uint32_t)bfValue, + 0x100000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxBufResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxBufResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x300), + &rxBfData[0], + 0x100000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x304), + (uint32_t)bfValue, + 0x700000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x304), + &rxBfData[0], + 0x700000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive CDR Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxCdrHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxCdrHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxCdrHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x314), + (uint32_t)bfValue, + 0x1000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive CDR Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxCdrHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxCdrHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x314), + &rxBfData[0], + 0x1000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxCdrlockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxCdrlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxCdrlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x304), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxCdrlockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxCdrlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x304), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxCommaDetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxCommaDetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxCommaDetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x304), + (uint32_t)bfValue, + 0x1000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxCommaDetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxCommaDetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x304), + &rxBfData[0], + 0x1000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxDfeLpmEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxDfeLpmEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxDfeLpmEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x314), + (uint32_t)bfValue, + 0x100, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxDfeLpmEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxDfeLpmEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x314), + &rxBfData[0], + 0x100, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxDfeLpmHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxDfeLpmHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxDfeLpmHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x314), + (uint32_t)bfValue, + 0x200, + 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxDfeLpmHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxDfeLpmHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x314), + &rxBfData[0], + 0x200, + 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxDfeLpmOverrideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxDfeLpmOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxDfeLpmOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x314), + (uint32_t)bfValue, + 0x400, + 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxDfeLpmOverrideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxDfeLpmOverrideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x314), + &rxBfData[0], + 0x400, + 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxDfeLpmResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxDfeLpmResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxDfeLpmResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x300), + (uint32_t)bfValue, + 0x40000, + 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxDfeLpmResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxDfeLpmResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x300), + &rxBfData[0], + 0x40000, + 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive Gearbox Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxGearboxSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxGearboxSlipBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxGearboxSlipBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x314), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive Gearbox Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxGearboxSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxGearboxSlipBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x314), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 RX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxOutClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxOutClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x310), + (uint32_t)bfValue, + 0x7000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 RX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxOutClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x310), + &rxBfData[0], + 0x7000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x300), + (uint32_t)bfValue, + 0x80000, + 0x13); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x300), + &rxBfData[0], + 0x80000, + 0xD3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x310), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x310), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x300), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x300), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 GT RX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x304), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x314), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x314), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x314), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x314), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Receiver PRBS Error Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxPrbsErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPrbsErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x324), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxPrbsErrCntRstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPrbsErrCntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPrbsErrCntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x320), + (uint32_t)bfValue, + 0x100000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxPrbsErrCntRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPrbsErrCntRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x320), + &rxBfData[0], + 0x100000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x320), + (uint32_t)bfValue, + 0xF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x320), + &rxBfData[0], + 0xF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x314), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x314), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x300), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x300), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 GT RX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2RxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2RxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x304), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2Tx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2Tx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2Tx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x318), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2Tx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2Tx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x318), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x304), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x304), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxDiffControlBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxDiffControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxDiffControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x318), + (uint32_t)bfValue, + 0x1F000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxDiffControlBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxDiffControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x318), + &rxBfData[0], + 0x1F000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 TX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxOutClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxOutClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x310), + (uint32_t)bfValue, + 0x700, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 TX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxOutClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x310), + &rxBfData[0], + 0x700, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x300), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x300), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x310), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x310), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x300), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x300), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 GT TX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x304), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x318), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x318), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPostcursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPostcursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPostcursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x318), + (uint32_t)bfValue, + 0x1F00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPostcursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPostcursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x318), + &rxBfData[0], + 0x1F00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x318), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x318), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPrbsInjErrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPrbsInjErrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPrbsInjErrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x320), + (uint32_t)bfValue, + 0x10000000, + 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPrbsInjErrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPrbsInjErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x320), + &rxBfData[0], + 0x10000000, + 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x320), + (uint32_t)bfValue, + 0xF000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x320), + &rxBfData[0], + 0xF000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPrecursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPrecursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPrecursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x318), + (uint32_t)bfValue, + 0x1F0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxPrecursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxPrecursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x318), + &rxBfData[0], + 0x1F0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x318), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x318), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x300), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 2 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x300), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 2 GT TX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel2TxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel2TxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x304), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Channel PLL Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3CpllLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3CpllLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x410), + &rxBfData[0], + 0x4000000, + 0xDA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3CpllPdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3CpllPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3CpllPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x410), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3CpllPdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3CpllPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x410), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3CpllRefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3CpllRefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3CpllRefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x410), + (uint32_t)bfValue, + 0x70000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3CpllRefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3CpllRefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x410), + &rxBfData[0], + 0x70000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1023U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x440), + (uint32_t)bfValue, + 0x3FF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x440), + &rxBfData[0], + 0x3FF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x440), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x440), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x44C), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x44C), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x44C), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x440), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x440), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x444), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x444), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x448), + (uint32_t)bfValue, + 0xFFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x448), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x448), + (uint32_t)bfValue, + 0xFFFF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x448), + &rxBfData[0], + 0xFFFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x440), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x440), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3GtpowergoodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3GtpowergoodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3GtpowergoodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x404), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3GtpowergoodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3GtpowergoodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x404), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3LoopbackBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3LoopbackBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3LoopbackBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x420), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3LoopbackBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3LoopbackBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x420), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3Rx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3Rx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3Rx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x414), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3Rx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3Rx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x414), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxBufResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxBufResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxBufResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x400), + (uint32_t)bfValue, + 0x100000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxBufResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxBufResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x400), + &rxBfData[0], + 0x100000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x404), + (uint32_t)bfValue, + 0x700000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x404), + &rxBfData[0], + 0x700000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive CDR Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxCdrHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxCdrHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxCdrHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x414), + (uint32_t)bfValue, + 0x1000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive CDR Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxCdrHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxCdrHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x414), + &rxBfData[0], + 0x1000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxCdrlockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxCdrlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxCdrlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x404), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxCdrlockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxCdrlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x404), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxCommaDetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxCommaDetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxCommaDetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x404), + (uint32_t)bfValue, + 0x1000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxCommaDetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxCommaDetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x404), + &rxBfData[0], + 0x1000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxDfeLpmEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxDfeLpmEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxDfeLpmEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x414), + (uint32_t)bfValue, + 0x100, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxDfeLpmEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxDfeLpmEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x414), + &rxBfData[0], + 0x100, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxDfeLpmHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxDfeLpmHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxDfeLpmHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x414), + (uint32_t)bfValue, + 0x200, + 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxDfeLpmHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxDfeLpmHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x414), + &rxBfData[0], + 0x200, + 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxDfeLpmOverrideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxDfeLpmOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxDfeLpmOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x414), + (uint32_t)bfValue, + 0x400, + 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxDfeLpmOverrideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxDfeLpmOverrideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x414), + &rxBfData[0], + 0x400, + 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxDfeLpmResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxDfeLpmResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxDfeLpmResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x400), + (uint32_t)bfValue, + 0x40000, + 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxDfeLpmResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxDfeLpmResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x400), + &rxBfData[0], + 0x40000, + 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive Gearbox Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxGearboxSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxGearboxSlipBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxGearboxSlipBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x414), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive Gearbox Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxGearboxSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxGearboxSlipBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x414), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 RX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxOutClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxOutClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x410), + (uint32_t)bfValue, + 0x7000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 RX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxOutClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x410), + &rxBfData[0], + 0x7000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x400), + (uint32_t)bfValue, + 0x80000, + 0x13); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x400), + &rxBfData[0], + 0x80000, + 0xD3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x410), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x410), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x400), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x400), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 GT RX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x404), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x414), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x414), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x414), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x414), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Receiver PRBS Error Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxPrbsErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPrbsErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x424), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxPrbsErrCntRstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPrbsErrCntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPrbsErrCntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x420), + (uint32_t)bfValue, + 0x100000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxPrbsErrCntRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPrbsErrCntRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x420), + &rxBfData[0], + 0x100000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x420), + (uint32_t)bfValue, + 0xF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x420), + &rxBfData[0], + 0xF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x414), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x414), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x400), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x400), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 GT RX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3RxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3RxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x404), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3Tx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3Tx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3Tx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x418), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3Tx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3Tx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x418), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x404), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x404), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxDiffControlBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxDiffControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxDiffControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x418), + (uint32_t)bfValue, + 0x1F000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxDiffControlBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxDiffControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x418), + &rxBfData[0], + 0x1F000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 TX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxOutClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxOutClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x410), + (uint32_t)bfValue, + 0x700, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 TX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxOutClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x410), + &rxBfData[0], + 0x700, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x400), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x400), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x410), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x410), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x400), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x400), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 GT TX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x404), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x418), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x418), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPostcursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPostcursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPostcursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x418), + (uint32_t)bfValue, + 0x1F00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPostcursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPostcursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x418), + &rxBfData[0], + 0x1F00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x418), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x418), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPrbsInjErrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPrbsInjErrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPrbsInjErrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x420), + (uint32_t)bfValue, + 0x10000000, + 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPrbsInjErrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPrbsInjErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x420), + &rxBfData[0], + 0x10000000, + 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x420), + (uint32_t)bfValue, + 0xF000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x420), + &rxBfData[0], + 0xF000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPrecursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPrecursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPrecursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x418), + (uint32_t)bfValue, + 0x1F0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxPrecursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxPrecursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x418), + &rxBfData[0], + 0x1F0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x418), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x418), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x400), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 3 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x400), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 3 GT TX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel3TxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel3TxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x404), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Channel PLL Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4CpllLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4CpllLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x510), + &rxBfData[0], + 0x4000000, + 0xDA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4CpllPdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4CpllPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4CpllPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x510), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4CpllPdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4CpllPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x510), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4CpllRefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4CpllRefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4CpllRefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x510), + (uint32_t)bfValue, + 0x70000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4CpllRefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4CpllRefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x510), + &rxBfData[0], + 0x70000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1023U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x540), + (uint32_t)bfValue, + 0x3FF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x540), + &rxBfData[0], + 0x3FF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x540), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x540), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x54C), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x54C), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x54C), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x540), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x540), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x544), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x544), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x548), + (uint32_t)bfValue, + 0xFFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x548), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x548), + (uint32_t)bfValue, + 0xFFFF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x548), + &rxBfData[0], + 0xFFFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x540), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x540), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4GtpowergoodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4GtpowergoodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4GtpowergoodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x504), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4GtpowergoodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4GtpowergoodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x504), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4LoopbackBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4LoopbackBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4LoopbackBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x520), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4LoopbackBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4LoopbackBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x520), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4Rx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4Rx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4Rx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x514), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4Rx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4Rx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x514), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxBufResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxBufResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxBufResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x500), + (uint32_t)bfValue, + 0x100000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxBufResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxBufResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x500), + &rxBfData[0], + 0x100000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x504), + (uint32_t)bfValue, + 0x700000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x504), + &rxBfData[0], + 0x700000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive CDR Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxCdrHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxCdrHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxCdrHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x514), + (uint32_t)bfValue, + 0x1000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive CDR Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxCdrHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxCdrHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x514), + &rxBfData[0], + 0x1000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxCdrlockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxCdrlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxCdrlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x504), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxCdrlockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxCdrlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x504), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxCommaDetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxCommaDetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxCommaDetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x504), + (uint32_t)bfValue, + 0x1000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxCommaDetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxCommaDetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x504), + &rxBfData[0], + 0x1000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxDfeLpmEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxDfeLpmEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxDfeLpmEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x514), + (uint32_t)bfValue, + 0x100, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxDfeLpmEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxDfeLpmEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x514), + &rxBfData[0], + 0x100, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxDfeLpmHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxDfeLpmHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxDfeLpmHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x514), + (uint32_t)bfValue, + 0x200, + 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxDfeLpmHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxDfeLpmHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x514), + &rxBfData[0], + 0x200, + 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxDfeLpmOverrideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxDfeLpmOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxDfeLpmOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x514), + (uint32_t)bfValue, + 0x400, + 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxDfeLpmOverrideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxDfeLpmOverrideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x514), + &rxBfData[0], + 0x400, + 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxDfeLpmResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxDfeLpmResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxDfeLpmResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x500), + (uint32_t)bfValue, + 0x40000, + 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxDfeLpmResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxDfeLpmResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x500), + &rxBfData[0], + 0x40000, + 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive Gearbox Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxGearboxSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxGearboxSlipBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxGearboxSlipBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x514), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive Gearbox Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxGearboxSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxGearboxSlipBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x514), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 RX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxOutClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxOutClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x510), + (uint32_t)bfValue, + 0x7000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 RX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxOutClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x510), + &rxBfData[0], + 0x7000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x500), + (uint32_t)bfValue, + 0x80000, + 0x13); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x500), + &rxBfData[0], + 0x80000, + 0xD3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x510), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x510), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x500), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x500), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 GT RX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x504), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x514), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x514), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x514), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x514), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Receiver PRBS Error Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxPrbsErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPrbsErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x524), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxPrbsErrCntRstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPrbsErrCntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPrbsErrCntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x520), + (uint32_t)bfValue, + 0x100000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxPrbsErrCntRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPrbsErrCntRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x520), + &rxBfData[0], + 0x100000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x520), + (uint32_t)bfValue, + 0xF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x520), + &rxBfData[0], + 0xF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x514), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x514), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x500), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x500), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 GT RX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4RxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4RxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x504), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4Tx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4Tx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4Tx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x518), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4Tx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4Tx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x518), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x504), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x504), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxDiffControlBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxDiffControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxDiffControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x518), + (uint32_t)bfValue, + 0x1F000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxDiffControlBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxDiffControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x518), + &rxBfData[0], + 0x1F000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 TX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxOutClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxOutClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x510), + (uint32_t)bfValue, + 0x700, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 TX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxOutClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x510), + &rxBfData[0], + 0x700, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x500), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x500), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x510), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x510), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x500), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x500), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 GT TX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x504), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x518), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x518), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPostcursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPostcursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPostcursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x518), + (uint32_t)bfValue, + 0x1F00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPostcursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPostcursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x518), + &rxBfData[0], + 0x1F00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x518), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x518), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPrbsInjErrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPrbsInjErrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPrbsInjErrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x520), + (uint32_t)bfValue, + 0x10000000, + 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPrbsInjErrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPrbsInjErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x520), + &rxBfData[0], + 0x10000000, + 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x520), + (uint32_t)bfValue, + 0xF000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x520), + &rxBfData[0], + 0xF000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPrecursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPrecursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPrecursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x518), + (uint32_t)bfValue, + 0x1F0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxPrecursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxPrecursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x518), + &rxBfData[0], + 0x1F0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x518), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x518), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x500), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 4 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x500), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 4 GT TX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel4TxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel4TxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x504), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Channel PLL Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5CpllLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5CpllLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x610), + &rxBfData[0], + 0x4000000, + 0xDA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5CpllPdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5CpllPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5CpllPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x610), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5CpllPdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5CpllPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x610), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5CpllRefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5CpllRefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5CpllRefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x610), + (uint32_t)bfValue, + 0x70000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5CpllRefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5CpllRefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x610), + &rxBfData[0], + 0x70000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1023U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x640), + (uint32_t)bfValue, + 0x3FF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x640), + &rxBfData[0], + 0x3FF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x640), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x640), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64C), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64C), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64C), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x640), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x640), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x644), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x644), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x648), + (uint32_t)bfValue, + 0xFFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x648), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x648), + (uint32_t)bfValue, + 0xFFFF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x648), + &rxBfData[0], + 0xFFFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x640), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x640), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5GtpowergoodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5GtpowergoodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5GtpowergoodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x604), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5GtpowergoodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5GtpowergoodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x604), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5LoopbackBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5LoopbackBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5LoopbackBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x620), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5LoopbackBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5LoopbackBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x620), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5Rx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5Rx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5Rx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x614), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5Rx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5Rx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x614), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxBufResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxBufResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxBufResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x600), + (uint32_t)bfValue, + 0x100000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxBufResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxBufResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x600), + &rxBfData[0], + 0x100000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x604), + (uint32_t)bfValue, + 0x700000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x604), + &rxBfData[0], + 0x700000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive CDR Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxCdrHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxCdrHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxCdrHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x614), + (uint32_t)bfValue, + 0x1000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive CDR Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxCdrHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxCdrHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x614), + &rxBfData[0], + 0x1000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxCdrlockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxCdrlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxCdrlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x604), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxCdrlockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxCdrlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x604), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxCommaDetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxCommaDetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxCommaDetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x604), + (uint32_t)bfValue, + 0x1000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxCommaDetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxCommaDetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x604), + &rxBfData[0], + 0x1000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxDfeLpmEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxDfeLpmEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxDfeLpmEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x614), + (uint32_t)bfValue, + 0x100, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxDfeLpmEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxDfeLpmEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x614), + &rxBfData[0], + 0x100, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxDfeLpmHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxDfeLpmHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxDfeLpmHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x614), + (uint32_t)bfValue, + 0x200, + 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxDfeLpmHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxDfeLpmHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x614), + &rxBfData[0], + 0x200, + 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxDfeLpmOverrideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxDfeLpmOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxDfeLpmOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x614), + (uint32_t)bfValue, + 0x400, + 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxDfeLpmOverrideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxDfeLpmOverrideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x614), + &rxBfData[0], + 0x400, + 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxDfeLpmResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxDfeLpmResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxDfeLpmResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x600), + (uint32_t)bfValue, + 0x40000, + 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxDfeLpmResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxDfeLpmResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x600), + &rxBfData[0], + 0x40000, + 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive Gearbox Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxGearboxSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxGearboxSlipBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxGearboxSlipBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x614), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive Gearbox Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxGearboxSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxGearboxSlipBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x614), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 RX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxOutClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxOutClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x610), + (uint32_t)bfValue, + 0x7000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 RX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxOutClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x610), + &rxBfData[0], + 0x7000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x600), + (uint32_t)bfValue, + 0x80000, + 0x13); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x600), + &rxBfData[0], + 0x80000, + 0xD3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x610), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x610), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x600), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x600), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 GT RX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x604), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x614), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x614), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x614), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x614), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Receiver PRBS Error Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxPrbsErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPrbsErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x624), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxPrbsErrCntRstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPrbsErrCntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPrbsErrCntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x620), + (uint32_t)bfValue, + 0x100000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxPrbsErrCntRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPrbsErrCntRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x620), + &rxBfData[0], + 0x100000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x620), + (uint32_t)bfValue, + 0xF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x620), + &rxBfData[0], + 0xF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x614), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x614), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x600), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x600), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 GT RX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5RxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5RxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x604), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5Tx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5Tx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5Tx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x618), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5Tx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5Tx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x618), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x604), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x604), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxDiffControlBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxDiffControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxDiffControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x618), + (uint32_t)bfValue, + 0x1F000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxDiffControlBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxDiffControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x618), + &rxBfData[0], + 0x1F000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 TX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxOutClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxOutClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x610), + (uint32_t)bfValue, + 0x700, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 TX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxOutClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x610), + &rxBfData[0], + 0x700, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x600), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x600), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x610), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x610), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x600), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x600), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 GT TX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x604), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x618), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x618), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPostcursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPostcursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPostcursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x618), + (uint32_t)bfValue, + 0x1F00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPostcursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPostcursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x618), + &rxBfData[0], + 0x1F00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x618), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x618), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPrbsInjErrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPrbsInjErrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPrbsInjErrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x620), + (uint32_t)bfValue, + 0x10000000, + 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPrbsInjErrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPrbsInjErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x620), + &rxBfData[0], + 0x10000000, + 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x620), + (uint32_t)bfValue, + 0xF000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x620), + &rxBfData[0], + 0xF000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPrecursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPrecursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPrecursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x618), + (uint32_t)bfValue, + 0x1F0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxPrecursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxPrecursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x618), + &rxBfData[0], + 0x1F0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x618), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x618), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x600), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 5 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x600), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 5 GT TX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel5TxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel5TxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x604), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Channel PLL Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6CpllLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6CpllLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x710), + &rxBfData[0], + 0x4000000, + 0xDA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6CpllPdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6CpllPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6CpllPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x710), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6CpllPdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6CpllPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x710), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6CpllRefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6CpllRefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6CpllRefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x710), + (uint32_t)bfValue, + 0x70000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6CpllRefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6CpllRefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x710), + &rxBfData[0], + 0x70000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1023U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x740), + (uint32_t)bfValue, + 0x3FF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x740), + &rxBfData[0], + 0x3FF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x740), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x740), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x74C), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x74C), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x74C), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x740), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x740), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x744), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x744), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x748), + (uint32_t)bfValue, + 0xFFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x748), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x748), + (uint32_t)bfValue, + 0xFFFF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x748), + &rxBfData[0], + 0xFFFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x740), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x740), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6GtpowergoodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6GtpowergoodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6GtpowergoodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x704), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6GtpowergoodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6GtpowergoodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x704), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6LoopbackBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6LoopbackBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6LoopbackBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x720), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6LoopbackBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6LoopbackBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x720), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6Rx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6Rx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6Rx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x714), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6Rx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6Rx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x714), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxBufResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxBufResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxBufResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x700), + (uint32_t)bfValue, + 0x100000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxBufResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxBufResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x700), + &rxBfData[0], + 0x100000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x704), + (uint32_t)bfValue, + 0x700000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x704), + &rxBfData[0], + 0x700000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive CDR Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxCdrHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxCdrHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxCdrHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x714), + (uint32_t)bfValue, + 0x1000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive CDR Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxCdrHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxCdrHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x714), + &rxBfData[0], + 0x1000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxCdrlockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxCdrlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxCdrlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x704), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxCdrlockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxCdrlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x704), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxCommaDetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxCommaDetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxCommaDetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x704), + (uint32_t)bfValue, + 0x1000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxCommaDetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxCommaDetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x704), + &rxBfData[0], + 0x1000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxDfeLpmEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxDfeLpmEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxDfeLpmEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x714), + (uint32_t)bfValue, + 0x100, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxDfeLpmEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxDfeLpmEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x714), + &rxBfData[0], + 0x100, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxDfeLpmHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxDfeLpmHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxDfeLpmHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x714), + (uint32_t)bfValue, + 0x200, + 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxDfeLpmHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxDfeLpmHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x714), + &rxBfData[0], + 0x200, + 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxDfeLpmOverrideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxDfeLpmOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxDfeLpmOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x714), + (uint32_t)bfValue, + 0x400, + 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxDfeLpmOverrideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxDfeLpmOverrideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x714), + &rxBfData[0], + 0x400, + 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxDfeLpmResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxDfeLpmResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxDfeLpmResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x700), + (uint32_t)bfValue, + 0x40000, + 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxDfeLpmResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxDfeLpmResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x700), + &rxBfData[0], + 0x40000, + 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive Gearbox Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxGearboxSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxGearboxSlipBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxGearboxSlipBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x714), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive Gearbox Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxGearboxSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxGearboxSlipBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x714), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 RX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxOutClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxOutClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x710), + (uint32_t)bfValue, + 0x7000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 RX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxOutClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x710), + &rxBfData[0], + 0x7000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x700), + (uint32_t)bfValue, + 0x80000, + 0x13); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x700), + &rxBfData[0], + 0x80000, + 0xD3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x710), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x710), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x700), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x700), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 GT RX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x704), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x714), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x714), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x714), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x714), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Receiver PRBS Error Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxPrbsErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPrbsErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x724), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxPrbsErrCntRstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPrbsErrCntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPrbsErrCntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x720), + (uint32_t)bfValue, + 0x100000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxPrbsErrCntRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPrbsErrCntRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x720), + &rxBfData[0], + 0x100000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x720), + (uint32_t)bfValue, + 0xF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x720), + &rxBfData[0], + 0xF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x714), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x714), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x700), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x700), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 GT RX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6RxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6RxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x704), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6Tx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6Tx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6Tx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x718), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6Tx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6Tx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x718), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x704), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x704), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxDiffControlBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxDiffControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxDiffControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x718), + (uint32_t)bfValue, + 0x1F000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxDiffControlBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxDiffControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x718), + &rxBfData[0], + 0x1F000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 TX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxOutClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxOutClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x710), + (uint32_t)bfValue, + 0x700, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 TX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxOutClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x710), + &rxBfData[0], + 0x700, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x700), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x700), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x710), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x710), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x700), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x700), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 GT TX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x704), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x718), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x718), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPostcursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPostcursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPostcursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x718), + (uint32_t)bfValue, + 0x1F00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPostcursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPostcursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x718), + &rxBfData[0], + 0x1F00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x718), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x718), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPrbsInjErrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPrbsInjErrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPrbsInjErrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x720), + (uint32_t)bfValue, + 0x10000000, + 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPrbsInjErrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPrbsInjErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x720), + &rxBfData[0], + 0x10000000, + 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x720), + (uint32_t)bfValue, + 0xF000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x720), + &rxBfData[0], + 0xF000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPrecursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPrecursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPrecursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x718), + (uint32_t)bfValue, + 0x1F0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxPrecursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxPrecursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x718), + &rxBfData[0], + 0x1F0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x718), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x718), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x700), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 6 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x700), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 6 GT TX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel6TxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel6TxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x704), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Channel PLL Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7CpllLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7CpllLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x810), + &rxBfData[0], + 0x4000000, + 0xDA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7CpllPdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7CpllPdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7CpllPdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x810), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Channel PLL Powerdown + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7CpllPdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7CpllPdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x810), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7CpllRefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7CpllRefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7CpllRefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x810), + (uint32_t)bfValue, + 0x70000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Channel PLL Reference Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7CpllRefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7CpllRefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x810), + &rxBfData[0], + 0x70000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1023U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x840), + (uint32_t)bfValue, + 0x3FF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x840), + &rxBfData[0], + 0x3FF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x840), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x840), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x84C), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x84C), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x84C), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x840), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x840), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x844), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x844), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x848), + (uint32_t)bfValue, + 0xFFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x848), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x848), + (uint32_t)bfValue, + 0xFFFF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x848), + &rxBfData[0], + 0xFFFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x840), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x840), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7GtpowergoodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7GtpowergoodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7GtpowergoodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x804), + (uint32_t)bfValue, + 0x80000000, + 0x1F); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 GT Power Good + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7GtpowergoodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7GtpowergoodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x804), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7LoopbackBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7LoopbackBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7LoopbackBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x820), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 GT Loopback + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7LoopbackBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7LoopbackBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x820), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7Rx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7Rx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7Rx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x814), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7Rx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7Rx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x814), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxBufResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxBufResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxBufResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x800), + (uint32_t)bfValue, + 0x100000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 GT RX Elastic Buffer Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxBufResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxBufResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x800), + &rxBfData[0], + 0x100000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x804), + (uint32_t)bfValue, + 0x700000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x804), + &rxBfData[0], + 0x700000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive CDR Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxCdrHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxCdrHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxCdrHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x814), + (uint32_t)bfValue, + 0x1000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive CDR Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxCdrHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxCdrHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x814), + &rxBfData[0], + 0x1000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxCdrlockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxCdrlockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxCdrlockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x804), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive CDR Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxCdrlockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxCdrlockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x804), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxCommaDetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxCommaDetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxCommaDetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x804), + (uint32_t)bfValue, + 0x1000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive Comma Detection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxCommaDetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxCommaDetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x804), + &rxBfData[0], + 0x1000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxDfeLpmEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxDfeLpmEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxDfeLpmEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x814), + (uint32_t)bfValue, + 0x100, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive DFE/LPM Enable Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxDfeLpmEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxDfeLpmEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x814), + &rxBfData[0], + 0x100, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxDfeLpmHoldBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxDfeLpmHoldBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxDfeLpmHoldBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x814), + (uint32_t)bfValue, + 0x200, + 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive DFE/LPM Hold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxDfeLpmHoldBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxDfeLpmHoldBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x814), + &rxBfData[0], + 0x200, + 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxDfeLpmOverrideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxDfeLpmOverrideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxDfeLpmOverrideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x814), + (uint32_t)bfValue, + 0x400, + 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive DFE/LPM Override + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxDfeLpmOverrideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxDfeLpmOverrideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x814), + &rxBfData[0], + 0x400, + 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxDfeLpmResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxDfeLpmResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxDfeLpmResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x800), + (uint32_t)bfValue, + 0x40000, + 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 GT RX DFE LPM Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxDfeLpmResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxDfeLpmResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x800), + &rxBfData[0], + 0x40000, + 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive Gearbox Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxGearboxSlipBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxGearboxSlipBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxGearboxSlipBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x814), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive Gearbox Slip + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxGearboxSlipBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxGearboxSlipBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x814), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 RX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxOutClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxOutClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x810), + (uint32_t)bfValue, + 0x7000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 RX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxOutClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x810), + &rxBfData[0], + 0x7000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x800), + (uint32_t)bfValue, + 0x80000, + 0x13); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 GT RX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x800), + &rxBfData[0], + 0x80000, + 0xD3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x810), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Receiver PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x810), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x800), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 GT RX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x800), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 GT RX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x804), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x814), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x814), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x814), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x814), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Receiver PRBS Error Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxPrbsErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPrbsErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x824), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxPrbsErrCntRstBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPrbsErrCntRstBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPrbsErrCntRstBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x820), + (uint32_t)bfValue, + 0x100000, + 0x14); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Receiver PRBS Error Counter Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxPrbsErrCntRstBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPrbsErrCntRstBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x820), + &rxBfData[0], + 0x100000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x820), + (uint32_t)bfValue, + 0xF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Receiver PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x820), + &rxBfData[0], + 0xF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x814), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Receive Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x814), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x800), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 GT RX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x800), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 GT RX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7RxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7RxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x804), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7Tx8b10bEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7Tx8b10bEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7Tx8b10bEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x818), + (uint32_t)bfValue, + 0x8, + 0x3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmit 8B10B Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7Tx8b10bEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7Tx8b10bEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x818), + &rxBfData[0], + 0x8, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxBufStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxBufStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxBufStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x804), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmit Buffer Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxBufStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxBufStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x804), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxDiffControlBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxDiffControlBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxDiffControlBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x818), + (uint32_t)bfValue, + 0x1F000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmit Differential Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxDiffControlBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxDiffControlBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x818), + &rxBfData[0], + 0x1F000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 TX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxOutClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxOutClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxOutClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x810), + (uint32_t)bfValue, + 0x700, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 TX Out Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxOutClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxOutClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x810), + &rxBfData[0], + 0x700, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPcsResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPcsResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPcsResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x800), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 GT TX PCS Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPcsResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPcsResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x800), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPllClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPllClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPllClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x810), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmitter PLL Clock Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPllClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPllClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x810), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPmaResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPmaResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPmaResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x800), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 GT TX PMA Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPmaResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPmaResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x800), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 GT TX PMA Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPmaResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPmaResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x804), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x818), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmit Polarity Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x818), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPostcursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPostcursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPostcursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x818), + (uint32_t)bfValue, + 0x1F00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmit Postcursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPostcursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPostcursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x818), + &rxBfData[0], + 0x1F00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPowerdownBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPowerdownBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPowerdownBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x818), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmit Power Down Control + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPowerdownBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPowerdownBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x818), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPrbsInjErrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPrbsInjErrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPrbsInjErrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x820), + (uint32_t)bfValue, + 0x10000000, + 0x1C); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmitter PRBS Inject Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPrbsInjErrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPrbsInjErrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x820), + &rxBfData[0], + 0x10000000, + 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPrbsSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPrbsSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPrbsSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x820), + (uint32_t)bfValue, + 0xF000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmitter PRBS Selection + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPrbsSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPrbsSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x820), + &rxBfData[0], + 0xF000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPrecursorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPrecursorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPrecursorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x818), + (uint32_t)bfValue, + 0x1F0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmit Precursor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxPrecursorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxPrecursorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x818), + &rxBfData[0], + 0x1F0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxRateBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxRateBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxRateBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x818), + (uint32_t)bfValue, + 0x70, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 Transmit Rate Final Divider + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxRateBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxRateBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x818), + &rxBfData[0], + 0x70, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x800), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Channel 7 GT TX Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x800), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Channel 7 GT TX Reset Done + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Channel7TxResetDoneBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Channel7TxResetDoneBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x804), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief MMCM Reference Clock Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9MmcmRefclkSelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9MmcmRefclkSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9MmcmRefclkSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief MMCM Reference Clock Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9MmcmRefclkSelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9MmcmRefclkSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9ModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9ModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9ModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9ModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 0 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x940), + (uint32_t)bfValue, + 0xFFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad 0 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x940), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 0 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x940), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad 0 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x940), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 0 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x94C), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 0 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x94C), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 0 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x94C), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 0 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x944), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad 0 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x944), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 0 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x948), + (uint32_t)bfValue, + 0xFFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad 0 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x948), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 0 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x948), + (uint32_t)bfValue, + 0xFFFF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad 0 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x948), + &rxBfData[0], + 0xFFFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 0 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x940), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad 0 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x940), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad PLL 0 Lock for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll0LockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll0LockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x910), + &rxBfData[0], + 0x8000, + 0xCF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad PLL 0 Powerdown for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll0PdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll0PdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll0PdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x910), + (uint32_t)bfValue, + 0x200, + 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad PLL 0 Powerdown for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll0PdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll0PdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x910), + &rxBfData[0], + 0x200, + 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad PLL 0 Reference Clock Selection for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll0RefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll0RefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll0RefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x910), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad PLL 0 Reference Clock Selection for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll0RefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll0RefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x910), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad PLL 0 Reset for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll0ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll0ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll0ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x910), + (uint32_t)bfValue, + 0x100, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad PLL 0 Reset for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll0ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll0ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x910), + &rxBfData[0], + 0x100, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad PLL 1 Lock for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll1LockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll1LockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x910), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad PLL 1 Powerdown for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll1PdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll1PdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll1PdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x910), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad PLL 1 Powerdown for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll1PdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll1PdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x910), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad PLL 1 Reference Clock Selection for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll1RefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll1RefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll1RefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x910), + (uint32_t)bfValue, + 0x70000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad PLL 1 Reference Clock Selection for Quad 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll1RefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll1RefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x910), + &rxBfData[0], + 0x70000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad PLL 1 Reset for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll1ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll1ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll1ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x910), + (uint32_t)bfValue, + 0x1000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad PLL 1 Reset for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad0Qpll1ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad0Qpll1ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x910), + &rxBfData[0], + 0x1000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 1 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1DrpAddressBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpAddressBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpAddressBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0xA40), + (uint32_t)bfValue, + 0xFFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad 1 DRP Address + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1DrpAddressBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpAddressBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xA40), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 1 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1DrpEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0xA40), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad 1 DRP Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1DrpEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xA40), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 1 DRP Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1DrpErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xA4C), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 1 DRP Read Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1DrpReadDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpReadDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xA4C), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 1 DRP Ready + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1DrpReadyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpReadyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xA4C), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 1 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1DrpTimeoutBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpTimeoutBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpTimeoutBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0xA44), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad 1 DRP Timeout + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1DrpTimeoutBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpTimeoutBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0xA44), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 1 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1DrpWriteDataBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpWriteDataBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpWriteDataBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0xA48), + (uint32_t)bfValue, + 0xFFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad 1 DRP Write Data + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1DrpWriteDataBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpWriteDataBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xA48), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 1 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1DrpWriteDataMaskBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpWriteDataMaskBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpWriteDataMaskBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0xA48), + (uint32_t)bfValue, + 0xFFFF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad 1 DRP Write Data Mask + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1DrpWriteDataMaskBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpWriteDataMaskBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xA48), + &rxBfData[0], + 0xFFFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Quad 1 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1DrpWriteEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpWriteEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpWriteEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0xA40), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad 1 DRP Write Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1DrpWriteEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1DrpWriteEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xA40), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad PLL 0 Lock for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll0LockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll0LockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xA10), + &rxBfData[0], + 0x8000, + 0xCF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad PLL 0 Powerdown for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll0PdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll0PdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll0PdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0xA10), + (uint32_t)bfValue, + 0x200, + 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad PLL 0 Powerdown for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll0PdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll0PdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xA10), + &rxBfData[0], + 0x200, + 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad PLL 0 Reference Clock Selection for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll0RefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll0RefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll0RefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0xA10), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad PLL 0 Reference Clock Selection for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll0RefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll0RefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xA10), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad PLL 0 Reset for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll0ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll0ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll0ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0xA10), + (uint32_t)bfValue, + 0x100, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad PLL 0 Reset for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll0ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll0ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xA10), + &rxBfData[0], + 0x100, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad PLL 1 Lock for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll1LockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll1LockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xA10), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad PLL 1 Powerdown for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll1PdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll1PdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll1PdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0xA10), + (uint32_t)bfValue, + 0x2000000, + 0x19); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad PLL 1 Powerdown for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll1PdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll1PdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xA10), + &rxBfData[0], + 0x2000000, + 0xD9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad PLL 1 Reference Clock Selection for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll1RefClkSelBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll1RefClkSelBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll1RefClkSelBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0xA10), + (uint32_t)bfValue, + 0x70000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad PLL 1 Reference Clock Selection for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll1RefClkSelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll1RefClkSelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xA10), + &rxBfData[0], + 0x70000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Quad PLL 1 Reset for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll1ResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll1ResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll1ResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0xA10), + (uint32_t)bfValue, + 0x1000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Quad PLL 1 Reset for Quad 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204PhyAds9ChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204PhyAds9Quad1Qpll1ResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_ADS9_JESD_PHY)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204PhyAds9Quad1Qpll1ResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xA10), + &rxBfData[0], + 0x1000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_jesd204_phy_ads9.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204_rx_lane_xbar.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204_rx_lane_xbar.c new file mode 100644 index 0000000..3538f79 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204_rx_lane_xbar.c @@ -0,0 +1,5080 @@ +/** + * \file fpga9025_bf_jesd204_rx_lane_xbar.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_jesd204_rx_lane_xbar.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Lane 0 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane0SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane0SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane0SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x10), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 0 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane0SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane0SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 10 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane10SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane10SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane10SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x38), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 10 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane10SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane10SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x38), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 11 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane11SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane11SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane11SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x3C), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 11 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane11SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane11SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x3C), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 12 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane12SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane12SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane12SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x40), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 12 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane12SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane12SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x40), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 13 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane13SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane13SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane13SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x44), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 13 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane13SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane13SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x44), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 14 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane14SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane14SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane14SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x48), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 14 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane14SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane14SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x48), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 15 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane15SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane15SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane15SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4C), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 15 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane15SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane15SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4C), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 16 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane16SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane16SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane16SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x50), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 16 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane16SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane16SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x50), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 17 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane17SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane17SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane17SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x54), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 17 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane17SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane17SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x54), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 18 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane18SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane18SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane18SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x58), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 18 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane18SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane18SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x58), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 19 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane19SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane19SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane19SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x5C), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 19 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane19SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane19SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x5C), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 1 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane1SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane1SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane1SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x14), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 1 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane1SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane1SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x14), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 20 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane20SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane20SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane20SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x60), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 20 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane20SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane20SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x60), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 21 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane21SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane21SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane21SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x64), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 21 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane21SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane21SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 22 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane22SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane22SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane22SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x68), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 22 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane22SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane22SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x68), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 23 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane23SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane23SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane23SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x6C), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 23 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane23SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane23SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x6C), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 24 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane24SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane24SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane24SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x70), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 24 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane24SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane24SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x70), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 25 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane25SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane25SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane25SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x74), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 25 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane25SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane25SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x74), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 26 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane26SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane26SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane26SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x78), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 26 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane26SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane26SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x78), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 27 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane27SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane27SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane27SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x7C), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 27 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane27SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane27SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x7C), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 28 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane28SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane28SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane28SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x80), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 28 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane28SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane28SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 29 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane29SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane29SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane29SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x84), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 29 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane29SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane29SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x84), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 2 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane2SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane2SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane2SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x18), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 2 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane2SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane2SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 30 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane30SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane30SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane30SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x88), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 30 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane30SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane30SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x88), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 31 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane31SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane31SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane31SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8C), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 31 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane31SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane31SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8C), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 3 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane3SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane3SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane3SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x1C), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 3 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane3SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane3SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 4 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane4SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane4SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane4SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x20), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 4 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane4SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane4SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 5 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane5SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane5SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane5SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x24), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 5 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane5SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane5SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x24), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 6 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane6SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane6SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane6SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x28), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 6 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane6SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane6SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x28), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 7 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane7SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane7SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane7SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x2C), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 7 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane7SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane7SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x2C), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 8 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane8SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane8SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane8SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x30), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 8 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane8SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane8SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x30), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 9 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane9SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLane9SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane9SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x34), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 9 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLane9SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLane9SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x34), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLaneResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204RxLaneXbarLaneResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLaneResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x4), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarLaneResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarLaneResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204RxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204RxLaneXbarModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1) && + (baseAddr != FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204RxLaneXbarModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_jesd204_rx_lane_xbar.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204_sysref_control.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204_sysref_control.c new file mode 100644 index 0000000..582f50f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204_sysref_control.c @@ -0,0 +1,1387 @@ +/** + * \file fpga9025_bf_jesd204_sysref_control.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_jesd204_sysref_control.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief External SYSREF Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlExtSysrefPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204SysrefControlExtSysrefPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlExtSysrefPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x20000, + 0x11); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External SYSREF Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlExtSysrefPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlExtSysrefPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x20000, + 0xD1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief External SYSREF Request + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlExtSysrefRequestBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204SysrefControlExtSysrefRequestBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlExtSysrefRequestBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x40000, + 0x12); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External SYSREF Request + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlExtSysrefRequestBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlExtSysrefRequestBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x40000, + 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief External SYSREF Sample Edge + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlExtSysrefSampleEdgeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204SysrefControlExtSysrefSampleEdgeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlExtSysrefSampleEdgeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief External SYSREF Sample Edge + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlExtSysrefSampleEdgeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlExtSysrefSampleEdgeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Internal SYSREF Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlIntSysrefEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204SysrefControlIntSysrefEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlIntSysrefEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Internal SYSREF Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlIntSysrefEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlIntSysrefEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Internal SYSREF Free Run + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlIntSysrefFreerunBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204SysrefControlIntSysrefFreerunBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlIntSysrefFreerunBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Internal SYSREF Free Run + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlIntSysrefFreerunBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlIntSysrefFreerunBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Internal SYSREF Generator Period + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlIntSysrefGenPeriodBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204SysrefControlIntSysrefGenPeriodBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlIntSysrefGenPeriodBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0xC), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Internal SYSREF Generator Period + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlIntSysrefGenPeriodBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlIntSysrefGenPeriodBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Internal SYSREF Request + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlIntSysrefRequestBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204SysrefControlIntSysrefRequestBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlIntSysrefRequestBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Internal SYSREF Request + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlIntSysrefRequestBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlIntSysrefRequestBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief SYSREF Output Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlOutputEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204SysrefControlOutputEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlOutputEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x10), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief SYSREF Output Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlOutputEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlOutputEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief SYSREF Received + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204SysrefControlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204SysrefControlSysrefReceivedBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204SysrefControlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_SYSREF_CONTROL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204SysrefControlSysrefReceivedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_jesd204_sysref_control.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204_test_det_lat.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204_test_det_lat.c new file mode 100644 index 0000000..f5c1a2a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204_test_det_lat.c @@ -0,0 +1,812 @@ +/** + * \file fpga9025_bf_jesd204_test_det_lat.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_jesd204_test_det_lat.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TestDetLatChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TestDetLatEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TestDetLatEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TEST_DET_LAT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TestDetLatEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TestDetLatChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TestDetLatEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TEST_DET_LAT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TestDetLatEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Round Trip Latency + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TestDetLatChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TestDetLatLatencyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TEST_DET_LAT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TestDetLatLatencyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TestDetLatChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TestDetLatModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TEST_DET_LAT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TestDetLatModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TestDetLatChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TestDetLatModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TEST_DET_LAT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TestDetLatModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Receive Link + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TestDetLatChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TestDetLatRxLinkBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TestDetLatRxLinkBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TEST_DET_LAT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TestDetLatRxLinkBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x300, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Receive Link + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TestDetLatChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TestDetLatRxLinkBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TEST_DET_LAT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TestDetLatRxLinkBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x300, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Transmit Link + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TestDetLatChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TestDetLatTxLinkBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TestDetLatTxLinkBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TEST_DET_LAT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TestDetLatTxLinkBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x30, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Transmit Link + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TestDetLatChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TestDetLatTxLinkBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TEST_DET_LAT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TestDetLatTxLinkBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x30, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Valid Data Width + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TestDetLatChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TestDetLatValidDataWidthBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TestDetLatValidDataWidthBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TEST_DET_LAT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TestDetLatValidDataWidthBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0xF000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Valid Data Width + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TestDetLatChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TestDetLatValidDataWidthBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TestDetLatChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TEST_DET_LAT)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TestDetLatValidDataWidthBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0xF000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_jesd204_test_det_lat.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204_tx_lane_xbar.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204_tx_lane_xbar.c new file mode 100644 index 0000000..6f50089 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204_tx_lane_xbar.c @@ -0,0 +1,5012 @@ +/** + * \file fpga9025_bf_jesd204_tx_lane_xbar.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_jesd204_tx_lane_xbar.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Lane 0 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane0SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane0SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane0SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x10), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 0 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane0SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane0SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 10 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane10SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane10SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane10SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x38), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 10 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane10SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane10SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x38), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 11 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane11SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane11SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane11SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x3C), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 11 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane11SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane11SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x3C), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 12 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane12SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane12SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane12SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x40), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 12 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane12SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane12SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x40), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 13 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane13SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane13SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane13SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x44), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 13 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane13SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane13SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x44), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 14 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane14SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane14SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane14SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x48), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 14 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane14SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane14SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x48), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 15 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane15SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane15SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane15SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4C), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 15 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane15SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane15SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4C), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 16 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane16SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane16SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane16SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x50), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 16 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane16SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane16SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x50), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 17 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane17SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane17SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane17SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x54), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 17 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane17SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane17SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x54), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 18 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane18SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane18SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane18SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x58), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 18 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane18SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane18SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x58), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 19 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane19SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane19SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane19SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x5C), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 19 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane19SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane19SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x5C), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 1 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane1SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane1SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane1SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x14), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 1 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane1SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane1SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x14), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 20 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane20SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane20SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane20SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x60), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 20 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane20SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane20SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x60), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 21 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane21SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane21SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane21SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x64), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 21 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane21SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane21SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 22 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane22SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane22SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane22SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x68), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 22 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane22SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane22SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x68), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 23 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane23SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane23SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane23SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x6C), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 23 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane23SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane23SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x6C), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 24 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane24SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane24SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane24SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x70), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 24 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane24SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane24SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x70), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 25 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane25SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane25SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane25SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x74), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 25 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane25SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane25SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x74), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 26 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane26SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane26SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane26SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x78), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 26 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane26SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane26SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x78), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 27 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane27SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane27SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane27SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x7C), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 27 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane27SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane27SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x7C), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 28 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane28SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane28SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane28SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x80), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 28 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane28SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane28SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 29 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane29SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane29SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane29SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x84), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 29 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane29SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane29SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x84), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 2 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane2SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane2SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane2SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x18), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 2 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane2SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane2SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 30 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane30SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane30SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane30SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x88), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 30 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane30SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane30SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x88), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 31 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane31SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane31SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane31SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8C), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 31 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane31SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane31SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8C), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 3 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane3SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane3SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane3SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x1C), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 3 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane3SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane3SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 4 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane4SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane4SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane4SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x20), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 4 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane4SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane4SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 5 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane5SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane5SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane5SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x24), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 5 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane5SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane5SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x24), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 6 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane6SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane6SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane6SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x28), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 6 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane6SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane6SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x28), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 7 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane7SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane7SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane7SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x2C), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 7 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane7SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane7SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x2C), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 8 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane8SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane8SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane8SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x30), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 8 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane8SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane8SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x30), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane 9 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane9SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLane9SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane9SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x34), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane 9 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLane9SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLane9SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x34), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLaneResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204TxLaneXbarLaneResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLaneResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x4), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarLaneResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarLaneResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204TxLaneXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204TxLaneXbarModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0) && + (baseAddr != FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204TxLaneXbarModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_jesd204_tx_lane_xbar.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204b_sync_xbar.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204b_sync_xbar.c new file mode 100644 index 0000000..a7dcffd --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_jesd204b_sync_xbar.c @@ -0,0 +1,1757 @@ +/** + * \file fpga9025_bf_jesd204b_sync_xbar.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_jesd204b_sync_xbar.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Module Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarModuleVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarModuleVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Module Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarModuleVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarModuleVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Sync Input Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncInPolarityBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204bSyncXbarSyncInPolarityBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncInPolarityBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Sync Input Polarity + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncInPolarityBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncInPolarityBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Sync 0 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOut0SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut0SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut0SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x10), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Sync 0 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOut0SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut0SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Sync 1 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOut1SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut1SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut1SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x14), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Sync 1 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOut1SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut1SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x14), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Sync 2 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOut2SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut2SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut2SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x18), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Sync 2 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOut2SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut2SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Sync 3 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOut3SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut3SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut3SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x1C), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Sync 3 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOut3SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut3SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Sync 4 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOut4SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut4SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut4SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x20), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Sync 4 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOut4SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut4SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Sync 5 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOut5SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut5SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut5SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x24), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Sync 5 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOut5SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut5SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x24), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Sync 6 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOut6SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut6SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut6SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x28), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Sync 6 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOut6SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut6SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x28), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Sync 7 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOut7SelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut7SelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut7SelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x2C), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Sync 7 Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOut7SelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOut7SelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x2C), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Sync Output Force Output + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOutForceOutputBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204bSyncXbarSyncOutForceOutputBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOutForceOutputBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0xFF00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Sync Output Force Output + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOutForceOutputBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOutForceOutputBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0xFF00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Sync Output Force Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOutForceValueBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_Jesd204bSyncXbarSyncOutForceValueBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOutForceValueBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Sync Output Force Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfJesd204bSyncXbarChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_Jesd204bSyncXbarSyncOutForceValueBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_SYNC_XBAR)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_Jesd204bSyncXbarSyncOutForceValueBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_jesd204b_sync_xbar.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_orx_pin_encode_tokelau.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_orx_pin_encode_tokelau.c new file mode 100644 index 0000000..513f1fc --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_orx_pin_encode_tokelau.c @@ -0,0 +1,1467 @@ +/** + * \file fpga9025_bf_orx_pin_encode_tokelau.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_orx_pin_encode_tokelau.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Enable Fast Switching Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauFastSwitchingEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_OrxPinEncodeTokelauFastSwitchingEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauFastSwitchingEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Enable Fast Switching Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauFastSwitchingEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauFastSwitchingEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Mode 1A ORX Select High + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauMode1aOrxSelectHighBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_OrxPinEncodeTokelauMode1aOrxSelectHighBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauMode1aOrxSelectHighBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0xC00, + 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Mode 1A ORX Select High + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauMode1aOrxSelectHighBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauMode1aOrxSelectHighBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0xC00, + 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Mode 1A ORX Select Low + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauMode1aOrxSelectLowBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_OrxPinEncodeTokelauMode1aOrxSelectLowBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauMode1aOrxSelectLowBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x300, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Mode 1A ORX Select Low + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauMode1aOrxSelectLowBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauMode1aOrxSelectLowBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x300, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Mode 3 ORX Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauMode3OrxSelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_OrxPinEncodeTokelauMode3OrxSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauMode3OrxSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x3000, + 0xC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Mode 3 ORX Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauMode3OrxSelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauMode3OrxSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x3000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Mode Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauModeSelectBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_OrxPinEncodeTokelauModeSelectBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauModeSelectBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Mode Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauModeSelectBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauModeSelectBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Minimum ORX Enable High Time + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauOrxEnableHighTimeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_OrxPinEncodeTokelauOrxEnableHighTimeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauOrxEnableHighTimeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x14), + (uint32_t)bfValue, + 0xFFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Minimum ORX Enable High Time + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauOrxEnableHighTimeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauOrxEnableHighTimeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x14), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Minimum ORX Enable Low Time + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauOrxEnableLowTimeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_OrxPinEncodeTokelauOrxEnableLowTimeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauOrxEnableLowTimeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x18), + (uint32_t)bfValue, + 0xFFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Minimum ORX Enable Low Time + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauOrxEnableLowTimeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauOrxEnableLowTimeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief ORX Select Setup Time + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauOrxSelectSetupTimeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 65535U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_OrxPinEncodeTokelauOrxSelectSetupTimeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauOrxSelectSetupTimeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x10), + (uint32_t)bfValue, + 0xFFFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief ORX Select Setup Time + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauOrxSelectSetupTimeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauOrxSelectSetupTimeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_OrxPinEncodeTokelauResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauResetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauResetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfOrxPinEncodeTokelauChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_OrxPinEncodeTokelauVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfOrxPinEncodeTokelauChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ORX_PIN_ENCODE)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_OrxPinEncodeTokelauVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_orx_pin_encode_tokelau.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_tdd_dp_ctrl.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_tdd_dp_ctrl.c new file mode 100644 index 0000000..8994053 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_tdd_dp_ctrl.c @@ -0,0 +1,473 @@ +/** + * \file fpga9025_bf_tdd_dp_ctrl.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_tdd_dp_ctrl.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Enable Bit for the Datapath Control Module + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddDpCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddDpCtrlEnableBitBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddDpCtrlChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddDpCtrlEnableBitBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_0) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_1) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_0) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_2) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddDpCtrlEnableBitBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Enable Bit for the Datapath Control Module + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddDpCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddDpCtrlEnableBitBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddDpCtrlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_0) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_1) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_0) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_2) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddDpCtrlEnableBitBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Start Value for Datapath Control Module + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddDpCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddDpCtrlStartValueBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddDpCtrlChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddDpCtrlStartValueBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_0) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_1) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_0) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_2) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddDpCtrlStartValueBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x4), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Start Value for Datapath Control Module + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddDpCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddDpCtrlStartValueBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddDpCtrlChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_0) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_1) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_0) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_2) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddDpCtrlStartValueBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddDpCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddDpCtrlVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddDpCtrlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_0) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_1) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_0) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_2) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddDpCtrlVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddDpCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddDpCtrlVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddDpCtrlChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_0) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_1) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_0) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_2) && + (baseAddr != FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddDpCtrlVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_tdd_dp_ctrl.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_tdd_enable_ctrl.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_tdd_enable_ctrl.c new file mode 100644 index 0000000..8147487 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_tdd_enable_ctrl.c @@ -0,0 +1,2097 @@ +/** + * \file fpga9025_bf_tdd_enable_ctrl.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_tdd_enable_ctrl.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Enable Bit + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddEnableCtrlEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0xC), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Enable Bit + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief End Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlEndValueBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddEnableCtrlEndValueBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlEndValueBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x8), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief End Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlEndValueBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlEndValueBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Active Frames + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlFramesActiveBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddEnableCtrlFramesActiveBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlFramesActiveBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x20), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Active Frames + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlFramesActiveBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlFramesActiveBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Inactive Frames + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlFramesInactiveBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddEnableCtrlFramesInactiveBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlFramesInactiveBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x24), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Inactive Frames + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlFramesInactiveBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlFramesInactiveBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x24), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Frames Offset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlFramesOffsetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddEnableCtrlFramesOffsetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlFramesOffsetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x1C), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Frames Offset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlFramesOffsetBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlFramesOffsetBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Manual TDD Enable Signal + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlManualEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddEnableCtrlManualEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlManualEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x28), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Manual TDD Enable Signal + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlManualEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlManualEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x28), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Secondary Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlSecEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddEnableCtrlSecEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlSecEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x18), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Secondary Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlSecEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlSecEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Secondary End Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlSecEndValueBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddEnableCtrlSecEndValueBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlSecEndValueBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x14), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Secondary End Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlSecEndValueBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlSecEndValueBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x14), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Secondary Start Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlSecStartValueBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddEnableCtrlSecStartValueBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlSecStartValueBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x10), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Secondary Start Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlSecStartValueBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlSecStartValueBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Start Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlStartValueBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddEnableCtrlStartValueBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlStartValueBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x4), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Start Value + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlStartValueBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlStartValueBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddEnableCtrlChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddEnableCtrlVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddEnableCtrlChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_RX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4) && + (baseAddr != FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddEnableCtrlVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_tdd_enable_ctrl.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_tdd_frame_cnt.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_tdd_frame_cnt.c new file mode 100644 index 0000000..681f343 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_tdd_frame_cnt.c @@ -0,0 +1,881 @@ +/** + * \file fpga9025_bf_tdd_frame_cnt.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_tdd_frame_cnt.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Enable Bit + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddFrameCntEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddFrameCntEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddFrameCntEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Enable Bit + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddFrameCntEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddFrameCntEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief End Value Indicates the End of Frame Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddFrameCntEndValueBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddFrameCntEndValueBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddFrameCntEndValueBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x4), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief End Value Indicates the End of Frame Counter + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddFrameCntEndValueBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddFrameCntEndValueBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Loop Count for the Frame Counter to Roll Over + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddFrameCntLoopCountBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddFrameCntLoopCountBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddFrameCntLoopCountBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0xC), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Loop Count for the Frame Counter to Roll Over + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddFrameCntLoopCountBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddFrameCntLoopCountBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Loop Count Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddFrameCntLoopCountEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddFrameCntLoopCountEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddFrameCntLoopCountEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x10), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Loop Count Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddFrameCntLoopCountEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddFrameCntLoopCountEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Trigger Bit + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddFrameCntTriggerBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_TddFrameCntTriggerBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddFrameCntTriggerBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Trigger Bit + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddFrameCntTriggerBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddFrameCntTriggerBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Major Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddFrameCntVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddFrameCntVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Minor Version + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfTddFrameCntChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_TddFrameCntVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfTddFrameCntChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_TDD_FRAME_COUNTER)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_TddFrameCntVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_tdd_frame_cnt.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_xilinx_clock_wizard.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_xilinx_clock_wizard.c new file mode 100644 index 0000000..4f9d97f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_xilinx_clock_wizard.c @@ -0,0 +1,4532 @@ +/** + * \file fpga9025_bf_xilinx_clock_wizard.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_xilinx_clock_wizard.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Feedback Clock Multiplier Fractional Portion + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkfboutFracBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1023U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkfboutFracBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkfboutFracBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x200), + (uint32_t)bfValue, + 0x3FF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Feedback Clock Multiplier Fractional Portion + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkfboutFracBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkfboutFracBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x200), + &rxBfData[0], + 0x3FF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Feedback Clock Multiplier + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkfboutMultBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkfboutMultBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkfboutMultBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x200), + (uint32_t)bfValue, + 0xFF00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Feedback Clock Multiplier + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkfboutMultBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkfboutMultBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x200), + &rxBfData[0], + 0xFF00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Feedback Clock Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkfboutPhaseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkfboutPhaseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkfboutPhaseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x204), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Feedback Clock Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkfboutPhaseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkfboutPhaseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x204), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 0 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout0DivideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout0DivideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout0DivideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x208), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 0 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout0DivideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout0DivideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x208), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 0 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout0DutyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout0DutyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout0DutyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x210), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 0 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout0DutyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout0DutyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x210), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 0 Fractional Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout0FracBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1023U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout0FracBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout0FracBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x208), + (uint32_t)bfValue, + 0x3FF00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 0 Fractional Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout0FracBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout0FracBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x208), + &rxBfData[0], + 0x3FF00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 0 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout0PhaseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout0PhaseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout0PhaseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x20C), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 0 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout0PhaseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout0PhaseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x20C), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 1 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout1DivideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout1DivideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout1DivideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x214), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 1 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout1DivideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout1DivideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x214), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 1 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout1DutyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout1DutyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout1DutyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x21C), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 1 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout1DutyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout1DutyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x21C), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 1 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout1PhaseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout1PhaseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout1PhaseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x218), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 1 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout1PhaseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout1PhaseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x218), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 2 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout2DivideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout2DivideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout2DivideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x220), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 2 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout2DivideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout2DivideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x220), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 2 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout2DutyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout2DutyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout2DutyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x228), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 2 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout2DutyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout2DutyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x228), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 2 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout2PhaseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout2PhaseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout2PhaseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x224), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 2 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout2PhaseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout2PhaseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x224), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 3 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout3DivideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout3DivideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout3DivideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x22C), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 3 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout3DivideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout3DivideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x22C), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 3 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout3DutyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout3DutyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout3DutyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x234), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 3 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout3DutyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout3DutyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x234), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 3 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout3PhaseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout3PhaseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout3PhaseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x230), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 3 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout3PhaseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout3PhaseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x230), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 4 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout4DivideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout4DivideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout4DivideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x238), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 4 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout4DivideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout4DivideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x238), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 4 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout4DutyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout4DutyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout4DutyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x240), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 4 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout4DutyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout4DutyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x240), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 4 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout4PhaseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout4PhaseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout4PhaseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x23C), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 4 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout4PhaseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout4PhaseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x23C), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 5 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout5DivideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout5DivideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout5DivideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x244), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 5 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout5DivideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout5DivideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x244), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 5 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout5DutyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout5DutyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout5DutyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x24C), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 5 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout5DutyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout5DutyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x24C), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 5 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout5PhaseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout5PhaseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout5PhaseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x248), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 5 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout5PhaseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout5PhaseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x248), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 6 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout6DivideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout6DivideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout6DivideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x250), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 6 Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout6DivideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout6DivideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x250), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 6 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout6DutyBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout6DutyBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout6DutyBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x258), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 6 Duty Cycle + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout6DutyBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout6DutyBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x258), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Clock Output 6 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout6PhaseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardClkout6PhaseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout6PhaseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x254), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Clock Output 6 Phase + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardClkout6PhaseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardClkout6PhaseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x254), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief DIVCLK Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardDivclkDivideBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardDivclkDivideBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardDivclkDivideBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x200), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief DIVCLK Divide + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardDivclkDivideBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardDivclkDivideBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x200), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Error Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardErrorStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardErrorStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardInterruptEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardInterruptEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardInterruptEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x10), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Interrupt Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardInterruptEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardInterruptEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardInterruptStatusBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardInterruptStatusBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardInterruptStatusBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0xC), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Interrupt Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardInterruptStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardInterruptStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Load Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardLoadBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardLoadBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardLoadBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x25C), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Load Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardLoadBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardLoadBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x25C), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Locked + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardLockedBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardLockedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief SADDR + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardSaddrBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardSaddrBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardSaddrBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x25C), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief SADDR + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardSaddrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardSaddrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x25C), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Software Reset + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxClockWizardChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxClockWizardSoftwareResetBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxClockWizardSoftwareResetBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxClockWizardSoftwareResetBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x0), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/* EOF: fpga9025_bf_xilinx_clock_wizard.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_xilinx_jesd204b.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_xilinx_jesd204b.c new file mode 100644 index 0000000..45da35d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_xilinx_jesd204b.c @@ -0,0 +1,9217 @@ +/** + * \file fpga9025_bf_xilinx_jesd204b.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_xilinx_jesd204b.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Octets per Frame (F) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bCfgFBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bCfgFBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bCfgFBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x20), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Octets per Frame (F) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bCfgFBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bCfgFBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Frames per Multiframe (K) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bCfgKBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bCfgKBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bCfgKBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x24), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Frames per Multiframe (K) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bCfgKBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bCfgKBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x24), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief ID of Lane N + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bCfgLaneIdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bCfgLaneIdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bCfgLaneIdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bCfgLaneIdBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x400 + channelId * 4), + (uint32_t)bfValue, + 0x1F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief ID of Lane N + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bCfgLaneIdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bCfgLaneIdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) && + (channelId != 0x8) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bCfgLaneIdBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x400 + channelId * 4), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Subclass Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bCfgSubclassvBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bCfgSubclassvBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bCfgSubclassvBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x2C), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Subclass Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bCfgSubclassvBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bCfgSubclassvBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x2C), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Disable Error Reporting Using SYNC Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bDisErrOnSyncBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bDisErrOnSyncBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bDisErrOnSyncBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x34), + (uint32_t)bfValue, + 0x100, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Disable Error Reporting Using SYNC Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bDisErrOnSyncBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bDisErrOnSyncBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x34), + &rxBfData[0], + 0x100, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief ADJCNT (Phase Adjust Request) [Subclass 2 Only] + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaAdjcntBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaAdjcntBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaAdjcntBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaAdjcntBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x81C + channelId * 64), + (uint32_t)bfValue, + 0xF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief ADJCNT (Phase Adjust Request) [Subclass 2 Only] + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaAdjcntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaAdjcntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaAdjcntBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x81C + channelId * 64), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief ADJDIR (Adjust Direction) [Subclass 2 Only] + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaAdjdirBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaAdjdirBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaAdjdirBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaAdjdirBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x81C + channelId * 64), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief ADJDIR (Adjust Direction) [Subclass 2 Only] + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaAdjdirBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaAdjdirBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaAdjdirBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x81C + channelId * 64), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief BID (Bank ID) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaBidBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaBidBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaBidBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaBidBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x80C + channelId * 64), + (uint32_t)bfValue, + 0xF00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief BID (Bank ID) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaBidBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaBidBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaBidBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80C + channelId * 64), + &rxBfData[0], + 0xF00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief CF (Control Words per Frame) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaCfBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaCfBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaCfBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaCfBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x814 + channelId * 64), + (uint32_t)bfValue, + 0x1F000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief CF (Control Words per Frame) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaCfBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaCfBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaCfBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x814 + channelId * 64), + &rxBfData[0], + 0x1F000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief CS (Control Bits per Sample) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaCsBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaCsBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaCsBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaCsBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x810 + channelId * 64), + (uint32_t)bfValue, + 0x3000000, + 0x18); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief CS (Control Bits per Sample) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaCsBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaCsBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaCsBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x810 + channelId * 64), + &rxBfData[0], + 0x3000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief DID (Device ID) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaDidBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaDidBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaDidBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaDidBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x80C + channelId * 64), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief DID (Device ID) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaDidBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaDidBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaDidBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80C + channelId * 64), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief F (Octets per Frame) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaFBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaFBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaFBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x804 + channelId * 64), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief FCHK (Checksum) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaFchkBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaFchkBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaFchkBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaFchkBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x818 + channelId * 64), + (uint32_t)bfValue, + 0xFF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief FCHK (Checksum) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaFchkBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaFchkBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaFchkBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x818 + channelId * 64), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief HD (High Density Format) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaHdBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaHdBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaHdBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaHdBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x814 + channelId * 64), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief HD (High Density Format) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaHdBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaHdBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaHdBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x814 + channelId * 64), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief JESDV (JESD204 Version) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaJesdvBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaJesdvBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaJesdvBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x800 + channelId * 64), + &rxBfData[0], + 0x700, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief K (Frames per Multiframe) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaKBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaKBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaKBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x808 + channelId * 64), + &rxBfData[0], + 0x1F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief L (Lanes per Link) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaLBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaLBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaLBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80C + channelId * 64), + &rxBfData[0], + 0x1F000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief LID (Lane ID) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaLidBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaLidBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaLidBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x80C + channelId * 64), + &rxBfData[0], + 0x1F0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief M (Converters per Device) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaMBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaMBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaMBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaMBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x810 + channelId * 64), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief M (Converters per Device) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaMBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaMBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaMBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x810 + channelId * 64), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Multiframes in the Transmitted ILAS + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaMultiframesBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaMultiframesBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaMultiframesBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x14), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Multiframes in the Transmitted ILAS + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaMultiframesBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaMultiframesBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x14), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief N (Converter Resolution) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaNBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaNBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaNBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaNBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x810 + channelId * 64), + (uint32_t)bfValue, + 0x1F00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief N (Converter Resolution) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaNBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaNBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaNBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x810 + channelId * 64), + &rxBfData[0], + 0x1F00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief N' (Totals Bits per Sample) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaNpBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaNpBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaNpBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaNpBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x810 + channelId * 64), + (uint32_t)bfValue, + 0x1F0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief N' (Totals Bits per Sample) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaNpBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaNpBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaNpBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x810 + channelId * 64), + &rxBfData[0], + 0x1F0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief PHADJ (Phase Adjust Request) [Subclass 2 Only] + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaPhadjBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaPhadjBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaPhadjBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaPhadjBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x81C + channelId * 64), + (uint32_t)bfValue, + 0x100, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief PHADJ (Phase Adjust Request) [Subclass 2 Only] + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaPhadjBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaPhadjBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaPhadjBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x81C + channelId * 64), + &rxBfData[0], + 0x100, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief RES1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaRes1BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaRes1BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaRes1BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaRes1BfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x818 + channelId * 64), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief RES1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaRes1BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaRes1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaRes1BfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x818 + channelId * 64), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief RES2 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaRes2BfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaRes2BfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaRes2BfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaRes2BfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x818 + channelId * 64), + (uint32_t)bfValue, + 0xFF00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief RES2 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaRes2BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaRes2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaRes2BfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x818 + channelId * 64), + &rxBfData[0], + 0xFF00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief S (Samples per Converter per Frame) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaSBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 31U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaSBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaSBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaSBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x814 + channelId * 64), + (uint32_t)bfValue, + 0x1F00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief S (Samples per Converter per Frame) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaSBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaSBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaSBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x814 + channelId * 64), + &rxBfData[0], + 0x1F00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief SCR (Scrambling Enable) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaScrBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaScrBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaScrBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x814 + channelId * 64), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief SUBCLASS + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaSubclassBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaSubclassBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bIlaSubclassBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x800 + channelId * 64), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief ILA Support Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaSupportEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bIlaSupportEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaSupportEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x8), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief ILA Support Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bIlaSupportEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bIlaSupportEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x8), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane Alignment Error Detected Alarm + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLaneAlignAlarmBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLaneAlignAlarmBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x80000000, + 0xDF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lanes in Use + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLanesInUseBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bLanesInUseBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLanesInUseBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x28), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lanes in Use + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLanesInUseBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLanesInUseBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x28), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Debug Status Lane 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkDebugStatusLane0BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkDebugStatusLane0BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x3C), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Debug Status Lane 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkDebugStatusLane1BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkDebugStatusLane1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x3C), + &rxBfData[0], + 0xF0, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Debug Status Lane 2 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkDebugStatusLane2BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkDebugStatusLane2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x3C), + &rxBfData[0], + 0xF00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Debug Status Lane 3 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkDebugStatusLane3BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkDebugStatusLane3BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x3C), + &rxBfData[0], + 0xF000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Debug Status Lane 4 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkDebugStatusLane4BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkDebugStatusLane4BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x3C), + &rxBfData[0], + 0xF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Debug Status Lane 5 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkDebugStatusLane5BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkDebugStatusLane5BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x3C), + &rxBfData[0], + 0xF00000, + 0xD4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Debug Status Lane 6 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkDebugStatusLane6BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkDebugStatusLane6BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x3C), + &rxBfData[0], + 0xF000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Debug Status Lane 7 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkDebugStatusLane7BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkDebugStatusLane7BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x3C), + &rxBfData[0], + 0xF0000000, + 0xDC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Error Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkErrCntBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bLinkErrCntBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkErrCntBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bLinkErrCntBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x824 + channelId * 64), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Link Error Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bLinkErrCntBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x824 + channelId * 64), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Link Error Counters Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkErrCntrsEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bLinkErrCntrsEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkErrCntrsEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x34), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Link Error Counters Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkErrCntrsEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkErrCntrsEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x34), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Error Status, Lane 0 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkErrorStatusLane0BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkErrorStatusLane0BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Error Status, Lane 1 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkErrorStatusLane1BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkErrorStatusLane1BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x38, + 0xC3); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Error Status, Lane 2 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkErrorStatusLane2BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkErrorStatusLane2BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x1C0, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Error Status, Lane 3 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkErrorStatusLane3BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkErrorStatusLane3BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0xE00, + 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Error Status, Lane 4 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkErrorStatusLane4BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkErrorStatusLane4BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x7000, + 0xCC); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Error Status, Lane 5 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkErrorStatusLane5BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkErrorStatusLane5BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x38000, + 0xCF); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Error Status, Lane 6 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkErrorStatusLane6BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkErrorStatusLane6BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x1C0000, + 0xD2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Link Error Status, Lane 7 + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bLinkErrorStatusLane7BfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bLinkErrorStatusLane7BfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0xE00000, + 0xD5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Reset, Fixed + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bResetFixedBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bResetFixedBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bResetFixedBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Reset, Fixed + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bResetFixedBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bResetFixedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Reset, Self Clearing + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bResetSelfClearingBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bResetSelfClearingBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bResetSelfClearingBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Reset, Self Clearing + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bResetSelfClearingBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bResetSelfClearingBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief RX Buffer Adjust + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bRxBufAdjBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bRxBufAdjBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bRxBufAdjBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x830 + channelId * 64), + &rxBfData[0], + 0x3FF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief RX Buffer Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bRxBufferDelayBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint16_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1023U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bRxBufferDelayBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bRxBufferDelayBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x30), + (uint32_t)bfValue, + 0x3FF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief RX Buffer Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bRxBufferDelayBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bRxBufferDelayBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x30), + &rxBfData[0], + 0x3FF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief RX Buffer Overflow Alarm + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bRxBufferOvrfAlarmBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bRxBufferOvrfAlarmBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x20000000, + 0xDD); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Scrambling Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bScramblingEnBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bScramblingEnBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bScramblingEnBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0xC), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Scrambling Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bScramblingEnBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bScramblingEnBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0xC), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief SYNC Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bSyncStatusBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bSyncStatusBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x38), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief SYSREF Always + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bSysrefAlwaysBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bSysrefAlwaysBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bSysrefAlwaysBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x10), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief SYSREF Always + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bSysrefAlwaysBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bSysrefAlwaysBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief SYSREF Captured (Subclass 1 Only) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bSysrefCapturedBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bSysrefCapturedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x38), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief SYSREF Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bSysrefDelayBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bSysrefDelayBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bSysrefDelayBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x10), + (uint32_t)bfValue, + 0xF00, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief SYSREF Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bSysrefDelayBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bSysrefDelayBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0xF00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief SYSREF LMFC Alarm (Subclass 1 Only) + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bSysrefLmfcAlarmBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bSysrefLmfcAlarmBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x1C), + &rxBfData[0], + 0x40000000, + 0xDE); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief SYSREF Required on Re-Sync + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bSysrefRequiredOnResyncBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bSysrefRequiredOnResyncBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bSysrefRequiredOnResyncBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x10), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief SYSREF Required on Re-Sync + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bSysrefRequiredOnResyncBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bSysrefRequiredOnResyncBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x10), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Test Mode Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bTestModeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bTestModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bTestModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x18), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Test Mode Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bTestModeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bTestModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x18), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Test Mode Error Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bTestModeErrCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bTestModeErrCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bTestModeErrCntBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x820 + channelId * 64), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Test Mode ILA Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bTestModeIlaCntBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bTestModeIlaCntBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bTestModeIlaCntBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bTestModeIlaCntBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x828 + channelId * 64), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Test Mode ILA Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bTestModeIlaCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bTestModeIlaCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bTestModeIlaCntBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x828 + channelId * 64), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Test Mode Multiframe Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bTestModeMfCntBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 4294967295U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bTestModeMfCntBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bTestModeMfCntBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bTestModeMfCntBfSet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Write to Single Register */ + recoveryAction = fpga9025_BfRegisterWrite(device, + (baseAddr + 0x82C + channelId * 64), + ((uint32_t)bfValue)); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Test Mode Multiframe Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint32_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bTestModeMfCntBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t channelId, + uint32_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bTestModeMfCntBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204bTestModeMfCntBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read to Single Register */ + recoveryAction = fpga9025_BfRegisterRead(device, + (baseAddr + 0x82C + channelId * 64), + &rxBfData[0], + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint32_t)data; + + return recoveryAction; +} + +/** + * \brief Version Major + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Version Minor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Revision + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bVersionRevisionBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bVersionRevisionBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Watchdog Timer Disable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bWatchdogTimerDisableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204bWatchdogTimerDisableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bWatchdogTimerDisableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4), + (uint32_t)bfValue, + 0x10000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Watchdog Timer Disable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204bChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204bWatchdogTimerDisableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204bChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204B_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204B_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204bWatchdogTimerDisableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_xilinx_jesd204b.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_xilinx_jesd204c.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_xilinx_jesd204c.c new file mode 100644 index 0000000..57d08af --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_bf_xilinx_jesd204c.c @@ -0,0 +1,5489 @@ +/** + * \file fpga9025_bf_xilinx_jesd204c.c Automatically generated file with generator ver 0.0.1.0. + * + * \brief Contains BitField functions to support FPGA9025 transceiver device. + * + * FPGA9025 BITFIELD VERSION: 0.0.0.1 + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "./../../private/include/fpga9025_bf_xilinx_jesd204c.h" +#include "./../../private/include/fpga9025_bf_hal.h" +#include "adi_common_error.h" + +/** + * \brief Buffer Fill Level + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cBufferLevelBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cBufferLevelBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204cBufferLevelBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x400 + channelId * 128), + &rxBfData[0], + 0x3F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Buffer Overflow Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cBufferOverflowBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cBufferOverflowBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x60), + &rxBfData[0], + 0x400, + 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Multi-blocks in Extended Multi-blocks + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cCfgMbInEmbBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cCfgMbInEmbBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cCfgMbInEmbBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x30), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Multi-blocks in Extended Multi-blocks + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cCfgMbInEmbBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cCfgMbInEmbBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x30), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Subclass Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cCfgSubclassvBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cCfgSubclassvBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cCfgSubclassvBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x34), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Subclass Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cCfgSubclassvBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cCfgSubclassvBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x34), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Core is TX + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cCoreIsTxBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cCoreIsTxBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0x10000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief CRC Error Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cCrcErrorCountBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t channelId, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cCrcErrorCountBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204cCrcErrorCountBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x410 + channelId * 128), + &rxBfData[0], + 0xFFFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Enable Command Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cEnableCmdInterfaceBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cEnableCmdInterfaceBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cEnableCmdInterfaceBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x24), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Enable Command Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cEnableCmdInterfaceBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cEnableCmdInterfaceBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x24), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Enable Data Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cEnableDataInterfaceBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cEnableDataInterfaceBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cEnableDataInterfaceBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x24), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Enable Data Interface + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cEnableDataInterfaceBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cEnableDataInterfaceBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x24), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief FEC Corrected Error Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cFecCorrectedErrorCountBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t channelId, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cFecCorrectedErrorCountBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204cFecCorrectedErrorCountBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x414 + channelId * 128), + &rxBfData[0], + 0xFFFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief FEC Uncorrected Error Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint16_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cFecUncorrectedErrorCountBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t channelId, + uint16_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cFecUncorrectedErrorCountBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204cFecUncorrectedErrorCountBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x414 + channelId * 128), + &rxBfData[0], + 0xFFFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint16_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Status Block Sync Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqBlockSyncErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqBlockSyncErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x68), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Status CRC Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqCrcErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqCrcErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x68), + &rxBfData[0], + 0x100, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Enable Block Sync Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnBlockSyncErrorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cIrqEnBlockSyncErrorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnBlockSyncErrorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x64), + (uint32_t)bfValue, + 0x40, + 0x6); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Interrupt Enable Block Sync Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnBlockSyncErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnBlockSyncErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x40, + 0xC6); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Enable CRC Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnCrcErrorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cIrqEnCrcErrorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnCrcErrorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x64), + (uint32_t)bfValue, + 0x100, + 0x8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Interrupt Enable CRC Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnCrcErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnCrcErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x100, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Enable FEC Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnFecErrorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cIrqEnFecErrorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnFecErrorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x64), + (uint32_t)bfValue, + 0x200, + 0x9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Interrupt Enable FEC Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnFecErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnFecErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x200, + 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Global Interrupt Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnGlobalBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cIrqEnGlobalBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnGlobalBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x64), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Global Interrupt Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnGlobalBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnGlobalBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Enable Loss of Multi-block Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnLossMbLockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cIrqEnLossMbLockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnLossMbLockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x64), + (uint32_t)bfValue, + 0x20, + 0x5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Interrupt Enable Loss of Multi-block Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnLossMbLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnLossMbLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Enable Loss of 64b66b Sync Header Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnLossSyncHeaderLockBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cIrqEnLossSyncHeaderLockBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnLossSyncHeaderLockBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x64), + (uint32_t)bfValue, + 0x10, + 0x4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Interrupt Enable Loss of 64b66b Sync Header Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnLossSyncHeaderLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnLossSyncHeaderLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Enable Multi-block Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnMbErrorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cIrqEnMbErrorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnMbErrorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x64), + (uint32_t)bfValue, + 0x80, + 0x7); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Interrupt Enable Multi-block Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnMbErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnMbErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Enable Overflow Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnOverflowErrorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cIrqEnOverflowErrorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnOverflowErrorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x64), + (uint32_t)bfValue, + 0x400, + 0xA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Interrupt Enable Overflow Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnOverflowErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnOverflowErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x400, + 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Enable SYSREF Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnSysrefErrorBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cIrqEnSysrefErrorBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnSysrefErrorBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x64), + (uint32_t)bfValue, + 0x4, + 0x2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Interrupt Enable SYSREF Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnSysrefErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnSysrefErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Enable SYSREF Received + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnSysrefReceivedBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cIrqEnSysrefReceivedBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnSysrefReceivedBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x64), + (uint32_t)bfValue, + 0x2, + 0x1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Interrupt Enable SYSREF Received + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqEnSysrefReceivedBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqEnSysrefReceivedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x64), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Status FEC Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqFecErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqFecErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x68), + &rxBfData[0], + 0x200, + 0xC9); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Status Loss of Multi-block Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqLossMbLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqLossMbLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x68), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Status Loss of 64b66b Sync Header Lock + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqLossSyncHeaderLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqLossSyncHeaderLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x68), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Status Multi-block Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqMbErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqMbErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x68), + &rxBfData[0], + 0x80, + 0xC7); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Status Overflow Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqOverflowErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqOverflowErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x68), + &rxBfData[0], + 0x400, + 0xCA); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Pending + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqPendingBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqPendingBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x60), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Status SYSREF Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqSysrefErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqSysrefErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x68), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Interrupt Status SYSREF Received + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cIrqSysrefReceivedBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cIrqSysrefReceivedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x68), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane Indicator 64b66b Sync Header Aligned + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cLane64b66bAlignBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cLane64b66bAlignBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x54), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cLaneEnableBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 255U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cLaneEnableBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cLaneEnableBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x40), + (uint32_t)bfValue, + 0xFF, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Lane Enable + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cLaneEnableBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cLaneEnableBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x40), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Lane Indicator Multi-block Aligned + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cLaneMbAlignBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cLaneMbAlignBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x54), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Multi-block Lock Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cMbLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cMbLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x60), + &rxBfData[0], + 0x20, + 0xC5); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Meta Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cMetaModeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 3U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cMetaModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cMetaModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x38), + (uint32_t)bfValue, + 0x3, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Meta Mode + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cMetaModeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cMetaModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x38), + &rxBfData[0], + 0x3, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Multiblock Alignment Error Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cMulitblockAlignmentErrorCountBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cMulitblockAlignmentErrorCountBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204cMulitblockAlignmentErrorCountBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x410 + channelId * 128), + &rxBfData[0], + 0xFF00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Number of Lanes in Core + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cNumberOfLanesInCoreBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cNumberOfLanesInCoreBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4), + &rxBfData[0], + 0xF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Reset, Fixed + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cResetFixedBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cResetFixedBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cResetFixedBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x20), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Reset, Fixed + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cResetFixedBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cResetFixedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x20), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief RX Buffer Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cRxBufferDelayBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 63U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cRxBufferDelayBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cRxBufferDelayBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x44), + (uint32_t)bfValue, + 0x3F, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief RX Buffer Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cRxBufferDelayBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cRxBufferDelayBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x44), + &rxBfData[0], + 0x3F, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Multi-block Lock Threshold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cRxMbThBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 7U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cRxMbThBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cRxMbThBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x4C), + (uint32_t)bfValue, + 0x7, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Multi-block Lock Threshold + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cRxMbThBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cRxMbThBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x4C), + &rxBfData[0], + 0x7, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Sync Header Alignment Error Count + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param channelId Channel ID to be configured. + * Parameter is of type uint8_t + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cSyncHeaderAlignmentErrorCountBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t channelId, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cSyncHeaderAlignmentErrorCountBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + +#if FPGA9025_CHANNELID_CHECK > 0 + /* Channel ID check */ + if ( + (channelId != 0x0) && + (channelId != 0x1) && + (channelId != 0x2) && + (channelId != 0x3) && + (channelId != 0x4) && + (channelId != 0x5) && + (channelId != 0x6) && + (channelId != 0x7) + ) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + channelId, + "Invalid fpga9025_XilinxJesd204cSyncHeaderAlignmentErrorCountBfGet channelId"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x410 + channelId * 128), + &rxBfData[0], + 0xFF, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Sync Header Lock Status + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cSyncHeaderLockBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cSyncHeaderLockBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x60), + &rxBfData[0], + 0x10, + 0xC4); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief SYSREF Captured + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cSysrefCapturedBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cSysrefCapturedBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x60), + &rxBfData[0], + 0x2, + 0xC1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief SYSREF Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cSysrefDelayBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 15U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cSysrefDelayBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cSysrefDelayBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x50), + (uint32_t)bfValue, + 0xF0000, + 0x10); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief SYSREF Delay + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cSysrefDelayBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cSysrefDelayBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x50), + &rxBfData[0], + 0xF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief SYSREF Error + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cSysrefErrorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cSysrefErrorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x60), + &rxBfData[0], + 0x4, + 0xC2); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Test Mode Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cTestModeBfSet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_VALUE_CHECK > 0 + /* Range check */ + if ((bfValue < 0) || + (bfValue > 1U)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + bfValue, + "Invalid fpga9025_XilinxJesd204cTestModeBfSet parameter"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_VALUE_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cTestModeBfSet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfWriteCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write to Field */ + recoveryAction = fpga9025_BfFieldWrite(device, + (baseAddr + 0x48), + (uint32_t)bfValue, + 0x1, + 0x0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfWriteCacheFlush(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +/** + * \brief Test Mode Select + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cTestModeBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cTestModeBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x48), + &rxBfData[0], + 0x1, + 0xC0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Version Major + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cVersionMajorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cVersionMajorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF000000, + 0xD8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Version Minor + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cVersionMinorBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cVersionMinorBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF0000, + 0xD0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/** + * \brief Revision + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the FPGA9025 device data structure. + * \param baseAddr Base Address of instance to be configured. + * Parameter is of type ::fpga9025_BfXilinxJesd204cChanAddr_e. + * \param bfValue Data to be configured. Parameter is of type uint8_t. + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required. + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. + * + */ +int32_t fpga9025_XilinxJesd204cVersionRevisionBfGet(adi_fpga9025_Device_t* device, + fpga9025_BfXilinxJesd204cChanAddr_e baseAddr, + uint8_t* bfValue) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rxBfData[8] = {0}; + uint64_t data = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_BF); + +#if FPGA9025_BITFIELD_NULL_CHECK > 0 + /* NULL check */ + ADI_NULL_PTR_RETURN(&device->common, bfValue); +#endif /* FPGA9025_BITFIELD_NULL_CHECK */ + +#if FPGA9025_BITFIELD_ADDR_CHECK > 0 + /* Base Address check */ + if ((baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_1) && + (baseAddr != FPGA9025_BF_JESD204C_DEFRAMER_2) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_0) && + (baseAddr != FPGA9025_BF_JESD204C_FRAMER_1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEBF, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + baseAddr, + "Invalid fpga9025_XilinxJesd204cVersionRevisionBfGet Address"); + ADI_ERROR_RETURN(device->common.error.newAction); + } +#endif /* FPGA9025_BITFIELD_ADDR_CHECK */ + + recoveryAction = fpga9025_BfReadCacheInit(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Read Field */ + recoveryAction = fpga9025_BfFieldRead(device, + (baseAddr + 0x0), + &rxBfData[0], + 0xFF00, + 0xC8); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_BfReadAssembleData(device, + &rxBfData[0x0], + 0x1, + &data); + ADI_ERROR_RETURN(device->common.error.newAction); + + *bfValue = (uint8_t)data; + + return recoveryAction; +} + +/* EOF: fpga9025_bf_xilinx_jesd204c.c */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_jesd.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_jesd.c new file mode 100644 index 0000000..d91b736 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_jesd.c @@ -0,0 +1,3296 @@ +/** + * \file: fpga9025_jesd.c + * + * \brief Contains private jesd related functions + * + * FPGA9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9025_user.h" +#include "adi_fpga9025.h" +#include "adi_fpga9025_error.h" +#include "adi_fpga9025_jesd.h" +#include "../../private/include/fpga9025_jesd.h" +#include "../../private/include/fpga9025_bf_xilinx_jesd204b.h" +#include "../../private/include/fpga9025_bf_xilinx_jesd204c.h" + +int32_t fpga9025_Jesd204BDeframerCfgSet(adi_fpga9025_Device_t* device, + uint32_t deframerSelMask, + adi_fpga9025_DeframerCfg_t* deframerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + deframerCfg); + + if ((deframerSelMask < ADI_FPGA9025_DEFRAMER_0) || (deframerSelMask > ADI_FPGA9025_DEFRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelMask, + "Invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((deframerSelMask & ADI_FPGA9025_DEFRAMER_0) == ADI_FPGA9025_DEFRAMER_0) + { + /* set ILA multiframes to 4 multiframes */ + recoveryAction = fpga9025_XilinxJesd204bIlaMultiframesBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_0, + 3); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set deframer ila_multiframes"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Configure lane xbar */ + recoveryAction = adi_fpga9025_RxLaneXBarCfgSet(device, + ADI_FPGA9025_DEFRAMER_0, + deframerCfg->laneXbar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure ILA support */ + recoveryAction = fpga9025_XilinxJesd204bIlaSupportEnBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_0, + deframerCfg->ilaSupportEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Deframer 0 ILA support"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure scrambling */ + recoveryAction = fpga9025_XilinxJesd204bScramblingEnBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_0, + deframerCfg->scramblingEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 0 scrambling"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure SYSREF settings */ + recoveryAction = fpga9025_XilinxJesd204bSysrefAlwaysBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_0, + deframerCfg->sysRefAlways); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 0 SYSREF always"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204bSysrefDelayBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_0, + deframerCfg->sysRefDelay); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 0 SYSREF delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204bSysrefRequiredOnResyncBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_0, + deframerCfg->sysRefRequiredOnResync); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 0 SYSREF required on resync"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure octets per frame (F) */ + recoveryAction = fpga9025_XilinxJesd204bCfgFBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_0, + deframerCfg->cfgF - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 0 F"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure frames per multiframe (K) */ + recoveryAction = fpga9025_XilinxJesd204bCfgKBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_0, + deframerCfg->cfgK - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 0 K"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure lanes in use */ + recoveryAction = fpga9025_XilinxJesd204bLanesInUseBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_0, + deframerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 0 lanes in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure subclass */ + recoveryAction = fpga9025_XilinxJesd204bCfgSubclassvBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_0, + deframerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 0 subclass"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure RX buffer delay */ + recoveryAction = fpga9025_XilinxJesd204bRxBufferDelayBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_0, + deframerCfg->rxBufferDly); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 0 RX buffer delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure error reporting on sync disable */ + recoveryAction = fpga9025_XilinxJesd204bDisErrOnSyncBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_0, + deframerCfg->errReportingDisable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 0 error reporting on sync disable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* disable watchdog timer & set the self-clearing reset bit */ + recoveryAction = fpga9025_XilinxJesd204bWatchdogTimerDisableBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_0, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error disabling Deframer 0 watchdog timer"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((deframerSelMask & ADI_FPGA9025_DEFRAMER_1) == ADI_FPGA9025_DEFRAMER_1) + { + /* set ILA multiframes to 4 multiframes */ + recoveryAction = fpga9025_XilinxJesd204bIlaMultiframesBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_1, + 3); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set deframer ila_multiframes"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Configure lane xbar */ + recoveryAction = adi_fpga9025_RxLaneXBarCfgSet(device, + ADI_FPGA9025_DEFRAMER_1, + deframerCfg->laneXbar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure ILA support */ + recoveryAction = fpga9025_XilinxJesd204bIlaSupportEnBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_1, + deframerCfg->ilaSupportEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Deframer 2 ILA support"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure scrambling */ + recoveryAction = fpga9025_XilinxJesd204bScramblingEnBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_1, + deframerCfg->scramblingEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 scrambling"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure SYSREF settings */ + recoveryAction = fpga9025_XilinxJesd204bSysrefAlwaysBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_1, + deframerCfg->sysRefAlways); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 SYSREF always"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204bSysrefDelayBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_1, + deframerCfg->sysRefDelay); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 SYSREF delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204bSysrefRequiredOnResyncBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_1, + deframerCfg->sysRefRequiredOnResync); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 SYSREF required on resync"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure octets per frame (F) */ + recoveryAction = fpga9025_XilinxJesd204bCfgFBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_1, + deframerCfg->cfgF - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 F"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure frames per multiframe (K) */ + recoveryAction = fpga9025_XilinxJesd204bCfgKBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_1, + deframerCfg->cfgK - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 K"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure lanes in use */ + recoveryAction = fpga9025_XilinxJesd204bLanesInUseBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_1, + deframerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 lanes in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure subclass */ + recoveryAction = fpga9025_XilinxJesd204bCfgSubclassvBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_1, + deframerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 subclass"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure RX buffer delay */ + recoveryAction = fpga9025_XilinxJesd204bRxBufferDelayBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_1, + deframerCfg->rxBufferDly); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 RX buffer delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure error reporting on sync disable */ + recoveryAction = fpga9025_XilinxJesd204bDisErrOnSyncBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_1, + deframerCfg->errReportingDisable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 error reporting on sync disable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* disable watchdog timer & set the self-clearing reset bit */ + recoveryAction = fpga9025_XilinxJesd204bWatchdogTimerDisableBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_1, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error disabling Deframer 2 watchdog timer"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((deframerSelMask & ADI_FPGA9025_DEFRAMER_2) == ADI_FPGA9025_DEFRAMER_2) + { + /* set ILA multiframes to 4 multiframes */ + recoveryAction = fpga9025_XilinxJesd204bIlaMultiframesBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_2, + 3); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set deframer ila_multiframes"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Configure lane xbar */ + recoveryAction = adi_fpga9025_RxLaneXBarCfgSet(device, + ADI_FPGA9025_DEFRAMER_2, + deframerCfg->laneXbar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure ILA support */ + recoveryAction = fpga9025_XilinxJesd204bIlaSupportEnBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_2, + deframerCfg->ilaSupportEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Deframer 2 ILA support"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure scrambling */ + recoveryAction = fpga9025_XilinxJesd204bScramblingEnBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_2, + deframerCfg->scramblingEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 scrambling"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure SYSREF settings */ + recoveryAction = fpga9025_XilinxJesd204bSysrefAlwaysBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_2, + deframerCfg->sysRefAlways); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 SYSREF always"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204bSysrefDelayBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_2, + deframerCfg->sysRefDelay); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 SYSREF delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204bSysrefRequiredOnResyncBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_2, + deframerCfg->sysRefRequiredOnResync); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 SYSREF required on resync"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure octets per frame (F) */ + recoveryAction = fpga9025_XilinxJesd204bCfgFBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_2, + deframerCfg->cfgF - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 F"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure frames per multiframe (K) */ + recoveryAction = fpga9025_XilinxJesd204bCfgKBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_2, + deframerCfg->cfgK - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 K"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure lanes in use */ + recoveryAction = fpga9025_XilinxJesd204bLanesInUseBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_2, + deframerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 lanes in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure subclass */ + recoveryAction = fpga9025_XilinxJesd204bCfgSubclassvBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_2, + deframerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 subclass"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure RX buffer delay */ + recoveryAction = fpga9025_XilinxJesd204bRxBufferDelayBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_2, + deframerCfg->rxBufferDly); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 RX buffer delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure error reporting on sync disable */ + recoveryAction = fpga9025_XilinxJesd204bDisErrOnSyncBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_2, + deframerCfg->errReportingDisable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Deframer 2 error reporting on sync disable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* disable watchdog timer & set the self-clearing reset bit */ + recoveryAction = fpga9025_XilinxJesd204bWatchdogTimerDisableBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_2, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error disabling Deframer 2 watchdog timer"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t fpga9025_Jesd204BDeframerCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_DeframerSel_e deframerSel, + adi_fpga9025_DeframerCfg_t* deframerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxJesd204bChanAddr_e deframerBase = FPGA9025_BF_JESD204B_DEFRAMER_0; + uint8_t byteRead = 0; + int8_t i = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + deframerCfg); + + /* Set correct addresses for the deframer selected */ + if (deframerSel == ADI_FPGA9025_DEFRAMER_0) + { + deframerBase = FPGA9025_BF_JESD204B_DEFRAMER_0; + } + else if (deframerSel == ADI_FPGA9025_DEFRAMER_1) + { + deframerBase = FPGA9025_BF_JESD204B_DEFRAMER_1; + } + else if (deframerSel == ADI_FPGA9025_DEFRAMER_2) + { + deframerBase = FPGA9025_BF_JESD204B_DEFRAMER_2; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSel, + "Invalid deframer selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* lane xbar */ + recoveryAction = adi_fpga9025_RxLaneXBarCfgGet(device, + deframerSel, + &deframerCfg->laneXbar[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ILA support */ + recoveryAction = fpga9025_XilinxJesd204bIlaSupportEnBfGet(device, + deframerBase, + &deframerCfg->ilaSupportEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting RX ILA support"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* scrambling */ + recoveryAction = fpga9025_XilinxJesd204bScramblingEnBfGet(device, + deframerBase, + &deframerCfg->scramblingEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX scrambling"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* SYSREF settings */ + recoveryAction = fpga9025_XilinxJesd204bSysrefAlwaysBfGet(device, + deframerBase, + &deframerCfg->sysRefAlways); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX SYSREF always"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204bSysrefDelayBfGet(device, + deframerBase, + &deframerCfg->sysRefDelay); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX SYSREF delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204bSysrefRequiredOnResyncBfGet(device, + deframerBase, + &deframerCfg->sysRefRequiredOnResync); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX SYSREF required on resync"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* octets per frame (F) */ + recoveryAction = fpga9025_XilinxJesd204bCfgFBfGet(device, + deframerBase, + &byteRead); + deframerCfg->cfgF = byteRead + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX F"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* frames per multiframe (K) */ + recoveryAction = fpga9025_XilinxJesd204bCfgKBfGet(device, + deframerBase, + &byteRead); + deframerCfg->cfgK = byteRead + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX K"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* lanes in use */ + recoveryAction = fpga9025_XilinxJesd204bLanesInUseBfGet(device, + deframerBase, + &deframerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX lanes in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* subclass */ + recoveryAction = fpga9025_XilinxJesd204bCfgSubclassvBfGet(device, + deframerBase, + &deframerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX subclass"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* rxBufferDelay */ + recoveryAction = fpga9025_XilinxJesd204bRxBufferDelayBfGet(device, + deframerBase, + &deframerCfg->rxBufferDly); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX buffer delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* error reporting disable on sync */ + recoveryAction = fpga9025_XilinxJesd204bDisErrOnSyncBfGet(device, + deframerBase, + &deframerCfg->errReportingDisable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX error reporting disable on sync"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Reading ILA data per lane*/ + for (i = 0; i < ADI_FPGA9025_NUM_LANES; i++) + { + /* bank ID */ + recoveryAction = fpga9025_XilinxJesd204bIlaBidBfGet(device, + deframerBase, + i, + &deframerCfg->bankId[i]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX bank ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* lane ID */ + recoveryAction = fpga9025_XilinxJesd204bCfgLaneIdBfGet(device, + deframerBase, + i, + &deframerCfg->cfgLaneId[i]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX lane ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ilaS */ + recoveryAction = fpga9025_XilinxJesd204bIlaSBfGet(device, + deframerBase, + i, + &byteRead); + deframerCfg->ilaS[i] = byteRead + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX ilaS"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ilaM */ + recoveryAction = fpga9025_XilinxJesd204bIlaMBfGet(device, + deframerBase, + i, + &byteRead); + deframerCfg->ilaM[i] = byteRead + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX ilaM"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ilaN */ + recoveryAction = fpga9025_XilinxJesd204bIlaNBfGet(device, + deframerBase, + i, + &byteRead); + deframerCfg->ilaN[i] = byteRead + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX ilaM"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ilaNp */ + recoveryAction = fpga9025_XilinxJesd204bIlaNpBfGet(device, + deframerBase, + i, + &byteRead); + deframerCfg->ilaNp[i] = byteRead + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX ilaM"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* rxBufferAdj */ + recoveryAction = fpga9025_XilinxJesd204bRxBufAdjBfGet(device, + deframerBase, + i, + &deframerCfg->rxBufferAdj[i]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading RX buffer adj"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t fpga9025_Jesd204BFramerCfgSet(adi_fpga9025_Device_t* device, + uint8_t linkSelMask, + adi_fpga9025_FramerCfg_t* framerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + framerCfg); + + if ((linkSelMask < ADI_FPGA9025_FRAMER_0) || (linkSelMask > ADI_FPGA9025_FRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + linkSelMask, + "Invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Configure one or both framers */ + if ((linkSelMask & ADI_FPGA9025_FRAMER_0) == ADI_FPGA9025_FRAMER_0) + { + /* Configure lane xbar */ + recoveryAction = adi_fpga9025_TxLaneXBarCfgSet(device, + ADI_FPGA9025_FRAMER_0, + framerCfg->laneXbar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure ILA support */ + recoveryAction = fpga9025_XilinxJesd204bIlaSupportEnBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + framerCfg->ilaSupportEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Framer 0 ILA support"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure scrambling */ + recoveryAction = fpga9025_XilinxJesd204bScramblingEnBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + framerCfg->scramblingEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 scrambling"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure SYSREF settings */ + recoveryAction = fpga9025_XilinxJesd204bSysrefAlwaysBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + framerCfg->sysRefAlways); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 SYSREF always"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204bSysrefDelayBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + framerCfg->sysRefDelay); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 SYSREF delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204bSysrefRequiredOnResyncBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + framerCfg->sysRefRequiredOnResync); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 SYSREF required on resync"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure ILA multiframes */ + recoveryAction = fpga9025_XilinxJesd204bIlaMultiframesBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + (uint8_t)(framerCfg->ilaMultiFrames - 1)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 ILA multiframes"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure octets per frame (F) */ + recoveryAction = fpga9025_XilinxJesd204bCfgFBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + (uint8_t)(framerCfg->cfgF - 1)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 F"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure frames per multiframe (K) */ + recoveryAction = fpga9025_XilinxJesd204bCfgKBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + framerCfg->cfgK - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 K"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure lanes in use */ + recoveryAction = fpga9025_XilinxJesd204bLanesInUseBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + framerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 lanes in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure subclass */ + recoveryAction = fpga9025_XilinxJesd204bCfgSubclassvBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + framerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 subclass"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* For ILA configuration registers, TX uses lane 0 register addresses for setup */ + /* configure Bank ID */ + recoveryAction = fpga9025_XilinxJesd204bIlaBidBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + 0, + framerCfg->bankId); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 bank ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure Device ID */ + recoveryAction = fpga9025_XilinxJesd204bIlaDidBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + 0, + framerCfg->deviceId); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 device ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure control bits per sample (CS)*/ + recoveryAction = fpga9025_XilinxJesd204bIlaCsBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + 0, + framerCfg->ilaCs); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 control bits per sample (CS)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure total bits per sample (Np) */ + recoveryAction = fpga9025_XilinxJesd204bIlaNpBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + 0, + framerCfg->ilaNp - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 total bits per sample (Np)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure converter resolution (N) */ + recoveryAction = fpga9025_XilinxJesd204bIlaNBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + 0, + framerCfg->ilaN - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 converter resolution (N)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure converters per device (M) */ + recoveryAction = fpga9025_XilinxJesd204bIlaMBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + 0, + framerCfg->ilaM - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 converters per device (M)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure control words per frame (CF) */ + recoveryAction = fpga9025_XilinxJesd204bIlaCfBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + 0, + framerCfg->ilaCf); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 control words per frame (CF)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure high density format (HD) */ + recoveryAction = fpga9025_XilinxJesd204bIlaHdBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + 0, + framerCfg->ilaHd); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 high density format (HD)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure samples per converter per frame (S) */ + recoveryAction = fpga9025_XilinxJesd204bIlaSBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + 0, + framerCfg->ilaS - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 0 samples per converter per frame (S) "); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* disable watchdog timer & set the self-clearing reset bit */ + recoveryAction = fpga9025_XilinxJesd204bWatchdogTimerDisableBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error disabling Framer 0 watchdog timer"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((linkSelMask & ADI_FPGA9025_FRAMER_1) == ADI_FPGA9025_FRAMER_1) + { + /* Configure lane xbar */ + recoveryAction = adi_fpga9025_TxLaneXBarCfgSet(device, + ADI_FPGA9025_FRAMER_1, + framerCfg->laneXbar); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure ILA support */ + recoveryAction = fpga9025_XilinxJesd204bIlaSupportEnBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + framerCfg->ilaSupportEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Framer 1 ILA support"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure scrambling */ + recoveryAction = fpga9025_XilinxJesd204bScramblingEnBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + framerCfg->scramblingEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 scrambling"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure SYSREF settings */ + recoveryAction = fpga9025_XilinxJesd204bSysrefAlwaysBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + framerCfg->sysRefAlways); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 SYSREF always"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204bSysrefDelayBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + framerCfg->sysRefDelay); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 SYSREF delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204bSysrefRequiredOnResyncBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + framerCfg->sysRefRequiredOnResync); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 SYSREF required on resync"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure ILA multiframes */ + recoveryAction = fpga9025_XilinxJesd204bIlaMultiframesBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + (uint8_t)(framerCfg->ilaMultiFrames - 1)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 ILA multiframes"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure octets per frame (F) */ + recoveryAction = fpga9025_XilinxJesd204bCfgFBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + (uint8_t)(framerCfg->cfgF - 1)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 F"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure frames per multiframe (K) */ + recoveryAction = fpga9025_XilinxJesd204bCfgKBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + framerCfg->cfgK - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 K"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure lanes in use */ + recoveryAction = fpga9025_XilinxJesd204bLanesInUseBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + framerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 lanes in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure subclass */ + recoveryAction = fpga9025_XilinxJesd204bCfgSubclassvBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + framerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 subclass"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* For ILA configuration registers, TX uses lane 0 register addresses for setup */ + /* configure Bank ID */ + recoveryAction = fpga9025_XilinxJesd204bIlaBidBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + 0, + framerCfg->bankId); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 bank ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure Device ID */ + recoveryAction = fpga9025_XilinxJesd204bIlaDidBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + 0, + framerCfg->deviceId); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 device ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure control bits per sample (CS)*/ + recoveryAction = fpga9025_XilinxJesd204bIlaCsBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + 0, + framerCfg->ilaCs); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 control bits per sample (CS)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure total bits per sample (Np) */ + recoveryAction = fpga9025_XilinxJesd204bIlaNpBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + 0, + framerCfg->ilaNp - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 total bits per sample (Np)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure converter resolution (N) */ + recoveryAction = fpga9025_XilinxJesd204bIlaNBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + 0, + framerCfg->ilaN - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 converter resolution (N)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure converters per device (M) */ + recoveryAction = fpga9025_XilinxJesd204bIlaMBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + 0, + framerCfg->ilaM - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 converters per device (M)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure control words per frame (CF) */ + recoveryAction = fpga9025_XilinxJesd204bIlaCfBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + 0, + framerCfg->ilaCf); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 control words per frame (CF)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure high density format (HD) */ + recoveryAction = fpga9025_XilinxJesd204bIlaHdBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + 0, + framerCfg->ilaHd); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 high density format (HD)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure samples per converter per frame (S) */ + recoveryAction = fpga9025_XilinxJesd204bIlaSBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + 0, + framerCfg->ilaS - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error configuring Framer 1 samples per converter per frame (S) "); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* disable watchdog timer & set the self-clearing reset bit */ + recoveryAction = fpga9025_XilinxJesd204bWatchdogTimerDisableBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error disabling Framer 1 watchdog timer"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t fpga9025_Jesd204BFramerCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_FramerSel_e framerSel, + adi_fpga9025_FramerCfg_t* framerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxJesd204bChanAddr_e framerBase = FPGA9025_BF_JESD204B_DEFRAMER_0; + uint8_t byteRead = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + framerCfg); + + /* Set correct addresses for the framer selected */ + if (framerSel == ADI_FPGA9025_FRAMER_0) + { + framerBase = FPGA9025_BF_JESD204B_FRAMER_0; + } + else if (framerSel == ADI_FPGA9025_FRAMER_1) + { + framerBase = FPGA9025_BF_JESD204B_FRAMER_1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Invalid framer selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* lane xbar */ + recoveryAction = adi_fpga9025_TxLaneXBarCfgGet(device, + framerSel, + &framerCfg->laneXbar[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ILA support */ + recoveryAction = fpga9025_XilinxJesd204bIlaSupportEnBfGet(device, + framerBase, + &framerCfg->ilaSupportEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading ILA support"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* scrambling */ + recoveryAction = fpga9025_XilinxJesd204bScramblingEnBfGet(device, + framerBase, + &framerCfg->scramblingEn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading scrambling"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* SYSREF settings */ + recoveryAction = fpga9025_XilinxJesd204bSysrefAlwaysBfGet(device, + framerBase, + &framerCfg->sysRefAlways); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading SYSREF always"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204bSysrefDelayBfGet(device, + framerBase, + &framerCfg->sysRefDelay); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading SYSREF delay"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204bSysrefRequiredOnResyncBfGet(device, + framerBase, + &framerCfg->sysRefRequiredOnResync); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading SYSREF required on resync"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* ILA multiframes */ + recoveryAction = fpga9025_XilinxJesd204bIlaMultiframesBfGet(device, + framerBase, + &byteRead); + framerCfg->ilaMultiFrames = (uint16_t)byteRead + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading ILA multiframes"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* octets per frame (F) */ + recoveryAction = fpga9025_XilinxJesd204bCfgFBfGet(device, + framerBase, + &byteRead); + framerCfg->cfgF = (uint16_t)byteRead + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading F"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* frames per multiframe (K) */ + recoveryAction = fpga9025_XilinxJesd204bCfgKBfGet(device, + framerBase, + &byteRead); + framerCfg->cfgK = byteRead + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading K"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* lanes in use */ + recoveryAction = fpga9025_XilinxJesd204bLanesInUseBfGet(device, + framerBase, + &framerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading lanes in use"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* subclass */ + recoveryAction = fpga9025_XilinxJesd204bCfgSubclassvBfGet(device, + framerBase, + &framerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading subclass"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* For ILA configuration registers, TX uses lane 0 register addresses for setup */ + /* Bank ID */ + recoveryAction = fpga9025_XilinxJesd204bIlaBidBfGet(device, + framerBase, + 0, + &framerCfg->bankId); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading bank ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Device ID */ + recoveryAction = fpga9025_XilinxJesd204bIlaDidBfGet(device, + framerBase, + 0, + &framerCfg->deviceId); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading device ID"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* control bits per sample (CS)*/ + recoveryAction = fpga9025_XilinxJesd204bIlaCsBfGet(device, + framerBase, + 0, + &framerCfg->ilaCs); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading control bits per sample (CS)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* total bits per sample (Np) */ + recoveryAction = fpga9025_XilinxJesd204bIlaNpBfGet(device, + framerBase, + 0, + &byteRead); + framerCfg->ilaNp = byteRead + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading total bits per sample (Np)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* converter resolution (N) */ + recoveryAction = fpga9025_XilinxJesd204bIlaNBfGet(device, + framerBase, + 0, + &byteRead); + framerCfg->ilaN = byteRead + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading converter resolution (N)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* converters per device (M) */ + recoveryAction = fpga9025_XilinxJesd204bIlaMBfGet(device, + framerBase, + 0, + &byteRead); + framerCfg->ilaM = byteRead + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading converters per device (M)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* control words per frame (CF) */ + recoveryAction = fpga9025_XilinxJesd204bIlaCfBfGet(device, + framerBase, + 0, + &framerCfg->ilaCf); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading control words per frame (CF)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* high density format (HD) */ + recoveryAction = fpga9025_XilinxJesd204bIlaHdBfGet(device, + framerBase, + 0, + &framerCfg->ilaHd); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading high density format (HD)"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* samples per converter per frame (S) */ + recoveryAction = fpga9025_XilinxJesd204bIlaSBfGet(device, + framerBase, + 0, + &byteRead); + framerCfg->ilaS = byteRead + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading samples per converter per frame (S) "); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t fpga9025_Jesd204BFramerResetGet(adi_fpga9025_Device_t* device, + uint32_t framerSelMask, + uint8_t* resetBits) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t resetGet = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + resetBits); + + if ((framerSelMask < ADI_FPGA9025_FRAMER_0) || (framerSelMask > ADI_FPGA9025_FRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSelMask, + "Invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *resetBits = 0x00; + + if ((framerSelMask & ADI_FPGA9025_FRAMER_0) == ADI_FPGA9025_FRAMER_0) + { + recoveryAction = fpga9025_XilinxJesd204bResetSelfClearingBfGet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + &resetGet); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading Framer 0 reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *resetBits |= (resetGet & 0x01) << 0; + } + if ((framerSelMask & ADI_FPGA9025_FRAMER_1) == ADI_FPGA9025_FRAMER_1) + { + recoveryAction = fpga9025_XilinxJesd204bResetSelfClearingBfGet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + &resetGet); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading Framer 1 reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *resetBits |= (resetGet & 0x01) << 1; + } + + return recoveryAction; +} + +int32_t fpga9025_Jesd204BFramerReset(adi_fpga9025_Device_t* device, + uint8_t framerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxJesd204bChanAddr_e instanceAddress = FPGA9025_BF_JESD204B_FRAMER_0; + uint32_t i = 0; + uint32_t j = 0; + adi_fpga9025_FramerSel_e framerSel = ADI_FPGA9025_FRAMER_0; + uint8_t resetBit = 1; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if ((framerSelMask < ADI_FPGA9025_FRAMER_0) || (framerSelMask > ADI_FPGA9025_FRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSelMask, + "Invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_FRAMERS; i++) + { + framerSel = (adi_fpga9025_FramerSel_e)((uint8_t)(1 << i)); + + switch (framerSel) + { + case ADI_FPGA9025_FRAMER_0: + instanceAddress = FPGA9025_BF_JESD204B_FRAMER_0; + break; + case ADI_FPGA9025_FRAMER_1: + instanceAddress = FPGA9025_BF_JESD204B_FRAMER_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)framerSel & framerSelMask) > 0) + { + resetBit = 1; + + recoveryAction = fpga9025_XilinxJesd204bResetFixedBfSet(device, + instanceAddress, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error clearing Framer 0 fixed reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204bResetSelfClearingBfSet(device, + instanceAddress, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Framer 0 self-clearing reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Give the framer 50ms to reset itself */ + for (j = 0; j < 5; j++) + { + if ((resetBit & 0x1) > 0) + { + recoveryAction = fpga9025_XilinxJesd204bResetSelfClearingBfGet(device, + instanceAddress, + &resetBit); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading Framer 0 self-clearing reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_common_hal_Wait_ms(&device->common, + 10); + } + else + { + break; + } + } + + if ((resetBit & 0x1) > 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_LINK_LAYER_RESET_FAIL, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "Framer 0 self-clearing bit did not clear"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return recoveryAction; +} + +int32_t fpga9025_Jesd204BFramerDisable(adi_fpga9025_Device_t* device, + uint8_t framerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if ((framerSelMask < ADI_FPGA9025_FRAMER_0) || (framerSelMask > ADI_FPGA9025_FRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSelMask, + "Invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((framerSelMask & ADI_FPGA9025_FRAMER_0) == ADI_FPGA9025_FRAMER_0) + { + recoveryAction = fpga9025_XilinxJesd204bResetFixedBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Framer 0 fixed reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((framerSelMask & ADI_FPGA9025_FRAMER_1) == ADI_FPGA9025_FRAMER_1) + { + recoveryAction = fpga9025_XilinxJesd204bResetFixedBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Framer 1 fixed reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t fpga9025_Jesd204BDeframerReset(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxJesd204bChanAddr_e instanceAddress = FPGA9025_BF_JESD204B_DEFRAMER_0; + uint32_t i = 0; + uint32_t j = 0; + adi_fpga9025_DeframerSel_e deframerSel = ADI_FPGA9025_DEFRAMER_0; + uint8_t resetBit = 1; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if ((deframerSelMask < ADI_FPGA9025_DEFRAMER_0) || (deframerSelMask > ADI_FPGA9025_DEFRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelMask, + "Invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_DEFRAMERS; i++) + { + deframerSel = (adi_fpga9025_DeframerSel_e)((uint8_t)(1 << i)); + + switch (deframerSel) + { + case ADI_FPGA9025_DEFRAMER_0: + instanceAddress = FPGA9025_BF_JESD204B_DEFRAMER_0; + break; + case ADI_FPGA9025_DEFRAMER_1: + instanceAddress = FPGA9025_BF_JESD204B_DEFRAMER_1; + break; + case ADI_FPGA9025_DEFRAMER_2: + instanceAddress = FPGA9025_BF_JESD204B_DEFRAMER_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)deframerSel & deframerSelMask) > 0) + { + recoveryAction = fpga9025_XilinxJesd204bResetFixedBfSet(device, + instanceAddress, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error clearing Deframer fixed reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204bResetSelfClearingBfSet(device, + instanceAddress, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Deframer self-clearing reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Give the deframer 50ms to reset itself */ + for (j = 0; j < 5; j++) + { + if ((resetBit & 0x1) > 0) + { + recoveryAction = fpga9025_XilinxJesd204bResetSelfClearingBfGet(device, + instanceAddress, + &resetBit); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading Deframer self-clearing reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_common_hal_Wait_ms(&device->common, + 10); + } + else + { + break; + } + } + + if ((resetBit & 0x1) > 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_LINK_LAYER_RESET_FAIL, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "Deframer self-clearing bit did not clear"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return recoveryAction; +} + +int32_t fpga9025_Jesd204BDeframerDisable(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if ((deframerSelMask < ADI_FPGA9025_DEFRAMER_0) || (deframerSelMask > ADI_FPGA9025_DEFRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelMask, + "Invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((deframerSelMask & ADI_FPGA9025_DEFRAMER_0) == ADI_FPGA9025_DEFRAMER_0) + { + recoveryAction = fpga9025_XilinxJesd204bResetFixedBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_0, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Deframer 0 fixed reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((deframerSelMask & ADI_FPGA9025_DEFRAMER_1) == ADI_FPGA9025_DEFRAMER_1) + { + recoveryAction = fpga9025_XilinxJesd204bResetFixedBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_1, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Deframer 1 fixed reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((deframerSelMask & ADI_FPGA9025_DEFRAMER_2) == ADI_FPGA9025_DEFRAMER_2) + { + recoveryAction = fpga9025_XilinxJesd204bResetFixedBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_2, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Deframer 2 fixed reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t fpga9025_Jesd204BDeframerStatusGet(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask, + uint8_t* status) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t statusGet = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + status); + + if ((deframerSelMask < ADI_FPGA9025_DEFRAMER_0) || (deframerSelMask > ADI_FPGA9025_DEFRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelMask, + "Invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *status = 0x00; + + if ((deframerSelMask & ADI_FPGA9025_DEFRAMER_0) == ADI_FPGA9025_DEFRAMER_0) + { + recoveryAction = fpga9025_XilinxJesd204bSyncStatusBfGet(device, + FPGA9025_BF_JESD204B_DEFRAMER_0, + &statusGet); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading Deframer 0 reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *status |= (statusGet & 0x01) << 0; + } + if ((deframerSelMask & ADI_FPGA9025_DEFRAMER_1) == ADI_FPGA9025_DEFRAMER_1) + { + recoveryAction = fpga9025_XilinxJesd204bSyncStatusBfGet(device, + FPGA9025_BF_JESD204B_DEFRAMER_1, + &statusGet); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading Deframer 1 reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *status |= (statusGet & 0x01) << 1; + } + if ((deframerSelMask & ADI_FPGA9025_DEFRAMER_2) == ADI_FPGA9025_DEFRAMER_2) + { + recoveryAction = fpga9025_XilinxJesd204bSyncStatusBfGet(device, + FPGA9025_BF_JESD204B_DEFRAMER_2, + &statusGet); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error reading Deframer 2 reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *status |= (statusGet & 0x01) << 2; + } + + return recoveryAction; +} + +int32_t fpga9025_Jesd204CDeframerCfgSet(adi_fpga9025_Device_t* device, + uint32_t deframerSelMask, + adi_fpga9025_DeframerCfg_t* deframerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9025_BF_JESD204C_DEFRAMER_0; + uint32_t i = 0; + adi_fpga9025_DeframerSel_e deframerSel = ADI_FPGA9025_DEFRAMER_0; + uint32_t firstUnusedLaneNum = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + deframerCfg); + + if ((deframerSelMask < ADI_FPGA9025_DEFRAMER_0) || (deframerSelMask > ADI_FPGA9025_DEFRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelMask, + "Invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Find the first unused lane. Starting from this lane fill the remainder of the lane xbar with the + last good phy lane. This is a bug in the JESD204C Xilinx Rx link layer module */ + for (i = 0; i < ADI_FPGA9025_NUM_LANES; i++) + { + if ((deframerCfg->lanesInUse & (1 << i)) == 0) + { + firstUnusedLaneNum = i; + break; + } + } + + for (i = firstUnusedLaneNum; i < ADI_FPGA9025_NUM_LANES; i++) + { + deframerCfg->laneXbar[i] = deframerCfg->laneXbar[firstUnusedLaneNum - 1]; + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_DEFRAMERS; i++) + { + deframerSel = (adi_fpga9025_DeframerSel_e)((uint8_t)(1 << i)); + + switch (deframerSel) + { + case ADI_FPGA9025_DEFRAMER_0: + instanceAddress = FPGA9025_BF_JESD204C_DEFRAMER_0; + deframerCfg->lanesInUse = 0xF; + break; + case ADI_FPGA9025_DEFRAMER_1: + instanceAddress = FPGA9025_BF_JESD204C_DEFRAMER_1; + deframerCfg->lanesInUse = 0xF; + break; + case ADI_FPGA9025_DEFRAMER_2: + instanceAddress = FPGA9025_BF_JESD204C_DEFRAMER_2; + deframerCfg->lanesInUse = 0x3; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)deframerSel & deframerSelMask) > 0) + { + /* Configure lane xbar */ + recoveryAction = adi_fpga9025_RxLaneXBarCfgSet(device, + (adi_fpga9025_DeframerSel_e)deframerSel, + deframerCfg->laneXbar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cCfgMbInEmbBfSet(device, + instanceAddress, + deframerCfg->cfgE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set cfgE."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cMetaModeBfSet(device, + instanceAddress, + deframerCfg->ctrlMetaMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set meta mode."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cRxBufferDelayBfSet(device, + instanceAddress, + deframerCfg->ctrlRxBufAdv); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set buffer advance bitfield."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cRxMbThBfSet(device, + instanceAddress, + deframerCfg->ctrlRxMBlockTh - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set MB lock threshold."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cLaneEnableBfSet(device, + instanceAddress, + deframerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set lanes enabled."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cCfgSubclassvBfSet(device, + instanceAddress, + deframerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set subclass."); + ADI_ERROR_RETURN(device->common.error.newAction); + + //recoveryAction = adi_fpga9025_Jesd204cLinkLayerIrqEnSet(device, (uint8_t)deframerSel, deframerCfg->ctrlIrq); + //ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t fpga9025_Jesd204CDeframerCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_DeframerSel_e deframerSel, + adi_fpga9025_DeframerCfg_t* deframerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxJesd204cChanAddr_e deframerBase = FPGA9025_BF_JESD204C_DEFRAMER_0; + uint8_t registerValue = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + deframerCfg); + + /* Set correct addresses for the deframer selected */ + if (deframerSel == ADI_FPGA9025_DEFRAMER_0) + { + deframerBase = FPGA9025_BF_JESD204C_DEFRAMER_0; + } + else if (deframerSel == ADI_FPGA9025_DEFRAMER_1) + { + deframerBase = FPGA9025_BF_JESD204C_DEFRAMER_1; + } + else if (deframerSel == ADI_FPGA9025_DEFRAMER_2) + { + deframerBase = FPGA9025_BF_JESD204C_DEFRAMER_2; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSel, + "Invalid deframer selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* lane xbar */ + recoveryAction = adi_fpga9025_RxLaneXBarCfgGet(device, + deframerSel, + &deframerCfg->laneXbar[0]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + deframerCfg->laneXbar, + "Error reading RX Lane XBar"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cEnableCmdInterfaceBfGet(device, + deframerBase, + &deframerCfg->enableCmdInterface); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to get cmd interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cEnableDataInterfaceBfGet(device, + deframerBase, + &deframerCfg->enableDataInterface); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to get data interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cCfgMbInEmbBfGet(device, + deframerBase, + &deframerCfg->cfgE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to get cfgE."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cMetaModeBfGet(device, + deframerBase, + &deframerCfg->ctrlMetaMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to get meta mode."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cRxBufferDelayBfGet(device, + deframerBase, + &deframerCfg->ctrlRxBufAdv); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to get buffer advance bitfield."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cRxMbThBfGet(device, + deframerBase, + ®isterValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to get MB lock threshold."); + ADI_ERROR_RETURN(device->common.error.newAction); + deframerCfg->ctrlRxMBlockTh = registerValue + 1; + + recoveryAction = fpga9025_XilinxJesd204cLaneEnableBfGet(device, + deframerBase, + &deframerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to get lanes enabled."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cCfgSubclassvBfGet(device, + deframerBase, + &deframerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to get subclass."); + ADI_ERROR_RETURN(device->common.error.newAction); + + //recoveryAction = adi_fpga9025_Jesd204cLinkLayerIrqEnGet(device, (uint8_t)deframerSel, &deframerCfg->ctrlIrq); + //ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t fpga9025_Jesd204CFramerCfgSet(adi_fpga9025_Device_t* device, + uint32_t framerSelMask, + adi_fpga9025_FramerCfg_t* framerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9025_BF_JESD204C_FRAMER_0; + uint32_t i = 0; + adi_fpga9025_FramerSel_e framerSel = ADI_FPGA9025_FRAMER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + framerCfg); + + if ((framerSelMask < ADI_FPGA9025_FRAMER_0) || (framerSelMask > ADI_FPGA9025_FRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSelMask, + "Invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_FRAMERS; i++) + { + framerSel = (adi_fpga9025_FramerSel_e)((uint8_t)(1 << i)); + + switch (framerSel) + { + case ADI_FPGA9025_FRAMER_0: + instanceAddress = FPGA9025_BF_JESD204C_FRAMER_0; + break; + case ADI_FPGA9025_FRAMER_1: + instanceAddress = FPGA9025_BF_JESD204C_FRAMER_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)framerSel & framerSelMask) > 0) + { + /* Configure lane xbar */ + recoveryAction = adi_fpga9025_TxLaneXBarCfgSet(device, + (adi_fpga9025_FramerSel_e)framerSel, + framerCfg->laneXbar); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cCfgMbInEmbBfSet(device, + instanceAddress, + framerCfg->cfgE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set cfgE."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cMetaModeBfSet(device, + instanceAddress, + framerCfg->ctrlMetaMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set meta mode."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cLaneEnableBfSet(device, + instanceAddress, + framerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to get lanes enabled."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cCfgSubclassvBfSet(device, + instanceAddress, + framerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set subclass."); + ADI_ERROR_RETURN(device->common.error.newAction); + + //recoveryAction = adi_fpga9025_Jesd204cLinkLayerIrqEnSet(device, (uint8_t)(framerSel << ADI_FPGA9025_NUM_OF_DEFRAMERS), framerCfg->ctrlIrq); + //ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t fpga9025_Jesd204CFramerCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_FramerSel_e framerSel, + adi_fpga9025_FramerCfg_t* framerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + fpga9025_BfXilinxJesd204cChanAddr_e framerBase = FPGA9025_BF_JESD204C_FRAMER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + framerCfg); + + /* Set correct addresses for the framer selected */ + if (framerSel == ADI_FPGA9025_FRAMER_0) + { + framerBase = FPGA9025_BF_JESD204C_FRAMER_0; + } + else if (framerSel == ADI_FPGA9025_FRAMER_1) + { + framerBase = FPGA9025_BF_JESD204C_FRAMER_1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Invalid framer selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* lane xbar */ + recoveryAction = adi_fpga9025_TxLaneXBarCfgGet(device, + framerSel, + &framerCfg->laneXbar[0]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + framerCfg->laneXbar, + "Error reading TX Lane XBar"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cEnableCmdInterfaceBfGet(device, + framerBase, + &framerCfg->enableCmdInterface); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to get cmd interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cEnableDataInterfaceBfGet(device, + framerBase, + &framerCfg->enableDataInterface); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to get data interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cCfgMbInEmbBfGet(device, + framerBase, + &framerCfg->cfgE); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to get cfgE."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cMetaModeBfGet(device, + framerBase, + &framerCfg->ctrlMetaMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to get meta mode."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cLaneEnableBfGet(device, + framerBase, + &framerCfg->lanesInUse); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to get lanes enabled."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cCfgSubclassvBfGet(device, + framerBase, + &framerCfg->subclassV); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to get subclass."); + ADI_ERROR_RETURN(device->common.error.newAction); + + //recoveryAction = adi_fpga9025_Jesd204cLinkLayerIrqEnGet(device, (uint8_t)(framerSel << ADI_FPGA9025_NUM_OF_DEFRAMERS), &framerCfg->ctrlIrq); + //ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t fpga9025_Jesd204CFramerResetGet(adi_fpga9025_Device_t* device, + uint32_t framerSelMask, + uint8_t* resetBits) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t resetGet = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + resetBits); + + if ((framerSelMask < ADI_FPGA9025_FRAMER_0) || (framerSelMask > ADI_FPGA9025_FRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSelMask, + "Invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *resetBits = 0x00; + + if ((framerSelMask & ADI_FPGA9025_FRAMER_0) == ADI_FPGA9025_FRAMER_0) + { + recoveryAction = fpga9025_XilinxJesd204cResetFixedBfGet(device, + FPGA9025_BF_JESD204C_FRAMER_0, + &resetGet); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Framer 0 reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *resetBits |= (resetGet & 0x01) << 0; + } + if ((framerSelMask & ADI_FPGA9025_FRAMER_1) == ADI_FPGA9025_FRAMER_1) + { + recoveryAction = fpga9025_XilinxJesd204cResetFixedBfGet(device, + FPGA9025_BF_JESD204C_FRAMER_1, + &resetGet); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Framer 1 reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *resetBits |= (resetGet & 0x01) << 1; + } + + return recoveryAction; +} + +int32_t fpga9025_Jesd204CFramerReset(adi_fpga9025_Device_t* device, + uint8_t framerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9025_BF_JESD204C_FRAMER_0; + uint32_t i = 0; + uint32_t j = 0; + adi_fpga9025_FramerSel_e framerSel = ADI_FPGA9025_FRAMER_0; + uint8_t resetBit = 1; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if ((framerSelMask < ADI_FPGA9025_FRAMER_0) || (framerSelMask > ADI_FPGA9025_FRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSelMask, + "Invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_FRAMERS; i++) + { + framerSel = (adi_fpga9025_FramerSel_e)((uint8_t)(1 << i)); + + switch (framerSel) + { + case ADI_FPGA9025_FRAMER_0: + instanceAddress = FPGA9025_BF_JESD204C_FRAMER_0; + break; + case ADI_FPGA9025_FRAMER_1: + instanceAddress = FPGA9025_BF_JESD204C_FRAMER_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)framerSel & framerSelMask) > 0) + { + resetBit = 1; + + recoveryAction = fpga9025_XilinxJesd204cResetFixedBfSet(device, + instanceAddress, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Framer reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cResetFixedBfSet(device, + instanceAddress, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error clearing Framer reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Give the framer 50ms to reset itself */ + for (j = 0; j < 5; j++) + { + if ((resetBit & 0x1) > 0) + { + recoveryAction = fpga9025_XilinxJesd204cResetFixedBfGet(device, + instanceAddress, + &resetBit); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Framer reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_common_hal_Wait_ms(&device->common, + 10); + } + else + { + break; + } + } + + if ((resetBit & 0x1) > 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "Framer did not reset correctly"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return recoveryAction; +} + +int32_t fpga9025_Jesd204CFramerDisable(adi_fpga9025_Device_t* device, + uint8_t framerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9025_BF_JESD204C_FRAMER_0; + uint32_t i = 0; + adi_fpga9025_FramerSel_e framerSel = ADI_FPGA9025_FRAMER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if ((framerSelMask < ADI_FPGA9025_FRAMER_0) || (framerSelMask > ADI_FPGA9025_FRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSelMask, + "Invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_FRAMERS; i++) + { + framerSel = (adi_fpga9025_FramerSel_e)((uint8_t)(1 << i)); + + switch (framerSel) + { + case ADI_FPGA9025_FRAMER_0: + instanceAddress = FPGA9025_BF_JESD204C_FRAMER_0; + break; + case ADI_FPGA9025_FRAMER_1: + instanceAddress = FPGA9025_BF_JESD204C_FRAMER_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)framerSel & framerSelMask) > 0) + { + /* These two bitfields are tied to the LEDs on the ADS9. Zero out to ensure the LEDs are turned off */ + recoveryAction = fpga9025_XilinxJesd204cEnableCmdInterfaceBfSet(device, + instanceAddress, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set cmd interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cEnableDataInterfaceBfSet(device, + instanceAddress, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set data interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cResetFixedBfSet(device, + instanceAddress, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Framer 0 reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t fpga9025_Jesd204CDeframerReset(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9025_BF_JESD204C_DEFRAMER_0; + uint32_t i = 0; + uint32_t j = 0; + adi_fpga9025_DeframerSel_e deframerSel = ADI_FPGA9025_DEFRAMER_0; + uint8_t resetBit = 1; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if ((deframerSelMask < ADI_FPGA9025_DEFRAMER_0) || (deframerSelMask > ADI_FPGA9025_DEFRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelMask, + "Invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_DEFRAMERS; i++) + { + deframerSel = (adi_fpga9025_DeframerSel_e)((uint8_t)(1 << i)); + + switch (deframerSel) + { + case ADI_FPGA9025_DEFRAMER_0: + instanceAddress = FPGA9025_BF_JESD204C_DEFRAMER_0; + break; + case ADI_FPGA9025_DEFRAMER_1: + instanceAddress = FPGA9025_BF_JESD204C_DEFRAMER_1; + break; + case ADI_FPGA9025_DEFRAMER_2: + instanceAddress = FPGA9025_BF_JESD204C_DEFRAMER_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)deframerSel & deframerSelMask) > 0) + { + recoveryAction = fpga9025_XilinxJesd204cResetFixedBfSet(device, + instanceAddress, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Deframer reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cResetFixedBfSet(device, + instanceAddress, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error clearing Deframer reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Give the deframer 50ms to reset itself */ + for (j = 0; j < 5; j++) + { + if ((resetBit & 0x1) > 0) + { + recoveryAction = fpga9025_XilinxJesd204cResetFixedBfGet(device, + instanceAddress, + &resetBit); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Deframer reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_common_hal_Wait_ms(&device->common, + 10); + } + else + { + break; + } + } + + if ((resetBit & 0x1) > 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "Deframer did not reset correctly"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + } + + return recoveryAction; +} + +int32_t fpga9025_Jesd204CDeframerDisable(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9025_BF_JESD204C_DEFRAMER_0; + uint32_t i = 0; + adi_fpga9025_DeframerSel_e deframerSel = ADI_FPGA9025_DEFRAMER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if ((deframerSelMask < ADI_FPGA9025_DEFRAMER_0) || (deframerSelMask > ADI_FPGA9025_DEFRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelMask, + "Invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_DEFRAMERS; i++) + { + deframerSel = (adi_fpga9025_DeframerSel_e)((uint8_t)(1 << i)); + + switch (deframerSel) + { + case ADI_FPGA9025_DEFRAMER_0: + instanceAddress = FPGA9025_BF_JESD204C_DEFRAMER_0; + break; + case ADI_FPGA9025_DEFRAMER_1: + instanceAddress = FPGA9025_BF_JESD204C_DEFRAMER_1; + break; + case ADI_FPGA9025_DEFRAMER_2: + instanceAddress = FPGA9025_BF_JESD204C_DEFRAMER_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)deframerSel & deframerSelMask) > 0) + { + /* These two bitfields are tied to the LEDs on the ADS9. Zero out to ensure the LEDs are turned off */ + recoveryAction = fpga9025_XilinxJesd204cEnableCmdInterfaceBfSet(device, + instanceAddress, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set cmd interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cEnableDataInterfaceBfSet(device, + instanceAddress, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set data interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cResetFixedBfSet(device, + instanceAddress, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Deframer reset bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t fpga9025_Jesd204CDeframerStatusGet(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask, + uint8_t* status) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t syncHeaderStatusGet = 0; + uint8_t mbLockStatusGet = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + status); + + if ((deframerSelMask < ADI_FPGA9025_DEFRAMER_0) || (deframerSelMask > ADI_FPGA9025_DEFRAMER_ALL)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSelMask, + "Invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *status = 0x00; + + if ((deframerSelMask & ADI_FPGA9025_DEFRAMER_0) == ADI_FPGA9025_DEFRAMER_0) + { + recoveryAction = fpga9025_XilinxJesd204cMbLockBfGet(device, + FPGA9025_BF_JESD204C_DEFRAMER_0, + &mbLockStatusGet); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Deframer 0 mb lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_XilinxJesd204cSyncHeaderLockBfGet(device, + FPGA9025_BF_JESD204C_DEFRAMER_0, + &syncHeaderStatusGet); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Deframer 0 loss sync header lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *status |= (mbLockStatusGet & syncHeaderStatusGet) << 0; + } + if ((deframerSelMask & ADI_FPGA9025_DEFRAMER_1) == ADI_FPGA9025_DEFRAMER_1) + { + recoveryAction = fpga9025_XilinxJesd204cMbLockBfGet(device, + FPGA9025_BF_JESD204C_DEFRAMER_1, + &mbLockStatusGet); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Deframer 1 mb lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_XilinxJesd204cSyncHeaderLockBfGet(device, + FPGA9025_BF_JESD204C_DEFRAMER_1, + &syncHeaderStatusGet); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Deframer 1 loss sync header lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *status |= (mbLockStatusGet & syncHeaderStatusGet) << 1; + } + if ((deframerSelMask & ADI_FPGA9025_DEFRAMER_2) == ADI_FPGA9025_DEFRAMER_2) + { + recoveryAction = fpga9025_XilinxJesd204cMbLockBfGet(device, + FPGA9025_BF_JESD204C_DEFRAMER_2, + &mbLockStatusGet); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Deframer 2 mb lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_XilinxJesd204cSyncHeaderLockBfGet(device, + FPGA9025_BF_JESD204C_DEFRAMER_2, + &syncHeaderStatusGet); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Deframer 2 loss sync header lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + *status |= (mbLockStatusGet & syncHeaderStatusGet) << 2; + } + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_tdd.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_tdd.c new file mode 100644 index 0000000..298fa96 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_tdd.c @@ -0,0 +1,316 @@ +/** + * \file: fpga9025_tdd.c + * + * \brief Contains private tdd related functions + * + * FPGA9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9025_user.h" +#include "adi_fpga9025.h" +#include "adi_fpga9025_error.h" +#include "../../private/include/fpga9025_tdd.h" +#include "../../private/include/fpga9025_bf_tdd_dp_ctrl.h" +#include "../../private/include/fpga9025_bf_tdd_dp_ctrl_types.h" +#include "../../private/include/fpga9025_bf_tdd_enable_ctrl.h" +#include "../../private/include/fpga9025_bf_tdd_enable_ctrl_types.h" +#include "../../private/include/fpga9025_bf_tdd_frame_cnt.h" +#include "../../private/include/fpga9025_bf_tdd_frame_cnt_types.h" + +int32_t fpga9025_TddEnableControlModuleSet(adi_fpga9025_Device_t* device, + adi_fpga_TddTiming_t* module, + uint32_t baseAddress) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + module); + + if (module->offPtr != module->onPtr) + { + recoveryAction = fpga9025_TddEnableCtrlEnableBfSet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + 0x01); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlStartValueBfSet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + module->onPtr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlEndValueBfSet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + module->offPtr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module end bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = fpga9025_TddEnableCtrlEnableBfSet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + 0x00); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlStartValueBfSet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + 0x00); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlEndValueBfSet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + 0x00); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module end bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (module->secondaryOffPtr != module->secondaryOnPtr) + { + recoveryAction = fpga9025_TddEnableCtrlSecEnableBfSet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + 0x01); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlSecStartValueBfSet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + module->secondaryOnPtr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlSecEndValueBfSet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + module->secondaryOffPtr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module end bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = fpga9025_TddEnableCtrlSecEnableBfSet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + 0x00); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlSecStartValueBfSet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + 0x00); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlSecEndValueBfSet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + 0x00); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module end bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = fpga9025_TddEnableCtrlFramesOffsetBfSet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + module->offsetFrames); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlFramesInactiveBfSet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + module->inactiveFrames); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlFramesActiveBfSet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + module->activeFrames); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t fpga9025_TddEnableControlModuleGet(adi_fpga9025_Device_t* device, + adi_fpga_TddTiming_t* module, + uint32_t baseAddress) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + module); + + recoveryAction = fpga9025_TddEnableCtrlStartValueBfGet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + &module->onPtr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlEndValueBfGet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + &module->offPtr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module end bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlSecStartValueBfGet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + &module->secondaryOnPtr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlSecEndValueBfGet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + &module->secondaryOffPtr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module end bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlFramesOffsetBfGet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + &module->offsetFrames); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlFramesInactiveBfGet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + &module->inactiveFrames); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlFramesActiveBfGet(device, + (fpga9025_BfTddEnableCtrlChanAddr_e)baseAddress, + &module->activeFrames); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Rx4 Enable Control module start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_utilities.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_utilities.c new file mode 100644 index 0000000..022c4c7 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/private/src/fpga9025_utilities.c @@ -0,0 +1,21289 @@ +/** + * \file: fpga9025_jesd.c + * + * \brief Contains private jesd related functions + * + * FPGA9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9025.h" +#include "../../private/include/fpga9025_utilities.h" +#define EXCELSHEET 1 + +int32_t fpga9025_QpllDrpCfg(adi_fpga9025_Device_t* device, + const uint32_t refClk_kHz, + const uint32_t qpllVcoOut_kHz, + const uint8_t qpllDivideRatio) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 122880 && qpllVcoOut_kHz == 9830400) + { + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x400, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x400, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x1, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x1, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x21f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x21f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 153600 && qpllVcoOut_kHz == 12288000) + { + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x21f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x21f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 11059200) + { + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x33f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x33f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 14745600) + { + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xb00, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xb00, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x37f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x37f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 9830400) + { + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x400, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x400, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x1, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x1, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x37f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x37f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 7372800) + { + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x0b00, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x0b00, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x333c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x333c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc0, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc0, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc0, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc0, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x31d, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x31d, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 14745600) + { + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xb00, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xb00, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x333c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x333c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc0, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc0, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc0, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc0, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x31d, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x31d, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 307200 && qpllVcoOut_kHz == 12288000) + { + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x37f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x37f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 368640 && qpllVcoOut_kHz == 11059200) + { + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x37f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x37f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 491520 && qpllVcoOut_kHz == 9830400) + { + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x400, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x400, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x1, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x1, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x27f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x27f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 368640 && qpllVcoOut_kHz == 9123840 && qpllDivideRatio == 1) + { + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x400, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x400, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x1, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x1, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc0, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc0, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc0, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc0, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x23f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x23f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x1, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x1, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x3, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x3, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x21d, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x21d, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 122880 && qpllVcoOut_kHz == 16220160 && qpllDivideRatio == 2) + { + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x600, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x600, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x0, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x0, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x37f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x37f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x0, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x0, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x21f, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x21f, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xb00, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xb00, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 153600 && qpllVcoOut_kHz == 10137600 && qpllDivideRatio == 1) + { + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x600, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x600, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x1, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x1, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc0, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc0, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc0, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc0, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x3, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x3, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x23f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x23f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x1, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x1, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x21f, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x21f, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x400, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x400, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 9123840 && qpllDivideRatio == 1) + { + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x400, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x400, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x1, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x1, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc0, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc0, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc0, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc0, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x23f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x23f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x1, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x1, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x3, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x3, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x21d, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x21d, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 12165120 && qpllDivideRatio == 1) + { + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x600, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x600, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x1, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x1, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x3, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x3, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x33f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x33f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x1, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x1, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x21f, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x21f, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 12165120 && qpllDivideRatio == 1) + { + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x600, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x600, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x1, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x1, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x3, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x3, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x21f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x21f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x1, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x1, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x21f, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x21f, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 16220160 && qpllDivideRatio == 2) + { + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x600, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x600, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x0, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x0, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc0, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc0, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc0, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc0, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x31d, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x31d, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x0, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x0, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x21f, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x21f, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xb00, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xb00, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x333c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x333c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 307200 && qpllVcoOut_kHz == 10137600 && qpllDivideRatio == 1) + { + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x600, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x600, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x1, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x1, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x3, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x3, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x37f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x37f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x1, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x1, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x21f, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x21f, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x400, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x400, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 491520 && qpllVcoOut_kHz == 16220160 && qpllDivideRatio == 2) + { + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x600, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x600, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x0, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x0, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc0, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc0, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc0, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc0, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x31d, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x31d, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x0, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x0, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc3, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc3, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x21f, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x21f, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xb00, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xb00, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x333c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x333c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 8110080 && qpllDivideRatio == 2) + { + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x200, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x200, + 0xffff); /* ppf1Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf1Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x0, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x0, + 0x1); /* qpll0ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc0, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc0, + 0xffff); /* qpll0Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc0, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x001b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc0, + 0xffff); /* qpll0Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0030, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x2, + 0xffff); /* qpll0Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x23f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0019, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x23f, + 0x03ff); /* qpll0Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x0, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008e, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x0, + 0x1); /* qpll1ClkOutRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1ClkOutRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0091, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll1Cfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0xfc1, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009b, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0xfc1, + 0xffff); /* qpll1Cfg2G3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg2G3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x1, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x1, + 0xffff); /* qpll1Cfg4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Cfg4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x33f, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0099, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x33f, + 0x03ff); /* qpll1Lpf */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll1Lpf"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x000d, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x600, + 0xffff); /* ppf0Cfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ppf0Cfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD0, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0008, + (uint32_t)ADI_FPGA9025_PHY_QUAD1, + 0x331c, + 0xffff); /* qpll0Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to qpll0Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + return ADI_COMMON_ACT_NO_ACTION; + + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_INVALID_CLK_CONFIG, + ADI_COMMON_ACT_WARN_CHECK_PARAM, + NULL, + "WARNING: Clock config is not supported. Performance may suffer."); + return recoveryAction; +} + +int32_t fpga9025_SerializerDrpCfg(adi_fpga9025_Device_t* device, + const uint32_t refClk_kHz, + const uint32_t laneRate, + const uint32_t qpllVcoOut_kHz, + const uint8_t fpgaLane) +{ +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 122880 && qpllVcoOut_kHz == 4915200 && laneRate == 4915200) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008f, + fpgaLane, + 0x723, + 0xffff); /* TxphCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x300, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x1000, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x0, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 122880 && qpllVcoOut_kHz == 4915200 && laneRate == 9830400) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008f, + fpgaLane, + 0x323, + 0xffff); /* TxphCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x300, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x1000, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x0, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 153600 && qpllVcoOut_kHz == 6144000 && laneRate == 6144000) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008f, + fpgaLane, + 0x723, + 0xffff); /* TxphCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x1000, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 153600 && qpllVcoOut_kHz == 6144000 && laneRate == 12288000) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008f, + fpgaLane, + 0x323, + 0xffff); /* TxphCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x1000, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 5529600 && laneRate == 11059200) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008f, + fpgaLane, + 0x323, + 0xffff); /* TxphCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x1000, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && (refClk_kHz == 184320 || refClk_kHz == 245760) && qpllVcoOut_kHz == 7372800 && laneRate == 7372800) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008f, + fpgaLane, + 0x723, + 0xffff); /* TxphCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 7372800 && laneRate == 14745600) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x200, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008f, + fpgaLane, + 0x323, + 0xffff); /* TxphCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 4915200 && laneRate == 4915200) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008f, + fpgaLane, + 0x723, + 0xffff); /* TxphCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x300, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x1000, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x0, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 4915200 && laneRate == 9830400) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008f, + fpgaLane, + 0x323, + 0xffff); /* TxphCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x300, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x1000, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x0, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 7372800 && laneRate == 14745600) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x200, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008f, + fpgaLane, + 0x323, + 0xffff); /* TxphCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 307200 && qpllVcoOut_kHz == 6144000 && laneRate == 6144000) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008f, + fpgaLane, + 0x723, + 0xffff); /* TxphCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x1000, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 307200 && qpllVcoOut_kHz == 6144000 && laneRate == 12288000) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008f, + fpgaLane, + 0x323, + 0xffff); /* TxphCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x1000, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 368640 && qpllVcoOut_kHz == 5529600 && laneRate == 11059200) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008f, + fpgaLane, + 0x323, + 0xffff); /* TxphCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x1000, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 491520 && qpllVcoOut_kHz == 4915200 && laneRate == 9830400) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008f, + fpgaLane, + 0x323, + 0xffff); /* TxphCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x300, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x1000, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x0, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 122880 && qpllVcoOut_kHz == 8110080 && laneRate == 16220160) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x200, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x1, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xe, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 122880 && qpllVcoOut_kHz == 8110080 && laneRate == 4055040) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x1, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xf, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 122880 && qpllVcoOut_kHz == 8110080 && laneRate == 8110080) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x1, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xf, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 153600 && qpllVcoOut_kHz == 10137600 && laneRate == 10137600) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3000, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x4, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x0, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xf, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 153600 && qpllVcoOut_kHz == 10137600 && laneRate == 20275200) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x600, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c6, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0xf800, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0xf800, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0xf800, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3000, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x40, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x4, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe218, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x0, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xe, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 153600 && qpllVcoOut_kHz == 10137600 && laneRate == 5068800) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3000, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x4, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x0, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xf, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 12165120 && laneRate == 12165120) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3000, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x4, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x0, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xf, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 12165120 && laneRate == 24330240) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x600, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c6, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0xf800, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0xf800, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0xf800, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3000, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x40, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x4, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe218, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x0, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xe, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 12165120 && laneRate == 6082560) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3000, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x4, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x0, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xf, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 9123840 && laneRate == 18247680) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x200, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x4, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe218, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x0, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xe, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x1000, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 9123840 && laneRate == 9123840) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x4, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x0, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xf, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x1000, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 12165120 && laneRate == 12165120) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3000, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x4, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x0, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xf, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 12165120 && laneRate == 24330240) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x600, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c6, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0xf800, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0xf800, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0xf800, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3000, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x40, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x4, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe218, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x0, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xe, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 8110080 && laneRate == 16220160) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x200, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x1, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xe, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 8110080 && laneRate == 4055040) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x1, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xf, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 8110080 && laneRate == 8110080) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x1, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xf, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 307200 && qpllVcoOut_kHz == 10137600 && laneRate == 10137600) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3000, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x4, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x0, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xf, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 307200 && qpllVcoOut_kHz == 10137600 && laneRate == 20275200) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x600, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c6, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0xf800, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0xf800, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0xf800, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3000, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x40, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x4, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe218, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x0, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xe, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 307200 && qpllVcoOut_kHz == 10137600 && laneRate == 5068800) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3000, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x4, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x0, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xf, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 368640 && qpllVcoOut_kHz == 9123840 && laneRate == 18247680) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x200, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x4, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe218, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x0, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xe, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x1000, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 368640 && qpllVcoOut_kHz == 9123840 && laneRate == 9123840) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x4, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x0, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xf, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x1000, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 491520 && qpllVcoOut_kHz == 8110080 && laneRate == 16220160) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x200, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x1, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xe, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 4055040 && laneRate == 8110080) + { + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x000, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c2, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0x6c00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x0300, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x0, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x0, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xE200, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x1, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xe, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x1000, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + return ADI_COMMON_ACT_NO_ACTION; +} + + /* Default cases Logs a warning if the code gets to here but allows init to continue since the configuration may work OK. */ + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID) + { + /* Uses the settings from refClk == 245.76 & laneRate == 14.7G */ + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x200, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0xaa00, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x008f, + fpgaLane, + 0x323, + 0xffff); /* TxphCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3100, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x2, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_INVALID_CLK_CONFIG, + ADI_COMMON_ACT_WARN_CHECK_PARAM, + NULL, + "WARNING: Clock config is not supported. Performance may suffer."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + /* Uses the settings from refClk == 245.76 & laneRate == 24.3G */ + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x600, + 0x0600); /* TxdrvFreqband */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxdrvFreqband"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x009d, + fpgaLane, + 0x3c6, + 0xffff); /* TxfeCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a1, + fpgaLane, + 0xf800, + 0xffff); /* TxfeCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0053, + fpgaLane, + 0xf800, + 0xffff); /* TxfeCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0054, + fpgaLane, + 0xf800, + 0xffff); /* TxfeCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxfeCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a7, + fpgaLane, + 0x3000, + 0xffff); /* TxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fa, + fpgaLane, + 0x40, + 0x0040); /* TxswbstEn */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxswbstEn"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x4, + 0x0006); /* TxpiBiasset */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiBiasset"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0057, + fpgaLane, + 0xe218, + 0xffff); /* TxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0105, + fpgaLane, + 0x0, + 0xffff); /* TxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x006f, + fpgaLane, + 0xe, + 0xffff); /* TxphdlyCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxphdlyCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a8, + fpgaLane, + 0x0, + 0xffff); /* TxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to TxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_INVALID_CLK_CONFIG, + ADI_COMMON_ACT_WARN_CHECK_PARAM, + NULL, + "WARNING: Clock config is not supported. Performance may suffer."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_INVALID_CLK_CONFIG, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Could not find valid DRP settings for this FPGA configuration."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t fpga9025_DeserializerDrpCfg(adi_fpga9025_Device_t* device, + const uint32_t refClk_kHz, + const uint32_t laneRate, + const uint32_t qpllVcoOut_kHz, + const uint8_t fpgaLane) +{ +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 122880 && qpllVcoOut_kHz == 4915200 && laneRate == 4915200) + { + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xf81c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x2020, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x1000, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x0, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x0, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x3, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x259, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x4800, + 0xfc00); /* RxcdrCfg3Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a5, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x011c, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3Gen4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x100, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x0, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 122880 && qpllVcoOut_kHz == 4915200 && laneRate == 9830400) + { + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x2020, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x0, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x3, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x4800, + 0xfc00); /* RxcdrCfg3Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a5, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x011c, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3Gen4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x100, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x0, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 153600 && qpllVcoOut_kHz == 6144000 && laneRate == 6144000) + { + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xf81c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x1000, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x0, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x4, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x259, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x4800, + 0xfc00); /* RxcdrCfg3Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a5, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x011c, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3Gen4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x102, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x0, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 153600 && qpllVcoOut_kHz == 6144000 && laneRate == 12288000) + { + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x4, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x1e9, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x8c00, + 0xfc00); /* RxcdrCfg3Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a5, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x011c, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3Gen4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x102, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 5529600 && laneRate == 11059200) + { + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x4, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x1e9, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x8c00, + 0xfc00); /* RxcdrCfg3Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a5, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x011c, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3Gen4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x102, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && (refClk_kHz == 184320 || refClk_kHz == 245760) && qpllVcoOut_kHz == 7372800 && laneRate == 7372800) + { + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xf81c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x1000, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x0, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x4, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x259, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x4800, + 0xfc00); /* RxcdrCfg3Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a5, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x011c, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3Gen4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3002, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x0, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 7372800 && laneRate == 14745600) + { + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x4, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x1e9, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x8c00, + 0xfc00); /* RxcdrCfg3Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a5, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x011c, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3Gen4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3002, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 4915200 && laneRate == 4915200) + { + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xf81c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x2020, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x1000, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x0, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x0, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x3, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x259, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x4800, + 0xfc00); /* RxcdrCfg3Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a5, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x011c, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3Gen4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x100, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x0, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 4915200 && laneRate == 9830400) + { + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x2020, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x0, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x3, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x4800, + 0xfc00); /* RxcdrCfg3Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a5, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x011c, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3Gen4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x100, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x0, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 7372800 && laneRate == 14745600) + { + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x4, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x1e9, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x8c00, + 0xfc00); /* RxcdrCfg3Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a5, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x011c, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3Gen4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3002, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 307200 && qpllVcoOut_kHz == 6144000 && laneRate == 6144000) + { + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xf81c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x1000, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x0, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x4, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x259, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x4800, + 0xfc00); /* RxcdrCfg3Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a5, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x011c, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3Gen4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x102, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x0, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 307200 && qpllVcoOut_kHz == 6144000 && laneRate == 12288000) + { + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x4, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x1e9, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x8c00, + 0xfc00); /* RxcdrCfg3Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a5, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x011c, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3Gen4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x102, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 368640 && qpllVcoOut_kHz == 5529600 && laneRate == 11059200) + { + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x4, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x1e9, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x8c00, + 0xfc00); /* RxcdrCfg3Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a5, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x011c, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3Gen4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x102, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID && refClk_kHz == 491520 && qpllVcoOut_kHz == 4915200 && laneRate == 9830400) + { + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x2020, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x0, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x3, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x4800, + 0xfc00); /* RxcdrCfg3Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a5, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x011c, + fpgaLane, + 0x12, + 0xffff); /* RxcdrCfg3Gen4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x100, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x0, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 122880 && qpllVcoOut_kHz == 8110080 && laneRate == 16220160) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x5, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3002, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x54, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x1, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 122880 && qpllVcoOut_kHz == 8110080 && laneRate == 4055040) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x5, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x249, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3002, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x54, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x1, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xf81c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x1000, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x0, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x249, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x249, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 122880 && qpllVcoOut_kHz == 8110080 && laneRate == 8110080) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x5, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3002, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x54, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x1, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x259, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 153600 && qpllVcoOut_kHz == 10137600 && laneRate == 20275200) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x6060, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0x4040, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x1040, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0x4040, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x40, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x20, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x6, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x1e9, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x281c, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4120, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3004, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x0, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe218, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x0, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x8, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 153600 && qpllVcoOut_kHz == 10137600 && laneRate == 10137600) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x6060, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x20, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x6, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3004, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x0, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x0, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x259, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 153600 && qpllVcoOut_kHz == 10137600 && laneRate == 5068800) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x6060, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x20, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x6, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x249, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3004, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x0, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x0, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xf81c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x1000, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x0, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x249, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x249, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 12165120 && laneRate == 24330240) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x6060, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0x4040, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x1040, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0x4040, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x40, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x20, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x6, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x1e9, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x281c, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4120, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3004, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x0, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe218, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x0, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x8, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 12165120 && laneRate == 12165120) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x6060, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x20, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x6, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3004, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x0, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x0, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x259, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 12165120 && laneRate == 6082560) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x6060, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x20, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x6, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x249, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3004, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x0, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x0, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xf81c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x1000, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x0, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x249, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x249, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 9123840 && laneRate == 18247680) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x6060, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x20, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x5, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x1e9, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x281c, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4120, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x104, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x0, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe218, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x0, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x8, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x1000, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x600, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1800, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 184320 && qpllVcoOut_kHz == 9123840 && laneRate == 9123840) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x6060, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x20, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x5, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x104, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x0, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x0, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x1000, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x600, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x259, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1800, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 12165120 && laneRate == 24330240) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x6060, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0x4040, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x1040, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0x4040, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x40, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x20, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x6, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x1e9, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x281c, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4120, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3004, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x0, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe218, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x0, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x8, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 12165120 && laneRate == 12165120) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x6060, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x20, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x6, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3004, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x0, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x0, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x259, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 8110080 && laneRate == 16220160) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x5, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3002, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x54, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x1, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 8110080 && laneRate == 4055040) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x5, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x249, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3002, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x54, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x1, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xf81c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x1000, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x0, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x249, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x249, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 8110080 && laneRate == 8110080) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x5, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3002, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x54, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x1, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x259, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 307200 && qpllVcoOut_kHz == 10137600 && laneRate == 20275200) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x6060, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0x4040, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x1040, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0x4040, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x40, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x20, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x6, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x1e9, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x281c, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4120, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3004, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x0, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe218, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x0, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x8, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 307200 && qpllVcoOut_kHz == 10137600 && laneRate == 10137600) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x6060, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x20, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x6, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3004, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x0, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x0, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x259, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 307200 && qpllVcoOut_kHz == 10137600 && laneRate == 5068800) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x6060, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x20, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x6, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x249, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3004, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x0, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x0, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xf81c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x1000, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x0, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x249, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x249, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 368640 && qpllVcoOut_kHz == 9123840 && laneRate == 18247680) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x6060, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x20, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x5, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x1e9, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x281c, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4120, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x104, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x0, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe218, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x0, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x8, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x1000, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x600, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1800, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 368640 && qpllVcoOut_kHz == 9123840 && laneRate == 9123840) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x6060, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x20, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x5, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x104, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x0, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x0, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x1000, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x600, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x259, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x259, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1800, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 491520 && qpllVcoOut_kHz == 8110080 && laneRate == 16220160) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x5, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3002, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x54, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x1, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return ADI_COMMON_ACT_NO_ACTION; + } + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID && refClk_kHz == 245760 && qpllVcoOut_kHz == 4055040 && laneRate == 8110080) + { + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x2020, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x10c0, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0xc0c0, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x80c0, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x0, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x3, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x0, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x200, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4101, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x100, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x54, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xE200, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x1, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x1000, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x600, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x2, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x0300, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + return ADI_COMMON_ACT_NO_ACTION; + } + + /* Default cases Logs a warning if the code gets to here but allows init to continue since the configuration may work OK. */ + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID) + { + /* Uses the settings from refClk == 245.76 & laneRate == 14.7G */ + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x4040, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x10, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x4, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x1e9, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0011, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x8c00, + 0xfc00); /* RxcdrCfg3Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a5, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x011c, + fpgaLane, + 0x23, + 0xffff); /* RxcdrCfg3Gen4 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg3Gen4"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3002, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x4, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + /* Uses the settings from refClk == 245.76 & laneRate == 24.3G */ + adi_fpga9025_DrpWrite(device, + 0x0116, + fpgaLane, + 0x6060, + 0xffff); /* ChHspmux */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to ChHspmux"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f7, + fpgaLane, + 0x4040, + 0xffff); /* Ckcal1Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f8, + fpgaLane, + 0x1040, + 0xffff); /* Ckcal1Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal1Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00f9, + fpgaLane, + 0x4040, + 0xffff); /* Ckcal2Cfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0101, + fpgaLane, + 0x40, + 0xffff); /* Ckcal2Cfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Ckcal2Cfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00fb, + fpgaLane, + 0x20, + 0x0030); /* PreiqFreqBst */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PreiqFreqBst"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00dd, + fpgaLane, + 0x6, + 0x0007); /* RtxBufCmlCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RtxBufCmlCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0010, + fpgaLane, + 0x1e9, + 0xffff); /* RxcdrCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010a, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal1IqLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1IqLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0108, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal1ILoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1ILoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0109, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal1QLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal1QLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010e, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2DxLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DxLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010b, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2DLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2DLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010d, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2SLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2SLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x010c, + fpgaLane, + 0x4, + 0xffff); /* Rxckcal2XLoopRstCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to Rxckcal2XLoopRstCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b1, + fpgaLane, + 0x281c, + 0xffff); /* RxdfeKhCfg2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00b0, + fpgaLane, + 0x4120, + 0xffff); /* RxdfeKhCfg3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxdfeKhCfg3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0075, + fpgaLane, + 0x3004, + 0xffff); /* RxpiCfg0 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg0"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d2, + fpgaLane, + 0x0, + 0xffff); /* RxpiCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxpiCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c6, + fpgaLane, + 0xe218, + 0xffff); /* RxProgdivCfg */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivCfg"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0103, + fpgaLane, + 0x0, + 0xffff); /* RxProgdivRate */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxProgdivRate"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0066, + fpgaLane, + 0x8, + 0x000c); /* RxWidemodeCdr */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxWidemodeCdr"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0092, + fpgaLane, + 0xfb1c, + 0xffff); /* AdaptCfg1 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to AdaptCfg1"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00c3, + fpgaLane, + 0x3500, + 0xffff); /* PcieBufgDivCtrl */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PcieBufgDivCtrl"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x400, + 0x0600); /* PciePllSelModeGen12 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen12"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x0135, + fpgaLane, + 0x269, + 0x03ff); /* RxcdrCfg2Gen2 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen2"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00a4, + fpgaLane, + 0x269, + 0xffff); /* RxcdrCfg2Gen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxcdrCfg2Gen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00d3, + fpgaLane, + 0x0, + 0x0002); /* RxXmodeSel */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to RxXmodeSel"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_fpga9025_DrpWrite(device, + 0x00ad, + fpgaLane, + 0x1000, + 0x0300); /* PciePllSelModeGen3 */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + "Could not write to PciePllSelModeGen3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_INVALID_CLK_CONFIG, + ADI_COMMON_ACT_WARN_CHECK_PARAM, + NULL, + "WARNING: Clock config is not supported. Performance may suffer."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_INVALID_CLK_CONFIG, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Could not find valid DRP settings for this FPGA configuration."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return ADI_COMMON_ACT_NO_ACTION; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025.h new file mode 100644 index 0000000..254b989 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025.h @@ -0,0 +1,228 @@ +/** +* \file adi_fpga9025.h +* \brief Contains top level fpga9025 related function prototypes for +* adi_fpga9025.c +* +* FPGA9025 API Version: 6.4.0.14 +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_H_ +#define _ADI_FPGA9025_H_ + +#include "adi_fpga9025_types.h" +#include "adi_fpga9025_error.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \brief Performs a Hardware Initialization for FPGA Device. +* +* \pre This function may be called after device->common.devHalInfo has been initialized with +* user values +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to FPGA device data structure +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +*/ +int32_t adi_fpga9025_HwOpen(adi_fpga9025_Device_t* device); + +/** +* \brief Performs a hardware shutdown for FPGA Device. +* +* \pre This function may be called after device->common.devHalInfo has been initialized with +* user values +* +* \dep_begin +* \dep{device->common.devHalInfo} +* \dep_end +* +* \param device Pointer to FPGA device data structure +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +*/ +int32_t adi_fpga9025_HwClose(adi_fpga9025_Device_t* device); + +/** +* \brief Reads the Major, Minor, & Design ID bitfields and stores these values +* in the device->devStateInfo structure. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_VersionRead(adi_fpga9025_Device_t* device); + +/** +* \brief Unimplemented. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param detectedRefClock_kHz FPGA high speed serial reference clock frequency returned in this parameter in kHz. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RefClockFreqRead(adi_fpga9025_Device_t* device, + uint32_t* detectedRefClock_kHz); + +/** +* \brief Unimplemented. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RegisterReset(adi_fpga9025_Device_t* device); + +/** +* \brief Unimplemented. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param IpToReset is a bit mask comprised of fpgaIpBlockResets_t enum types which select the FPGA IP blocks +* to be reset +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_IpReset(adi_fpga9025_Device_t* device, + uint32_t IpToReset); + +/** +* \brief Dynamic Reconfiguration Port (DRP) read helper function. After a successful +* DRP read the rdMask value is applied to the register address value and the value +* written to the address pointed to by rdWord. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param addr is a uint32_t DRP address word +* \param drp is a adi_fpga_DrpInterface_e enum type for DRP selection +* \param rdWord is uint32_t pointer to the register read value +* \param rdMask is applied to the word read from the DRP register +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_DrpRead(adi_fpga9025_Device_t* device, + adi_fpga9025_DrpAddress_e addr, + uint8_t drp, + uint16_t* rdWord, + adi_fpga9025_DrpMask_e rdMask); + +/** +* \brief Dynamic Reconfiguration Port (DRP) write helper function. The addr, wrWord, and wrMask are written to the +* appropriate DRP bitfields based on the drp parameter. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param addr is a uint32_t DRP address word +* \param drp is a uin32_t for DRP selection. See adi_fpga_DrpInterface_e for valid values. +* \param wrWord is a uint32_t register write value +* \param wrMask is written to a DRP configuration register and is applied internally +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_DrpWrite(adi_fpga9025_Device_t* device, + uint32_t addr, + uint8_t drp, + uint16_t wrWord, + uint16_t wrMask); + +/** +* \brief Initializes the FPGA based on the settings in initSettings. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param initSettings initialisation settings for fpga. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_InitSet(adi_fpga9025_Device_t* device, + adi_fpga9025_Init_t* initSettings); + +/** +* \brief Populates the initSettings structure based on the values read back from the FPGA. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param initsettings initialisation settings for fpga. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_InitGet(adi_fpga9025_Device_t* device, + adi_fpga9025_Init_t* initsettings); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_axi_adv_spi.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_axi_adv_spi.h new file mode 100644 index 0000000..677d58c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_axi_adv_spi.h @@ -0,0 +1,36 @@ +/** +* \file adi_fpga9025_axi_adv_spi.h +* \brief Contains top level fpga9025 related function prototypes for +* adi_fpga9025.c +* +* FPGA9025 API Version: 6.4.0.14 +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_axi_adv_spi_H_ +#define _ADI_FPGA9025_axi_adv_spi_H_ + +#include "adi_fpga9025_axi_adv_spi_types.h" +#include +#include "adi_fpga9025.h" +//#include "adi_common_macros.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +int32_t adi_fpga9025_AxiAdvSpiCfgSet(adi_fpga9025_Device_t* device, + adi_fpga9025_AxiAdvSpiFeatConfig_t* advSpiCfg, + uint8_t slaveSelect); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_axi_adv_spi_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_axi_adv_spi_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_axi_adv_spi_types.h new file mode 100644 index 0000000..4258523 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_axi_adv_spi_types.h @@ -0,0 +1,129 @@ +/** +* \file adi_fpga9025.h +* \brief Contains top level fpga9025 related function prototypes for +* adi_fpga9025.c +* +* FPGA9025 API Version: 6.4.0.14 +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_AXI_ADV_SPI_TYPES_H_ +#define _ADI_FPGA9025_AXI_ADV_SPI_TYPES_H_ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef struct adi_fpga9025_AxiAdvSpiVersion +{ + uint8_t module_version_major; /*!< Global Interrupt Enable. Allows passing all individually enabled interrupts to the interrupt controller. When set to: 0 = Disabled. 1 = Enabled.*/ + uint16_t module_version_minor; /*!< Global Interrupt Enable. Allows passing all individually enabled interrupts to the interrupt controller. When set to: 0 = Disabled. 1 = Enabled.*/ +} adi_fpga9025_AxiAdvSpiVersion_t; + +// typedef struct adi_fpga9025_AxiAdvSpiDgier +// { +// uint8_t gie; /*!< Global Interrupt Enable. Allows passing all individually enabled interrupts to the interrupt controller. When set to: 0 = Disabled. 1 = Enabled.*/ +// } adi_fpga9025_AxiAdvSpiDgier_t; + +typedef struct adi_fpga9025_AxiAdvSpiIpisr +{ + uint8_t tx_fifo_half_empty; /*!< Transmit FIFO Half Empty.*/ + uint8_t drr_overrun; /*!< Data Receive Register/FIFO Overrun.*/ + uint8_t drr_full; /*!< Data Receive Register/FIFO Full.*/ + uint8_t dtr_empty; /*!< Data Transmit Register/FIFO Empty. */ + uint8_t modf; /*!< Mode Fault Error. */ +} adi_fpga9025_AxiAdvSpiIpisr_t; + +typedef struct adi_fpga9025_AxiAdvSpiIpier +{ + uint8_t tx_fifo_half_empty_ien; /*!< Transmit FIFO Half Empty IRQ Enable. 0 = Disabled. 1 = Enabled..*/ + uint8_t drr_overrun; /*!< Data Receive Register/FIFO Overrun IRQ Enable. 0 = Disabled. 1 = Enabled.*/ + uint8_t drr_full; /*!< Data Receive Register/FIFO Full IRQ Enable. 0 = Disabled. 1 = Enabled.*/ + uint8_t dtr_empty_ien; /*!< Data Transmit Register/FIFO Empty IRQ Enable. 0 = Disabled. 1 = Enabled. */ + uint8_t modf_ien; /*!< Mode Fault Error IRQ Enable. 0 = Disabled. 1 = Enabled. */ +} adi_fpga9025_AxiAdvSpiIpier_t; + +/** +* \brief Data structure to hold SPI settings for all system device types +*/ +typedef struct adi_fpga9025_AxiAdvSpiSpicr +{ + uint8_t lsbFirst; /*!< 1 = MSB First, 0 = LSB First Bit order for SPI transaction. Default = 0 (msbFirst*/ + uint8_t mstr_inhibit; /*!< This bit inhibits master transactions. This bit has no effect on slave operation. Default = 1 (Disabled)*/ + uint8_t man_ss_en; /*!< Manual Slave Select Assertion Enable. Default = 1 (Disabled)*/ + uint8_t rx_fifo_reset; /*!< RX FIFO Reset. When written to 1, this bit forces a reset of the receive FIFO to the empty condition. Default = 0 (Disabled)*/ + uint8_t tx_fifo_reset; /*!< TX FIFO Reset. When written to 1, this bit forces a reset of the transmit FIFO to the empty condition. Default = 0 (Disabled)*/ + uint8_t cpha; /*!< Clock Phase. Setting this bit defines the default clock phase. */ + uint8_t cpol; /*!< Clock Polarity. When set to: 0 = Active-High clock; SCK idles Low. 1 = Active-Low clock; SCK idles High. */ + uint8_t master; /*!< Master Mode Select. When set to: 0 = Active-High clock; SCK idles Low. 1 = Active-Low clock; SCK idles High. */ + uint8_t spe; /*!< 1= SPI System Enable. */ + uint8_t loop; /*!< 0= Normal Operation; 1=The transmitter output is internally connected to the receiver input */ +} adi_fpga9025_AxiAdvSpiSpicr_t; + +/** + * \brief Data structure to hold SPI settings for all system device types + */ +typedef struct adi_fpga9025_AxiAdvSpiSpisr +{ + uint8_t modf_flag; /*!< Mode Fault Error Flag.*/ + uint8_t tx_full; /*!< Transmit Full Flag. This bit is set high when the transmit FIFO is full.*/ + uint8_t tx_empty; /*!< Transmit Empty Flag. This bit is set high when the transmit FIFO is empty.*/ + uint8_t rx_full; /*!< Receive Full Flag. This bit is set high when the receive FIFO is full.*/ + uint8_t rx_empty; /*!< Receive Empty Flag. This bit is set high when the receive FIFO is empty.*/ +} adi_fpga9025_AxiAdvSpiSpisr_t; + +typedef struct adi_fpga9025_AxiAdvSpiFeatConfig +{ + uint16_t clockDiv; /*!< Advanced Feature Set Clock Divider.*/ + uint8_t threeWireTriPoint; /*!< Advanced Feature Set Three Wire Tristate Point.*/ + uint8_t misoSampleSlip; /*!< Advanced Feature Set MISO Sample Slip.*/ + uint8_t fourWire; /*!< Advanced Feature Set Four Wire Mode.*/ + uint8_t lsbFirst; /*!< Advanced Feature Set LSB First.*/ + uint8_t cpha; /*!< Advanced Feature Set Clock Phase.*/ + uint8_t cpol; /*!< Advanced Feature Set Clock Polarity.*/ + uint8_t enable; /*!< Advanced Feature Set Enable.*/ +} adi_fpga9025_AxiAdvSpiFeatConfig_t; + +// typedef struct adi_fpga9025_AxiAdvSpiSpidtr +// { +// uint8_t tx_data; /*!< Transmit Data. Data to be pushed into the TX Data FIFO.*/ +// } adi_fpga9025_AxiAdvSpiSpidtr_t; + +// typedef struct adi_fpga9025_AxiAdvSpiSpidrr +// { +// uint8_t rx_data; /*!< Transmit Data. Data to be pushed into the TX Data FIFO.*/ +// } adi_fpga9025_AxiAdvSpiSpidrr_t; + +// typedef struct adi_fpga9025_AxiAdvSpiSpissr +// { +// uint32_t slave_select; /*!< Slave Select. Active-Low, one-hot encoded slave select vector.*/ +// } adi_fpga9025_AxiAdvSpiSpissr_t; + +// typedef struct adi_fpga9025_AxiAdvSpiTxFIFOocy +// { +// uint8_t tx_fifo_occupancy; /*!< Transmit FIFO Occupancy. This field indicates the number of elements that are currently in the transmit FIFO..*/ +// } adi_fpga9025_AxiAdvSpiTxFIFOocy_t; + +typedef struct adi_fpga9025_axiAdvSpiSettings +{ + adi_fpga9025_AxiAdvSpiVersion_t spiModVersion; /*!< axi_adv_spi module version */ + adi_fpga9025_AxiAdvSpiIpisr_t spiIntStatus; /*!< The IP Interrupt Status Register */ + adi_fpga9025_AxiAdvSpiIpier_t spiIntEnable; /*!< Interrupt Enable Register */ + adi_fpga9025_AxiAdvSpiSpicr_t spiCtrlRegSettings; /*!< SPI settings data structure */ + adi_fpga9025_AxiAdvSpiSpisr_t SpiStatus; /*!< Holds settings for CLKPLL and reference clock */ + adi_fpga9025_AxiAdvSpiFeatConfig_t advFeatSS[32]; /*!< Advanced Feature Configuration Register for Slave Select 0-31. */ +} adi_fpga9025_axiAdvSpiSettings_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_AXI_ADV_SPI_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_clk.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_clk.h new file mode 100644 index 0000000..143336d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_clk.h @@ -0,0 +1,200 @@ +/** + * \file: adi_fpga9025_jesd.h + * + * \brief Contains top level tx fpga9025 related prototypes + * + * FPGA9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_CLK_H_ +#define _ADI_FPGA9025_CLK_H_ + +#include +#include "adi_fpga9025_types.h" +#include "adi_fpga9025_clk_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif +/** +* \brief writes the configuration to the FPGA MMCM via the Dynamic Reconfiguration Port (DRP) +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param mmcmSel selection of the mmcm device to config +* \param mmcm is a adi_fpga_MmcmCfg_t used to configure the mmcm +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_MmcmSet(adi_fpga9025_Device_t* device, + adi_fpga9025_MmcmSel_e mmcmSel, + adi_fpga9025_MmcmCfg_t* mmcm); + +/** +* \brief reads the configuration to the FPGA MMCM clock tile via the Dynamic Reconfiguration Port (DRP) +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param mmcmSel selection of the mmcm device to config +* \param mmcm is a adi_fpga_MmcmCfg_t used to configure the mmcm +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_MmcmGet(adi_fpga9025_Device_t* device, + adi_fpga9025_MmcmSel_e mmcmSel, + adi_fpga9025_MmcmCfg_t* mmcm); + +/** +* \brief Returns the value of the MMCM lock bit +* +* \dep_begin +* \dep{device} +* \dep{mmcm} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param mmcmSel selection of the mmcm device to config, rx or tx +* \param lockBit Pointer to return lock bit value +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_MmcmLockGet(adi_fpga9025_Device_t* device, + adi_fpga9025_MmcmSel_e mmcmSel, + uint8_t* lockBit); + +/** +* \brief Peforms a soft reset on the selected MMCM. The reset is self-clearing. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param mmcmSel selection of the mmcm device to config +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_MmcmResetSet(adi_fpga9025_Device_t* device, + adi_fpga9025_MmcmSel_e mmcmSel); + +/** +* \brief writes the configuration to the FPGA QPLL via the Dynamic Reconfiguration Port (DRP) +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param quadMask selection of the Qpll device to config +* \param qPll is a adi_fpga9025_QpllCfg_t used to configure the Qpll +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_QpllSet(adi_fpga9025_Device_t* device, + uint8_t quadMask, + adi_fpga9025_QpllCfg_t* qPll); + +/** +* \brief reads the configuration to the FPGA QPLL via the Dynamic Reconfiguration Port (DRP) +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param quadSel one of adi_fpga9025_QPLL_Quad_e enum values +* \param bandSel one of adi_fpga9025_LaneClkSel_e enum values +* \param qPll is a adi_fpga9025_QpllCfg_t used to configure the Qpll +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_QpllGet(adi_fpga9025_Device_t* device, + adi_fpga9025_Qpll_Quad_e quadSel, + adi_fpga9025_LaneClkSel_e bandSel, + adi_fpga9025_QpllCfg_t* qPll); + +/** +* \brief Returns the valueo of the QPLL lock bit pointed to by the quadMask and bandSel +* +* \dep_begin +* \dep{device} +* \dep{qPll->band} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param quadSel selecting either 0 for quad 0 or 1 for quad 1 +* \param bandSel selecting either 0 for qpll0 or 1 for qpll1 +* \param lockBit will be set with the lock bit bitfield value, either 0 or 1 +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_ERR_RESET_SPI Recovery action for SPI reset required +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_QpllLockGet(adi_fpga9025_Device_t* device, + uint8_t quadSel, + uint8_t bandSel, + uint8_t* lockBit); + +/** +* \brief Reads the power good bit for each lane +* +* This function will return a mask indicating the status of each channel's power good bit +* +* Dependencies +* - device->common.devHalInfo +* +* \param device is structure pointer to AD9528 clock device structure +* \param quadSel 0 for quad 0; 1 for quad 1 +* \param powerGood status an 8-bit mask of each channels power good bit, bit 7 = channel 7's power good, etc. +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action +* required +*/ +int32_t adi_fpga9025_LanePowerGoodGet(adi_fpga9025_Device_t* device, + uint8_t quadSel, + uint8_t* powerGood); //todo: move this to jesd.h + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_CLK_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_clk_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_clk_types.h new file mode 100644 index 0000000..51ce915 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_clk_types.h @@ -0,0 +1,80 @@ +/*! +* \file adi_fpga9025_types.h +* \brief Contains ADRV9025 API configuration and run-time type definitions +* +* ADRV9025 API Version: 6.4.0.14 +* +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_CLK_TYPES_H_ +#define _ADI_FPGA9025_CLK_TYPES_H_ + +#include +#include "adi_fpga9025_jesd_types.h" + +#define ADI_FPGA9025_NUM_MMCM_OUTPUT_CLOCKS 7 +#define ADI_FPGA9025_PHY_NUM_CHANNELS 8 + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum adi_fpga9025_Qpll_Band +{ + ADI_FPGA9025_QPLL_BAND0 = 0x0, + ADI_FPGA9025_QPLL_BAND1 = 0x1 +} adi_fpga9025_Qpll_Band_e; + +typedef enum adi_fpga9025_QpllClkSel +{ + ADI_FPGA9025_QPLL_GTREFCLK0 = 0x1, + ADI_FPGA9025_QPLL_GTREFCLK1 = 0x2, + ADI_FPGA9025_QPLL_GTNORTHREFCLK0 = 0x3, + ADI_FPGA9025_QPLL_GTNORTHREFCLK1 = 0x4, + ADI_FPGA9025_QPLL_GTSOUTHREFCLK0 = 0x5, + ADI_FPGA9025_QPLL_GTSOUTHREFCLK1 = 0x6, + ADI_FPGA9025_QPLL_GTGREFCLK = 0x7 +} adi_fpga9025_QpllClkSel_e; + +typedef enum adi_fpga9025_MmcmSel +{ + ADI_FPGA9025_CORE_MMCM +} adi_fpga9025_MmcmSel_e; + +typedef struct adi_fpga9025_QpllCfg +{ + uint8_t quadSelect; /*! Apply these settings to the selected quads (0x3 for both; 0x2 for quad 1; 0x1 for quad 0) */ + adi_fpga9025_LaneClkSel_e band; /*! GTX QPLL upper or lower band VCO select, */ + adi_fpga9025_QpllClkSel_e refClkSelect[2]; /*! GTX QPLL Ref Clk select */ + uint16_t mVal; /*! reference clock divisor value, */ + uint16_t nVal; /*! loop divisor value, */ + uint32_t qpllVco_kHz; /*! GTX QPLL upper or lower band VCO select, */ + uint32_t qpllVcoOut_kHz; /*! The actual output freq of the QPLL */ + uint16_t lpf; /*! Value determined by FPGA reference clock & lane rate */ + uint16_t cfg4; /*! Value determined by FPGA reference clock & lane rate */ + uint16_t cp; /*! Value determined by FPGA reference clock & lane rate */ + uint16_t lockCfg; /*! Value determined by FPGA reference clock & lane rate */ + uint16_t lockCfgG3; /*! Value determined by FPGA reference clock & lane rate */ + uint8_t qpllClkOutRate; /*! 0: Out freq = Vcxo / 2; 1: Out freq = Vcxo */ +} adi_fpga9025_QpllCfg_t; + +typedef struct adi_fpga9025_MmcmCfg +{ + uint8_t mVal; + uint8_t dVal; + uint8_t outputClkDiv[7]; + uint32_t outputClkFreq_kHz[7]; +} adi_fpga9025_MmcmCfg_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_CLK_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_error.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_error.h new file mode 100644 index 0000000..40be1f4 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_error.h @@ -0,0 +1,46 @@ +/** +* \file adi_fpga9025_error.h +* \brief AD9528 ERROR header file +* +* Extension of adi_common_error +* +* API Version: 6.4.0.14 +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADI API license, for more information +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADI_FPGA9025_ERROR_H_ +#define _ADI_FPGA9025_ERROR_H_ + +#include "adi_common_error.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Extending Common error for FPGA9025 */ +#define ADI_FPGA9025_ERR_INV_NULL_INIT_PARAM 0x3001 +#define ADI_FPGA9025_ERR_DRP_ERROR 0x3002 +#define ADI_FPGA9025_ERR_CHANNEL_POWER_GOOD_FAILURE 0x3003 +#define ADI_FPGA9025_ERR_API_FAIL 0x3004 +#define ADI_FPGA9025_ERR_NUMBER_OF_ERRORS 0x3005 +#define ADI_FPGA9025_ERR_REGISTER_IO_FAIL 0x3006 +#define ADI_FPGA9025_ERR_DATA_RX_MOVER_WAIT_TIMEOUT 0x3007 /*!< API NG - Timeout occurred during Rx transaction */ +#define ADI_FPGA9025_ERR_LINK_LAYER_RESET_FAIL 0x3008 +#define ADI_FPGA9025_ERR_INVALID_FPGA_IMAGE 0x3009 +#define ADI_FPGA9025_ERR_CLOCK_FAILURE 0x300A +#define ADI_FPGA9025_ERR_PHY_RESET_FAIL 0x300B +#define ADI_FPGA9025_ERR_INVALID_CLK_CONFIG 0x300C + +/* Extending Common Actions for FPGA9025 */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_ERROR_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_gpio.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_gpio.h new file mode 100644 index 0000000..7294ddb --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_gpio.h @@ -0,0 +1,228 @@ +/** +* \file adi_fpga9025_gpio.h +* \brief Contains top level fpga9025 related function prototypes for +* adi_fpga9025_gpio.c +* +* FPGA9025 API Version: 6.4.0.14 +*/ +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_GPIO_H_ +#define _ADI_FPGA9025_GPIO_H_ + +#include "adi_fpga9025_gpio_types.h" +#include "adi_fpga9025_tdd_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \brief Writes the values to the GPIO output register. +* +* This function will write contents of wrData to the the GPIO output register +* +* \param device Pointer to the FPGA9025 data structure +* \param wrData The user provided variable containing the output register values. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9025_GpioWrite(adi_fpga9025_Device_t* device, + uint32_t wrData); + +/** +* \brief reads the values on the GPIO input register. +* +* This function will read the GPIO input register and put the value into the +* the user provided rdData variable. +* +* \param device Pointer to the FPGA9025 data structure +* \param rdData The user provided variable containing the input register values. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9025_GpioRead(adi_fpga9025_Device_t* device, + uint32_t* rdData); + +/** +* \brief Sets the gpioMode. +* +* This function will set the Gpio Mode. +* Valid Modes are +* gpioMode[2:0] | GPIO direction +* ----------------|------------------- +* 000 | normal +* 001 | Jtag +* 010 | spi2 +* +* \param device Pointer to the FPGA9025 data structure +* \param gpioMode The user provided variable containing the mode to set. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9025_GpioModeSet(adi_fpga9025_Device_t* device, + adi_fpga9025_GpioModes_e gpioMode); + +/** +* \brief Gets the gpioMode. +* +* This function will read the Gpio Mode. +* Valid Modes are +* gpioMode[2:0] | GPIO direction +* ----------------|------------------- +* 000 | normal +* 001 | Jtag +* 010 | spi2 +* +* \param device Pointer to the FPGA9025 data structure +* \param gpioMode The user provided variable into which the mode value will be written. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9025_GpioModeGet(adi_fpga9025_Device_t* device, + adi_fpga9025_GpioModes_e* gpioMode); + +/** +* \brief Sets the gpio input direction pins. +* +* This function will mask all other gpio bits and only set the bits that are high +* in the pinSelMask variable. +* +* \param device Pointer to the FPGA9025 data structure +* \param pinSelMask The user provided variable containing the mapping of bits +* to be set as input pins. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9025_GpioInputDirSet(adi_fpga9025_Device_t* device, + uint32_t pinSelMask); + +/** +* \brief Gets the gpio input direction pins. +* +* \param device Pointer to the FPGA9025 data structure +* \param pinSelMask The user provided variable which will contain the mapping of bits +* set as Input pins, a high means the pin is an input. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9025_GpioInputDirGet(adi_fpga9025_Device_t* device, + uint32_t* pinDirMask); + +/** +* \brief Sets the gpio output directction pins. +* +* This function will mask all other gpio bits and and only set the bits that are high +* in the pinSelMask variable. +* +* \param device Pointer to the FPGA9025 data structure +* \param pinSelMask The user provided variable containing the mapping of bits +* to be set as Output pins . +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9025_GpioOutputDirSet(adi_fpga9025_Device_t* device, + uint32_t pinDirMask); + +/** +* \brief Gets the gpio output directction pins. +* +* \param device Pointer to the FPGA9025 data structure +* \param pinSelMask The user provided variable which will contain the mapping of bits +* set as Output pins, a high means the pin is an Output. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9025_GpioOutputDirGet(adi_fpga9025_Device_t* device, + uint32_t* pinDirMask); + +/** +* \brief Gets the output Enable register. +* similar functionality to adi_fpga9025_GpioInputDirGet but with a different signiture +* +* This function will get gpio output enable register value +* +* \param pinSelMask The user provided variable containing the input/output mapping of bits. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9025_GpioOeGet(adi_fpga9025_Device_t* device, + uint32_t* pinSelMask); + +/** +* \brief Sets the output Enable register. +* similar functionality to adi_fpga9025_GpioInputDirSet but with a different signiture +* +* This function will set gpio pins to either input or output depending on the gpioPinType variable. +* the pinSelMask is used to mask all other gpio bits and +* only set the bits that are high in the pinSelMask. +* +* \param device Pointer to the FPGA9025 data structure +* \param gpioPinType The variable containing the direction in which to set the pins. +* \param pinSelMask The user provided variable containing the mapping of bits to set. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9025_GpioOeSet(adi_fpga9025_Device_t* device, + adi_fpga9025_GpioPinType_e gpioPinType, + uint32_t pinSelMask); + +/** +* \brief Maps the selected TDD module enable signal to the selected GPIO pin. +* +* \param device Pointer to the FPGA9025 data structure +* \param tddModuleSel The selected TDD module. +* \param gpioSel Which GPIO the tddModuleSel enable signal will be routed to. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9025_TddGpioSet(adi_fpga9025_Device_t* device, + adi_fpga9025_TddModule_e tddModuleSel, + adi_fpga9025_GpioPinSel_e gpioSel); + +/** +* \brief Returns which GPIO is mapped to the selected TDD module. +* +* \param device Pointer to the FPGA9025 data structure +* \param tddModuleSel The selected TDD module. +* \param gpioSel A pointer to adi_fpga9025_GpioPinSel_e that will hold the GPIO for the selected TDD module. +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9025_TddGpioGet(adi_fpga9025_Device_t* device, + adi_fpga9025_TddModule_e tddModuleSel, + adi_fpga9025_GpioPinSel_e* gpioSel); + +/** +* \brief Clears all TDD GPIO settings. +* +* \param device Pointer to the FPGA9025 data structure +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset. +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check. +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required. +*/ +int32_t adi_fpga9025_TddGpioAllClear(adi_fpga9025_Device_t* device); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_GPIO_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_gpio_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_gpio_types.h new file mode 100644 index 0000000..7960878 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_gpio_types.h @@ -0,0 +1,69 @@ +/*! +* \file adi_adrv9025_gpio_types.h +* \brief Contains FPGA9025 GPIO enum and struct definitions +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_GPIO_TYPES_H_ +#define _ADI_FPGA9025_GPIO_TYPES_H_ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define ADI_FPGA9025_GPIO_PINS 19 +#define ADI_FPGA9025_GPIO_MAX_VALUE 0x7FFFF + +typedef enum adi_fpga9025_GpioModes +{ + ADI_FPGA9025_GPIO_MODE_NONE = 0x0, + ADI_FPGA9025_GPIO_MODE_JTAG, + ADI_FPGA9025_GPIO_MODE_SPI2, + ADI_FPGA9025_GPIO_MODE_TDD +} adi_fpga9025_GpioModes_e; + +typedef enum adi_fpga9025_GpioPinType +{ + ADI_FPGA9025_GPIO_PIN_OUTPUT = 0x0, + ADI_FPGA9025_GPIO_PIN_INPUT = 0x1 +} adi_fpga9025_GpioPinType_e; + +typedef enum adi_fpga9025_GpioPinSel +{ + ADI_FPGA9025_GPIO_00 = 0, /*!< Select GPIO_00*/ + ADI_FPGA9025_GPIO_01, /*!< Select GPIO_01*/ + ADI_FPGA9025_GPIO_02, /*!< Select GPIO_02*/ + ADI_FPGA9025_GPIO_03, /*!< Select GPIO_03*/ + ADI_FPGA9025_GPIO_04, /*!< Select GPIO_04*/ + ADI_FPGA9025_GPIO_05, /*!< Select GPIO_05*/ + ADI_FPGA9025_GPIO_06, /*!< Select GPIO_06*/ + ADI_FPGA9025_GPIO_07, /*!< Select GPIO_07*/ + ADI_FPGA9025_GPIO_08, /*!< Select GPIO_08*/ + ADI_FPGA9025_GPIO_09, /*!< Select GPIO_09*/ + ADI_FPGA9025_GPIO_10, /*!< Select GPIO_10*/ + ADI_FPGA9025_GPIO_11, /*!< Select GPIO_11*/ + ADI_FPGA9025_GPIO_12, /*!< Select GPIO_12*/ + ADI_FPGA9025_GPIO_13, /*!< Select GPIO_13*/ + ADI_FPGA9025_GPIO_14, /*!< Select GPIO_14*/ + ADI_FPGA9025_GPIO_15, /*!< Select GPIO_15*/ + ADI_FPGA9025_GPIO_16, /*!< Select GPIO_16*/ + ADI_FPGA9025_GPIO_17, /*!< Select GPIO_17*/ + ADI_FPGA9025_GPIO_18, /*!< Select GPIO_18*/ + ADI_FPGA9025_GPIO_INVALID /*!< Invalid GPIO*/ +} adi_fpga9025_GpioPinSel_e; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_GPIO_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_hal.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_hal.h new file mode 100644 index 0000000..21184aa --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_hal.h @@ -0,0 +1,160 @@ +/** +* \file adi_fpga9025_hal.h +* \brief Contains ADI Transceiver Hardware Abstraction functions +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ +#ifndef _ADI_FPGA9025_HAL_H_ +#define _ADI_FPGA9025_HAL_H_ + +#include +#include +#include "adi_fpga9025_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Performs a read of a single 32-bit register +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param addr Address of the register to be read. Must be on a word boundary +* \param data Pointer where the register value will be assigned +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RegisterRead(adi_fpga9025_Device_t* device, + uint32_t addr, + uint32_t* data); + +/** +* \brief Performs a write of a single 32-bit register +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param addr Address of the register to be written. Must be on a word boundary +* \param data The data to write +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RegisterWrite(adi_fpga9025_Device_t* device, + uint32_t addr, + uint32_t data); + +/** +* \brief Performs bit field read +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param addr Address of the register where the field resides +* \param fieldVal A pointer to store the value in the field +* \param mask A bit-wise mask that determines which bits are part of the field +* \param startBit The bit location in the addr where the field starts +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RegisterFieldRead(adi_fpga9025_Device_t* device, + const uint32_t addr, + uint32_t* fieldVal, + uint32_t mask, + uint8_t startBit); + +/** +* \brief Performs bit field write +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param addr Address of the register where the field resides +* \param fieldVal The value to write to the field +* \param mask A bit-wise mask that determines which bits are part of the field +* \param startBit The bit location in the addr where the field starts +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RegisterFieldWrite(adi_fpga9025_Device_t* device, + const uint32_t addr, + uint32_t fieldVal, + uint32_t mask, + uint8_t startBit); + +/** +* \brief Performs a RAM memory read. ramAddress should be from 0GB - 16GB and must be on a 32-word boundary. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param ramAddress Address to begin the read from +* \param data An array to hold the values read back from RAM. Must have enough space to store 'length' elements +* \param length The number of words to read starting from ramAddress +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RamRead(adi_fpga9025_Device_t* device, + const uint64_t ramAddress, + uint32_t data[], + uint32_t length); + +/** +* \brief Performs a RAM memory write. ramAddress should be from 0GB - 16GB and must be on a 32-word boundary. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param ramAddress Address to begin writing to +* \param data An array that holds the values to write to RAM +* \param length The number of words to write starting at ramAddress +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RamWrite(adi_fpga9025_Device_t* device, + const uint64_t ramAddress, + uint32_t data[], + uint32_t length); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_HAL_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_jesd.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_jesd.h new file mode 100644 index 0000000..8127f7d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_jesd.h @@ -0,0 +1,824 @@ +/** + * \file: adi_fpga9025_jesd.h + * + * \brief Contains top level tx fpga9025 related prototypes + * + * FPGA9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_JESD_H_ +#define _ADI_FPGA9025_JESD_H_ + +#include "adi_fpga9025_types.h" +#include "adi_fpga9025_jesd_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t adi_fpga9025_SerializerCfgSet(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + adi_fpga9025_SerializerCfg_t* serializerCfg); + +/** +* \brief reads the configuration to one or more FPGA JESD204B Serializer +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param laneSel an adi_fpga9025_LaneSel_e enum value +* \param serializerCfg contains the serializer configuration setting +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_SerializerCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_LaneSel_e laneSel, + adi_fpga9025_SerializerCfg_t* serializerCfg); + +/** +* \brief Sets the reset bit for both rx & tx channel in the selected lanes +* Used as part of PHY bring up +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param laneSelMask an adi_fpga9025_LaneSel_e enum value +* \param resetVal either 0 or 1. Value to be written to the reset bit (1 to reset; 0 to release reset) +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_SerializerResetSet(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + uint8_t resetVal); + +/** +* \brief Returns the tx reset done for all eight PHY lanes +* Note: channels must have stable clock input for Reset Done to be set +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param txResetDone pointer that will be assigned each lanes tx reset done bit +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_SerializerResetDoneGet(adi_fpga9025_Device_t* device, + uint8_t* txResetDone); + +/** +* \brief Sets the lane cpll power down bit +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param laneSelMask mask to select which channels to apply pdVal +* \param pdVal either 0 or 1. Value to be written to the cpll power down bit (1 to reset; 0 to release reset) +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_LaneCpllPdSet(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + uint8_t pdVal); + +/** +* \brief writes the configuration of one or more FPGA JESD204B Deserializers +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param laneSelMask an or'd combination of one or more adi_fpga9025_LaneSel_e enum values +* \param deserializerCfg contains the deserializer configuration setting +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_DeserializerCfgSet(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + adi_fpga9025_DeserializerCfg_t* deserializerCfg); + +/** +* \brief reads the configuration to one or more FPGA JESD204B Deserializer +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param laneSel an adi_fpga9025_LaneSel_e enum value +* \param deserializerCfg contains the deserializer configuration setting +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_DeserializerCfgGet(adi_fpga9025_Device_t* device, + const adi_fpga9025_LaneSel_e laneSel, + adi_fpga9025_DeserializerCfg_t* deserializerCfg); + +/** +* \brief Sets the reset bit for both rx channel in the selected lanes +* Used as part of PHY bring up +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param laneSelMask an adi_fpga9025_LaneSel_e enum value +* \param resetVal either 0 or 1. Value to be written to the reset bit (1 to reset; 0 to release reset) +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_DeserializerResetSet(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + uint8_t resetVal); + +/** +* \brief Returns the rx reset done for all eight lanes +* Note: channels must have stable clock input for Reset Done to be set +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxResetDone pointer that will be assigned each lanes rx reset done bit +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_DeserializerResetDoneGet(adi_fpga9025_Device_t* device, + uint8_t* rxResetDone); + +/** +* \brief This function writes the adi_fpga9025_DeframerCfg_t structure to the framer modules + * selected in the deframerSelMask, where the bit location corresponds to the rx link number. + * This function is used in the link bringup sequence just prior to reset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9025_DeframerSel_e enum values +* \param deframerCfg contains the deserializer configuration setting +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_DeframerCfgSet(adi_fpga9025_Device_t* device, + uint32_t deframerSelMask, + adi_fpga9025_DeframerCfg_t* deframerCfg); + +/** +* \brief Reads the configuration for a single deframer module and populates the empty adi_fpga9025_DeframerCfg_t +* structure pointed to by deframerCfg. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSel an adi_fpga9025_LinkSel_e enum value +* \param deframerCfg contains the deframer configuration setting +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_DeframerCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_DeframerSel_e deframerSel, + adi_fpga9025_DeframerCfg_t* deframerCfg); + +/** +* \brief Unimplemented +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9025_DeframerSel_e enum values +* \param resetBits the reset bits of the selected deframers will correspond with their adi_fpga9025_DeframerSel_e bit locations +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_DeframerResetGet(adi_fpga9025_Device_t* device, + uint32_t deframerSelMask, + uint8_t* resetBits); + +/** +* \brief This function writes the adi_fpga9025_FramerCfg_t structure to the framer modules +* selected in the framerSelMask, where the bit location corresponds to the tx link number. +* This function is used in the link bringup sequence just prior to reset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9025_FramerSel_e enum values +* \param framerCfg contains the deserializer configuration setting +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_FramerCfgSet(adi_fpga9025_Device_t* device, + uint8_t framerSelMask, + adi_fpga9025_FramerCfg_t* framerCfg); + +/** +* \brief Reads the configuration for a single framer module and populates the empty adi_fpga9025_FramerCfg_t +* structure pointed to by framerCfg. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSel an adi_fpga9025_FramerSel_e enum value selecting a single framer +* \param framerCfg pointer to an empty adi_fpga9025_FramerCfg_t structure +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_FramerCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_FramerSel_e framerSel, + adi_fpga9025_FramerCfg_t* framerCfg); + +/** +* \brief Reads the reset bit for the selected framers in framerSelMask and sets the corresponding bit +* in resetBits. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9025_FramerSel_e enum values +* \param resetBits the reset bits of the selected deframers will correspond with their adi_fpga9025_FramerSel_e bit locations +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_FramerResetGet(adi_fpga9025_Device_t* device, + uint32_t framerSelMask, + uint8_t* resetBits); + +/** +* \brief Sets the configuration for the first eight outputs of the Lane XBar for the selected link using +* framerSel. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSel adi_fpga9025_FramerSel_e enum value to select the laneXBar +* \param laneXBar an eight element array holding the PHY lane assignments for each output lane +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxLaneXBarCfgSet(adi_fpga9025_Device_t* device, + adi_fpga9025_FramerSel_e framerSel, + uint8_t* laneXBar); + +/** +* \brief Sets the configuration for the first eight outputs of the Lane XBar +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSel adi_fpga9025_DeframerSel_e enum value to select which deframer +* \param laneXBar an eight element array holding the PHY lane assignments for each output lane +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxLaneXBarCfgSet(adi_fpga9025_Device_t* device, + adi_fpga9025_DeframerSel_e deframerSel, + uint8_t* laneXBar); + +/** +* \brief Reads the configuration for the first eight outputs of the Lane XBar for the selected link using +* framerSel and stores them in the eight-element laneXBar array. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSel adi_fpga9025_FramerSel_e enum value to select which framer +* \param laneXBar an eight element array where the lane assignments will be written to +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxLaneXBarCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_FramerSel_e framerSel, + uint8_t* laneXBar); + +/** +* \brief Gets the configuration for the first eight outputs of the Lane XBar +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSel adi_fpga9025_DeframerSel_e enum value to select which deframer +* \param laneXBar an eight element array where the lane assignments will be written to +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxLaneXBarCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_DeframerSel_e deframerSel, + uint8_t* laneXBar); + +/** +* \brief This function goes through the reset sequence for the selected framers in +* framerSelMask, where the bit location corresponds to the tx link number. This +* function should be called after adi_fpga9025_FramerCfgSet as part of link bringup. +* After this function the framer is ready for sysref signal. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9025_FramerSel_e enum values +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_FramerReset(adi_fpga9025_Device_t* device, + uint8_t framerSelMask); + +/** +* \brief This function disables all framers selected through the framerSelMask by setting +* the fixed reset bit. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9025_FramerSel_e enum values +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_FramerDisable(adi_fpga9025_Device_t* device, + uint8_t framerSelMask); + +/** +* \brief Enables the FPGA JESD204B Rx deframer +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9025_DeframerSel_e enum values +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_DeframerReset(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask); + +/** +* \brief Disables the FPGA JESD204B Rx deframer +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9025_DeframerSel_e enum values +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_DeframerDisable(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask); + +/** +* \brief For JESD204B returns the Sync status bit for the selected deframers in deframerSelMask. +* For JESD204C The status bit for each link will be a logical +* and of mb_lock & sync_header_lock bitfield values. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9025_DeframerSel_e enum values +* \param status the Sync status bits of the selected deframers will correspond with their adi_fpga9025_DeframerSel_e bit locations +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_DeframerStatusGet(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask, + uint8_t* status); + +/** +* \brief sets the loopback value for the selected lanes +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param laneSelMask to enable prbs on a lane set the corresponding bit to 1 +* \param loopbackValue sets the loopback mode, eg 2 for near-end PCS loopback +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_ChannelLoopbackEnable(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + uint8_t loopbackValue); + +/** +* \brief sets the DFE LPM Override value for the selected lanes +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param laneSelMask to enable prbs on a lane set the corresponding bit to 1 +* \param value sets the DFE LPM Override value (1 to override, 0 to disable override) +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_ChannelDfeLpmOverrideSet(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + uint8_t value); + +/** +* \brief Sets the configuration for the sync crossbar +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param polarity The sync xbar polarity. +* \param inputSyncSel an array of eight 3-bit values indicating the input sync selection for each sync crossbar output +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_SyncXBarCfgSet(adi_fpga9025_Device_t* device, + uint8_t polarity, + uint8_t* inputSyncSel); + +/** +* \brief Reads the configuration for the sync crossbar +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param polarity Pointer to the sync xbar polarity. +* \param inputSyncSel an array of eight uin8_t types. Will be filled with the 3-bit values from the input select registers +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_SyncXBarCfgGet(adi_fpga9025_Device_t* device, + uint8_t* polarity, + uint8_t* inputSyncSel); + +/** +* \brief Setup the FPGA JESD204 reference clock and SYSREF settings +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param sysRefCfg FPGA JESD204B clock structure settings for the reference clock +* frequency and SYSREF configuration +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_SysRefControlSet(adi_fpga9025_Device_t* device, + adi_fpga9025_SysRefClkCfg_t* sysRefCfg); + +/** +* \brief Enable or disable Sysref for the selected Framers and Deframers +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9025_FramerSel_e enum values +* \param deframerSelMask an or'd combination of one or more adi_fpga9025_DeframerSel_e enum values +* \param enable ADI_ENABLE or ADI_DISABLE to enable or disable respectively +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_SysRefEnableSet(adi_fpga9025_Device_t* device, + uint8_t framerSelMask, + uint8_t deframerSelMask, + uint8_t enable); + +/** +* \brief Reads the FPGA JESD204 reference clock and SYSREF settings +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param sysRefCfg FPGA JESD204B clock structure settings for the reference clock +* frequency and SYSREF configuration +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_SysRefControlGet(adi_fpga9025_Device_t* device, + adi_fpga9025_SysRefClkCfg_t* sysRefCfg); + +/** +* \brief Requests a SYSREF to be issued +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_SysRefRequest(adi_fpga9025_Device_t* device); + +/** +* \brief This function will set the interrupt enabled register in the JESD204C link layer. The parameter +* interruptBitMask is an or'd combination of the adi_fpga9025_Jesd204cIrq_e enum. +* The linkSelMask parameter is a bitmask that encapsulates the Rx & Tx links, ie: +* +* linkSelMask | Link +* ----------------------|------------------------------------ +* Bit 0 | RX Link 0 +* Bit 1 | RX Link 1 +* Bit 2 | RX Link 2 +* Bit 3 | TX Link 0 +* Bit 4 | TX Link 1 +* +* For the Set function, any number of links can be set with the same interruptBitMask value. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param interruptBitMask uint16_t bitmask of adi_fpga9025_Jesd204cIrq_e indicating the IRQs to be enabled/disabled. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_Jesd204cLinkLayerIrqEnSet(adi_fpga9025_Device_t* device, + uint8_t linkSelMask, + uint16_t interruptBitMask); + +/** +* \brief This function will read the interrupt enabled register in the JESD204C link layer. The parameter +* interruptBitMask will be a bitmask indicating which IRQs are enabled. It is structured off the +* adi_fpga9025_Jesd204cIrq_e enum. +* The linkSel parameter is a bitmask that encapsulates the Rx & Tx links, ie: +* +* linkSel | Link +* ----------------------|------------------------------------ +* Bit 0 | RX Link 0 +* Bit 1 | RX Link 1 +* Bit 2 | RX Link 2 +* Bit 3 | TX Link 0 +* Bit 4 | TX Link 1 +* + For the Get functions, only one bit can be set in linkSel per function call. + +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param linkSelMask a bitmask to choose between Rx & Tx links +* \param interruptBitMask uint16_t pointer that will contain which IRQs are enabled/disabled. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_Jesd204cLinkLayerIrqEnGet(adi_fpga9025_Device_t* device, + uint8_t linkSelMask, + uint16_t* interruptBitMask); + +/** +* \brief This function will read the interrupt status register in the JESD204C link layer. The parameter +* interruptBitMask will be a bitmask indicating which IRQs have been triggered. It is structured off the +* adi_fpga9025_Jesd204cIrq_e enum. +* The linkSel parameter is a bitmask that encapsulates the Rx & Tx links, ie: +* +* linkSel | Link +* ----------------------|------------------------------------ +* Bit 0 | RX Link 0 +* Bit 1 | RX Link 1 +* Bit 2 | RX Link 2 +* Bit 3 | TX Link 0 +* Bit 4 | TX Link 1 +* + For the Get functions, only one bit can be set in linkSel per function call. + +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param linkSel a bitmask to choose a single Rx or Tx link +* \param interruptBitMask uint16_t pointer that will contain which IRQs are triggered with a 1 in their respective bit location. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_Jesd204cLinkLayerIrqStatusGet(adi_fpga9025_Device_t* device, + uint8_t linkSel, + uint16_t* interruptBitMask); + +/** +* \brief Enables or disables the Command and Data interface of the Deframer's selected through the deframerSelMask bitmask. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param deframerSelMask an or'd combination of one or more adi_fpga9025_DeframerSel_e enum values +* \param cmdEnable ADI_ENABLE or ADI_DISABLE to enable and disable the command interface +* \param dataEnable ADI_ENABLE or ADI_DISABLE to enable and disable the data interface +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_Jesd204CDeframerCmdDataSet(adi_fpga9025_Device_t* device, + uint32_t deframerSelMask, + uint8_t cmdEnable, + uint8_t dataEnable); + +/** +* \brief Enables or disables the Command and Data interface of the Framer's selected through the framerSelMask bitmask. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9025_FramerSel_e enum values +* \param cmdEnable ADI_ENABLE or ADI_DISABLE to enable and disable the command interface +* \param dataEnable ADI_ENABLE or ADI_DISABLE to enable and disable the data interface +* +* \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_Jesd204CFramerCmdDataSet(adi_fpga9025_Device_t* device, + uint32_t framerSelMask, + uint8_t cmdEnable, + uint8_t dataEnable); + +/** +* \brief Enable or disable Sysref for the selected Framers and Deframers +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param framerSelMask an or'd combination of one or more adi_fpga9025_FramerSel_e enum values +* \param deframerSelMask an or'd combination of one or more adi_fpga9025_DeframerSel_e enum values +* \param enable ADI_ENABLE or ADI_DISABLE to enable or disable respectively +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_SysRefEnableSet(adi_fpga9025_Device_t* device, + uint8_t framerSelMask, + uint8_t deframerSelMask, + uint8_t enable); + +int32_t adi_fpga9025_InternalSysrefEnableSet(adi_fpga9025_Device_t* device, + uint8_t enable); + +int32_t adi_fpga9025_InternalSysrefRequest(adi_fpga9025_Device_t* device); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_JESD_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_jesd_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_jesd_types.h new file mode 100644 index 0000000..1fc4b7f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_jesd_types.h @@ -0,0 +1,300 @@ +/*! +* \file adi_fpga9025_jesd_types.h +* \brief Contains FPGA9025 JESD enum and struct definitions +* +* ADRV9025 API Version: 6.4.0.14 +* +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_JESD_TYPES_H_ +#define _ADI_FPGA9025_JESD_TYPES_H_ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define ADI_FPGA9025_ZERO 0x00 +#define ADI_FPGA9025_BYTE 0xFF +#define ADI_FPGA9025_NUM_LANES 8 +#define ADI_FPGA9025_NUM_OF_DEFRAMERS 3 +#define ADI_FPGA9025_NUM_OF_FRAMERS 2 + +#define ADI_FPGA9025_2P02_GHZ 2027520 +#define ADI_FPGA9025_2P53_GHZ 2534400 +#define ADI_FPGA9025_3_GHZ 3041280 +#define ADI_FPGA9025_4P05_GHZ 4055040 +#define ADI_FPGA9025_4P91_GHZ 4915200 +#define ADI_FPGA9025_5_GHZ 5068800 +#define ADI_FPGA9025_6P08_GHZ 6082560 +#define ADI_FPGA9025_6P14_GHZ 6144000 +#define ADI_FPGA9025_7_GHZ 7372800 +#define ADI_FPGA9025_8_GHZ 8110080 +#define ADI_FPGA9025_9_GHZ 9830400 +#define ADI_FPGA9025_10_GHZ 10137600 +#define ADI_FPGA9025_11_GHZ 11059200 +#define ADI_FPGA9025_12P16_GHZ 12165120 +#define ADI_FPGA9025_12P28_GHZ 12288000 +#define ADI_FPGA9025_14_GHZ 14745600 +#define ADI_FPGA9025_16_GHZ 16220160 + +#define ADI_FPGA9025_61P44_MHZ 61440 +#define ADI_FPGA9025_122P88_MHZ 122880 +#define ADI_FPGA9025_153P6_MHZ 153600 +#define ADI_FPGA9025_184P32_MHZ 184320 +#define ADI_FPGA9025_245P76_MHZ 245760 +#define ADI_FPGA9025_307P2_MHZ 307200 +#define ADI_FPGA9025_491P52_MHZ 491520 + +/** +* \brief Enumerated list of DRP mask values +*/ +typedef enum adi_fpga9025_DrpMask +{ + ADI_FPGA9025_TXCLK25DIV_MASK = 0xF800, + ADI_FPGA9025_TXPHDLY_CFG1_MASK = 0xFFFF, + ADI_FPGA9025_TXPI_CFG3_MASK = 0x0040, + ADI_FPGA9025_TX_PROGDIV_CFG_MASK = 0xFFFF, + ADI_FPGA9025_RXCLK25DIV_MASK = 0x00F8, + ADI_FPGA9025_PMA_RSV1_MASK = 0xFFFF, + ADI_FPGA9025_RXCDR_CFG2_MASK = 0xFFFF, + ADI_FPGA9025_RXDFE_GC_CFG1_MASK = 0xFFFF, + ADI_FPGA9025_RXPI_CFG4_MASK = 0x0200, + ADI_FPGA9025_RXPI_CFG5_MASK = 0x0100, + ADI_FPGA9025_RX_EN_HI_LR_MASK = 0x0400, + ADI_FPGA9025_RX_WIDEMODE_CDR_MASK = 0x0004, + ADI_FPGA9025_RX_PROGDIV_CFG_MASK = 0xFFFF, + ADI_FPGA9025_QPLL_N_MASK = 0x00FF, + ADI_FPGA9025_QPLL_M_MASK = 0x0F80, + ADI_FPGA9025_QPLL_LPF_MASK = 0x03FF, + ADI_FPGA9025_QPLL_CFG4_MASK = 0xFFFF, + ADI_FPGA9025_QPLL_CP_MASK = 0x03FF, + ADI_FPGA9025_QPLL_FBDIV_MASK = 0x00FF, + ADI_FPGA9025_QPLL_LOCK_CFG_MASK = 0xFFFF, + ADI_FPGA9025_QPLL_LOCK_CFG_G3_MASK = 0x03FF, + ADI_FPGA9025_QPLL_REFCLK_DIV_MASK = 0x0F80, + ADI_FPGA9025_QPLL_CLKOUT_RATE_MASK = 0x0001 +} adi_fpga9025_DrpMask_e; + +/** +* \brief Enumerated list of DRP mask values +*/ +typedef enum adi_fpga9025_DrpAddress +{ + ADI_FPGA9025_TXCLK25DIV_ADDRESS = 0x007A, + ADI_FPGA9025_TXPHDLY_CFG1_ADDRESS = 0x006F, + ADI_FPGA9025_TXPI_CFG3_ADDRESS = 0x009C, + ADI_FPGA9025_TX_PROGDIV_CFG_ADDRESS = 0x0057, + ADI_FPGA9025_RXCLK25DIV_ADDRESS = 0x006D, + ADI_FPGA9025_PMA_RSV1_ADDRESS = 0x0095, + ADI_FPGA9025_RXCDR_CFG2_ADDRESS = 0x0010, + ADI_FPGA9025_RXDFE_GC_CFG1_ADDRESS = 0x00CC, + ADI_FPGA9025_RXPI_CFG4_ADDRESS = 0x009D, + ADI_FPGA9025_RXPI_CFG5_ADDRESS = 0x009D, + ADI_FPGA9025_RX_EN_HI_LR_ADDRESS = 0x0052, + ADI_FPGA9025_RX_WIDEMODE_CDR_ADDRESS = 0x0066, + ADI_FPGA9025_RX_PROGDIV_CFG_ADDRESS = 0x00C6, + ADI_FPGA9025_QPLLCLK0_N_ADDRESS = 0x0014, + ADI_FPGA9025_QPLLCLK0_M_ADDRESS = 0x0018, + ADI_FPGA9025_QPLLCLK0_LPF_ADDRESS = 0x0019, + ADI_FPGA9025_QPLLCLK0_CFG4_ADDRESS = 0x0030, + ADI_FPGA9025_QPLLCLK0_CP_ADDRESS = 0x0016, + ADI_FPGA9025_QPLLCLK0_FBDIV_ADDRESS = 0x0014, + ADI_FPGA9025_QPLLCLK0_LOCK_CFG_ADDRESS = 0x0012, + ADI_FPGA9025_QPLLCLK0_LOCK_CFG_G3_ADDRESS = 0x001D, + ADI_FPGA9025_QPLLCLK0_REFCLK_DIV_ADDRESS = 0x0018, + ADI_FPGA9025_QPLLCLK0_CLKOUT_RATE_ADDRESS = 0x000E, + ADI_FPGA9025_QPLLCLK1_N_ADDRESS = 0x0094, + ADI_FPGA9025_QPLLCLK1_M_ADDRESS = 0x0098, + ADI_FPGA9025_QPLLCLK1_CLKOUT_RATE_ADDRESS = 0x008E +} adi_fpga9025_DrpAddress_e; + +/** +* \brief Enumerated list of clk sources available to the Serializer/deserializer +*/ +typedef enum adi_fpga9025_LaneClkSel +{ + ADI_FPGA9025_CPLL = 0x0, + ADI_FPGA9025_QPLLCLK0 = 0x3, + ADI_FPGA9025_QPLLCLK1 = 0x2 +} adi_fpga9025_LaneClkSel_e; + +/** +* \brief Enumerated list of clk sources available to the Serializer/deserializer +*/ +typedef enum adi_fpga9025_Qpll_Quad +{ + ADI_FPGA9025_QPLL_QUAD0 = 0x1, + ADI_FPGA9025_QPLL_QUAD1 = 0x2 +} adi_fpga9025_Qpll_Quad_e; + +/** +* \brief Enumerated list of Gth Serializer/deserializer each is identified by a separate bit +*/ +typedef enum adi_fpga9025_LaneSel +{ + ADI_FPGA9025_LANE_0 = 0x1, /*!Gth serializer/deserializer Lane 1 */ + ADI_FPGA9025_LANE_1 = 0x2, /*!Gth serializer/deserializer Lane 2 */ + ADI_FPGA9025_LANE_2 = 0x4, /*!Gth serializer/deserializer Lane 3 */ + ADI_FPGA9025_LANE_3 = 0x8, /*!Gth serializer/deserializer Lane 4 */ + ADI_FPGA9025_LANE_4 = 0x10, /*!Gth serializer/deserializer Lane 5 */ + ADI_FPGA9025_LANE_5 = 0x20, /*!Gth serializer/deserializer Lane 6 */ + ADI_FPGA9025_LANE_6 = 0x40, /*!Gth serializer/deserializer Lane 7 */ + ADI_FPGA9025_LANE_7 = 0x80 /*!Gth serializer/deserializer Lane 8 */ +} adi_fpga9025_LaneSel_e; + +/** +* \brief Enumerated list of JESD204C interrupts each identified by a separate bit +*/ +typedef enum adi_fpga9025_Jesd204cIrq +{ + ADI_FPGA9025_GLOBAL = 0x1, /*!Global Interrupt Enable*/ + ADI_FPGA9025_SYSREF_RECEIVED = 0x2, /*!Interrupt Enable SYSREF Received*/ + ADI_FPGA9025_SYSREF_ERROR = 0X4, /*!Interrupt Enable SYSREF Error*/ + ADI_FPGA9025_LOSS_SYNC_HEADER_LOCK = 0x10, /*!Interrupt Enable Loss of 64b66b Sync Header Lock*/ + ADI_FPGA9025_LOSS_MB_LOCK = 0x20, /*!Interrupt Enable Loss of Multi-block Lock*/ + ADI_FPGA9025_BLOCK_SYNC_ERROR = 0x40, /*!Interrupt Enable Block Sync Error*/ + ADI_FPGA9025_MB_ERROR = 0x80, /*!Interrupt Enable Multi-block Error*/ + ADI_FPGA9025_CRC_ERROR = 0x100, /*!Interrupt Enable CRC Error*/ + ADI_FPGA9025_FEC_ERROR = 0x200, /*!Interrupt Enable FEC Error*/ + ADI_FPGA9025_OVERFLOW_ERROR = 0x400 /*!Interrupt Enable Overflow Error*/ +} adi_fpga9025_Jesd204cIrq_e; + +/** +* \brief Enumerated list of Gth Serializer/deserializer each is identified by a separate bit +*/ +typedef struct adi_fpga9025_SerializerCfg +{ + uint8_t chnl; /*! Identifies the lane to be configured by these settings 0..7 */ + uint8_t cpllRefClkSel; /*! Only needed for Cpll which is not used */ + adi_fpga9025_LaneClkSel_e txPllClkSel; /*! Selects the PLL to drive the transmitter data path. valid values from adi_fpga9025_PllClkSel_e */ + /* Rx Configs &TxConfigs */ + uint8_t rate; /*! Sets the final divider for the Channel receiver. The settings are: 000: Use RXOUT_DIV attributes 001: Divide by 1 010: Divide by 2 011: Divide by 4 100: Divide by 8 101: Divide by 16 110: Divide by 1 111: Divide by 1 */ + uint8_t encoder8b10bEnable; /*! 1: enable the 8b10b encoder in the Channel 0 transmitter - this is needed for JESD204B operation. 0: bypass the 8b10b encoder - this is needed for JESD204C operation.*/ + uint8_t polarity; /*! When set to 1, the corresponding transmit channel is inverted. When cleared to 0, the channel is not inverted. */ + uint8_t powerDown; /*! 00: P0 (normal operation) 01: P0s (low recovery time power down) 10: P1 (longer recovery time; Receiver Detection still on) 11: P2 (lowest power state) Attributes can control the transition times between these power-down states. */ + /* Tx Config */ + uint8_t txOutClkSel; /*! Selects the source of the output clock. 0x2 for 204B operation; 0x5 for 204C operation (default) */ + uint8_t precursor; /*! Transmitter post-cursor TX pre-emphasis control */ + uint8_t postcursor; /*! Transmitter post-cursor TX pre-emphasis control. */ + uint8_t diffCtrl; /*! Driver Swing/ Amplitude Control. */ +} adi_fpga9025_SerializerCfg_t; + +typedef struct adi_fpga9025_DeserializerCfg +{ + uint8_t chnl; /*!Identifies the lane to be configured by these settings. 0..7 */ + adi_fpga9025_LaneClkSel_e rxPllClkSel; /*! Selects the PLL to drive the receiver data path valid values from adi_fpga_qpllClkSel */ + //Rx Configs &TxConfigs; + uint8_t rate; /*! This bit field sets the final divider for the Channel receiver. valid values form adi_fpga9025_QpllFDVals_e. */ + uint8_t encoder8b10bEnable; /*! 1: enable the 8b10b encoder in the Channel 0 transmitter - this is needed for JESD204B operation. 0: bypass the 8b10b encoder - this is needed for JESD204C operation.*/ + uint8_t polarity; /*! When set to 1, the corresponding transmit channel is inverted. When cleared to 0, the channel is not inverted. */ + uint8_t powerDown; /*! 00: P0 (normal operation) 01: P0s (low recovery time power down) 10: P1 (longer recovery time; Receiver Detection still on) 11: P2 (lowest power state) Attributes can control the transition times between these power-down states.*/ + //Rx Config + uint8_t rxOutClkSel; /*! Selects the source of the output clock. 0x2 for 204B operation; 0x5 for 204C operation (default) */ + uint8_t rxDfeLpmEn; /*! Controls a receive channel's rx_dfelpm_en signal. When set to 1, the LPM equalizer is enabled. When cleared to 0, the DFE equalizer is enabled.. */ + uint8_t cdrSetting; /*! TBD */ +} adi_fpga9025_DeserializerCfg_t; + +/** +* \brief Enum to select desired FPGA deframer +*/ +typedef enum adi_fpga9025_DeframerSel +{ + ADI_FPGA9025_DEFRAMER_0 = 1, /*< Deframer 0 selected */ + ADI_FPGA9025_DEFRAMER_1 = 2, /*< Deframer 1 selected */ + ADI_FPGA9025_DEFRAMER_2 = 4, /*< Deframer 2 selected */ + ADI_FPGA9025_DEFRAMER_ALL = 7 /*< All deframers selected */ +} adi_fpga9025_DeframerSel_e; + +/** +* \brief Enum to select desired FPGA framer +*/ +typedef enum adi_fpga9025_FramerSel +{ + ADI_FPGA9025_FRAMER_0 = 1, /*< Framer 0 selected */ + ADI_FPGA9025_FRAMER_1 = 2, /*< Framer 1 selected */ + ADI_FPGA9025_FRAMER_ALL = 3 /*< All framers selected */ +} adi_fpga9025_FramerSel_e; + +typedef struct adi_fpga9025_DeframerCfg +{ + /* Common Data */ + uint8_t laneXbar[ADI_FPGA9025_NUM_LANES]; /*! Indices correspond to Lane XBar outputs. Values correspond to Lane XBar inputs */ + uint8_t sysRefDelay; /*! Add additional delay to SYSREF re-alignment of LMFC counter 1111 = 15 core_clk cycles */ + uint8_t subclassV; /*! JESD204b sublcass: Subclass 2 = 0x10 Subclass 1 = 0x01 Subclass 0 = 0x00. JESD204c subclass: 0 = Subclass 0; 1 = Subclass 1 */ + uint8_t lanesInUse; /*! Each bit corresponds to a single lane, when set to 1 lane is active. Due to Lane XBars will always fill from bit 0 */ + + /* JESD204B */ + uint8_t bankId[ADI_FPGA9025_NUM_LANES]; /*! JESD204b Configuration Bank ID extension to Device ID. Read only, captured by ILA sequence */ + uint8_t cfgLaneId[ADI_FPGA9025_NUM_LANES]; /*! Read only, captured by ILA sequence */ + uint8_t scramblingEn; /*! Set to 1 to enable scrambling. Clear to disable */ + uint16_t cfgF; /*! Octets per frame. Register programmed with value - 1 */ + uint8_t cfgK; /*! Frames per multiframe. Register programmed with value - 1 */ + uint8_t ilaNp[ADI_FPGA9025_NUM_LANES]; /*! N' (Totals bits per Sample) */ + uint8_t ilaN[ADI_FPGA9025_NUM_LANES]; /*! N Converter Resolution */ + uint8_t ilaS[ADI_FPGA9025_NUM_LANES]; /*! Number of samples per converter per frame. Read only, captured by ILA sequence. Register programmed with value - 1 */ + uint8_t ilaM[ADI_FPGA9025_NUM_LANES]; /*! Number of converters per device. Read only, captured by ILA sequence. Register programmed with value - 1 */ + uint16_t rxBufferDly; /*! Used with RX Buffer Adjust to minimize latency */ + uint16_t rxBufferAdj[ADI_FPGA9025_NUM_LANES]; /*! Used with RX Buffer Delay to minimize latency. Read only, captured by ILA sequence */ + uint8_t errReportingDisable; /*! Disable Error Reporting Using SYNC Interface */ + uint8_t ilaSupportEn; /*! ILA Support Enable */ + uint8_t sysRefAlways; /*! SYSREF Always 1 = Core re-aligns LMFC counter on all SYSREF events */ + uint8_t sysRefRequiredOnResync; /*! 1 = A SYSREF event is required following a Link Re-Sync event */ + + /* JESD204C */ + uint8_t enableCmdInterface; /*! 1 = Enables AXI4-Stream Cmd interface; 0 = Cmd words will be zeroed */ + uint8_t enableDataInterface; /*! 1 = Enables AXI4-Stream Data interface; 0 = Link will be transmitting scrambled zeros */ + uint8_t cfgE; /*! CTRL_MB_IN_EMB- Number of multi-blocks in an extended multi-block. Programmed with actual value (0 is invalid) */ + uint8_t ctrlMetaMode; /*! 0 = Cmd; 1 = CRC; 2 = FEC [TBD] */ + uint8_t ctrlRxBufAdv; /*! Advance the release of the receiver buffer by N 64-bit words */ + uint8_t ctrlRxMBlockTh; /*! MB lock threshold */ + uint16_t ctrlIrq; /*! Bit mask to enable/disable individual interrupts. Bit 0 is Global Interrupt Enable */ +} adi_fpga9025_DeframerCfg_t; + +typedef struct adi_fpga9025_FramerCfg +{ + /* Common data */ + uint8_t laneXbar[ADI_FPGA9025_NUM_LANES]; /*! Indices correspond to Lane XBar outputs. Values correspond to Lane XBar inputs */ + uint8_t sysRefDelay; /*! Add additional delay to SYSREF re-alignment of LMFC counter 1111 = 15 core_clk cycles */ + uint8_t subclassV; /*! JESD204b sublcass: Subclass 2 = 0x10 Subclass 1 = 0x01 Subclass 0 = 0x00. JESD204c subclass: 0 = Subclass 0; 1 = Subclass 1 */ + uint8_t lanesInUse; /*! Each bit corresponds to a single lane, when set to 1 lane is active. Due to Lane XBars will always fill from bit 0 */ + + /* JESD204B */ + uint8_t deviceId; /*! JESD204b Configuration Device ID. Sets value for all lanes */ + uint8_t bankId; /*! JESD204b Configuration Bank ID extension to Device ID. Sets value for all lanes */ + uint8_t scramblingEn; /*! Set to 1 to enable scrambling. Clear to disable */ + uint16_t ilaMultiFrames; /*! Multiframes in the Transmitted ILAS. Register programmed with value - 1 */ + uint16_t cfgF; /*! Octets per frame. Register programmed with value - 1 */ + uint8_t cfgK; /*! Frames per multiframe. Register programmed with value - 1 */ + uint8_t ilaM; /*! Number of converters per device. Sets value for all lanes. Register programmed with value - 1 */ + uint8_t ilaN; /*! Converter resolution. Sets value for all lanes. Register programmed with value - 1 */ + uint8_t ilaCs; /*! Control bits per sample. Sets value for all lanes */ + uint8_t ilaNp; /*! Total bits per sampele. Sets value for all lanes. Register programmed with value - 1 */ + uint8_t ilaS; /*! Samples per converter per frame. Sets value for all lanes. Register programmed with value - 1 */ + uint8_t ilaCf; /*! Control words per frame. Sets value for all lanes */ + uint8_t ilaHd; /*! High density format. Sets value for all lanes */ + uint8_t ilaSupportEn; /*! ILA Support Enable */ + uint8_t sysRefAlways; /*! SYSREF Always 1 = Core re-aligns LMFC counter on all SYSREF events */ + uint8_t sysRefRequiredOnResync; /*! 1 = A SYSREF event is required following a Link Re-Sync event */ + + /* JESD204C */ + uint8_t enableCmdInterface; /*! 1 = Enables AXI4-Stream Cmd interface; 0 = Cmd words will be zeroed */ + uint8_t enableDataInterface; /*! 1 = Enables AXI4-Stream Data interface; 0 = Link will be transmitting scrambled zeros */ + uint8_t cfgE; /*! CTRL_MB_IN_EMB- Number of multi-blocks in an extended multi-block. Programmed with actual value (0 is invalid) */ + uint8_t ctrlMetaMode; /*! 0 = Cmd; 1 = CRC; 2 = FEC [TBD] */ + uint16_t ctrlIrq; /*! Bit mask to enable/disable individual interrupts. Bit 0 is Global Interrupt Enable */ +} adi_fpga9025_FramerCfg_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_JESD_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_prbs.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_prbs.h new file mode 100644 index 0000000..81ee5df --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_prbs.h @@ -0,0 +1,123 @@ +/** +* \file adi_fpga9025.h +* \brief Contains top level fpga9025 related function prototypes for +* adi_fpga9025.c +* +* FPGA9025 API Version: 6.4.0.14 +*/ +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_PRBS_H_ +#define _ADI_FPGA9025_PRBS_H_ + +#include "adi_fpga9025_prbs_types.h" +#include "adi_fpga9025_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \brief Enable PRBS generator on the selected TX lanes with the desired PRBS mode +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param laneSelMask to enable prbs on a lane set the corresponding bit to 1 +* \param prbsSel 4 bit value selecting the prbs mode +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_PrbsSerializerEnable(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + adi_fpga9025_PrbsTestModes_e prbsModeSel); + +/** +* \brief Enable PRBS checker on the selected lanes RX with the desired PRBS mode +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param laneSelMask to enable prbs on a lane set the corresponding bit to 1 +* \param prbsSel 4 bit value selecting the prbs mode +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_PrbsDeserializerEnable(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + adi_fpga9025_PrbsTestModes_e prbsModeSel); + +/** +* \brief Inject errors on the selected TX lanes +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param laneSelMask to enable prbs on a lane set the corresponding bit to 1 +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_PrbsSerializerErrorInject(adi_fpga9025_Device_t* device, + uint8_t laneSelMask); + +/** +* \brief Reads FPGA deserializer PRBS error counts on all lanes +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param errCounts an array of uint32_t of length 8. Will be set with the error count per lane +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_PrbsErrorCountRead(adi_fpga9025_Device_t* device, + uint32_t* errCounts); + +/** +* \brief Clears the error counter on the selected RX lanes +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param laneSelMask to enable prbs on a lane set the corresponding bit to 1 +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_PrbsErrorClear(adi_fpga9025_Device_t* device, + uint8_t laneSelMask); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_PRBS_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_prbs_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_prbs_types.h new file mode 100644 index 0000000..ad6a7bd --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_prbs_types.h @@ -0,0 +1,40 @@ +/*! +* \file adi_adrv9025_tx_types.h +* \brief Contains FPGA9025 PRBS enum and struct definitions +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_PRBS_TYPES_H_ +#define _ADI_FPGA9025_PRBS_TYPES_H_ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef enum adi_fpga9025_PrbsTestModes +{ + ADI_FPGA9025_PRBS_OFF = 0, + ADI_FPGA9025_PRBS_7 = 1, + ADI_FPGA9025_PRBS_9 = 2, + ADI_FPGA9025_PRBS_15 = 3, + ADI_FPGA9025_PRBS_23 = 4, + ADI_FPGA9025_PRBS_31 = 5, + ADI_FPGA9025_SQ_2UI = 9, + ADI_FPGA9025_SQ_INT_UI = 10 +} adi_fpga9025_PrbsTestModes_e; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_PRBS_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_rx.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_rx.h new file mode 100644 index 0000000..f1e912f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_rx.h @@ -0,0 +1,466 @@ +/** + * \file: adi_fpga9025_rx.h + * + * \brief Contains top level rx fpga9025 related prototypes + * + * FPGA9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_RX_H_ +#define _ADI_FPGA9025_RX_H_ + +#include "adi_fpga9025_rx_types.h" +#include "adi_fpga9025.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \brief This function writes the adi_fpga9025_RxTollgateCfg_t structure to the tollgate +* modules selected in the rxDatamoverSelMask. This function could be used as part +* of an rx capture setup procedure if more than just the trigger select should be +* configured. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9025_RxDataMoverSel_e enum values +* \param tollGateCfg contains the tollgate configuration setting structure +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxTollgateSet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + adi_fpga9025_RxTollgateCfg_t* tollGateCfg); + +/** +* \brief Reads the configuration for a single tollgate module and populates the empty +* adi_fpga9025_RxTollgateCfg_t structure passed in to the function. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDatamoverSel an adi_fpga9025_RxDataMoverSel_e enum value selecting a single datamover +* \param tollGateCfg an empty structure that will be written with the selected tollgate's configuration values +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxTollgateGet(adi_fpga9025_Device_t* device, + adi_fpga9025_RxDatamoverSel_e rxDatamoverSel, + adi_fpga9025_RxTollgateCfg_t* tollGateCfg); + +/** +* \brief This function writes the reset bit to the tollgate +* modules selected in the rxDatamoverSelMask. The reset bit is not self-clearing +* so a full reset will require a call to this function to write a 1 then another +* call to write a 0 for normal operation. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9025_RxDataMoverSel_e enum values +* \param resetVal the reset value (1 for reset; 0 for normal operation) +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxTollgateResetSet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + uint8_t resetVal); + +/** +* \brief This function reads the reset bit to the tollgate +* modules selected in the rxDatamoverSelMask. It zeros the resetVal parameter +* and copies each module's reset value to the bit location given by the +* adi_fpga9025_RxDataMoverSel_e enum. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9025_RxDataMoverSel_e enum values +* \param resetVal a combination of all the selected tollgate modules' reset value +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxTollgateResetGet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + uint16_t* resetVal); + +/** +* \brief This function writes the trigger select to the tollgate +* modules selected in the rxDatamoverSelMask. This function could be used as part +* of an rx capture setup procedure. It puts the tollgate in reset, configures the +* trigger, then releases the reset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9025_RxDataMoverSel_e enum values +* \param triggerSelect Select from adi_fpga_TrigSources_e enum +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxTollgateTriggerSet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + adi_fpga9025_RxTollgateTrigSources_e triggerSelect); + +/** +* \brief Reads the trigger bitfield for a single tollgate module and populates the empty +* pointer passed in to the function. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDatamoverSel an adi_fpga9025_RxDataMoverSel_e enum value selecting a single datamover +* \param triggerSelect pointer to an adi_fpga9025_RxTollgateTrigSources_e enum to hold the readback value +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxTollgateTriggerGet(adi_fpga9025_Device_t* device, + adi_fpga9025_RxDatamoverSel_e rxDatamoverSel, + adi_fpga9025_RxTollgateTrigSources_e* triggerSelect); + +/** +* \brief This function writes the adi_fpga9025_RxDmaCfg_t structure to the DMA +* modules selected in the rxDatamoverSelMask. This function could be used as part +* of an rx capture setup procedure. The LastDescriptor bitfield and RunStop bits +* are not written during this function call. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9025_RxDataMoverSel_e enum values +* \param rxDmaCfg contains the dma configuration settings to apply to all selected DMA modules +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxDmaSet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + adi_fpga9025_RxDmaCfg_t* rxDmaCfg); + +/** +* \brief This function writes the static members of the adi_fpga9025_RxDmaCfg_t structure to the DMA +* modules selected in the rxDatamoverSelMask. This function is used when the fpga +* boots up. The DMAs are not ready for capture after this function. +* The LastDescriptor, RunStop, and Length bitfields are not written +* during this function call. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9025_RxDataMoverSel_e enum values +* \param rxDmaCfg contains the dma configuration settings to apply to all selected DMA modules +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxDmaInit(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + adi_fpga9025_RxDmaCfg_t* rxDmaCfg); + +/** +* \brief Reads the configuration for a single DMA module and populates the empty +* adi_fpga9025_RxDmaCfg_t structure passed in to the function. This function reads +* Read-Write & Read-Only bitfields, including status bits. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDatamoverSel an adi_fpga9025_RxDataMoverSel_e enum value selecting a single datamover +* \param rxDmaCfg contains the dma configuration setting +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxDmaGet(adi_fpga9025_Device_t* device, + adi_fpga9025_RxDatamoverSel_e rxDatamoverSel, + adi_fpga9025_RxDmaCfg_t* rxDmaCfg); + +/** +* \brief This function writes the reset bit to the dma +* modules selected in the rxDatamoverSelMask. The reset bit is self-clearing +* so there is no need to clear after setting. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9025_RxDataMoverSel_e enum values +* \param resetVal set to 1 to reset module +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxDmaResetSet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + uint8_t reset); + +/** +* \brief This function writes the run-stop bit to the dma +* modules selected in the rxDatamoverSelMask. This can be used during the middle of a transfer +* to gracefully halt the DMA. In this case the module must be halted after halting. +* More commonly used prior to an rx capture to start the DMAs before +* triggering. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9025_RxDataMoverSel_e enum values +* \param runStop set to 1 to begin transfer; 0 to halt transfer +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxDmaRunStopSet(adi_fpga9025_Device_t* device, + uint32_t rxDataMoverSelMask, + uint8_t runStop); + +/** +* \brief This function writes the length bitfield to the dma +* modules selected in the rxDatamoverSelMask. This should be done prior to performing a capture. +* The length indicates the number of bytes the DMA will run for after triggering. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9025_RxDataMoverSel_e enum values +* \param numBytes the number of bytes to transfer +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxDmaLengthSet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + uint32_t numBytes); + +/** +* \brief Unimplemented +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9025_RxDataMoverSel_e enum values +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_INV_RX_DATA_MOVER_ENABLE An invalid rx data mover trigger selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxDatamoverEnableSet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask); + +/** +* \brief This function will configure all the selected Datachains in the rxDataMoverSelMask. +* A Datachain consists of the Capture Control, Tollgate, & DMA modules. The tollgate trigger +* is configured using adi_fpga9025_RxTollgateTriggerSet, +* the DMA is reset then configured using adi_fpga9025_RxDmaSet, +* the DMA is started by setting the run-stop bit using adi_fpga9025_RxDmaRunStopSet, +* and finally the token passing is initiated in the Capture Control module. This function +* is used in rx captures and is the final step before triggering. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9025_RxDataMoverSel_e enum values +* \param triggerSelect Select from adi_fpga_TrigSources_e enum +* \param rxDmaCfg contains the dma configuration settings to apply to all selected DMA modules +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxDataChainConfigure(adi_fpga9025_Device_t* device, + uint32_t rxDataMoverSelMask, + adi_fpga9025_RxTollgateTrigSources_e triggerSelect, + adi_fpga9025_RxDmaCfg_t* rxDmaCfg); + +/** +* \brief This function clears and resets all Datachains to prepare for a new capture or as part +* of a tear down routine. The Capture Controls are reset and deactivated, the DMAs are halted +* and will return errors if halted ungracefully, and the Tollgates are held in reset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxDataChainReset(adi_fpga9025_Device_t* device); + +/** +* \brief Unimplemented +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDatamoverSelMask an or'd combination of one or more adi_fpga9025_RxDataMoverSel_e enum values +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_INV_RX_DATA_MOVER_ENABLE An invalid rx data mover trigger selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxDatamoverEnableGet(adi_fpga9025_Device_t* device, + uint32_t* rxDatamoverSelMask); + +/** +* \brief Writes a 1 to the Capture Control modules Datapath Active bitfield. A capture will then occur +* based on the Tollgate trigger selections. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxCaptureStart(adi_fpga9025_Device_t* device); + +/** +* \brief Called after adi_fpga9025_RxCaptureStart to block program execution until the capture completes +* or the timeMsDelay expires. The function waits for the Active bitfield in the Capture Control +* module to clear. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param timeMsDelay is uint32_t type which conveys the wait time in milliseconds, i.e. 200 = 200 ms +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_DATA_RX_MOVER_WAIT_TIMEOUT Timeout occurred during Rx transaction +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxCaptureWait(adi_fpga9025_Device_t* device, + uint32_t timeMsDelay); + +/** +* \brief Unimplemented +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDatamoverSel the selected datamover to read +* \param data the user provided array into which the data is placed. +* \param dataSize the size of the data array. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_DATA_RX_MOVER_WAIT_TIMEOUT Timeout occurred during Rx transaction +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxDataGet(adi_fpga9025_Device_t* device, + adi_fpga9025_RxDatamoverSel_e rxDatamoverSel, + int32_t data[], + uint32_t* dataSize); + +/** +* \brief Unimplemented +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param rxDataMoverSelMask an or'd combination of one or more adi_fpga9025_RxDataMoverSel_e enum values +* \param numSamples the number of samples to be written from part to the memory. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_DATA_RX_MOVER_WAIT_TIMEOUT Timeout occurred during Rx transaction +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_RxSamplesSet(adi_fpga9025_Device_t* device, + uint32_t rxDataMoverSelMask, + uint32_t numSamples); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_RX_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_rx_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_rx_types.h new file mode 100644 index 0000000..68ffa5e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_rx_types.h @@ -0,0 +1,90 @@ +/*! +* \file adi_fpga9025_rx_types.h +* \brief Contains FPGA9025 rx enum and struct definitions +* +* ADRV9025 API Version: 6.4.0.14 +* +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_RX_TYPES_H_ +#define _ADI_FPGA9025_RX_TYPES_H_ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define ADI_FPGA9025_NUM_OF_RX_DATAMOVERS 3 +/* 0x2AAAAA80, 2G /3, then reduced to a 64byte boundary */ +#define ADI_FPGA9025_RX_START_ADDRESS 0 +#define ADI_FPGA9025_RX_DMA_SIZE 715827840 + +/** +* \brief Enumerated list of fpga Rx Tollgata trigger sources +*/ +typedef enum adi_fpga9025_RxTollgateTrigSources +{ + ADI_FPGA9025_IMM_TRIG = 0x1, /*!Immediate trigger. */ + ADI_FPGA9025_EXT_TRIG = 0x2, /*!External Trigger external SMA. */ + ADI_FPGA9025_TDD_SM = 0x4, /*!TDD State Machine. */ + ADI_FPGA9025_ARM_ACK = 0x8, /*!GPIO. */ + ADI_FPGA9025_TX1_SOF = 0x10, /*!TX1 Start of File Flag from transmit to indicate start of transmit tone.*/ + ADI_FPGA9025_TX2_SOF = 0x20, /*!TX2 Start of File Flag from transmit to indicate start of transmit tone. */ + ADI_FPGA9025_TX3_SOF = 0x40, /*!TX3 Start of File Flag from transmit to indicate start of transmit tone. */ + ADI_FPGA9025_TX4_SOF = 0x80 /*!TX4 Start of File Flag from transmit to indicate start of transmit tone. */ +} adi_fpga9025_RxTollgateTrigSources_e; + +/** +* \brief Data structure to hold the Fpga Data mover tollgate Configuration +*/ +typedef struct adi_fpga9025_RxTollgateCfg +{ + uint32_t tollGateEdgeOrLvl; /*!1 indicates that the trigger input is edge detected. 0 indicates that the trigger input is level sensitive. */ + uint32_t tollGateHiRiseOrLoFall; /*!1 indicates either high level or rising edge. 0 indicates either low level or falling edge. */ + uint8_t tollgateReset; /*!Set to 1 resets the Tollgate. Clear to 0 allows for normal operation.. */ + adi_fpga9025_RxTollgateTrigSources_e tollGateTrigSource; /*!Selects the trigger input that is used to open the Tollgate. multiple triggers Supported */ +} adi_fpga9025_RxTollgateCfg_t; + +/** +* \brief Data structure to hold the Fpga Data mover dma Configuration +*/ +typedef struct adi_fpga9025_RxDmaCfg +{ + uint8_t enableEnhancedMode; /*!When set to 1, the enhanced mode of the selected transfer is performed. When cleared to 0, the traditional mode of the selected transfer is performed. */ + uint8_t enableSg; /*!When set to 1, the DMA performs a scatter-gather transfer. When cleared to 0, the DMA performs a simple transfer. */ + uint64_t simpleStartAddr; /*!indicates the starting address in memory where the data should be written.*/ + uint32_t length; /*!Identifies the number of bytes to transfer in the simple mode and enhanced scatter-gather mode. */ + uint8_t validDataWidthStream; /*!This field indicates what the width of valid data is on the stream interface. This field is used to pack/unpack the data from the memory.*/ + uint32_t sgFirstDescriptor; /*!Contains the location of the first descriptor used in both scatter-gather modes. */ + uint32_t sgLastDescriptor; /*!Contains the location of the last descriptor used in both scatter-gather modes. */ + uint8_t runStop; /*! When set to 1, the DMA begins the transfer. When cleared to 0, any active transfer is gracefully halted. When halted, the module needs to be reset after the halt completes.*/ + uint8_t active; /*! When this bit is 1, the DMA is actively transferring data. Read-only */ + uint8_t complete; /*! When this bit is 1, the transfer has completed successfully. This bit will clear when run_stop is cleared to '0'. Read-only */ + uint8_t haltComplete; /*! When this bit is 1, the halt that was previously issued has completed. This module must be reset after a halt completes. Read-only */ + uint8_t overflow; /*! When this bit is 1, an overflow has occurred on the FIFO. This is a sticky bit. Write a 1 to this bit to clear it. Read-only */ +} adi_fpga9025_RxDmaCfg_t; + +/** +* \brief Enumerated list of fpga rx data movers +*/ +typedef enum adi_fpga9025_RxDatamoverSel +{ + ADI_FPGA9025_RX_DATAMOVER_0 = 1, /*!Rx Datamover 0. */ + ADI_FPGA9025_RX_DATAMOVER_1 = 2, /*!Rx Datamover 1. */ + ADI_FPGA9025_RX_DATAMOVER_2 = 4, /*!Rx Datamover 2. */ + ADI_FPGA9025_RX_DATAMOVER_ALL = 7 /*!All Rx Datamovers. */ +} adi_fpga9025_RxDatamoverSel_e; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_RX_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_tdd.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_tdd.h new file mode 100644 index 0000000..226bae0 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_tdd.h @@ -0,0 +1,231 @@ +/** +* \file adi_fpga9025.h +* \brief Contains top level fpga9025 related function prototypes for +* adi_fpga9025_tdd.c +* +* FPGA9025 API Version: 6.4.0.14 +*/ +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_TDD_H_ +#define _ADI_FPGA9025_TDD_H_ + +#include "adi_fpga9025_tdd_types.h" +#include "adi_fpga9025_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \brief Initializes the FPGA TDD state machine +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param fpgaTddStateMachine is a pointer to structure type fpgaTddStateMachine_t which contains all +* TDD state machine parameters. This structure must be pre-loaded before use and is checked for a +* null pointer if not initialized and an error will be thrown. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TddInit(adi_fpga9025_Device_t* device, + adi_fpga_TddStateMachine_t* fpgaTddStateMachine); + +/** +* \brief Reads the FPGA TDD state machine from the FPGA modules and loads the values into the structure +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param fpgaTddStateMachine is a pointer to an empty structure type fpgaTddStateMachine_t. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TddInitGet(adi_fpga9025_Device_t* device, + adi_fpga_TddStateMachine_t* fpgaTddStateMachine); + +/** +* \brief Enables the TDD state machine by setting the Frame Counter module enable bit +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TddEnable(adi_fpga9025_Device_t* device); + +/** +* \brief Disables the TDD state machine by clearing the Frame Counter enable bit +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TddDisable(adi_fpga9025_Device_t* device); + +int32_t adi_fpga9025_TddDataGate(adi_fpga9025_Device_t* device); + +/** +* \brief Manually asserts the TDD enable pins indicated in the fpgaTddEnables parameter +* using the following bitmapping: +* +* fpgaTddEnables[bit] | TDD Enable signal +* ---------------------|------------------------ +* 0 | Rx1 +* 1 | Rx2 +* 2 | Rx3 +* 3 | Rx4 +* 4 | Orx1 +* 5 | Orx2 +* 6 | Orx3 +* 7 | Orx4 +* 8 | Tx1 +* 9 | Tx2 +* 10 | Tx3 +* 11 | Tx4 +* 12 | Ext1 +* 13 | Ext2 +* 14 | Ext3 +* 15 | Ext4 +* 16 | Tx1 to Orx1 +* 17 | Tx2 to Orx1 +* 18 | Tx1 to Orx2 +* 19 | Tx2 to Orx2 +* 20 | Tx3 to Orx3 +* 21 | Tx4 to Orx3 +* 22 | Tx3 to Orx4 +* 23 | Tx4 to Orx4 +* +* This is a manual control used for debug and is overridden +* anytime the TDD state machine is enabled. The function will +* NOT disable all TDD modules prior to asserting the enables, it +* is incumbent on the user to disable TDD prior to using manual +* enable assertion. The value of the bit for each TDD enable module +* is what will be written to the manual assert value. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param fpgaTddEnables is a uint32_t bit field which contains the TDD enable +* bits for assertion. +* +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* \retval ADI_FPGA9025_ACT_INV_TDD_ASSERT_SELECT Invalid bits were selected when asserting TDD pins +* +*/ +int32_t adi_fpga9025_TddEnablesAssertSet(adi_fpga9025_Device_t* device, + uint32_t fpgaTddEnables); + +/** +* \brief This function will read back the manual enable assert value that is currently written in each +* Enable Control module. Note: If TDD is not properly disabled, the manual enable value might not +* correspond with the actual pin logic state. +* +* fpgaTddEnables[bit] | TDD Enable signal +* ---------------------|------------------------ +* 0 | Rx1 +* 1 | Rx2 +* 2 | Rx3 +* 3 | Rx4 +* 4 | Orx1 +* 5 | Orx2 +* 6 | Orx3 +* 7 | Orx4 +* 8 | Tx1 +* 9 | Tx2 +* 10 | Tx3 +* 11 | Tx4 +* 12 | Ext1 +* 13 | Ext2 +* 14 | Ext3 +* 15 | Ext4 +* 16 | Tx1 to Orx1 +* 17 | Tx2 to Orx1 +* 18 | Tx1 to Orx2 +* 19 | Tx2 to Orx2 +* 20 | Tx3 to Orx3 +* 21 | Tx4 to Orx3 +* 22 | Tx3 to Orx4 +* 23 | Tx4 to Orx4 +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param fpgaTddEnables is a uint32_t bit field which will hold the TDD enable +* bits currently set in the module. +* +* \retval ADI_FPGA9025_ACT_NO_ACTION Function completed successfully, no action required +* \retval ADI_FPGA9025_ACT_INV_TDD_ASSERT_SELECT Invalid bits were selected when asserting TDD pins +* +*/ +int32_t adi_fpga9025_TddEnablesAssertGet(adi_fpga9025_Device_t* device, + uint32_t* fpgaTddEnables); + +/** +* \brief This function will setup the Orx Pin Encode module with the values passed in +* through the orxPinEncodeCfg structure. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param orxPinEncodeCfg Pointer to a filled out adi_fpga9025_OrxPinEncodeCfg_t structure +* +* \retval ADI_FPGA9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TddOrxPinCfgSet(adi_fpga9025_Device_t* device, + adi_fpga9025_OrxPinEncodeCfg_t* orxPinEncodeCfg); + +/** +* \brief This function will read the Orx Pin Encode module and write the values to the +* orxPinEncodeCfg structure passed in. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param orxPinEncodeCfg Pointer to a adi_fpga9025_OrxPinEncodeCfg_t structure to be filled with current module values +* +* \retval ADI_FPGA9025_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TddOrxPinCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_OrxPinEncodeCfg_t* orxPinEncodeCfg); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_TDD_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_tdd_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_tdd_types.h new file mode 100644 index 0000000..242df6d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_tdd_types.h @@ -0,0 +1,137 @@ +/*! +* \file adi_fpga9025_tdd_types.h +* \brief Contains FPGA9025 TDD enum and struct definitions +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_TDD_TYPES_H_ +#define _ADI_FPGA9025_TDD_TYPES_H_ + +#include +//#include "adi_fpga9025_tdd_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Enumumerated list of the Orx Pin Encode modes +*/ +typedef enum adi_fpga9025_OrxPinEncodeModes +{ + ADI_FPGA9025_ORXPINENCODE_MODE1 = 0, /* 3 pin mode (ORx_Enable and ORx_Select[1:0] pins) */ + ADI_FPGA9025_ORXPINENCODE_MODE1A = 1, /* 2 pin mode (ORx_Enable and ORx_Select pins) */ + ADI_FPGA9025_ORXPINENCODE_MODE2 = 2, /* 4 pin mode (2 ORx_Enable pins and 2 ORx Select pins) */ + ADI_FPGA9025_ORXPINENCODE_MODE3 = 3, /* 1 pin mode (ORx selection is accomplished via SPI bits) */ + ADI_FPGA9025_ORXPINENCODE_MODE4 = 4 /* 2 pin mode (ORx selection is accomplished via SPI bits) */ +} adi_fpga9025_OrxPinEncodeModes_e; + +/** +* \brief Structure to hold the FPGA TDD Timing parameters. Located in the TDD Enable +* Control FPGA module. Includes primary & secondary region parameters. +*/ +typedef struct adi_fpga_TddTiming +{ + uint32_t onPtr; /*!< On pointer (start value) for TDD primary region */ + uint32_t offPtr; /*!< Off pointer (start value) for TDD primary region */ + uint32_t secondaryOnPtr; /*!< On pointer (start value) for TDD secondary region */ + uint32_t secondaryOffPtr; /*!< Off pointer (start value) for TDD secondary region */ + uint32_t offsetFrames; /*!< Offset frame value for primary & secondary region */ + uint32_t activeFrames; /*!< Active frame value for primary & secondary region */ + uint32_t inactiveFrames; /*!< Inactive frame value for primary & secondary region */ +} adi_fpga_TddTiming_t; + +/** +* \brief Structure to hold the FPGA TDD Datapath parameters. Located in the TDD Datapath +* Control FPGA module. +*/ +typedef struct adi_fpga_TddDatapathControl +{ + uint8_t enable; /*!< Set this value to 1 to enable this datapath. Otherwise, set to 0 */ + uint32_t startValue; /*!< Start Value for Datapath Control Module. Effectively the Datapath Delay value */ +} adi_fpga_TddDatapathControl_t; + +/** +* \brief Structure to hold the FPGA TDD state machine parameters +*/ +typedef struct adi_fpga_TddStateMachine +{ + uint32_t loopCount; /*!< Set this value to > 1 to enable looping */ + uint8_t syncExtTrig; /*!< Set this value to 1 to enable external triggering. Otherwise, set to 0 */ + uint32_t frameCount; /*!< Number of Tx LaneRate /40 clock cycles in the desired frame time */ + + adi_fpga_TddTiming_t rx1EnableControl; + adi_fpga_TddTiming_t rx2EnableControl; + adi_fpga_TddTiming_t rx3EnableControl; + adi_fpga_TddTiming_t rx4EnableControl; + + adi_fpga_TddTiming_t orx1EnableControl; + adi_fpga_TddTiming_t orx2EnableControl; + adi_fpga_TddTiming_t orx3EnableControl; + adi_fpga_TddTiming_t orx4EnableControl; + + adi_fpga_TddTiming_t tx1EnableControl; + adi_fpga_TddTiming_t tx2EnableControl; + adi_fpga_TddTiming_t tx3EnableControl; + adi_fpga_TddTiming_t tx4EnableControl; + + adi_fpga_TddTiming_t tx1ToOrx1EnableControl; + adi_fpga_TddTiming_t tx2ToOrx1EnableControl; + adi_fpga_TddTiming_t tx1ToOrx2EnableControl; + adi_fpga_TddTiming_t tx2ToOrx2EnableControl; + adi_fpga_TddTiming_t tx3ToOrx3EnableControl; + adi_fpga_TddTiming_t tx4ToOrx3EnableControl; + adi_fpga_TddTiming_t tx3ToOrx4EnableControl; + adi_fpga_TddTiming_t tx4ToOrx4EnableControl; + + adi_fpga_TddTiming_t extTrig1; + adi_fpga_TddTiming_t extTrig2; + adi_fpga_TddTiming_t extTrig3; + adi_fpga_TddTiming_t extTrig4; + + adi_fpga_TddDatapathControl_t rxDatapath0; + adi_fpga_TddDatapathControl_t rxDatapath1; + adi_fpga_TddDatapathControl_t rxDatapath2; + adi_fpga_TddDatapathControl_t txDatapath0; + adi_fpga_TddDatapathControl_t txDatapath1; +} adi_fpga_TddStateMachine_t; + +typedef enum adi_fpga9025_TddGpioModule +{ + ADI_FPGA9025_ENABLE1CONTROL, + ADI_FPGA9025_ENABLE2CONTROL, + ADI_FPGA9025_ENABLE3CONTROL, + ADI_FPGA9025_ENABLE4CONTROL, + ADI_FPGA9025_SELECT1CONTROL, + ADI_FPGA9025_SELECT2CONTROL, + ADI_FPGA9025_SELECT3CONTROL, + ADI_FPGA9025_SELECT4CONTROL +} adi_fpga9025_TddModule_e; + +/** +* \brief Structure to hold the FPGA TDD Orx Pin Encode module parameters +*/ +typedef struct adi_fpga9025_OrxPinEncodeCfg +{ + adi_fpga9025_OrxPinEncodeModes_e modeSelect; /*!< Selects the ORX Pin mode encoding. */ + uint8_t fastSwitchingEnable; /*!< Enables fast switching when changing ORX Select. When set to 1, ORX Select is allowed to change with ORX Enable high. When set to 0, ORX Enable is brought low before switching the ORX Select bits. */ + uint8_t mode1aOrxSelectLow; /*!< When in Mode 1A, this bit field identifies which ORX channel is enabled when the ORX Select pin is low. The valid values are:0b00 - ORX1; 0b01 - ORX2; 0b10 - ORX3; 0b11 - ORX4; */ + uint8_t mode1aOrxSelectHigh; /*!< When in Mode 1A, this bit field identifies which ORX channel is enabled when the ORX Select pin is high. The valid values are:0b00 - ORX1; 01 - ORX2; 0b10 - ORX3; 0b11 - ORX4; */ + uint8_t mode3OrxSelect; /*!< When in Mode 3, this bit field identifies the ORX channel that is enabled. The valid values are:0b00 - ORX1; 01 - ORX2; 0b10 - ORX3; 0b11 - ORX4; */ + uint16_t orxSelectSetupTime; /*!< This bit field sets the amount of time, in TDD State Machine clock periods, that the state machine waits after setting the ORX Select pins before raising ORX Enable. If the state machine is configured to allow fast switching, this setup time is performed before ORX Enable raises. Once high, the ORX Select is switched immediately. Should be written value minus 1. */ + uint16_t orxEnableHighTime; /*!< Sets the minimum amount of time that ORX Enable is high in 10s of nanoseconds. Should be written value minus 1. */ + uint16_t orxEnableLowTime; /*!< Sets the minimum amount of time that ORX Enable is low in 10s of nanoseconds. Should be written value minus 1. */ +} adi_fpga9025_OrxPinEncodeCfg_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_TDD_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_tx.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_tx.h new file mode 100644 index 0000000..a20a635 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_tx.h @@ -0,0 +1,424 @@ +/** + * \file: adi_fpga9025_tx.h + * + * \brief Contains top level tx fpga9025 related prototypes + * + * FPGA9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_TX_H_ +#define _ADI_FPGA9025_TX_H_ + +#include "adi_fpga9025_tx_types.h" +#include "adi_fpga9025_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \brief This function writes the adi_fpga9025_TxTollgateCfg_t structure to the tollgate +* modules selected in the txDataMoverSelMask. This function could be used as part +* of a transmit setup procedure if more than just the trigger select should be +* configured. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param txDataMoverSelMask an or'd combination of one or more adi_fpga9025_TxDataMoverSel_e enum values +* \param tollGateCfg contains the transport configuration setting structure +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxTollgateSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + adi_fpga9025_TxTollgateCfg_t* tollGateCfg); + +/** +* \brief Reads the configuration for a single tollgate module and populates the empty +* adi_fpga9025_TxTollgateCfg_t structure passed in to the function. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param txDataMoverSel an adi_fpga9025_TxDataMoverSel_e enum value selecting a single datamover +* \param tollGateCfg an empty structure that will be written with the selected tollgate's configuration values +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_INV_TX_DATA_MOVER_TOLLGATE_SETUP An invalid tx datamover selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxTollgateGet(adi_fpga9025_Device_t* device, + adi_fpga9025_TxDatamoverSel_e txDataMoverSel, + adi_fpga9025_TxTollgateCfg_t* tollGateCfg); + +/** +* \brief This function writes the reset bit to the tollgate +* modules selected in the txDatamoverSelMask. The reset bit is not self-clearing +* so a full reset will require a call to this function to write a 1 then another +* call to write a 0 for normal operation. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param txDataMoverSelMask an or'd combination of one or more adi_fpga9025_TxDataMoverSel_e enum values +* \param resetVal the reset value (1 for reset; 0 for normal operation) +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_INV_TX_DATA_MOVER_TOLLGATE_SETUP An invalid tx datamover selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxTollgateResetSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + uint8_t resetVal); + +/** +* \brief This function reads the reset bit to the tollgate +* modules selected in the txDatamoverSelMask. It zeros the resetVal parameter +* and copies each module's reset value to the bit location given by the +* adi_fpga9025_TxDataMoverSel_e enum. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param txDataMoverSelMask an or'd combination of one or more adi_fpga9025_TxDataMoverSel_e enum values +* \param resetVal each corresponds to that datamover's tollgate reset bit +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_INV_TX_DATA_MOVER_TOLLGATE_SETUP An invalid tx datamover selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxTollgateResetGet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + uint8_t* resetVal); + +/** +* \brief This function writes the adi_fpga9025_TxDmaCfg_t structure to the DMA +* modules selected in the txDatamoverSelMask. This function could be used as part +* of an transmit setup procedure. The LastDescriptor bitfield and RunStop bits +* are not written during this function call. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param txDataMoverSelMask an or'd combination of one or more adi_fpga9025_TxDataMoverSel_e enum values +* \param txDmaCfg is the number of samples to transmit +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_INV_TX_DATA_MOVER_DMA_SETUP An invalid tx datamover selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxDmaSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + adi_fpga9025_TxDmaCfg_t* txDmaCfg); + +/** +* \brief Reads the configuration for a single DMA module and populates the empty +* adi_fpga9025_TxDmaCfg_t structure passed in to the function. This function reads +* Read-Write & Read-Only bitfields, including status bits. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param txDataMoverSel anadi_fpga9025_TxDataMoverSel_e enum values +* \param dmaCfg Pointer to return the adi_fpga9025_TxDmaCfg_t data structure. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_INV_TX_DATA_MOVER_DMA_SETUP An invalid tx datamover selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxDmaGet(adi_fpga9025_Device_t* device, + adi_fpga9025_TxDatamoverSel_e txDataMoverSel, + adi_fpga9025_TxDmaCfg_t* dmaCfg); + +/** +* \brief writes the tramsmit mode for one or more Tx data movers +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param txDataMoverSelMask an or'd combination of one or more adi_fpga9025_TxDataMoverSel_e enum values +* \param txmode can be one of adi_fpga9025_TxDatamoverMode_e +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_INV_TX_DATA_MOVER_SETUP An invalid tx datamover selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +/* int32_t adi_fpga9025_TxModeSetup(adi_fpga9025_Device_t *device, adi_fpga_TramsmitMode_t transmitMode); */ +int32_t adi_fpga9025_TxModeSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + adi_fpga9025_TxDatamoverMode_e txmode); + +/** +* \brief reads the tramsmit mode for all Tx data movers +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param transmitModeMask can be one of adi_fpga9025_TxDatamoverMode_e +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_FPGA9025_ACT_INV_TX_DATA_MOVER_SETUP An invalid tx datamover selected +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxModeGet(adi_fpga9025_Device_t* device, + uint8_t* transmitModeMask); + +/** +* \brief writes the trigger source for one or more Tx data movers +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param txDataMoverSelMask an or'd combination of one or more adi_fpga9025_TxDataMoverSel_e enum values +* \param triggerSelect can be a combination of adi_fpga_TrigSources_e +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* \retval ADI_FPGA9025_ACT_INV_TX_DATA_MOVER_TRIGGER An invalid trigger type selected +* +*/ +int32_t adi_fpga9025_TxTollgateTriggerSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + adi_fpga9025_TxTollgateTrigSources_e triggerSelect); + +/** +* \brief reads the trigger source for all Tx data movers +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param txDataMoverSel one of adi_fpga9025_TxDataMoverSel_e enum values +* \param triggerSelect can be a combination of adi_fpga_TrigSources_e +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* \retval ADI_FPGA9025_ACT_INV_TX_DATA_MOVER_TRIGGER An invalid trigger type selected +* +*/ +int32_t adi_fpga9025_TxTollgateTriggerGet(adi_fpga9025_Device_t* device, + adi_fpga9025_TxDatamoverSel_e txDataMoverSel, + adi_fpga9025_TxTollgateTrigSources_e* triggerSelect); + +/** +* \brief Writes a 1 to the Capture Control modules Datapath Active bitfield. A capture will then occur +* based on the Tollgate trigger selections. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxDataStart(adi_fpga9025_Device_t* device); + +/** +* \brief Stops all enabled FPGA Tx data movers +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxDataStop(adi_fpga9025_Device_t* device); + +/** +* \brief This function writes the reset bit to the dma +* modules selected in the txDatamoverSelMask. The reset bit is self-clearing +* so there is no need to clear after setting. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param txDatamoverSelMask an or'd combination of one or more adi_fpga9025_TxDataMoverSel_e enum values +* \param resetVal set to 1 to reset module +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxDmaResetSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + uint8_t reset); + +/** +* \brief This function writes the run-stop bit to the dma +* modules selected in the txDatamoverSelMask. This can be used during the middle of a transfer +* to gracefully halt the DMA. In this case the module must be halted after halting. +* More commonly used prior to a transmit to start the DMAs before +* triggering. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param txDatamoverSelMask an or'd combination of one or more adi_fpga9025_TxDataMoverSel_e enum values +* \param runStop set to 1 to begin transfer; 0 to halt transfer +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxDmaRunStopSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + uint8_t runStop); + +/** +* \brief This function writes the length bitfield to the dma +* modules selected in the txDatamoverSelMask. This should be done prior to performing a transmit. +* The length indicates the number of bytes the DMA will run for after triggering. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param txDatamoverSelMask an or'd combination of one or more adi_fpga9025_TxDataMoverSel_e enum values +* \param numBytes the number of bytes to transfer +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxDmaLengthSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + uint32_t numBytes); + +/** +* \brief This function will configure all the selected Datachains in the txDataMoverSelMask. +* A Datachain consists of the Capture Control, Tollgate, & DMA modules. The tollgate trigger +* is configured using adi_fpga9025_TxTollgateTriggerSet, +* the DMA is reset then configured using adi_fpga9025_TxDmaSet, +* the DMA is started by setting the run-stop bit using adi_fpga9025_TxDmaRunStopSet, +* and finally the token passing is initiated in the Capture Control module. This function +* is used in transmit sequences and is the final step before triggering. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param txDatamoverSelMask an or'd combination of one or more adi_fpga9025_TxDataMoverSel_e enum values +* \param triggerSelect Select from adi_fpga9025_TxTollgateTrigSources_e enum +* \param txDmaCfg contains the dma configuration settings to apply to all selected DMA modules +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxDataChainConfigure(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + adi_fpga9025_TxTollgateTrigSources_e triggerSelect, + adi_fpga9025_TxDmaCfg_t* txDmaCfg); + +/** +* \brief This function clears and resets all Datachains to prepare for a new transmit or as part +* of a tear down routine. The Capture Controls are reset and deactivated, the DMAs are halted +* and will return errors if halted ungracefully, and the Tollgates are held in reset. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxDataChainReset(adi_fpga9025_Device_t* device); + +/** +* \brief This function writes the static members of the adi_fpga9025_TxDmaCfg_t structure to the DMA +* modules selected in the txDatamoverSelMask. This function is used when the fpga +* boots up. The DMAs are not ready for transmit after this function. +* The LastDescriptor, RunStop, and Length bitfields are not written +* during this function call. +* +* \dep_begin +* \dep{device} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param txDatamoverSelMask an or'd combination of one or more adi_fpga9025_TxDataMoverSel_e enum values +* \param txDmaCfg contains the dma configuration settings to apply to all selected DMA modules +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_TxDmaInit(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + adi_fpga9025_TxDmaCfg_t* txDmaCfg); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_TX_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_tx_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_tx_types.h new file mode 100644 index 0000000..14d4682 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_tx_types.h @@ -0,0 +1,90 @@ +/*! +* \file adi_adrv9025_tx_types.h +* \brief Contains FPGA9025 tx enum and struct definitions +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_TX_TYPES_H_ +#define _ADI_FPGA9025_TX_TYPES_H_ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define ADI_FPGA9025_NUM_OF_TX_DATAMOVERS 2 +#define ADI_FPGA9025_TX_START_ADDRESS 0x100000000 +#define ADI_FPGA9025_TX_DMA_SIZE 0x40000000 + +typedef enum adi_fpga9025_TxDatamoverMode +{ + ADI_FPGA9025_TXMODE_SNGL = 0, + ADI_FPGA9025_TXMODE_CONT = 1 +} adi_fpga9025_TxDatamoverMode_e; + +/** +* \brief Enumerated list of fpga Tx Tollgata trigger sources +*/ +typedef enum adi_fpga9025_TxTollgateTrigSources +{ + ADI_FPGA9025_TX_IMM_TRIG = 0x1, /*!Immediate trigger. */ + ADI_FPGA9025_TX_EXT_TRIG = 0x2, /*!External Trigger external SMA. */ + ADI_FPGA9025_TX_TDD_SM = 0x4, /*!TDD State Machine. */ + ADI_FPGA9025_TX_ARM_ACK = 0x8 /*!GPIO. */ +} adi_fpga9025_TxTollgateTrigSources_e; + +/** +* \brief Data structure to hold the Fpga Data mover tollgate Configuration +*/ +typedef struct adi_fpga9025_TxTollgateCfg +{ + uint32_t tollGateEdgeOrLvl; /*!1 indicates that the trigger input is edge detected. 0 indicates that the trigger input is level sensitive. */ + uint32_t tollGateHiRiseOrLoFall; /*!1 indicates either high level or rising edge. 0 indicates either low level or falling edge. */ + uint8_t tollgateReset; /*!Set to 1 resets the Tollgate. Clear to 0 allows for normal operation.. */ + adi_fpga9025_TxTollgateTrigSources_e tollGateTrigSource; /*!Selects the trigger input that is used to open the Tollgate. multiple triggers Supported */ +} adi_fpga9025_TxTollgateCfg_t; + +/** +* \brief Data structure to hold the Fpga Data mover dma Configuration +*/ +typedef struct adi_fpga9025_TxDmaCfg +{ + uint8_t enableEnhancedMode; /*!When set to 1, the enhanced mode of the selected transfer is performed. When cleared to 0, the traditional mode of the selected transfer is performed. */ + uint8_t enableSg; /*!When set to 1, the DMA performs a scatter-gather transfer. When cleared to 0, the DMA performs a simple transfer. */ + uint64_t simpleStartAddr; /*!indicates the starting address in memory where the data should be written.*/ + uint32_t length; /*!Identifies the number of bytes to transfer in the simple mode and enhanced scatter-gather mode. */ + uint8_t validDataWidthStream; /*!This field indicates what the width of valid data is on the stream interface. This field is used to pack/unpack the data from the memory.*/ + uint32_t sgFirstDescriptor; /*!Contains the location of the first descriptor used in both scatter-gather modes. */ + uint32_t sgLastDescriptor; /*!Contains the location of the last descriptor used in both scatter-gather modes. */ + uint8_t runStop; /*! When set to 1, the DMA begins the transfer. When cleared to 0, any active transfer is gracefully halted. When halted, the module needs to be reset after the halt completes.*/ + uint8_t continuous; /*! When set to 1, the DMA will restart the transfer. When cleared to 0, the DMA performs one transfer and stops.*/ + uint8_t active; /*! When this bit is 1, the DMA is actively transferring data. Read-only */ + uint8_t complete; /*! When this bit is 1, the transfer has completed successfully. This bit will clear when run_stop is cleared to '0'. Read-only */ + uint8_t haltComplete; /*! When this bit is 1, the halt that was previously issued has completed. This module must be reset after a halt completes. Read-only */ + uint8_t underflow; /*! When this bit is 1, an overflow has occurred on the FIFO. This is a sticky bit. Write a 1 to this bit to clear it. Read-only */ +} adi_fpga9025_TxDmaCfg_t; + +/** +* \brief Enumerated list of fpga tx data movers +*/ +typedef enum adi_fpga9025_TxDatamoverSel +{ + ADI_FPGA9025_TX_DATAMOVER_0 = 1, /*!Tx Datamover 0. */ + ADI_FPGA9025_TX_DATAMOVER_1 = 2, /*!Tx Datamover 1. */ + ADI_FPGA9025_TX_DATAMOVER_ALL = 3 /*!All Rx Datamovers. */ +} adi_fpga9025_TxDatamoverSel_e; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_TX_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_types.h new file mode 100644 index 0000000..fcc9963 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_types.h @@ -0,0 +1,182 @@ +/*! +* \file adi_fpga9025_types.h +* \brief Contains ADRV9025 API configuration and run-time type definitions +* +* ADRV9025 API Version: 6.4.0.14 +* +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_TYPES_H_ +#define _ADI_FPGA9025_TYPES_H_ + +#include +#include "adi_common.h" +#include "adi_fpga9025_tx_types.h" +#include "adi_fpga9025_rx_types.h" +#include "adi_fpga9025_jesd_types.h" +#include "adi_fpga9025_clk_types.h" +#include "adi_fpga9025_gpio_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define ADI_FPGA9025_MIN_VERSION 0x000000 +#define ADI_FPGA9025_JESD204B_DEVICEID 0xD9 +#define ADI_FPGA9025_JESD204C_DEVICEID 0xDA +#define ADI_FPGA9025_JESD204H_DEVICEID 1 +#define ADI_FPGA9025_RAM_ADDRESS_BOUNDARY 32 +#define ADI_FPGA9025_DRP_TIMEOUT_MS 200 + +typedef enum adi_fpga9025_PinDir +{ + ADI_FPGA9025_PIN_DIR_IN = 0, + ADI_FPGA9025_PIN_DIR_OUT = 1 +} adi_fpga9025_PinDir_e; + +typedef struct adi_fpga9025_LinkSetting +{ + uint32_t IqRate_kHz; + uint8_t M; + uint8_t L; + uint8_t K; + uint8_t Scrambling; + uint8_t S; + uint8_t Np; + uint8_t LinkToUse; + uint8_t jesd204C_en; + uint8_t realIf; /* ignore in tx link*/ +} adi_fpga9025_LinkSetting_t; + +/** +* \brief Data structure to hold digital clock settings +*/ +typedef struct adi_fpga9025_ClockSettings +{ + adi_fpga9025_MmcmCfg_t coreMmcm; + adi_fpga9025_QpllCfg_t qpll; +} adi_fpga9025_ClockSettings_t; + +typedef struct adi_fpga9025_SysRefClkCfg +{ + uint32_t internalSysRefGeneratorFrequency; /*!< The number of device clock cycles to generate internal SYSREF pulse */ + uint8_t internalSysrefEnable; /*!< Set this to 1 to enable internal SYSREF */ + uint8_t externalSysrefSampleEdge; /*!< Set this to 1 to sample external SYSREF on rising edge; 0 for falling edge */ + uint8_t externalSysrefPolarity; /*!< Set to 1 to invert external SYSREF polarity */ +} adi_fpga9025_SysRefClkCfg_t; + +/** +* \brief Data structure to hold the Fpga Data mover transport Configuration +*/ +typedef struct adi_fpga9025_TransportCfg +{ + uint16_t linkCfgF; /*!clkFreq_kHz} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param refClk_kHz The input clock rate in kHz +* \param mmcmConfig Pointer to the adi_fpga9025_MmcmCfg_t data structure +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_CalculateMmcmSettings(adi_fpga9025_Device_t* device, + const uint32_t refClk_kHz, + adi_fpga9025_MmcmCfg_t* mmcmConfig); + +/** +* \brief Platform FPGA command calculate the Mmcm settings +* +* Fills the given init structure with values whyich should cover the majority of use cases. +* The values are based on a few essential values given by the fpgaCfg structure +* +* \dep_begin +* \dep{device} +* \dep{mmcmConfig->clkFreq_kHz} +* \dep_end +* +* \param device Pointer to the FPGA9025 device data structure. +* \param fpgaCfg contains the essential values in order to configure the fpga +* \param fpgaInit the resulting structure which can be modified if required or +* passed to adi_fpga9025_Initialize to initialise the part +* +* \retval ADI_FPGA9025_ACT_RESET_LOG Recovery action for log reset +* \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check +* \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required +* +*/ +int32_t adi_fpga9025_InitConfig(adi_fpga9025_Device_t* device, + adi_fpga9025_SetupFpgaCfg_t* fpgaCfg, + adi_fpga9025_Init_t* fpgaInit); + +int32_t adi_fpga9025_FpgaConfigurationPrint(adi_fpga9025_Device_t* device); + +int32_t adi_fpga9025_FpgaDatapathCfgPrint(adi_fpga9025_Device_t* device); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_UTILITIES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_utilities_types.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_utilities_types.h new file mode 100644 index 0000000..917be10 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/include/adi_fpga9025_utilities_types.h @@ -0,0 +1,63 @@ +/*! +* \file adi_adrv9025_utilities_types.h +* \brief Contains FPGA9025 utilities enum and struct definitions +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA9025_UTILITIES_TYPES_H_ +#define _ADI_FPGA9025_UTILITIES_TYPES_H_ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef struct adi_fpga9025_DesLaneXbar +{ + uint8_t lane0FramerOutSel; /*!< Framer output to route to Physical Lane 0 (valid 0-7) */ + uint8_t lane1FramerOutSel; /*!< Framer output to route to Physical Lane 1 (valid 0-7) */ + uint8_t lane2FramerOutSel; /*!< Framer output to route to Physical Lane 2 (valid 0-7) */ + uint8_t lane3FramerOutSel; /*!< Framer output to route to Physical Lane 3 (valid 0-7) */ +} adi_fpga9025_DesLaneXbar_t; + +typedef struct adi_fpga9025_DataLinkCfg +{ + uint32_t iqRate_kHz; + uint8_t jesd204M; + uint8_t lanesEnabled; + uint16_t jesd204K; + uint8_t scramble; + uint8_t jesd204S; + uint8_t jesd204Np; + uint8_t jesd204E; + uint16_t datamoversUsed; + uint8_t deviceId; + adi_fpga9025_DesLaneXbar_t serializerLaneCrossbar; /*!< Lane crossbar to map framer lane outputs to physical lanes */ +} adi_fpga9025_DataLinkCfg_t; + +typedef struct adi_fpga9025_SetupFpgaCfg +{ + uint32_t deviceClk_kHz; + adi_fpga9025_DataLinkCfg_t deframerlink0; // Rx + adi_fpga9025_DataLinkCfg_t deframerlink1; // ORx + adi_fpga9025_DataLinkCfg_t deframerlink2; // Not in FPGA at the moment + + adi_fpga9025_DataLinkCfg_t framerlink0; // Tx + adi_fpga9025_DataLinkCfg_t framerlink1; // Not in FPGA at the moment + uint8_t realIf; +} adi_fpga9025_SetupFpgaCfg_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_UTILITIES_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025.c new file mode 100644 index 0000000..7d6ff42 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025.c @@ -0,0 +1,1509 @@ +/*! +* \file adi_fpga9025.c +* \brief Contains FPGA9025 API configuration and run-time type definitions +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + * + */ + +#include "adi_fpga9025_user.h" +#include "adi_fpga9025.h" +#include "adi_fpga9025_error.h" + +#include "adi_fpga9025_jesd.h" +#include "adi_fpga9025_rx.h" +#include "adi_fpga9025_tx.h" +#include "adi_fpga9025_clk.h" +#include "adi_fpga9025_utilities.h" +#include "adi_fpga9025_hal.h" +#include "adi_fpga9025_tdd.h" +#include "../../private/include/fpga9025_bf_ads9v2.h" +#include "../../private/include/fpga9025_bf_axi_adrv9025.h" +#include "../../private/include/fpga9025_bf_dp_capture_control.h" +#include "../../private/include/fpga9025_bf_jesd204_rx_lane_xbar.h" +#include "../../private/include/fpga9025_bf_jesd204_tx_lane_xbar.h" +#include "../../private/include/fpga9025_bf_xilinx_jesd204b.h" +#include "../../private/include/fpga9025_bf_xilinx_jesd204b.h" +#include "../../private/include/fpga9025_bf_jesd204_phy_ads9.h" + +//kluge +#include "adi_platform.h" + +int32_t adi_fpga9025_HwOpen(adi_fpga9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + adi_common_LogLevelSet(&device->common, + ADI_FPGA9025_LOGGING); + if (device->common.error.errCode != ADI_COMMON_HAL_OK) + { + switch (device->common.error.errCode) + { + case ADI_COMMON_HAL_LOGGING_FAIL: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + device->common.error.errCode, + ADI_COMMON_ACT_WARN_RESET_LOG, + NULL, + "Logging error"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_COMMON_HAL_LOGGGING_LEVEL_FAIL: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + device->common.error.errCode, + ADI_COMMON_ACT_WARN_RESET_LOG, + NULL, + "Logging Level error"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_COMMON_HAL_GEN_SW: /* fall through */ + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Param error"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + } + + recoveryAction = adi_common_hal_HwOpen(&device->common); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Param error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9025_HwClose(adi_fpga9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + + //LOG_FUNCTION_ENTRY_REPORT(ADI_COMMON_LOG_API); + + recoveryAction = adi_common_hal_HwClose(&device->common); + if (recoveryAction != ADI_COMMON_ACT_NO_ACTION) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + device->common.error.errCode, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Param error"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return (device->common.error.newAction); +} + +int32_t adi_fpga9025_VersionRead(adi_fpga9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + recoveryAction = fpga9025_AxiAdrv9025DesignIdBfGet(device, + FPGA9025_BF_AXI_ADRV9025, + &device->devStateInfo.designId); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_AxiAdrv9025VersionMajorBfGet(device, + FPGA9025_BF_AXI_ADRV9025, + &device->devStateInfo.versionMajor); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_AxiAdrv9025VersionMinorBfGet(device, + FPGA9025_BF_AXI_ADRV9025, + &device->devStateInfo.versionMinor); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_RefClockFreqRead(adi_fpga9025_Device_t* device, + uint32_t* detectedRefClock_kHz) +{ + UNUSED_PARA(detectedRefClock_kHz); + //TODO: implement this + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} + +int32_t adi_fpga9025_RegisterReset(adi_fpga9025_Device_t* device) +{ + //TODO: implement this + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} + +int32_t adi_fpga9025_IpReset(adi_fpga9025_Device_t* device, + uint32_t IpToResetMask) +{ + UNUSED_PARA(IpToResetMask); + //TODO: implement this + //normally use a int32_t as a mask for this but there are likely to be too many for a uint64_t so use struct + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} + +int32_t adi_fpga9025_DrpRead(adi_fpga9025_Device_t* device, + adi_fpga9025_DrpAddress_e addr, + uint8_t drp, + uint16_t* rdWord, + adi_fpga9025_DrpMask_e rdMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t i = 0; + uint8_t drpReady = 0; + uint8_t drpError = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + switch (drp) + { + case ADI_FPGA9025_PHY_CH0: + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + case ADI_FPGA9025_PHY_CH1: + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + case ADI_FPGA9025_PHY_CH2: + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + case ADI_FPGA9025_PHY_CH3: + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + case ADI_FPGA9025_PHY_CH4: + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + case ADI_FPGA9025_PHY_CH5: + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + case ADI_FPGA9025_PHY_CH6: + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + case ADI_FPGA9025_PHY_CH7: + return ADI_COMMON_ACT_ERR_CHECK_PARAM; + + case ADI_FPGA9025_PHY_QUAD0: + + /*Write address, clear write_enable bit then set enable bit*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad0DrpAddressBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint16_t)addr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + addr, + "Invalid DRP addr"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204PhyAds9Quad0DrpWriteEnableBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error writing to DRP write enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204PhyAds9Quad0DrpEnableBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error enabling DRP transaction"); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_FPGA9025_DRP_TIMEOUT_MS; i++) + { + /* kluge to get drp read functionality working. after fpga has been updated to prevent the entire drp_read_data + * register from clearing when reading just the drp_ready bit remove this code and uncomment out the bf function below + */ + uint32_t debugData = 0; + adi_hal_BbicRegisterRead(device->common.devHalInfo, + 0x4340094c, + &debugData); + + drpReady = (debugData >> 16) & 0x1; + *rdWord = debugData & 0xFFFF; + //fpga9025_Jesd204PhyAds9Quad0DrpReadyBfGet(device, FPGA9025_BF_ADS9_JESD_PHY, &drpReady); + //ADI_ERROR_RETURN(device->common.error.newAction); + + if (drpReady) + { + break; + } + else + { + //todo: platform wait 1ms + } + } + + recoveryAction = fpga9025_Jesd204PhyAds9Quad0DrpErrorBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &drpError); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading DRP error bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((drpReady == 0) || (drpError == 1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_DRP_ERROR, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Quad DRP error: requires full reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* kluged- see comment above */ + //fpga9025_Jesd204PhyAds9Quad0DrpReadDataBfGet(device, FPGA9025_BF_ADS9_JESD_PHY, rdWord); + //ADI_ERROR_RETURN(device->common.error.newAction); + *rdWord = *rdWord & (uint16_t)rdMask; + } + + break; + + case ADI_FPGA9025_PHY_QUAD1: + + /*Write address, clear write_enable bit then set enable bit*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad1DrpAddressBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint16_t)addr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + addr, + "Invalid DRP addr"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204PhyAds9Quad1DrpWriteEnableBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error writing to DRP write enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204PhyAds9Quad1DrpEnableBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error enabling DRP transaction"); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_FPGA9025_DRP_TIMEOUT_MS; i++) + { + /* kluge to get drp read functionality working. after fpga has been updated to prevent the entire drp_read_data + * register from clearing when reading just the drp_ready bit remove this code and uncomment out the bf function below + */ + uint32_t debugData = 0; + adi_hal_BbicRegisterRead(device->common.devHalInfo, + 0x43400a4c, + &debugData); + drpReady = (debugData >> 16) & 0x1; + *rdWord = debugData & 0xFFFF; + //fpga9025_Jesd204PhyAds9Quad1DrpReadyBfGet(device, FPGA9025_BF_ADS9_JESD_PHY, &drpReady); + //ADI_ERROR_RETURN(device->common.error.newAction); + + if (drpReady) + { + break; + } + else + { + //todo: platform wait 1ms + } + } + + recoveryAction = fpga9025_Jesd204PhyAds9Quad1DrpErrorBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &drpError); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading DRP error bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if ((drpReady == 0) || (drpError == 1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_DRP_ERROR, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Quad DRP error: requires full reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* kluged- see comment above */ + //fpga9025_Jesd204PhyAds9Quad1DrpReadDataBfGet(device, FPGA9025_BF_ADS9_JESD_PHY, rdWord); + //ADI_ERROR_RETURN(device->common.error.newAction); + *rdWord = *rdWord & (uint16_t)rdMask; + } + + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Invalid DRP selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + return recoveryAction; +} + +int32_t adi_fpga9025_DrpWrite(adi_fpga9025_Device_t* device, + uint32_t addr, + uint8_t drp, + uint16_t wrWord, + uint16_t wrMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t i = 0; + uint8_t drpReady = 0; + uint8_t drpError = 0; + + typedef struct + { + int32_t (*DrpWriteDataBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t ); + + int32_t (*DrpWriteDataMaskBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t ); + + int32_t (*DrpAddressBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint16_t ); + + int32_t (*DrpWriteEnableBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*DrpEnableBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*DrpReadyBfGet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + + int32_t (*DrpErrorBfGet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + } fpgaDrpWriteBf_t; + + fpgaDrpWriteBf_t fpgaDrpWriteFct[] = { + { + .DrpWriteDataBfSet = fpga9025_Jesd204PhyAds9Channel0DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9025_Jesd204PhyAds9Channel0DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9025_Jesd204PhyAds9Channel0DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9025_Jesd204PhyAds9Channel0DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9025_Jesd204PhyAds9Channel0DrpEnableBfSet, + .DrpReadyBfGet = fpga9025_Jesd204PhyAds9Channel0DrpReadyBfGet, + .DrpErrorBfGet = fpga9025_Jesd204PhyAds9Channel0DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9025_Jesd204PhyAds9Channel1DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9025_Jesd204PhyAds9Channel1DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9025_Jesd204PhyAds9Channel1DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9025_Jesd204PhyAds9Channel1DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9025_Jesd204PhyAds9Channel1DrpEnableBfSet, + .DrpReadyBfGet = fpga9025_Jesd204PhyAds9Channel1DrpReadyBfGet, + .DrpErrorBfGet = fpga9025_Jesd204PhyAds9Channel1DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9025_Jesd204PhyAds9Channel2DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9025_Jesd204PhyAds9Channel2DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9025_Jesd204PhyAds9Channel2DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9025_Jesd204PhyAds9Channel2DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9025_Jesd204PhyAds9Channel2DrpEnableBfSet, + .DrpReadyBfGet = fpga9025_Jesd204PhyAds9Channel2DrpReadyBfGet, + .DrpErrorBfGet = fpga9025_Jesd204PhyAds9Channel2DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9025_Jesd204PhyAds9Channel3DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9025_Jesd204PhyAds9Channel3DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9025_Jesd204PhyAds9Channel3DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9025_Jesd204PhyAds9Channel3DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9025_Jesd204PhyAds9Channel3DrpEnableBfSet, + .DrpReadyBfGet = fpga9025_Jesd204PhyAds9Channel3DrpReadyBfGet, + .DrpErrorBfGet = fpga9025_Jesd204PhyAds9Channel3DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9025_Jesd204PhyAds9Channel4DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9025_Jesd204PhyAds9Channel4DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9025_Jesd204PhyAds9Channel4DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9025_Jesd204PhyAds9Channel4DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9025_Jesd204PhyAds9Channel4DrpEnableBfSet, + .DrpReadyBfGet = fpga9025_Jesd204PhyAds9Channel4DrpReadyBfGet, + .DrpErrorBfGet = fpga9025_Jesd204PhyAds9Channel4DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9025_Jesd204PhyAds9Channel5DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9025_Jesd204PhyAds9Channel5DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9025_Jesd204PhyAds9Channel5DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9025_Jesd204PhyAds9Channel5DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9025_Jesd204PhyAds9Channel5DrpEnableBfSet, + .DrpReadyBfGet = fpga9025_Jesd204PhyAds9Channel5DrpReadyBfGet, + .DrpErrorBfGet = fpga9025_Jesd204PhyAds9Channel5DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9025_Jesd204PhyAds9Channel6DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9025_Jesd204PhyAds9Channel6DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9025_Jesd204PhyAds9Channel6DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9025_Jesd204PhyAds9Channel6DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9025_Jesd204PhyAds9Channel6DrpEnableBfSet, + .DrpReadyBfGet = fpga9025_Jesd204PhyAds9Channel6DrpReadyBfGet, + .DrpErrorBfGet = fpga9025_Jesd204PhyAds9Channel6DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9025_Jesd204PhyAds9Channel7DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9025_Jesd204PhyAds9Channel7DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9025_Jesd204PhyAds9Channel7DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9025_Jesd204PhyAds9Channel7DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9025_Jesd204PhyAds9Channel7DrpEnableBfSet, + .DrpReadyBfGet = fpga9025_Jesd204PhyAds9Channel7DrpReadyBfGet, + .DrpErrorBfGet = fpga9025_Jesd204PhyAds9Channel7DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9025_Jesd204PhyAds9Quad0DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9025_Jesd204PhyAds9Quad0DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9025_Jesd204PhyAds9Quad0DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9025_Jesd204PhyAds9Quad0DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9025_Jesd204PhyAds9Quad0DrpEnableBfSet, + .DrpReadyBfGet = fpga9025_Jesd204PhyAds9Quad0DrpReadyBfGet, + .DrpErrorBfGet = fpga9025_Jesd204PhyAds9Quad0DrpErrorBfGet + }, + { + .DrpWriteDataBfSet = fpga9025_Jesd204PhyAds9Quad1DrpWriteDataBfSet, + .DrpWriteDataMaskBfSet = fpga9025_Jesd204PhyAds9Quad1DrpWriteDataMaskBfSet, + .DrpAddressBfSet = fpga9025_Jesd204PhyAds9Quad1DrpAddressBfSet, + .DrpWriteEnableBfSet = fpga9025_Jesd204PhyAds9Quad1DrpWriteEnableBfSet, + .DrpEnableBfSet = fpga9025_Jesd204PhyAds9Quad1DrpEnableBfSet, + .DrpReadyBfGet = fpga9025_Jesd204PhyAds9Quad1DrpReadyBfGet, + .DrpErrorBfGet = fpga9025_Jesd204PhyAds9Quad1DrpErrorBfGet + } + }; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (drp > ADI_FPGA9025_PHY_QUAD1) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Invalid DRP selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Write data bitfields */ + if (fpgaDrpWriteFct[drp].DrpWriteDataBfSet != NULL) + { + recoveryAction = fpgaDrpWriteFct[drp].DrpWriteDataBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + wrWord); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + wrWord, + "Invalid DRP data word"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Write mask bitfields */ + if (fpgaDrpWriteFct[drp].DrpWriteDataMaskBfSet != NULL) + { + recoveryAction = fpgaDrpWriteFct[drp].DrpWriteDataMaskBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint16_t)wrMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + wrMask, + "Invalid DRP data mask"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Write address */ + if (fpgaDrpWriteFct[drp].DrpAddressBfSet != NULL) + { + recoveryAction = fpgaDrpWriteFct[drp].DrpAddressBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint16_t)addr); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + addr, + "Invalid DRP addr"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Write enable bit */ + if (fpgaDrpWriteFct[drp].DrpWriteEnableBfSet != NULL) + { + recoveryAction = fpgaDrpWriteFct[drp].DrpWriteEnableBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error writing to DRP write enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Set enable bit */ + if (fpgaDrpWriteFct[drp].DrpEnableBfSet != NULL) + { + recoveryAction = fpgaDrpWriteFct[drp].DrpEnableBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error enabling DRP transaction"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Looping and wait for channel ready */ + drpReady = 0; + for (i = 0; i < ADI_FPGA9025_DRP_TIMEOUT_MS; i++) + { + if (fpgaDrpWriteFct[drp].DrpReadyBfGet != NULL) + { + recoveryAction = fpgaDrpWriteFct[drp].DrpReadyBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &drpReady); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading DRP ready bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (drpReady) + { + break; + } + else + { + adi_common_hal_Wait_ms(&device->common, + 1); + } + } + + drpError = 0; + if (fpgaDrpWriteFct[drp].DrpErrorBfGet != NULL) + { + recoveryAction = fpgaDrpWriteFct[drp].DrpErrorBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &drpError); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading DRP error bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* If not ready or error occurred then report error. */ + if ((drpReady == 0) || (drpError == 1)) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_DRP_ERROR, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Quad DRP error: requires full reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_InitSet(adi_fpga9025_Device_t* device, + adi_fpga9025_Init_t* initSettings) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t i = 0; + uint8_t helperMask8bit = 0; + uint8_t deserializerChannelMask = 0; + uint8_t serializerChannelMask = 0; + uint8_t lockBit = 0; + uint8_t resetDone = 0; + uint32_t deframer0LaneXbarReset = 0; + uint32_t deframer1LaneXbarReset = 0; + uint32_t deframer2LaneXbarReset = 0; + uint32_t framer0LaneXbarReset = 0; + uint32_t framer1LaneXbarReset = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + initSettings); + + /* reset lane xbars. Do this first to prevent any deframer settings from affecting the PHY */ + recoveryAction = fpga9025_Jesd204RxLaneXbarLaneResetBfSet(device, + FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0, + 0xFFFFFFFF); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Rx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_Jesd204RxLaneXbarLaneResetBfSet(device, + FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1, + 0xFFFFFFFF); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Rx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_Jesd204RxLaneXbarLaneResetBfSet(device, + FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2, + 0xFFFFFFFF); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Rx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_Jesd204TxLaneXbarLaneResetBfSet(device, + FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0, + 0xFFFFFFFF); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Tx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_Jesd204TxLaneXbarLaneResetBfSet(device, + FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1, + 0xFFFFFFFF); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Tx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*************************************************************************************************************************************** + * Physical layer + ***************************************************************************************************************************************/ + /* Place all PHY channels in reset */ + recoveryAction = adi_fpga9025_DeserializerResetSet(device, + 0xFF, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adi_fpga9025_SerializerResetSet(device, + 0xFF, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* qpll setup */ + recoveryAction = adi_fpga9025_QpllSet(device, + initSettings->clocks.qpll.quadSelect, + &initSettings->clocks.qpll); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* serializer/deserializer channel setup */ + for (i = 0; i < ADI_FPGA9025_NUM_LANES; i++) + { + helperMask8bit = (0x01 << i); + if (initSettings->datapath.serializerCfg[i].powerDown == 0) + { + recoveryAction = adi_fpga9025_SerializerCfgSet(device, + helperMask8bit, + &initSettings->datapath.serializerCfg[i]); + ADI_ERROR_RETURN(device->common.error.newAction); + serializerChannelMask |= (0x01 << i); + } + if (initSettings->datapath.deserializerCfg[i].powerDown == 0) + { + recoveryAction = adi_fpga9025_DeserializerCfgSet(device, + helperMask8bit, + &initSettings->datapath.deserializerCfg[i]); + ADI_ERROR_RETURN(device->common.error.newAction); + deserializerChannelMask |= (0x01 << i); + } + } + + /* release the desired channels from reset based on the power down bits */ + recoveryAction = adi_fpga9025_DeserializerResetSet(device, + deserializerChannelMask, + 0); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = adi_fpga9025_SerializerResetSet(device, + serializerChannelMask, + 0); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* check for qpll locks */ + if ((initSettings->clocks.qpll.quadSelect & ADI_FPGA9025_QPLL_QUAD0) > 0) + { + lockBit = 0; + for (i = 0; i < 5; i++) + { + recoveryAction = adi_fpga9025_QpllLockGet(device, + ADI_FPGA9025_QPLL_QUAD0, + initSettings->clocks.qpll.band, + &lockBit); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading qpll quad 0 lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (lockBit == 1) + { + break; + } + else + { + recoveryAction = adi_common_hal_Wait_ms(&device->common, + 10); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if (lockBit != 1) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_CLOCK_FAILURE, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + ADI_FPGA9025_QPLLCLK0, + "Error Qpll0 not locked"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + if ((initSettings->clocks.qpll.quadSelect & ADI_FPGA9025_QPLL_QUAD1) > 0) + { + lockBit = 0; + for (i = 0; i < 5; i++) + { + recoveryAction = adi_fpga9025_QpllLockGet(device, + ADI_FPGA9025_QPLL_QUAD1, + initSettings->clocks.qpll.band, + &lockBit); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading qpll quad 1 lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (lockBit == 1) + { + break; + } + else + { + recoveryAction = adi_common_hal_Wait_ms(&device->common, + 10); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if (lockBit != 1) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_CLOCK_FAILURE, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + ADI_FPGA9025_QPLLCLK1, + "Error Qpll1 not locked"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* check PHY layer has finished reset routine */ + resetDone = 0; + for (i = 0; i < 5; i++) + { + recoveryAction = adi_fpga9025_DeserializerResetDoneGet(device, + &resetDone); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading deserializer channel reset done bits"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resetDone == deserializerChannelMask) + { + break; + } + else + { + recoveryAction = adi_common_hal_Wait_ms(&device->common, + 10); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if (resetDone != deserializerChannelMask) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_PHY_RESET_FAIL, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "Deserializer channels have not reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + resetDone = 0; + for (i = 0; i < 5; i++) + { + recoveryAction = adi_fpga9025_SerializerResetDoneGet(device, + &resetDone); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading serializer channel reset done bits"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (resetDone == serializerChannelMask) + { + break; + } + else + { + recoveryAction = adi_common_hal_Wait_ms(&device->common, + 10); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if (resetDone != serializerChannelMask) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_PHY_RESET_FAIL, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + NULL, + "Serializer channels have not reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*************************************************************************************************************************************** + * MMCM + ***************************************************************************************************************************************/ + /* Disable TDD FSM before calling MmcmSet */ + recoveryAction = adi_fpga9025_TddDisable(device); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* RX must be setup prior to TX since the final output of RX feeds TX mmcm*/ + recoveryAction = adi_fpga9025_MmcmSet(device, + ADI_FPGA9025_CORE_MMCM, + &initSettings->clocks.coreMmcm); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + lockBit = 0; + for (i = 0; i < 5; i++) + { + recoveryAction = adi_fpga9025_MmcmLockGet(device, + ADI_FPGA9025_CORE_MMCM, + &lockBit); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading mmcm lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (lockBit == 1) + { + break; + } + else + { + recoveryAction = adi_common_hal_Wait_ms(&device->common, + 10); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + device->common.error.newAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + if (lockBit != 1) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_CLOCK_FAILURE, + ADI_COMMON_ACT_ERR_RESET_INTERFACE, + ADI_FPGA9025_CORE_MMCM, + "Error Core MMCM not locked"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*************************************************************************************************************************************** + * Lane Xbars + ***************************************************************************************************************************************/ + /* reset lane xbars */ + recoveryAction = fpga9025_Jesd204RxLaneXbarLaneResetBfSet(device, + FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0, + 0xFFFFFFFF); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Rx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_Jesd204RxLaneXbarLaneResetBfSet(device, + FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1, + 0xFFFFFFFF); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Rx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_Jesd204RxLaneXbarLaneResetBfSet(device, + FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2, + 0xFFFFFFFF); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Rx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_Jesd204TxLaneXbarLaneResetBfSet(device, + FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0, + 0xFFFFFFFF); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Tx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_Jesd204TxLaneXbarLaneResetBfSet(device, + FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1, + 0xFFFFFFFF); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Tx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* build up the link layer's lane xbar resets based on which phy lanes they're using */ + /* can't use dserializerChannelMask here because we need to reset based on which channels go to which + * link layer. the dserializerChannelMask shows us all the channels that are active, not how they map onto the link layers */ + for (i = 0; i < ADI_FPGA9025_NUM_LANES; i++) + { + /* The reset bit location maps to the PHY lane # for tx & rx. */ + /* For rx, the value in the laneXBar array is used to + * determine the PHY lane #*/ + if (((initSettings->datapath.deframerCfg[0].lanesInUse >> i) & 0x01) == 0x01) + { + deframer0LaneXbarReset |= (0x01 << initSettings->datapath.deframerCfg[0].laneXbar[i]); + } + + if (((initSettings->datapath.deframerCfg[1].lanesInUse >> i) & 0x01) == 0x01) + { + deframer1LaneXbarReset |= (0x01 << initSettings->datapath.deframerCfg[1].laneXbar[i]); + } + + if (((initSettings->datapath.deframerCfg[2].lanesInUse >> i) & 0x01) == 0x01) + { + deframer2LaneXbarReset |= (0x01 << initSettings->datapath.deframerCfg[2].laneXbar[i]); + } + + /* For tx, the index of the laneXBar maps to the PHY lane #. + * If the laneXBar value is not the initial value (0x1F) that means this index corresponds to a PHY lane + * connected to this framer */ + if (initSettings->datapath.framerCfg[0].laneXbar[i] != 0x1F) + { + framer0LaneXbarReset |= (0x01 << i); + } + if (initSettings->datapath.framerCfg[1].laneXbar[i] != 0x1F) + { + framer1LaneXbarReset |= (0x01 << i); + } + } + + deframer0LaneXbarReset = ~deframer0LaneXbarReset; + deframer1LaneXbarReset = ~deframer1LaneXbarReset; + deframer2LaneXbarReset = ~deframer2LaneXbarReset; + framer0LaneXbarReset = ~framer0LaneXbarReset; + framer1LaneXbarReset = ~framer1LaneXbarReset; + + /* Remove the reset on the lanes in use in lane xbars */ + recoveryAction = fpga9025_Jesd204RxLaneXbarLaneResetBfSet(device, + FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0, + deframer0LaneXbarReset); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Rx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_Jesd204RxLaneXbarLaneResetBfSet(device, + FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1, + deframer1LaneXbarReset); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Rx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_Jesd204RxLaneXbarLaneResetBfSet(device, + FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2, + deframer2LaneXbarReset); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Rx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_Jesd204TxLaneXbarLaneResetBfSet(device, + FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0, + framer0LaneXbarReset); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Tx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_Jesd204TxLaneXbarLaneResetBfSet(device, + FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1, + framer1LaneXbarReset); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting Tx Lane XBar Reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*************************************************************************************************************************************** + * Link layer + ***************************************************************************************************************************************/ + /* Disable all framers/deframers */ + recoveryAction = adi_fpga9025_DeframerDisable(device, + ADI_FPGA9025_DEFRAMER_ALL); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_FramerDisable(device, + ADI_FPGA9025_FRAMER_ALL); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* deframers & framers setup (only configure those that are in use) */ + if (initSettings->datapath.deframerCfg[0].lanesInUse != 0) + { + recoveryAction = adi_fpga9025_DeframerCfgSet(device, + ADI_FPGA9025_DEFRAMER_0, + &initSettings->datapath.deframerCfg[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Hold unused deframer in reset (reset bit in FPGA is read by PerformTx to know if link is used) */ + recoveryAction = fpga9025_XilinxJesd204bResetFixedBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_0, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error holding used FPGA deframer0 in reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (initSettings->datapath.deframerCfg[1].lanesInUse != 0) + { + recoveryAction = adi_fpga9025_DeframerCfgSet(device, + ADI_FPGA9025_DEFRAMER_1, + &initSettings->datapath.deframerCfg[1]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Hold unused deframer in reset (reset bit in FPGA is read by PerformTx to know if link is used) */ + recoveryAction = fpga9025_XilinxJesd204bResetFixedBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_1, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error holding used FPGA deframer1 in reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (initSettings->datapath.deframerCfg[2].lanesInUse != 0) + { + recoveryAction = adi_fpga9025_DeframerCfgSet(device, + ADI_FPGA9025_DEFRAMER_2, + &initSettings->datapath.deframerCfg[2]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Hold unused deframer in reset (reset bit in FPGA is read by PerformTx to know if link is used) */ + recoveryAction = fpga9025_XilinxJesd204bResetFixedBfSet(device, + FPGA9025_BF_JESD204B_DEFRAMER_2, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error holding used FPGA deframer2 in reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (initSettings->datapath.framerCfg[0].lanesInUse != 0) + { + recoveryAction = adi_fpga9025_FramerCfgSet(device, + ADI_FPGA9025_FRAMER_0, + &initSettings->datapath.framerCfg[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Hold unused deframer in reset (reset bit in FPGA is read by PerformTx to know if link is used) */ + recoveryAction = fpga9025_XilinxJesd204bResetFixedBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_0, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error holding used FPGA framer0 in reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (initSettings->datapath.framerCfg[1].lanesInUse != 0) + { + recoveryAction = adi_fpga9025_FramerCfgSet(device, + ADI_FPGA9025_FRAMER_1, + &initSettings->datapath.framerCfg[1]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Hold unused deframer in reset (reset bit in FPGA is read by PerformTx to know if link is used) */ + recoveryAction = fpga9025_XilinxJesd204bResetFixedBfSet(device, + FPGA9025_BF_JESD204B_FRAMER_1, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error holding used FPGA framer1 in reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*************************************************************************************************************************************** + * Sync XBar + ***************************************************************************************************************************************/ + recoveryAction = adi_fpga9025_SyncXBarCfgSet(device, + initSettings->datapath.syncBPolarity, + &initSettings->datapath.syncBSel[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*************************************************************************************************************************************** + * Sysref + ***************************************************************************************************************************************/ + recoveryAction = adi_fpga9025_SysRefControlSet(device, + &initSettings->sysref); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*************************************************************************************************************************************** + * Set the static information in DMAs + ***************************************************************************************************************************************/ + recoveryAction = adi_fpga9025_RxDmaInit(device, + ADI_FPGA9025_DEFRAMER_0, + &initSettings->datapath.rxDmaCfg[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_RxDmaInit(device, + ADI_FPGA9025_DEFRAMER_1, + &initSettings->datapath.rxDmaCfg[1]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_RxDmaInit(device, + ADI_FPGA9025_DEFRAMER_2, + &initSettings->datapath.rxDmaCfg[2]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_TxDmaInit(device, + ADI_FPGA9025_FRAMER_0, + &initSettings->datapath.txDmaCfg[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_TxDmaInit(device, + ADI_FPGA9025_FRAMER_1, + &initSettings->datapath.txDmaCfg[1]); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*************************************************************************************************************************************** + * Reset datapaths + ***************************************************************************************************************************************/ + recoveryAction = adi_fpga9025_RxDataChainReset(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_TxDataChainReset(device); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_InitGet(adi_fpga9025_Device_t* device, + adi_fpga9025_Init_t* initSettings) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t i = 0; + uint8_t laneSel = 1; + uint16_t dataMoverSel = 1; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + initSettings); + + for (i = 0; i < ADI_FPGA9025_NUM_LANES; i++) + { + // int32_t adi_fpga9025_SerializerCfgGet(adi_fpga9025_Device_t *device, adi_fpga9025_LaneSel_e laneSel, adi_fpga9025_SerializerCfg_t *serializerCfg) + recoveryAction = adi_fpga9025_SerializerCfgGet(device, + (adi_fpga9025_LaneSel_e)laneSel, + &initSettings->datapath.serializerCfg[i]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_DeserializerCfgGet(device, + (adi_fpga9025_LaneSel_e)laneSel, + &initSettings->datapath.deserializerCfg[i]); + ADI_ERROR_RETURN(device->common.error.newAction); + laneSel = laneSel << 1; + } + + // get the framer configurations + recoveryAction = adi_fpga9025_FramerCfgGet(device, + ADI_FPGA9025_FRAMER_0, + &initSettings->datapath.framerCfg[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + // get the 2 deframer configurations + recoveryAction = adi_fpga9025_DeframerCfgGet(device, + ADI_FPGA9025_DEFRAMER_0, + &initSettings->datapath.deframerCfg[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_DeframerCfgGet(device, + ADI_FPGA9025_DEFRAMER_1, + &initSettings->datapath.deframerCfg[1]); + ADI_ERROR_RETURN(device->common.error.newAction); + + // get the 8 txdataMover configurations + dataMoverSel = 1; + for (i = 0; i < ADI_FPGA9025_NUM_OF_TX_DATAMOVERS; i++) + { + recoveryAction = adi_fpga9025_TxDmaGet(device, + (adi_fpga9025_TxDatamoverSel_e)dataMoverSel, + &initSettings->datapath.txDmaCfg[i]); + ADI_ERROR_RETURN(device->common.error.newAction); + dataMoverSel = dataMoverSel << 1; + } + + //get the 16 rxdataMover configurations + dataMoverSel = 1; + for (i = 0; i < ADI_FPGA9025_NUM_OF_RX_DATAMOVERS; i++) + { + recoveryAction = adi_fpga9025_RxDmaGet(device, + (adi_fpga9025_RxDatamoverSel_e)dataMoverSel, + &initSettings->datapath.rxDmaCfg[i]); + ADI_ERROR_RETURN(device->common.error.newAction); + dataMoverSel = dataMoverSel << 1; + } + + //the configuration of all tollgates must be the same so we only need to store one of each + recoveryAction = adi_fpga9025_TxTollgateGet(device, + ADI_FPGA9025_TX_DATAMOVER_0, + &initSettings->datapath.txTollgateCfg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_RxTollgateGet(device, + ADI_FPGA9025_RX_DATAMOVER_0, + &initSettings->datapath.rxTollgateCfg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + device->common.error.newAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_axi_adv_spi.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_axi_adv_spi.c new file mode 100644 index 0000000..f0ad535 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_axi_adv_spi.c @@ -0,0 +1,133 @@ +/*! +* \file adi_fpga9025_axi_adv_spi.c +* \brief Contains FPGA9025 AXI Advanced SPI function implementations +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9025_axi_adv_spi.h" +#include "adi_fpga9025_axi_adv_spi_types.h" +#include "../../private/include/fpga9025_bf_axi_adv_spi.h" + +int32_t adi_fpga9025_AxiAdvSpiCfgSet(adi_fpga9025_Device_t* device, + adi_fpga9025_AxiAdvSpiFeatConfig_t* advSpiCfg, + uint8_t slaveSelect) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t registerValue = 0; + /* starting address is slaveSelect0's address. Multiply parameter by 4 since it's byte-addressing and each SS gets a full register */ + uint32_t registerAddress = 0x44A00080 + (slaveSelect * 4); + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + advSpiCfg); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_HAL); +#endif + + /* Build up the registerValue */ + registerValue |= ((uint32_t)advSpiCfg->enable & 0x1) << 0; + registerValue |= ((uint32_t)advSpiCfg->cpol & 0x1) << 1; + registerValue |= ((uint32_t)advSpiCfg->cpha & 0x1) << 2; + registerValue |= ((uint32_t)advSpiCfg->lsbFirst & 0x1) << 3; + registerValue |= ((uint32_t)advSpiCfg->fourWire & 0x1) << 4; + registerValue |= ((uint32_t)advSpiCfg->misoSampleSlip & 0x1) << 5; + registerValue |= ((uint32_t)advSpiCfg->threeWireTriPoint & 0xFF) << 8; + registerValue |= ((uint32_t)advSpiCfg->clockDiv & 0xFFFF) << 16; + + recoveryAction = adi_hal_BbicRegisterWrite(device->common.devHalInfo, + registerAddress, + registerValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + recoveryAction, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + advSpiCfg, + "Error configuring Advanced SPI"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_fpga9025_AxiAdvSpiChipSelectAll(adi_fpga9025_Device_t* device, + uint8_t enable) +{ + /* Manual Slave Select Assertion Enable Bit */ + static const uint32_t MAN_SS_EN = 0x00000080; + + /* Tokelau Device/s slave select indices*/ + /* TODO: This variable should be calculated at Board Discover in future */ + static const uint32_t TOK_CS = 0x00000001; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + /*Address of SPICR*/ + uint32_t spicrAddress = 0x44A00060; + + /*Address of SPISSR*/ + uint32_t spissrAddress = 0x44A00070; + + uint32_t spicrValue = 0; + + recoveryAction = adi_hal_BbicRegisterRead(device->common.devHalInfo, + spicrAddress, + &spicrValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + recoveryAction, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + spicrAddress, + "Error reading spicrAddress"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (enable == ADI_TRUE) + { + /* Select all Tokelau devices */ + recoveryAction = adi_hal_BbicRegisterWrite(device->common.devHalInfo, + spissrAddress, + ~TOK_CS); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + recoveryAction, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + spissrAddress, + "Error selecting all Tokelau devices"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Enable manual select mode */ + recoveryAction = adi_hal_BbicRegisterWrite(device->common.devHalInfo, + spicrAddress, + (spicrValue | MAN_SS_EN)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + recoveryAction, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + spicrAddress, + "Error writing spicrAddress"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Disable manual select mode */ + recoveryAction = adi_hal_BbicRegisterWrite(device->common.devHalInfo, + spicrAddress, + (spicrValue & (~MAN_SS_EN))); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + recoveryAction, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + spicrAddress, + "Error writing spicrAddress"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return device->common.error.newAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_clk.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_clk.c new file mode 100644 index 0000000..6d18425 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_clk.c @@ -0,0 +1,1608 @@ +/** + * \file: adi_fpga9025_clk.c + * + * \brief Contains top level fpga9025 related functions + * + * FPGA9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9025_user.h" +#include "adi_fpga9025_clk.h" +#include "adi_fpga9025.h" +#include "../../private/include/fpga9025_bf_xilinx_clock_wizard.h" +#include "../../private/include/fpga9025_bf_jesd204_phy_ads9.h" + +int32_t adi_fpga9025_MmcmSet(adi_fpga9025_Device_t* device, + adi_fpga9025_MmcmSel_e mmcmSel, + adi_fpga9025_MmcmCfg_t* mmcm) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr = FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + /* Set base address for the correct Clock Wizard module */ + if (mmcmSel == ADI_FPGA9025_CORE_MMCM) + { + baseAddr = FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + mmcmSel, + "Invalid MMCM selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Reset the clock wizard */ + recoveryAction = fpga9025_XilinxClockWizardSoftwareResetBfSet(device, + baseAddr, + 0xA); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error resetting clock wizard"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write the configuration registers */ + recoveryAction = fpga9025_XilinxClockWizardClkfboutMultBfSet(device, + baseAddr, + mmcm->mVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + mmcm->mVal, + "Error setting clock wizard M value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxClockWizardDivclkDivideBfSet(device, + baseAddr, + mmcm->dVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + mmcm->dVal, + "Error setting clock wizard D value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxClockWizardClkout0DivideBfSet(device, + baseAddr, + mmcm->outputClkDiv[0]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + mmcm->outputClkDiv[0], + "Error setting clock wizard channel 0 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxClockWizardClkout1DivideBfSet(device, + baseAddr, + mmcm->outputClkDiv[1]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + mmcm->outputClkDiv[1], + "Error setting clock wizard channel 1 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxClockWizardClkout2DivideBfSet(device, + baseAddr, + mmcm->outputClkDiv[2]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + mmcm->outputClkDiv[2], + "Error setting clock wizard channel 2 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxClockWizardClkout3DivideBfSet(device, + baseAddr, + mmcm->outputClkDiv[3]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + mmcm->outputClkDiv[3], + "Error setting clock wizard channel 3 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxClockWizardClkout4DivideBfSet(device, + baseAddr, + mmcm->outputClkDiv[4]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + mmcm->outputClkDiv[4], + "Error setting clock wizard channel 4 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxClockWizardClkout5DivideBfSet(device, + baseAddr, + mmcm->outputClkDiv[5]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + mmcm->outputClkDiv[5], + "Error setting clock wizard channel 5 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxClockWizardClkout6DivideBfSet(device, + baseAddr, + mmcm->outputClkDiv[6]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + mmcm->outputClkDiv[6], + "Error setting clock wizard channel 6 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set the saddr bitfield to indicate current configuration register values are for dynamic reconfiguration*/ + recoveryAction = fpga9025_XilinxClockWizardSaddrBfSet(device, + baseAddr, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting clock wizard saddr"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set load bitfield to start the dynamic reconfiguration process*/ + recoveryAction = fpga9025_XilinxClockWizardLoadBfSet(device, + baseAddr, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error starting clock wizard dynamic reconfiguration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_MmcmGet(adi_fpga9025_Device_t* device, + adi_fpga9025_MmcmSel_e mmcmSel, + adi_fpga9025_MmcmCfg_t* mmcm) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr = FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + /* Set base address for the correct Clock Wizard module */ + if (mmcmSel == ADI_FPGA9025_CORE_MMCM) + { + baseAddr = FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + mmcmSel, + "Invalid MMCM selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Read the configuration registers */ + recoveryAction = fpga9025_XilinxClockWizardClkfboutMultBfGet(device, + baseAddr, + &mmcm->mVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading clock wizard M value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxClockWizardDivclkDivideBfGet(device, + baseAddr, + &mmcm->dVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading clock wizard D value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxClockWizardClkout0DivideBfGet(device, + baseAddr, + &mmcm->outputClkDiv[0]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading clock wizard channel 0 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxClockWizardClkout1DivideBfGet(device, + baseAddr, + &mmcm->outputClkDiv[1]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading clock wizard channel 1 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxClockWizardClkout2DivideBfGet(device, + baseAddr, + &mmcm->outputClkDiv[2]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading clock wizard channel 2 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxClockWizardClkout3DivideBfGet(device, + baseAddr, + &mmcm->outputClkDiv[3]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading clock wizard channel 3 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxClockWizardClkout4DivideBfGet(device, + baseAddr, + &mmcm->outputClkDiv[4]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading clock wizard channel 4 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxClockWizardClkout5DivideBfGet(device, + baseAddr, + &mmcm->outputClkDiv[5]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading clock wizard channel 5 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxClockWizardClkout6DivideBfGet(device, + baseAddr, + &mmcm->outputClkDiv[6]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading clock wizard channel 6 divider"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_MmcmLockGet(adi_fpga9025_Device_t* device, + adi_fpga9025_MmcmSel_e mmcmSel, + uint8_t* lockBit) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr = FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + lockBit); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + /* Set base address for the correct Clock Wizard module */ + if (mmcmSel == ADI_FPGA9025_CORE_MMCM) + { + baseAddr = FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + mmcmSel, + "Invalid MMCM selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Load bit returns to 0 after reconfiguring and locked */ + recoveryAction = fpga9025_XilinxClockWizardLockedBfGet(device, + baseAddr, + lockBit); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading clock wizard lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_MmcmResetSet(adi_fpga9025_Device_t* device, + adi_fpga9025_MmcmSel_e mmcmSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxClockWizardChanAddr_e baseAddr = FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + /* Set base address for the correct Clock Wizard module */ + if (mmcmSel == ADI_FPGA9025_CORE_MMCM) + { + baseAddr = FPGA9025_BF_JESD204_CORE_CLOCK_WIZARD; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + mmcmSel, + "Invalid MMCM selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Reset the clock wizard */ + recoveryAction = fpga9025_XilinxClockWizardSoftwareResetBfSet(device, + baseAddr, + 0xA); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error resetting clock wizard"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_QpllSet(adi_fpga9025_Device_t* device, + uint8_t quadMask, + adi_fpga9025_QpllCfg_t* qPll) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint16_t mDrpVal = 0; + uint16_t nDrpVal = 0; + uint8_t powerGood = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + qPll); + + switch (qPll->mVal) + { + case 1: + mDrpVal = 0x0800; + break; + case 2: + mDrpVal = 0x0000; + break; + case 3: + mDrpVal = 0x0080; + break; + case 4: + mDrpVal = 0x0100; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + qPll->mVal, + "Invalid M val"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + nDrpVal = qPll->nVal - 2; + + /* Range checks */ + if (qPll->band > ADI_FPGA9025_QPLLCLK0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + qPll->band, + "Invalid band"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /*Quad 0*/ + if ((quadMask & 0x1) == 0x1) + { + /* set ref clk for qpll*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad0Qpll0RefClkSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + qPll->refClkSelect[0]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting ref clk for quad 0 qppl 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204PhyAds9Quad0Qpll1RefClkSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + qPll->refClkSelect[0]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting ref clk for quad 0 qppl 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (qPll->band == ADI_FPGA9025_QPLLCLK0) + { + /* Power up this qpll*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad0Qpll0PdBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error powering up quad 0 qppl 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Power down the other qpll in this quad*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad0Qpll1PdBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error powering down quad 0 qppl 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set the reset bit of the correct qpll*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad0Qpll0ResetBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error resetting quad 0 qpll 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write n and m values through DRP transactions*/ + recoveryAction = adi_fpga9025_DrpWrite(device, + ADI_FPGA9025_QPLLCLK0_N_ADDRESS, + (uint8_t)ADI_FPGA9025_PHY_QUAD0, + nDrpVal, + ADI_FPGA9025_QPLL_N_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error writing to quad 0 qpll 0 N value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_DrpWrite(device, + ADI_FPGA9025_QPLLCLK0_M_ADDRESS, + (uint8_t)ADI_FPGA9025_PHY_QUAD0, + mDrpVal, + ADI_FPGA9025_QPLL_M_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error writing to quad 0 qpll 0 M value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write clk out rate */ + recoveryAction = adi_fpga9025_DrpWrite(device, + ADI_FPGA9025_QPLLCLK0_CLKOUT_RATE_ADDRESS, + (uint8_t)ADI_FPGA9025_PHY_QUAD0, + qPll->qpllClkOutRate, + ADI_FPGA9025_QPLL_CLKOUT_RATE_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error writing to quad 0 qpll 0 clk out rate through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Ensure power good is set for all channels*/ + recoveryAction = adi_fpga9025_LanePowerGoodGet(device, + 0, + &powerGood); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error trying to read power good signals from quad 0 channels"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (powerGood != 0x0F) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ACT_ERR_RESET_FULL, + ADI_FPGA9025_ERR_CHANNEL_POWER_GOOD_FAILURE, + NULL, + "One of more quad 0 channels reporting invalid power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Clear the reset bit of the correct qpll*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad0Qpll0ResetBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error trying to reset qpll 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Power up this qpll*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad0Qpll1PdBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error powering up quad 0 qppl 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Power down the other qpll in this quad*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad0Qpll0PdBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error powering down quad 0 qppl 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set the reset bit */ + recoveryAction = fpga9025_Jesd204PhyAds9Quad0Qpll1ResetBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error resetting quad 0 qpll 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write n and m values through DRP transactions*/ + recoveryAction = adi_fpga9025_DrpWrite(device, + ADI_FPGA9025_QPLLCLK1_N_ADDRESS, + ADI_FPGA9025_PHY_QUAD0, + nDrpVal, + ADI_FPGA9025_QPLL_N_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error writing to quad 0 qpp 1 N value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_DrpWrite(device, + ADI_FPGA9025_QPLLCLK1_M_ADDRESS, + ADI_FPGA9025_PHY_QUAD0, + mDrpVal, + ADI_FPGA9025_QPLL_M_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error writing to quad 0 qpll 1 M value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write clk out rate */ + recoveryAction = adi_fpga9025_DrpWrite(device, + ADI_FPGA9025_QPLLCLK1_CLKOUT_RATE_ADDRESS, + (uint8_t)ADI_FPGA9025_PHY_QUAD0, + qPll->qpllClkOutRate, + ADI_FPGA9025_QPLL_CLKOUT_RATE_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error writing to quad 0 qpll 1 clk out rate through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Ensure power good is set for all channels*/ + recoveryAction = adi_fpga9025_LanePowerGoodGet(device, + 0, + &powerGood); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error trying to read power good signals from quad 0 channels"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (powerGood != 0x0F) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ACT_ERR_RESET_FULL, + ADI_FPGA9025_ERR_CHANNEL_POWER_GOOD_FAILURE, + NULL, + "One of more quad 0 channels reporting invalid power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Clear the reset bit*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad0Qpll1ResetBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error taking quad 0 qpll 1 out of reset"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + /* Quad 1*/ + if ((quadMask & 0x2) == 0x2) + { + /* set ref clk for qpll*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad1Qpll0RefClkSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + qPll->refClkSelect[1]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting ref clk for quad 1 qppl 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204PhyAds9Quad1Qpll1RefClkSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + qPll->refClkSelect[1]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting ref clk for quad 1 qppl 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (qPll->band == ADI_FPGA9025_QPLLCLK0) + { + /* Power up this qpll*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad1Qpll0PdBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error powering up quad 1 qppl 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Power down the other qpll in this quad*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad1Qpll1PdBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error powering down quad 1 qppl 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set the reset bit*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad1Qpll0ResetBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error resetting quad 1 qpll 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write n and m values through DRP transactions*/ + recoveryAction = adi_fpga9025_DrpWrite(device, + ADI_FPGA9025_QPLLCLK0_N_ADDRESS, + ADI_FPGA9025_PHY_QUAD1, + nDrpVal, + ADI_FPGA9025_QPLL_N_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error writing to quad 1 qpp 0 N value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_DrpWrite(device, + ADI_FPGA9025_QPLLCLK0_M_ADDRESS, + ADI_FPGA9025_PHY_QUAD1, + mDrpVal, + ADI_FPGA9025_QPLL_M_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error writing to quad 1 qpll 0 M value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write clk out rate */ + recoveryAction = adi_fpga9025_DrpWrite(device, + ADI_FPGA9025_QPLLCLK0_CLKOUT_RATE_ADDRESS, + (uint8_t)ADI_FPGA9025_PHY_QUAD1, + qPll->qpllClkOutRate, + ADI_FPGA9025_QPLL_CLKOUT_RATE_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error writing to quad 1 qpll 0 clk out rate through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Ensure power good is set for all channels*/ + recoveryAction = adi_fpga9025_LanePowerGoodGet(device, + 1, + &powerGood); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error trying to read power good signals from quad 0 channels"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (powerGood != 0xF0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ACT_ERR_RESET_FULL, + ADI_FPGA9025_ERR_CHANNEL_POWER_GOOD_FAILURE, + NULL, + "One of more quad 1 channels reporting invalid power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Clear reset bit */ + recoveryAction = fpga9025_Jesd204PhyAds9Quad1Qpll0ResetBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error trying to reset qpll 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + /* Power up this qpll*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad1Qpll1PdBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error powering up quad 1 qppl 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Power down the other qpll in this quad*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad1Qpll0PdBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error powering down quad 1 qppl 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Set the reset bit*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad1Qpll1ResetBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error resetting quad 1 qpll 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write n and m values through DRP transactions*/ + recoveryAction = adi_fpga9025_DrpWrite(device, + ADI_FPGA9025_QPLLCLK1_N_ADDRESS, + ADI_FPGA9025_PHY_QUAD1, + nDrpVal, + ADI_FPGA9025_QPLL_N_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error writing to quad 1 qpp 1 N value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_DrpWrite(device, + ADI_FPGA9025_QPLLCLK1_M_ADDRESS, + ADI_FPGA9025_PHY_QUAD1, + mDrpVal, + ADI_FPGA9025_QPLL_M_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error writing to quad 1 qpll 1 M value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write clk out rate */ + recoveryAction = adi_fpga9025_DrpWrite(device, + ADI_FPGA9025_QPLLCLK1_CLKOUT_RATE_ADDRESS, + (uint8_t)ADI_FPGA9025_PHY_QUAD1, + qPll->qpllClkOutRate, + ADI_FPGA9025_QPLL_CLKOUT_RATE_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error writing to quad 1 qpll 1 clk out rate through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Ensure power good is set for all channels*/ + recoveryAction = adi_fpga9025_LanePowerGoodGet(device, + 1, + &powerGood); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error trying to read power good signals from quad 0 channels"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (powerGood != 0xF0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ACT_ERR_RESET_FULL, + ADI_FPGA9025_ERR_CHANNEL_POWER_GOOD_FAILURE, + NULL, + "One of more quad 1 channels reporting invalid power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Clear reset bit*/ + recoveryAction = fpga9025_Jesd204PhyAds9Quad1Qpll1ResetBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error trying to reset qpll 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +//int32_t adi_fpga9025_QpllGet(adi_fpga9025_Device_t *device, adi_fpga9025_QpllSel_e qpllSel, adi_fpga9025_QpllCfg_t *qPll) +int32_t adi_fpga9025_QpllGet(adi_fpga9025_Device_t* device, + adi_fpga9025_Qpll_Quad_e quadSel, + adi_fpga9025_LaneClkSel_e bandSel, + adi_fpga9025_QpllCfg_t* qPll) +{ + int recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint16_t mDrpVal = 0; + uint16_t nDrpVal = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + qPll); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + if (quadSel == ADI_FPGA9025_QPLL_QUAD0) + { + if (bandSel == ADI_FPGA9025_QPLLCLK0) + { + /* Read n and m values through DRP transactions*/ + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK0_N_ADDRESS, + ADI_FPGA9025_PHY_QUAD0, + &nDrpVal, + ADI_FPGA9025_QPLL_N_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Unable to read quad 0 qppl 0 N value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK0_M_ADDRESS, + ADI_FPGA9025_PHY_QUAD0, + &mDrpVal, + ADI_FPGA9025_QPLL_M_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Unable to read quad 0 qppl 0 M value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lpf value */ + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK0_LPF_ADDRESS, + ADI_FPGA9025_PHY_QUAD0, + &qPll->lpf, + ADI_FPGA9025_QPLL_LPF_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading to quad 0 qpll 0 lpf value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write cfg4 value */ + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK0_CFG4_ADDRESS, + ADI_FPGA9025_PHY_QUAD0, + &qPll->cfg4, + ADI_FPGA9025_QPLL_CFG4_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading to quad 0 qpll 0 cfg4 value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write cp value */ + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK0_CP_ADDRESS, + ADI_FPGA9025_PHY_QUAD0, + &qPll->cp, + ADI_FPGA9025_QPLL_CP_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading to quad 0 qpll 0 cp value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lock cfg value */ + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK0_LOCK_CFG_ADDRESS, + ADI_FPGA9025_PHY_QUAD0, + &qPll->lockCfg, + ADI_FPGA9025_QPLL_LOCK_CFG_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading to quad 0 qpll 0 lock cfg value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lock cfg g3 value */ + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK0_LOCK_CFG_G3_ADDRESS, + ADI_FPGA9025_PHY_QUAD0, + &qPll->lockCfgG3, + ADI_FPGA9025_QPLL_LOCK_CFG_G3_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading to quad 0 qpll 0 lock cfg g3 value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (bandSel == ADI_FPGA9025_QPLLCLK1) + { + /* Read n and m values through DRP transactions*/ + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK1_N_ADDRESS, + ADI_FPGA9025_PHY_QUAD0, + &nDrpVal, + ADI_FPGA9025_QPLL_N_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Unable to read quad 0 qppl 1 N value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK1_M_ADDRESS, + ADI_FPGA9025_PHY_QUAD0, + &mDrpVal, + ADI_FPGA9025_QPLL_M_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Unable to read quad 0 qppl 1 M value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Invalid qpll band selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else if (quadSel == ADI_FPGA9025_QPLL_QUAD1) + { + if (bandSel == ADI_FPGA9025_QPLLCLK0) + { + /* Read n and m values through DRP transactions*/ + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK0_N_ADDRESS, + ADI_FPGA9025_PHY_QUAD1, + &nDrpVal, + ADI_FPGA9025_QPLL_N_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Unable to read quad 1 qppl 0 N value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK0_M_ADDRESS, + ADI_FPGA9025_PHY_QUAD1, + &mDrpVal, + ADI_FPGA9025_QPLL_M_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Unable to read quad 1 qppl 0 M value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lpf value */ + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK0_LPF_ADDRESS, + ADI_FPGA9025_PHY_QUAD0, + &qPll->lpf, + ADI_FPGA9025_QPLL_LPF_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading to quad 1 qpll 0 lpf value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write cfg4 value */ + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK0_CFG4_ADDRESS, + ADI_FPGA9025_PHY_QUAD0, + &qPll->cfg4, + ADI_FPGA9025_QPLL_CFG4_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading to quad 1 qpll 0 cfg4 value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write cp value */ + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK0_CP_ADDRESS, + ADI_FPGA9025_PHY_QUAD0, + &qPll->cp, + ADI_FPGA9025_QPLL_CP_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading to quad 1 qpll 0 cp value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lock cfg value */ + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK0_LOCK_CFG_ADDRESS, + ADI_FPGA9025_PHY_QUAD0, + &qPll->lockCfg, + ADI_FPGA9025_QPLL_LOCK_CFG_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading to quad 1 qpll 0 lock cfg value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* write lock cfg g3 value */ + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK0_LOCK_CFG_G3_ADDRESS, + ADI_FPGA9025_PHY_QUAD0, + &qPll->lockCfgG3, + ADI_FPGA9025_QPLL_LOCK_CFG_G3_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading to quad 1 qpll 0 lock cfg g3 value through DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (bandSel == ADI_FPGA9025_QPLLCLK1) + { + /* Read n and m values through DRP transactions*/ + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK1_N_ADDRESS, + ADI_FPGA9025_PHY_QUAD1, + &nDrpVal, + ADI_FPGA9025_QPLL_N_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Unable to read quad 1 qppl 1 N value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_DrpRead(device, + ADI_FPGA9025_QPLLCLK1_M_ADDRESS, + ADI_FPGA9025_PHY_QUAD1, + &mDrpVal, + ADI_FPGA9025_QPLL_M_MASK); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Unable to read quad 1 qppl 1 M value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Invalid qpll band selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Invalid qpll Quad selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + switch (mDrpVal) + { + case 0x0800: + qPll->mVal = 1; + break; + case 0x0000: + qPll->mVal = 2; + break; + case 0x0080: + qPll->mVal = 3; + break; + case 0x0100: + qPll->mVal = 4; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + ADI_FPGA9025_ERR_DRP_ERROR, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Invalid M val reported from DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + switch (nDrpVal) + { + case 0x000E: + qPll->nVal = 16; + break; + case 0x0012: + nDrpVal = 20; + break; + case 0x001E: + nDrpVal = 32; + break; + case 0x0026: + nDrpVal = 40; + break; + case 0x003A: + nDrpVal = 60; + break; + case 0x003E: + nDrpVal = 64; + break; + case 0x0040: + nDrpVal = 66; + break; + case 0x0049: + nDrpVal = 75; + break; + case 0x004E: + nDrpVal = 80; + break; + case 0x0052: + nDrpVal = 84; + break; + case 0x005A: + nDrpVal = 90; + break; + case 0x005E: + nDrpVal = 96; + break; + case 0x0062: + nDrpVal = 100; + break; + case 0x006E: + nDrpVal = 112; + break; + case 0x0076: + nDrpVal = 120; + break; + case 0x007B: + nDrpVal = 125; + break; + case 0x0094: + nDrpVal = 150; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_DEVICEHAL, + ADI_FPGA9025_ERR_DRP_ERROR, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Invalid N val reported from DRP"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + return recoveryAction; +} + +int32_t adi_fpga9025_QpllLockGet(adi_fpga9025_Device_t* device, + uint8_t quadSel, + uint8_t bandSel, + uint8_t* lockBit) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + lockBit); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + if (quadSel == ADI_FPGA9025_QPLL_QUAD0) + { + if (bandSel == ADI_FPGA9025_QPLLCLK0) + { + recoveryAction = fpga9025_Jesd204PhyAds9Quad0Qpll0LockBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + lockBit); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read quad 0 qpll0 lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = fpga9025_Jesd204PhyAds9Quad0Qpll1LockBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + lockBit); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read quad 0 qpll 1 lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else if (quadSel == ADI_FPGA9025_QPLL_QUAD1) + { + if (bandSel == ADI_FPGA9025_QPLLCLK0) + { + recoveryAction = fpga9025_Jesd204PhyAds9Quad1Qpll0LockBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + lockBit); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read quad 1 qpll0 lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + recoveryAction = fpga9025_Jesd204PhyAds9Quad1Qpll1LockBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + lockBit); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read quad 1 qpll 1 lock bit"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + quadSel, + "Invalid quad selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_LanePowerGoodGet(adi_fpga9025_Device_t* device, + uint8_t quadSel, + uint8_t* powerGood) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t bfReturn = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + powerGood); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + /* Range checks */ + if (quadSel > 1) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + quadSel, + "Invalid quad selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *powerGood = 0; + + if (quadSel == 0) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel0GtpowergoodBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &bfReturn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read channel 0 power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + *powerGood |= (bfReturn & 0x01) << 0; + + recoveryAction = fpga9025_Jesd204PhyAds9Channel1GtpowergoodBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &bfReturn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read channel 1 power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + *powerGood |= (bfReturn & 0x01) << 1; + + recoveryAction = fpga9025_Jesd204PhyAds9Channel2GtpowergoodBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &bfReturn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read channel 2 power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + *powerGood |= (bfReturn & 0x01) << 2; + + recoveryAction = fpga9025_Jesd204PhyAds9Channel3GtpowergoodBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &bfReturn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read channel 3 power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + *powerGood |= (bfReturn & 0x01) << 3; + } + else + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel4GtpowergoodBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &bfReturn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read channel 4 power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + *powerGood |= (bfReturn & 0x01) << 4; + + recoveryAction = fpga9025_Jesd204PhyAds9Channel5GtpowergoodBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &bfReturn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read channel 5 power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + *powerGood |= (bfReturn & 0x01) << 5; + + recoveryAction = fpga9025_Jesd204PhyAds9Channel6GtpowergoodBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &bfReturn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read channel 6 power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + *powerGood |= (bfReturn & 0x01) << 6; + + recoveryAction = fpga9025_Jesd204PhyAds9Channel7GtpowergoodBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &bfReturn); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read channel 7 power good"); + ADI_ERROR_RETURN(device->common.error.newAction); + *powerGood |= (bfReturn & 0x01) << 7; + } + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_gpio.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_gpio.c new file mode 100644 index 0000000..512d56e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_gpio.c @@ -0,0 +1,791 @@ +/** + * \file: adi_fpga9025_jesd.c + * + * \brief Contains top level tx fpga9025 related functions + * + * FPGA9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9025_user.h" +#include "adi_fpga9025_gpio.h" +#include "adi_fpga9025.h" +#include "../../private/include/fpga9025_bf_axi_adrv9025.h" + +int32_t adi_fpga9025_GpioModeSet(adi_fpga9025_Device_t* device, + adi_fpga9025_GpioModes_e gpioMode) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t enable = 1; + uint8_t disable = 0; + uint8_t i = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + if (gpioMode == ADI_FPGA9025_GPIO_MODE_NONE) + { + recoveryAction = fpga9025_AxiAdrv9025GpioEnSpi2BfSet(device, + FPGA9025_BF_AXI_ADRV9025, + disable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not disable spi2 mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_AxiAdrv9025GpioEnArmJtagBfSet(device, + FPGA9025_BF_AXI_ADRV9025, + disable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not disable jtag mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_FPGA9025_GPIO_PINS; i++) + { + device->devStateInfo.gpioPinMode[i] = ADI_FPGA9025_GPIO_MODE_NONE; + } + } + + if (gpioMode == ADI_FPGA9025_GPIO_MODE_JTAG) + { + recoveryAction = fpga9025_AxiAdrv9025GpioEnArmJtagBfSet(device, + FPGA9025_BF_AXI_ADRV9025, + enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not enable jtag mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_FPGA9025_GPIO_PINS; i++) + { + device->devStateInfo.gpioPinMode[i] = ADI_FPGA9025_GPIO_MODE_JTAG; + } + } + + if (gpioMode == ADI_FPGA9025_GPIO_MODE_SPI2) + { + recoveryAction = fpga9025_AxiAdrv9025GpioEnSpi2BfSet(device, + FPGA9025_BF_AXI_ADRV9025, + enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not enable spi2 mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* GPIO[3:0] are used for SPI2 mode */ + device->devStateInfo.gpioPinMode[0] = ADI_FPGA9025_GPIO_MODE_SPI2; + device->devStateInfo.gpioPinMode[1] = ADI_FPGA9025_GPIO_MODE_SPI2; + device->devStateInfo.gpioPinMode[2] = ADI_FPGA9025_GPIO_MODE_SPI2; + device->devStateInfo.gpioPinMode[3] = ADI_FPGA9025_GPIO_MODE_SPI2; + } + + return recoveryAction; +} + +int32_t adi_fpga9025_GpioModeGet(adi_fpga9025_Device_t* device, + adi_fpga9025_GpioModes_e* gpioMode) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t jtagStatus; + uint8_t spi2Status; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, + gpioMode); + + recoveryAction = fpga9025_AxiAdrv9025GpioEnSpi2BfGet(device, + FPGA9025_BF_AXI_ADRV9025, + &spi2Status); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read spi2 mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_AxiAdrv9025GpioEnArmJtagBfGet(device, + FPGA9025_BF_AXI_ADRV9025, + &jtagStatus); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read jtag mode"); + ADI_ERROR_RETURN(device->common.error.newAction); + + *gpioMode = ADI_FPGA9025_GPIO_MODE_NONE; + + if (spi2Status > 0) + { + *gpioMode = ADI_FPGA9025_GPIO_MODE_SPI2; + } + + if (jtagStatus > 0) + { + //Jtag mode overrides spi2 mode + *gpioMode = ADI_FPGA9025_GPIO_MODE_JTAG; + } + + return recoveryAction; +} + +int32_t adi_fpga9025_GpioInputDirSet(adi_fpga9025_Device_t* device, + uint32_t pinSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t orgPinSelMask = 0; + uint32_t newPinSelMask = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + if (pinSelMask > ADI_FPGA9025_GPIO_MAX_VALUE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pinSelMask, + "pinSelMask cannot exceed max value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = fpga9025_AxiAdrv9025GpioTristateBfGet(device, + FPGA9025_BF_AXI_ADRV9025, + &orgPinSelMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read GPIO tristate state"); + ADI_ERROR_RETURN(device->common.error.newAction); + + newPinSelMask = orgPinSelMask | pinSelMask; + + recoveryAction = fpga9025_AxiAdrv9025GpioTristateBfSet(device, + FPGA9025_BF_AXI_ADRV9025, + newPinSelMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write GPIO tristate value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_GpioInputDirGet(adi_fpga9025_Device_t* device, + uint32_t* pinSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, + pinSelMask); + + recoveryAction = fpga9025_AxiAdrv9025GpioTristateBfGet(device, + FPGA9025_BF_AXI_ADRV9025, + pinSelMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read GPIO tristate state"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_GpioOutputDirSet(adi_fpga9025_Device_t* device, + uint32_t pinSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t orgPinSelMask = 0; + uint32_t newPinSelMask = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + if (pinSelMask > ADI_FPGA9025_GPIO_MAX_VALUE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pinSelMask, + "pinSelMask cannot exceed max value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = fpga9025_AxiAdrv9025GpioTristateBfGet(device, + FPGA9025_BF_AXI_ADRV9025, + &orgPinSelMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read GPIO tristate state"); + ADI_ERROR_RETURN(device->common.error.newAction); + + newPinSelMask = ~(~orgPinSelMask | pinSelMask); + + recoveryAction = fpga9025_AxiAdrv9025GpioTristateBfSet(device, + FPGA9025_BF_AXI_ADRV9025, + newPinSelMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write GPIO tristate value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_GpioOutputDirGet(adi_fpga9025_Device_t* device, + uint32_t* pinSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + uint32_t mask = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, + pinSelMask); + + recoveryAction = fpga9025_AxiAdrv9025GpioTristateBfGet(device, + FPGA9025_BF_AXI_ADRV9025, + &mask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read GPIO tristate state"); + ADI_ERROR_RETURN(device->common.error.newAction); + + //an output pin is represented as a 0 in the diredction register. + *pinSelMask = ~mask & ADI_FPGA9025_GPIO_MAX_VALUE; + + return recoveryAction; +} + +int32_t adi_fpga9025_GpioOeSet(adi_fpga9025_Device_t* device, + adi_fpga9025_GpioPinType_e gpioPinType, + uint32_t pinSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t orgPinSelMask = 0; + uint32_t newPinSelMask = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + if (pinSelMask > ADI_FPGA9025_GPIO_MAX_VALUE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + pinSelMask, + "pinSelMask cannot exceed max value"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = fpga9025_AxiAdrv9025GpioTristateBfGet(device, + FPGA9025_BF_AXI_ADRV9025, + &orgPinSelMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read GPIO tristate state"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (gpioPinType == ADI_FPGA9025_GPIO_PIN_OUTPUT) + { + //output pins are 0 + newPinSelMask = orgPinSelMask & ~pinSelMask; + } + else + { + //input pins are 1 + newPinSelMask = orgPinSelMask | pinSelMask; + } + + recoveryAction = fpga9025_AxiAdrv9025GpioTristateBfSet(device, + FPGA9025_BF_AXI_ADRV9025, + newPinSelMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write GPIO tristate value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_GpioOeGet(adi_fpga9025_Device_t* device, + uint32_t* pinSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, + pinSelMask); + + recoveryAction = fpga9025_AxiAdrv9025GpioTristateBfGet(device, + FPGA9025_BF_AXI_ADRV9025, + pinSelMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read GPIO tristate value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_GpioWrite(adi_fpga9025_Device_t* device, + uint32_t wrData) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + recoveryAction = fpga9025_AxiAdrv9025GpioOutputBfSet(device, + FPGA9025_BF_AXI_ADRV9025, + wrData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write GPIO pin value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_GpioRead(adi_fpga9025_Device_t* device, + uint32_t* rdData) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + ADI_NULL_PTR_RETURN(&device->common, + rdData); + + recoveryAction = fpga9025_AxiAdrv9025GpioInputBfGet(device, + FPGA9025_BF_AXI_ADRV9025, + rdData); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not read GPIO pin value"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_TddGpioSet(adi_fpga9025_Device_t* device, + adi_fpga9025_TddModule_e tddModuleSel, + adi_fpga9025_GpioPinSel_e gpioSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t txToOrxEnMask = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + if (gpioSel < ADI_FPGA9025_GPIO_00 || gpioSel > ADI_FPGA9025_GPIO_18) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioSel, + "Invalid GPIO selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (device->devStateInfo.gpioPinMode[(uint32_t)gpioSel] != ADI_FPGA9025_GPIO_MODE_NONE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioSel, + "GPIO selected is currently in use."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + device->devStateInfo.gpioPinMode[(uint32_t)gpioSel] = ADI_FPGA9025_GPIO_MODE_TDD; + + switch (tddModuleSel) + { + case ADI_FPGA9025_ENABLE1CONTROL: + recoveryAction = fpga9025_AxiAdrv9025GpioSelTx1ToOrx1BfSet(device, + FPGA9025_BF_AXI_ADRV9025, + gpioSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not set Enable1 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9025_ENABLE2CONTROL: + recoveryAction = fpga9025_AxiAdrv9025GpioSelTx2ToOrx1BfSet(device, + FPGA9025_BF_AXI_ADRV9025, + gpioSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not set Enable2 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9025_ENABLE3CONTROL: + recoveryAction = fpga9025_AxiAdrv9025GpioSelTx1ToOrx2BfSet(device, + FPGA9025_BF_AXI_ADRV9025, + gpioSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not set Enable3 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9025_ENABLE4CONTROL: + recoveryAction = fpga9025_AxiAdrv9025GpioSelTx2ToOrx2BfSet(device, + FPGA9025_BF_AXI_ADRV9025, + gpioSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not set Enable4 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9025_SELECT1CONTROL: + recoveryAction = fpga9025_AxiAdrv9025GpioSelTx3ToOrx3BfSet(device, + FPGA9025_BF_AXI_ADRV9025, + gpioSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not set Select1 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9025_SELECT2CONTROL: + recoveryAction = fpga9025_AxiAdrv9025GpioSelTx4ToOrx3BfSet(device, + FPGA9025_BF_AXI_ADRV9025, + gpioSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not set Select2 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9025_SELECT3CONTROL: + recoveryAction = fpga9025_AxiAdrv9025GpioSelTx3ToOrx4BfSet(device, + FPGA9025_BF_AXI_ADRV9025, + gpioSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not set Select3 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9025_SELECT4CONTROL: + recoveryAction = fpga9025_AxiAdrv9025GpioSelTx4ToOrx4BfSet(device, + FPGA9025_BF_AXI_ADRV9025, + gpioSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not set Select4 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioSel, + "Invalid TDD module selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + txToOrxEnMask |= (1 << (uint32_t)gpioSel); + + recoveryAction = fpga9025_AxiAdrv9025GpioEnTxToOrxBfSet(device, + FPGA9025_BF_AXI_ADRV9025, + txToOrxEnMask); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not set Tx to ORx enable bitfield."); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_TddGpioGet(adi_fpga9025_Device_t* device, + adi_fpga9025_TddModule_e tddModuleSel, + adi_fpga9025_GpioPinSel_e* gpioSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + gpioSel); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + switch (tddModuleSel) + { + case ADI_FPGA9025_ENABLE1CONTROL: + recoveryAction = fpga9025_AxiAdrv9025GpioSelTx1ToOrx1BfGet(device, + FPGA9025_BF_AXI_ADRV9025, + (uint8_t *)gpioSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not get Enable1 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9025_ENABLE2CONTROL: + recoveryAction = fpga9025_AxiAdrv9025GpioSelTx2ToOrx1BfGet(device, + FPGA9025_BF_AXI_ADRV9025, + (uint8_t *)gpioSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not get Enable2 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9025_ENABLE3CONTROL: + recoveryAction = fpga9025_AxiAdrv9025GpioSelTx1ToOrx2BfGet(device, + FPGA9025_BF_AXI_ADRV9025, + (uint8_t *)gpioSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not get Enable3 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9025_ENABLE4CONTROL: + recoveryAction = fpga9025_AxiAdrv9025GpioSelTx2ToOrx2BfGet(device, + FPGA9025_BF_AXI_ADRV9025, + (uint8_t *)gpioSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not get Enable4 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9025_SELECT1CONTROL: + recoveryAction = fpga9025_AxiAdrv9025GpioSelTx3ToOrx3BfGet(device, + FPGA9025_BF_AXI_ADRV9025, + (uint8_t *)gpioSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not get Select1 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9025_SELECT2CONTROL: + recoveryAction = fpga9025_AxiAdrv9025GpioSelTx4ToOrx3BfGet(device, + FPGA9025_BF_AXI_ADRV9025, + (uint8_t *)gpioSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not get Select2 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9025_SELECT3CONTROL: + recoveryAction = fpga9025_AxiAdrv9025GpioSelTx3ToOrx4BfGet(device, + FPGA9025_BF_AXI_ADRV9025, + (uint8_t *)gpioSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not get Select3 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + case ADI_FPGA9025_SELECT4CONTROL: + recoveryAction = fpga9025_AxiAdrv9025GpioSelTx4ToOrx4BfGet(device, + FPGA9025_BF_AXI_ADRV9025, + (uint8_t *)gpioSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not get Select4 GPIO sel."); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + gpioSel, + "Invalid TDD module selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_TddGpioAllClear(adi_fpga9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t i = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); + + for (i = 0; i < ADI_FPGA9025_GPIO_PINS; i++) + { + if (device->devStateInfo.gpioPinMode[i] == ADI_FPGA9025_GPIO_MODE_TDD) + { + device->devStateInfo.gpioPinMode[i] = ADI_FPGA9025_GPIO_MODE_NONE; + } + } + + recoveryAction = adi_hal_BbicRegisterWrite(device->common.devHalInfo, + 0x43041080, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + recoveryAction, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error clearing gpio_sel_tx_to_orx_0 register."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_hal_BbicRegisterWrite(device->common.devHalInfo, + 0x43041084, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + recoveryAction, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Error clearing gpio_sel_tx_to_orx_1 register."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_AxiAdrv9025GpioEnTxToOrxBfSet(device, + FPGA9025_BF_AXI_ADRV9025, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + "Could not clear Tx to ORx enable bitfield."); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_hal.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_hal.c new file mode 100644 index 0000000..7e9b0ba --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_hal.c @@ -0,0 +1,294 @@ +/** +* \file adi_fpga9025_hal.c +* \brief Contains ADI Transceiver Hardware Abstraction functions +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +*/ + +/* Intermediate platform HAL layer maintained by Analog Devices */ + +#include "adi_fpga9025_user.h" +#include "adi_fpga9025_hal.h" +#include "adi_fpga9025_error.h" +#include "adi_platform.h" + +#include "../../private/include/fpga9025_bf_axi_hmc.h" + +int32_t adi_fpga9025_RegisterFieldRead(adi_fpga9025_Device_t* device, + const uint32_t addr, + uint32_t* fieldVal, + uint32_t mask, + uint8_t startBit) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t rdData = 0; + uint32_t regVal = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + ADI_NULL_PTR_RETURN(&device->common, + fieldVal); + + recoveryAction = adi_fpga9025_RegisterRead(device, + addr, + &rdData); + ADI_ERROR_RETURN(device->common.error.newAction); + + regVal = rdData; + *fieldVal = (regVal & mask) >> startBit; + + return recoveryAction; +} + +int32_t adi_fpga9025_RegisterFieldWrite(adi_fpga9025_Device_t* device, + const uint32_t addr, + uint32_t fieldVal, + uint32_t mask, + uint8_t startBit) +{ + UNUSED_PARA(startBit); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + uint32_t registerVal = 0; + uint32_t newRegVal = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + recoveryAction = adi_fpga9025_RegisterRead(device, + addr, + ®isterVal); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* modify the register value*/ + newRegVal = (registerVal & ~mask) | fieldVal; + + /* write to the register with modified value*/ + recoveryAction = adi_fpga9025_RegisterWrite(device, + addr, + newRegVal); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_RegisterRead(adi_fpga9025_Device_t* device, + uint32_t addr, + uint32_t* data) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t halError = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + halError = adi_hal_BbicRegisterRead(device->common.devHalInfo, + addr, + data); + ADI_ERROR_REPORT(&device->common, + 2, + (adi_common_ErrSources_e)halError, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "FPGA AXI Reg Read error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_RegisterWrite(adi_fpga9025_Device_t* device, + uint32_t addr, + uint32_t data) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t halError = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + halError = adi_hal_BbicRegisterWrite(device->common.devHalInfo, + addr, + data); + ADI_ERROR_REPORT(&device->common, + 2, + (adi_common_ErrSources_e)halError, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "FPGA Reg write error"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_RamRead(adi_fpga9025_Device_t* device, + const uint64_t ramAddress, + uint32_t data[], + uint32_t length) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + uint32_t remainingLength = length; + uint64_t endAddr = ramAddress + (length * sizeof(uint32_t)); + uint64_t currRamAddress = ramAddress; + uint32_t currLength = 0; + uint32_t dataOffset = 0; + + /* HMC = 8GB divided by pagesize withb a max page size of 1GB */ + /* offset into a page accessed via devuio1 */ + uint32_t offsetAddr = ramAddress & (device->memoryPageSize - 1); /* Mask off the upper bits in the addr */ + uint8_t pageId = (uint8_t)(ramAddress / device->memoryPageSize); + uint64_t nextPageBoundary = (uint64_t)(pageId + 1) * device->memoryPageSize; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + if (ramAddress % ADI_FPGA9025_RAM_ADDRESS_BOUNDARY != 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + ramAddress, + "RAM address must be on a 128 byte boundary"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + do + { + recoveryAction = fpga9025_AxiHmcAxilitePageBfSet(device, + FPGA9025_BF_AXI_HMC, + pageId); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to HMC page"); + ADI_ERROR_RETURN(device->common.error.newAction); + + currLength = (uint32_t)((endAddr > nextPageBoundary) ? (nextPageBoundary - currRamAddress) / sizeof(uint32_t) : remainingLength); + /* If we cross a page boundary, only send the difference */ + + recoveryAction = adi_hal_BbicRegistersRead(device->common.devHalInfo, + offsetAddr, + &data[dataOffset], + currLength); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + remainingLength -= currLength; + offsetAddr = 0; + /* The first access could be in the middle of a page. However, each subsequent pages will be offset 0 from the start of that page */ + currRamAddress += currLength * sizeof(uint32_t); /* Move to where the next access will point to in RAM */ + pageId++; /* Move to the next page */ + dataOffset += currLength; /* Move to the next block in the data array */ + nextPageBoundary += device->memoryPageSize; + } + while (remainingLength > 0); + + return recoveryAction; +} + +int32_t adi_fpga9025_RamWrite(adi_fpga9025_Device_t* device, + const uint64_t ramAddress, + uint32_t data[], + uint32_t length) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + uint32_t remainingLength = length; + uint64_t endAddr = ramAddress + (length * sizeof(uint32_t)); + uint64_t currRamAddress = ramAddress; + uint32_t currLength = 0; + uint32_t dataOffset = 0; + + /* HMC = 8GB divided by pagesize withb a max page size of 1GB */ + /* offset into a page accessed via devuio1 */ + uint32_t offsetAddr = ramAddress & (device->memoryPageSize - 1); /* Mask off the upper bits in the addr */ + uint8_t pageId = (uint8_t)(ramAddress / device->memoryPageSize); + uint64_t nextPageBoundary = (uint64_t)(pageId + 1) * device->memoryPageSize; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + if (ramAddress % ADI_FPGA9025_RAM_ADDRESS_BOUNDARY != 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + ramAddress, + "RAM address must be on a 128 byte boundary"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + do + { + recoveryAction = fpga9025_AxiHmcAxilitePageBfSet(device, + FPGA9025_BF_AXI_HMC, + pageId); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to HMC page"); + ADI_ERROR_RETURN(device->common.error.newAction); + + currLength = (uint32_t)((endAddr > nextPageBoundary) ? (nextPageBoundary - currRamAddress) / sizeof(uint32_t) : remainingLength); + /* If we cross a page boundary, only send the difference */ + + recoveryAction = adi_hal_BbicRegistersWrite(device->common.devHalInfo, + offsetAddr, + &data[dataOffset], + currLength); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + remainingLength -= currLength; + offsetAddr = 0; + /* The first access could be in the middle of a page. However, each subsequent pages will be offset 0 from the start of that page */ + currRamAddress += currLength * sizeof(uint32_t); /* Move to where the next access will point to in RAM */ + pageId ++; /* Move to the next page */ + dataOffset += currLength; /* Move to the next block in the data array */ + nextPageBoundary += device->memoryPageSize; + } + while (remainingLength > 0); + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_jesd.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_jesd.c new file mode 100644 index 0000000..2cb8ea7 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_jesd.c @@ -0,0 +1,3417 @@ +/** + * \file: adi_fpga9025_jesd.c + * + * \brief Contains top level tx fpga9025 related functions + * + * FPGA9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9025_user.h" +#include "adi_fpga9025_jesd.h" +#include "adi_fpga9025.h" +#include "../../private/include/fpga9025_bf_axi_adrv9025.h" +#include "../../private/include/fpga9025_bf_jesd204_phy_ads9.h" +#include "../../private/include/fpga9025_jesd.h" +#include "../../private/include/fpga9025_bf_xilinx_jesd204b.h" +#include "../../private/include/fpga9025_bf_xilinx_jesd204c.h" +#include "../../private/include/fpga9025_bf_jesd204_sysref_control.h" +#include "../../private/include/fpga9025_bf_jesd204b_sync_xbar.h" +#include "../../private/include/fpga9025_bf_jesd204_rx_lane_xbar.h" +#include "../../private/include/fpga9025_bf_jesd204_tx_lane_xbar.h" + +int32_t adi_fpga9025_SerializerCfgSet(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + adi_fpga9025_SerializerCfg_t* serializerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + uint8_t txRateEncodedValue = 0; + int32_t i = 0; + int32_t selectBit = 0; + + char serializerErrStr[][64] = { + "Error setting channel 0 cpll ref clk", + "Error setting channel 0 tx pll clk sel", + "Error setting channel 0 tx rate (final divider)", + "Error setting channel 0 tx polarity", + "Error setting channel 0 tx precursor", + "Error setting channel 0 tx postcursor", + "Error setting channel 0 tx diffCtrl", + "Error setting channel 0 tx encoder8b10bEnable", + "Error setting channel 0 tx clk out", + "Error setting channel 0 tx powerDown" /* Leave this as the last element. The order here matches the order in which they are called below */ + }; + uint32_t laneNumPos = 22; + + typedef struct + { + int32_t (*CpllRefClkSelBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*TxPllClkSelBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*TxRateBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*TxPolarityBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*TxPrecursorBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*TxPostcursorBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*TxDiffControlBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*Tx8b10bEnableBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*TxClkOutBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*TxPowerdownBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + } fpgaSerializerSet_t; + + fpgaSerializerSet_t serializerSetFct[] = { + { + .CpllRefClkSelBfSet = fpga9025_Jesd204PhyAds9Channel0CpllRefClkSelBfSet, + .TxPllClkSelBfSet = fpga9025_Jesd204PhyAds9Channel0TxPllClkSelBfSet, + .TxRateBfSet = fpga9025_Jesd204PhyAds9Channel0TxRateBfSet, + .TxPolarityBfSet = fpga9025_Jesd204PhyAds9Channel0TxPolarityBfSet, + .TxPrecursorBfSet = fpga9025_Jesd204PhyAds9Channel0TxPrecursorBfSet, + .TxPostcursorBfSet = fpga9025_Jesd204PhyAds9Channel0TxPostcursorBfSet, + .TxDiffControlBfSet = fpga9025_Jesd204PhyAds9Channel0TxDiffControlBfSet, + .Tx8b10bEnableBfSet = fpga9025_Jesd204PhyAds9Channel0Tx8b10bEnableBfSet, + .TxClkOutBfSet = fpga9025_Jesd204PhyAds9Channel0TxOutClkSelBfSet, + .TxPowerdownBfSet = fpga9025_Jesd204PhyAds9Channel0TxPowerdownBfSet + }, + { + .CpllRefClkSelBfSet = fpga9025_Jesd204PhyAds9Channel1CpllRefClkSelBfSet, + .TxPllClkSelBfSet = fpga9025_Jesd204PhyAds9Channel1TxPllClkSelBfSet, + .TxRateBfSet = fpga9025_Jesd204PhyAds9Channel1TxRateBfSet, + .TxPolarityBfSet = fpga9025_Jesd204PhyAds9Channel1TxPolarityBfSet, + .TxPrecursorBfSet = fpga9025_Jesd204PhyAds9Channel1TxPrecursorBfSet, + .TxPostcursorBfSet = fpga9025_Jesd204PhyAds9Channel1TxPostcursorBfSet, + .TxDiffControlBfSet = fpga9025_Jesd204PhyAds9Channel1TxDiffControlBfSet, + .Tx8b10bEnableBfSet = fpga9025_Jesd204PhyAds9Channel1Tx8b10bEnableBfSet, + .TxClkOutBfSet = fpga9025_Jesd204PhyAds9Channel1TxOutClkSelBfSet, + .TxPowerdownBfSet = fpga9025_Jesd204PhyAds9Channel1TxPowerdownBfSet + }, + { + .CpllRefClkSelBfSet = fpga9025_Jesd204PhyAds9Channel2CpllRefClkSelBfSet, + .TxPllClkSelBfSet = fpga9025_Jesd204PhyAds9Channel2TxPllClkSelBfSet, + .TxRateBfSet = fpga9025_Jesd204PhyAds9Channel2TxRateBfSet, + .TxPolarityBfSet = fpga9025_Jesd204PhyAds9Channel2TxPolarityBfSet, + .TxPrecursorBfSet = fpga9025_Jesd204PhyAds9Channel2TxPrecursorBfSet, + .TxPostcursorBfSet = fpga9025_Jesd204PhyAds9Channel2TxPostcursorBfSet, + .TxDiffControlBfSet = fpga9025_Jesd204PhyAds9Channel2TxDiffControlBfSet, + .Tx8b10bEnableBfSet = fpga9025_Jesd204PhyAds9Channel2Tx8b10bEnableBfSet, + .TxClkOutBfSet = fpga9025_Jesd204PhyAds9Channel2TxOutClkSelBfSet, + .TxPowerdownBfSet = fpga9025_Jesd204PhyAds9Channel2TxPowerdownBfSet + }, + { + .CpllRefClkSelBfSet = fpga9025_Jesd204PhyAds9Channel3CpllRefClkSelBfSet, + .TxPllClkSelBfSet = fpga9025_Jesd204PhyAds9Channel3TxPllClkSelBfSet, + .TxRateBfSet = fpga9025_Jesd204PhyAds9Channel3TxRateBfSet, + .TxPolarityBfSet = fpga9025_Jesd204PhyAds9Channel3TxPolarityBfSet, + .TxPrecursorBfSet = fpga9025_Jesd204PhyAds9Channel3TxPrecursorBfSet, + .TxPostcursorBfSet = fpga9025_Jesd204PhyAds9Channel3TxPostcursorBfSet, + .TxDiffControlBfSet = fpga9025_Jesd204PhyAds9Channel3TxDiffControlBfSet, + .Tx8b10bEnableBfSet = fpga9025_Jesd204PhyAds9Channel3Tx8b10bEnableBfSet, + .TxClkOutBfSet = fpga9025_Jesd204PhyAds9Channel3TxOutClkSelBfSet, + .TxPowerdownBfSet = fpga9025_Jesd204PhyAds9Channel3TxPowerdownBfSet + }, + { + .CpllRefClkSelBfSet = fpga9025_Jesd204PhyAds9Channel4CpllRefClkSelBfSet, + .TxPllClkSelBfSet = fpga9025_Jesd204PhyAds9Channel4TxPllClkSelBfSet, + .TxRateBfSet = fpga9025_Jesd204PhyAds9Channel4TxRateBfSet, + .TxPolarityBfSet = fpga9025_Jesd204PhyAds9Channel4TxPolarityBfSet, + .TxPrecursorBfSet = fpga9025_Jesd204PhyAds9Channel4TxPrecursorBfSet, + .TxPostcursorBfSet = fpga9025_Jesd204PhyAds9Channel4TxPostcursorBfSet, + .TxDiffControlBfSet = fpga9025_Jesd204PhyAds9Channel4TxDiffControlBfSet, + .Tx8b10bEnableBfSet = fpga9025_Jesd204PhyAds9Channel4Tx8b10bEnableBfSet, + .TxClkOutBfSet = fpga9025_Jesd204PhyAds9Channel4TxOutClkSelBfSet, + .TxPowerdownBfSet = fpga9025_Jesd204PhyAds9Channel4TxPowerdownBfSet + }, + { + .CpllRefClkSelBfSet = fpga9025_Jesd204PhyAds9Channel5CpllRefClkSelBfSet, + .TxPllClkSelBfSet = fpga9025_Jesd204PhyAds9Channel5TxPllClkSelBfSet, + .TxRateBfSet = fpga9025_Jesd204PhyAds9Channel5TxRateBfSet, + .TxPolarityBfSet = fpga9025_Jesd204PhyAds9Channel5TxPolarityBfSet, + .TxPrecursorBfSet = fpga9025_Jesd204PhyAds9Channel5TxPrecursorBfSet, + .TxPostcursorBfSet = fpga9025_Jesd204PhyAds9Channel5TxPostcursorBfSet, + .TxDiffControlBfSet = fpga9025_Jesd204PhyAds9Channel5TxDiffControlBfSet, + .Tx8b10bEnableBfSet = fpga9025_Jesd204PhyAds9Channel5Tx8b10bEnableBfSet, + .TxClkOutBfSet = fpga9025_Jesd204PhyAds9Channel5TxOutClkSelBfSet, + .TxPowerdownBfSet = fpga9025_Jesd204PhyAds9Channel5TxPowerdownBfSet + }, + { + .CpllRefClkSelBfSet = fpga9025_Jesd204PhyAds9Channel6CpllRefClkSelBfSet, + .TxPllClkSelBfSet = fpga9025_Jesd204PhyAds9Channel6TxPllClkSelBfSet, + .TxRateBfSet = fpga9025_Jesd204PhyAds9Channel6TxRateBfSet, + .TxPolarityBfSet = fpga9025_Jesd204PhyAds9Channel6TxPolarityBfSet, + .TxPrecursorBfSet = fpga9025_Jesd204PhyAds9Channel6TxPrecursorBfSet, + .TxPostcursorBfSet = fpga9025_Jesd204PhyAds9Channel6TxPostcursorBfSet, + .TxDiffControlBfSet = fpga9025_Jesd204PhyAds9Channel6TxDiffControlBfSet, + .Tx8b10bEnableBfSet = fpga9025_Jesd204PhyAds9Channel6Tx8b10bEnableBfSet, + .TxClkOutBfSet = fpga9025_Jesd204PhyAds9Channel6TxOutClkSelBfSet, + .TxPowerdownBfSet = fpga9025_Jesd204PhyAds9Channel6TxPowerdownBfSet + }, + { + .CpllRefClkSelBfSet = fpga9025_Jesd204PhyAds9Channel7CpllRefClkSelBfSet, + .TxPllClkSelBfSet = fpga9025_Jesd204PhyAds9Channel7TxPllClkSelBfSet, + .TxRateBfSet = fpga9025_Jesd204PhyAds9Channel7TxRateBfSet, + .TxPolarityBfSet = fpga9025_Jesd204PhyAds9Channel7TxPolarityBfSet, + .TxPrecursorBfSet = fpga9025_Jesd204PhyAds9Channel7TxPrecursorBfSet, + .TxPostcursorBfSet = fpga9025_Jesd204PhyAds9Channel7TxPostcursorBfSet, + .TxDiffControlBfSet = fpga9025_Jesd204PhyAds9Channel7TxDiffControlBfSet, + .Tx8b10bEnableBfSet = fpga9025_Jesd204PhyAds9Channel7Tx8b10bEnableBfSet, + .TxClkOutBfSet = fpga9025_Jesd204PhyAds9Channel7TxOutClkSelBfSet, + .TxPowerdownBfSet = fpga9025_Jesd204PhyAds9Channel7TxPowerdownBfSet + } + }; + + uint32_t strIdx = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + serializerCfg); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + switch (serializerCfg->rate) + { + case 0: + txRateEncodedValue = 0; + break; + case 1: + txRateEncodedValue = 1; + break; + case 2: + txRateEncodedValue = 2; + break; + case 4: + txRateEncodedValue = 3; + break; + case 8: + txRateEncodedValue = 4; + break; + case 16: + txRateEncodedValue = 5; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + serializerCfg->rate, + "Invalid tx rate (final divider) value"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + for (i = 0; i < ADI_FPGA9025_NUM_LANES; i++) + { + if (laneSelMask == 0) + { + break; /* Already processed all mask bits. */ + } + + selectBit = 1 << i; /* process each bit from right most to left most. */ + + if ((laneSelMask & selectBit) == 0) + { + continue; /* If current bit mask is not set then go to next bit mask */ + } + + laneSelMask &= ~selectBit; /* mark off the select bit that is currently processing. */ + + /* set cpll ref clk */ + strIdx = 0; + if (serializerSetFct[i].CpllRefClkSelBfSet != NULL) + { + recoveryAction = serializerSetFct[i].CpllRefClkSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + serializerCfg->cpllRefClkSel); + serializerErrStr[strIdx][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* set channel clk */ + strIdx++; + if (serializerSetFct[i].TxPllClkSelBfSet != NULL) + { + recoveryAction = serializerSetFct[i].TxPllClkSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + serializerCfg->txPllClkSel); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* set channel final divider */ + strIdx++; + if (serializerSetFct[i].TxRateBfSet != NULL) + { + recoveryAction = serializerSetFct[i].TxRateBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + txRateEncodedValue); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* set polarity */ + strIdx++; + if (serializerSetFct[i].TxPolarityBfSet != NULL) + { + recoveryAction = serializerSetFct[i].TxPolarityBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + serializerCfg->polarity); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* set precursor */ + strIdx++; + if (serializerSetFct[i].TxPrecursorBfSet != NULL) + { + recoveryAction = serializerSetFct[i].TxPrecursorBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + serializerCfg->precursor); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* set postcursor */ + strIdx++; + if (serializerSetFct[i].TxPostcursorBfSet != NULL) + { + recoveryAction = serializerSetFct[i].TxPostcursorBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + serializerCfg->postcursor); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* set differential control */ + strIdx++; + if (serializerSetFct[i].TxDiffControlBfSet != NULL) + { + recoveryAction = serializerSetFct[i].TxDiffControlBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + serializerCfg->diffCtrl); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + /* set 8b10b enable */ + strIdx++; + if (serializerSetFct[i].Tx8b10bEnableBfSet != NULL) + { + recoveryAction = serializerSetFct[i].Tx8b10bEnableBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + serializerCfg->encoder8b10bEnable); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + strIdx++; + /* clk out select */ + if (serializerSetFct[i].TxClkOutBfSet != NULL) + { + recoveryAction = serializerSetFct[i].TxClkOutBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + serializerCfg->txOutClkSel); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + strIdx++; + + /* bring channel out of power down */ + if (serializerSetFct[i].TxPowerdownBfSet != NULL) + { + recoveryAction = serializerSetFct[i].TxPowerdownBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + serializerCfg->powerDown); + serializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_SerializerCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_LaneSel_e laneSel, + adi_fpga9025_SerializerCfg_t* serializerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t txPllClkSelReadBack = 0; + uint8_t txRateEncodedValue = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + serializerCfg); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + char serializerErrStr[][64] = { + "Error reading channel 0 cpll ref clk", + "Error reading channel 0 tx pll clk sel", + "Error reading channel 0 tx rate (final divider)", + "Error reading channel 0 tx polarity", + "Error reading channel 0 tx precursor", + "Error reading channel 0 tx postcursor", + "Error reading channel 0 tx diffCtrl", + "Error reading channel 0 tx encoder8b10bEnable", + "Error setting channel 0 tx clk out", + "Error reading channel 0 tx powerDown" + }; + uint32_t laneNumPos = 22; + + typedef struct + { + int32_t (*CpllRefClkSelBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + + int32_t (*TxPllClkSelBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + + int32_t (*TxRateBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + + int32_t (*TxPolarityBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + + int32_t (*TxPrecursorBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + + int32_t (*TxPostcursorBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + + int32_t (*TxDiffControlBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + + int32_t (*Tx8b10bEnableBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + + int32_t (*TxClkOutBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + + int32_t (*TxPowerdownBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + } fpgaSerializerGet_t; + + fpgaSerializerGet_t serializerGetFct[] = { + { + .CpllRefClkSelBf = fpga9025_Jesd204PhyAds9Channel0CpllRefClkSelBfGet, + .TxPllClkSelBf = fpga9025_Jesd204PhyAds9Channel0TxPllClkSelBfGet, + .TxRateBf = fpga9025_Jesd204PhyAds9Channel0TxRateBfGet, + .TxPolarityBf = fpga9025_Jesd204PhyAds9Channel0TxPolarityBfGet, + .TxPrecursorBf = fpga9025_Jesd204PhyAds9Channel0TxPrecursorBfGet, + .TxPostcursorBf = fpga9025_Jesd204PhyAds9Channel0TxPostcursorBfGet, + .TxDiffControlBf = fpga9025_Jesd204PhyAds9Channel0TxDiffControlBfGet, + .Tx8b10bEnableBf = fpga9025_Jesd204PhyAds9Channel0Tx8b10bEnableBfGet, + .TxClkOutBf = fpga9025_Jesd204PhyAds9Channel0TxOutClkSelBfGet, + .TxPowerdownBf = fpga9025_Jesd204PhyAds9Channel0TxPowerdownBfGet + }, + { + .CpllRefClkSelBf = fpga9025_Jesd204PhyAds9Channel1CpllRefClkSelBfGet, + .TxPllClkSelBf = fpga9025_Jesd204PhyAds9Channel1TxPllClkSelBfGet, + .TxRateBf = fpga9025_Jesd204PhyAds9Channel1TxRateBfGet, + .TxPolarityBf = fpga9025_Jesd204PhyAds9Channel1TxPolarityBfGet, + .TxPrecursorBf = fpga9025_Jesd204PhyAds9Channel1TxPrecursorBfGet, + .TxPostcursorBf = fpga9025_Jesd204PhyAds9Channel1TxPostcursorBfGet, + .TxDiffControlBf = fpga9025_Jesd204PhyAds9Channel1TxDiffControlBfGet, + .Tx8b10bEnableBf = fpga9025_Jesd204PhyAds9Channel1Tx8b10bEnableBfGet, + .TxClkOutBf = fpga9025_Jesd204PhyAds9Channel1TxOutClkSelBfGet, + .TxPowerdownBf = fpga9025_Jesd204PhyAds9Channel1TxPowerdownBfGet + }, + { + .CpllRefClkSelBf = fpga9025_Jesd204PhyAds9Channel2CpllRefClkSelBfGet, + .TxPllClkSelBf = fpga9025_Jesd204PhyAds9Channel2TxPllClkSelBfGet, + .TxRateBf = fpga9025_Jesd204PhyAds9Channel2TxRateBfGet, + .TxPolarityBf = fpga9025_Jesd204PhyAds9Channel2TxPolarityBfGet, + .TxPrecursorBf = fpga9025_Jesd204PhyAds9Channel2TxPrecursorBfGet, + .TxPostcursorBf = fpga9025_Jesd204PhyAds9Channel2TxPostcursorBfGet, + .TxDiffControlBf = fpga9025_Jesd204PhyAds9Channel2TxDiffControlBfGet, + .Tx8b10bEnableBf = fpga9025_Jesd204PhyAds9Channel2Tx8b10bEnableBfGet, + .TxClkOutBf = fpga9025_Jesd204PhyAds9Channel2TxOutClkSelBfGet, + .TxPowerdownBf = fpga9025_Jesd204PhyAds9Channel2TxPowerdownBfGet + }, + { + .CpllRefClkSelBf = fpga9025_Jesd204PhyAds9Channel3CpllRefClkSelBfGet, + .TxPllClkSelBf = fpga9025_Jesd204PhyAds9Channel3TxPllClkSelBfGet, + .TxRateBf = fpga9025_Jesd204PhyAds9Channel3TxRateBfGet, + .TxPolarityBf = fpga9025_Jesd204PhyAds9Channel3TxPolarityBfGet, + .TxPrecursorBf = fpga9025_Jesd204PhyAds9Channel3TxPrecursorBfGet, + .TxPostcursorBf = fpga9025_Jesd204PhyAds9Channel3TxPostcursorBfGet, + .TxDiffControlBf = fpga9025_Jesd204PhyAds9Channel3TxDiffControlBfGet, + .Tx8b10bEnableBf = fpga9025_Jesd204PhyAds9Channel3Tx8b10bEnableBfGet, + .TxClkOutBf = fpga9025_Jesd204PhyAds9Channel3TxOutClkSelBfGet, + .TxPowerdownBf = fpga9025_Jesd204PhyAds9Channel3TxPowerdownBfGet + }, + { + .CpllRefClkSelBf = fpga9025_Jesd204PhyAds9Channel4CpllRefClkSelBfGet, + .TxPllClkSelBf = fpga9025_Jesd204PhyAds9Channel4TxPllClkSelBfGet, + .TxRateBf = fpga9025_Jesd204PhyAds9Channel4TxRateBfGet, + .TxPolarityBf = fpga9025_Jesd204PhyAds9Channel4TxPolarityBfGet, + .TxPrecursorBf = fpga9025_Jesd204PhyAds9Channel4TxPrecursorBfGet, + .TxPostcursorBf = fpga9025_Jesd204PhyAds9Channel4TxPostcursorBfGet, + .TxDiffControlBf = fpga9025_Jesd204PhyAds9Channel4TxDiffControlBfGet, + .Tx8b10bEnableBf = fpga9025_Jesd204PhyAds9Channel4Tx8b10bEnableBfGet, + .TxClkOutBf = fpga9025_Jesd204PhyAds9Channel4TxOutClkSelBfGet, + .TxPowerdownBf = fpga9025_Jesd204PhyAds9Channel4TxPowerdownBfGet + }, + { + .CpllRefClkSelBf = fpga9025_Jesd204PhyAds9Channel5CpllRefClkSelBfGet, + .TxPllClkSelBf = fpga9025_Jesd204PhyAds9Channel5TxPllClkSelBfGet, + .TxRateBf = fpga9025_Jesd204PhyAds9Channel5TxRateBfGet, + .TxPolarityBf = fpga9025_Jesd204PhyAds9Channel5TxPolarityBfGet, + .TxPrecursorBf = fpga9025_Jesd204PhyAds9Channel5TxPrecursorBfGet, + .TxPostcursorBf = fpga9025_Jesd204PhyAds9Channel5TxPostcursorBfGet, + .TxDiffControlBf = fpga9025_Jesd204PhyAds9Channel5TxDiffControlBfGet, + .Tx8b10bEnableBf = fpga9025_Jesd204PhyAds9Channel5Tx8b10bEnableBfGet, + .TxClkOutBf = fpga9025_Jesd204PhyAds9Channel5TxOutClkSelBfGet, + .TxPowerdownBf = fpga9025_Jesd204PhyAds9Channel5TxPowerdownBfGet + }, + { + .CpllRefClkSelBf = fpga9025_Jesd204PhyAds9Channel6CpllRefClkSelBfGet, + .TxPllClkSelBf = fpga9025_Jesd204PhyAds9Channel6TxPllClkSelBfGet, + .TxRateBf = fpga9025_Jesd204PhyAds9Channel6TxRateBfGet, + .TxPolarityBf = fpga9025_Jesd204PhyAds9Channel6TxPolarityBfGet, + .TxPrecursorBf = fpga9025_Jesd204PhyAds9Channel6TxPrecursorBfGet, + .TxPostcursorBf = fpga9025_Jesd204PhyAds9Channel6TxPostcursorBfGet, + .TxDiffControlBf = fpga9025_Jesd204PhyAds9Channel6TxDiffControlBfGet, + .Tx8b10bEnableBf = fpga9025_Jesd204PhyAds9Channel6Tx8b10bEnableBfGet, + .TxClkOutBf = fpga9025_Jesd204PhyAds9Channel6TxOutClkSelBfGet, + .TxPowerdownBf = fpga9025_Jesd204PhyAds9Channel6TxPowerdownBfGet + }, + { + .CpllRefClkSelBf = fpga9025_Jesd204PhyAds9Channel7CpllRefClkSelBfGet, + .TxPllClkSelBf = fpga9025_Jesd204PhyAds9Channel7TxPllClkSelBfGet, + .TxRateBf = fpga9025_Jesd204PhyAds9Channel7TxRateBfGet, + .TxPolarityBf = fpga9025_Jesd204PhyAds9Channel7TxPolarityBfGet, + .TxPrecursorBf = fpga9025_Jesd204PhyAds9Channel7TxPrecursorBfGet, + .TxPostcursorBf = fpga9025_Jesd204PhyAds9Channel7TxPostcursorBfGet, + .TxDiffControlBf = fpga9025_Jesd204PhyAds9Channel7TxDiffControlBfGet, + .Tx8b10bEnableBf = fpga9025_Jesd204PhyAds9Channel7Tx8b10bEnableBfGet, + .TxClkOutBf = fpga9025_Jesd204PhyAds9Channel7TxOutClkSelBfGet, + .TxPowerdownBf = fpga9025_Jesd204PhyAds9Channel7TxPowerdownBfGet + } + }; + uint32_t laneIdx = 0; + + switch (laneSel) + { + case ADI_FPGA9025_LANE_0: + laneIdx = 0; + break; + case ADI_FPGA9025_LANE_1: + laneIdx = 1; + break; + case ADI_FPGA9025_LANE_2: + laneIdx = 2; + break; + case ADI_FPGA9025_LANE_3: + laneIdx = 3; + break; + case ADI_FPGA9025_LANE_4: + laneIdx = 4; + break; + case ADI_FPGA9025_LANE_5: + laneIdx = 5; + break; + case ADI_FPGA9025_LANE_6: + laneIdx = 6; + break; + case ADI_FPGA9025_LANE_7: + laneIdx = 7; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + laneSelMask, + "Invalid lane selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + /* Get cpll ref clk */ + if (serializerGetFct[laneIdx].CpllRefClkSelBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].CpllRefClkSelBf(device, + FPGA9025_BF_ADS9_JESD_PHY, + &serializerCfg->cpllRefClkSel); + serializerErrStr[0][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get channel clk */ + if (serializerGetFct[laneIdx].TxPllClkSelBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].TxPllClkSelBf(device, + FPGA9025_BF_ADS9_JESD_PHY, + &txPllClkSelReadBack); + serializerErrStr[1][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[1]); + ADI_ERROR_RETURN(device->common.error.newAction); + serializerCfg->txPllClkSel = (adi_fpga9025_LaneClkSel_e)txPllClkSelReadBack; + } + + /* Get channel final divider */ + if (serializerGetFct[laneIdx].TxRateBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].TxRateBf(device, + FPGA9025_BF_ADS9_JESD_PHY, + &txRateEncodedValue); + serializerErrStr[2][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[2]); + ADI_ERROR_RETURN(device->common.error.newAction); + if (txRateEncodedValue > 5) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Invalid tx rate (final divider) value read from FPGA"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + serializerCfg->rate = (1 << txRateEncodedValue) / 2; + } + + /* Get polarity */ + if (serializerGetFct[laneIdx].TxPolarityBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].TxPolarityBf(device, + FPGA9025_BF_ADS9_JESD_PHY, + &serializerCfg->polarity); + serializerErrStr[3][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[3]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get precursor */ + if (serializerGetFct[laneIdx].TxPrecursorBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].TxPrecursorBf(device, + FPGA9025_BF_ADS9_JESD_PHY, + &serializerCfg->precursor); + serializerErrStr[4][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[4]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get postcursor */ + if (serializerGetFct[laneIdx].TxPostcursorBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].TxPostcursorBf(device, + FPGA9025_BF_ADS9_JESD_PHY, + &serializerCfg->postcursor); + serializerErrStr[5][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[5]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get differential control */ + if (serializerGetFct[laneIdx].TxDiffControlBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].TxDiffControlBf(device, + FPGA9025_BF_ADS9_JESD_PHY, + &serializerCfg->diffCtrl); + serializerErrStr[6][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[6]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get 8b10b enable */ + if (serializerGetFct[laneIdx].Tx8b10bEnableBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].Tx8b10bEnableBf(device, + FPGA9025_BF_ADS9_JESD_PHY, + &serializerCfg->encoder8b10bEnable); + serializerErrStr[7][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[7]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get power down status */ + if (serializerGetFct[laneIdx].TxClkOutBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].TxClkOutBf(device, + FPGA9025_BF_ADS9_JESD_PHY, + &serializerCfg->txOutClkSel); + serializerErrStr[8][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[8]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get power down status */ + if (serializerGetFct[laneIdx].TxPowerdownBf != NULL) + { + recoveryAction = serializerGetFct[laneIdx].TxPowerdownBf(device, + FPGA9025_BF_ADS9_JESD_PHY, + &serializerCfg->powerDown); + serializerErrStr[9][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[9]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_SerializerResetSet(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + uint8_t resetVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + char serializerErrStr[][64] = { + "Error resetting channel 0 tx" + }; + uint32_t laneNumPos = 24; + + typedef struct + { + int32_t (*TxResetBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + } fpgaTxResetSet_t; + + fpgaTxResetSet_t txResetSetFct[] = { + {.TxResetBfSet = fpga9025_Jesd204PhyAds9Channel0TxResetBfSet}, + {.TxResetBfSet = fpga9025_Jesd204PhyAds9Channel1TxResetBfSet}, + {.TxResetBfSet = fpga9025_Jesd204PhyAds9Channel2TxResetBfSet}, + {.TxResetBfSet = fpga9025_Jesd204PhyAds9Channel3TxResetBfSet}, + {.TxResetBfSet = fpga9025_Jesd204PhyAds9Channel4TxResetBfSet}, + {.TxResetBfSet = fpga9025_Jesd204PhyAds9Channel5TxResetBfSet}, + {.TxResetBfSet = fpga9025_Jesd204PhyAds9Channel6TxResetBfSet}, + {.TxResetBfSet = fpga9025_Jesd204PhyAds9Channel7TxResetBfSet} + }; + int32_t i = 0; + int32_t selectBit = 0; + int32_t loopCnt = sizeof(txResetSetFct) / sizeof(fpgaTxResetSet_t); + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_fpga9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + for (i = 0; i < loopCnt; i++) + { + if (laneSelMask == 0) + { + break; /* Already processed all mask bits. */ + } + + selectBit = 1 << i; /* process each bit from right most to left most. */ + + if ((laneSelMask & selectBit) == 0) + { + continue; /* If current bit mask is not set then go to next bit mask */ + } + + laneSelMask &= ~selectBit; /* mark off the select bit that is currently processing. */ + + if (txResetSetFct[i].TxResetBfSet != NULL) + { + recoveryAction = txResetSetFct[i].TxResetBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (resetVal & 0x01)); + serializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_SerializerResetDoneGet(adi_fpga9025_Device_t* device, + uint8_t* txResetDone) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t resetBitRead = 0; + + char serializerErrStr[][64] = { + "Error resetting channel 0 tx" + }; + uint32_t laneNumPos = 24; + + typedef struct + { + int32_t (*TxResetBfGet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + } fpgaTxResetSet_t; + + fpgaTxResetSet_t txResetGetFct[] = { + {.TxResetBfGet = fpga9025_Jesd204PhyAds9Channel0TxResetDoneBfGet}, + {.TxResetBfGet = fpga9025_Jesd204PhyAds9Channel1TxResetDoneBfGet}, + {.TxResetBfGet = fpga9025_Jesd204PhyAds9Channel2TxResetDoneBfGet}, + {.TxResetBfGet = fpga9025_Jesd204PhyAds9Channel3TxResetDoneBfGet}, + {.TxResetBfGet = fpga9025_Jesd204PhyAds9Channel4TxResetDoneBfGet}, + {.TxResetBfGet = fpga9025_Jesd204PhyAds9Channel5TxResetDoneBfGet}, + {.TxResetBfGet = fpga9025_Jesd204PhyAds9Channel6TxResetDoneBfGet}, + {.TxResetBfGet = fpga9025_Jesd204PhyAds9Channel7TxResetDoneBfGet} + }; + int32_t i = 0; + int32_t loopCnt = sizeof(txResetGetFct) / sizeof(fpgaTxResetSet_t); + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + txResetDone); + +#if ADI_fpga9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + *txResetDone = 0; + + for (i = 0; i < loopCnt; i++) + { + if (txResetGetFct[i].TxResetBfGet != NULL) + { + recoveryAction = txResetGetFct[i].TxResetBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &resetBitRead); + *txResetDone |= (uint8_t)(resetBitRead << i); + serializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_LaneCpllPdSet(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + uint8_t pdVal) +{ + UNUSED_PARA(device); + UNUSED_PARA(laneSelMask); + UNUSED_PARA(pdVal); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + return recoveryAction; +} + +int32_t adi_fpga9025_DeserializerCfgSet(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + adi_fpga9025_DeserializerCfg_t* deserializerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxRateEncodedValue = 0; + + int32_t i = 0; + int32_t selectBit = 0; + + char deserializerErrStr[][64] = { + "Error setting channel 0 rx pll clk sel", + "Error setting channel 0 rx rate (final divider)", + "Error setting channel 0 rx polarity", + "Error setting channel 0 rx encoder8b10bEnable", + "Error setting channel 0 rx DFE/LPMr", + "Error setting channel 0 rx clock out", + "Error setting channel 0 rx power down" + }; + uint32_t laneNumPos = 22; + + typedef struct + { + int32_t (*RxPllClkSelBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*RxRateBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*RxPolarityBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*Rx8b10bEnableBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*RxDfeLpmEnBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*RxOutClkSelBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + + int32_t (*RxPowerdownBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + } fpgaDeserializerSet_t; + + fpgaDeserializerSet_t deserializerSetFct[] = { + { + .RxPllClkSelBfSet = fpga9025_Jesd204PhyAds9Channel0RxPllClkSelBfSet, + .RxRateBfSet = fpga9025_Jesd204PhyAds9Channel0RxRateBfSet, + .RxPolarityBfSet = fpga9025_Jesd204PhyAds9Channel0RxPolarityBfSet, + .Rx8b10bEnableBfSet = fpga9025_Jesd204PhyAds9Channel0Rx8b10bEnableBfSet, + .RxDfeLpmEnBfSet = fpga9025_Jesd204PhyAds9Channel0RxDfeLpmEnBfSet, + .RxOutClkSelBfSet = fpga9025_Jesd204PhyAds9Channel0RxOutClkSelBfSet, + .RxPowerdownBfSet = fpga9025_Jesd204PhyAds9Channel0RxPowerdownBfSet + }, + { + .RxPllClkSelBfSet = fpga9025_Jesd204PhyAds9Channel1RxPllClkSelBfSet, + .RxRateBfSet = fpga9025_Jesd204PhyAds9Channel1RxRateBfSet, + .RxPolarityBfSet = fpga9025_Jesd204PhyAds9Channel1RxPolarityBfSet, + .Rx8b10bEnableBfSet = fpga9025_Jesd204PhyAds9Channel1Rx8b10bEnableBfSet, + .RxDfeLpmEnBfSet = fpga9025_Jesd204PhyAds9Channel1RxDfeLpmEnBfSet, + .RxOutClkSelBfSet = fpga9025_Jesd204PhyAds9Channel1RxOutClkSelBfSet, + .RxPowerdownBfSet = fpga9025_Jesd204PhyAds9Channel1RxPowerdownBfSet + }, + { + .RxPllClkSelBfSet = fpga9025_Jesd204PhyAds9Channel2RxPllClkSelBfSet, + .RxRateBfSet = fpga9025_Jesd204PhyAds9Channel2RxRateBfSet, + .RxPolarityBfSet = fpga9025_Jesd204PhyAds9Channel2RxPolarityBfSet, + .Rx8b10bEnableBfSet = fpga9025_Jesd204PhyAds9Channel2Rx8b10bEnableBfSet, + .RxDfeLpmEnBfSet = fpga9025_Jesd204PhyAds9Channel2RxDfeLpmEnBfSet, + .RxOutClkSelBfSet = fpga9025_Jesd204PhyAds9Channel2RxOutClkSelBfSet, + .RxPowerdownBfSet = fpga9025_Jesd204PhyAds9Channel2RxPowerdownBfSet + }, + { + .RxPllClkSelBfSet = fpga9025_Jesd204PhyAds9Channel3RxPllClkSelBfSet, + .RxRateBfSet = fpga9025_Jesd204PhyAds9Channel3RxRateBfSet, + .RxPolarityBfSet = fpga9025_Jesd204PhyAds9Channel3RxPolarityBfSet, + .Rx8b10bEnableBfSet = fpga9025_Jesd204PhyAds9Channel3Rx8b10bEnableBfSet, + .RxDfeLpmEnBfSet = fpga9025_Jesd204PhyAds9Channel3RxDfeLpmEnBfSet, + .RxOutClkSelBfSet = fpga9025_Jesd204PhyAds9Channel3RxOutClkSelBfSet, + .RxPowerdownBfSet = fpga9025_Jesd204PhyAds9Channel3RxPowerdownBfSet + }, + { + .RxPllClkSelBfSet = fpga9025_Jesd204PhyAds9Channel4RxPllClkSelBfSet, + .RxRateBfSet = fpga9025_Jesd204PhyAds9Channel4RxRateBfSet, + .RxPolarityBfSet = fpga9025_Jesd204PhyAds9Channel4RxPolarityBfSet, + .Rx8b10bEnableBfSet = fpga9025_Jesd204PhyAds9Channel4Rx8b10bEnableBfSet, + .RxDfeLpmEnBfSet = fpga9025_Jesd204PhyAds9Channel4RxDfeLpmEnBfSet, + .RxOutClkSelBfSet = fpga9025_Jesd204PhyAds9Channel4RxOutClkSelBfSet, + .RxPowerdownBfSet = fpga9025_Jesd204PhyAds9Channel4RxPowerdownBfSet + }, + { + .RxPllClkSelBfSet = fpga9025_Jesd204PhyAds9Channel5RxPllClkSelBfSet, + .RxRateBfSet = fpga9025_Jesd204PhyAds9Channel5RxRateBfSet, + .RxPolarityBfSet = fpga9025_Jesd204PhyAds9Channel5RxPolarityBfSet, + .Rx8b10bEnableBfSet = fpga9025_Jesd204PhyAds9Channel5Rx8b10bEnableBfSet, + .RxDfeLpmEnBfSet = fpga9025_Jesd204PhyAds9Channel5RxDfeLpmEnBfSet, + .RxOutClkSelBfSet = fpga9025_Jesd204PhyAds9Channel5RxOutClkSelBfSet, + .RxPowerdownBfSet = fpga9025_Jesd204PhyAds9Channel5RxPowerdownBfSet + }, + { + .RxPllClkSelBfSet = fpga9025_Jesd204PhyAds9Channel6RxPllClkSelBfSet, + .RxRateBfSet = fpga9025_Jesd204PhyAds9Channel6RxRateBfSet, + .RxPolarityBfSet = fpga9025_Jesd204PhyAds9Channel6RxPolarityBfSet, + .Rx8b10bEnableBfSet = fpga9025_Jesd204PhyAds9Channel6Rx8b10bEnableBfSet, + .RxDfeLpmEnBfSet = fpga9025_Jesd204PhyAds9Channel6RxDfeLpmEnBfSet, + .RxOutClkSelBfSet = fpga9025_Jesd204PhyAds9Channel6RxOutClkSelBfSet, + .RxPowerdownBfSet = fpga9025_Jesd204PhyAds9Channel6RxPowerdownBfSet + }, + { + .RxPllClkSelBfSet = fpga9025_Jesd204PhyAds9Channel7RxPllClkSelBfSet, + .RxRateBfSet = fpga9025_Jesd204PhyAds9Channel7RxRateBfSet, + .RxPolarityBfSet = fpga9025_Jesd204PhyAds9Channel7RxPolarityBfSet, + .Rx8b10bEnableBfSet = fpga9025_Jesd204PhyAds9Channel7Rx8b10bEnableBfSet, + .RxDfeLpmEnBfSet = fpga9025_Jesd204PhyAds9Channel7RxDfeLpmEnBfSet, + .RxOutClkSelBfSet = fpga9025_Jesd204PhyAds9Channel7RxOutClkSelBfSet, + .RxPowerdownBfSet = fpga9025_Jesd204PhyAds9Channel7RxPowerdownBfSet + } + }; + + uint32_t strIdx = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + deserializerCfg); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + switch (deserializerCfg->rate) + { + case 0: + rxRateEncodedValue = 0; + break; + case 1: + rxRateEncodedValue = 1; + break; + case 2: + rxRateEncodedValue = 2; + break; + case 4: + rxRateEncodedValue = 3; + break; + case 8: + rxRateEncodedValue = 4; + break; + case 16: + rxRateEncodedValue = 5; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deserializerCfg->rate, + "Invalid rx rate (final divider) value"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + for (i = 0; i < ADI_FPGA9025_NUM_LANES; i++) + { + if (laneSelMask == 0) + { + break; /* Already processed all mask bits. */ + } + + selectBit = 1 << i; /* process each bit from right most to left most. */ + + if ((laneSelMask & selectBit) == 0) + { + continue; /* If current bit mask is not set then go to next bit mask */ + } + + laneSelMask &= ~selectBit; /* mark off the select bit that is currently processing. */ + + /* set channel clk */ + strIdx = 0; + if (deserializerSetFct[i].RxPllClkSelBfSet != NULL) + { + recoveryAction = deserializerSetFct[i].RxPllClkSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + deserializerCfg->rxPllClkSel); + deserializerErrStr[strIdx][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)deserializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* set channel final divider */ + strIdx++; + if (deserializerSetFct[i].RxRateBfSet != NULL) + { + recoveryAction = deserializerSetFct[i].RxRateBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + rxRateEncodedValue); + deserializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)deserializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* set polarity */ + strIdx++; + if (deserializerSetFct[i].RxPolarityBfSet != NULL) + { + recoveryAction = deserializerSetFct[i].RxPolarityBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + deserializerCfg->polarity); + deserializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)deserializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* set 8b10b enable */ + strIdx++; + if (deserializerSetFct[i].Rx8b10bEnableBfSet != NULL) + { + recoveryAction = deserializerSetFct[i].Rx8b10bEnableBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + deserializerCfg->encoder8b10bEnable); + deserializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)deserializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* set dfe_lpm enable */ + strIdx++; + if (deserializerSetFct[i].RxDfeLpmEnBfSet != NULL) + { + recoveryAction = deserializerSetFct[i].RxDfeLpmEnBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + deserializerCfg->rxDfeLpmEn); + deserializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)deserializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* set rx clk out */ + strIdx++; + if (deserializerSetFct[i].RxOutClkSelBfSet != NULL) + { + recoveryAction = deserializerSetFct[i].RxOutClkSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + deserializerCfg->rxOutClkSel); + deserializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)deserializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* bring channel out of power down */ + strIdx++; + if (deserializerSetFct[i].RxPowerdownBfSet != NULL) + { + recoveryAction = deserializerSetFct[i].RxPowerdownBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + deserializerCfg->powerDown); + deserializerErrStr[strIdx][laneNumPos] = i + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)deserializerErrStr[strIdx]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_DeserializerCfgGet(adi_fpga9025_Device_t* device, + const adi_fpga9025_LaneSel_e laneSel, + adi_fpga9025_DeserializerCfg_t* deserializerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t rxPllClkSelReadBack = 0; + uint8_t rxRateEncodedValue = 0; + + char deserializerErrStr[][64] = { + "Error reading channel 0 rx pll clk sel", + "Error reading channel 0 rx rate (final divider)", + "Error reading channel 0 rx polarity", + "Error reading channel 0 rx encoder8b10bEnable", + "Error reading channel 0 rx DFE/LPM", + "Error setting channel 0 rx clock out", + "Error reading channel 0 rx power down" + }; + uint32_t laneNumPos = 22; + + typedef struct + { + int32_t (*RxPllClkSelBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + + int32_t (*RxRateBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + + int32_t (*RxPolarityBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + + int32_t (*Rx8b10bEnableBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + + int32_t (*RxDfeLpmEnBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + + int32_t (*RxOutClkSelBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + + int32_t (*RxPowerdownBf)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + } fpgaDeserializerGet_t; + + fpgaDeserializerGet_t deserializerGetFct[] = { + { + .RxPllClkSelBf = fpga9025_Jesd204PhyAds9Channel0RxPllClkSelBfGet, + .RxRateBf = fpga9025_Jesd204PhyAds9Channel0RxRateBfGet, + .RxPolarityBf = fpga9025_Jesd204PhyAds9Channel0RxPolarityBfGet, + .Rx8b10bEnableBf = fpga9025_Jesd204PhyAds9Channel0Rx8b10bEnableBfGet, + .RxDfeLpmEnBf = fpga9025_Jesd204PhyAds9Channel0RxDfeLpmEnBfGet, + .RxOutClkSelBf = fpga9025_Jesd204PhyAds9Channel0RxOutClkSelBfGet, + .RxPowerdownBf = fpga9025_Jesd204PhyAds9Channel0RxPowerdownBfGet + }, + { + .RxPllClkSelBf = fpga9025_Jesd204PhyAds9Channel1RxPllClkSelBfGet, + .RxRateBf = fpga9025_Jesd204PhyAds9Channel1RxRateBfGet, + .RxPolarityBf = fpga9025_Jesd204PhyAds9Channel1RxPolarityBfGet, + .Rx8b10bEnableBf = fpga9025_Jesd204PhyAds9Channel1Rx8b10bEnableBfGet, + .RxDfeLpmEnBf = fpga9025_Jesd204PhyAds9Channel1RxDfeLpmEnBfGet, + .RxOutClkSelBf = fpga9025_Jesd204PhyAds9Channel1RxOutClkSelBfGet, + .RxPowerdownBf = fpga9025_Jesd204PhyAds9Channel1RxPowerdownBfGet + }, + { + .RxPllClkSelBf = fpga9025_Jesd204PhyAds9Channel2RxPllClkSelBfGet, + .RxRateBf = fpga9025_Jesd204PhyAds9Channel2RxRateBfGet, + .RxPolarityBf = fpga9025_Jesd204PhyAds9Channel2RxPolarityBfGet, + .Rx8b10bEnableBf = fpga9025_Jesd204PhyAds9Channel2Rx8b10bEnableBfGet, + .RxDfeLpmEnBf = fpga9025_Jesd204PhyAds9Channel2RxDfeLpmEnBfGet, + .RxOutClkSelBf = fpga9025_Jesd204PhyAds9Channel2RxOutClkSelBfGet, + .RxPowerdownBf = fpga9025_Jesd204PhyAds9Channel2RxPowerdownBfGet + }, + { + .RxPllClkSelBf = fpga9025_Jesd204PhyAds9Channel3RxPllClkSelBfGet, + .RxRateBf = fpga9025_Jesd204PhyAds9Channel3RxRateBfGet, + .RxPolarityBf = fpga9025_Jesd204PhyAds9Channel3RxPolarityBfGet, + .Rx8b10bEnableBf = fpga9025_Jesd204PhyAds9Channel3Rx8b10bEnableBfGet, + .RxDfeLpmEnBf = fpga9025_Jesd204PhyAds9Channel3RxDfeLpmEnBfGet, + .RxOutClkSelBf = fpga9025_Jesd204PhyAds9Channel3RxOutClkSelBfGet, + .RxPowerdownBf = fpga9025_Jesd204PhyAds9Channel3RxPowerdownBfGet + }, + { + .RxPllClkSelBf = fpga9025_Jesd204PhyAds9Channel4RxPllClkSelBfGet, + .RxRateBf = fpga9025_Jesd204PhyAds9Channel4RxRateBfGet, + .RxPolarityBf = fpga9025_Jesd204PhyAds9Channel4RxPolarityBfGet, + .Rx8b10bEnableBf = fpga9025_Jesd204PhyAds9Channel4Rx8b10bEnableBfGet, + .RxDfeLpmEnBf = fpga9025_Jesd204PhyAds9Channel4RxDfeLpmEnBfGet, + .RxOutClkSelBf = fpga9025_Jesd204PhyAds9Channel4RxOutClkSelBfGet, + .RxPowerdownBf = fpga9025_Jesd204PhyAds9Channel4RxPowerdownBfGet + }, + { + .RxPllClkSelBf = fpga9025_Jesd204PhyAds9Channel5RxPllClkSelBfGet, + .RxRateBf = fpga9025_Jesd204PhyAds9Channel5RxRateBfGet, + .RxPolarityBf = fpga9025_Jesd204PhyAds9Channel5RxPolarityBfGet, + .Rx8b10bEnableBf = fpga9025_Jesd204PhyAds9Channel5Rx8b10bEnableBfGet, + .RxDfeLpmEnBf = fpga9025_Jesd204PhyAds9Channel5RxDfeLpmEnBfGet, + .RxOutClkSelBf = fpga9025_Jesd204PhyAds9Channel5RxOutClkSelBfGet, + .RxPowerdownBf = fpga9025_Jesd204PhyAds9Channel5RxPowerdownBfGet + }, + { + .RxPllClkSelBf = fpga9025_Jesd204PhyAds9Channel6RxPllClkSelBfGet, + .RxRateBf = fpga9025_Jesd204PhyAds9Channel6RxRateBfGet, + .RxPolarityBf = fpga9025_Jesd204PhyAds9Channel6RxPolarityBfGet, + .Rx8b10bEnableBf = fpga9025_Jesd204PhyAds9Channel6Rx8b10bEnableBfGet, + .RxDfeLpmEnBf = fpga9025_Jesd204PhyAds9Channel6RxDfeLpmEnBfGet, + .RxOutClkSelBf = fpga9025_Jesd204PhyAds9Channel6RxOutClkSelBfGet, + .RxPowerdownBf = fpga9025_Jesd204PhyAds9Channel6RxPowerdownBfGet + }, + { + .RxPllClkSelBf = fpga9025_Jesd204PhyAds9Channel7RxPllClkSelBfGet, + .RxRateBf = fpga9025_Jesd204PhyAds9Channel7RxRateBfGet, + .RxPolarityBf = fpga9025_Jesd204PhyAds9Channel7RxPolarityBfGet, + .Rx8b10bEnableBf = fpga9025_Jesd204PhyAds9Channel7Rx8b10bEnableBfGet, + .RxDfeLpmEnBf = fpga9025_Jesd204PhyAds9Channel7RxDfeLpmEnBfGet, + .RxOutClkSelBf = fpga9025_Jesd204PhyAds9Channel7RxOutClkSelBfGet, + .RxPowerdownBf = fpga9025_Jesd204PhyAds9Channel7RxPowerdownBfGet + } + }; + uint32_t laneIdx = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + deserializerCfg); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + switch (laneSel) + { + case ADI_FPGA9025_LANE_0: + laneIdx = 0; + break; + case ADI_FPGA9025_LANE_1: + laneIdx = 1; + break; + case ADI_FPGA9025_LANE_2: + laneIdx = 2; + break; + case ADI_FPGA9025_LANE_3: + laneIdx = 3; + break; + case ADI_FPGA9025_LANE_4: + laneIdx = 4; + break; + case ADI_FPGA9025_LANE_5: + laneIdx = 5; + break; + case ADI_FPGA9025_LANE_6: + laneIdx = 6; + break; + case ADI_FPGA9025_LANE_7: + laneIdx = 7; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + laneSel, + "Invalid lane selection"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + /* Get channel clk */ + if (deserializerGetFct[laneIdx].RxPllClkSelBf != NULL) + { + recoveryAction = deserializerGetFct[laneIdx].RxPllClkSelBf(device, + FPGA9025_BF_ADS9_JESD_PHY, + &rxPllClkSelReadBack); + deserializerCfg->rxPllClkSel = (adi_fpga9025_LaneClkSel_e)rxPllClkSelReadBack; + deserializerErrStr[0][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)deserializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get channel final divider */ + if (deserializerGetFct[laneIdx].RxRateBf != NULL) + { + recoveryAction = deserializerGetFct[laneIdx].RxRateBf(device, + FPGA9025_BF_ADS9_JESD_PHY, + &rxRateEncodedValue); + deserializerErrStr[1][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)deserializerErrStr[1]); + ADI_ERROR_RETURN(device->common.error.newAction); + if (rxRateEncodedValue > 5) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Invalid rx rate (final divider) value read from FPGA"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + deserializerCfg->rate = (1 << rxRateEncodedValue) / 2; + } + + /* Get polarity */ + if (deserializerGetFct[laneIdx].RxPolarityBf != NULL) + { + recoveryAction = deserializerGetFct[laneIdx].RxPolarityBf(device, + FPGA9025_BF_ADS9_JESD_PHY, + &deserializerCfg->polarity); + deserializerErrStr[2][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)deserializerErrStr[2]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Get 8b10b enable */ + if (deserializerGetFct[laneIdx].Rx8b10bEnableBf != NULL) + { + recoveryAction = deserializerGetFct[laneIdx].Rx8b10bEnableBf(device, + FPGA9025_BF_ADS9_JESD_PHY, + &deserializerCfg->encoder8b10bEnable); + deserializerErrStr[3][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)deserializerErrStr[3]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* set dfe_lpm enable */ + if (deserializerGetFct[laneIdx].RxDfeLpmEnBf != NULL) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel0RxDfeLpmEnBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &deserializerCfg->rxDfeLpmEn); + deserializerErrStr[4][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)deserializerErrStr[4]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* reading rx clk out */ + if (deserializerGetFct[laneIdx].RxOutClkSelBf != NULL) + { + recoveryAction = deserializerGetFct[laneIdx].RxOutClkSelBf(device, + FPGA9025_BF_ADS9_JESD_PHY, + &deserializerCfg->rxOutClkSel); + deserializerErrStr[5][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)deserializerErrStr[5]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* bring channel out of power down */ + if (deserializerGetFct[laneIdx].RxPowerdownBf != NULL) + { + recoveryAction = deserializerGetFct[laneIdx].RxPowerdownBf(device, + FPGA9025_BF_ADS9_JESD_PHY, + &deserializerCfg->powerDown); + deserializerErrStr[6][laneNumPos] = laneIdx + 48; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)deserializerErrStr[6]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_DeserializerResetSet(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + uint8_t resetVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + char deserializerErrStr[][64] = { + "Error resetting channel 0 Rx" + }; + uint32_t laneNumPos = 24; + + typedef struct + { + int32_t (*RxResetBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t ); + } fpgaRxResetSet_t; + + fpgaRxResetSet_t RxResetSetFct[] = { + {.RxResetBfSet = fpga9025_Jesd204PhyAds9Channel0RxResetBfSet}, + {.RxResetBfSet = fpga9025_Jesd204PhyAds9Channel1RxResetBfSet}, + {.RxResetBfSet = fpga9025_Jesd204PhyAds9Channel2RxResetBfSet}, + {.RxResetBfSet = fpga9025_Jesd204PhyAds9Channel3RxResetBfSet}, + {.RxResetBfSet = fpga9025_Jesd204PhyAds9Channel4RxResetBfSet}, + {.RxResetBfSet = fpga9025_Jesd204PhyAds9Channel5RxResetBfSet}, + {.RxResetBfSet = fpga9025_Jesd204PhyAds9Channel6RxResetBfSet}, + {.RxResetBfSet = fpga9025_Jesd204PhyAds9Channel7RxResetBfSet} + }; + int32_t i = 0; + int32_t selectBit = 0; + int32_t loopCnt = sizeof(RxResetSetFct) / sizeof(fpgaRxResetSet_t); + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_fpga9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + for (i = 0; i < loopCnt; i++) + { + if (laneSelMask == 0) + { + break; /* Already processed all mask bits. */ + } + + selectBit = 1 << i; /* process each bit from right most to left most. */ + + if ((laneSelMask & selectBit) == 0) + { + continue; /* If current bit mask is not set then go to next bit mask */ + } + + laneSelMask &= ~selectBit; /* mark off the select bit that is currently processing. */ + + if (RxResetSetFct[i].RxResetBfSet != NULL) + { + recoveryAction = RxResetSetFct[i].RxResetBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (resetVal & 0x01)); + deserializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)deserializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_DeserializerResetDoneGet(adi_fpga9025_Device_t* device, + uint8_t* rxResetDone) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t resetBitRead = 0; + + char deserializerErrStr[][64] = { + "Error resetting channel 0 rx" + }; + uint32_t laneNumPos = 24; + + typedef struct + { + int32_t (*RxResetBfGet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204PhyAds9ChanAddr_e baseAddr, + uint8_t* ); + } fpgaRxResetSet_t; + + fpgaRxResetSet_t rxResetGetFct[] = { + {.RxResetBfGet = fpga9025_Jesd204PhyAds9Channel0RxResetDoneBfGet}, + {.RxResetBfGet = fpga9025_Jesd204PhyAds9Channel1RxResetDoneBfGet}, + {.RxResetBfGet = fpga9025_Jesd204PhyAds9Channel2RxResetDoneBfGet}, + {.RxResetBfGet = fpga9025_Jesd204PhyAds9Channel3RxResetDoneBfGet}, + {.RxResetBfGet = fpga9025_Jesd204PhyAds9Channel4RxResetDoneBfGet}, + {.RxResetBfGet = fpga9025_Jesd204PhyAds9Channel5RxResetDoneBfGet}, + {.RxResetBfGet = fpga9025_Jesd204PhyAds9Channel6RxResetDoneBfGet}, + {.RxResetBfGet = fpga9025_Jesd204PhyAds9Channel7RxResetDoneBfGet} + }; + int32_t i = 0; + int32_t loopCnt = sizeof(rxResetGetFct) / sizeof(fpgaRxResetSet_t); + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + rxResetDone); + +#if ADI_fpga9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); +#endif + + *rxResetDone = 0; + + for (i = 0; i < loopCnt; i++) + { + if (rxResetGetFct[i].RxResetBfGet != NULL) + { + recoveryAction = rxResetGetFct[i].RxResetBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &resetBitRead); + *rxResetDone |= (uint8_t)(resetBitRead << i); + deserializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)deserializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_DeframerCfgSet(adi_fpga9025_Device_t* device, + uint32_t deframerSelMask, + adi_fpga9025_DeframerCfg_t* deframerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + deframerCfg); + + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID) + { + recoveryAction = fpga9025_Jesd204BDeframerCfgSet(device, + deframerSelMask, + deframerCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + recoveryAction = fpga9025_Jesd204CDeframerCfgSet(device, + deframerSelMask, + deframerCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_DeframerCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_DeframerSel_e deframerSel, + adi_fpga9025_DeframerCfg_t* deframerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + deframerCfg); + + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID) + { + recoveryAction = fpga9025_Jesd204BDeframerCfgGet(device, + deframerSel, + deframerCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + recoveryAction = fpga9025_Jesd204CDeframerCfgGet(device, + deframerSel, + deframerCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_DeframerResetGet(adi_fpga9025_Device_t* device, + uint32_t deframerSelMask, + uint8_t* resetBits) +{ + UNUSED_PARA(device); + UNUSED_PARA(deframerSelMask); + UNUSED_PARA(resetBits); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + // //uint8_t resetGet = 0; + // + //#if ADI_FPGA9025_VERBOSE > 0 + // ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + //#endif + // + return recoveryAction; +} + +int32_t adi_fpga9025_FramerCfgSet(adi_fpga9025_Device_t* device, + uint8_t framerSelMask, + adi_fpga9025_FramerCfg_t* framerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + framerCfg); + + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID) + { + recoveryAction = fpga9025_Jesd204BFramerCfgSet(device, + framerSelMask, + framerCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + recoveryAction = fpga9025_Jesd204CFramerCfgSet(device, + framerSelMask, + framerCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_FramerCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_FramerSel_e framerSel, + adi_fpga9025_FramerCfg_t* framerCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + framerCfg); + + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID) + { + recoveryAction = fpga9025_Jesd204BFramerCfgGet(device, + framerSel, + framerCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + recoveryAction = fpga9025_Jesd204CFramerCfgGet(device, + framerSel, + framerCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_FramerResetGet(adi_fpga9025_Device_t* device, + uint32_t framerSelMask, + uint8_t* resetBits) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + resetBits); + + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID) + { + recoveryAction = fpga9025_Jesd204BFramerResetGet(device, + framerSelMask, + resetBits); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + recoveryAction = fpga9025_Jesd204CFramerResetGet(device, + framerSelMask, + resetBits); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_TxLaneXBarCfgSet(adi_fpga9025_Device_t* device, + adi_fpga9025_FramerSel_e framerSel, + uint8_t* laneXBar) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfJesd204TxLaneXbarChanAddr_e baseAddr = FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + laneXBar); + + /* Set correct addresses for the framer selected */ + if (framerSel == ADI_FPGA9025_FRAMER_0) + { + baseAddr = FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0; + } + else if (framerSel == ADI_FPGA9025_FRAMER_1) + { + baseAddr = FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Invalid framer selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + recoveryAction = fpga9025_Jesd204TxLaneXbarLane0SelectBfSet(device, + baseAddr, + laneXBar[0]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 0 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204TxLaneXbarLane1SelectBfSet(device, + baseAddr, + laneXBar[1]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 1 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204TxLaneXbarLane2SelectBfSet(device, + baseAddr, + laneXBar[2]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 2 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204TxLaneXbarLane3SelectBfSet(device, + baseAddr, + laneXBar[3]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 3 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204TxLaneXbarLane4SelectBfSet(device, + baseAddr, + laneXBar[4]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 4 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204TxLaneXbarLane5SelectBfSet(device, + baseAddr, + laneXBar[5]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 5 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204TxLaneXbarLane6SelectBfSet(device, + baseAddr, + laneXBar[6]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 6 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204TxLaneXbarLane7SelectBfSet(device, + baseAddr, + laneXBar[7]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 7 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_RxLaneXBarCfgSet(adi_fpga9025_Device_t* device, + adi_fpga9025_DeframerSel_e deframerSel, + uint8_t* laneXBar) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfJesd204RxLaneXbarChanAddr_e baseAddr = FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + laneXBar); + + /* Set correct addresses for the deframer selected */ + if (deframerSel == ADI_FPGA9025_DEFRAMER_0) + { + baseAddr = FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0; + } + else if (deframerSel == ADI_FPGA9025_DEFRAMER_1) + { + baseAddr = FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1; + } + else if (deframerSel == ADI_FPGA9025_DEFRAMER_2) + { + baseAddr = FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSel, + "Invalid deframer selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + recoveryAction = fpga9025_Jesd204RxLaneXbarLane0SelectBfSet(device, + baseAddr, + laneXBar[0]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 0 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204RxLaneXbarLane1SelectBfSet(device, + baseAddr, + laneXBar[1]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 1 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204RxLaneXbarLane2SelectBfSet(device, + baseAddr, + laneXBar[2]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 2 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204RxLaneXbarLane3SelectBfSet(device, + baseAddr, + laneXBar[3]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 3 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204RxLaneXbarLane4SelectBfSet(device, + baseAddr, + laneXBar[4]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 4 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204RxLaneXbarLane5SelectBfSet(device, + baseAddr, + laneXBar[5]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 5 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204RxLaneXbarLane6SelectBfSet(device, + baseAddr, + laneXBar[6]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 6 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204RxLaneXbarLane7SelectBfSet(device, + baseAddr, + laneXBar[7]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 7 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_TxLaneXBarCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_FramerSel_e framerSel, + uint8_t* laneXBar) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t baseAddr = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + laneXBar); + + /* Set correct addresses for the framer selected */ + if (framerSel == ADI_FPGA9025_FRAMER_0) + { + baseAddr = FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_0; + } + else if (framerSel == ADI_FPGA9025_FRAMER_1) + { + baseAddr = FPGA9025_BF_JESD204_TX_LANE_XBAR_LINK_1; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + framerSel, + "Invalid framer selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = fpga9025_Jesd204TxLaneXbarLane0SelectBfGet(device, + (fpga9025_BfJesd204TxLaneXbarChanAddr_e)baseAddr, + &laneXBar[0]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 0 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204TxLaneXbarLane1SelectBfGet(device, + (fpga9025_BfJesd204TxLaneXbarChanAddr_e)baseAddr, + &laneXBar[1]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 1 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204TxLaneXbarLane2SelectBfGet(device, + (fpga9025_BfJesd204TxLaneXbarChanAddr_e)baseAddr, + &laneXBar[2]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 2 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204TxLaneXbarLane3SelectBfGet(device, + (fpga9025_BfJesd204TxLaneXbarChanAddr_e)baseAddr, + &laneXBar[3]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 3 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204TxLaneXbarLane4SelectBfGet(device, + (fpga9025_BfJesd204TxLaneXbarChanAddr_e)baseAddr, + &laneXBar[4]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 4 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204TxLaneXbarLane5SelectBfGet(device, + (fpga9025_BfJesd204TxLaneXbarChanAddr_e)baseAddr, + &laneXBar[5]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 5 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204TxLaneXbarLane6SelectBfGet(device, + (fpga9025_BfJesd204TxLaneXbarChanAddr_e)baseAddr, + &laneXBar[6]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 6 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204TxLaneXbarLane7SelectBfGet(device, + (fpga9025_BfJesd204TxLaneXbarChanAddr_e)baseAddr, + &laneXBar[7]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 7 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_RxLaneXBarCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_DeframerSel_e deframerSel, + uint8_t* laneXBar) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t baseAddr = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + laneXBar); + + /* Set correct addresses for the deframer selected */ + if (deframerSel == ADI_FPGA9025_DEFRAMER_0) + { + baseAddr = FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_0; + } + else if (deframerSel == ADI_FPGA9025_DEFRAMER_1) + { + baseAddr = FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_1; + } + else if (deframerSel == ADI_FPGA9025_DEFRAMER_2) + { + baseAddr = FPGA9025_BF_JESD204_RX_LANE_XBAR_LINK_2; + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + deframerSel, + "Invalid deframer selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + recoveryAction = fpga9025_Jesd204RxLaneXbarLane0SelectBfGet(device, + (fpga9025_BfJesd204RxLaneXbarChanAddr_e)baseAddr, + &laneXBar[0]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 0 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204RxLaneXbarLane1SelectBfGet(device, + (fpga9025_BfJesd204RxLaneXbarChanAddr_e)baseAddr, + &laneXBar[1]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 1 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204RxLaneXbarLane2SelectBfGet(device, + (fpga9025_BfJesd204RxLaneXbarChanAddr_e)baseAddr, + &laneXBar[2]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 2 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204RxLaneXbarLane3SelectBfGet(device, + (fpga9025_BfJesd204RxLaneXbarChanAddr_e)baseAddr, + &laneXBar[3]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 3 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204RxLaneXbarLane4SelectBfGet(device, + (fpga9025_BfJesd204RxLaneXbarChanAddr_e)baseAddr, + &laneXBar[4]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 4 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204RxLaneXbarLane5SelectBfGet(device, + (fpga9025_BfJesd204RxLaneXbarChanAddr_e)baseAddr, + &laneXBar[5]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 5 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204RxLaneXbarLane6SelectBfGet(device, + (fpga9025_BfJesd204RxLaneXbarChanAddr_e)baseAddr, + &laneXBar[6]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 6 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204RxLaneXbarLane7SelectBfGet(device, + (fpga9025_BfJesd204RxLaneXbarChanAddr_e)baseAddr, + &laneXBar[7]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading Lane 7 configuration"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_FramerReset(adi_fpga9025_Device_t* device, + uint8_t framerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID) + { + recoveryAction = fpga9025_Jesd204BFramerReset(device, + framerSelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + recoveryAction = fpga9025_Jesd204CFramerReset(device, + framerSelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_FramerDisable(adi_fpga9025_Device_t* device, + uint8_t framerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID) + { + recoveryAction = fpga9025_Jesd204BFramerDisable(device, + framerSelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + recoveryAction = fpga9025_Jesd204CFramerDisable(device, + framerSelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_DeframerReset(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID) + { + recoveryAction = fpga9025_Jesd204BDeframerReset(device, + deframerSelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + recoveryAction = fpga9025_Jesd204CDeframerReset(device, + deframerSelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_DeframerDisable(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID) + { + recoveryAction = fpga9025_Jesd204BDeframerDisable(device, + deframerSelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + recoveryAction = fpga9025_Jesd204CDeframerDisable(device, + deframerSelMask); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_DeframerStatusGet(adi_fpga9025_Device_t* device, + uint8_t deframerSelMask, + uint8_t* status) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID) + { + recoveryAction = fpga9025_Jesd204BDeframerStatusGet(device, + deframerSelMask, + status); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + recoveryAction = fpga9025_Jesd204CDeframerStatusGet(device, + deframerSelMask, + status); + ADI_ERROR_RETURN(device->common.error.newAction); + } + else + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "FPGA device not initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_ChannelLoopbackEnable(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + uint8_t loopbackValue) +{ + UNUSED_PARA(device); + UNUSED_PARA(laneSelMask); + UNUSED_PARA(loopbackValue); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + // + // ADI_NULL_DEVICE_PTR_RETURN(device); + // + //#if ADI_FPGA9025_VERBOSE > 0 + // ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + //#endif + // + // if ((laneSelMask & ADI_FPGA9025_LANE_0) == ADI_FPGA9025_LANE_0) + // { + // recoveryAction = fpga9025_Jesd204PhyAds9Channel0LoopbackBfSet(device, FPGA9025_BF_ADS9_JESD_PHY, (loopbackValue & 0x07)); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting loopback for channel 0"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // if ((laneSelMask & ADI_FPGA9025_LANE_1) == ADI_FPGA9025_LANE_1) + // { + // recoveryAction = fpga9025_Jesd204PhyAds9Channel1LoopbackBfSet(device, FPGA9025_BF_ADS9_JESD_PHY, (loopbackValue & 0x07)); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting loopback for channel 1"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // if ((laneSelMask & ADI_FPGA9025_LANE_2) == ADI_FPGA9025_LANE_2) + // { + // recoveryAction = fpga9025_Jesd204PhyAds9Channel2LoopbackBfSet(device, FPGA9025_BF_ADS9_JESD_PHY, (loopbackValue & 0x07)); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error resettingsetting loopback for channel 2"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // if ((laneSelMask & ADI_FPGA9025_LANE_3) == ADI_FPGA9025_LANE_3) + // { + // recoveryAction = fpga9025_Jesd204PhyAds9Channel3LoopbackBfSet(device, FPGA9025_BF_ADS9_JESD_PHY, (loopbackValue & 0x07)); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting loopback for channel 3"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // if ((laneSelMask & ADI_FPGA9025_LANE_4) == ADI_FPGA9025_LANE_4) + // { + // recoveryAction = fpga9025_Jesd204PhyAds9Channel4LoopbackBfSet(device, FPGA9025_BF_ADS9_JESD_PHY, (loopbackValue & 0x07)); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting loopback for channel 4"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // if ((laneSelMask & ADI_FPGA9025_LANE_5) == ADI_FPGA9025_LANE_5) + // { + // recoveryAction = fpga9025_Jesd204PhyAds9Channel5LoopbackBfSet(device, FPGA9025_BF_ADS9_JESD_PHY, (loopbackValue & 0x07)); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting loopback for channel 5"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // if ((laneSelMask & ADI_FPGA9025_LANE_6) == ADI_FPGA9025_LANE_6) + // { + // recoveryAction = fpga9025_Jesd204PhyAds9Channel6LoopbackBfSet(device, FPGA9025_BF_ADS9_JESD_PHY, (loopbackValue & 0x07)); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting loopback for channel 6"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // if ((laneSelMask & ADI_FPGA9025_LANE_7) == ADI_FPGA9025_LANE_7) + // { + // recoveryAction = fpga9025_Jesd204PhyAds9Channel7LoopbackBfSet(device, FPGA9025_BF_ADS9_JESD_PHY, (loopbackValue & 0x07)); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting loopback for channel 7"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // + return recoveryAction; +} + +int32_t adi_fpga9025_ChannelDfeLpmOverrideSet(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + uint8_t value) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + if (laneSelMask == ADI_FPGA9025_ZERO) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + laneSelMask, + "Error laneSelMask cannot be zero"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & ADI_FPGA9025_LANE_0) == ADI_FPGA9025_LANE_0) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel0RxDfeLpmOverrideBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + value); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting RxDfeLpmOverride for channel 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & ADI_FPGA9025_LANE_1) == ADI_FPGA9025_LANE_1) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel1RxDfeLpmOverrideBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + value); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting RxDfeLpmOverride for channel 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & ADI_FPGA9025_LANE_2) == ADI_FPGA9025_LANE_2) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel2RxDfeLpmOverrideBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + value); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error resettingsetting RxDfeLpmOverride for channel 2"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & ADI_FPGA9025_LANE_3) == ADI_FPGA9025_LANE_3) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel3RxDfeLpmOverrideBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + value); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting RxDfeLpmOverride for channel 3"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & ADI_FPGA9025_LANE_4) == ADI_FPGA9025_LANE_4) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel4RxDfeLpmOverrideBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + value); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting RxDfeLpmOverride for channel 4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & ADI_FPGA9025_LANE_5) == ADI_FPGA9025_LANE_5) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel5RxDfeLpmOverrideBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + value); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting RxDfeLpmOverride for channel 5"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & ADI_FPGA9025_LANE_6) == ADI_FPGA9025_LANE_6) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel6RxDfeLpmOverrideBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + value); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting RxDfeLpmOverride for channel 6"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & ADI_FPGA9025_LANE_7) == ADI_FPGA9025_LANE_7) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel7RxDfeLpmOverrideBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + value); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting RxDfeLpmOverride for channel 7"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_SyncXBarCfgSet(adi_fpga9025_Device_t* device, + uint8_t polarity, + uint8_t* inputSyncSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t maxIndex = ADI_FPGA9025_NUM_OF_DEFRAMERS + ADI_FPGA9025_NUM_OF_FRAMERS; + char serializerErrStr[][64] = {"Error setting output sync 0 configuration"}; + uint32_t laneNumPos = 26; + + typedef struct + { + int32_t (*SyncXbarSyncOutSelectBfSet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t ); + } fpgaSyncXbarSyncOutSelectBfSet_t; + + fpgaSyncXbarSyncOutSelectBfSet_t syncXbarSyncOutSelectBfSetFct[] = { + {.SyncXbarSyncOutSelectBfSet = fpga9025_Jesd204bSyncXbarSyncOut0SelectBfSet}, + {.SyncXbarSyncOutSelectBfSet = fpga9025_Jesd204bSyncXbarSyncOut1SelectBfSet}, + {.SyncXbarSyncOutSelectBfSet = fpga9025_Jesd204bSyncXbarSyncOut2SelectBfSet}, + {.SyncXbarSyncOutSelectBfSet = fpga9025_Jesd204bSyncXbarSyncOut3SelectBfSet}, + {.SyncXbarSyncOutSelectBfSet = fpga9025_Jesd204bSyncXbarSyncOut4SelectBfSet}, + {.SyncXbarSyncOutSelectBfSet = fpga9025_Jesd204bSyncXbarSyncOut5SelectBfSet}, + {.SyncXbarSyncOutSelectBfSet = fpga9025_Jesd204bSyncXbarSyncOut6SelectBfSet}, + {.SyncXbarSyncOutSelectBfSet = fpga9025_Jesd204bSyncXbarSyncOut7SelectBfSet} + }; + int32_t i = 0; + int32_t loopCnt = sizeof(syncXbarSyncOutSelectBfSetFct) / sizeof(fpgaSyncXbarSyncOutSelectBfSet_t); + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + inputSyncSel); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + for (i = 0; i < loopCnt; i++) + { + if (syncXbarSyncOutSelectBfSetFct[i].SyncXbarSyncOutSelectBfSet != NULL) + { + if (maxIndex > 0) + { + recoveryAction = syncXbarSyncOutSelectBfSetFct[i].SyncXbarSyncOutSelectBfSet(device, + FPGA9025_BF_JESD204B_SYNC_XBAR, + inputSyncSel[i]); + serializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + maxIndex--; + } + else + { + break; + } + } + } + + recoveryAction = fpga9025_Jesd204bSyncXbarSyncInPolarityBfSet(device, + FPGA9025_BF_JESD204B_SYNC_XBAR, + polarity); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting sync xbar polarity"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_SyncXBarCfgGet(adi_fpga9025_Device_t* device, + uint8_t* polarity, + uint8_t* inputSyncSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t maxIndex = ADI_FPGA9025_NUM_OF_DEFRAMERS + ADI_FPGA9025_NUM_OF_FRAMERS; + char serializerErrStr[][64] = {"Error reading output sync 0 configuration"}; + uint32_t laneNumPos = 26; + + typedef struct + { + int32_t (*SyncXbarSyncOutSelectBfGet)(adi_fpga9025_Device_t* device, + fpga9025_BfJesd204bSyncXbarChanAddr_e baseAddr, + uint8_t* ); + } fpgaSyncXbarSyncOutSelectBfGet_t; + + fpgaSyncXbarSyncOutSelectBfGet_t syncXbarSyncOutSelectBfGetFct[] = { + {.SyncXbarSyncOutSelectBfGet = fpga9025_Jesd204bSyncXbarSyncOut0SelectBfGet}, + {.SyncXbarSyncOutSelectBfGet = fpga9025_Jesd204bSyncXbarSyncOut1SelectBfGet}, + {.SyncXbarSyncOutSelectBfGet = fpga9025_Jesd204bSyncXbarSyncOut2SelectBfGet}, + {.SyncXbarSyncOutSelectBfGet = fpga9025_Jesd204bSyncXbarSyncOut3SelectBfGet}, + {.SyncXbarSyncOutSelectBfGet = fpga9025_Jesd204bSyncXbarSyncOut4SelectBfGet}, + {.SyncXbarSyncOutSelectBfGet = fpga9025_Jesd204bSyncXbarSyncOut5SelectBfGet}, + {.SyncXbarSyncOutSelectBfGet = fpga9025_Jesd204bSyncXbarSyncOut6SelectBfGet}, + {.SyncXbarSyncOutSelectBfGet = fpga9025_Jesd204bSyncXbarSyncOut7SelectBfGet} + }; + int32_t i = 0; + int32_t loopCnt = sizeof(syncXbarSyncOutSelectBfGetFct) / sizeof(fpgaSyncXbarSyncOutSelectBfGet_t); + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + inputSyncSel); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + for (i = 0; i < loopCnt; i++) + { + if (syncXbarSyncOutSelectBfGetFct[i].SyncXbarSyncOutSelectBfGet != NULL) + { + if (maxIndex > 0) + { + recoveryAction = syncXbarSyncOutSelectBfGetFct[i].SyncXbarSyncOutSelectBfGet(device, + FPGA9025_BF_JESD204B_SYNC_XBAR, + &inputSyncSel[i]); + serializerErrStr[0][laneNumPos] = i + 48; /* convert a number to ascii character of the number i.e. 0 --> '0' */ + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + (const char *)serializerErrStr[0]); + ADI_ERROR_RETURN(device->common.error.newAction); + maxIndex--; + } + else + { + break; + } + } + } + + recoveryAction = fpga9025_Jesd204bSyncXbarSyncInPolarityBfGet(device, + FPGA9025_BF_JESD204B_SYNC_XBAR, + polarity); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading sync xbar polarity"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_SysRefControlSet(adi_fpga9025_Device_t* device, + adi_fpga9025_SysRefClkCfg_t* sysRefCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + sysRefCfg); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + recoveryAction = fpga9025_Jesd204SysrefControlExtSysrefPolarityBfSet(device, + FPGA9025_BF_JESD204_SYSREF_CONTROL, + sysRefCfg->externalSysrefPolarity); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting external sysref polarity"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204SysrefControlExtSysrefSampleEdgeBfSet(device, + FPGA9025_BF_JESD204_SYSREF_CONTROL, + sysRefCfg->externalSysrefSampleEdge); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting external sysref sample edge"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204SysrefControlIntSysrefEnableBfSet(device, + FPGA9025_BF_JESD204_SYSREF_CONTROL, + sysRefCfg->internalSysrefEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting internal sysref enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Write (actual value) - 1 to register */ + recoveryAction = fpga9025_Jesd204SysrefControlIntSysrefGenPeriodBfSet(device, + FPGA9025_BF_JESD204_SYSREF_CONTROL, + sysRefCfg->internalSysRefGeneratorFrequency - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting internal sysref generator"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_SysRefControlGet(adi_fpga9025_Device_t* device, + adi_fpga9025_SysRefClkCfg_t* sysRefCfg) +{ + UNUSED_PARA(device); + UNUSED_PARA(sysRefCfg); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + // + // ADI_NULL_DEVICE_PTR_RETURN(device); + // + // ADI_NULL_PTR_RETURN(&device->common, sysRefCfg); + // + //#if ADI_FPGA9025_VERBOSE > 0 + // ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + //#endif + // + // recoveryAction = fpga9025_Jesd204SysrefControlExtSysrefPolarityBfGet(device, FPGA9025_BF_JESD204_SYSREF_CONTROL, &sysRefCfg->externalSysrefPolarity); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting external sysref polarity"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // + // recoveryAction = fpga9025_Jesd204SysrefControlExtSysrefSampleEdgeBfGet(device, FPGA9025_BF_JESD204_SYSREF_CONTROL, &sysRefCfg->externalSysrefSampleEdge); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting external sysref sample edge"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // + // recoveryAction = fpga9025_Jesd204SysrefControlIntSysrefEnableBfGet(device, FPGA9025_BF_JESD204_SYSREF_CONTROL, &sysRefCfg->internalSysrefEnable); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting internal sysref enable"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // + // /* Write (actual value) - 1 to register */ + // recoveryAction = fpga9025_Jesd204SysrefControlIntSysrefGenPeriodBfGet(device, FPGA9025_BF_JESD204_SYSREF_CONTROL, &sysRefCfg->internalSysRefGeneratorFrequency); + // sysRefCfg->internalSysRefGeneratorFrequency++; + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting internal sysref generator"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // + return recoveryAction; +} + +// +int32_t adi_fpga9025_SysRefRequest(adi_fpga9025_Device_t* device) +{ + UNUSED_PARA(device); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + // uint8_t internalSysrefEnable = 0; + // + // ADI_NULL_DEVICE_PTR_RETURN(device); + // + //#if ADI_FPGA9025_VERBOSE > 0 + // ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + //#endif + // + // recoveryAction = fpga9025_Jesd204SysrefControlIntSysrefEnableBfGet(device, FPGA9025_BF_JESD204_SYSREF_CONTROL, &internalSysrefEnable); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error reading sync xbar polarity"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // + // if (internalSysrefEnable == 1) + // { + // recoveryAction = fpga9025_Jesd204SysrefControlIntSysrefRequestBfSet(device, FPGA9025_BF_JESD204_SYSREF_CONTROL, 1); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting internal sysref request"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // else + // { + // recoveryAction = fpga9025_Jesd204SysrefControlExtSysrefRequestBfSet(device, FPGA9025_BF_JESD204_SYSREF_CONTROL, 1); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_COMMON_ERR_INV_PARAM, recoveryAction, NULL, "Error setting external sysref request"); + // ADI_ERROR_RETURN(device->common.error.newAction); + // } + // + return recoveryAction; +} + +// +//int32_t adi_fpga9025_SyncbStatus(adi_fpga9025_Device_t *device, uint32_t *status) +//{ +// //TODO: implement this +// int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; +// return recoveryAction; +//} + +int32_t adi_fpga9025_Jesd204CDeframerCmdDataSet(adi_fpga9025_Device_t* device, + uint32_t deframerSelMask, + uint8_t cmdEnable, + uint8_t dataEnable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9025_BF_JESD204C_DEFRAMER_0; + uint32_t i = 0; + adi_fpga9025_DeframerSel_e deframerSel = ADI_FPGA9025_DEFRAMER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (deframerSelMask < ADI_FPGA9025_DEFRAMER_0 || deframerSelMask > ADI_FPGA9025_DEFRAMER_ALL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid deframer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_DEFRAMERS; i++) + { + deframerSel = (adi_fpga9025_DeframerSel_e)((uint8_t)(1 << i)); + + switch (deframerSel) + { + case ADI_FPGA9025_DEFRAMER_0: + instanceAddress = FPGA9025_BF_JESD204C_DEFRAMER_0; + break; + case ADI_FPGA9025_DEFRAMER_1: + instanceAddress = FPGA9025_BF_JESD204C_DEFRAMER_1; + break; + case ADI_FPGA9025_DEFRAMER_2: + instanceAddress = FPGA9025_BF_JESD204C_DEFRAMER_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)deframerSel & deframerSelMask) > 0) + { + recoveryAction = fpga9025_XilinxJesd204cEnableCmdInterfaceBfSet(device, + instanceAddress, + cmdEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set cmd interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cEnableDataInterfaceBfSet(device, + instanceAddress, + dataEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set data interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_Jesd204CFramerCmdDataSet(adi_fpga9025_Device_t* device, + uint32_t framerSelMask, + uint8_t cmdEnable, + uint8_t dataEnable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfXilinxJesd204cChanAddr_e instanceAddress = FPGA9025_BF_JESD204C_FRAMER_0; + uint32_t i = 0; + adi_fpga9025_FramerSel_e framerSel = ADI_FPGA9025_FRAMER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (framerSelMask < ADI_FPGA9025_FRAMER_0 || framerSelMask > ADI_FPGA9025_FRAMER_ALL) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid framer selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_FRAMERS; i++) + { + framerSel = (adi_fpga9025_FramerSel_e)((uint8_t)(1 << i)); + + switch (framerSel) + { + case ADI_FPGA9025_FRAMER_0: + instanceAddress = FPGA9025_BF_JESD204C_FRAMER_0; + break; + case ADI_FPGA9025_FRAMER_1: + instanceAddress = FPGA9025_BF_JESD204C_FRAMER_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)framerSel & framerSelMask) > 0) + { + recoveryAction = fpga9025_XilinxJesd204cEnableCmdInterfaceBfSet(device, + instanceAddress, + cmdEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set cmd interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_XilinxJesd204cEnableDataInterfaceBfSet(device, + instanceAddress, + dataEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Unable to set data interface enable."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_SysRefEnableSet(adi_fpga9025_Device_t* device, + uint8_t framerSelMask, + uint8_t deframerSelMask, + uint8_t enable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t outputEnableRegisterVal = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + recoveryAction = fpga9025_Jesd204SysrefControlOutputEnableBfGet(device, + FPGA9025_BF_JESD204_SYSREF_CONTROL, + &outputEnableRegisterVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting output enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Force only the bits we care about */ + framerSelMask = (ADI_FPGA9025_FRAMER_ALL & framerSelMask); + deframerSelMask = (ADI_FPGA9025_DEFRAMER_ALL & deframerSelMask); + + if (enable == ADI_ENABLE) + { + outputEnableRegisterVal |= (uint32_t)deframerSelMask; + outputEnableRegisterVal |= (uint32_t)framerSelMask << ADI_FPGA9025_NUM_OF_DEFRAMERS; + } + else if (enable == ADI_DISABLE) + { + outputEnableRegisterVal &= ~((uint32_t)deframerSelMask); + outputEnableRegisterVal &= ~((uint32_t)framerSelMask << ADI_FPGA9025_NUM_OF_DEFRAMERS); + } + + recoveryAction = fpga9025_Jesd204SysrefControlOutputEnableBfSet(device, + FPGA9025_BF_JESD204_SYSREF_CONTROL, + outputEnableRegisterVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting output enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_InternalSysrefEnableSet(adi_fpga9025_Device_t* device, + uint8_t enable) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + recoveryAction = fpga9025_Jesd204SysrefControlIntSysrefEnableBfSet(device, + FPGA9025_BF_JESD204_SYSREF_CONTROL, + enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting internal sysref enable"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_InternalSysrefRequest(adi_fpga9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + recoveryAction = fpga9025_Jesd204SysrefControlIntSysrefRequestBfSet(device, + FPGA9025_BF_JESD204_SYSREF_CONTROL, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting internal sysref request"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_prbs.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_prbs.c new file mode 100644 index 0000000..9f5999a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_prbs.c @@ -0,0 +1,629 @@ +/** + * \file: adi_fpga9025_jesd.c + * + * \brief Contains top level tx fpga9025 related functions + * + * FPGA9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9025_user.h" +#include "adi_fpga9025_prbs.h" +#include "adi_fpga9025.h" +#include "../../private/include/fpga9025_bf_jesd204_phy_ads9.h" + +int32_t adi_fpga9025_PrbsSerializerEnable(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + adi_fpga9025_PrbsTestModes_e prbsModeSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + if ((prbsModeSel < ADI_FPGA9025_PRBS_OFF || prbsModeSel > ADI_FPGA9025_PRBS_31) && ((prbsModeSel != ADI_FPGA9025_SQ_2UI) && (prbsModeSel != + ADI_FPGA9025_SQ_INT_UI))) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + prbsModeSel, + "An invalid PRBS test mode is selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((laneSelMask & 0x01) == 0x01) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel0TxPrbsSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint8_t)prbsModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting PRBS mode for channel 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x02) == 0x02) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel1TxPrbsSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint8_t)prbsModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting PRBS mode for channel 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x04) == 0x04) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel2TxPrbsSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint8_t)prbsModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting PRBS mode for channel 2"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x08) == 0x08) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel3TxPrbsSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint8_t)prbsModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting PRBS mode for channel 3"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x10) == 0x10) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel4TxPrbsSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint8_t)prbsModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting PRBS mode for channel 4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x20) == 0x20) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel5TxPrbsSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint8_t)prbsModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting PRBS mode for channel 5"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x40) == 0x40) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel6TxPrbsSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint8_t)prbsModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting PRBS mode for channel 6"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x80) == 0x80) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel7TxPrbsSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint8_t)prbsModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting PRBS mode for channel 7"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_PrbsDeserializerEnable(adi_fpga9025_Device_t* device, + uint8_t laneSelMask, + adi_fpga9025_PrbsTestModes_e prbsModeSel) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + if (prbsModeSel < ADI_FPGA9025_PRBS_OFF || prbsModeSel > ADI_FPGA9025_PRBS_31) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + prbsModeSel, + "An invalid PRBS test mode is selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if ((laneSelMask & 0x01) == 0x01) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel0RxPrbsSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint8_t)prbsModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting PRBS mode for channel 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x02) == 0x02) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel1RxPrbsSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint8_t)prbsModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting PRBS mode for channel 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x04) == 0x04) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel2RxPrbsSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint8_t)prbsModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting PRBS mode for channel 2"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x08) == 0x08) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel3RxPrbsSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint8_t)prbsModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting PRBS mode for channel 3"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x10) == 0x10) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel4RxPrbsSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint8_t)prbsModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting PRBS mode for channel 4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x20) == 0x20) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel5RxPrbsSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint8_t)prbsModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting PRBS mode for channel 5"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x40) == 0x40) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel6RxPrbsSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint8_t)prbsModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting PRBS mode for channel 6"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x80) == 0x80) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel7RxPrbsSelBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + (uint8_t)prbsModeSel); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error setting PRBS mode for channel 7"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_PrbsSerializerErrorInject(adi_fpga9025_Device_t* device, + uint8_t laneSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + if ((laneSelMask & 0x01) == 0x01) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel0TxPrbsInjErrBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error injecting an error for channel 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x02) == 0x02) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel1TxPrbsInjErrBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error injecting an error for channel 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x04) == 0x04) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel2TxPrbsInjErrBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error injecting an error for channel 2"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x08) == 0x08) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel3TxPrbsInjErrBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error injecting an error for channel 3"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x10) == 0x10) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel4TxPrbsInjErrBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error injecting an error for channel 4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x20) == 0x20) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel5TxPrbsInjErrBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error injecting an error for channel 5"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x40) == 0x40) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel6TxPrbsInjErrBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error injecting an error for channel 6"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x80) == 0x80) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel7TxPrbsInjErrBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error injecting an error for channel 7"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_PrbsErrorCountRead(adi_fpga9025_Device_t* device, + uint32_t* errCounts) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + errCounts); + + recoveryAction = fpga9025_Jesd204PhyAds9Channel0RxPrbsErrCntBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &errCounts[0]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading PRBS error count for channel 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204PhyAds9Channel1RxPrbsErrCntBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &errCounts[1]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading PRBS error count for channel 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204PhyAds9Channel2RxPrbsErrCntBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &errCounts[2]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading PRBS error count for channel 2"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204PhyAds9Channel3RxPrbsErrCntBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &errCounts[3]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading PRBS error count for channel 3"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204PhyAds9Channel4RxPrbsErrCntBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &errCounts[4]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading PRBS error count for channel 4"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204PhyAds9Channel5RxPrbsErrCntBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &errCounts[5]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading PRBS error count for channel 5"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204PhyAds9Channel6RxPrbsErrCntBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &errCounts[6]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading PRBS error count for channel 6"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_Jesd204PhyAds9Channel7RxPrbsErrCntBfGet(device, + FPGA9025_BF_ADS9_JESD_PHY, + &errCounts[7]); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error reading PRBS error count for channel 7"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_PrbsErrorClear(adi_fpga9025_Device_t* device, + uint8_t laneSelMask) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + if ((laneSelMask & 0x01) == 0x01) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel0RxPrbsErrCntRstBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error clearing the error count for channel 0"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x02) == 0x02) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel1RxPrbsErrCntRstBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error clearing the error count for channel 1"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x04) == 0x04) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel2RxPrbsErrCntRstBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error clearing the error count for channel 2"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x08) == 0x08) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel3RxPrbsErrCntRstBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error clearing the error count for channel 3"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x10) == 0x10) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel4RxPrbsErrCntRstBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error clearing the error count for channel 4"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x20) == 0x20) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel5RxPrbsErrCntRstBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error clearing the error count for channel 5"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x40) == 0x40) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel6RxPrbsErrCntRstBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error clearing the error count for channel 6"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + if ((laneSelMask & 0x80) == 0x80) + { + recoveryAction = fpga9025_Jesd204PhyAds9Channel7RxPrbsErrCntRstBfSet(device, + FPGA9025_BF_ADS9_JESD_PHY, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Error clearing the error count for channel 7"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_rx.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_rx.c new file mode 100644 index 0000000..2d53e63 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_rx.c @@ -0,0 +1,1504 @@ +/** + * \file: adi_fpga9025_rx.c + * + * \brief Contains top level rx fpga9025 related functions + * + * FPGA9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9025_user.h" +#include "adi_fpga9025_rx.h" +#include "adi_fpga9025.h" +#include "../../private/include/fpga9025_bf_dp_tollgate.h" +#include "../../private/include/fpga9025_bf_dp_rx_dma.h" +#include "../../private/include/fpga9025_bf_dp_capture_control.h" + +int32_t adi_fpga9025_RxTollgateSet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + adi_fpga9025_RxTollgateCfg_t* tollGateCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTollgateChanAddr_e instanceAddress = FPGA9025_BF_DP_TOLLGATE_RX_0; + uint32_t i = 0; + adi_fpga9025_RxDatamoverSel_e dataMoverSel = ADI_FPGA9025_RX_DATAMOVER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + tollGateCfg); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_RX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_RxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_RX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_RX_0; + break; + case ADI_FPGA9025_RX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_RX_1; + break; + case ADI_FPGA9025_RX_DATAMOVER_2: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = fpga9025_DpTollgateEdgeLevelBfSet(device, + instanceAddress, + tollGateCfg->tollGateEdgeOrLvl); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to detection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTollgateHighRisingLowFallingBfSet(device, + instanceAddress, + tollGateCfg->tollGateHiRiseOrLoFall); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to polarity register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTollgateTriggerSelectBfSet(device, + instanceAddress, + (uint32_t)tollGateCfg->tollGateTrigSource); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to selection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_RxTollgateGet(adi_fpga9025_Device_t* device, + adi_fpga9025_RxDatamoverSel_e rxDatamoverSel, + adi_fpga9025_RxTollgateCfg_t* tollGateCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTollgateChanAddr_e baseAddress = FPGA9025_BF_DP_TOLLGATE_RX_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + tollGateCfg); + + switch (rxDatamoverSel) + { + case ADI_FPGA9025_RX_DATAMOVER_0: + baseAddress = FPGA9025_BF_DP_TOLLGATE_RX_0; + break; + case ADI_FPGA9025_RX_DATAMOVER_1: + baseAddress = FPGA9025_BF_DP_TOLLGATE_RX_1; + break; + case ADI_FPGA9025_RX_DATAMOVER_2: + baseAddress = FPGA9025_BF_DP_TOLLGATE_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxDatamoverSel, + "Invalid datamover selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + recoveryAction = fpga9025_DpTollgateEdgeLevelBfGet(device, + baseAddress, + &tollGateCfg->tollGateEdgeOrLvl); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to detection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTollgateHighRisingLowFallingBfGet(device, + baseAddress, + &tollGateCfg->tollGateHiRiseOrLoFall); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to polarity register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTollgateTriggerSelectBfGet(device, + baseAddress, + (uint32_t*)&tollGateCfg->tollGateTrigSource); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to selection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_RxTollgateResetSet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + uint8_t resetVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTollgateChanAddr_e instanceAddress = FPGA9025_BF_DP_TOLLGATE_RX_0; + uint32_t i = 0; + adi_fpga9025_RxDatamoverSel_e dataMoverSel = ADI_FPGA9025_RX_DATAMOVER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_RX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_RxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_RX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_RX_0; + break; + case ADI_FPGA9025_RX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_RX_1; + break; + case ADI_FPGA9025_RX_DATAMOVER_2: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = fpga9025_DpTollgateResetTollgateBfSet(device, + instanceAddress, + resetVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to reset register"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_RxTollgateResetGet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + uint16_t* resetVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTollgateChanAddr_e instanceAddress = FPGA9025_BF_DP_TOLLGATE_RX_0; + uint32_t i = 0; + adi_fpga9025_RxDatamoverSel_e dataMoverSel = ADI_FPGA9025_RX_DATAMOVER_0; + uint8_t resetBitRead = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + resetVal); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *resetVal = 0; + + for (i = 0; i < ADI_FPGA9025_NUM_OF_RX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_RxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_RX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_RX_0; + break; + case ADI_FPGA9025_RX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_RX_1; + break; + case ADI_FPGA9025_RX_DATAMOVER_2: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = fpga9025_DpTollgateResetTollgateBfGet(device, + instanceAddress, + &resetBitRead); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read from reset register"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *resetVal |= (resetBitRead & 1) << i; + } + + return recoveryAction; +} + +int32_t adi_fpga9025_RxTollgateTriggerSet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + adi_fpga9025_RxTollgateTrigSources_e triggerSelect) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTollgateChanAddr_e instanceAddress = FPGA9025_BF_DP_TOLLGATE_RX_0; + uint32_t i = 0; + adi_fpga9025_RxDatamoverSel_e dataMoverSel = ADI_FPGA9025_RX_DATAMOVER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_RX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_RxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_RX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_RX_0; + break; + case ADI_FPGA9025_RX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_RX_1; + break; + case ADI_FPGA9025_RX_DATAMOVER_2: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = adi_fpga9025_RxTollgateResetSet(device, + rxDatamoverSelMask, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTollgateTriggerSelectBfSet(device, + (fpga9025_BfDpTollgateChanAddr_e)instanceAddress, + (uint32_t)triggerSelect); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to triggerSelect bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_RxTollgateResetSet(device, + rxDatamoverSelMask, + 0); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_RxTollgateTriggerGet(adi_fpga9025_Device_t* device, + adi_fpga9025_RxDatamoverSel_e rxDatamoverSel, + adi_fpga9025_RxTollgateTrigSources_e* triggerSelect) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTollgateChanAddr_e baseAddress = FPGA9025_BF_DP_TOLLGATE_RX_0; + uint32_t triggerSelectGet = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + triggerSelect); + + switch (rxDatamoverSel) + { + case ADI_FPGA9025_RX_DATAMOVER_0: + baseAddress = FPGA9025_BF_DP_TOLLGATE_RX_0; + break; + case ADI_FPGA9025_RX_DATAMOVER_1: + baseAddress = FPGA9025_BF_DP_TOLLGATE_RX_1; + break; + case ADI_FPGA9025_RX_DATAMOVER_2: + baseAddress = FPGA9025_BF_DP_TOLLGATE_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxDatamoverSel, + "Invalid datamover selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + recoveryAction = fpga9025_DpTollgateTriggerSelectBfGet(device, + baseAddress, + &triggerSelectGet); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to selection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + *triggerSelect = (adi_fpga9025_RxTollgateTrigSources_e)triggerSelectGet; + + return recoveryAction; +} + +int32_t adi_fpga9025_RxDmaSet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + adi_fpga9025_RxDmaCfg_t* rxDmaCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpRxDmaChanAddr_e instanceAddress = FPGA9025_BF_DP_DMA_RX_0; + uint32_t i = 0; + adi_fpga9025_RxDatamoverSel_e dataMoverSel = ADI_FPGA9025_RX_DATAMOVER_0; + uint32_t tempWorkAround = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + rxDmaCfg); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_RX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_RxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_RX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_DMA_RX_0; + break; + case ADI_FPGA9025_RX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_DMA_RX_1; + break; + case ADI_FPGA9025_RX_DATAMOVER_2: + instanceAddress = FPGA9025_BF_DP_DMA_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* TODO: start address could be changed at runtime by this function, and this length check is not enough to ensure RAM buffers do not overlap */ + if (rxDmaCfg->length > ADI_FPGA9025_RX_DMA_SIZE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Rx DMA capture length is too large"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = fpga9025_DpRxDmaEnableEnhancedModeBfSet(device, + instanceAddress, + rxDmaCfg->enableEnhancedMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write enableEnhancedMode bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaEnableSgBfSet(device, + instanceAddress, + rxDmaCfg->enableSg); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write enableSg bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaLengthBfSet(device, + instanceAddress, + rxDmaCfg->length); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write length bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaSgFirstDescriptorBfSet(device, + instanceAddress, + rxDmaCfg->sgFirstDescriptor); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write sgFirstDescriptor bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* TODO: writing to this seems to be clearing the status register. debug later */ + /* recoveryAction = fpga9025_DpRxDmaSgLastDescriptorBfSet(device, instanceAddress, rxDmaCfg->sgLastDescriptor); + * ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9025_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write sgLastDescriptor bitfield"); + * ADI_ERROR_RETURN(device->common.error.newAction); + */ + recoveryAction = adi_hal_BbicRegisterRead(device->common.devHalInfo, + instanceAddress + 0x2C, + &tempWorkAround); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + recoveryAction, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + spicrAddress, + "Error"); + ADI_ERROR_RETURN(device->common.error.newAction); + tempWorkAround &= (0xFFFF0000); + tempWorkAround |= (0x4000); + recoveryAction = adi_hal_BbicRegisterWrite(device->common.devHalInfo, + instanceAddress + 0x2C, + tempWorkAround); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + recoveryAction, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + spissrAddress, + "Error selecting all Tokelau devices"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaSimpleStartAddrBfSet(device, + instanceAddress, + (uint32_t)(rxDmaCfg->simpleStartAddr & 0x00000000FFFFFFFF)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write simpleStartAddr bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaSimpleStartAddrMswBfSet(device, + instanceAddress, + (uint32_t)(rxDmaCfg->simpleStartAddr >> 32)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write simpleStartAddrMsw bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaValidDataWidthStreamBfSet(device, + instanceAddress, + rxDmaCfg->validDataWidthStream); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write validDataWidthStream bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_RxDmaInit(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + adi_fpga9025_RxDmaCfg_t* rxDmaCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpRxDmaChanAddr_e instanceAddress = FPGA9025_BF_DP_DMA_RX_0; + uint32_t i = 0; + adi_fpga9025_RxDatamoverSel_e dataMoverSel = ADI_FPGA9025_RX_DATAMOVER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + rxDmaCfg); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_RX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_RxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_RX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_DMA_RX_0; + break; + case ADI_FPGA9025_RX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_DMA_RX_1; + break; + case ADI_FPGA9025_RX_DATAMOVER_2: + instanceAddress = FPGA9025_BF_DP_DMA_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = fpga9025_DpRxDmaEnableEnhancedModeBfSet(device, + instanceAddress, + rxDmaCfg->enableEnhancedMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write enableEnhancedMode bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaEnableSgBfSet(device, + instanceAddress, + rxDmaCfg->enableSg); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write enableSg bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaSgFirstDescriptorBfSet(device, + instanceAddress, + rxDmaCfg->sgFirstDescriptor); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write sgFirstDescriptor bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* TODO: writing to this seems to be clearing the status register. debug later */ + /* recoveryAction = fpga9025_DpRxDmaSgLastDescriptorBfSet(device, instanceAddress, rxDmaCfg->sgLastDescriptor); + * ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9025_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write sgLastDescriptor bitfield"); + * ADI_ERROR_RETURN(device->common.error.newAction); + */ + + recoveryAction = fpga9025_DpRxDmaSimpleStartAddrBfSet(device, + instanceAddress, + (uint32_t)(rxDmaCfg->simpleStartAddr & 0x00000000FFFFFFFF)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write simpleStartAddr bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaSimpleStartAddrMswBfSet(device, + instanceAddress, + (uint32_t)(rxDmaCfg->simpleStartAddr >> 32)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write simpleStartAddrMsw bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaValidDataWidthStreamBfSet(device, + instanceAddress, + rxDmaCfg->validDataWidthStream); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write validDataWidthStream bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_RxDmaGet(adi_fpga9025_Device_t* device, + adi_fpga9025_RxDatamoverSel_e rxDatamoverSel, + adi_fpga9025_RxDmaCfg_t* rxDmaCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpRxDmaChanAddr_e baseAddress = FPGA9025_BF_DP_DMA_RX_0; + uint32_t addressReadValue = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + rxDmaCfg); + + switch (rxDatamoverSel) + { + case ADI_FPGA9025_RX_DATAMOVER_0: + baseAddress = FPGA9025_BF_DP_DMA_RX_0; + break; + case ADI_FPGA9025_RX_DATAMOVER_1: + baseAddress = FPGA9025_BF_DP_DMA_RX_1; + break; + case ADI_FPGA9025_RX_DATAMOVER_2: + baseAddress = FPGA9025_BF_DP_DMA_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + rxDatamoverSel, + "Invalid datamover selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + recoveryAction = fpga9025_DpRxDmaActiveBfGet(device, + baseAddress, + &rxDmaCfg->active); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read active bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaCompleteBfGet(device, + baseAddress, + &rxDmaCfg->complete); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read complete bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaEnableEnhancedModeBfGet(device, + baseAddress, + &rxDmaCfg->enableEnhancedMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read enableEnhancedMode bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaEnableSgBfGet(device, + baseAddress, + &rxDmaCfg->enableSg); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read enableSg bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaHaltCompleteBfGet(device, + baseAddress, + &rxDmaCfg->haltComplete); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read haltComplete bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaLengthBfGet(device, + baseAddress, + &rxDmaCfg->length); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read length bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + // recoveryAction = fpga9025_DpRxDmaOverflowBfGet(device, baseAddress, &rxDmaCfg->overflow); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9025_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not read overflow bitfield"); + // ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaRunStopBfGet(device, + baseAddress, + &rxDmaCfg->runStop); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read runStop bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaSgFirstDescriptorBfGet(device, + baseAddress, + &rxDmaCfg->sgFirstDescriptor); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read sgFirstDescriptor bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaSgLastDescriptorBfGet(device, + baseAddress, + &rxDmaCfg->sgLastDescriptor); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read sgLastDescriptor bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpRxDmaSimpleStartAddrBfGet(device, + baseAddress, + &addressReadValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read simpleStartAddr bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + rxDmaCfg->simpleStartAddr = addressReadValue; + + recoveryAction = fpga9025_DpRxDmaSimpleStartAddrMswBfGet(device, + baseAddress, + &addressReadValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read simpleStartAddrMsw bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + rxDmaCfg->simpleStartAddr |= (uint64_t)addressReadValue << 32; + + recoveryAction = fpga9025_DpRxDmaValidDataWidthStreamBfGet(device, + baseAddress, + &rxDmaCfg->validDataWidthStream); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read validDataWidthStream bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_RxDmaResetSet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + uint8_t reset) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpRxDmaChanAddr_e instanceAddress = FPGA9025_BF_DP_DMA_RX_0; + uint32_t i = 0; + adi_fpga9025_RxDatamoverSel_e dataMoverSel = ADI_FPGA9025_RX_DATAMOVER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_RX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_RxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_RX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_DMA_RX_0; + break; + case ADI_FPGA9025_RX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_DMA_RX_1; + break; + case ADI_FPGA9025_RX_DATAMOVER_2: + instanceAddress = FPGA9025_BF_DP_DMA_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = fpga9025_DpRxDmaResetBfSet(device, + instanceAddress, + reset); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to reset register"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_RxDmaRunStopSet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + uint8_t runStop) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpRxDmaChanAddr_e instanceAddress = FPGA9025_BF_DP_DMA_RX_0; + uint32_t i = 0; + adi_fpga9025_RxDatamoverSel_e dataMoverSel = ADI_FPGA9025_RX_DATAMOVER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_RX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_RxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_RX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_DMA_RX_0; + break; + case ADI_FPGA9025_RX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_DMA_RX_1; + break; + case ADI_FPGA9025_RX_DATAMOVER_2: + instanceAddress = FPGA9025_BF_DP_DMA_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = fpga9025_DpRxDmaRunStopBfSet(device, + instanceAddress, + runStop); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to reset register"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_RxDmaLengthSet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask, + uint32_t numBytes) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpRxDmaChanAddr_e instanceAddress = FPGA9025_BF_DP_DMA_RX_0; + uint32_t i = 0; + adi_fpga9025_RxDatamoverSel_e dataMoverSel = ADI_FPGA9025_RX_DATAMOVER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (rxDatamoverSelMask < 1 || rxDatamoverSelMask > 7) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid rx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_RX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_RxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_RX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_DMA_RX_0; + break; + case ADI_FPGA9025_RX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_DMA_RX_1; + break; + case ADI_FPGA9025_RX_DATAMOVER_2: + instanceAddress = FPGA9025_BF_DP_DMA_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (numBytes > ADI_FPGA9025_RX_DMA_SIZE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Rx DMA capture length is too large"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & rxDatamoverSelMask) > 0) + { + recoveryAction = fpga9025_DpRxDmaLengthBfSet(device, + instanceAddress, + numBytes); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to length bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_RxDatamoverEnableSet(adi_fpga9025_Device_t* device, + uint32_t rxDatamoverSelMask) +{ + UNUSED_PARA(rxDatamoverSelMask); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + return recoveryAction; +} + +int32_t adi_fpga9025_RxDataChainConfigure(adi_fpga9025_Device_t* device, + uint32_t rxDataMoverSelMask, + adi_fpga9025_RxTollgateTrigSources_e triggerSelect, + adi_fpga9025_RxDmaCfg_t* rxDmaCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* reset capture control */ + + recoveryAction = fpga9025_DpCaptureControlResetBfSet(device, + FPGA9025_BF_DP_CAPTURE_CONTROL_RX, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* set trigger */ + recoveryAction = adi_fpga9025_RxTollgateTriggerSet(device, + rxDataMoverSelMask, + triggerSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*reset dmas */ + recoveryAction = adi_fpga9025_RxDmaResetSet(device, + rxDataMoverSelMask, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure dmas */ + recoveryAction = adi_fpga9025_RxDmaSet(device, + rxDataMoverSelMask, + rxDmaCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* set run_stop bit */ + recoveryAction = adi_fpga9025_RxDmaRunStopSet(device, + rxDataMoverSelMask, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* pass token to start dma arbitration */ + recoveryAction = fpga9025_DpCaptureControlResetBfSet(device, + FPGA9025_BF_DP_CAPTURE_CONTROL_RX, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_DpCaptureControlPassTokenBfSet(device, + FPGA9025_BF_DP_CAPTURE_CONTROL_RX, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Capture Control PassToken bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_RxDataChainReset(adi_fpga9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t active = 0; + uint8_t haltComplete = 0; + fpga9025_BfDpRxDmaChanAddr_e instanceAddress = FPGA9025_BF_DP_DMA_RX_0; + uint32_t i = 0; + adi_fpga9025_RxDatamoverSel_e dataMoverSel = ADI_FPGA9025_RX_DATAMOVER_0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* reset */ + recoveryAction = fpga9025_DpCaptureControlDatapathActiveBfSet(device, + FPGA9025_BF_DP_CAPTURE_CONTROL_RX, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to DatapathActive bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_DpCaptureControlResetBfSet(device, + FPGA9025_BF_DP_CAPTURE_CONTROL_RX, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_FPGA9025_NUM_OF_RX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_RxDatamoverSel_e)((uint8_t)(1 << i)); + active = 0; + haltComplete = 0; + + switch (dataMoverSel) + { + case ADI_FPGA9025_RX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_DMA_RX_0; + break; + case ADI_FPGA9025_RX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_DMA_RX_1; + break; + case ADI_FPGA9025_RX_DATAMOVER_2: + instanceAddress = FPGA9025_BF_DP_DMA_RX_2; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = fpga9025_DpRxDmaActiveBfGet(device, + instanceAddress, + &active); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_RxDmaRunStopSet(device, + dataMoverSel, + 0); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (active == 1) + { + while (haltComplete == 0) + { + recoveryAction = fpga9025_DpRxDmaHaltCompleteBfGet(device, + instanceAddress, + &haltComplete); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + recoveryAction = adi_fpga9025_RxDmaResetSet(device, + dataMoverSel, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adi_fpga9025_RxTollgateResetSet(device, + ADI_FPGA9025_RX_DATAMOVER_ALL, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_RxCaptureStart(adi_fpga9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + recoveryAction = fpga9025_DpCaptureControlDatapathActiveBfSet(device, + FPGA9025_BF_DP_CAPTURE_CONTROL_RX, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to DatapathActive bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_RxCaptureWait(adi_fpga9025_Device_t* device, + uint32_t timeMsDelay) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t datapathActive = 0; + uint32_t i; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + for (i = 0; i < timeMsDelay; i++) + { + recoveryAction = fpga9025_DpCaptureControlDatapathActiveBfGet(device, + FPGA9025_BF_DP_CAPTURE_CONTROL_RX, + &datapathActive); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read DatapathActive bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (datapathActive == 0) + { + return ADI_COMMON_ACT_NO_ACTION; + } + + adi_common_hal_Wait_us(&device->common, + 1000); + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_DATA_RX_MOVER_WAIT_TIMEOUT, + ADI_COMMON_ACT_ERR_RESET_FEATURE, + NULL, + "RxCaptureWait timeout"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_RxDatamoverEnableGet(adi_fpga9025_Device_t* device, + uint32_t* rxDatamoverSelMask) +{ + UNUSED_PARA(device); + UNUSED_PARA(rxDatamoverSelMask); + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + return recoveryAction; +} + +int32_t adi_fpga9025_RxSamplesSet(adi_fpga9025_Device_t* device, + uint32_t rxDataMoverSelMask, + uint32_t numSamples) +{ + UNUSED_PARA(rxDataMoverSelMask); + UNUSED_PARA(numSamples); + //TODO: implement this + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_tdd.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_tdd.c new file mode 100644 index 0000000..5f795c5 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_tdd.c @@ -0,0 +1,1039 @@ +/** + * \file: adi_fpga9025_tdd.c + * + * \brief Contains top level tdd fpga9025 related functions + * + * FPGA9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9025_tdd.h" +#include "adi_fpga9025.h" +#include "../../private/include/fpga9025_tdd.h" +#include "../../private/include/fpga9025_bf_tdd_dp_ctrl.h" +#include "../../private/include/fpga9025_bf_tdd_enable_ctrl.h" +#include "../../private/include/fpga9025_bf_tdd_frame_cnt.h" +#include "../../private/include/fpga9025_bf_orx_pin_encode_tokelau.h" + +#define ADI_FPGA9025_TDDENABLECTRL_CNT 24 +#define ADI_FPGA9025_TDDDATAPATHCTRL_CNT 5 + +static const fpga9025_BfTddEnableCtrlChanAddr_e enableCtrlAddrArray[ADI_FPGA9025_TDDENABLECTRL_CNT] = +{ + FPGA9025_BF_TDD_ENABLE_CONTROL_RX1, + FPGA9025_BF_TDD_ENABLE_CONTROL_RX2, + FPGA9025_BF_TDD_ENABLE_CONTROL_RX3, + FPGA9025_BF_TDD_ENABLE_CONTROL_RX4, + FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1, + FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2, + FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3, + FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX1, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX2, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX3, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX4, + FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1, + FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2, + FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3, + FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4, + FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4 +}; + +static const fpga9025_BfTddDpCtrlChanAddr_e datapathctrlAddrArray[ADI_FPGA9025_TDDDATAPATHCTRL_CNT] = +{ + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_0, + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_1, + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_2, + FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_0, + FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_1 +}; + +int32_t adi_fpga9025_TddInit(adi_fpga9025_Device_t* device, + adi_fpga_TddStateMachine_t* fpgaTddStateMachine) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + fpgaTddStateMachine); + + /* Frame Counter module setup */ + if (fpgaTddStateMachine->loopCount > 0) + { + recoveryAction = fpga9025_TddFrameCntLoopCountEnBfSet(device, + FPGA9025_BF_TDD_FRAME_COUNTER, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to loop_count_en bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = fpga9025_TddFrameCntLoopCountBfSet(device, + FPGA9025_BF_TDD_FRAME_COUNTER, + fpgaTddStateMachine->loopCount); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to loop_count_en bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddFrameCntTriggerBfSet(device, + FPGA9025_BF_TDD_FRAME_COUNTER, + fpgaTddStateMachine->syncExtTrig); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to loop_count bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddFrameCntEndValueBfSet(device, + FPGA9025_BF_TDD_FRAME_COUNTER, + fpgaTddStateMachine->frameCount); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to End_value bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Enable Control module setup */ + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->rx1EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_RX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->rx2EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_RX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->rx3EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_RX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->rx4EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_RX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->orx1EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->orx2EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->orx3EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->orx4EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->tx1EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->tx2EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->tx3EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->tx4EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->tx1ToOrx1EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->tx2ToOrx1EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->tx1ToOrx2EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->tx2ToOrx2EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->tx3ToOrx3EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->tx4ToOrx3EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->tx3ToOrx4EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->tx4ToOrx4EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->extTrig1, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->extTrig2, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->extTrig3, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleSet(device, + &fpgaTddStateMachine->extTrig4, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Datapath control module setup */ + recoveryAction = fpga9025_TddDpCtrlEnableBitBfSet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_0, + fpgaTddStateMachine->rxDatapath0.enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_TddDpCtrlStartValueBfSet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_0, + fpgaTddStateMachine->rxDatapath0.startValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddDpCtrlEnableBitBfSet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_1, + fpgaTddStateMachine->rxDatapath1.enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_TddDpCtrlStartValueBfSet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_1, + fpgaTddStateMachine->rxDatapath1.startValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddDpCtrlEnableBitBfSet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_2, + fpgaTddStateMachine->rxDatapath2.enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_TddDpCtrlStartValueBfSet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_2, + fpgaTddStateMachine->rxDatapath2.startValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddDpCtrlEnableBitBfSet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_0, + fpgaTddStateMachine->txDatapath0.enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_TddDpCtrlStartValueBfSet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_0, + fpgaTddStateMachine->txDatapath0.startValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddDpCtrlEnableBitBfSet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_1, + fpgaTddStateMachine->txDatapath1.enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_TddDpCtrlStartValueBfSet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_1, + fpgaTddStateMachine->txDatapath1.startValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_TddInitGet(adi_fpga9025_Device_t* device, + adi_fpga_TddStateMachine_t* fpgaTddStateMachine) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + fpgaTddStateMachine); + + recoveryAction = fpga9025_TddFrameCntLoopCountBfGet(device, + FPGA9025_BF_TDD_FRAME_COUNTER, + &fpgaTddStateMachine->loopCount); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to loop_count_en bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddFrameCntTriggerBfGet(device, + FPGA9025_BF_TDD_FRAME_COUNTER, + &fpgaTddStateMachine->syncExtTrig); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to loop_count bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddFrameCntEndValueBfGet(device, + FPGA9025_BF_TDD_FRAME_COUNTER, + &fpgaTddStateMachine->frameCount); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to End_value bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Enable Control module setup */ + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->rx1EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_RX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->rx2EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_RX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->rx3EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_RX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->rx4EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_RX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->orx1EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_ORX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->orx2EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_ORX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->orx3EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_ORX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->orx4EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_ORX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->tx1EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->tx2EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->tx3EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->tx4EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->tx1ToOrx1EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->tx2ToOrx1EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX1); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->tx1ToOrx2EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX1_TO_ORX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->tx2ToOrx2EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX2_TO_ORX2); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->tx3ToOrx3EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->tx4ToOrx3EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX3); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->tx3ToOrx4EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX3_TO_ORX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->tx4ToOrx4EnableControl, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_TX4_TO_ORX4); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->extTrig1, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_EXT1); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->extTrig2, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_EXT2); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->extTrig3, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_EXT3); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableControlModuleGet(device, + &fpgaTddStateMachine->extTrig4, + (uint32_t)FPGA9025_BF_TDD_ENABLE_CONTROL_EXT4); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Datapath control module read */ + recoveryAction = fpga9025_TddDpCtrlEnableBitBfGet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_0, + &fpgaTddStateMachine->rxDatapath0.enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_TddDpCtrlStartValueBfGet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_0, + &fpgaTddStateMachine->rxDatapath0.startValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddDpCtrlEnableBitBfGet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_1, + &fpgaTddStateMachine->rxDatapath1.enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_TddDpCtrlStartValueBfGet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_1, + &fpgaTddStateMachine->rxDatapath1.startValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddDpCtrlEnableBitBfGet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_2, + &fpgaTddStateMachine->rxDatapath2.enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_TddDpCtrlStartValueBfGet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_RX_DP_2, + &fpgaTddStateMachine->rxDatapath2.startValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddDpCtrlEnableBitBfGet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_0, + &fpgaTddStateMachine->txDatapath0.enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_TddDpCtrlStartValueBfGet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_0, + &fpgaTddStateMachine->txDatapath0.startValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddDpCtrlEnableBitBfGet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_1, + &fpgaTddStateMachine->txDatapath1.enable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_TddDpCtrlStartValueBfGet(device, + FPGA9025_BF_TDD_DATAPATH_CONTROL_TX_DP_1, + &fpgaTddStateMachine->txDatapath1.startValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control start bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_TddEnable(adi_fpga9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + recoveryAction = fpga9025_TddFrameCntEnableBfSet(device, + FPGA9025_BF_TDD_FRAME_COUNTER, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_TddDisable(adi_fpga9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t i = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + recoveryAction = fpga9025_TddFrameCntEnableBfSet(device, + FPGA9025_BF_TDD_FRAME_COUNTER, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddFrameCntLoopCountEnBfSet(device, + FPGA9025_BF_TDD_FRAME_COUNTER, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to loop_count_en bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* Disable the enable control modules */ + for (i = 0; i < ADI_FPGA9025_TDDENABLECTRL_CNT; i++) + { + recoveryAction = fpga9025_TddEnableCtrlEnableBfSet(device, + enableCtrlAddrArray[i], + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Enable Control module enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_TddEnableCtrlSecEnableBfSet(device, + enableCtrlAddrArray[i], + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Secondary Enable Control module enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Disable the datapath control modules */ + for (i = 0; i < ADI_FPGA9025_TDDDATAPATHCTRL_CNT; i++) + { + recoveryAction = fpga9025_TddDpCtrlEnableBitBfSet(device, + datapathctrlAddrArray[i], + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to Datapath Control enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_TddDataGate(adi_fpga9025_Device_t* device) +{ + UNUSED_PARA(device); + //TODO: implement this + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + return recoveryAction; +} + +int32_t adi_fpga9025_TddEnablesAssertSet(adi_fpga9025_Device_t* device, + uint32_t fpgaTddEnables) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t i = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + /* Set the enable control modules */ + for (i = 0; i < ADI_FPGA9025_TDDENABLECTRL_CNT; i++) + { + recoveryAction = fpga9025_TddEnableCtrlManualEnableBfSet(device, + enableCtrlAddrArray[i], + (uint8_t)((fpgaTddEnables >> i) & 1)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to manual enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + return recoveryAction; +} + +int32_t adi_fpga9025_TddEnablesAssertGet(adi_fpga9025_Device_t* device, + uint32_t* fpgaTddEnables) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + int32_t i = 0; + uint8_t enableRead = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + fpgaTddEnables); + + *fpgaTddEnables = 0; + + /* Get the enable control modules */ + for (i = 0; i < ADI_FPGA9025_TDDENABLECTRL_CNT; i++) + { + recoveryAction = fpga9025_TddEnableCtrlManualEnableBfGet(device, + enableCtrlAddrArray[i], + &enableRead); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to manual enable bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + *fpgaTddEnables |= ((uint32_t)enableRead & 1) << i; + } + + return recoveryAction; +} + +int32_t adi_fpga9025_TddOrxPinCfgSet(adi_fpga9025_Device_t* device, + adi_fpga9025_OrxPinEncodeCfg_t* orxPinEncodeCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + orxPinEncodeCfg); + + recoveryAction = fpga9025_OrxPinEncodeTokelauModeSelectBfSet(device, + FPGA9025_BF_TDD_ORX_PIN_ENCODE, + orxPinEncodeCfg->modeSelect); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_OrxPinEncodeTokelauFastSwitchingEnableBfSet(device, + FPGA9025_BF_TDD_ORX_PIN_ENCODE, + orxPinEncodeCfg->fastSwitchingEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_OrxPinEncodeTokelauMode1aOrxSelectLowBfSet(device, + FPGA9025_BF_TDD_ORX_PIN_ENCODE, + orxPinEncodeCfg->mode1aOrxSelectLow); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_OrxPinEncodeTokelauMode1aOrxSelectHighBfSet(device, + FPGA9025_BF_TDD_ORX_PIN_ENCODE, + orxPinEncodeCfg->mode1aOrxSelectHigh); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_OrxPinEncodeTokelauMode3OrxSelectBfSet(device, + FPGA9025_BF_TDD_ORX_PIN_ENCODE, + orxPinEncodeCfg->mode3OrxSelect); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_OrxPinEncodeTokelauOrxSelectSetupTimeBfSet(device, + FPGA9025_BF_TDD_ORX_PIN_ENCODE, + orxPinEncodeCfg->orxSelectSetupTime - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_OrxPinEncodeTokelauOrxEnableHighTimeBfSet(device, + FPGA9025_BF_TDD_ORX_PIN_ENCODE, + orxPinEncodeCfg->orxEnableHighTime - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_OrxPinEncodeTokelauOrxEnableLowTimeBfSet(device, + FPGA9025_BF_TDD_ORX_PIN_ENCODE, + orxPinEncodeCfg->orxEnableLowTime - 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_TddOrxPinCfgGet(adi_fpga9025_Device_t* device, + adi_fpga9025_OrxPinEncodeCfg_t* orxPinEncodeCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint16_t rawRegisterValue = 0; + uint8_t modeSelectReadback = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + orxPinEncodeCfg); + + recoveryAction = fpga9025_OrxPinEncodeTokelauModeSelectBfGet(device, + FPGA9025_BF_TDD_ORX_PIN_ENCODE, + &modeSelectReadback); + orxPinEncodeCfg->modeSelect = (adi_fpga9025_OrxPinEncodeModes_e)modeSelectReadback; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_OrxPinEncodeTokelauFastSwitchingEnableBfGet(device, + FPGA9025_BF_TDD_ORX_PIN_ENCODE, + &orxPinEncodeCfg->fastSwitchingEnable); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_OrxPinEncodeTokelauMode1aOrxSelectLowBfGet(device, + FPGA9025_BF_TDD_ORX_PIN_ENCODE, + &orxPinEncodeCfg->mode1aOrxSelectLow); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_OrxPinEncodeTokelauMode1aOrxSelectHighBfGet(device, + FPGA9025_BF_TDD_ORX_PIN_ENCODE, + &orxPinEncodeCfg->mode1aOrxSelectHigh); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_OrxPinEncodeTokelauMode3OrxSelectBfGet(device, + FPGA9025_BF_TDD_ORX_PIN_ENCODE, + &orxPinEncodeCfg->mode3OrxSelect); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_OrxPinEncodeTokelauOrxSelectSetupTimeBfGet(device, + FPGA9025_BF_TDD_ORX_PIN_ENCODE, + &rawRegisterValue); + orxPinEncodeCfg->orxSelectSetupTime = rawRegisterValue + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_OrxPinEncodeTokelauOrxEnableHighTimeBfGet(device, + FPGA9025_BF_TDD_ORX_PIN_ENCODE, + &rawRegisterValue); + orxPinEncodeCfg->orxEnableHighTime = rawRegisterValue + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_OrxPinEncodeTokelauOrxEnableLowTimeBfGet(device, + FPGA9025_BF_TDD_ORX_PIN_ENCODE, + &rawRegisterValue); + orxPinEncodeCfg->orxEnableLowTime = rawRegisterValue + 1; + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + recoveryAction, + NULL, + "Could not write to mode select bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_tx.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_tx.c new file mode 100644 index 0000000..c47d07e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_tx.c @@ -0,0 +1,1500 @@ +/** + * \file: adi_fpga9025_tx.c + * + * \brief Contains top level tx fpga9025 related functions + * + * FPGA9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9025_user.h" +#include "adi_fpga9025_tx.h" +#include "adi_fpga9025_error.h" +#include "../../private/include/fpga9025_bf_dp_tollgate.h" +#include "../../private/include/fpga9025_bf_dp_tx_dma.h" +#include "../../private/include/fpga9025_bf_dp_capture_control.h" + +int32_t adi_fpga9025_TxTollgateSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + adi_fpga9025_TxTollgateCfg_t* tollGateCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTollgateChanAddr_e instanceAddress = FPGA9025_BF_DP_TOLLGATE_TX_0; + uint32_t i = 0; + adi_fpga9025_TxDatamoverSel_e dataMoverSel = ADI_FPGA9025_TX_DATAMOVER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + tollGateCfg); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txDataMoverSelMask, + "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_TX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_TxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_TX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_TX_0; + break; + case ADI_FPGA9025_TX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = fpga9025_DpTollgateEdgeLevelBfSet(device, + instanceAddress, + tollGateCfg->tollGateEdgeOrLvl); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to detection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTollgateHighRisingLowFallingBfSet(device, + instanceAddress, + tollGateCfg->tollGateHiRiseOrLoFall); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to polarity register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTollgateTriggerSelectBfSet(device, + instanceAddress, + (uint32_t)tollGateCfg->tollGateTrigSource); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to selection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_TxTollgateGet(adi_fpga9025_Device_t* device, + adi_fpga9025_TxDatamoverSel_e txDataMoverSel, + adi_fpga9025_TxTollgateCfg_t* tollGateCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTollgateChanAddr_e baseAddress = FPGA9025_BF_DP_TOLLGATE_TX_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + tollGateCfg); + + switch (txDataMoverSel) + { + case ADI_FPGA9025_TX_DATAMOVER_0: + baseAddress = FPGA9025_BF_DP_TOLLGATE_TX_0; + break; + case ADI_FPGA9025_TX_DATAMOVER_1: + baseAddress = FPGA9025_BF_DP_TOLLGATE_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txDataMoverSel, + "Invalid datamover selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + recoveryAction = fpga9025_DpTollgateEdgeLevelBfGet(device, + baseAddress, + &tollGateCfg->tollGateEdgeOrLvl); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to detection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTollgateHighRisingLowFallingBfGet(device, + baseAddress, + &tollGateCfg->tollGateHiRiseOrLoFall); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to polarity register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTollgateTriggerSelectBfGet(device, + baseAddress, + (uint32_t *)&tollGateCfg->tollGateTrigSource); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to selection register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_TxTollgateResetSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + uint8_t resetVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTollgateChanAddr_e instanceAddress = FPGA9025_BF_DP_TOLLGATE_TX_0; + uint32_t i = 0; + adi_fpga9025_TxDatamoverSel_e dataMoverSel = ADI_FPGA9025_TX_DATAMOVER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_TX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_TxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_TX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_TX_0; + break; + case ADI_FPGA9025_TX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = fpga9025_DpTollgateResetTollgateBfSet(device, + instanceAddress, + resetVal); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to reset register"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_TxTollgateResetGet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + uint8_t* resetVal) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTollgateChanAddr_e instanceAddress = FPGA9025_BF_DP_TOLLGATE_TX_0; + uint32_t i = 0; + adi_fpga9025_TxDatamoverSel_e dataMoverSel = ADI_FPGA9025_TX_DATAMOVER_0; + uint8_t resetBitRead = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + resetVal); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + *resetVal = 0; + + for (i = 0; i < ADI_FPGA9025_NUM_OF_TX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_TxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_TX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_TX_0; + break; + case ADI_FPGA9025_TX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = fpga9025_DpTollgateResetTollgateBfGet(device, + instanceAddress, + &resetBitRead); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read from reset register"); + ADI_ERROR_RETURN(device->common.error.newAction); + + *resetVal |= (resetBitRead & 0x01) << i; + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_TxDmaSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + adi_fpga9025_TxDmaCfg_t* txDmaCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTxDmaChanAddr_e instanceAddress = FPGA9025_BF_DP_DMA_TX_0; + uint32_t i = 0; + adi_fpga9025_TxDatamoverSel_e dataMoverSel = ADI_FPGA9025_TX_DATAMOVER_0; + uint32_t tempWorkAround = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + txDmaCfg); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_TX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_TxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_TX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_DMA_TX_0; + break; + case ADI_FPGA9025_TX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_DMA_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* TODO: start address could be changed at runtime by this function, and this length check is not enough to ensure RAM buffers do not overlap */ + if (txDmaCfg->length > ADI_FPGA9025_TX_DMA_SIZE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "FPGA Tx DMA length too large for RAM buffer area"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = fpga9025_DpTxDmaEnableEnhancedModeBfSet(device, + instanceAddress, + txDmaCfg->enableEnhancedMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write enableEnhancedMode bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaEnableSgBfSet(device, + instanceAddress, + txDmaCfg->enableSg); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write enableSg bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaLengthBfSet(device, + instanceAddress, + txDmaCfg->length); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write length bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaSqFirstDescriptorBfSet(device, + instanceAddress, + txDmaCfg->sgFirstDescriptor); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write sgFirstDescriptor bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* todo: writing to this seems to be clearing the status register. debug later */ + // recoveryAction = fpga9025_DpTxDmaSgLastDescriptorBfSet(device, instanceAddress, txDmaCfg->sgLastDescriptor); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9025_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write sgLastDescriptor bitfield"); + // ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_hal_BbicRegisterRead(device->common.devHalInfo, + instanceAddress + 0x2C, + &tempWorkAround); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + recoveryAction, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + spicrAddress, + "Error"); + ADI_ERROR_RETURN(device->common.error.newAction); + tempWorkAround &= (0xFFFF0000); + tempWorkAround |= (0x4000); + recoveryAction = adi_hal_BbicRegisterWrite(device->common.devHalInfo, + instanceAddress + 0x2C, + tempWorkAround); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + recoveryAction, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + spissrAddress, + "Error selecting all Tokelau devices"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaSimpleStartAddrBfSet(device, + instanceAddress, + (txDmaCfg->simpleStartAddr & 0x00000000FFFFFFFF)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write simpleStartAddr bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaSimpleStartAddrMswBfSet(device, + instanceAddress, + (txDmaCfg->simpleStartAddr >> 32)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write simpleStartAddr bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaValidDataWidthStreamBfSet(device, + instanceAddress, + txDmaCfg->validDataWidthStream); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write validDataWidthStream bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaContinuousBfSet(device, + instanceAddress, + txDmaCfg->continuous); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write continuous bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_TxDmaInit(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + adi_fpga9025_TxDmaCfg_t* txDmaCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTxDmaChanAddr_e instanceAddress = FPGA9025_BF_DP_DMA_TX_0; + uint32_t i = 0; + adi_fpga9025_TxDatamoverSel_e dataMoverSel = ADI_FPGA9025_TX_DATAMOVER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + txDmaCfg); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_TX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_TxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_TX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_DMA_TX_0; + break; + case ADI_FPGA9025_TX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_DMA_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = fpga9025_DpTxDmaEnableEnhancedModeBfSet(device, + instanceAddress, + txDmaCfg->enableEnhancedMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write enableEnhancedMode bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaEnableSgBfSet(device, + instanceAddress, + txDmaCfg->enableSg); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write enableSg bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaSqFirstDescriptorBfSet(device, + instanceAddress, + txDmaCfg->sgFirstDescriptor); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write sgFirstDescriptor bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* todo: writing to this seems to be clearing the status register. debug later */ + // recoveryAction = fpga9025_DpTxDmaSgLastDescriptorBfSet(device, instanceAddress, txDmaCfg->sgLastDescriptor); + // ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_API, ADI_FPGA9025_ERR_REGISTER_IO_FAIL, recoveryAction, NULL, "Could not write sgLastDescriptor bitfield"); + // ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaSimpleStartAddrBfSet(device, + instanceAddress, + (txDmaCfg->simpleStartAddr & 0x00000000FFFFFFFF)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write simpleStartAddr bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaSimpleStartAddrMswBfSet(device, + instanceAddress, + (txDmaCfg->simpleStartAddr >> 32)); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write simpleStartAddr bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaValidDataWidthStreamBfSet(device, + instanceAddress, + txDmaCfg->validDataWidthStream); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write validDataWidthStream bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_TxDmaGet(adi_fpga9025_Device_t* device, + adi_fpga9025_TxDatamoverSel_e txDataMoverSel, + adi_fpga9025_TxDmaCfg_t* txDmaCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTxDmaChanAddr_e baseAddress = FPGA9025_BF_DP_DMA_TX_0; + uint32_t addressReadValue = 0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + txDmaCfg); + + switch (txDataMoverSel) + { + case ADI_FPGA9025_TX_DATAMOVER_0: + baseAddress = FPGA9025_BF_DP_DMA_TX_0; + break; + case ADI_FPGA9025_TX_DATAMOVER_1: + baseAddress = FPGA9025_BF_DP_DMA_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txDataMoverSel, + "Invalid datamover selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + recoveryAction = fpga9025_DpTxDmaActiveBfGet(device, + baseAddress, + &txDmaCfg->active); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read active bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaCompleteBfGet(device, + baseAddress, + &txDmaCfg->complete); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read complete bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaEnableEnhancedModeBfGet(device, + baseAddress, + &txDmaCfg->enableEnhancedMode); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read enableEnhancedMode bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaEnableSgBfGet(device, + baseAddress, + &txDmaCfg->enableSg); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read enableSg bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaHaltCompleteBfGet(device, + baseAddress, + &txDmaCfg->haltComplete); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read haltComplete bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaLengthBfGet(device, + baseAddress, + &txDmaCfg->length); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read length bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaUnderflowBfGet(device, + baseAddress, + &txDmaCfg->underflow); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read underflow bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaRunStopBfGet(device, + baseAddress, + &txDmaCfg->runStop); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read runStop bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaContinuousBfGet(device, + baseAddress, + &txDmaCfg->continuous); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read continuous bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaSqFirstDescriptorBfGet(device, + baseAddress, + &txDmaCfg->sgFirstDescriptor); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read sgFirstDescriptor bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaSgLastDescriptorBfGet(device, + baseAddress, + &txDmaCfg->sgLastDescriptor); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read sgLastDescriptor bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTxDmaSimpleStartAddrBfGet(device, + baseAddress, + &addressReadValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read simpleStartAddr bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + txDmaCfg->simpleStartAddr = addressReadValue; + + recoveryAction = fpga9025_DpTxDmaSimpleStartAddrMswBfGet(device, + baseAddress, + &addressReadValue); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read simpleStartAddrMsw bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + txDmaCfg->simpleStartAddr |= (uint64_t)addressReadValue << 32; + + recoveryAction = fpga9025_DpTxDmaValidDataWidthStreamBfGet(device, + baseAddress, + &txDmaCfg->validDataWidthStream); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read validDataWidthStream bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_TxModeSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + adi_fpga9025_TxDatamoverMode_e txMode) +{ + UNUSED_PARA(txDataMoverSelMask); + UNUSED_PARA(txMode); + //TODO: implement this + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} + +int32_t adi_fpga9025_TxModeGet(adi_fpga9025_Device_t* device, + uint8_t* transmitModeMask) +{ + UNUSED_PARA(transmitModeMask); + //TODO: implement this + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} + +int32_t adi_fpga9025_TxTollgateTriggerSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + adi_fpga9025_TxTollgateTrigSources_e triggerSelect) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTollgateChanAddr_e instanceAddress = FPGA9025_BF_DP_TOLLGATE_TX_0; + uint32_t i = 0; + adi_fpga9025_TxDatamoverSel_e dataMoverSel = ADI_FPGA9025_TX_DATAMOVER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_TX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_TxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_TX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_TX_0; + break; + case ADI_FPGA9025_TX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_TOLLGATE_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = adi_fpga9025_TxTollgateResetSet(device, + txDataMoverSelMask, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpTollgateTriggerSelectBfSet(device, + instanceAddress, + (uint32_t)triggerSelect); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to triggerSelect bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_TxTollgateResetSet(device, + txDataMoverSelMask, + 0); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_TxTollgateTriggerGet(adi_fpga9025_Device_t* device, + adi_fpga9025_TxDatamoverSel_e txDataMoverSel, + adi_fpga9025_TxTollgateTrigSources_e* triggerSelect) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTollgateChanAddr_e baseAddress = FPGA9025_BF_DP_TOLLGATE_TX_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + triggerSelect); + + switch (txDataMoverSel) + { + case ADI_FPGA9025_TX_DATAMOVER_0: + baseAddress = FPGA9025_BF_DP_TOLLGATE_TX_0; + break; + case ADI_FPGA9025_TX_DATAMOVER_1: + baseAddress = FPGA9025_BF_DP_TOLLGATE_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + txDataMoverSel, + "Invalid datamover selected"); + ADI_ERROR_RETURN(device->common.error.newAction); + break; + } + + recoveryAction = fpga9025_DpTollgateTriggerSelectBfGet(device, + baseAddress, + (uint32_t *)triggerSelect); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not read triggerSelect bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_TxDatamoverEnableSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask) +{ + UNUSED_PARA(txDataMoverSelMask); + //TODO: implement this using adi_fpga_txChannelSel_e + //TxChannelSel_t will refer to all modules within a channel + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} + +int32_t adi_fpga9025_TxDatamoverEnableGet(adi_fpga9025_Device_t* device, + uint32_t* txDataMoverSelMask) +{ + UNUSED_PARA(txDataMoverSelMask); + //TODO: implement this using adi_fpga_txChannelSel_e + //TxChannelSel_t will refer to all modules within a channel + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + return recoveryAction; +} + +int32_t adi_fpga9025_TxDataChainConfigure(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + adi_fpga9025_TxTollgateTrigSources_e triggerSelect, + adi_fpga9025_TxDmaCfg_t* txDmaCfg) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* reset capture control */ + recoveryAction = fpga9025_DpCaptureControlResetBfSet(device, + FPGA9025_BF_DP_CAPTURE_CONTROL_TX, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* set trigger */ + recoveryAction = adi_fpga9025_TxTollgateTriggerSet(device, + txDataMoverSelMask, + triggerSelect); + ADI_ERROR_RETURN(device->common.error.newAction); + + /*reset dmas */ + recoveryAction = adi_fpga9025_TxDmaResetSet(device, + txDataMoverSelMask, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* configure dmas */ + recoveryAction = adi_fpga9025_TxDmaSet(device, + txDataMoverSelMask, + txDmaCfg); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* set run_stop bit */ + recoveryAction = adi_fpga9025_TxDmaRunStopSet(device, + txDataMoverSelMask, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* pass token to start dma arbitration */ + recoveryAction = fpga9025_DpCaptureControlResetBfSet(device, + FPGA9025_BF_DP_CAPTURE_CONTROL_TX, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_DpCaptureControlPassTokenBfSet(device, + FPGA9025_BF_DP_CAPTURE_CONTROL_TX, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Capture Control PassToken bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_TxDataChainReset(adi_fpga9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t active = 0; + uint8_t haltComplete = 0; + fpga9025_BfDpTxDmaChanAddr_e instanceAddress = FPGA9025_BF_DP_DMA_TX_0; + uint32_t i = 0; + adi_fpga9025_TxDatamoverSel_e dataMoverSel = ADI_FPGA9025_TX_DATAMOVER_0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* reset */ + recoveryAction = fpga9025_DpCaptureControlDatapathActiveBfSet(device, + FPGA9025_BF_DP_CAPTURE_CONTROL_TX, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to DatapathActive bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + recoveryAction = fpga9025_DpCaptureControlResetBfSet(device, + FPGA9025_BF_DP_CAPTURE_CONTROL_TX, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + for (i = 0; i < ADI_FPGA9025_NUM_OF_TX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_TxDatamoverSel_e)((uint8_t)(1 << i)); + active = 0; + haltComplete = 0; + + switch (dataMoverSel) + { + case ADI_FPGA9025_TX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_DMA_TX_0; + break; + case ADI_FPGA9025_TX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_DMA_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = fpga9025_DpTxDmaActiveBfGet(device, + instanceAddress, + &active); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = adi_fpga9025_TxDmaRunStopSet(device, + dataMoverSel, + 0); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (active == 1) + { + while (haltComplete == 0) + { + recoveryAction = fpga9025_DpTxDmaHaltCompleteBfGet(device, + instanceAddress, + &haltComplete); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Error setting Capture Control Reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + recoveryAction = adi_fpga9025_TxDmaResetSet(device, + dataMoverSel, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adi_fpga9025_TxTollgateResetSet(device, + ADI_FPGA9025_TX_DATAMOVER_ALL, + 1); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_TxDataStart(adi_fpga9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + recoveryAction = fpga9025_DpCaptureControlDatapathActiveBfSet(device, + FPGA9025_BF_DP_CAPTURE_CONTROL_TX, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to DatapathActive bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_TxDataStop(adi_fpga9025_Device_t* device) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + ADI_NULL_DEVICE_PTR_RETURN(device); + + recoveryAction = fpga9025_DpTxDmaRunStopBfSet(device, + FPGA9025_BF_DP_DMA_TX_0, + 0); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write runStop bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + recoveryAction = fpga9025_DpCaptureControlResetBfSet(device, + FPGA9025_BF_DP_CAPTURE_CONTROL_TX, + 1); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_REGISTER_IO_FAIL, + recoveryAction, + NULL, + "Could not write to DatapathActive bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t adi_fpga9025_TxDmaResetSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + uint8_t reset) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTxDmaChanAddr_e instanceAddress = FPGA9025_BF_DP_DMA_TX_0; + uint32_t i = 0; + adi_fpga9025_TxDatamoverSel_e dataMoverSel = ADI_FPGA9025_TX_DATAMOVER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_TX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_TxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_TX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_DMA_TX_0; + break; + case ADI_FPGA9025_TX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_DMA_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = fpga9025_DpTxDmaResetBfSet(device, + instanceAddress, + reset); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + recoveryAction, + NULL, + "Could not write reset bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_TxDmaRunStopSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + uint8_t runStop) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTxDmaChanAddr_e instanceAddress = FPGA9025_BF_DP_DMA_TX_0; + uint32_t i = 0; + adi_fpga9025_TxDatamoverSel_e dataMoverSel = ADI_FPGA9025_TX_DATAMOVER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_TX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_TxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_TX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_DMA_TX_0; + break; + case ADI_FPGA9025_TX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_DMA_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = fpga9025_DpTxDmaRunStopBfSet(device, + instanceAddress, + runStop); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + recoveryAction, + NULL, + "Could not write runStop bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} + +int32_t adi_fpga9025_TxDmaLengthSet(adi_fpga9025_Device_t* device, + uint32_t txDataMoverSelMask, + uint32_t numBytes) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + fpga9025_BfDpTxDmaChanAddr_e instanceAddress = FPGA9025_BF_DP_DMA_TX_0; + uint32_t i = 0; + adi_fpga9025_TxDatamoverSel_e dataMoverSel = ADI_FPGA9025_TX_DATAMOVER_0; + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_API); +#endif + + /* Range checks */ + ADI_NULL_DEVICE_PTR_RETURN(device); + + if (txDataMoverSelMask < 1 || txDataMoverSelMask > 3) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "An invalid tx datamover selected."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + for (i = 0; i < ADI_FPGA9025_NUM_OF_TX_DATAMOVERS; i++) + { + dataMoverSel = (adi_fpga9025_TxDatamoverSel_e)((uint8_t)(1 << i)); + + switch (dataMoverSel) + { + case ADI_FPGA9025_TX_DATAMOVER_0: + instanceAddress = FPGA9025_BF_DP_DMA_TX_0; + break; + case ADI_FPGA9025_TX_DATAMOVER_1: + instanceAddress = FPGA9025_BF_DP_DMA_TX_1; + break; + default: + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "Fatal API error."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (numBytes > ADI_FPGA9025_TX_DMA_SIZE) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + ADI_COMMON_ACT_ERR_RESET_FULL, + NULL, + "FPGA Tx DMA length too large for RAM buffer area"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (((uint32_t)dataMoverSel & txDataMoverSelMask) > 0) + { + recoveryAction = fpga9025_DpTxDmaLengthBfSet(device, + instanceAddress, + numBytes); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_FPGA9025_ERR_API_FAIL, + recoveryAction, + NULL, + "Could not write length bitfield"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_utilities.c b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_utilities.c new file mode 100644 index 0000000..807409a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/public/src/adi_fpga9025_utilities.c @@ -0,0 +1,3104 @@ +/*! +* \file adi_fpga9025_utilities.c +* \brief Contains FPGA9025 API configuration and run-time type definitions for utitility functions +* +* ADRV9025 API Version: 6.4.0.14 +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the FPGA9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#include "adi_fpga9025_user.h" +#include "adi_fpga9025_utilities.h" +#include "adi_fpga9025_rx.h" +#include "adi_fpga9025_tx.h" +#include "adi_common_error.h" +#include "adi_fpga9025_hal.h" +#include "../../private/include/fpga9025_utilities.h" + +int32_t adi_fpga9025_CalculateQpllSettings(adi_fpga9025_Device_t* device, + const uint32_t refClk_kHz, + const uint32_t fastestLaneRate_kHz, + adi_fpga9025_QpllCfg_t* qplls) +{ + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + static const uint8_t ADI_FPGA9025_N_START = 16; + static const uint8_t ADI_FPGA9025_N_END = 160; + uint8_t n = 0; + uint8_t _M[] = {1, 2, 3, 4}; + uint8_t _MLength = 4; + uint8_t m = 0; + uint8_t _D[] = {1, 2, 4, 8, 16, 32}; + uint8_t _DLength = 6; + uint8_t d = 0; + uint32_t qpllVcoFreq_kHz = 0; + uint32_t qpllDivideRatio = 1; + uint32_t qpllVcoOutFreq_kHz = 0; + adi_fpga9025_LaneClkSel_e qpllBand = ADI_FPGA9025_QPLLCLK0; + uint8_t validConfigFound = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + qplls); + + if (fastestLaneRate_kHz < 16375000) + { + qpllDivideRatio = 2; + qplls->qpllClkOutRate = 0; + } + else + { + qpllDivideRatio = 1; + qplls->qpllClkOutRate = 1; + } + + for (m = 0; m < _MLength; m++) + { + for (d = 0; d < _DLength; d++) + { + for (n = ADI_FPGA9025_N_START; n < ADI_FPGA9025_N_END; n++) + { + qpllVcoFreq_kHz = refClk_kHz * n / _M[m]; + qpllVcoOutFreq_kHz = qpllVcoFreq_kHz / qpllDivideRatio; + + if ((qpllVcoFreq_kHz >= 9800000) && (qpllVcoFreq_kHz <= 16375000)) + { + qpllBand = ADI_FPGA9025_QPLLCLK0; + } + else if ((qpllVcoFreq_kHz >= 8000000) && (qpllVcoFreq_kHz <= 13000000)) + { + qpllBand = ADI_FPGA9025_QPLLCLK1; + } + else + { + continue; + } + + if (qpllVcoOutFreq_kHz * 2 / _D[d] == fastestLaneRate_kHz) + { + qplls->mVal = _M[m]; + qplls->nVal = n; + qplls->band = qpllBand; + qplls->qpllVco_kHz = qpllVcoFreq_kHz; + qplls->qpllVcoOut_kHz = qpllVcoOutFreq_kHz; + + validConfigFound = 1; + } + } + } + } + + if (validConfigFound == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Could not find a valid configuration for qpll"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = fpga9025_QpllDrpCfg(device, + refClk_kHz, + qplls->qpllVco_kHz, + (qplls->qpllClkOutRate == 0 ? 2 : 1)); + return recoveryAction; +} + +int32_t adi_fpga9025_CalculateQpllDivisor(adi_fpga9025_Device_t* device, + uint32_t qpllVcoFreq_kHz, + const uint32_t desiredLaneRate_kHz, + uint8_t* dVal) +{ + uint8_t _D[] = {1, 2, 4, 8, 16}; + uint8_t _DLength = 5; + uint8_t d = 0; + uint8_t desiredDVal = 1; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + dVal); + + /* Prevent divide by 0 */ + if (desiredLaneRate_kHz == 0) + { + *dVal = 1; /* Return valid divide by 1 setting */ + return recoveryAction; + } + else + { + desiredDVal = (uint8_t)(qpllVcoFreq_kHz / desiredLaneRate_kHz); + } + + for (d = 0; d < _DLength; d++) + { + if (desiredDVal == _D[d]) + { + *dVal = _D[d]; + return recoveryAction; + } + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Desired PLL divisor invalid"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return device->common.error.newAction; +} + +int32_t adi_fpga9025_CalculateMmcmSettings(adi_fpga9025_Device_t* device, + const uint32_t refClk_kHz, + adi_fpga9025_MmcmCfg_t* mmcmConfig) +{ + uint32_t mmcmVcoFreq_kHz = 0; + uint32_t m; + uint32_t d; + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + + ADI_NULL_DEVICE_PTR_RETURN(device); + + ADI_NULL_PTR_RETURN(&device->common, + mmcmConfig); + + for (m = 0; m < ADI_FPGA9025_NUM_MMCM_OUTPUT_CLOCKS; m++) + { + if (mmcmConfig->outputClkFreq_kHz[m] == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Cannot have a 0 value for any output clocks in mmcm"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* find an m & d value that works for all output clocks */ + for (d = 1; d < 256; d++) + { + for (m = 255; m > 0; m--) + { + mmcmVcoFreq_kHz = refClk_kHz * m / d; + + if (mmcmVcoFreq_kHz > 1600000 || mmcmVcoFreq_kHz < 600000) + { + continue; + } + + /* with the current m & d, make sure the output clocks can be achieved within the channel divider limits */ + if (((mmcmVcoFreq_kHz % mmcmConfig->outputClkFreq_kHz[0]) == 0) && ((mmcmVcoFreq_kHz % mmcmConfig->outputClkFreq_kHz[1]) == 0) && ((mmcmVcoFreq_kHz + % mmcmConfig->outputClkFreq_kHz[2]) == 0) && + ((mmcmVcoFreq_kHz % mmcmConfig->outputClkFreq_kHz[3]) == 0) && ((mmcmVcoFreq_kHz % mmcmConfig->outputClkFreq_kHz[4]) == 0) && ((mmcmVcoFreq_kHz + % mmcmConfig->outputClkFreq_kHz[5]) == 0) && + ((mmcmVcoFreq_kHz % mmcmConfig->outputClkFreq_kHz[6]) == 0) && + + ((mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[0]) < 256) && ((mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[1]) < 256) && (( + mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[2]) < 256) && + ((mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[3]) < 256) && ((mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[4]) < 256) && (( + mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[5]) < 256) && + ((mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[6]) < 256)) + { + mmcmConfig->mVal = m; + mmcmConfig->dVal = d; + mmcmConfig->outputClkDiv[0] = mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[0]; + mmcmConfig->outputClkDiv[1] = mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[1]; + mmcmConfig->outputClkDiv[2] = mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[2]; + mmcmConfig->outputClkDiv[3] = mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[3]; + mmcmConfig->outputClkDiv[4] = mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[4]; + mmcmConfig->outputClkDiv[5] = mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[5]; + mmcmConfig->outputClkDiv[6] = mmcmVcoFreq_kHz / mmcmConfig->outputClkFreq_kHz[6]; + + return recoveryAction; + } + } + } + + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "Could not find a valid configuration for mmcm"); + ADI_ERROR_RETURN(device->common.error.newAction); + + return recoveryAction; +} + +int32_t static fpga9025_SerializerCfg(adi_fpga9025_Device_t* device, + adi_fpga9025_Init_t* fpgaInit, + uint8_t laneIndex, + uint8_t frmOutputIndex, + uint8_t dVal, + uint32_t refClk_kHz, + uint8_t framerSel) +{ + uint32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t fpgaLane = fpgaInit->datapath.pcbSerLaneSwap[laneIndex]; + uint32_t laneRate = fpgaInit->clocks.qpll.qpllVcoOut_kHz * 2 / dVal; + + fpgaInit->datapath.framerCfg[framerSel].laneXbar[fpgaLane] = frmOutputIndex; + + fpgaInit->datapath.serializerCfg[fpgaLane].cpllRefClkSel = 0x01; + fpgaInit->datapath.serializerCfg[fpgaLane].txPllClkSel = fpgaInit->clocks.qpll.band; + fpgaInit->datapath.serializerCfg[fpgaLane].rate = dVal; + fpgaInit->datapath.serializerCfg[fpgaLane].polarity = fpgaInit->datapath.serLanePnInvert[laneIndex]; + fpgaInit->datapath.serializerCfg[fpgaLane].powerDown = 0; + + recoveryAction = fpga9025_SerializerDrpCfg(device, + refClk_kHz, + laneRate, + fpgaInit->clocks.qpll.qpllVcoOut_kHz, + fpgaLane); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID) + { + fpgaInit->datapath.serializerCfg[fpgaLane].precursor = 4; + fpgaInit->datapath.serializerCfg[fpgaLane].diffCtrl = 12; + fpgaInit->datapath.serializerCfg[fpgaLane].postcursor = 16; + fpgaInit->datapath.serializerCfg[fpgaLane].txOutClkSel = 0x2; + fpgaInit->datapath.serializerCfg[fpgaLane].encoder8b10bEnable = 1; + } + else if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + if (laneRate >= 20000000) + { + fpgaInit->datapath.serializerCfg[fpgaLane].precursor = 12; + fpgaInit->datapath.serializerCfg[fpgaLane].diffCtrl = 15; + fpgaInit->datapath.serializerCfg[fpgaLane].postcursor = 0; + } + else + { + fpgaInit->datapath.serializerCfg[fpgaLane].precursor = 0; + fpgaInit->datapath.serializerCfg[fpgaLane].diffCtrl = 15; + fpgaInit->datapath.serializerCfg[fpgaLane].postcursor = 12; + } + fpgaInit->datapath.serializerCfg[fpgaLane].txOutClkSel = 0x5; + fpgaInit->datapath.serializerCfg[fpgaLane].encoder8b10bEnable = 0; + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t static fpga9025_DeserializerCfg(adi_fpga9025_Device_t* device, + adi_fpga9025_Init_t* fpgaInit, + uint8_t adrv9025FramerLanexbarVal, + uint8_t defInputIndex, + uint8_t dVal, + uint32_t refClk_kHz, + uint8_t deframerSel) +{ + uint32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint8_t fpgaLane = fpgaInit->datapath.pcbDesLaneSwap[adrv9025FramerLanexbarVal]; + uint32_t laneRate = fpgaInit->clocks.qpll.qpllVcoOut_kHz * 2 / dVal; + + fpgaInit->datapath.deframerCfg[deframerSel].laneXbar[defInputIndex++] = fpgaInit->datapath.pcbDesLaneSwap[adrv9025FramerLanexbarVal]; + //for each deserializer used by deframer 0 setup its parameters + fpgaInit->datapath.deserializerCfg[fpgaLane].rxPllClkSel = fpgaInit->clocks.qpll.band; + fpgaInit->datapath.deserializerCfg[fpgaLane].rate = dVal; + fpgaInit->datapath.deserializerCfg[fpgaLane].polarity = fpgaInit->datapath.desLanePnInvert[adrv9025FramerLanexbarVal]; + fpgaInit->datapath.deserializerCfg[fpgaLane].powerDown = 0; + + if (laneRate <= ADI_FPGA9025_16_GHZ && laneRate != ADI_FPGA9025_8_GHZ) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeLpmEn = 1; + } + else + { + fpgaInit->datapath.deserializerCfg[fpgaLane].rxDfeLpmEn = 0; + } + + recoveryAction = fpga9025_DeserializerDrpCfg(device, + refClk_kHz, + laneRate, + fpgaInit->clocks.qpll.qpllVcoOut_kHz, + fpgaLane); + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + device->common.error.errCode, + recoveryAction, + NULL, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + if (device->devStateInfo.designId == ADI_FPGA9025_JESD204B_DEVICEID) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].rxOutClkSel = 0x2; + fpgaInit->datapath.deserializerCfg[fpgaLane].encoder8b10bEnable = 1; + } + else if (device->devStateInfo.designId == ADI_FPGA9025_JESD204C_DEVICEID) + { + fpgaInit->datapath.deserializerCfg[fpgaLane].rxOutClkSel = 0x5; + fpgaInit->datapath.deserializerCfg[fpgaLane].encoder8b10bEnable = 0; + } + + return ADI_COMMON_ACT_NO_ACTION; +} + +int32_t static fpga9025_FindValidUnusedClk(uint32_t defrm0CoreClk_kHz, + uint32_t defrm1CoreClk_kHz, + uint32_t defrm2CoreClk_kHz, + uint32_t frm0CoreClk_kHz, + uint32_t frm1CoreClk_kHz) +{ + if (defrm0CoreClk_kHz != 0) + { + return defrm0CoreClk_kHz; + } + else if (defrm1CoreClk_kHz != 0) + { + return defrm1CoreClk_kHz; + } + else if (defrm2CoreClk_kHz != 0) + { + return defrm2CoreClk_kHz; + } + else if (frm0CoreClk_kHz != 0) + { + return frm0CoreClk_kHz; + } + else if (frm1CoreClk_kHz != 0) + { + return frm1CoreClk_kHz; + } + else + { + return 0; + } +} + +int32_t adi_fpga9025_InitConfig(adi_fpga9025_Device_t* device, + adi_fpga9025_SetupFpgaCfg_t* fpgaCfg, + adi_fpga9025_Init_t* fpgaInit) +{ + int32_t i = 0; + + int32_t recoveryAction = ADI_COMMON_ACT_NO_ACTION; + uint32_t fastestLaneRate_kHz = 0; + uint32_t refClk_kHz = fpgaCfg->deviceClk_kHz; + + /* Lane rate declarations */ + uint64_t defrm0LaneRate_kHz = 0; + uint64_t defrm1LaneRate_kHz = 0; + uint64_t defrm2LaneRate_kHz = 0; + uint64_t frm0LaneRate_kHz = 0; + uint64_t frm1LaneRate_kHz = 0; + + /* Framer/Deframer clock rate declarations */ + uint32_t defrm0CoreClk_kHz = 0; // lanerate /40 for JESD204B, lanerate/66 for JESD204C + uint32_t defrm1CoreClk_kHz = 0; + uint32_t defrm2CoreClk_kHz = 0; + uint32_t frm0CoreClk_kHz = 0; // lanerate /40 for JESD204B, lanerate/66 for JESD204C + uint32_t frm1CoreClk_kHz = 0; + uint32_t mmcmUnusedClk_kHz = 0; + + uint8_t jesd204F = 0; + uint8_t adrv9025LanesEnabled = 0; + uint8_t dVal = 0; + + uint8_t defrm0L = 0; + uint8_t defrm1L = 0; + uint8_t defrm2L = 0; + uint8_t frm0L = 0; + uint8_t frm1L = 0; + + uint8_t adrv9025SerLaneIndex = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_NULL_DEVICE_PTR_RETURN(fpgaCfg); + ADI_NULL_PTR_RETURN(&device->common, + fpgaInit); + +#if ADI_FPGA9025_VERBOSE > 0 + ADI_FUNCTION_ENTRY_LOG(&device->common, + ADI_COMMON_LOG_HAL); +#endif + + /* Check that the parameters that could cause divide-by-0 faults */ + if (device->devStateInfo.linkLayerDataWidth == 0 || device->devStateInfo.encodingLowValue == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + NULL, + "FPGA device has not been initialized."); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + if (fpgaCfg->deviceClk_kHz == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + fpgaCfg->deviceClk_kHz, + "deviceClk_kHz should not be 0. Verify init structures are set"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + /* Calculate L */ + for (i = 0; i < 8; i++) + { + defrm0L = (defrm0L + ((fpgaCfg->deframerlink0.lanesEnabled >> i) & 1)); + defrm1L = (defrm1L + ((fpgaCfg->deframerlink1.lanesEnabled >> i) & 1)); + defrm2L = (defrm2L + ((fpgaCfg->deframerlink2.lanesEnabled >> i) & 1)); + frm0L = (frm0L + ((fpgaCfg->framerlink0.lanesEnabled >> i) & 1)); + frm1L = (frm1L + ((fpgaCfg->framerlink1.lanesEnabled >> i) & 1)); + } + + /* init the mmcm settings */ + /* calculate the framer/deframer lane rates in order to determine + a Qpll rate which will support all of them.*/ + if (defrm0L != 0) + { + defrm0LaneRate_kHz = ((uint64_t)fpgaCfg->deframerlink0.iqRate_kHz + * fpgaCfg->deframerlink0.jesd204M + * fpgaCfg->deframerlink0.jesd204Np + * device->devStateInfo.encodingHighValue) / (device->devStateInfo.encodingLowValue * defrm0L); + + defrm0CoreClk_kHz = (uint32_t)(defrm0LaneRate_kHz / device->devStateInfo.linkLayerDataWidth); + } + + if (defrm1L != 0) + { + defrm1LaneRate_kHz = ((uint64_t)fpgaCfg->deframerlink1.iqRate_kHz + * fpgaCfg->deframerlink1.jesd204M + * fpgaCfg->deframerlink1.jesd204Np + * device->devStateInfo.encodingHighValue) / (device->devStateInfo.encodingLowValue * defrm1L); + defrm1CoreClk_kHz = (uint32_t)(defrm1LaneRate_kHz / device->devStateInfo.linkLayerDataWidth); + } + + if (defrm2L != 0) + { + defrm2LaneRate_kHz = ((uint64_t)fpgaCfg->deframerlink2.iqRate_kHz + * fpgaCfg->deframerlink2.jesd204M + * fpgaCfg->deframerlink2.jesd204Np + * device->devStateInfo.encodingHighValue) / (device->devStateInfo.encodingLowValue * defrm2L); + defrm2CoreClk_kHz = (uint32_t)(defrm2LaneRate_kHz / device->devStateInfo.linkLayerDataWidth); + } + + if (frm0L != 0) + { + frm0LaneRate_kHz = ((uint64_t)fpgaCfg->framerlink0.iqRate_kHz + * fpgaCfg->framerlink0.jesd204M + * fpgaCfg->framerlink0.jesd204Np + * device->devStateInfo.encodingHighValue) / (device->devStateInfo.encodingLowValue * frm0L); + frm0CoreClk_kHz = (uint32_t)(frm0LaneRate_kHz / device->devStateInfo.linkLayerDataWidth); + } + + if (frm1L != 0) + { + frm1LaneRate_kHz = ((uint64_t)fpgaCfg->framerlink1.iqRate_kHz + * fpgaCfg->framerlink1.jesd204M + * fpgaCfg->framerlink1.jesd204Np + * device->devStateInfo.encodingHighValue) / (device->devStateInfo.encodingLowValue * frm1L); + frm1CoreClk_kHz = (uint32_t)(frm1LaneRate_kHz / device->devStateInfo.linkLayerDataWidth); + } + + /* init the qpll settings */ + fastestLaneRate_kHz = (uint32_t)(defrm0LaneRate_kHz > defrm1LaneRate_kHz ? defrm0LaneRate_kHz : defrm1LaneRate_kHz); + fastestLaneRate_kHz = (uint32_t)(defrm2LaneRate_kHz > fastestLaneRate_kHz ? defrm2LaneRate_kHz : fastestLaneRate_kHz); + fastestLaneRate_kHz = (uint32_t)(frm0LaneRate_kHz > fastestLaneRate_kHz ? frm0LaneRate_kHz : fastestLaneRate_kHz); + fastestLaneRate_kHz = (uint32_t)(frm1LaneRate_kHz > fastestLaneRate_kHz ? frm1LaneRate_kHz : fastestLaneRate_kHz); + if (fastestLaneRate_kHz == 0) + { + ADI_ERROR_REPORT(&device->common, + ADI_COMMON_ERRSRC_API, + ADI_COMMON_ERR_INV_PARAM, + ADI_COMMON_ACT_ERR_CHECK_PARAM, + serializerCfg->txPllClkSel, + "All lane rates are 0 Gbps (disabled)"); + ADI_ERROR_RETURN(device->common.error.newAction); + } + + recoveryAction = adi_fpga9025_CalculateQpllSettings(device, + refClk_kHz, + fastestLaneRate_kHz, + &fpgaInit->clocks.qpll); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + fpgaInit->clocks.qpll.quadSelect = (ADI_FPGA9025_QPLL_QUAD0 | ADI_FPGA9025_QPLL_QUAD1); /* Default to setting */ + fpgaInit->clocks.qpll.refClkSelect[0] = ADI_FPGA9025_QPLL_GTREFCLK0; + fpgaInit->clocks.qpll.refClkSelect[1] = ADI_FPGA9025_QPLL_GTREFCLK0; + + mmcmUnusedClk_kHz = fpga9025_FindValidUnusedClk(defrm0CoreClk_kHz, + defrm1CoreClk_kHz, + defrm2CoreClk_kHz, + frm0CoreClk_kHz, + frm1CoreClk_kHz); + + /* add the required mmsm setting to support the deserializers and deframers. */ + fpgaInit->clocks.coreMmcm.outputClkFreq_kHz[0] = (defrm0CoreClk_kHz == 0) ? mmcmUnusedClk_kHz : defrm0CoreClk_kHz; + fpgaInit->clocks.coreMmcm.outputClkFreq_kHz[1] = (defrm1CoreClk_kHz == 0) ? mmcmUnusedClk_kHz : defrm1CoreClk_kHz; + fpgaInit->clocks.coreMmcm.outputClkFreq_kHz[2] = (defrm2CoreClk_kHz == 0) ? mmcmUnusedClk_kHz : defrm2CoreClk_kHz; + + /* TODO: FPGA was updated to use frm0 clock for lanes 1-4, and frm1 clk for 4-7. If framer 0 uses all 8 lanes, both clocks must be set */ + fpgaInit->clocks.coreMmcm.outputClkFreq_kHz[3] = (frm0CoreClk_kHz == 0) ? ((frm1CoreClk_kHz == 0) ? mmcmUnusedClk_kHz : frm1CoreClk_kHz) : frm0CoreClk_kHz; + fpgaInit->clocks.coreMmcm.outputClkFreq_kHz[4] = (frm1CoreClk_kHz == 0) ? ((frm0CoreClk_kHz == 0) ? mmcmUnusedClk_kHz : frm0CoreClk_kHz) : frm1CoreClk_kHz; + fpgaInit->clocks.coreMmcm.outputClkFreq_kHz[5] = fastestLaneRate_kHz / device->devStateInfo.linkLayerDataWidth; /* TDD FSM frequency */ + device->devStateInfo.tddStateMachineClk_kHz = fpgaInit->clocks.coreMmcm.outputClkFreq_kHz[5]; + fpgaInit->clocks.coreMmcm.outputClkFreq_kHz[6] = mmcmUnusedClk_kHz; /* unused */ + + recoveryAction = adi_fpga9025_CalculateMmcmSettings(device, + refClk_kHz, + &fpgaInit->clocks.coreMmcm); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + /* init the serializer/deserializer settings */ + /* Power down all deserializer lanes in FPGA */ + for (i = 0; i < ADI_FPGA9025_NUM_LANES; i++) + { + fpgaInit->datapath.deserializerCfg[i].powerDown = 3; + fpgaInit->datapath.deserializerCfg[i].rate = 1; + } + + recoveryAction = adi_fpga9025_CalculateQpllDivisor(device, + fpgaInit->clocks.qpll.qpllVcoOut_kHz * 2, + (uint32_t)defrm0LaneRate_kHz, + &dVal); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025LanesEnabled = fpgaCfg->deframerlink0.lanesEnabled; + + /* Power up used lanes */ + uint8_t adrv9025Framer0Lanexbar[8] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; /* Each number specifies the physical ADRV9025 serializer lane */ + /*Add flexibility to handle with different lane mappings of the tranceiver LaneXbar*/ + uint8_t adrv9025Framer0LaneFramer[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + if(fpgaCfg->deframerlink0.serializerLaneCrossbar.lane0FramerOutSel != 4) + { + adrv9025Framer0Lanexbar[0] = 0 ; + adrv9025Framer0LaneFramer[0] = fpgaCfg->deframerlink0.serializerLaneCrossbar.lane0FramerOutSel; + } + if(fpgaCfg->deframerlink0.serializerLaneCrossbar.lane1FramerOutSel != 4) + { + adrv9025Framer0Lanexbar[1] = 1 ; + adrv9025Framer0LaneFramer[1] = fpgaCfg->deframerlink0.serializerLaneCrossbar.lane1FramerOutSel; + } + if(fpgaCfg->deframerlink0.serializerLaneCrossbar.lane2FramerOutSel != 4) + { + adrv9025Framer0Lanexbar[2] = 2 ; + adrv9025Framer0LaneFramer[2] = fpgaCfg->deframerlink0.serializerLaneCrossbar.lane2FramerOutSel; + } + if(fpgaCfg->deframerlink0.serializerLaneCrossbar.lane3FramerOutSel != 4) + { + adrv9025Framer0Lanexbar[3] = 3 ; + adrv9025Framer0LaneFramer[3] = fpgaCfg->deframerlink0.serializerLaneCrossbar.lane3FramerOutSel; + } + uint8_t usedLaneIndex = 0; + uint8_t tempValue = 0; + for (adrv9025SerLaneIndex = 0; adrv9025SerLaneIndex < 8; adrv9025SerLaneIndex++) + { + if ((adrv9025LanesEnabled >> adrv9025SerLaneIndex) & 0x1) + { + if (adrv9025Framer0LaneFramer[adrv9025SerLaneIndex] != usedLaneIndex) + { + for (i = adrv9025SerLaneIndex; i< 8; i++) + { + if (adrv9025Framer0LaneFramer[i] == usedLaneIndex) + { + tempValue = adrv9025Framer0Lanexbar[i]; + adrv9025Framer0Lanexbar[i] = adrv9025Framer0Lanexbar[adrv9025SerLaneIndex] ; + adrv9025Framer0Lanexbar[adrv9025SerLaneIndex] = tempValue; + break; + } + } + } + usedLaneIndex++; + } + } + uint8_t defInputIndex = 0; + for (adrv9025SerLaneIndex = 0; adrv9025SerLaneIndex < 8; adrv9025SerLaneIndex++) + { + if ((adrv9025LanesEnabled >> adrv9025SerLaneIndex) & 0x1) + { + recoveryAction = fpga9025_DeserializerCfg(device, + fpgaInit, + adrv9025Framer0Lanexbar[adrv9025SerLaneIndex], + defInputIndex++, + dVal, + refClk_kHz, + 0); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + recoveryAction = adi_fpga9025_CalculateQpllDivisor(device, + fpgaInit->clocks.qpll.qpllVcoOut_kHz * 2, + (uint32_t)defrm1LaneRate_kHz, + &dVal); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025LanesEnabled = fpgaCfg->deframerlink1.lanesEnabled; + /* Don't reset j from loop above, continue using its value for the next valid lane. */ + + uint8_t adrv9025Framer1Lanexbar[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; /*Each number specifies the physical ADRV9025 serializer lane */ + /*Add flexibility to handle with different lane mappings of the tranceiver LaneXbar*/ + uint8_t adrv9025Framer1LaneFramer[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + if(fpgaCfg->deframerlink1.serializerLaneCrossbar.lane0FramerOutSel != 4) + { + adrv9025Framer1Lanexbar[0] = 0 ; + adrv9025Framer1LaneFramer[0] = fpgaCfg->deframerlink1.serializerLaneCrossbar.lane0FramerOutSel; + } + if(fpgaCfg->deframerlink1.serializerLaneCrossbar.lane1FramerOutSel != 4) + { + adrv9025Framer1Lanexbar[1] = 1 ; + adrv9025Framer1LaneFramer[1] = fpgaCfg->deframerlink1.serializerLaneCrossbar.lane1FramerOutSel; + } + if(fpgaCfg->deframerlink1.serializerLaneCrossbar.lane2FramerOutSel != 4) + { + adrv9025Framer1Lanexbar[2] = 2 ; + adrv9025Framer1LaneFramer[2] = fpgaCfg->deframerlink1.serializerLaneCrossbar.lane2FramerOutSel; + } + if(fpgaCfg->deframerlink1.serializerLaneCrossbar.lane3FramerOutSel != 4) + { + adrv9025Framer1Lanexbar[3] = 3 ; + adrv9025Framer1LaneFramer[3] = fpgaCfg->deframerlink1.serializerLaneCrossbar.lane3FramerOutSel; + } + usedLaneIndex = 0; + tempValue = 0; + for (adrv9025SerLaneIndex = 0; adrv9025SerLaneIndex < 8; adrv9025SerLaneIndex++) + { + if ((adrv9025LanesEnabled >> adrv9025SerLaneIndex) & 0x1) + { + if (adrv9025Framer1LaneFramer[adrv9025SerLaneIndex] != usedLaneIndex) + { + for (i = adrv9025SerLaneIndex; i< 8; i++) + { + if (adrv9025Framer1LaneFramer[i] == usedLaneIndex) + { + tempValue = adrv9025Framer1Lanexbar[i]; + adrv9025Framer1Lanexbar[i] = adrv9025Framer1Lanexbar[adrv9025SerLaneIndex] ; + adrv9025Framer1Lanexbar[adrv9025SerLaneIndex] = tempValue; + } + } + } + usedLaneIndex++; + } + } + defInputIndex = 0; + for (adrv9025SerLaneIndex = 0; adrv9025SerLaneIndex < 8; adrv9025SerLaneIndex++) + { + /* for each deserializer used by deframer 1 setup its parameters */ + if ((adrv9025LanesEnabled >> adrv9025SerLaneIndex) & 0x1) + { + recoveryAction = fpga9025_DeserializerCfg(device, + fpgaInit, + adrv9025Framer1Lanexbar[adrv9025SerLaneIndex], + defInputIndex++, + dVal, + refClk_kHz, + 1); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + recoveryAction = adi_fpga9025_CalculateQpllDivisor(device, + fpgaInit->clocks.qpll.qpllVcoOut_kHz * 2, + (uint32_t)defrm2LaneRate_kHz, + &dVal); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025LanesEnabled = fpgaCfg->deframerlink2.lanesEnabled; + uint8_t adrv9025Framer2Lanexbar[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; /* Each number specifies the physical ADRV9025 serializer lane */ + /*Add flexibility to handle with different lane mappings of the tranceiver LaneXbar*/ + uint8_t adrv9025Framer2LaneFramer[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + + if(fpgaCfg->deframerlink2.serializerLaneCrossbar.lane0FramerOutSel != 4) + { + adrv9025Framer2Lanexbar[0] = 0 ; + adrv9025Framer2LaneFramer[0] = fpgaCfg->deframerlink2.serializerLaneCrossbar.lane0FramerOutSel; + } + if(fpgaCfg->deframerlink2.serializerLaneCrossbar.lane1FramerOutSel != 4) + { + adrv9025Framer2Lanexbar[1] = 1 ; + adrv9025Framer2LaneFramer[0] = fpgaCfg->deframerlink2.serializerLaneCrossbar.lane1FramerOutSel; + } + if(fpgaCfg->deframerlink2.serializerLaneCrossbar.lane2FramerOutSel != 4) + { + adrv9025Framer2Lanexbar[2] = 2 ; + adrv9025Framer2LaneFramer[0] = fpgaCfg->deframerlink2.serializerLaneCrossbar.lane2FramerOutSel; + } + if(fpgaCfg->deframerlink2.serializerLaneCrossbar.lane3FramerOutSel != 4) + { + adrv9025Framer2Lanexbar[3] = 3 ; + adrv9025Framer2LaneFramer[0] = fpgaCfg->deframerlink2.serializerLaneCrossbar.lane3FramerOutSel; + } + usedLaneIndex = 0; + tempValue = 0; + for (adrv9025SerLaneIndex = 0; adrv9025SerLaneIndex < 8; adrv9025SerLaneIndex++) + { + if ((adrv9025LanesEnabled >> adrv9025SerLaneIndex) & 0x1) + { + if (adrv9025Framer2LaneFramer[adrv9025SerLaneIndex] != usedLaneIndex) + { + for (i = adrv9025SerLaneIndex; i< 8; i++) + { + if (adrv9025Framer2LaneFramer[i] == usedLaneIndex) + { + tempValue = adrv9025Framer2Lanexbar[i]; + adrv9025Framer2Lanexbar[i] = adrv9025Framer2Lanexbar[adrv9025SerLaneIndex] ; + adrv9025Framer2Lanexbar[adrv9025SerLaneIndex] = tempValue; + } + } + } + usedLaneIndex++; + } + } + defInputIndex = 0; + for (adrv9025SerLaneIndex = 0; adrv9025SerLaneIndex < 8; adrv9025SerLaneIndex++) + { + /* for each deserializer used by deframer 4 setup its parameters */ + if ((adrv9025LanesEnabled >> adrv9025SerLaneIndex) & 0x1) + { + recoveryAction = fpga9025_DeserializerCfg(device, + fpgaInit, + adrv9025Framer2Lanexbar[adrv9025SerLaneIndex], + defInputIndex++, + dVal, + refClk_kHz, + 2); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* Power down all FPGA serializer lanes */ + for (i = 0; i < ADI_FPGA9025_NUM_LANES; i++) + { + fpgaInit->datapath.serializerCfg[i].powerDown = 3; + fpgaInit->datapath.serializerCfg[i].rate = 1; + + /* Initialize Lane Xbar to 0x1F. 0x1F is the max the lane_x_select bitfield can take before error */ + fpgaInit->datapath.framerCfg[0].laneXbar[i] = 0x1F; + fpgaInit->datapath.framerCfg[1].laneXbar[i] = 0x1F; + } + + recoveryAction = adi_fpga9025_CalculateQpllDivisor(device, + fpgaInit->clocks.qpll.qpllVcoOut_kHz * 2, + (uint32_t)frm0LaneRate_kHz, + &dVal); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + + adrv9025LanesEnabled = fpgaCfg->framerlink0.lanesEnabled; + uint8_t frmOutputIndex = 0; + for (i = 0; i < ADI_FPGA9025_NUM_LANES; i++) + { + /* for each serializer used by framer 0 setup its parameters */ + if ((adrv9025LanesEnabled >> i) & 0x1) + { + recoveryAction = fpga9025_SerializerCfg(device, + fpgaInit, + i, + frmOutputIndex++, + dVal, + refClk_kHz, + 0); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + recoveryAction = adi_fpga9025_CalculateQpllDivisor(device, + fpgaInit->clocks.qpll.qpllVcoOut_kHz * 2, + (uint32_t)frm1LaneRate_kHz, + &dVal); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + adrv9025LanesEnabled = fpgaCfg->framerlink1.lanesEnabled; + frmOutputIndex = 0; + for (i = 0; i < ADI_FPGA9025_NUM_LANES; i++) + { + /* for each serializer used by framer 2 setup its parameters */ + if ((adrv9025LanesEnabled >> i) & 0x1) + { + recoveryAction = fpga9025_SerializerCfg(device, + fpgaInit, + i, + frmOutputIndex++, + dVal, + refClk_kHz, + 1); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + } + } + + /* init the framer/deframer settings */ + + /* set deframer 0 settings */ + if (defrm0L > 0) + { + jesd204F = (fpgaCfg->deframerlink0.jesd204Np * fpgaCfg->deframerlink0.jesd204M * fpgaCfg->deframerlink0.jesd204S) / (8 * defrm0L); + } + + /* Common */ + fpgaInit->datapath.deframerCfg[0].sysRefDelay = 0; + fpgaInit->datapath.deframerCfg[0].subclassV = 1; + fpgaInit->datapath.deframerCfg[0].lanesInUse = (defrm0L == 8) ? 0xFF : + (defrm0L == 4) ? 0x0F : + (defrm0L == 2) ? 0x03 : + (defrm0L == 1) ? 0x01 : 0; + + /* JESD204B */ + fpgaInit->datapath.deframerCfg[0].scramblingEn = fpgaCfg->deframerlink0.scramble; + fpgaInit->datapath.deframerCfg[0].cfgF = (defrm0L > 0) ? jesd204F : 0; + fpgaInit->datapath.deframerCfg[0].cfgK = (uint8_t)fpgaCfg->deframerlink0.jesd204K; + fpgaInit->datapath.deframerCfg[0].rxBufferDly = 0; + fpgaInit->datapath.deframerCfg[0].errReportingDisable = 0; + fpgaInit->datapath.deframerCfg[0].ilaSupportEn = 1; + fpgaInit->datapath.deframerCfg[0].sysRefAlways = 0; + fpgaInit->datapath.deframerCfg[0].sysRefRequiredOnResync = 0; + + /* JESD204C */ + fpgaInit->datapath.deframerCfg[0].enableCmdInterface = 0; + fpgaInit->datapath.deframerCfg[0].enableDataInterface = 1; + fpgaInit->datapath.deframerCfg[0].cfgE = fpgaCfg->deframerlink0.jesd204E; + fpgaInit->datapath.deframerCfg[0].ctrlMetaMode = 0; + fpgaInit->datapath.deframerCfg[0].ctrlRxBufAdv = 0; + fpgaInit->datapath.deframerCfg[0].ctrlRxMBlockTh = 1; + fpgaInit->datapath.deframerCfg[0].ctrlIrq = 0x3FF; /* Enable all interrupts */ + + /* set deframer 0 datamover settings */ + fpgaInit->datapath.rxDmaCfg[0].enableEnhancedMode = 0; + fpgaInit->datapath.rxDmaCfg[0].enableSg = 0; + fpgaInit->datapath.rxDmaCfg[0].simpleStartAddr = ADI_FPGA9025_RX_START_ADDRESS; + fpgaInit->datapath.rxDmaCfg[0].length = ADI_FPGA9025_RX_DMA_SIZE; + fpgaInit->datapath.rxDmaCfg[0].validDataWidthStream = (defrm0L * device->devStateInfo.dmaDataWidth / 32) - 1; + fpgaInit->datapath.rxDmaCfg[0].sgFirstDescriptor = 0; + fpgaInit->datapath.rxDmaCfg[0].sgLastDescriptor = 0; + fpgaInit->datapath.rxDmaCfg[0].runStop = 0; + + /* set deframer 1 settings */ + if (defrm1L > 0) + { + jesd204F = (fpgaCfg->deframerlink1.jesd204Np * fpgaCfg->deframerlink1.jesd204M * fpgaCfg->deframerlink1.jesd204S) / (8 * defrm1L); + } + + /* Common */ + fpgaInit->datapath.deframerCfg[1].sysRefDelay = 0; + fpgaInit->datapath.deframerCfg[1].subclassV = 1; + fpgaInit->datapath.deframerCfg[1].lanesInUse = (defrm1L == 8) ? 0xFF : + (defrm1L == 4) ? 0x0F : + (defrm1L == 2) ? 0x03 : + (defrm1L == 1) ? 0x01 : 0; + + /* JESD204B */ + fpgaInit->datapath.deframerCfg[1].scramblingEn = fpgaCfg->deframerlink1.scramble; + fpgaInit->datapath.deframerCfg[1].cfgF = (defrm1L > 0) ? jesd204F : 0; + fpgaInit->datapath.deframerCfg[1].cfgK = (uint8_t)fpgaCfg->deframerlink1.jesd204K; + fpgaInit->datapath.deframerCfg[1].rxBufferDly = 0; + fpgaInit->datapath.deframerCfg[1].errReportingDisable = 0; + fpgaInit->datapath.deframerCfg[1].ilaSupportEn = 1; + fpgaInit->datapath.deframerCfg[1].sysRefAlways = 0; + fpgaInit->datapath.deframerCfg[1].sysRefRequiredOnResync = 0; + + /* JESD204C */ + fpgaInit->datapath.deframerCfg[1].enableCmdInterface = 0; + fpgaInit->datapath.deframerCfg[1].enableDataInterface = 1; + fpgaInit->datapath.deframerCfg[1].cfgE = fpgaCfg->deframerlink1.jesd204E; + fpgaInit->datapath.deframerCfg[1].ctrlMetaMode = 0; + fpgaInit->datapath.deframerCfg[1].ctrlRxBufAdv = 0; + fpgaInit->datapath.deframerCfg[1].ctrlRxMBlockTh = 1; + fpgaInit->datapath.deframerCfg[1].ctrlIrq = 0x3FF; /* Enable all interrupts */ + + /* set deframer 1 datamover settings */ + fpgaInit->datapath.rxDmaCfg[1].enableEnhancedMode = 0; + fpgaInit->datapath.rxDmaCfg[1].enableSg = 0; + fpgaInit->datapath.rxDmaCfg[1].simpleStartAddr = ADI_FPGA9025_RX_START_ADDRESS + (1 * ADI_FPGA9025_RX_DMA_SIZE); + fpgaInit->datapath.rxDmaCfg[1].length = ADI_FPGA9025_RX_DMA_SIZE; + fpgaInit->datapath.rxDmaCfg[1].validDataWidthStream = (defrm1L * device->devStateInfo.dmaDataWidth / 32) - 1; + fpgaInit->datapath.rxDmaCfg[1].sgFirstDescriptor = 0; + fpgaInit->datapath.rxDmaCfg[1].sgLastDescriptor = 0; + fpgaInit->datapath.rxDmaCfg[1].runStop = 0; + + /* set deframer 2 settings */ + if (defrm2L > 0) + { + jesd204F = (fpgaCfg->deframerlink2.jesd204Np * fpgaCfg->deframerlink2.jesd204M * fpgaCfg->deframerlink2.jesd204S) / (8 * defrm2L); + } + + /* Common */ + fpgaInit->datapath.deframerCfg[2].sysRefDelay = 0; + fpgaInit->datapath.deframerCfg[2].subclassV = 1; + fpgaInit->datapath.deframerCfg[2].lanesInUse = (defrm2L == 8) ? 0xFF : + (defrm2L == 4) ? 0x0F : + (defrm2L == 2) ? 0x03 : + (defrm2L == 1) ? 0x01 : 0; + + /* JESD204B */ + fpgaInit->datapath.deframerCfg[2].scramblingEn = fpgaCfg->deframerlink2.scramble; + fpgaInit->datapath.deframerCfg[2].cfgF = (defrm2L > 0) ? jesd204F : 0; + fpgaInit->datapath.deframerCfg[2].cfgK = (uint8_t)fpgaCfg->deframerlink2.jesd204K; + fpgaInit->datapath.deframerCfg[2].rxBufferDly = 0; + fpgaInit->datapath.deframerCfg[2].errReportingDisable = 0; + fpgaInit->datapath.deframerCfg[2].ilaSupportEn = 1; + fpgaInit->datapath.deframerCfg[2].sysRefAlways = 0; + fpgaInit->datapath.deframerCfg[2].sysRefRequiredOnResync = 0; + + /* JESD204C */ + fpgaInit->datapath.deframerCfg[2].enableCmdInterface = 0; + fpgaInit->datapath.deframerCfg[2].enableDataInterface = 1; + fpgaInit->datapath.deframerCfg[2].cfgE = fpgaCfg->deframerlink2.jesd204E; + fpgaInit->datapath.deframerCfg[2].ctrlMetaMode = 0; + fpgaInit->datapath.deframerCfg[2].ctrlRxBufAdv = 0; + fpgaInit->datapath.deframerCfg[2].ctrlRxMBlockTh = 1; + fpgaInit->datapath.deframerCfg[2].ctrlIrq = 0x3FF; /* Enable all interrupts */ + + /* set deframer 2 datamover settings */ + fpgaInit->datapath.rxDmaCfg[2].enableEnhancedMode = 0; + fpgaInit->datapath.rxDmaCfg[2].enableSg = 0; + fpgaInit->datapath.rxDmaCfg[2].simpleStartAddr = ADI_FPGA9025_RX_START_ADDRESS + (2 * ADI_FPGA9025_RX_DMA_SIZE); + fpgaInit->datapath.rxDmaCfg[2].length = ADI_FPGA9025_RX_DMA_SIZE; + fpgaInit->datapath.rxDmaCfg[2].validDataWidthStream = (defrm2L * device->devStateInfo.dmaDataWidth / 32) - 1; + fpgaInit->datapath.rxDmaCfg[2].sgFirstDescriptor = 0; + fpgaInit->datapath.rxDmaCfg[2].sgLastDescriptor = 0; + fpgaInit->datapath.rxDmaCfg[2].runStop = 0; + + /* set framer 0 settings */ + if (frm0L > 0) + { + jesd204F = (fpgaCfg->framerlink0.jesd204Np * fpgaCfg->framerlink0.jesd204M * fpgaCfg->framerlink0.jesd204S) / (8 * frm0L); + } + + /* Common */ + fpgaInit->datapath.framerCfg[0].deviceId = fpgaCfg->framerlink0.deviceId; + fpgaInit->datapath.framerCfg[0].bankId = 1; + fpgaInit->datapath.framerCfg[0].subclassV = 1; + fpgaInit->datapath.framerCfg[0].sysRefDelay = 0; + fpgaInit->datapath.framerCfg[0].lanesInUse = (frm0L == 8) ? 0xFF : + (frm0L == 4) ? 0x0F : + (frm0L == 2) ? 0x03 : + (frm0L == 1) ? 0x01 : 0; + + /* JESD204B */ + fpgaInit->datapath.framerCfg[0].ilaSupportEn = 1; + fpgaInit->datapath.framerCfg[0].scramblingEn = fpgaCfg->framerlink0.scramble; + fpgaInit->datapath.framerCfg[0].ilaMultiFrames = 4; + fpgaInit->datapath.framerCfg[0].cfgF = (frm0L > 0) ? jesd204F : 0; + fpgaInit->datapath.framerCfg[0].cfgK = (uint8_t)fpgaCfg->framerlink0.jesd204K; + fpgaInit->datapath.framerCfg[0].ilaM = fpgaCfg->framerlink0.jesd204M; + fpgaInit->datapath.framerCfg[0].ilaN = fpgaCfg->framerlink0.jesd204Np; + fpgaInit->datapath.framerCfg[0].ilaCs = 0; + fpgaInit->datapath.framerCfg[0].ilaNp = fpgaCfg->framerlink0.jesd204Np; + fpgaInit->datapath.framerCfg[0].ilaS = fpgaCfg->framerlink0.jesd204S; + fpgaInit->datapath.framerCfg[0].ilaCf = 0; + fpgaInit->datapath.framerCfg[0].sysRefAlways = 0; + fpgaInit->datapath.framerCfg[0].sysRefRequiredOnResync = 0; + + /* JESD204C */ + fpgaInit->datapath.framerCfg[0].enableCmdInterface = 0; + fpgaInit->datapath.framerCfg[0].enableDataInterface = 1; + fpgaInit->datapath.framerCfg[0].cfgE = fpgaCfg->framerlink0.jesd204E; + fpgaInit->datapath.framerCfg[0].ctrlMetaMode = 0; + fpgaInit->datapath.framerCfg[0].ctrlIrq = 0x3FF; /* Enable all interrupts */ + + /* Prevent divide by 0 */ + if (fpgaCfg->framerlink0.jesd204Np == 0) + { + fpgaInit->datapath.framerCfg[0].ilaHd = 0; + } + else + { + fpgaInit->datapath.framerCfg[0].ilaHd = ((((uint16_t)(jesd204F) * 8) % fpgaCfg->framerlink0.jesd204Np) > 0) ? 1 : 0; + } + + /* set deframer 0 datamover */ + fpgaInit->datapath.txDmaCfg[0].enableEnhancedMode = 0; + fpgaInit->datapath.txDmaCfg[0].enableSg = 0; + fpgaInit->datapath.txDmaCfg[0].simpleStartAddr = ADI_FPGA9025_TX_START_ADDRESS; /* First link starts on tx RAM boundary*/ + fpgaInit->datapath.txDmaCfg[0].length = ADI_FPGA9025_TX_DMA_SIZE - 1; /* End the first link just before the next link's memory starts */ + fpgaInit->datapath.txDmaCfg[0].validDataWidthStream = (frm0L * device->devStateInfo.dmaDataWidth / 32) - 1;; + fpgaInit->datapath.txDmaCfg[0].sgFirstDescriptor = 0; + fpgaInit->datapath.txDmaCfg[0].sgLastDescriptor = 0; + fpgaInit->datapath.txDmaCfg[0].runStop = 0; + fpgaInit->datapath.txDmaCfg[0].continuous = 1; + + /* set framer 1 settings */ + if (frm1L > 0) + { + jesd204F = (fpgaCfg->framerlink1.jesd204Np * fpgaCfg->framerlink1.jesd204M * fpgaCfg->framerlink1.jesd204S) / (8 * frm1L); + } + + /* Common */ + fpgaInit->datapath.framerCfg[1].deviceId = fpgaCfg->framerlink1.deviceId; + fpgaInit->datapath.framerCfg[1].bankId = 1; + fpgaInit->datapath.framerCfg[1].subclassV = 1; + fpgaInit->datapath.framerCfg[1].sysRefDelay = 0; + fpgaInit->datapath.framerCfg[1].lanesInUse = (frm1L == 8) ? 0xFF : + (frm1L == 4) ? 0x0F : + (frm1L == 2) ? 0x03 : + (frm1L == 1) ? 0x01 : 0; + + /* JESD204B */ + fpgaInit->datapath.framerCfg[1].ilaSupportEn = 1; + fpgaInit->datapath.framerCfg[1].scramblingEn = fpgaCfg->framerlink1.scramble; + fpgaInit->datapath.framerCfg[1].ilaMultiFrames = 4; + fpgaInit->datapath.framerCfg[1].cfgF = (frm1L > 0) ? jesd204F : 0; + fpgaInit->datapath.framerCfg[1].cfgK = (uint8_t)fpgaCfg->framerlink1.jesd204K; + fpgaInit->datapath.framerCfg[1].ilaM = fpgaCfg->framerlink1.jesd204M; + fpgaInit->datapath.framerCfg[1].ilaN = fpgaCfg->framerlink1.jesd204Np; + fpgaInit->datapath.framerCfg[1].ilaCs = 0; + fpgaInit->datapath.framerCfg[1].ilaNp = fpgaCfg->framerlink1.jesd204Np; + fpgaInit->datapath.framerCfg[1].ilaS = fpgaCfg->framerlink1.jesd204S; + fpgaInit->datapath.framerCfg[1].ilaCf = 0; + fpgaInit->datapath.framerCfg[1].sysRefAlways = 0; + fpgaInit->datapath.framerCfg[1].sysRefRequiredOnResync = 0; + + /* JESD204C */ + fpgaInit->datapath.framerCfg[1].enableCmdInterface = 0; + fpgaInit->datapath.framerCfg[1].enableDataInterface = 1; + fpgaInit->datapath.framerCfg[1].cfgE = fpgaCfg->framerlink1.jesd204E; + fpgaInit->datapath.framerCfg[1].ctrlMetaMode = 0; + fpgaInit->datapath.framerCfg[1].ctrlIrq = 0x3FF; /* Enable all interrupts */ + + /* Prevent divide by 0 */ + if (fpgaCfg->framerlink1.jesd204Np == 0) + { + fpgaInit->datapath.framerCfg[1].ilaHd = 0; + } + else + { + fpgaInit->datapath.framerCfg[1].ilaHd = ((((uint16_t)(jesd204F) * 8) % fpgaCfg->framerlink1.jesd204Np) > 0) ? 1 : 0; + } + + /* set deframer 0 datamover */ + fpgaInit->datapath.txDmaCfg[1].enableEnhancedMode = 0; + fpgaInit->datapath.txDmaCfg[1].enableSg = 0; + fpgaInit->datapath.txDmaCfg[1].simpleStartAddr = ADI_FPGA9025_TX_START_ADDRESS + (1 * ADI_FPGA9025_TX_DMA_SIZE); + /* First link starts on tx RAM boundary*/ + fpgaInit->datapath.txDmaCfg[1].length = ADI_FPGA9025_TX_DMA_SIZE - 1; + /* End the first link just before the next link's memory starts */ + fpgaInit->datapath.txDmaCfg[1].validDataWidthStream = (frm1L * device->devStateInfo.dmaDataWidth / 32) - 1; + + fpgaInit->datapath.txDmaCfg[1].sgFirstDescriptor = 0; + fpgaInit->datapath.txDmaCfg[1].sgLastDescriptor = 0; + fpgaInit->datapath.txDmaCfg[1].runStop = 0; + fpgaInit->datapath.txDmaCfg[1].continuous = 1; + + /* tollgates */ + fpgaInit->datapath.rxTollgateCfg.tollGateEdgeOrLvl = 1; + fpgaInit->datapath.rxTollgateCfg.tollGateHiRiseOrLoFall = 1; + fpgaInit->datapath.rxTollgateCfg.tollgateReset = 1; + fpgaInit->datapath.rxTollgateCfg.tollGateTrigSource = ADI_FPGA9025_IMM_TRIG; + + fpgaInit->datapath.txTollgateCfg.tollGateEdgeOrLvl = 1; + fpgaInit->datapath.txTollgateCfg.tollGateHiRiseOrLoFall = 1; + fpgaInit->datapath.txTollgateCfg.tollgateReset = 1; + fpgaInit->datapath.txTollgateCfg.tollGateTrigSource = ADI_FPGA9025_TX_IMM_TRIG; + + /* Setup SYNCB crossbars in FPGA */ + for (i = 0; i < (ADI_FPGA9025_NUM_OF_DEFRAMERS + ADI_FPGA9025_NUM_OF_FRAMERS); i++) + { + fpgaInit->datapath.syncBSel[i] = i; + } + + return recoveryAction; +} + +int32_t adi_fpga9025_FpgaConfigurationPrint(adi_fpga9025_Device_t* device) +{ + /* Read FPGA regs to verify state */ + uint32_t fpgaReg = 0; + uint32_t fpgaAddr; + uint32_t recoveryAction = 0; + int i, j, l; + + /*Physical layer*/ + fpgaAddr = 0x43400114; /* channel 0 rx control */ + for (i = 0; i < ADI_FPGA9025_NUM_LANES; i++) + { + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s\n", + "********************************************"); + printf("%s\n", + "INFO: FPGA Rx deserializer config per lane"); + printf("%s\n", + "********************************************"); + printf("%s%d%s0x%x\n", + "Rx channel_", + i, + "_rx_dfe_lpm_en: ", + ((fpgaReg >> 8) & 0x01)); + printf("%s%d%s0x%x\n", + "Rx channel_", + i, + "_rx_rate: ", + ((fpgaReg >> 4) & 0x07)); + printf("%s%d%s0x%x\n", + "Rx channel_", + i, + "_rx_8b10b_enable: ", + ((fpgaReg >> 3) & 0x01)); + printf("%s%d%s0x%x\n", + "Rx channel_", + i, + "_rx_polarity: ", + ((fpgaReg >> 2) & 0x01)); + printf("%s%d%s0x%x\n", + "Rx channel_", + i, + "_rx_powerdown: ", + ((fpgaReg >> 0) & 0x03)); + printf("\n"); + fpgaAddr += 0x100; + } + + fpgaAddr = 0x43400118; /* channel 0 tx control */ + for (i = 0; i < ADI_FPGA9025_NUM_LANES; i++) + { + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s\n", + "********************************************"); + printf("%s\n", + "INFO: FPGA Tx serializer config per lane"); + printf("%s\n", + "********************************************"); + printf("%s%d%s0x%x\n", + "Tx channel_", + i, + "_tx_diff_control: ", + ((fpgaReg >> 24) & 0x0F)); + printf("%s%d%s0x%x\n", + "Tx channel_", + i, + "_tx_precursor: ", + ((fpgaReg >> 16) & 0x1F)); + printf("%s%d%s0x%x\n", + "Tx channel_", + i, + "_tx_postcursor: ", + ((fpgaReg >> 8) & 0x1F)); + printf("%s%d%s0x%x\n", + "Tx channel_", + i, + "_tx_rate: ", + ((fpgaReg >> 4) & 0x07)); + printf("%s%d%s0x%x\n", + "Tx channel_", + i, + "_tx_8b10b_enable: ", + ((fpgaReg >> 3) & 0x01)); + printf("%s%d%s0x%x\n", + "Tx channel_", + i, + "_tx_polarity: ", + ((fpgaReg >> 2) & 0x01)); + printf("%s%d%s0x%x\n", + "Tx channel_", + i, + "_tx_powerdown: ", + ((fpgaReg >> 0) & 0x03)); + printf("\n"); + fpgaAddr += 0x100; + } + + /* Read FPGA CLK frequency detectors */ + printf("%s\n", + "********************************************"); + printf("%s\n", + "INFO: FPGA Clocks frequency detectors"); + printf("%s\n", + "********************************************"); + fpgaAddr = 0x43404010; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", + "rx_core_clock_0", + i, + ": ", + fpgaReg); + fpgaAddr += 4; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", + "rx_core_clock_1", + i, + ": ", + fpgaReg); + fpgaAddr += 4; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", + "rx_core_clock_2", + i, + ": ", + fpgaReg); + fpgaAddr += 4; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", + "tx_core_clock_0", + i, + ": ", + fpgaReg); + fpgaAddr += 4; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", + "tx_core_clock_1", + i, + ": ", + fpgaReg); + fpgaAddr += 4; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", + "tdd_clock", + i, + ": ", + fpgaReg); + fpgaAddr += 4; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", + "mmcm_ref_clock", + i, + ": ", + fpgaReg); + fpgaAddr += 4; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", + "tx_lane_0_clock", + i, + ": ", + fpgaReg); + fpgaAddr += 4; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u Hz\n", + "tx_lane_1_clock", + i, + ": ", + fpgaReg); + + /* Read FPGA deframer 0 lane crossbars */ + printf("%s\n", + "********************************************"); + printf("%s\n", + "INFO: FPGA Deframer 0 lane crossbars"); + printf("%s\n", + "********************************************"); + fpgaAddr = 0x43405004; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", + "rx_lane_xbar_link_0::reset: ", + fpgaReg); + + fpgaAddr = 0x43405010; + for (i = 0; i < ADI_FPGA9025_NUM_LANES; i++) + { + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", + "rx_lane_xbar_link_0::lane_", + i, + "_select: ", + (fpgaReg & 0x1F)); + fpgaAddr += 4; + } + + /* Read FPGA deframer 1 lane crossbars */ + printf("%s\n", + "********************************************"); + printf("%s\n", + "INFO: FPGA Deframer 1 lane crossbars"); + printf("%s\n", + "********************************************"); + fpgaAddr = 0x43406004; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", + "rx_lane_xbar_link_1::reset: ", + fpgaReg); + + fpgaAddr = 0x43406010; + for (i = 0; i < ADI_FPGA9025_NUM_LANES; i++) + { + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", + "rx_lane_xbar_link_1::lane_", + i, + "_select: ", + (fpgaReg & 0x1F)); + fpgaAddr += 4; + } + + /* Read FPGA framer 0 lane crossbars */ + printf("%s\n", + "********************************************"); + printf("%s\n", + "INFO: FPGA Framer 0 lane crossbars"); + printf("%s\n", + "********************************************"); + fpgaAddr = 0x43407004; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", + "tx_lane_xbar_link_0::reset: ", + fpgaReg); + + fpgaAddr = 0x43407010; + for (i = 0; i < ADI_FPGA9025_NUM_LANES; i++) + { + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", + "tx_lane_xbar_link_0::lane_", + i, + "_select: ", + (fpgaReg & 0x1F)); + fpgaAddr += 4; + } + + printf("%s\n", + "********************************************"); + printf("%s\n", + "INFO: FPGA Framer Config"); + printf("%s\n", + "********************************************"); + fpgaAddr = 0x4340A000; + for (i = 0; i < 1; i++) + { + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 4, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::reset_self_clearing: ", + fpgaReg & 0x1); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::reset_fixd: ", + (fpgaReg >> 1) & 0x1); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::watchdog_timer_disable: ", + (fpgaReg >> 16) & 0x1); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 8, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::ila_support_end: ", + fpgaReg & 0x1); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0xC, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::scrambling_en: ", + fpgaReg & 0x1); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x10, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::sysref_always: ", + fpgaReg & 0x1); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::sysref_delay: ", + (fpgaReg >> 8) & 0xF); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::sysref_required_on_resync: ", + (fpgaReg >> 16) & 0x1); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x14, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::ila_multiframes: ", + fpgaReg & 0xFF); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x18, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::test_mode: ", + fpgaReg & 0x7); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x1C, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + for (j = 0; j < 8; j++) + { + printf("%s%d%s%d%s%d\n", + "jesd204b_framer_", + i, + "::link_error_status_lane_", + j, + ": ", + ((fpgaReg >> i * 3) & 0x3)); + } + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::rx_buffer_ovfg_alarm: ", + (fpgaReg >> 29) & 0x1); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::sysref_lmfc_alarm: ", + (fpgaReg >> 30) & 0x1); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::lane_align_alarm: ", + (fpgaReg >> 31) & 0x1); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x20, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::cfg_f: ", + fpgaReg & 0xFF); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x24, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::cfg_k: ", + fpgaReg & 0x1F); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x28, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::lane_in_use: ", + fpgaReg & 0xFF); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x2C, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::cfg_subclassv: ", + fpgaReg & 0x3); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x30, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::rx_buffer_delay: ", + fpgaReg & 0x3FF); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x34, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::link_err_cntrs_en: ", + fpgaReg & 0x1); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::dis_err_on_sync: ", + (fpgaReg >> 8) & 0x1); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x38, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::sync_status: ", + fpgaReg & 0x1); + printf("%s%d%s%d\n", + "jesd204b_framer_", + i, + "::sysref_captured: ", + (fpgaReg >> 16) & 0x1); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x3C, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + for (j = 0; j < 8; j++) + { + printf("%s%d%s%d%s%d\n", + "jesd204b_framer_", + i, + "::link_debug_status_lane_", + j, + ": ", + ((fpgaReg >> i * 4) & 0xF)); + } + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x810, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("\t%s%d%s%d\n", + "jesd204b_framer_", + i, + "::ila_m: ", + fpgaReg & 0xFF); + printf("\t%s%d%s%d\n", + "jesd204b_framer_", + i, + "::ila_n: ", + (fpgaReg >> 8) & 0x1F); + printf("\t%s%d%s%d\n", + "jesd204b_framer_", + i, + "::ila_np: ", + (fpgaReg >> 16) & 0x1F); + printf("\t%s%d%s%d\n", + "jesd204b_framer_", + i, + "::ila_cs: ", + (fpgaReg >> 24) & 0x3); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x814, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("\t%s%d%s%d\n", + "jesd204b_framer_", + i, + "::ila_scr: ", + fpgaReg & 0x1); + printf("\t%s%d%s%d\n", + "jesd204b_framer_", + i, + "::ila_s: ", + (fpgaReg >> 8) & 0x1F); + printf("\t%s%d%s%d\n", + "jesd204b_framer_", + i, + "::ila_hd: ", + (fpgaReg >> 16) & 0x1); + printf("\t%s%d%s%d\n", + "jesd204b_framer_", + i, + "::ila_cf: ", + (fpgaReg >> 24) & 0x1F); + } + + printf("%s\n", + "********************************************"); + printf("%s\n", + "INFO: FPGA Rx DMAs & Tollgates"); + printf("%s\n", + "********************************************"); + fpgaAddr = 0x43101008; + for (i = 0; i < 2; i++) + { + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::run_stop: ", + (fpgaReg & 0x1)); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::enable_sg: ", + ((fpgaReg >> 2) & 0x1)); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::enable_enhanced_mode: ", + ((fpgaReg >> 3) & 0x1)); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::valid_data_width_stream: ", + ((fpgaReg >> 8) & 0xF)); + + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 4), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::active: ", + (fpgaReg & 0x1)); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::complete: ", + ((fpgaReg >> 1) & 0x1)); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::halt_complete: ", + ((fpgaReg >> 2) & 0x1)); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::overflow: ", + ((fpgaReg >> 3) & 0x1)); + + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 8), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s0x%x\n", + "dp_dma_rx_", + i, + "::simple_start_addr: ", + fpgaReg); + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 16), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::length: ", + fpgaReg); + + fpgaAddr += 0x1000; + } + fpgaAddr = 0x43103004; + for (i = 0; i < 2; i++) + { + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", + "dp_tollgate_rx_", + i, + "::reset: ", + (fpgaReg & 0x1)); + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 4), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s0x%x\n", + "dp_tollgate_rx_", + i, + "::trigger_select: ", + fpgaReg); + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 8), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s0x%x\n", + "dp_tollgate_rx_", + i, + "::edge_level: ", + fpgaReg); + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 12), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s0x%x\n", + "dp_tollgate_rx_", + i, + "::high_rising_low_falling: ", + fpgaReg); + + fpgaAddr += 0x1000; + } + + /* Read FPGA deframer 0 config */ + printf("%s\n", + "********************************************"); + printf("%s\n", + "INFO: FPGA Deframer Config"); + printf("%s\n", + "********************************************"); + fpgaAddr = 0x43408000; + for (i = 0; i < 2; i++) + { + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 4, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::reset_self_clearing: ", + fpgaReg & 0x1); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::reset_fixd: ", + (fpgaReg >> 1) & 0x1); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::watchdog_timer_disable: ", + (fpgaReg >> 16) & 0x1); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 8, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::ila_support_end: ", + fpgaReg & 0x1); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0xC, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::scrambling_en: ", + fpgaReg & 0x1); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x10, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::sysref_always: ", + fpgaReg & 0x1); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::sysref_delay: ", + (fpgaReg >> 8) & 0xF); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::sysref_required_on_resync: ", + (fpgaReg >> 16) & 0x1); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x14, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::ila_multiframes: ", + fpgaReg & 0xFF); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x18, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::test_mode: ", + fpgaReg & 0x7); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x1C, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + for (j = 0; j < 8; j++) + { + printf("%s%d%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::link_error_status_lane_", + j, + ": ", + ((fpgaReg >> i * 3) & 0x3)); + } + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::rx_buffer_ovfg_alarm: ", + (fpgaReg >> 29) & 0x1); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::sysref_lmfc_alarm: ", + (fpgaReg >> 30) & 0x1); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::lane_align_alarm: ", + (fpgaReg >> 31) & 0x1); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x20, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::cfg_f: ", + fpgaReg & 0xFF); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x24, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::cfg_k: ", + fpgaReg & 0x1F); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x28, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::lane_in_use: ", + fpgaReg & 0xFF); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x2C, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::cfg_subclassv: ", + fpgaReg & 0x3); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x30, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::rx_buffer_delay: ", + fpgaReg & 0x3FF); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x34, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::link_err_cntrs_en: ", + fpgaReg & 0x1); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::dis_err_on_sync: ", + (fpgaReg >> 8) & 0x1); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x38, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::sync_status: ", + fpgaReg & 0x1); + printf("%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::sysref_captured: ", + (fpgaReg >> 16) & 0x1); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x3C, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + for (j = 0; j < 8; j++) + { + printf("%s%d%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::link_debug_status_lane_", + j, + ": ", + ((fpgaReg >> i * 4) & 0xF)); + } + + /* start lane specific data captured through ila */ + for (l = 0; l < 8; l++) + { + printf("\t%s\n", + "********************************************"); + printf("\t%s%d\n", + "INFO: ILA info for lane ", + l); + printf("\t%s\n", + "********************************************"); + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x800 + (0x40 * l), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("\t%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::ila_subclass: ", + fpgaReg & 0x7); + printf("\t%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::ila_jesdv: ", + (fpgaReg >> 8) & 0x7); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x804 + (0x40 * l), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("\t%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::ila_f: ", + fpgaReg & 0xFF); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x808 + (0x40 * l), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("\t%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::ila_k: ", + fpgaReg & 0x1F); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x810 + (0x40 * l), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("\t%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::ila_m: ", + fpgaReg & 0xFF); + printf("\t%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::ila_n: ", + (fpgaReg >> 8) & 0x1F); + printf("\t%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::ila_np: ", + (fpgaReg >> 16) & 0x1F); + printf("\t%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::ila_cs: ", + (fpgaReg >> 24) & 0x3); + + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr + 0x814 + (0x40 * l), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("\t%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::ila_scr: ", + fpgaReg & 0x1); + printf("\t%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::ila_s: ", + (fpgaReg >> 8) & 0x1F); + printf("\t%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::ila_hd: ", + (fpgaReg >> 16) & 0x1); + printf("\t%s%d%s%d\n", + "jesd204b_deframer_", + i, + "::ila_cf: ", + (fpgaReg >> 24) & 0x1F); + } + fpgaAddr += 0x1000; + } + + printf("%s\n", + "********************************************"); + printf("%s\n", + "INFO: FPGA Tx DMAs & Tollgates"); + printf("%s\n", + "********************************************"); + fpgaAddr = 0x43201008; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", + "dp_dma_tx_0::run_stop: ", + (fpgaReg & 0x1)); + printf("%s%u\n", + "dp_dma_tx_0::continuous: ", + ((fpgaReg >> 1) & 0x1)); + printf("%s%u\n", + "dp_dma_tx_0::enable_sg: ", + ((fpgaReg >> 2) & 0x1)); + printf("%s%u\n", + "dp_dma_tx_0::enable_enhanced_mode: ", + ((fpgaReg >> 3) & 0x1)); + printf("%s%u\n", + "dp_dma_tx_0::valid_data_width_stream: ", + ((fpgaReg >> 8) & 0xF)); + + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 4), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", + "dp_dma_tx_0::active: ", + (fpgaReg & 0x1)); + printf("%s%u\n", + "dp_dma_tx_0::complete: ", + ((fpgaReg >> 1) & 0x1)); + printf("%s%u\n", + "dp_dma_tx_0::halt_complete: ", + ((fpgaReg >> 2) & 0x1)); + printf("%s%u\n", + "dp_dma_tx_0::underflow: ", + (fpgaReg & 0x8)); + + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 8), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", + "dp_dma_tx_0::simple_start_addr: ", + fpgaReg); + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 16), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", + "dp_dma_tx_0::length: ", + fpgaReg); + + fpgaAddr = 0x43202004; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", + "dp_tollgate_tx_0::reset: ", + (fpgaReg & 0x1)); + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 4), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", + "dp_tollgate_tx_0::trigger_select: ", + fpgaReg); + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 8), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", + "dp_tollgate_tx_0::edge_level: ", + fpgaReg); + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 12), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", + "dp_tollgate_tx_0::high_rising_low_falling: ", + fpgaReg); + + printf("%s\n", + "********************************************"); + printf("%s\n", + "INFO: FPGA Tx Capture Control"); + printf("%s\n", + "********************************************"); + fpgaAddr = 0x43200008; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", + "dp_capture_control_tx::datapath_active: ", + (fpgaReg & 0x1)); + printf("%s%u\n", + "dp_capture_control_tx::pass_token: ", + ((fpgaReg >> 1) & 0x1)); + + printf("%s\n", + "********************************************"); + printf("%s\n", + "INFO: FPGA Rx Capture Control"); + printf("%s\n", + "********************************************"); + fpgaAddr = 0x43100008; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", + "dp_capture_control_rx::datapath_active: ", + (fpgaReg & 0x1)); + printf("%s%u\n", + "dp_capture_control_rx::pass_token: ", + ((fpgaReg >> 1) & 0x1)); + + return recoveryAction; +} + +int32_t adi_fpga9025_FpgaDatapathCfgPrint(adi_fpga9025_Device_t* device) +{ + /* Read FPGA regs to verify state */ + uint32_t fpgaReg = 0; + uint32_t fpgaAddr; + uint32_t recoveryAction = 0; + int i; + + printf("%s\n", + "********************************************"); + printf("%s\n", + "INFO: FPGA Rx DMAs & Tollgates"); + printf("%s\n", + "********************************************"); + fpgaAddr = 0x43101008; + for (i = 0; i < 2; i++) + { + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::run_stop: ", + (fpgaReg & 0x1)); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::enable_sg: ", + ((fpgaReg >> 2) & 0x1)); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::enable_enhanced_mode: ", + ((fpgaReg >> 3) & 0x1)); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::valid_data_width_stream: ", + ((fpgaReg >> 8) & 0xF)); + + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 4), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::active: ", + (fpgaReg & 0x1)); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::complete: ", + ((fpgaReg >> 1) & 0x1)); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::halt_complete: ", + ((fpgaReg >> 2) & 0x1)); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::overflow: ", + ((fpgaReg >> 3) & 0x1)); + + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 8), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s0x%x\n", + "dp_dma_rx_", + i, + "::simple_start_addr: ", + fpgaReg); + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 16), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", + "dp_dma_rx_", + i, + "::length: ", + fpgaReg); + + fpgaAddr += 0x1000; + } + fpgaAddr = 0x43103004; + for (i = 0; i < 2; i++) + { + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s%u\n", + "dp_tollgate_rx_", + i, + "::reset: ", + (fpgaReg & 0x1)); + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 4), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s0x%x\n", + "dp_tollgate_rx_", + i, + "::trigger_select: ", + fpgaReg); + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 8), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s0x%x\n", + "dp_tollgate_rx_", + i, + "::edge_level: ", + fpgaReg); + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 12), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%d%s0x%x\n", + "dp_tollgate_rx_", + i, + "::high_rising_low_falling: ", + fpgaReg); + + fpgaAddr += 0x1000; + } + + printf("%s\n", + "********************************************"); + printf("%s\n", + "INFO: FPGA Tx DMAs & Tollgates"); + printf("%s\n", + "********************************************"); + fpgaAddr = 0x43201008; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", + "dp_dma_tx_0::run_stop: ", + (fpgaReg & 0x1)); + printf("%s%u\n", + "dp_dma_tx_0::continuous: ", + ((fpgaReg >> 1) & 0x1)); + printf("%s%u\n", + "dp_dma_tx_0::enable_sg: ", + ((fpgaReg >> 2) & 0x1)); + printf("%s%u\n", + "dp_dma_tx_0::enable_enhanced_mode: ", + ((fpgaReg >> 3) & 0x1)); + printf("%s%u\n", + "dp_dma_tx_0::valid_data_width_stream: ", + ((fpgaReg >> 8) & 0xF)); + + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 4), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", + "dp_dma_tx_0::active: ", + (fpgaReg & 0x1)); + printf("%s%u\n", + "dp_dma_tx_0::complete: ", + ((fpgaReg >> 1) & 0x1)); + printf("%s%u\n", + "dp_dma_tx_0::halt_complete: ", + ((fpgaReg >> 2) & 0x1)); + printf("%s%u\n", + "dp_dma_tx_0::underflow: ", + ((fpgaReg >> 3) & 0x1)); + + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 8), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", + "dp_dma_tx_0::simple_start_addr: ", + fpgaReg); + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 16), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", + "dp_dma_tx_0::length: ", + fpgaReg); + + fpgaAddr = 0x43202004; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", + "dp_tollgate_tx_0::reset: ", + (fpgaReg & 0x1)); + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 4), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", + "dp_tollgate_tx_0::trigger_select: ", + fpgaReg); + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 8), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", + "dp_tollgate_tx_0::edge_level: ", + fpgaReg); + recoveryAction = adi_fpga9025_RegisterRead(device, + (fpgaAddr + 12), + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s0x%x\n", + "dp_tollgate_tx_0::high_rising_low_falling: ", + fpgaReg); + + printf("%s\n", + "********************************************"); + printf("%s\n", + "INFO: FPGA Tx Capture Control"); + printf("%s\n", + "********************************************"); + fpgaAddr = 0x43200008; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", + "dp_capture_control_tx::datapath_active: ", + (fpgaReg & 0x1)); + printf("%s%u\n", + "dp_capture_control_tx::pass_token: ", + ((fpgaReg >> 1) & 0x1)); + + printf("%s\n", + "********************************************"); + printf("%s\n", + "INFO: FPGA Rx Capture Control"); + printf("%s\n", + "********************************************"); + fpgaAddr = 0x43100008; + recoveryAction = adi_fpga9025_RegisterRead(device, + fpgaAddr, + &fpgaReg); + ADI_ERROR_REPORT(&device->common, + device->common.error.errSource, + device->common.error.errCode, + recoveryAction, + device->common.error.varName, + device->common.error.errormessage); + ADI_ERROR_RETURN(device->common.error.newAction); + printf("%s%u\n", + "dp_capture_control_rx::datapath_active: ", + (fpgaReg & 0x1)); + printf("%s%u\n", + "dp_capture_control_rx::pass_token: ", + ((fpgaReg >> 1) & 0x1)); + + return recoveryAction; +} diff --git a/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/resources/adi_fpga_mem_map.h b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/resources/adi_fpga_mem_map.h new file mode 100644 index 0000000..8e78a7d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/fpga9025/resources/adi_fpga_mem_map.h @@ -0,0 +1,746 @@ +#ifndef _ADI_FPGA9025_MEM_MAP_H_ +#define _ADI_FPGA9025_MEM_MAP_H_ + +#include +uint32_t fpga9025_mem_map[] = { + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x13,0x03,0x03,0x13,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0xE4,0xE4,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA5,0xA5,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0xE4,0xE4,0x00,0x00,0x00,0x1F,0x00,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x9F,0xE0,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0xF5,0x8F,0x0F,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + +#endif /* _ADI_FPGA9025_MEM_MAP_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/devices/share_utils/adi_device_share.c b/driver/rfic/rf/adrv9025/c_src/devices/share_utils/adi_device_share.c new file mode 100644 index 0000000..44cf437 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/share_utils/adi_device_share.c @@ -0,0 +1,142 @@ +/** + * \file adi_device_share.c + * + * ADRV9025 API Version: 6.4.0.14 + */ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ +#include "adi_device_share.h" +#include "adi_adrv9025_types.h" +#include "adi_ad9528_types.h" +#include "adi_adrv9025_hal.h" +#include "adi_ad9528_hal.h" +#include "adi_ad9528_utilities.h" + + + +static int32_t reset_setup_hold_block(adi_adrv9025_Device_t* device) +{ + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + retVal = adi_adrv9025_SpiByteWrite(device,0x004a, 0x92); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, ADI_COMMON_ERR_API_FAIL, retVal, NULL,"SPI write failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adi_adrv9025_SpiByteWrite(device,0x004a, 0x12); /*toggle resetb_tflash to start a new setup/hold measurement*/ + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, ADI_COMMON_ERR_API_FAIL, retVal, NULL,"SPI write failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adi_adrv9025_SpiByteWrite(device,0x004a, 0x92); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, ADI_COMMON_ERR_API_FAIL, retVal, NULL,"SPI write failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + return 0; +} +static int32_t read_setup_hold_data(adi_adrv9025_Device_t *device, + uint16_t *setupWord, + uint16_t *holdWord) +{ + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + uint8_t setup_l = 0; + uint8_t setup_h = 0; + uint8_t hold_l = 0; + uint8_t hold_h = 0; + + retVal = adi_adrv9025_SpiByteRead(device,0x004c, &setup_l); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, ADI_COMMON_ERR_API_FAIL, retVal, NULL,"SPI read failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + retVal = adi_adrv9025_SpiByteRead(device,0x004d, &setup_h); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, ADI_COMMON_ERR_API_FAIL, retVal, NULL,"SPI read failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + retVal = adi_adrv9025_SpiByteRead(device,0x004e, &hold_l); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, ADI_COMMON_ERR_API_FAIL, retVal, NULL,"SPI read failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + retVal = adi_adrv9025_SpiByteRead(device,0x004f, &hold_h); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, ADI_COMMON_ERR_API_FAIL, retVal, NULL,"SPI read failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + + *setupWord = (uint16_t)(((uint16_t)setup_h << 8) | (uint16_t)setup_l); + *holdWord = (uint16_t)(((uint16_t)hold_h << 8) | (uint16_t)hold_l); + + return retVal; +} + +int32_t adi_device_share_setupHoldMonitorTimingBlock(adi_adrv9025_Device_t *device, + adi_ad9528_Device_t *clock, + uint8_t fine, + uint16_t *setupWordArr, + uint16_t *holdWordArr) +{ + + int32_t retVal = ADI_COMMON_ACT_NO_ACTION; + static const uint8_t FINE_MAX = 16; + static const uint8_t COARSE_MAX = 32; + uint8_t fineCount = 0; + uint8_t coarseCount = 0; + uint16_t counter = 0; + uint16_t setupWord = 0; + uint16_t holdWord = 0; + + ADI_NULL_DEVICE_PTR_RETURN(device); + ADI_NULL_DEVICE_PTR_RETURN(clock); + + ADI_NULL_DEVICE_PTR_RETURN(setupWordArr); + ADI_NULL_DEVICE_PTR_RETURN(holdWordArr); + + ADI_FUNCTION_ENTRY_LOG(&device->common, ADI_COMMON_LOG_API); + + /* Enable Timing Flash */ + retVal = adi_adrv9025_SpiByteWrite(device,0x0048, 0x58); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, ADI_COMMON_ERR_API_FAIL, retVal, NULL,"SPI write failure"); + ADI_ERROR_RETURN(device->common.error.newAction); + /* Reset/setup timing hold block */ + retVal = reset_setup_hold_block(device); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, ADI_COMMON_ERR_API_FAIL, retVal, NULL,"Error Resetting/setting up timing hold block"); + ADI_ERROR_RETURN(device->common.error.newAction); + + retVal = adi_ad9528_SysrefRequest(clock, 0x01); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, ADI_COMMON_ERR_API_FAIL, retVal, NULL,"Error while requesting sysref"); + ADI_ERROR_RETURN(device->common.error.newAction); + for (coarseCount = 0; coarseCount < COARSE_MAX; coarseCount++) + { + adi_ad9528_SpiByteWrite(clock, 0x304, coarseCount); + adi_ad9528_SpiByteWrite(clock, 0x00f, 0x01); + retVal = adi_ad9528_SysrefRequest(clock, 0x01); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, ADI_COMMON_ERR_API_FAIL, retVal, NULL,"Error while requesting sysref"); + ADI_ERROR_RETURN(device->common.error.newAction); + if (fine == 1) + { + for (fineCount = 0; fineCount < FINE_MAX-1; fineCount++) + { + adi_ad9528_SpiByteWrite(clock, 0x303, fineCount + 16); + adi_ad9528_SpiByteWrite(clock, 0x00f, 0x01); + retVal = reset_setup_hold_block(device); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, ADI_COMMON_ERR_API_FAIL, retVal, NULL,"Error Resetting/setting up timing hold block"); + ADI_ERROR_RETURN(device->common.error.newAction); + retVal = adi_ad9528_SysrefRequest(clock, 0x01); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, ADI_COMMON_ERR_API_FAIL, retVal, NULL,"Error while requesting sysref"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_common_hal_Wait_ms(&device->common, 100); + /* read data */ + read_setup_hold_data(device, &setupWord, &holdWord); + setupWordArr[counter] = setupWord; + holdWordArr[counter++] = holdWord; + } + } + retVal = reset_setup_hold_block(device); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, ADI_COMMON_ERR_API_FAIL, retVal, NULL,"Error Resetting/setting up timing hold block"); + ADI_ERROR_RETURN(device->common.error.newAction); + retVal = adi_ad9528_SysrefRequest(clock, 0x01); + ADI_ERROR_REPORT(&device->common, ADI_COMMON_ERRSRC_DEVICEBF, ADI_COMMON_ERR_API_FAIL, retVal, NULL,"Error while requesting sysref"); + ADI_ERROR_RETURN(device->common.error.newAction); + adi_common_hal_Wait_ms(&device->common, 100); + /* read data */ + read_setup_hold_data(device, &setupWord, &holdWord); + setupWordArr[counter] = setupWord; + holdWordArr[counter++] = holdWord; + } + return retVal; +} + diff --git a/driver/rfic/rf/adrv9025/c_src/devices/share_utils/adi_device_share.h b/driver/rfic/rf/adrv9025/c_src/devices/share_utils/adi_device_share.h new file mode 100644 index 0000000..b7c54d5 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/share_utils/adi_device_share.h @@ -0,0 +1,78 @@ +#ifndef _ADI_DEVICE_SHARE_H_ +#define _ADI_DEVICE_SHARE_H_ + +#include +#include "adi_common.h" +#include "adi_ad9528_types.h" +#include "adi_adrv9025_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** +* Runtime functions +**************************************************************************** +*/ + + +/** + * \brief This function uses a combination of adrv9025 device and ad9528 clock chip + * to test and see if sysref's are meeting timing requirements in a given clock chip state + * + * + * This function iterates over 32 coarse adjustments for the ad9528 clock chip and reads back the setup and hold time + * for this given setting. + * Optionally you can enable fine measurement which sets the ad9528 fine adjustment + * For coarse the expected output would be two arrays of size 32 i.e. 32 setup and 32 corresponding hold values + * for fine option, you would expect 512 results, a setup and hold value (corresponding to a coarse adjustment) and the results for + * 16 fine clock adjustments. + * + * Results can be interpreted as follows: + * ----------------------------------------------------------------------------------- + * | Sysref Timing | Setup Value | Hold Value | Meeting Timing | + * |----------------------- |----------------------|------------ |----------------| + * | Sysref Leading DEVCLK | 0x0000 | 0x0000 | Yes | + * | | 0x8000 - 0xFE00 | 0x0000 | Marginally | + * | | 0xFF00 - 0xFFFF | 0x0000 | No | + * |----------------------- |----------------------|-----------------|----------------| + * | Sysref Lagging DEVCLK | 0xFFFF | 0x0000 - 0x00FF | No | + * | | 0xFFFF | 0x00FF- 0xFFFF | Marginally | + * | | 0xFFFF | 0xFFFF | Yes | + * |------------------------|----------------------|-----------------|----------------| + * | Sysref Aligned with | 0x7FFF - 0x0001 | 0xFFFF | Yes | + * | Falling Edge of DevCLK | | | | + * | | 0x0000 | 0xFFFF - 0x8000 | Yes | + * |------------------------|----------------------|-----------------|----------------| + * + * + * \pre This function can be called at any time. + * + * \dep_begin + * \dep{device->common.devHalInfo} + * \dep_end + * + * \param device Pointer to the ADRV9025 device data structure containing settings + * \param clock pointer to ad9528 device clock + * \param fine paramter to enable fine measurement either (1 to enable fine and 0 to disable) + * \param setupWordArr array to hold setup word results (when fine =0 array size required is 32 and when fine is enabled array size 512 is required) + * \param holdWordArr array to capture hold word results (when fine =0 array size required is 32 and when fine is enabled array size 512 is required) + * + * \retval ADI_COMMON_ACT_WARN_RESET_LOG Recovery action for log reset + * \retval ADI_COMMON_ACT_ERR_CHECK_PARAM Recovery action for bad parameter check + * \retval ADI_COMMON_ACT_ERR_RESET_INTERFACE Recovery action for SPI reset required + * \retval ADI_COMMON_ACT_NO_ACTION Function completed successfully, no action required + */ + + +int32_t adi_device_share_setupHoldMonitorTimingBlock(adi_adrv9025_Device_t *device, + adi_ad9528_Device_t *clock, + uint8_t fine, + uint16_t *setupWordArr, + uint16_t *holdWordArr); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/devices/share_utils/adi_fpga_tdd_types.h b/driver/rfic/rf/adrv9025/c_src/devices/share_utils/adi_fpga_tdd_types.h new file mode 100644 index 0000000..4439640 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/devices/share_utils/adi_fpga_tdd_types.h @@ -0,0 +1,99 @@ +/*! +* \file adi_fpga_tdd_types.h +* \brief Contains FPGA TDD enum and struct definitions +* +* ADRV9025 API Version: $ADI_ADRV_API_VERSION$ +*/ + +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the API license, for more information + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef _ADI_FPGA_TDD_TYPES_H_ +#define _ADI_FPGA_TDD_TYPES_H_ + +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Structure to hold the FPGA TDD Timing parameters. Located in the TDD Enable +* Control FPGA module. Includes primary & secondary region parameters. +*/ +typedef struct adi_fpga_TddTiming +{ + uint32_t onPtr; /*!< On pointer (start value) for TDD primary region */ + uint32_t offPtr; /*!< Off pointer (start value) for TDD primary region */ + uint32_t secondaryOnPtr; /*!< On pointer (start value) for TDD secondary region */ + uint32_t secondaryOffPtr; /*!< Off pointer (start value) for TDD secondary region */ + uint32_t offsetFrames; /*!< Offset frame value for primary & secondary region */ + uint32_t activeFrames; /*!< Active frame value for primary & secondary region */ + uint32_t inactiveFrames; /*!< Inactive frame value for primary & secondary region */ +} adi_fpga_TddTiming_t; + +/** +* \brief Structure to hold the FPGA TDD Datapath parameters. Located in the TDD Datapath +* Control FPGA module. +*/ +typedef struct adi_fpga_TddDatapathControl +{ + uint8_t enable; /*!< Set this value to 1 to enable this datapath. Otherwise, set to 0 */ + uint32_t startValue; /*!< Start Value for Datapath Control Module. Effectively the Datapath Delay value */ +} adi_fpga_TddDatapathControl_t; + +/** +* \brief Structure to hold the FPGA TDD state machine parameters +*/ +typedef struct adi_fpga_TddStateMachine +{ + uint32_t loopCount; /*!< Set this value to > 1 to enable looping */ + uint8_t syncExtTrig; /*!< Set this value to 1 to enable external triggering. Otherwise, set to 0 */ + uint32_t frameCount; /*!< Number of Tx LaneRate /40 clock cycles in the desired frame time */ + + adi_fpga_TddTiming_t rx1EnableControl; + adi_fpga_TddTiming_t rx2EnableControl; + adi_fpga_TddTiming_t rx3EnableControl; + adi_fpga_TddTiming_t rx4EnableControl; + + adi_fpga_TddTiming_t orx1EnableControl; + adi_fpga_TddTiming_t orx2EnableControl; + adi_fpga_TddTiming_t orx3EnableControl; + adi_fpga_TddTiming_t orx4EnableControl; + + adi_fpga_TddTiming_t tx1EnableControl; + adi_fpga_TddTiming_t tx2EnableControl; + adi_fpga_TddTiming_t tx3EnableControl; + adi_fpga_TddTiming_t tx4EnableControl; + + adi_fpga_TddTiming_t tx1ToOrx1EnableControl; + adi_fpga_TddTiming_t tx2ToOrx1EnableControl; + adi_fpga_TddTiming_t tx1ToOrx2EnableControl; + adi_fpga_TddTiming_t tx2ToOrx2EnableControl; + adi_fpga_TddTiming_t tx3ToOrx3EnableControl; + adi_fpga_TddTiming_t tx4ToOrx3EnableControl; + adi_fpga_TddTiming_t tx3ToOrx4EnableControl; + adi_fpga_TddTiming_t tx4ToOrx4EnableControl; + + adi_fpga_TddTiming_t extTrig1; + adi_fpga_TddTiming_t extTrig2; + adi_fpga_TddTiming_t extTrig3; + adi_fpga_TddTiming_t extTrig4; + + adi_fpga_TddDatapathControl_t rxDatapath0; + adi_fpga_TddDatapathControl_t rxDatapath1; + adi_fpga_TddDatapathControl_t rxDatapath2; + adi_fpga_TddDatapathControl_t txDatapath0; + adi_fpga_TddDatapathControl_t txDatapath1; + +} adi_fpga_TddStateMachine_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ADI_FPGA9025_TDD_TYPES_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/adi_platform.c b/driver/rfic/rf/adrv9025/c_src/platforms/adi_platform.c new file mode 100644 index 0000000..e1f53e7 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/adi_platform.c @@ -0,0 +1,260 @@ +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include "adi_platform.h" + + + + +#if 0 +#include "ads9/ads9_init.h" +#include "ads9/ads9_spi.h" +#include "ads9/ads9_logging.h" +#include "ads9/ads9_timer.h" +#include "ads9/ads9_bbic_control.h" + +#include "ads8/ads8_init.h" +#include "ads8/ads8_spi.h" +#include "ads8/ads8_logging.h" +#include "ads8/ads8_timer.h" +#include "ads8/ads8_bbic_control.h" +#endif + +#include "ucp2/ucp2_init.h" +#include "ucp2/ucp2_spi.h" +#include "ucp2/ucp2_logging.h" +#include "ucp2/ucp2_timer.h" +#include "ucp2/ucp2_bbic_control.h" + +#include "adi_platform_identify.h" + +/* + * Function pointer assignemt for default configuration + */ + +/* Initialization interface to open, init, close drivers and pointers to resources */ +int32_t(*adi_hal_HwOpen)(void *devHalCfg) = NULL; +int32_t(*adi_hal_HwClose)(void *devHalCfg) = NULL; +int32_t(*adi_hal_HwReset)(void *devHalCfg, uint8_t pinLevel) = NULL; +int32_t(*adi_hal_SpiInit)(void *devHalCfg) = NULL; /* TODO: remove? called by HwOpen() */ +void* (*adi_hal_DevHalCfgCreate)(uint32_t interfaceMask, uint8_t spiChipSelect, const char *logFilename) = NULL; +int32_t(*adi_hal_DevHalCfgFree)(void *devHalCfg) = NULL; +int32_t(*adi_hal_HwVerify)(void *devHalCfg) = NULL; + +/* SPI Interface */ +int32_t (*adi_hal_SpiWrite)(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes) = NULL; + +int32_t (*adi_hal_SpiRead)(void* devHalCfg, + const uint8_t txData[], + uint8_t rxData[], + uint32_t numRxBytes) = NULL; + +/* Custom SPI streaming interface*/ +int32_t (*adi_hal_CustomSpiStreamWrite)(void* devHalCfg, + const uint16_t address, + const uint8_t txData[], + uint32_t numTxBytes, + uint8_t numBytesofAddress, + uint8_t numBytesOfDataPerStream) = NULL; + +int32_t (*adi_hal_CustomSpiStreamRead)(void* devHalCfg, + const uint16_t address, + uint8_t rxData[], + uint32_t numRxBytes, + uint8_t numBytesofAddress, + uint8_t numBytesOfDataPerStream) = NULL; + +/* Logging interface */ +int32_t (*adi_hal_LogFileOpen)(void* devHalCfg, + const char* filename) = NULL; + +int32_t (*adi_hal_LogLevelSet)(void* devHalCfg, + int32_t logLevel) = NULL; + +int32_t (*adi_hal_LogLevelGet)(void* devHalCfg, + int32_t* logLevel) = NULL; + +int32_t (*adi_hal_LogWrite)(void* devHalCfg, + int32_t logLevel, + const char* comment, + va_list args) = NULL; + +int32_t (*adi_hal_LogFileClose)(void* devHalCfg) = NULL; + +/* Timer interface */ +int32_t (*adi_hal_Wait_ms)(void* devHalCfg, + uint32_t time_ms) = NULL; + +int32_t (*adi_hal_Wait_us)(void* devHalCfg, + uint32_t time_us) = NULL; + +/* only required to support the FPGA / BBIC control interface */ +int32_t (*adi_hal_BbicRegisterRead)(void* devHalCfg, + uint32_t addr, + uint32_t* data) = NULL; + +int32_t (*adi_hal_BbicRegisterWrite)(void* devHalCfg, + uint32_t addr, + uint32_t data) = NULL; + +int32_t (*adi_hal_BbicRegistersRead)(void* devHalCfg, + uint32_t addr, + uint32_t data[], + uint32_t numDataWords) = NULL; + +int32_t (*adi_hal_BbicRegistersWrite)(void* devHalCfg, + uint32_t addr, + uint32_t data[], + uint32_t numDataWords) = NULL; + +/** + * \brief Platform setup + * + * \param devHalInfo void pointer to be casted to the HAL config structure + * \param platform Platform to be assigning the function pointers + * + * \return + */ +int32_t adi_hal_PlatformSetup(void* devHalInfo, + adi_hal_Platforms_e platform) +{ + UNUSED_PARA(devHalInfo); + adi_hal_Err_e error = ADI_HAL_OK; + switch (platform) + { +#if 0 + case ADI_ADS9_PLATFORM: + adi_hal_HwOpen = ads9_HwOpen; + adi_hal_HwClose = ads9_HwClose; + adi_hal_HwReset = ads9_HwReset; + adi_hal_DevHalCfgCreate = ads9_DevHalCfgCreate; + adi_hal_DevHalCfgFree = ads9_DevHalCfgFree; + adi_hal_HwVerify = ads9_HwVerify; + + adi_hal_SpiInit = ads9_SpiInit; /* TODO: remove? called by HwOpen() */ + adi_hal_SpiWrite = ads9_SpiWrite_v2; //ads9_SpiWrite; + adi_hal_SpiRead = ads9_SpiRead_v2; + adi_hal_CustomSpiStreamWrite = NULL; + adi_hal_CustomSpiStreamRead = NULL; + + adi_hal_LogFileOpen = ads9_LogFileOpen; + adi_hal_LogLevelSet = ads9_LogLevelSet; + adi_hal_LogLevelGet = ads9_LogLevelGet; + adi_hal_LogWrite = ads9_LogWrite; + adi_hal_LogFileClose = ads9_LogFileClose; + + adi_hal_Wait_us = ads9_TimerWait_us; + adi_hal_Wait_ms = ads9_TimerWait_ms; + + /* only required to support the ADI FPGA*/ + adi_hal_BbicRegisterRead = ads9_BbicRegisterRead; + adi_hal_BbicRegisterWrite = ads9_BbicRegisterWrite; + adi_hal_BbicRegistersRead = ads9_BbicRegistersRead; + adi_hal_BbicRegistersWrite = ads9_BbicRegistersWrite; + + break; + + case ADI_ADS8_PLATFORM: + adi_hal_HwOpen = ads8_HwOpen; + adi_hal_HwClose = ads8_HwClose; + adi_hal_HwReset = ads8_HwReset; + adi_hal_DevHalCfgCreate = ads8_DevHalCfgCreate; + adi_hal_DevHalCfgFree = ads8_DevHalCfgFree; + adi_hal_HwVerify = ads8_HwVerify; + + adi_hal_SpiInit = ads8_SpiInit; /* TODO: remove? called by HwOpen() */ + adi_hal_SpiWrite = ads8_SpiWrite_v2; + adi_hal_SpiRead = ads8_SpiRead_v2; + adi_hal_CustomSpiStreamWrite = NULL; + adi_hal_CustomSpiStreamRead = NULL; + + adi_hal_LogFileOpen = ads8_LogFileOpen; + adi_hal_LogLevelSet = ads8_LogLevelSet; + adi_hal_LogLevelGet = ads8_LogLevelGet; + adi_hal_LogWrite = ads8_LogWrite; + adi_hal_LogFileClose = ads8_LogFileClose; + + adi_hal_Wait_us = ads8_TimerWait_us; + adi_hal_Wait_ms = ads8_TimerWait_ms; + + /* only required to support the ADI FPGA*/ + adi_hal_BbicRegisterRead = ads8_BbicRegisterRead; + adi_hal_BbicRegisterWrite = ads8_BbicRegisterWrite; + adi_hal_BbicRegistersRead = ads8_BbicRegistersRead; + adi_hal_BbicRegistersWrite = ads8_BbicRegistersWrite; + + break; +#endif + case ADI_UCP2_PLATFORM: + adi_hal_HwOpen = ucp2_HwOpen; + adi_hal_HwClose = ucp2_HwClose; + adi_hal_HwReset = ucp2_HwReset; + adi_hal_DevHalCfgCreate = ucp2_DevHalCfgCreate; + adi_hal_DevHalCfgFree = ucp2_DevHalCfgFree; + adi_hal_HwVerify = ucp2_HwVerify; + + adi_hal_SpiInit = ucp2_SpiInit; /* TODO: remove? called by HwOpen() */ + adi_hal_SpiWrite = ucp2_SpiWrite_v2; //ucp2_SpiWrite; + adi_hal_SpiRead = ucp2_SpiRead_v2; + adi_hal_CustomSpiStreamWrite = NULL; + adi_hal_CustomSpiStreamRead = NULL; + + adi_hal_LogFileOpen = ucp2_LogFileOpen; + adi_hal_LogLevelSet = ucp2_LogLevelSet; + adi_hal_LogLevelGet = ucp2_LogLevelGet; + adi_hal_LogWrite = ucp2_LogWrite; + adi_hal_LogFileClose = ucp2_LogFileClose; + + adi_hal_Wait_us = ucp2_TimerWait_us; + adi_hal_Wait_ms = ucp2_TimerWait_ms; + + /* only required to support the ADI FPGA*/ + adi_hal_BbicRegisterRead = ucp2_BbicRegisterRead; + adi_hal_BbicRegisterWrite = ucp2_BbicRegisterWrite; + adi_hal_BbicRegistersRead = ucp2_BbicRegistersRead; + adi_hal_BbicRegistersWrite = ucp2_BbicRegistersWrite; + + break; +#if 0 + case ADI_UNKNOWN_PLATFORM: + adi_hal_HwOpen = NULL; + adi_hal_HwClose = NULL; + adi_hal_HwReset = NULL; + adi_hal_DevHalCfgCreate = NULL; + adi_hal_DevHalCfgFree = NULL; + adi_hal_HwVerify = NULL; + + adi_hal_SpiInit = NULL; /* TODO: remove? called by HwOpen() */ + adi_hal_SpiWrite = NULL; + adi_hal_SpiRead = NULL; + adi_hal_CustomSpiStreamWrite = NULL; + adi_hal_CustomSpiStreamRead = NULL; + + adi_hal_LogFileOpen = NULL; + adi_hal_LogLevelSet = NULL; + adi_hal_LogLevelGet = NULL; + adi_hal_LogWrite = ads8_LogWrite; + adi_hal_LogFileClose = NULL; + + adi_hal_Wait_us = NULL; + adi_hal_Wait_ms = NULL; + + /* only required to support the ADI FPGA*/ + adi_hal_BbicRegisterRead = ads8_BbicRegisterRead; + adi_hal_BbicRegisterWrite = ads8_BbicRegisterWrite; + adi_hal_BbicRegistersRead = ads8_BbicRegistersRead; + adi_hal_BbicRegistersWrite = ads8_BbicRegistersWrite; + break; +#endif + default: + error = ADI_HAL_GEN_SW; + break; + } + + return error; +} diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/adi_platform.h b/driver/rfic/rf/adrv9025/c_src/platforms/adi_platform.h new file mode 100644 index 0000000..fd3bf1e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/adi_platform.h @@ -0,0 +1,157 @@ +/** +* \file adi_platform.h +* \brief Contains ADI Transceiver Hardware Abstraction functions interface +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +*/ + +/** +* \Page Disclaimer Legal Disclaimer +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef __ADI_PLATFORM_H__ +#define __ADI_PLATFORM_H__ + +#ifdef __GNUC__ /* __unix__ verify if our linux image declare this */ +#define OS_Windows 0 +#else /* windows */ + +#if _WIN64 == 0 /* _Win32 */ + #define OS_Windows 32 +#elif _WIN64 == 1 /* _Win64 */ + #define OS_Windows 64 +#endif +#endif + +#include "adi_platform_types.h" + + + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef UNUSED_PARA +#define UNUSED_PARA(x) (void)(x) +#endif + +/** + * BBIC Init, Open, Close functions + */ +extern int32_t (*adi_hal_HwOpen)(void* devHalCfg); + +extern int32_t (*adi_hal_HwClose)(void* devHalCfg); + +extern int32_t (*adi_hal_HwReset)(void* devHalCfg, + uint8_t pinLevel); + +extern int32_t (*adi_hal_HwVerify)(void *devHalCfg); + +extern void* (*adi_hal_DevHalCfgCreate)(uint32_t interfaceMask, + uint8_t spiChipSelect, + const char* logFilename); + +extern int32_t (*adi_hal_DevHalCfgFree)(void* devHalCfg); + +/** + * BBIC SPI functions + */ +extern int32_t (*adi_hal_SpiInit)(void* devHalCfg); /* TODO Remove */ +extern int32_t (*adi_hal_SpiWrite)(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes); + +extern int32_t (*adi_hal_SpiRead)(void* devHalCfg, + const uint8_t txData[], + uint8_t rxData[], + uint32_t numRxBytes); + +/** +* Custom Spi streaming functions. Users don't need to implement streaming specific hal layer functions if they want to use standard SpiWrite/Read hal layer functions for streaming +*/ +extern int32_t (*adi_hal_CustomSpiStreamWrite)(void* devHalCfg, + const uint16_t address, + const uint8_t txData[], + uint32_t numTxBytes, + uint8_t numBytesofAddress, + uint8_t numBytesOfDataPerStream); + +extern int32_t (*adi_hal_CustomSpiStreamRead)(void* devHalCfg, + const uint16_t address, + uint8_t rxData[], + uint32_t numRxBytes, + uint8_t numBytesofAddress, + uint8_t numBytesOfDataPerStream); + +/** + * BBIC Logging functions + */ +extern int32_t (*adi_hal_LogFileOpen)(void* devHalCfg, + const char* filename); + +extern int32_t (*adi_hal_LogFileClose)(void* devHalCfg); + +extern int32_t (*adi_hal_LogLevelSet)(void* devHalCfg, + int32_t logLevel); + +extern int32_t (*adi_hal_LogLevelGet)(void* devHalCfg, + int32_t* logLevel); + +extern int32_t (*adi_hal_LogWrite)(void* devHalCfg, + int32_t logLevel, + const char* comment, + va_list argp); + +/** + * BBIC Timer functions + */ +extern int32_t (*adi_hal_Wait_us)(void* devHalCfg, + uint32_t time_us); + +extern int32_t (*adi_hal_Wait_ms)(void* devHalCfg, + uint32_t time_ms); + +/** + * BBIC Hal layer setup + */ +extern int32_t adi_hal_PlatformSetup(void* devHalCfg, + adi_hal_Platforms_e platform); + +/** + * BBIC GPIO functions - Currently only used to toggle hard reset pin on each device. + * + * ADI FPGA platform functions (only required for ADI FPGA platform) + */ +extern int32_t (*adi_hal_BbicRegisterRead)(void* devHalCfg, + uint32_t addr, + uint32_t* data); + +extern int32_t (*adi_hal_BbicRegisterWrite)(void* devHalCfg, + uint32_t addr, + uint32_t data); + +extern int32_t (*adi_hal_BbicRegistersRead)(void* devHalCfg, + uint32_t addr, + uint32_t data[], + uint32_t numDataWords); + +extern int32_t (*adi_hal_BbicRegistersWrite)(void* devHalCfg, + uint32_t addr, + uint32_t data[], + uint32_t numDataWords); + +/** + * Platform and board discovery functions + * This functions are called while in board discovery in order to assignate the correct HAL layer and FPGA drivers + */ +extern int32_t (*adi_hal_PlatformIdentify)(uint32_t* platform); + +extern struct FRU_DATA*(*adi_hal_BoardIdentify)(void* devHalCfg); + +#ifdef __cplusplus +} +#endif +#endif /* __ADI_PLATFORM_H__ */ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/adi_platform_types.h b/driver/rfic/rf/adrv9025/c_src/platforms/adi_platform_types.h new file mode 100644 index 0000000..c8d6faf --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/adi_platform_types.h @@ -0,0 +1,269 @@ +/** + * Copyright 2015 - 2020 Analog Devices Inc. + * Released under the ADRV9025 API license, for more information. + * see the "LICENSE.pdf" file in this zip file. + */ + +#ifndef __ADI_PLATFORM_TYPES_H__ +#define __ADI_PLATFORM_TYPES_H__ + +#include +#include +#include + +#define ADI_HAL_STRING_LENGTH 64 +#define ADI_HAL_MAX_LOG_LINE 1000 + +#ifdef __cplusplus +extern +"C" + { +#endif + +#define SPI_CHIP_SELECT_0 0 +#define SPI_CHIP_SELECT_1 1 +#define SPI_CHIP_SELECT_2 2 + +#define ADI_MANUFACTURER "Analog Devices" + +#define BBIC_CORE_REG_PATH "/dev/uio0\0" +#define BBIC_RAM_PATH "/dev/uio1\0" +#define BBIC_SPI_ADV_REG_PATH "/dev/uio2\0" + +#define I2C_EEPROM_PATH "/sys/bus/i2c/devices/3-0050/eeprom" + +#define MOTHERBOARD_NAME_PATH "/sys/class/uio/uio0/name" + +#define MEM_SIZE_16M 0x1000 +#define MEM_SIZE_256MB 0x10000000 +#define MEM_SIZE_512MB 0x20000000 +#define MEM_SIZE_1GB 0x40000000 + +#define SYM2STR(x) #x + + +/** + * \brief Enum of possible Errors Detected by HAL layer to be communicated + * to ADI APIs. + */ +typedef enum adi_hal_Err +{ + ADI_HAL_OK = 0, /*!< HAL function successful. No error Detected */ + ADI_HAL_I2C_FAIL, /*!< HAL I2C operation failure. I2C controller Down */ + ADI_HAL_SPI_FAIL, /*!< HAL SPI operation failure. SPI controller Down */ + ADI_HAL_GPIO_FAIL, /*!< HAL GPIO function Failure */ + ADI_HAL_TIMER_FAIL, /*!< HAL Timer function Failure */ + ADI_HAL_LOGGING_FAIL, /*!< HAL Logging function Failure */ + ADI_HAL_LOGGGING_LEVEL_FAIL, /*!< HAL Logging level Failure */ + ADI_HAL_WAIT_TIMEOUT, /*!< HAL function Timeout */ + ADI_HAL_GEN_SW, /*!< HAL function failed due to general invalid HAL data*/ + ADI_HAL_FUNCTION_NOT_IMP, /*!< HAL function error, not implemented in HAL layer */ + ADI_HAL_LIBRARY_NOT_AVAILABLE, /*!< HAL function error, HAL layer library not found or available in this build */ + ADI_HAL_WARNING, /*!< HAL function warning that non critical error was detected*/ + ADI_HAL_BBICCTRL_FAIL, /*!< BBIC control interface HAL function failure */ + ADI_HAL_NULL_PTR /*!< Function supplied with null pointer */ +} adi_hal_Err_e; + +/** + * \brief An enumerated type in bit mask format to list the log message + * categories or groups. + */ +/* In order to separate trx_hal and the platform layer this enum is duplicated. + its sister enum is adi_common_LogLevel_e in adi_common_log_types.h which need to reflect + any changes to this enum. +*/ +typedef enum adi_hal_LogLevel +{ + ADI_HAL_LOG_NONE = 0x0, /*!< HAL Log enum to represent all types of log messages not selected */ + ADI_HAL_LOG_MSG = 0x1, /*!< HAL Log enum to represent a log message type*/ + ADI_HAL_LOG_WARN = 0x2, /*!< HAL Log enum to represent a warning message type*/ + ADI_HAL_LOG_ERR = 0x4, /*!< HAL Log enum to represent a error message type*/ + ADI_HAL_LOG_API = 0x8, /*!< HAL Log enum to represent an API function entry for logging purposes*/ + ADI_HAL_LOG_API_PRIV = 0x10, /*!< HAL Log enum to represent an Private API function entry for logging purposes*/ + ADI_HAL_LOG_BF = 0x20, /*!< HAL Log enum to represent a BF function entry for logging purposes*/ + ADI_HAL_LOG_HAL = 0x40, /*!< HAL Log enum to represent a ADI HAL function entry for logging purposes*/ + ADI_HAL_LOG_SPI = 0x80, /*!< HAL Log enum to represent a spi transaction type*/ + ADI_HAL_LOG_ALL = 0xFF /*!< HAL Log enum to represent all types of log messages selected */ +} adi_hal_LogLevel_e; + +/** + * \brief Enum type for HAL platforms + */ +typedef enum adi_hal_Platforms +{ + ADI_ADS8_PLATFORM, /*!< ADS8 Platform (default for ADRV9010) */ + ADI_ADS9_PLATFORM, /*!< ADS9 Platform (default for ADRV9025) */ + ADI_UCP2_PLATFORM, /*!< UCP2 Platform (default for ADRV9025) */ + + ADI_UNKNOWN_PLATFORM +} adi_hal_Platforms_e; + +/** +* \brief Enum type for HAL Board (daughter card) Identity +*/ +typedef enum adi_hal_Boards +{ + ADI_BOARD_UNKNOWN, + ADI_BOARD_BLANK_EEPROM, /*!< Selects for no daughter board present */ + ADI_BOARD_9010CE01, /*!< 9010 CE 01 board */ + ADI_BOARD_9010EE01, /*!< 9010 EE 01 board */ + ADI_BOARD_9010STSHAL, /*!< 9010 STS board */ + ADI_BOARD_9025CE01, /*!< 9025 CE 01 board */ + ADI_BOARD_9025EE01, /*!< 9025 EE 01 board */ + ADI_BOARD_9026CE01, /*!< 9026 CE 01 board */ + ADI_BOARD_9024CE01, /*!< 9024 CE 01 board */ + ADI_BOARD_9029CE01, /*!< 9029 CE 01 board */ + ADI_BOARD_9020CE01, /*!< 9020 CE 01 board */ + ADI_BOARD_9025STSHAL, /*!< 9025 STS board */ + + /* for range checking */ + ADI_BOARD_9010_MIN = ADI_BOARD_9010CE01, + ADI_BOARD_9010_MAX = ADI_BOARD_9010STSHAL, + ADI_BOARD_9025_MIN = ADI_BOARD_9025CE01, + ADI_BOARD_9025_MAX = ADI_BOARD_9025STSHAL +} adi_hal_Boards_e; + +/** +* \brief Enum type for HAL Board (daughter card) and platform initialization +*/ +typedef enum adi_hal_dev_initialization +{ + ADI_DEV_CFG_CREATED = 0x00000001, + ADI_PLATFORM_CREATED = 0x00000002, /*!< 9010 CE board rev 1D */ + ADI_BOARD_CREATED = 0x00000004 /*!< 9010 EE board rev 1C */ +} adi_hal_dev_initialization_e; + +/** + * \brief Enum type for the hardware interfaces supported by the platform. + * Each device specifies which interfaces it needs from the BBIC in its + * devHalCfg structure. + */ +typedef enum adi_hal_Interfaces +{ + ADI_HAL_INTERFACE_SPI = 0x01, /* Device requires SPI interface from BBIC */ + ADI_HAL_INTERFACE_LOG = 0x02, /* Device requires Logging interface from BBIC */ + ADI_HAL_INTERFACE_BBICCTRL = 0x04, /* Device requires BBIC Register/Control interface from BBIC. Mututally exclusive with HWRESET */ + ADI_HAL_INTERFACE_HWRESET = 0x08, /* Device requires GPIO (reset pins) interface from BBIC. Mututally exclusive with BBICCTRL */ + ADI_HAL_INTERFACE_TIMER = 0x10, /* Device requires Timer interface from BBIC */ + ADI_HAL_INTERFACE_I2C = 0x20 /* Device requires I2C interface from BBIC */ +} adi_hal_Interfaces_e; + + +/** + * \brief Enum for the specific BBIC interfaces + */ +typedef enum adi_hal_BbicInterfaces +{ + ADI_HAL_BBIC_CORE = 0x01, /* Core FPGA registers, including HwReset pins */ + ADI_HAL_BBIC_RAM = 0x02, /* Ram registers */ + ADI_HAL_BBIC_SPI = 0x04 /* Advanced SPI configuration registers */ +} adi_hal_BbicInterfaces_e; + +/** + * \brief Data structure for Logging facility + */ +typedef struct adi_hal_LogCfg +{ + uint8_t interfaceEnabled; + int32_t logLevel; /*!< valid 0 - 0xFF */ + uintptr_t logfd; + char logFileName[ADI_HAL_STRING_LENGTH]; + uint32_t currentLineNumber; +} adi_hal_LogCfg_t; + +/** + * \brief Data structure for SPI configuration + */ +typedef struct adi_hal_SpiCfg +{ + uint8_t interfaceEnabled; + int fd; + char spidevName[ADI_HAL_STRING_LENGTH]; + uint8_t chipSelectIndex; /*!< valid 1~8 */ + uint8_t CPHA; /*!< clock phase, sets which clock edge the data updates (valid 0 or 1) */ + uint8_t CPOL; /*!< clock polarity 0 = clock starts low, 1 = clock starts high */ + uint8_t enSpiStreaming; /*!< Not implemented. SW feature to improve SPI throughput. */ + uint8_t autoIncAddrUp; /*!< Not implemented. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr = addr-1 */ + uint8_t fourWireMode; /*!< 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode. */ + uint32_t spiClkFreq_Hz; /*!< SPI Clk frequency in Hz (default 25000000), platform will use next lowest frequency that it's baud rate generator can create */ + uint8_t spiActionDisable; /*!< Disables the spi Driver actually writing the data */ +} adi_hal_SpiCfg_t; + +/** + * \brief Data structure for Hardware reset pin functionality + */ + typedef struct adi_hal_HwResetCfg +{ + uint8_t interfaceEnabled; + uint32_t resetPinIndex; +} adi_hal_HwResetCfg_t; + + +/** + * \brief Data structure for I2C configuration + */ +typedef struct adi_hal_I2cCfg +{ + uint8_t interfaceEnabled; + int fd; + char drvName[ADI_HAL_STRING_LENGTH]; +} adi_hal_I2cCfg_t; + +/** + * \brief Data structure for memory Fpga Driver configuration + */ +typedef struct adi_hal_fpga_AxiCfg +{ + char drvName[ADI_HAL_STRING_LENGTH]; + uint32_t mapSize; + uintptr_t mappedMemoryPtr; + int fd; +} adi_hal_fpga_AxiCfg_t; + +/** + * \brief Data structure to hold platform Hardware layer + * settings for all system related feature of the ADI transceiver device + * If the system has multiple ADI transceivers, the user should create one of + * these structures per transceiver device to specify the HAL settings + * per transceiver device. + */ +typedef struct adi_hal_BbicCfg +{ + uint8_t interfaceEnabled; /*!< Bitmask for the BBIC interfaces. Follows adi_hal_BbicInterfaces_e */ + adi_hal_fpga_AxiCfg_t coreRegsCfg; + adi_hal_fpga_AxiCfg_t ramCfg; + adi_hal_fpga_AxiCfg_t spiAdvRegsCfg; +} adi_hal_BbicCfg_t; + +typedef struct adi_hal_TimerCfg +{ + uint8_t interfaceEnabled; + /* ADS9 platform does not require any instance members per device */ +} adi_hal_TimerCfg_t; + + +/** + * \brief Data structure to hold platform Hardware layer + * settings for all system/platform related features. + + * If the system has multiple ADI transceivers/devices, the user should create one of + * these structures per device to specify the HAL settings + * per transceiver device. + */ +typedef struct adi_hal_Cfg +{ + char typeName[ADI_HAL_STRING_LENGTH]; + adi_hal_SpiCfg_t spiCfg; + adi_hal_LogCfg_t logCfg; + adi_hal_BbicCfg_t bbicCfg; + adi_hal_HwResetCfg_t hwResetCfg; + adi_hal_I2cCfg_t i2cCfg; + adi_hal_TimerCfg_t timerCfg; + uint32_t interfaceMask; + +} adi_hal_Cfg_t; + +#ifdef __cplusplus +} +#endif +#endif /* __ADI_PLATFORM_TYPES_H__*/ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_bbic_control.c b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_bbic_control.c new file mode 100644 index 0000000..02e996b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_bbic_control.c @@ -0,0 +1,450 @@ +/** +* \file ads8_bbic_control.c +* \brief Contains ADI Transceiver Hardware Abstraction functions for ADS8 interface to FPGA (BBIC) control registers. +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9010 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include +#include +#include + +#ifdef __GNUC__ +#include +#include +#endif + +#include +#include "ads8_bbic_control.h" + +/********************/ +/* Public functions */ +/********************/ + +/** +* \brief Function to open any necessary resources for the BBIC + interface functions in this file. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_NULL_PTR If devHalCfg pointer is NULL +* \retval ADI_HAL_BBICCTRL_FAIL If critical error trying to open resources +*/ +int32_t ads8_BbicOpen(void *devHalCfg) +{ + adi_hal_Cfg_t *halCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS8 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + +#ifdef __GNUC__ + /* Open UIO driver to FPGA register interface */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_CORE) > 0) && halCfg->bbicCfg.coreRegsCfg.fd <= 0) + { + halCfg->bbicCfg.coreRegsCfg.fd = open(halCfg->bbicCfg.coreRegsCfg.drvName, O_RDWR); + + if (halCfg->bbicCfg.coreRegsCfg.fd < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + /* offset must be page aligned */ + halCfg->bbicCfg.coreRegsCfg.mappedMemoryPtr = (uintptr_t)mmap(NULL, halCfg->bbicCfg.coreRegsCfg.mapSize, PROT_READ | PROT_WRITE, MAP_SHARED, halCfg->bbicCfg.coreRegsCfg.fd, 0); + + if ((void *)halCfg->bbicCfg.coreRegsCfg.mappedMemoryPtr == MAP_FAILED) + { + perror("Error mapping the file for fpga core registers."); + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + } + + /* Open UIO driver to FPGA Data capture memory RAM interface */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_RAM) > 0) && halCfg->bbicCfg.ramCfg.fd <= 0) + { + halCfg->bbicCfg.ramCfg.fd = open(halCfg->bbicCfg.ramCfg.drvName, O_RDWR); + + if (halCfg->bbicCfg.ramCfg.fd < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + /* offset must be page aligned */ + halCfg->bbicCfg.ramCfg.mappedMemoryPtr = (uintptr_t)mmap(NULL, halCfg->bbicCfg.ramCfg.mapSize, PROT_READ | PROT_WRITE, MAP_SHARED, halCfg->bbicCfg.ramCfg.fd, 0); + + if ((void *)halCfg->bbicCfg.ramCfg.mappedMemoryPtr == MAP_FAILED) + { + perror("Error mapping the file for fpga ram."); + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + } + + /* Open UIO driver to FPGA Advanced SPI settings interface */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_SPI) > 0) && halCfg->bbicCfg.spiAdvRegsCfg.fd <= 0) + { + halCfg->bbicCfg.spiAdvRegsCfg.fd = open(halCfg->bbicCfg.spiAdvRegsCfg.drvName, O_RDWR); + + if (halCfg->bbicCfg.spiAdvRegsCfg.fd < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + /* offset must be page aligned */ + halCfg->bbicCfg.spiAdvRegsCfg.mappedMemoryPtr = (uintptr_t)mmap(NULL, halCfg->bbicCfg.spiAdvRegsCfg.mapSize, PROT_READ | PROT_WRITE, MAP_SHARED, halCfg->bbicCfg.spiAdvRegsCfg.fd, 0); + + if ((void *)halCfg->bbicCfg.spiAdvRegsCfg.mappedMemoryPtr == MAP_FAILED) + { + perror("Error mapping the file for fpga spiAdvRegsCfg registers."); + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + } + +#endif /* __GNUC__ */ + return halError; +} + +/** +* \brief Function to close any necessary resources for the BBIC + interface functions in this file. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_NULL_PTR If devHalCfg pointer is NULL +* \retval ADI_HAL_BBICCTRL_FAIL If critical error trying to close resources +*/ +int32_t ads8_BbicClose(void *devHalCfg) +{ + adi_hal_Cfg_t *halCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS8 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + +#ifdef __GNUC__ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_CORE) > 0) && halCfg->bbicCfg.coreRegsCfg.fd != 0) + { + halError = munmap((void *)halCfg->bbicCfg.coreRegsCfg.mappedMemoryPtr, halCfg->bbicCfg.coreRegsCfg.mapSize); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + halError = close(halCfg->bbicCfg.coreRegsCfg.fd); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + halCfg->bbicCfg.coreRegsCfg.fd = 0; + } + + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_RAM) > 0) && halCfg->bbicCfg.ramCfg.fd != 0) + { + halError = munmap((void *)halCfg->bbicCfg.ramCfg.mappedMemoryPtr, halCfg->bbicCfg.ramCfg.mapSize); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + halError = close(halCfg->bbicCfg.ramCfg.fd); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + halCfg->bbicCfg.ramCfg.fd = 0; + } + + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_SPI) > 0) && halCfg->bbicCfg.spiAdvRegsCfg.fd != 0) + { + halError = munmap((void *)halCfg->bbicCfg.spiAdvRegsCfg.mappedMemoryPtr, halCfg->bbicCfg.spiAdvRegsCfg.mapSize); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + halError = close(halCfg->bbicCfg.spiAdvRegsCfg.fd); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + halCfg->bbicCfg.spiAdvRegsCfg.fd = 0; + } +#endif /* __GNUC__ */ + + return halError; +} + +/** +* \brief Function to initialize any necessary resources for the BBIC + interface functions in this file. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads8_BbicInit(void *devHalCfg) +{ + (void)(devHalCfg); + /* ADI ADS8 platform does not require any BBIC register/control init */ + return (int32_t)ADI_HAL_OK; +} + +/** + * \brief Function to read a single BBIC control register + * + * \param devHalCfg Pointer to device instance specific platform settings + * \param addr 32bit address of BBIC register to read + * \param data 32bit Pointer to store return value representing the data of the register at the specified address + * + * \retval ADI_HAL_OK Function completed successfully + * \retval ADI_HAL_NULL_PTR devHalCfg pointer is NULL or data pointer is NULL + */ +int32_t ads8_BbicRegisterRead(void *devHalCfg, uint32_t addr, uint32_t *data) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + static const uint8_t READ_REG = 0; + + if ((devHalCfg == NULL) || (data == NULL)) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + halError = ads8_fpga_AxiReadWrite(devHalCfg, READ_REG, addr, data); + + return halError; +} + +/** + * \brief Function to write a single BBIC control register + * + * \param devHalCfg Pointer to device instance specific platform settings + * \param addr 32bit address of BBIC register to write + * \param data 32bit data to write to the register at the specified address + * + * \retval ADI_HAL_OK Function completed successfully + * \retval ADI_HAL_NULL_PTR devHalCfg pointer is NULL + */ +int32_t ads8_BbicRegisterWrite(void *devHalCfg, uint32_t addr, uint32_t data) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + static const uint8_t WRITE_REG = 1; + + if (devHalCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + halError = ads8_fpga_AxiReadWrite(devHalCfg, WRITE_REG, addr, &data); + + return halError; +} + +/** + * \brief Function to read multiple consecutive BBIC control registers starting at a specified register address. + * + * \param devHalCfg Pointer to device instance specific platform settings + * \param addr 32bit address of BBIC register to start reading from + * \param data 32bit Pointer to store return array representing the data starting at the specified register address + and ending at (addr + numDataWords -1) + * \param numDataWords Number of elements in the data array + * + * \retval ADI_HAL_OK Function completed successfully + * \retval ADI_HAL_NULL_PTR devHalCfg pointer is NULL + */ +int32_t ads8_BbicRegistersRead(void *devHalCfg, uint32_t addr, uint32_t data[], uint32_t numDataWords) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + static const uint8_t READ_REG = 0; + + if (devHalCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + halError = ads8_fpga_AxiBulkReadWrite(devHalCfg, READ_REG, addr, data, numDataWords); + + return halError; +} + +/** + * \brief Function to write multiple consecutive BBIC control registers starting at a specified register address. + * + * \param devHalCfg Pointer to device instance specific platform settings + * \param addr 32bit address of BBIC register to start writing to + * \param data 32bit Pointer to array representing the data to write starting at the specified register address + and ending at (addr + numDataWords -1) + * \param numDataWords Number of elements in the data array + * + * \retval ADI_HAL_OK Function completed successfully + * \retval ADI_HAL_NULL_PTR devHalCfg pointer is NULL + */ +int32_t ads8_BbicRegistersWrite(void *devHalCfg, uint32_t addr, uint32_t data[], uint32_t numDataWords) +{ + static const uint8_t WRITE_REG = 1; + + return ads8_fpga_AxiBulkReadWrite(devHalCfg, WRITE_REG, addr, data, numDataWords); +} + +/*********************/ +/* Private functions */ +/*********************/ + +/** +* \brief Writes and reads to the BBIC (FPGA) AXI memory mapped registers. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param writeFlag (Hi)tells the function to write the data to address addr +* \Param writeFlag 1 = write, 0 = read. +* \param data the data to write to address addr. +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_GEN_SW If addr is out of valid range +* \retval ADI_HAL_BBICCTRL_FAIL If critical error during read or write operation +*/ +int32_t ads8_fpga_AxiReadWrite(void *devHalCfg, uint8_t writeFlag, uint32_t addr, uint32_t *data) +{ + adi_hal_Cfg_t *halCfg = NULL; + adi_hal_fpga_AxiCfg_t *axiCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + uint32_t offsetAddr = 0; + void *ptr = NULL; + + if (devHalCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if ((addr >= ADS8_FPGA_UIO0_START_ADDRESS) && + (addr <= ADS8_FPGA_UIO0_STOP_ADDRESS)) + { + offsetAddr = addr - ADS8_FPGA_UIO0_START_ADDRESS; + axiCfg = &halCfg->bbicCfg.coreRegsCfg; + } + else if ((addr >= ADS8_FPGA_UIO2_START_ADDRESS) && + (addr <= ADS8_FPGA_UIO2_STOP_ADDRESS)) + { + offsetAddr = addr - ADS8_FPGA_UIO2_START_ADDRESS; + axiCfg = &halCfg->bbicCfg.spiAdvRegsCfg; + } + else + { + /* The offset parameter is the actual fpga memory address. Range check to make sure it's valid */ + halError = (int32_t)ADI_HAL_GEN_SW; + return halError; + } + +#ifdef __GNUC__ + + if (axiCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + ptr = (void *)axiCfg->mappedMemoryPtr; + + /* If UIO driver file not open */ + if (ptr == MAP_FAILED || ptr == NULL) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + if (writeFlag) + { + *((uint32_t *)((uintptr_t)ptr + offsetAddr)) = *data; + } + else + { + *data = *((uint32_t*)((uintptr_t)ptr + offsetAddr)); + } + +#endif /* __GNUC__ */ + + return halError; +} + +/** +* \brief Writes and reads to the BBIC (FPGA) AXI memory mapped registers. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \Param writeFlag 1 = write, 0 = read. +* \param addr the addrers to write the data to. +* \param data the data to write to address addr. +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_BBICCTRL_FAIL If critcal error during read or write transaction +*/ +int32_t ads8_fpga_AxiBulkReadWrite(void *devHalCfg, uint8_t writeFlag, uint32_t addr, uint32_t data[], const uint32_t numData) +{ + adi_hal_Cfg_t *halCfg = NULL; + adi_hal_fpga_AxiCfg_t *ramCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + /* uint32_t offsetAddr = 0; */ + void *ptr = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + ramCfg = &halCfg->bbicCfg.ramCfg; + + if (ramCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + if (addr + numData > ramCfg->mapSize) + { + halError = (int32_t)ADI_HAL_BBICCTRL_FAIL; + return halError; + } + +#ifdef __GNUC__ + + ptr = (void *)ramCfg->mappedMemoryPtr; + + /* If UIO driver file not open */ + if (ptr == MAP_FAILED || ptr == NULL) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + if (writeFlag) + { + memcpy((void *)((uintptr_t)ptr + addr), data, numData * sizeof(uint32_t)); + } + else + { + memcpy(data, (void *)((uintptr_t)ptr + addr), numData * sizeof(uint32_t)); + } + +#endif /* __GNUC__ */ + + return halError; +} diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_bbic_control.h b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_bbic_control.h new file mode 100644 index 0000000..2c3d62b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_bbic_control.h @@ -0,0 +1,45 @@ +/** +* \file ads8_bbic_control.h +* \brief Contains ADI Transceiver Hardware Abstraction functions for ADS8 interface to FPGA (BBIC) control registers. +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9010 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef __ADS8_BBIC_CONTROL_H__ +#define __ADS8_BBIC_CONTROL_H__ + +#include +#include "adi_platform_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADS8_FPGA_UIO0_START_ADDRESS 0x43000000 +#define ADS8_FPGA_UIO0_STOP_ADDRESS 0x43415FFF +#define ADS8_FPGA_UIO2_START_ADDRESS 0x44A00000 +#define ADS8_FPGA_UIO2_STOP_ADDRESS 0x44A00FFF + +int32_t ads8_BbicOpen(void *devHalCfg); +int32_t ads8_BbicClose(void *devHalCfg); +int32_t ads8_BbicInit(void *devHalCfg); +int32_t ads8_BbicRegisterRead(void *devHalCfg, uint32_t addr, uint32_t *data); +int32_t ads8_BbicRegisterWrite(void *devHalCfg, uint32_t addr, uint32_t data); +int32_t ads8_BbicRegistersRead(void *devHalCfg, uint32_t addr, uint32_t data[], uint32_t numDataWords); +int32_t ads8_BbicRegistersWrite(void *devHalCfg, uint32_t addr, uint32_t data[], uint32_t numDataWords); + +/* Local helper functions */ +/* TODO: remove these functions */ +int32_t ads8_fpga_AxiReadWrite(void *devHalCfg, uint8_t writeFlag, uint32_t addr, uint32_t *data); +int32_t ads8_fpga_AxiBulkReadWrite(void *devHalCfg, uint8_t writeFlag, uint32_t addr, uint32_t data[], const uint32_t numData); + +#ifdef __cplusplus +} +#endif +#endif /*__ADS8_BBIC_CONTROL_H__*/ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_i2c.c b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_i2c.c new file mode 100644 index 0000000..2f4b0d5 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_i2c.c @@ -0,0 +1,254 @@ +/** + * \file ads8_i2c.c + * Analog Devices ADS8 Platform + microzed hardware abstraction layer + * + * Copyright 2017 Analog Devices Inc. + * + * Support for linux layer I2C functions + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9010 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifdef __GNUC__ +#include +#endif /* __GNUC__ */ + +#include +#include +#include "ads8_i2c.h" + +/** +* \brief Function to open/allocate any necessary resources for the I2C +* functions below. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads8_I2cOpen(void *devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t *halCfg = NULL; + adi_hal_I2cCfg_t *i2cCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS8 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + i2cCfg = &halCfg->i2cCfg; + + if (i2cCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + +#ifdef __GNUC__ + if (i2cCfg->fd <= 0) + { + i2cCfg->fd = open(i2cCfg->drvName, O_RDWR); + + if (i2cCfg->fd < 0) + { + return (int32_t)ADI_HAL_I2C_FAIL; + } + } +#endif /* __GNUC__ */ + return halError; +} + +/** +* \brief Function to close/deallocate any necessary resources for the I2C +* functions below. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads8_I2cClose(void *devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t *halCfg = NULL; + adi_hal_I2cCfg_t *i2cCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS8 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + i2cCfg = &halCfg->i2cCfg; + + if (i2cCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + +#ifdef __GNUC__ + if (i2cCfg->fd != 0) + { + halError = close(i2cCfg->fd); + if (halError < 0) + { + return (int32_t)ADI_HAL_I2C_FAIL; + } + + i2cCfg->fd = 0; + } +#endif /* __GNUC__ */ + + return halError; +} + +/** +* \brief Function to init any necessary resources for the I2C +* functions below. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads8_I2cInit(void *devHalCfg) +{ + (void) (devHalCfg); + return (int32_t)ADI_HAL_OK; +} + +/** +* \brief Function to write to an I2C device from the BBIC +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Byte array of data to write to the I2C device. First byte +* should be the I2C register address followed by one or more data bytes. +* \param numTxBytes Number of bytes in the txData array +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads8_I2cWrite(void *devHalCfg, const uint8_t txData[], uint32_t numTxBytes) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + int retVal = 0; + adi_hal_Cfg_t *halCfg = NULL; + adi_hal_I2cCfg_t *i2cCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS8 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + i2cCfg = &halCfg->i2cCfg; + if (i2cCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + if ((numTxBytes > 0) && + (txData != NULL)) + { + if (i2cCfg->fd > 0) + { +#ifdef __GNUC__ + retVal = write(i2cCfg->fd, &txData[0], numTxBytes); + if (retVal != (int)numTxBytes) + { + perror("I2C : Failed to Write to device"); + return (int32_t)ADI_HAL_I2C_FAIL; + } +#endif + } + else + { + perror("I2C : Failed to Write to device, file descriptor invalid"); + return (int32_t)ADI_HAL_GEN_SW; + } + } + + return halError; +} + +/** +* \brief Function to read from an I2C device to the BBIC +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Byte array of data to write to the I2C device. Depending on the +* I2C device, this might just be 1 byte containing the register +* address to read +* \param numTxBytes Number of bytes in the txData array +* \param rxData Byte array to return the read back data +* \param numRxBytes Number of bytes to read back, and size of rxData array +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads8_I2cRead(void *devHalCfg, const uint8_t txData[], uint32_t numTxBytes, uint8_t rxData[], uint32_t numRxBytes) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + int retVal = 0; + adi_hal_Cfg_t *halCfg = NULL; + adi_hal_I2cCfg_t *i2cCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS8 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + i2cCfg = &halCfg->i2cCfg; + + if (i2cCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + if (i2cCfg->fd > 0) + { + /* Write Register address */ + if ((numTxBytes > 0) && + (txData != NULL)) + { +#ifdef __GNUC__ + retVal = write(i2cCfg->fd, &txData[0], numTxBytes); + if (retVal != (int)numTxBytes) + { + perror("I2C : Failed to Write to I2C device"); + return (int32_t)ADI_HAL_I2C_FAIL; + } +#endif + } + + /* Read data */ + if ((numRxBytes > 0) && + (rxData != NULL)) + { +#ifdef __GNUC__ + retVal = read(i2cCfg->fd, &rxData[0], numRxBytes); + if (retVal != (int)numRxBytes) + { + perror("I2C : Failed to Read from I2C device"); + return (int32_t)ADI_HAL_I2C_FAIL; + } +#endif + } + } + else + { + perror("I2C : Failed to Write to device, file descriptor invalid"); + return (int32_t)ADI_HAL_GEN_SW; + } + + + return halError; +} diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_i2c.h b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_i2c.h new file mode 100644 index 0000000..871fe9e --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_i2c.h @@ -0,0 +1,34 @@ +/** + * \file ads8_i2c.h + * Analog Devices ADS8 Platform + microzed hardware abstraction layer + * + * Copyright 2017 Analog Devices Inc. + * + * Support for linux layer I2C functions + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9010 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ +#ifndef __ADS8_I2C_H__ +#define __ADS8_I2C_H__ + +#include +#include "adi_platform_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t ads8_I2cOpen(void *devHalCfg); +int32_t ads8_I2cClose(void *devHalCfg); +int32_t ads8_I2cInit(void *devHalCfg); +int32_t ads8_I2cWrite(void *devHalCfg, const uint8_t txData[], uint32_t numTxBytes); +int32_t ads8_I2cRead(void *devHalCfg, const uint8_t txData[], uint32_t numTxBytes, uint8_t rxData[], uint32_t numRxBytes); + +#ifdef __cplusplus +} +#endif +#endif /* __ADS8_I2C_H__ */ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_init.c b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_init.c new file mode 100644 index 0000000..321cdb8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_init.c @@ -0,0 +1,537 @@ +/** +* \file ads8_init.c +* \brief Contains ADI Transceiver Hardware Abstraction functions for hardware mode. +* Analog Devices maintains and provides updates to this code layer for the ADS8 platform. +* The end user should not modify this file or any code in this directory. The end user +* may provide a similar platform layer that can be used in place of this platform layer, +* that uses the same function prototypes. +*/ + +/** +* \Page Disclaimer Legal Disclaimer +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9010 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include +#include +#include +#include "ads8_init.h" +#include "ads8_spi.h" +#include "ads8_logging.h" +#include "ads8_timer.h" +#include "ads8_bbic_control.h" +#include "ads8_i2c.h" + + +static int32_t ads8_LogWriteHelper(void *devHalCfg, int32_t logLevel, const char *logMessage, ...) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + va_list args; + va_start(args, logMessage); + halError = ads8_LogWrite(devHalCfg, logLevel, logMessage, args); + va_end(args); + return halError; +} + + +/** +* \brief Opens all necessary files and device drivers for a specific device +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +*/ +int32_t ads8_HwOpen(void *devHalCfg) +{ + adi_hal_Cfg_t *halCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + char logMessage[ADI_HAL_MAX_LOG_LINE]; + int32_t result = 0; + + logMessage[0] = 0; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->logCfg.interfaceEnabled > 0) + { + if (halCfg->logCfg.logFileName[0] == '\0') + { + halError = ads8_LogFileOpen(devHalCfg, "ads8_adihal.log"); + } + else + { + halError = ads8_LogFileOpen(devHalCfg, NULL); + } + + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + result = snprintf(logMessage + strlen(logMessage), ADI_HAL_MAX_LOG_LINE, "ads8_LogFileOpen: device index %d\n", halCfg->spiCfg.chipSelectIndex); + if (result < 0) + { + return (int32_t)ADI_HAL_LOGGING_FAIL; + } + + halError = ads8_LogWriteHelper(devHalCfg, ADI_HAL_LOG_MSG, logMessage); + + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + } + + if (halCfg->spiCfg.interfaceEnabled > 0) + { + halError = ads8_SpiOpen(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads8_SpiInit(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + } + + if (halCfg->bbicCfg.interfaceEnabled > 0) + { + halError = ads8_BbicOpen(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads8_BbicInit(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + } + + if (halCfg->hwResetCfg.interfaceEnabled > 0) + { + /* ADS8 has nothing to open, as this interface is supported by the + * BBIC control interface */ + + /* Verify BBIC control interface was enabled */ + if (halCfg->bbicCfg.interfaceEnabled == 0) + { + halError = ADI_HAL_GEN_SW; + return halError; + } + } + + if (halCfg->i2cCfg.interfaceEnabled > 0) + { + halError = ads8_I2cOpen(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads8_I2cInit(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + } + + if (halCfg->timerCfg.interfaceEnabled > 0) + { + halError = ads8_TimerOpen(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads8_TimerInit(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + } + + /* ADS8 does not require any code to open /init timer support since using linux nanosleep function */ + + return halError; +} + +/** +* \brief Gracefully shuts down the the hardware closing any open resources +* such as log files, I2C, SPI, GPIO drivers, timer resources, etc. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +*/ +int32_t ads8_HwClose(void *devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halError = ads8_LogLevelSet(devHalCfg, ADI_HAL_LOG_NONE); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads8_LogFileClose(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads8_SpiClose(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads8_BbicClose(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads8_I2cClose(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads8_TimerClose(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + return halError; +} + +/** +* \brief This function control a BBIC GPIO pin that connects to the reset pin +* of each device. +* +* This function is called by each device API giving access to the Reset pin +* connected to each device. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param pinLevel The desired pin logic level 0=low, 1=high to set the GPIO pin to. +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +*/ +int32_t ads8_HwReset(void *devHalCfg, uint8_t pinLevel) +{ + adi_hal_Cfg_t *halCfg = NULL; + adi_hal_HwResetCfg_t *hwResetCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + int32_t retVal = 0; + uint32_t readData = 0; + uint32_t writeData = 0; + uint32_t pinLevelBit = 0; + uint32_t resetPinBitPostion = 0; + static const uint32_t FPGA_RESETPIN_REGISTER = 0x43041004; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + hwResetCfg = &halCfg->hwResetCfg; + + if (hwResetCfg == NULL) + { + return ADI_HAL_NULL_PTR; + } + +#ifdef __GNUC__ + + if (hwResetCfg->interfaceEnabled > 0) + { + /* Note the pin level is inverted in the ADS8 FPGA...hence then logic inversion here */ + pinLevelBit = (pinLevel > 0) ? 0 : 1; + + /* hwResetCfg->resetPinIndex is the bit position in FPGA_RESETPIN_REGISTER + * for the reset pin of the requested device */ + switch (hwResetCfg->resetPinIndex) + { + case 1: /* ADRV9010: For ADS8 platform, FPGA register 0x43041004 bit 1 controls RESET pin */ + { + resetPinBitPostion = hwResetCfg->resetPinIndex; + break; + } + + case 2: /* AD9528: For ADS8 platform, FPGA register 0x43041004 bit 2 controls RESET pin */ + { + resetPinBitPostion = hwResetCfg->resetPinIndex; + break; + } + + default: + { + /* Invalid Hardware reset pin index for ADS8 Platform */ + return ADI_HAL_GPIO_FAIL; + } + } + + /* Perform read/modify/write to change the bit of interest in the FPGA + * register that controls the reset pins to each device */ + retVal = ads8_BbicRegisterRead(devHalCfg, FPGA_RESETPIN_REGISTER, &readData); + if (retVal > 0) + { + return ADI_HAL_GPIO_FAIL; + } + + writeData = readData & ~(1UL << resetPinBitPostion); + writeData |= (pinLevelBit << resetPinBitPostion); + + retVal = ads8_BbicRegisterWrite(devHalCfg, FPGA_RESETPIN_REGISTER, writeData); + if (retVal > 0) + { + return ADI_HAL_GPIO_FAIL; + } + } + +#endif /* __GNUC__ */ + + return halError; +} + +/** +* \brief This function is a helper function to fill out the members of the +* devHalCfg structure with driver names for this specific (ADS8) platform. +* +* This function allows keeping the platform specific knowledge of driver names +* in this layer of code. Higher layers of code can call this to fill out the +* devHalCfg structure correctly for the ADS8 platform. +* +* Each device gets a unique instance of the devHalCfg structure describing the +* device resources for that device, such as the SPI chip select, etc. +* +* \param interfaceMask A mask that represents which platform interfaces are required by a particular device (SPI, Logging, etc) +* \param spiChipSelect The chip select index describing the particular device this structure is for (0, 1, 2 valid on ADS8) +* \param logFilename The filename of the logfile for this device. +*/ +void* ads8_DevHalCfgCreate(uint32_t interfaceMask, uint8_t spiChipSelect, const char *logFilename) +{ + adi_hal_Cfg_t *halCfg = (adi_hal_Cfg_t*)calloc(1, sizeof(adi_hal_Cfg_t)); + + if (halCfg == NULL) + { + return NULL; + } + + /* Disable all interfaces, and enable only if they are needed by the specific device */ + halCfg->spiCfg.interfaceEnabled = 0; + halCfg->logCfg.interfaceEnabled = 0; + halCfg->bbicCfg.interfaceEnabled = 0; + + /* If device requires SPI interface */ + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_SPI) > 0) + { + halCfg->spiCfg.interfaceEnabled = 1; + + switch (spiChipSelect) + { + case 0: + { + strncpy(halCfg->spiCfg.spidevName, "/dev/spidev12345.0\0", ADI_HAL_STRING_LENGTH); + halCfg->spiCfg.chipSelectIndex = spiChipSelect; + break; + } + case 1: + { + strncpy(halCfg->spiCfg.spidevName, "/dev/spidev12345.1\0", ADI_HAL_STRING_LENGTH); + halCfg->spiCfg.chipSelectIndex = spiChipSelect; + break; + } + case 2: + { + strncpy(halCfg->spiCfg.spidevName, "/dev/spidev12345.2\0", ADI_HAL_STRING_LENGTH); + halCfg->spiCfg.chipSelectIndex = spiChipSelect; + break; + } + default: + { + free(halCfg); + return NULL; + } + } + + /* Default SPI settings */ + halCfg->spiCfg.autoIncAddrUp = 1; + halCfg->spiCfg.CPHA = 0; + halCfg->spiCfg.CPOL = 0; + halCfg->spiCfg.enSpiStreaming = 0; + halCfg->spiCfg.fourWireMode = 1; + halCfg->spiCfg.spiActionDisable = 0; + halCfg->spiCfg.spiClkFreq_Hz = 25000000; + } + + /* If device requires Logging interface */ + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_LOG) > 0) + { + halCfg->logCfg.interfaceEnabled = 1; + halCfg->logCfg.logLevel = ADI_HAL_LOG_ALL; + strncpy(halCfg->logCfg.logFileName, logFilename, ADI_HAL_STRING_LENGTH); + /* ensure null termination */ + halCfg->logCfg.logFileName[sizeof(halCfg->logCfg.logFileName)-1] = '\0'; + } + + /* If device requires FPGA register interface */ + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_BBICCTRL) > 0) + { + halCfg->bbicCfg.interfaceEnabled = (ADI_HAL_BBIC_CORE | ADI_HAL_BBIC_RAM | ADI_HAL_BBIC_SPI); + strncpy(halCfg->bbicCfg.coreRegsCfg.drvName, "/dev/uio0\0", ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.coreRegsCfg.mapSize = 0x1000000; /* 16MB */ + strncpy(halCfg->bbicCfg.ramCfg.drvName, "/dev/uio1\0", ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.ramCfg.mapSize = 0x10000000; /* 256MB */ + + strncpy(halCfg->bbicCfg.spiAdvRegsCfg.drvName, "/dev/uio2\0", ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.spiAdvRegsCfg.mapSize = 0x1000; /* 16MB */ + } + else if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_HWRESET) > 0) + { + halCfg->hwResetCfg.interfaceEnabled = 1; + halCfg->bbicCfg.interfaceEnabled = ADI_HAL_BBIC_CORE | ADI_HAL_BBIC_SPI; + + strncpy(halCfg->bbicCfg.coreRegsCfg.drvName, "/dev/uio0\0", ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.coreRegsCfg.mapSize = 0x42000; /* 264kB to access hwReset TODO: include bitfields to get the correct address? */ + + strncpy(halCfg->bbicCfg.spiAdvRegsCfg.drvName, "/dev/uio2\0", ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.spiAdvRegsCfg.mapSize = 0x1000; /* 16MB */ + + switch(spiChipSelect) + { + case 0: + { + halCfg->hwResetCfg.resetPinIndex = 1; /* ADRV9010 reset pin bit position in FPGA register */ + break; + } + case 1: + { + halCfg->hwResetCfg.resetPinIndex = 2; /* AD9528 reset pin bit position in FPGA register */ + break; + } + case 2: + { + halCfg->hwResetCfg.resetPinIndex = 0; /* SPI2 does not need hwReset, only access to Adv Spi. A 0 value here will not get past the hwReset range checks */ + break; + } + default: + free(halCfg); + return NULL; + } + + } + + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_I2C) > 0) + { + /* TODO: Place holder for future support + * Need to update the passed parameters to include the driver location*/ + halCfg->i2cCfg.interfaceEnabled = 0; + strncpy(halCfg->i2cCfg.drvName, "/sys/bus/i2c/devices/3-0050/eeprom", ADI_HAL_STRING_LENGTH); + } + + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_TIMER) > 0) + { + halCfg->timerCfg.interfaceEnabled = 1; + /* Currently no timer config structure for ADS8 platform */ + } + halCfg->interfaceMask = interfaceMask; + return halCfg; +} + +int32_t ads8_DevHalCfgFree(void *devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + + free(devHalCfg); + + return halError; +} + +int32_t ads8_HwVerify(void *devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t *halCfg = NULL; + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + /* interpret the interface mask */ + + /* ADI_HAL_INTERFACE_SPI */ + if ((halCfg->interfaceMask & (uint32_t)ADI_HAL_INTERFACE_SPI) > 0) /* Device requires spi interface */ + { + /* throw an error if pointer is NULL */ + if (halCfg->spiCfg.fd == 0) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + } + } + + /* ADI_HAL_INTERFACE_LOG */ + if ((halCfg->interfaceMask & (uint32_t)ADI_HAL_INTERFACE_LOG) > 0) /* Device requires logging interface */ + { + /* throw an error if pointer is NULL */ + if (halCfg->logCfg.logfd == 0) + { + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + } + } + + /* ADI_HAL_INTERFACE_BBICCTRL */ + if ((halCfg->interfaceMask & (uint32_t)ADI_HAL_INTERFACE_BBICCTRL) > 0) /* Device requires fpga register interface */ + { + /* throw an error if pointer is NULL */ + if (halCfg->bbicCfg.coreRegsCfg.fd == 0 || + halCfg->bbicCfg.ramCfg.fd == 0 || + halCfg->bbicCfg.spiAdvRegsCfg.fd == 0) + { + halError = (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + } + + /* ADI_HAL_HWRESET */ + /* Not affected by HwClose */ + + /* ADI_HAL_INTERFACE_TIMER */ + /* Not affected by HwClose */ + + /* ADI_HAL_INTERFACE_I2C */ + if ((halCfg->interfaceMask & (uint32_t)ADI_HAL_INTERFACE_I2C) > 0) /* Device requires i2c interface */ + { + /* throw an error if pointer is NULL */ + if (halCfg->i2cCfg.fd == 0) + { + halError = (int32_t)ADI_HAL_I2C_FAIL; + } + } + return halError; +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_init.h b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_init.h new file mode 100644 index 0000000..b7a7c2f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_init.h @@ -0,0 +1,36 @@ +/** +* \file ads8_init.h +* \brief Contains ADI Transceiver Hardware Abstraction functions for the ADS8 Platform. +* Analog Devices maintains and provides updates to this code layer for the ADS8 platform. +* The end user should not modify this file or any code in this directory. The end user +* may provide a similar platform layer that can be used in place of this platform layer, +* that uses the same function prototypes. +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9010 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef __ADS8_INIT_H__ +#define __ADS8_INIT_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t ads8_HwOpen(void *devHalCfg); +int32_t ads8_HwReset(void *devHalCfg, uint8_t pinLevel); +int32_t ads8_HwClose(void *devHalCfg); +int32_t ads8_HwVerify(void *devHalCfg); + +void* ads8_DevHalCfgCreate(uint32_t interfaceMask, uint8_t spiChipSelect, const char *logFilename); +int32_t ads8_DevHalCfgFree(void *devHalCfg); + +#ifdef __cplusplus +} +#endif +#endif /*__ADS8_INIT_H__*/ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_logging.c b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_logging.c new file mode 100644 index 0000000..1648a1a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_logging.c @@ -0,0 +1,367 @@ +/* +* \file ads8_logging.c +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9010 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include +#include +#include +#include +#include +#include "ads8_logging.h" + +/** +* \brief Opens a logFile. If the file is already open it will be closed and reopened. +* +* This function opens the file for writing and saves the resulting file +* descriptor to the devHalCfg structure. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param filename The user provided name of the file to open. +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +* \retval ADI_HAL_LOGGING_FAIL If the function failed to open or write to the specified filename +*/ +int32_t ads8_LogFileOpen(void *devHalCfg, const char *filename) +{ + (void)(filename); + int32_t halError = ADI_HAL_OK; + int32_t result = 0; + adi_hal_Cfg_t *halCfg = NULL; + FILE *logfd = NULL; + struct tm tm = { 0 }; + time_t t = { 0 }; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + logfd = (FILE*)halCfg->logCfg.logfd; + + //if logfile already open, close it + if (logfd != 0) + { + halError = ads8_LogFileClose(devHalCfg); + } + + /* open a new log file */ + logfd = fopen(halCfg->logCfg.logFileName, "w+"); + if (logfd == NULL) + { + return (int32_t)ADI_HAL_LOGGING_FAIL; + } + + halCfg->logCfg.logfd = (uintptr_t)logfd; + + t = time(NULL); + + tm = *localtime(&t); + + result = fprintf(logfd, "API log file \nStart date %04d-%02d-%02d %02d:%02d:%02d \nLogging level %d\n\n\n", tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec, halCfg->logCfg.logLevel); + if (result < 0) + { + return ADI_HAL_LOGGING_FAIL; + } + + result = fflush(logfd); + if (result < ADI_HAL_OK) + { + halError = ADI_HAL_LOGGING_FAIL; + } + + return halError; +} + +/** +* \brief Flushes the logFile buffer to the currently open log file. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +*/ +int32_t ads8_LogFileFlush(void *devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t *halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->logCfg.logfd != 0) + { + halError = fflush((FILE*)halCfg->logCfg.logfd); + } + else + { + /* File not open, can not flush, No Error */ + halError = (int32_t)ADI_HAL_OK; + } + + return halError; +} + +/** +* \brief Gracefully closes the log file(s). +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +* \retval ADI_HAL_LOGGING_FAIL Error while flushing or closing the log file. +*/ +int32_t ads8_LogFileClose(void *devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + int32_t result = 0; + adi_hal_Cfg_t *halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->logCfg.logfd != 0) + { + result = fflush((FILE*)halCfg->logCfg.logfd); + if (result < 0) + { + halError = ADI_HAL_LOGGING_FAIL; + } + + result = fclose((FILE*)halCfg->logCfg.logfd); + if (result < 0) + { + halError = ADI_HAL_LOGGING_FAIL; + } + + halCfg->logCfg.logfd = 0; + /* Log level reset was causing issues with the log files, logging was disabled */ + /* halCfg->logCfg.logLevel = 0; */ + } + else + { + /* Log file is not open, can not close the file - no error */ + halError = ADI_HAL_OK; + } + + return halError; +} + +/** +* \brief Sets the log level, allowing the end user to select the granularity of +* what events get logged. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param logLevel A mask of valid log levels to allow to be written to the log file. +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +*/ +int32_t ads8_LogLevelSet(void *devHalCfg, int32_t logLevel) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t *halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + halCfg->logCfg.logLevel = (logLevel & (int32_t)ADI_HAL_LOG_ALL); + + return halError; +} + +/** + * \brief Gets the currently set log level: the mask of different types of log + * events that are currently enabled to be logged. + * + * \param devHalCfg Pointer to device instance specific platform settings + * \param logLevel Returns the current log level mask. + * + * \retval ADI_HAL_OK Function completed successfully, no action required + * \retval ADI_HAL_NULL_PTR The function has been called with a null pointer + */ +int32_t ads8_LogLevelGet(void *devHalCfg, int32_t *logLevel) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t *halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + *logLevel = halCfg->logCfg.logLevel; + + return halError; +} + + +/** +* \brief Writes a message to the currently open logFile specified in the +* adi_hal_LogCfg_t of the devHalCfg structure passed +* +* Uses the vfprintf functionality to allow the user to supply the format and +* the number of arguments that will be logged. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param logLevel the log level to be written into +* \param comment the string to include in the line added to the log. +* \param argp variable argument list to be printed +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +* \retval ADI_HAL_LOGGING_FAIL If the function failed to flush to write +*/ +int32_t ads8_LogWrite(void *devHalCfg, int32_t logLevel, const char *comment, va_list argp) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + int32_t result = 0; + adi_hal_Cfg_t *halCfg = NULL; + time_t t = time(NULL); + struct tm tm = { 0 }; + FILE *logfd = NULL; + char logMessage[ADI_HAL_MAX_LOG_LINE]; + const char *logLevelChar; + logMessage[0] = 0; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if ((halCfg->logCfg.interfaceEnabled == 0) || (halCfg->logCfg.logLevel == (int32_t)ADI_HAL_LOG_NONE)) + { + /* If logging disabled, exit gracefully */ + halError = (int32_t)ADI_HAL_OK; + return halError; + } + + if(logLevel > (int32_t)ADI_HAL_LOG_ALL) + { + halError = (int32_t)ADI_HAL_LOGGGING_LEVEL_FAIL; + return halError; + } + + /* Auto Open of log file is currently disabled */ + if (halCfg->logCfg.logfd == 0) + { + /* Log file is not open */ + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + return halError; + } + else + { + logfd = (FILE *)halCfg->logCfg.logfd; + + if (halCfg->logCfg.currentLineNumber >= ADS8_LOG_MAX_NUM_LINES) + { + /* seek back to beginning of file */ + /* fseek(logfd, 2, SEEK_SET); */ + rewind(logfd); + halCfg->logCfg.currentLineNumber = 0; + } + + /* Print Log type */ + if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_MSG) && (logLevel == (int32_t)ADI_HAL_LOG_MSG)) + { + logLevelChar = "MESSAGE:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_WARN) && (logLevel == (int32_t)ADI_HAL_LOG_WARN)) + { + logLevelChar = "WARNING:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_ERR) && (logLevel == (int32_t)ADI_HAL_LOG_ERR)) + { + logLevelChar = "ERROR:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_API) && (logLevel == (int32_t)ADI_HAL_LOG_API)) + { + logLevelChar = "API_LOG:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_BF) && (logLevel == (int32_t)ADI_HAL_LOG_BF)) + { + logLevelChar = "BF_LOG:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_HAL) && (logLevel == (int32_t)ADI_HAL_LOG_HAL)) + { + logLevelChar = "ADI_HAL_LOG:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_SPI) && (logLevel == (int32_t)ADI_HAL_LOG_SPI)) + { + logLevelChar = "SPI_LOG:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_API_PRIV) && (logLevel == (int32_t)ADI_HAL_LOG_API_PRIV)) + { + logLevelChar = "API_PRIV_LOG:"; + } + else + { + /* Nothing to log - exit cleanly */ + return (int32_t)ADI_HAL_OK; + } + + tm = *localtime(&t); + /* Print timestamp */ + result = snprintf(logMessage, ADI_HAL_MAX_LOG_LINE, "%04d-%02d-%02d %02d:%02d:%02d: %s", tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec, logLevelChar); + if (result < 0) + { + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + } + + result = vsnprintf(logMessage + strlen(logMessage), ADI_HAL_MAX_LOG_LINE, comment, argp) ; + if (result < 0) + { + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + return halError; + } + + result = fprintf(logfd, "%s\n", logMessage); + if (result < 0) + { + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + return halError; + } + + result = fflush(logfd); + if (result < 0) + { + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + return halError; + } + + halCfg->logCfg.currentLineNumber += 1; + } + + return halError; +} + diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_logging.h b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_logging.h new file mode 100644 index 0000000..4ae8997 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_logging.h @@ -0,0 +1,41 @@ +/** +* \file ads8_logging.h +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9010 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADS8_LOGGING_H_ +#define _ADS8_LOGGING_H_ + +#include +#include +#include "adi_platform_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + + /* + * Only allow log file to have MAX_NUM_LINES to prevent it from growing too large + * If max lines reached, start back at line 0. + * */ +#define ADS8_LOG_MAX_NUM_LINES 250000 + +int32_t ads8_LogFileOpen(void *devHalCfg, const char *filename); +int32_t ads8_LogFileFlush(void *devHalCfg); +int32_t ads8_LogFileClose(void *devHalCfg); +int32_t ads8_LogLevelSet(void *devHalCfg, int32_t logLevel); +int32_t ads8_LogLevelGet(void *devHalCfg, int32_t *logLevel); +int32_t ads8_LogWrite(void *devHalCfg, int32_t logLevel, const char *comment, va_list argp); + + +#ifdef __cplusplus +} +#endif + +#endif /* _ADS8_LOGGING_H_ */ \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_spi.c b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_spi.c new file mode 100644 index 0000000..696edc8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_spi.c @@ -0,0 +1,1040 @@ +/** + * \file ads8_spi.c + * Analog Devices ADS8 Platform + microzed hardware abstraction layer + * + * Copyright 2017 Analog Devices Inc. + * + * Support for linux layer SPI functions + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9010 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifdef __GNUC__ +#include +#include +#include +#endif /* __GNUC__ */ + +#include +#include +#include "ads8_spi.h" +#include "ads8_bbic_control.h" + +/** +* \brief Opens/allocates any necessary resources to communicate via SPI to a + particular device specified in the devHalCfg structure. +* +* This function should perform any necessary steps to open the SPI master resource +* on the BBIC to enable SPI communications to a particular SPI device. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the device driver was not opened successfully +*/ +int32_t ads8_SpiOpen(void *devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t *halCfg = NULL; + adi_hal_SpiCfg_t *spiCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS8 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + spiCfg = &halCfg->spiCfg; + + if (spiCfg == NULL) + { + return ADI_HAL_NULL_PTR; + } + +#ifdef __GNUC__ + if (spiCfg->fd <= 0) + { + spiCfg->fd = open(spiCfg->spidevName, O_RDWR); + + if (spiCfg->fd < 0) + { + return ADI_HAL_SPI_FAIL; + } + } +#endif /* __GNUC__ */ + return halError; +} + +/** +* \brief Closes any resources open/allocated for a specific SPI device +* +* Any information needed to close the particular SPI device should be passed in +* the devHalCfg structure. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the device driver was not closed successfully +*/ +int32_t ads8_SpiClose(void *devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t *halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS8 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.spiActionDisable == 0) + { + + if (halCfg->spiCfg.fd != 0) + { +#ifdef __GNUC__ + halError = close(halCfg->spiCfg.fd); + if (halError < 0) + { + return ADI_HAL_SPI_FAIL; + } +#endif /* __GNUC__ */ + + halCfg->spiCfg.fd = 0; + } + + } + return halError; +} + +/** +* \brief Initializes the SPI device driver mode, bits per word, and speed +* +* Any settings needed should be passed in the devHalCfg structure +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the SPI initialization failed +*/ +int32_t ads8_SpiInit(void *devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t *halCfg = NULL; + uint8_t spiMode = 0; + uint32_t bitsPerWord = 0; + uint32_t speed = 0; + int32_t result = 0; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS8 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + /* Initialize SPI driver with clockrate, SPI mode, etc */ + if (halCfg->spiCfg.spiActionDisable == 0) + { + + bitsPerWord = 8; + speed = halCfg->spiCfg.spiClkFreq_Hz; + + /*Get Chips SPI Driver File Descriptor*/ + if (halCfg->spiCfg.fd <= 0) + { + return ADI_HAL_SPI_FAIL; + } + + /* + * spi mode + */ + if ((halCfg->spiCfg.CPOL > 1) || (halCfg->spiCfg.CPHA > 1)) + { + /* + * Invalid SPI mode: CPOL and CPHA should be 1 or 0 + */ + return ADI_HAL_SPI_FAIL; + } + + spiMode = (halCfg->spiCfg.CPOL << 1) | halCfg->spiCfg.CPHA; + +#ifdef __GNUC__ + result = ioctl(halCfg->spiCfg.fd, SPI_IOC_WR_MODE, &spiMode); + if (result < 0) + { + /* + * Error settings requested SPI mode + */ + return ADI_HAL_SPI_FAIL; + } + + /* + * bits per word + */ + result = ioctl(halCfg->spiCfg.fd, SPI_IOC_WR_BITS_PER_WORD, &bitsPerWord); + if (result < 0) + { + /* + * Error setting the number of Bits per SPI word + */ + return ADI_HAL_SPI_FAIL; + } + + /* + * max speed hz + */ + result = ioctl(halCfg->spiCfg.fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); + if (result < 0) + { + /* + * Error Setting max SPI clock frequency for current chip select index. + */ + return ADI_HAL_SPI_FAIL; + } +#endif /* __GNUC__ */ + } /* If SPI hardware interface enabled */ + + + return halError; +} + +/** +* \brief Write an array of 8-bit data to a SPI device +* +* The function will write numTxBytes number of bytes to the SPI device +* selected in the devHalCfg structure. +* +* \dep_begin +* \dep{adi_hal_SpiCfg_t} +* \dep{adi_hal_SpiCfg_t->fd} +* \dep_end +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array txData buffer that has numTxBytes number of bytes +* \param numTxBytes The length of txData array +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not written successfully +*/ +int32_t ads8_SpiWrite(void *devHalCfg, const uint8_t txData[], uint32_t numTxBytes) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t *halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.spiActionDisable == 0) + { +#ifdef __GNUC__ + int32_t result = 0; + + if (halCfg->spiCfg.fd > 0) + { + result = write(halCfg->spiCfg.fd, txData, numTxBytes); + if (result <= 0) + { + halError = ADI_HAL_SPI_FAIL; + } + } + else + { + /* Invalid file descriptor */ + halError = ADI_HAL_SPI_FAIL; + } +#endif /* __GNUC__ */ + } + + return halError; +} + +/** +* \brief Write an array of 8-bit data to a SPI device +* +* The function will write numTxBytes number of bytes to the SPI device +* selected in the devHalCfg structure. + +* This function uses FPGA registers to manage spi transaction. It doesn't use spi device driver. +* +* \dep_begin +* \dep{adi_hal_SpiCfg_t} +* \dep{adi_hal_SpiCfg_t->fd} +* \dep_end +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array txData buffer that has numTxBytes number of bytes +* \param numTxBytes The length of txData array +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not written successfully +*/ +int32_t ads8_SpiWrite_v2(void *devHalCfg, const uint8_t txData[], uint32_t numTxBytes) +{ + static const uint16_t FPGA_FIFO_SIZE = 255; + static const uint32_t WAIT_FIFO_OCCUPANCY = 1024; + static const uint32_t SPI_CONTROL_REGISTER = 0x44A00060; + static const uint32_t SPI_TXFIFO_REGISTER = 0x44A00068; + static const uint32_t SPI_CS_REGISTER = 0x44A00070; + static const uint32_t SPI_TXFIFO_OCY_REGISTER = 0x44A00074; + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t *halCfg = NULL; + uint32_t chipSelMask = 0xFFFFFFFF; //one hot active low active chip select + uint32_t i = 0; + uint32_t readData = 0; + uint16_t numOfChunks = 0; + uint16_t numFifoBytes = 0; + uint16_t remainder = 0; + uint16_t byteCounter = 0; + uint16_t k = 0; + + /* Calculate number of full FIFO transactions and remainder for last flush */ + remainder = numTxBytes % FPGA_FIFO_SIZE; + numOfChunks = (numTxBytes - remainder) / FPGA_FIFO_SIZE; + + if(devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if(halCfg->spiCfg.spiActionDisable == 0) + { + # ifdef __GNUC__ + + /* This function requires access to advanced spi registers through BBIC */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_SPI) == ADI_HAL_BBIC_SPI)) + { + /* Reset Tx/Rx FIFO */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CONTROL_REGISTER, 0x64); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + chipSelMask = (0xFFFFFFFF & ~(1UL << halCfg->spiCfg.chipSelectIndex)); + + /* Write SS register */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CS_REGISTER, chipSelMask); + if(halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Write numOfChunks full chunks and remainder */ + numFifoBytes = FPGA_FIFO_SIZE; + for (k = 0; k < (numOfChunks + 1); k++) + { + /* If we're writing the remainder set numFifoBytes as remainder */ + if (k == numOfChunks) + { + numFifoBytes = remainder; + } + + for (i = 0; i < numFifoBytes; i++) + { + /* Write data bytes into Tx FIFO*/ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_TXFIFO_REGISTER, (uint32_t)txData[byteCounter++]); + if(halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Enable SPI to start transmitting */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CONTROL_REGISTER, 0x06); + if(halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Wait until Tx FIFO is empty*/ + for (i = 0; i < WAIT_FIFO_OCCUPANCY; i++) + { + /* Read Tx FIFO Occupancy */ + halError = ads8_BbicRegisterRead(devHalCfg, SPI_TXFIFO_OCY_REGISTER, &readData); + if(halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + if (readData == 0) + { + break; + } + + if (i == (WAIT_FIFO_OCCUPANCY -1)) + { + /* Timeout */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Reset Tx/Rx FIFO */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CONTROL_REGISTER, 0x64); + if(halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Write SS register */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CS_REGISTER, 0xFFFFFFFF); + if(halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + + } + } + else + { + /* Invalid file descriptor */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + # endif /* __GNUC__ */ + } + + return halError; +} + +/** +* \brief Write an array of 8-bit data to a SPI device +* +* The function will write numTxBytes number of bytes to the SPI device +* selected in the devHalCfg structure. +* +* This function uses FPGA registers to manage spi transaction. It doesn't use spi device driver. +* It implements the spi transfer sequence provided by XILINX DS742 document It's still under test. +* +* \dep_begin +* \dep{adi_hal_SpiCfg_t} +* \dep{adi_hal_SpiCfg_t->fd} +* \dep_end +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array txData buffer that has numTxBytes number of bytes +* \param numTxBytes The length of txData array +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not written successfully +*/ +int32_t ads8_SpiWrite_v3(void *devHalCfg, const uint8_t txData[], uint32_t numTxBytes) +{ + static const uint16_t FPGA_FIFO_SIZE = 256; + static const uint32_t WAIT_FIFO_OCCUPANCY = 1024; + static const uint32_t SPI_CONTROL_REGISTER = 0x44A00060; + static const uint32_t SPI_TXFIFO_REGISTER = 0x44A00068; + static const uint32_t SPI_CS_REGISTER = 0x44A00070; + static const uint32_t SPI_TXFIFO_OCY_REGISTER = 0x44A00074; + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t *halCfg = NULL; + uint32_t chipSelMask = 0xFFFFFFFF; //one hot active low active chip select + uint32_t i = 0; + uint32_t readData = 0; + uint16_t numOfChunks = 0; + uint16_t numFifoBytes = 0; + uint16_t remainder = 0; + uint16_t byteCounter = 0; + uint16_t k = 0; + + /* Calculate number of full FIFO transactions and remainder for last flush */ + remainder = numTxBytes % FPGA_FIFO_SIZE; + numOfChunks = (numTxBytes - remainder) / FPGA_FIFO_SIZE; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.spiActionDisable == 0) + { +# ifdef __GNUC__ + + /* This function requires access to advanced spi registers through BBIC */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_SPI) == ADI_HAL_BBIC_SPI)) + { + /* Reset Tx/Rx FIFO - Set Inhibit */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CONTROL_REGISTER, 0x1E4); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Write numOfChunks full chunks and remainder */ + numFifoBytes = FPGA_FIFO_SIZE; + for (k = 0; k < (numOfChunks + 1); k++) + { + /* If we're writing the remainder set numFifoBytes as remainder */ + if (k == numOfChunks) + { + numFifoBytes = remainder; + } + + for (i = 0; i < numFifoBytes; i++) + { + /* Write data bytes into Tx FIFO*/ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_TXFIFO_REGISTER, (uint32_t)txData[byteCounter++]); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Enable SPI - Set Inhibit */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CONTROL_REGISTER, 0x186); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* CS low */ + chipSelMask = (0xFFFFFFFF & ~(1UL << halCfg->spiCfg.chipSelectIndex)); + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CS_REGISTER, chipSelMask); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Clear Inhibit */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CONTROL_REGISTER, 0x86); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Wait until Tx FIFO is empty*/ + for (i = 0; i < WAIT_FIFO_OCCUPANCY; i++) + { + /* Read Tx FIFO Occupancy */ + halError = ads8_BbicRegisterRead(devHalCfg, SPI_TXFIFO_OCY_REGISTER, &readData); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + if (readData == 0) + { + break; + } + + if (i == (WAIT_FIFO_OCCUPANCY - 1)) + { + /* Timeout */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Reset Tx/Rx FIFO - Set Inhibit */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CONTROL_REGISTER, 0x1E6); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* CS High */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CS_REGISTER, 0xFFFFFFFF); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + + } + + /* Disable SPI - Set Inhibit */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CONTROL_REGISTER, 0x1E4); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + else + { + /* Invalid file descriptor */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + +# endif /* __GNUC__ */ + } + + return halError; +} + +/** +* \brief Read one or more bytes from the device specified by the devHalCfg structure +* +* The function will read numTxRxBytes number of bytes from the SPI device selected in +* the devHalCfg parameter and store the resulting data sent by the device in the rxData +* data buffer. +* +* For each byte in txData written to the device, a byte is read and returned by this +* function at the pointer provided by the rxData parameter. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array that has numTxRxBytes number of bytes +* \param rxData Pointer to byte array where read back data will be returned, that is at least numTxRxBytes in size. +* \param numTxBytes The length of txData and rxData arrays +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not read successfully +*/ +int32_t ads8_SpiRead(void *devHalCfg, const uint8_t txData[], uint8_t rxData[], + uint32_t numTxRxBytes) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + int32_t result = 0; + adi_hal_Cfg_t *halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.fd <= 0) + { + /* Invalid file descriptor */ + return ADI_HAL_SPI_FAIL; + } + + if(halCfg->spiCfg.spiActionDisable == 0) + { +#ifdef __GNUC__ + + /*Get device's SPI Driver File Descriptor*/ + struct spi_ioc_transfer tr = { 0 }; + + tr.tx_buf = (uintptr_t)&txData[0]; + tr.rx_buf = (uintptr_t)&rxData[0]; + tr.len = numTxRxBytes; + tr.delay_usecs = 0; + + result = ioctl(halCfg->spiCfg.fd, SPI_IOC_MESSAGE(1), &tr); + if (result <= 0) + { + halError = ADI_HAL_SPI_FAIL; + } +#endif /* __GNUC__ */ + } + + return halError; +} + +/** +* \brief Read one or more bytes from the device specified by the devHalCfg structure +* +* The function will read numTxRxBytes number of bytes from the SPI device selected in +* the devHalCfg parameter and store the resulting data sent by the device in the rxData +* data buffer. +* +* For each byte in txData written to the device, a byte is read and returned by this +* function at the pointer provided by the rxData parameter. +* +* This function uses FPGA registers to manage spi transaction. It doesn't use spi device driver. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array that has numTxRxBytes number of bytes +* \param rxData Pointer to byte array where read back data will be returned, that is at least numTxRxBytes in size. +* \param numTxBytes The length of txData and rxData arrays +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not read successfully +*/ +int32_t ads8_SpiRead_v2(void *devHalCfg, const uint8_t txData[], uint8_t rxData[], uint32_t numTxRxBytes) +{ + static const uint16_t FPGA_FIFO_SIZE = 255; + static const uint32_t WAIT_FIFO_OCCUPANCY = 1024; + static const uint32_t SPI_CONTROL_REGISTER = 0x44A00060; + static const uint32_t SPI_TXFIFO_REGISTER = 0x44A00068; + static const uint32_t SPI_RXFIFO_REGISTER = 0x44A0006C; + static const uint32_t SPI_CS_REGISTER = 0x44A00070; + static const uint32_t SPI_TXFIFO_OCY_REGISTER = 0x44A00074; + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t *halCfg = NULL; + uint32_t chipSelMask = 0xFFFFFFFF; //one hot active low active chip select + uint32_t i = 0; + uint32_t readData = 0; + uint16_t numOfChunks = 0; + uint16_t numFifoBytes = 0; + uint16_t remainder = 0; + uint16_t txByteCounter = 0; + uint16_t rxByteCounter = 0; + uint16_t k = 0; + + /* Calculate number of full FIFO transactions and remainder for last flush */ + remainder = numTxRxBytes % FPGA_FIFO_SIZE; + numOfChunks = (numTxRxBytes - remainder) / FPGA_FIFO_SIZE; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.spiActionDisable == 0) + { +# ifdef __GNUC__ + + /* This function requires access to advanced spi registers through BBIC */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_SPI) == ADI_HAL_BBIC_SPI)) + { + /* Reset Tx/Rx FIFO */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CONTROL_REGISTER, 0x64); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + chipSelMask = (0xFFFFFFFF & ~(1UL << halCfg->spiCfg.chipSelectIndex)); + + /* Write SS register */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CS_REGISTER, chipSelMask); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Write numOfChunks full chunks and remainder */ + numFifoBytes = FPGA_FIFO_SIZE; + for (k = 0; k < (numOfChunks + 1); k++) + { + /* If we're writing the remainder set numFifoBytes as remainder */ + if (k == numOfChunks) + { + numFifoBytes = remainder; + } + + for (i = 0; i < numFifoBytes; i++) + { + /* Write data bytes into Tx FIFO*/ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_TXFIFO_REGISTER, (uint32_t)txData[txByteCounter++]); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Enable SPI to start transmitting */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CONTROL_REGISTER, 0x06); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Wait until Tx FIFO is empty*/ + for (i = 0; i < WAIT_FIFO_OCCUPANCY; i++) + { + /* Read Tx FIFO Occupancy */ + halError = ads8_BbicRegisterRead(devHalCfg, SPI_TXFIFO_OCY_REGISTER, &readData); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + if (readData == 0) + { + break; + } + + if (i == (WAIT_FIFO_OCCUPANCY - 1)) + { + /* Timeout */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + for (i = 0; i < numFifoBytes; i++) + { + /* Read data bytes from Rx FIFO*/ + uint32_t dataTmp = 0; + halError = ads8_BbicRegisterRead(devHalCfg, SPI_RXFIFO_REGISTER, &dataTmp); + rxData[rxByteCounter++] = (uint8_t)(dataTmp & 0x000000FF); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CONTROL_REGISTER, 0x64); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Write SS register */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CS_REGISTER, 0xFFFFFFFF); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + + } + } + else + { + /* Invalid file descriptor */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + +# endif /* __GNUC__ */ + } + + return halError; +} + +/** +* \brief Read one or more bytes from the device specified by the devHalCfg structure +* +* The function will read numTxRxBytes number of bytes from the SPI device selected in +* the devHalCfg parameter and store the resulting data sent by the device in the rxData +* data buffer. +* +* For each byte in txData written to the device, a byte is read and returned by this +* function at the pointer provided by the rxData parameter. +* +* This function uses FPGA registers to manage spi transaction. It doesn't use spi device driver. +* It implements the spi transfer sequence provided by XILINX DS742 document It's still under test. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array that has numTxRxBytes number of bytes +* \param rxData Pointer to byte array where read back data will be returned, that is at least numTxRxBytes in size. +* \param numTxBytes The length of txData and rxData arrays +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not read successfully +*/ + +int32_t ads8_SpiRead_v3(void *devHalCfg, const uint8_t txData[], uint8_t rxData[], + uint32_t numTxRxBytes) +{ + static const uint16_t FPGA_FIFO_SIZE = 256; + static const uint32_t WAIT_FIFO_OCCUPANCY = 1024; + static const uint32_t SPI_CONTROL_REGISTER = 0x44A00060; + static const uint32_t SPI_TXFIFO_REGISTER = 0x44A00068; + static const uint32_t SPI_RXFIFO_REGISTER = 0x44A0006C; + static const uint32_t SPI_CS_REGISTER = 0x44A00070; + static const uint32_t SPI_TXFIFO_OCY_REGISTER = 0x44A00074; + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t *halCfg = NULL; + uint32_t chipSelMask = 0xFFFFFFFF; //one hot active low active chip select + uint32_t i = 0; + uint32_t readData = 0; + uint16_t numOfChunks = 0; + uint16_t numFifoBytes = 0; + uint16_t remainder = 0; + uint16_t txByteCounter = 0; + uint16_t rxByteCounter = 0; + uint16_t k = 0; + + /* Calculate number of full FIFO transactions and remainder for last flush */ + remainder = numTxRxBytes % FPGA_FIFO_SIZE; + numOfChunks = (numTxRxBytes - remainder) / FPGA_FIFO_SIZE; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.spiActionDisable == 0) + { +# ifdef __GNUC__ + + /* This function requires access to advanced spi registers through BBIC */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_SPI) == ADI_HAL_BBIC_SPI)) + { + /* Reset Tx/Rx FIFO - Set Inhibit */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CONTROL_REGISTER, 0x1E4); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Write numOfChunks full chunks and remainder */ + numFifoBytes = FPGA_FIFO_SIZE; + for (k = 0; k < (numOfChunks + 1); k++) + { + /* If we're writing the remainder set numFifoBytes as remainder */ + if (k == numOfChunks) + { + numFifoBytes = remainder; + } + + for (i = 0; i < numFifoBytes; i++) + { + /* Write data bytes into Tx FIFO*/ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_TXFIFO_REGISTER, (uint32_t)txData[txByteCounter++]); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Enable SPI - Set Inhibit */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CONTROL_REGISTER, 0x186); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* CS low */ + chipSelMask = (0xFFFFFFFF & ~(1UL << halCfg->spiCfg.chipSelectIndex)); + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CS_REGISTER, chipSelMask); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Clear Inhibit */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CONTROL_REGISTER, 0x86); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Wait until Tx FIFO is empty*/ + for (i = 0; i < WAIT_FIFO_OCCUPANCY; i++) + { + /* Read Tx FIFO Occupancy */ + halError = ads8_BbicRegisterRead(devHalCfg, SPI_TXFIFO_OCY_REGISTER, &readData); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + if (readData == 0) + { + break; + } + + if (i == (WAIT_FIFO_OCCUPANCY - 1)) + { + /* Timeout */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + for (i = 0; i < numFifoBytes; i++) + { + /* Read data bytes from Rx FIFO*/ + uint32_t dataTmp = 0; + halError = ads8_BbicRegisterRead(devHalCfg, SPI_RXFIFO_REGISTER, &dataTmp); + rxData[rxByteCounter++] = dataTmp & 0xFF; + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Reset Tx/Rx FIFO - Set Inhibit */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CONTROL_REGISTER, 0x1E6); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* CS High */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CS_REGISTER, 0xFFFFFFFF); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + + } + + /* Disable SPI - Set Inhibit */ + halError = ads8_BbicRegisterWrite(devHalCfg, SPI_CONTROL_REGISTER, 0x1E4); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + else + { + /* Invalid file descriptor */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + +# endif /* __GNUC__ */ + } + + return halError; +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_spi.h b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_spi.h new file mode 100644 index 0000000..7197807 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_spi.h @@ -0,0 +1,38 @@ +/** + * \file ads8_spi.h + * Analog Devices ADS8 Platform + microzed hardware abstraction layer + * + * Copyright 2017 Analog Devices Inc. + * + * Support for linux layer SPI functions + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9010 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ +#ifndef __ADS8_SPI_H__ +#define __ADS8_SPI_H__ + +#include +#include "adi_platform_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t ads8_SpiOpen(void *devHalCfg); +int32_t ads8_SpiClose(void *devHalCfg); +int32_t ads8_SpiInit(void *devHalCfg); +int32_t ads8_SpiWrite(void *devHalCfg, const uint8_t txData[], uint32_t numTxBytes); +int32_t ads8_SpiWrite_v2(void *devHalCfg, const uint8_t txData[], uint32_t numTxBytes); +int32_t ads8_SpiWrite_v3(void *devHalCfg, const uint8_t txData[], uint32_t numTxBytes); +int32_t ads8_SpiRead(void *devHalCfg, const uint8_t txData[], uint8_t rxData[], uint32_t numTxRxBytes); +int32_t ads8_SpiRead_v2(void *devHalCfg, const uint8_t txData[], uint8_t rxData[], uint32_t numTxRxBytes); +int32_t ads8_SpiRead_v3(void *devHalCfg, const uint8_t txData[], uint8_t rxData[], uint32_t numTxRxBytes); + +#ifdef __cplusplus +} +#endif +#endif /* __ADS8_SPI_H__ */ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_timer.c b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_timer.c new file mode 100644 index 0000000..7a7a89a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_timer.c @@ -0,0 +1,147 @@ +/** + * \file ads8_timer.c + * Analog Devices ADS8 Platform + microzed hardware abstraction layer + * + * Copyright 2017 Analog Devices Inc. + * + * Support for linux layer timer functions + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9010 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include +#include +#include "ads8_timer.h" + +/** +* \brief Function to open/allocate any necessary resources for the timer wait +* functions below. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads8_TimerOpen(void *devHalCfg) +{ + (void)(devHalCfg); + /* ADI ADS8 platform does not require any timer open /close */ + return (int32_t)ADI_HAL_OK; +} + +/** +* \brief Function to close any necessary resources for the timer wait +* functions below. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads8_TimerClose(void *devHalCfg) +{ + (void)(devHalCfg); + /* ADI ADS8 platform does not require any timer open /close */ + return (int32_t)ADI_HAL_OK; +} + +/** +* \brief Function to initialize any necessary resources for the timer wait +* functions below. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads8_TimerInit(void *devHalCfg) +{ + (void)(devHalCfg); + /* ADI ADS8 platform does not require any timer init */ + return (int32_t)ADI_HAL_OK; +} + +/** +* \brief Provides a blocking delay of the current thread +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param time_us the time to delay in mico seconds +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +*/ +int32_t ads8_TimerWait_us(void *devHalCfg, uint32_t time_us) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + +#ifdef __GNUC__ + (void)(devHalCfg); + struct timespec t0; + struct timespec t1; + struct timespec *temp; + struct timespec *waitTime = &t0; + struct timespec *remaining = &t1; + + waitTime->tv_sec = time_us / 1000000; + waitTime->tv_nsec = (time_us % 1000000) * (1000); + + do { + halError = nanosleep(waitTime, remaining); + temp = waitTime; + waitTime = remaining; + remaining = temp; + } while ((halError == -1) && (errno == EINTR)); + +#else + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + +#endif /* __GNUC__ */ + return halError; +} + +/** +* \brief Provides a blocking delay of the current thread +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param time_ms the Time to delay in milli seconds +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +*/ +int32_t ads8_TimerWait_ms(void *devHalCfg, uint32_t time_ms) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + +#ifdef __GNUC__ + (void)(devHalCfg); + struct timespec t0; + struct timespec t1; + struct timespec *temp; + struct timespec *waitTime = &t0; + struct timespec *remaining = &t1; + + waitTime->tv_sec = time_ms / 1000; + waitTime->tv_nsec = (time_ms % 1000) * (1000000); + + do { + halError = nanosleep(waitTime, remaining); + temp = waitTime; + waitTime = remaining; + remaining = temp; + } while ((halError == -1) && (errno == EINTR)); + +#else + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } +#endif /* __GNUC__ */ + return halError; +} + diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_timer.h b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_timer.h new file mode 100644 index 0000000..8dbd5ab --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/ads8_timer.h @@ -0,0 +1,35 @@ +/** + * \file ads8_timer.h + * Analog Devices ADS8 Platform + microzed hardware abstraction layer + * + * Copyright 2017 Analog Devices Inc. + * + * Support for linux layer timer functions + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9010 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ +#ifndef __ADS8_TIMER_H__ +#define __ADS8_TIMER_H__ + +#include +#include "adi_platform_types.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t ads8_TimerOpen(void *devHalCfg); +int32_t ads8_TimerClose(void *devHalCfg); +int32_t ads8_TimerInit(void *devHalCfg); +int32_t ads8_TimerWait_ms(void *devHalCfg, uint32_t time_ms); +int32_t ads8_TimerWait_us(void *devHalCfg, uint32_t time_us); + +#ifdef __cplusplus +} +#endif +#endif /* __ADS8_TIMER_H__ */ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads8/makefile b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/makefile new file mode 100644 index 0000000..b61d658 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads8/makefile @@ -0,0 +1,20 @@ +LIB_ADI_ADS8PLATFORM = libadi_ads8platform.a +#CC = aarch64-linux-gnu-gcc +ARFLAGS = -rv +CFLAGS = -Wall -Werror -I. -I../ +EXT = c + +SRC = $(wildcard *.$(EXT)) +OBJS = $(SRC:.$(EXT)=.o) + +all: $(SRC) $(LIB_ADI_ADS8PLATFORM) + +.$(EXT).o: + $(CC) $(CFLAGS) -o $@ -c $< + +$(LIB_ADI_ADS8PLATFORM): $(OBJS) + ar $(ARFLAGS) $(LIB_ADI_ADS8PLATFORM) $(OBJS) + +clean: + rm -rf *.o + rm -rf *.a \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_bbic_control.c b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_bbic_control.c new file mode 100644 index 0000000..c225230 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_bbic_control.c @@ -0,0 +1,514 @@ +/** +* \file ads9_bbic_control.c +* \brief Contains ADI Transceiver Hardware Abstraction functions for ADS9 interface to FPGA (BBIC) control registers. +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include +#include +#include + +#ifdef __GNUC__ +#include +#include +#endif + +#include +#include "ads9_bbic_control.h" + +/********************/ +/* Public functions */ +/********************/ + +/** +* \brief Function to open any necessary resources for the BBIC + interface functions in this file. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_NULL_PTR If devHalCfg pointer is NULL +* \retval ADI_HAL_BBICCTRL_FAIL If critical error trying to open resources +*/ +int32_t ads9_BbicOpen(void* devHalCfg) +{ + adi_hal_Cfg_t* halCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS9 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + +#ifdef __GNUC__ + /* Open UIO driver to FPGA register interface */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_CORE) > 0) && halCfg->bbicCfg.coreRegsCfg.fd <= 0) + { + halCfg->bbicCfg.coreRegsCfg.fd = open(halCfg->bbicCfg.coreRegsCfg.drvName, + O_RDWR); + + if (halCfg->bbicCfg.coreRegsCfg.fd < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + /* offset must be page aligned */ + halCfg->bbicCfg.coreRegsCfg.mappedMemoryPtr = (uintptr_t)mmap(NULL, + halCfg->bbicCfg.coreRegsCfg.mapSize, + PROT_READ | PROT_WRITE, + MAP_SHARED, + halCfg->bbicCfg.coreRegsCfg.fd, + 0); + + if ((void *)halCfg->bbicCfg.coreRegsCfg.mappedMemoryPtr == MAP_FAILED) + { + perror("Error mapping the file for fpga core registers."); + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + } + + /* Open UIO driver to FPGA Data capture memory RAM interface */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_RAM) > 0) && halCfg->bbicCfg.ramCfg.fd <= 0) + { + halCfg->bbicCfg.ramCfg.fd = open(halCfg->bbicCfg.ramCfg.drvName, + O_RDWR); + + if (halCfg->bbicCfg.ramCfg.fd < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + /* offset must be page aligned */ + halCfg->bbicCfg.ramCfg.mappedMemoryPtr = (uintptr_t)mmap(NULL, + halCfg->bbicCfg.ramCfg.mapSize, + PROT_READ | PROT_WRITE, + MAP_SHARED, + halCfg->bbicCfg.ramCfg.fd, + 0); + + if ((void *)halCfg->bbicCfg.ramCfg.mappedMemoryPtr == MAP_FAILED) + { + perror("Error mapping the file for fpga ram."); + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + } + + /* Open UIO driver to FPGA Advanced SPI settings interface */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_SPI) > 0) && halCfg->bbicCfg.spiAdvRegsCfg.fd <= 0) + { + halCfg->bbicCfg.spiAdvRegsCfg.fd = open(halCfg->bbicCfg.spiAdvRegsCfg.drvName, + O_RDWR); + + if (halCfg->bbicCfg.spiAdvRegsCfg.fd < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + /* offset must be page aligned */ + halCfg->bbicCfg.spiAdvRegsCfg.mappedMemoryPtr = (uintptr_t)mmap(NULL, + halCfg->bbicCfg.spiAdvRegsCfg.mapSize, + PROT_READ | PROT_WRITE, + MAP_SHARED, + halCfg->bbicCfg.spiAdvRegsCfg.fd, + 0); + + if ((void *)halCfg->bbicCfg.spiAdvRegsCfg.mappedMemoryPtr == MAP_FAILED) + { + perror("Error mapping the file for fpga spiAdvRegsCfg registers."); + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + } + +#endif /* __GNUC__ */ + return halError; +} + +/** +* \brief Function to close any necessary resources for the BBIC + interface functions in this file. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_NULL_PTR If devHalCfg pointer is NULL +* \retval ADI_HAL_BBICCTRL_FAIL If critical error trying to close resources +*/ +int32_t ads9_BbicClose(void* devHalCfg) +{ + adi_hal_Cfg_t* halCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS9 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + +#ifdef __GNUC__ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_CORE) > 0) && halCfg->bbicCfg.coreRegsCfg.fd != 0) + { + halError = munmap((void *)halCfg->bbicCfg.coreRegsCfg.mappedMemoryPtr, + halCfg->bbicCfg.coreRegsCfg.mapSize); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + halError = close(halCfg->bbicCfg.coreRegsCfg.fd); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + halCfg->bbicCfg.coreRegsCfg.fd = 0; + } + + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_RAM) > 0) && halCfg->bbicCfg.ramCfg.fd != 0) + { + halError = munmap((void *)halCfg->bbicCfg.ramCfg.mappedMemoryPtr, + halCfg->bbicCfg.ramCfg.mapSize); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + halError = close(halCfg->bbicCfg.ramCfg.fd); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + halCfg->bbicCfg.ramCfg.fd = 0; + } + + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_SPI) > 0) && halCfg->bbicCfg.spiAdvRegsCfg.fd != 0) + { + halError = munmap((void *)halCfg->bbicCfg.spiAdvRegsCfg.mappedMemoryPtr, + halCfg->bbicCfg.spiAdvRegsCfg.mapSize); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + halError = close(halCfg->bbicCfg.spiAdvRegsCfg.fd); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + halCfg->bbicCfg.spiAdvRegsCfg.fd = 0; + } +#endif /* __GNUC__ */ + + return halError; +} + +/** +* \brief Function to initialize any necessary resources for the BBIC + interface functions in this file. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads9_BbicInit(void* devHalCfg) +{ + (void)(devHalCfg); + /* ADI ADS9 platform does not require any BBIC register/control init */ + return (int32_t)ADI_HAL_OK; +} + +/** + * \brief Function to read a single BBIC control register + * + * \param devHalCfg Pointer to device instance specific platform settings + * \param addr 32bit address of BBIC register to read + * \param data 32bit Pointer to store return value representing the data of the register at the specified address + * + * \retval ADI_HAL_OK Function completed successfully + * \retval ADI_HAL_NULL_PTR devHalCfg pointer is NULL or data pointer is NULL + */ +int32_t ads9_BbicRegisterRead(void* devHalCfg, + uint32_t addr, + uint32_t* data) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + static const uint8_t READ_REG = 0; + + if ((devHalCfg == NULL) || (data == NULL)) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + halError = ads9_fpga_AxiReadWrite(devHalCfg, + READ_REG, + addr, + data); + + return halError; +} + +/** + * \brief Function to write a single BBIC control register + * + * \param devHalCfg Pointer to device instance specific platform settings + * \param addr 32bit address of BBIC register to write + * \param data 32bit data to write to the register at the specified address + * + * \retval ADI_HAL_OK Function completed successfully + * \retval ADI_HAL_NULL_PTR devHalCfg pointer is NULL + */ +int32_t ads9_BbicRegisterWrite(void* devHalCfg, + uint32_t addr, + uint32_t data) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + static const uint8_t WRITE_REG = 1; + + if (devHalCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + halError = ads9_fpga_AxiReadWrite(devHalCfg, + WRITE_REG, + addr, + &data); + + return halError; +} + +/** + * \brief Function to read multiple consecutive BBIC control registers starting at a specified register address. + * + * \param devHalCfg Pointer to device instance specific platform settings + * \param addr 32bit address of BBIC register to start reading from + * \param data 32bit Pointer to store return array representing the data starting at the specified register address + and ending at (addr + numDataWords -1) + * \param numDataWords Number of elements in the data array + * + * \retval ADI_HAL_OK Function completed successfully + * \retval ADI_HAL_NULL_PTR devHalCfg pointer is NULL + */ +int32_t ads9_BbicRegistersRead(void* devHalCfg, + uint32_t addr, + uint32_t data[], + uint32_t numDataWords) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + static const uint8_t READ_REG = 0; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halError = ads9_fpga_AxiBulkReadWrite(devHalCfg, + READ_REG, + addr, + data, + numDataWords); + + return halError; +} + +/** + * \brief Function to write multiple consecutive BBIC control registers starting at a specified register address. + * + * \param devHalCfg Pointer to device instance specific platform settings + * \param addr 32bit address of BBIC register to start writing to + * \param data 32bit Pointer to array representing the data to write starting at the specified register address + and ending at (addr + numDataWords -1) + * \param numDataWords Number of elements in the data array + * + * \retval ADI_HAL_OK Function completed successfully + * \retval ADI_HAL_NULL_PTR devHalCfg pointer is NULL + */ +int32_t ads9_BbicRegistersWrite(void* devHalCfg, + uint32_t addr, + uint32_t data[], + uint32_t numDataWords) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + static const uint8_t WRITE_REG = 1; + + if (devHalCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + halError = ads9_fpga_AxiBulkReadWrite(devHalCfg, + WRITE_REG, + addr, + data, + numDataWords); + + return halError; +} + +/*********************/ +/* Private functions */ +/*********************/ + +/** +* \brief Writes and reads to the BBIC (FPGA) AXI memory mapped registers. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param writeFlag (Hi) tells the function to write the data to address addr +* \Param writeFlag 1 = write, 0 = read. +* \param data the data to write to address addr. +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_GEN_SW If addr is out of valid range +* \retval ADI_HAL_BBICCTRL_FAIL If critical error during read or write operation +*/ +int32_t ads9_fpga_AxiReadWrite(void* devHalCfg, + uint8_t writeFlag, + uint32_t addr, + uint32_t* data) +{ + adi_hal_Cfg_t* halCfg = NULL; + adi_hal_fpga_AxiCfg_t* axiCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + uint32_t offsetAddr = 0; + void* ptr = NULL; + + if (devHalCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if ((addr >= ADS9_FPGA_UIO2_START_ADDRESS) && + (addr <= ADS9_FPGA_UIO2_STOP_ADDRESS)) + { + offsetAddr = addr - ADS9_FPGA_UIO2_START_ADDRESS; + axiCfg = &halCfg->bbicCfg.spiAdvRegsCfg; + } + else if ((addr >= ADS9_FPGA_UIO0_START_ADDRESS) && + (addr <= ADS9_FPGA_UIO0_STOP_ADDRESS)) + { + offsetAddr = addr - ADS9_FPGA_UIO0_START_ADDRESS; + axiCfg = &halCfg->bbicCfg.coreRegsCfg; + } + else + { + /* The offset parameter is the actual fpga memory address. Range check to make sure it's valid */ + halError = (int32_t)ADI_HAL_GEN_SW; + return halError; + } + +#ifdef __GNUC__ + + if (axiCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + ptr = (void *)axiCfg->mappedMemoryPtr; + + if (ptr == MAP_FAILED || ptr == NULL) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + if (writeFlag) + { + *((uint32_t *)((uintptr_t)ptr + offsetAddr)) = *data; + } + else + { + *data = *((uint32_t*)((uintptr_t)ptr + offsetAddr)); + } + +#endif /* __GNUC__ */ + + return halError; +} + +/** +* \brief Writes and reads to the BBIC (FPGA) AXI memory mapped registers. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \Param writeFlag 1 = write, 0 = read. +* \param addr the address to write the data to. +* \param data the data to write to address addr. +* \param numData number of data words (unit32_t). +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_BBICCTRL_FAIL If critcal error during read or write transaction +*/ +int32_t ads9_fpga_AxiBulkReadWrite(void* devHalCfg, + uint8_t writeFlag, + uint32_t addr, + uint32_t data[], + const uint32_t numData) +{ + adi_hal_Cfg_t* halCfg = NULL; + adi_hal_fpga_AxiCfg_t* ramCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + /* uint32_t offsetAddr = 0; */ + void* ptr = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + ramCfg = &halCfg->bbicCfg.ramCfg; + + if (ramCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + if (addr + numData > ramCfg->mapSize) + { + halError = (int32_t)ADI_HAL_BBICCTRL_FAIL; + return halError; + } + +#ifdef __GNUC__ + + ptr = (void *)ramCfg->mappedMemoryPtr; + + if (ptr == MAP_FAILED || ptr == NULL) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + if (writeFlag) + { + memcpy((void *)((uintptr_t)ptr + addr), + data, + numData * sizeof(uint32_t)); + } + else + { + memcpy(data, + (void *)((uintptr_t)ptr + addr), + numData * sizeof(uint32_t)); + } + +#endif /* __GNUC__ */ + + return halError; +} diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_bbic_control.h b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_bbic_control.h new file mode 100644 index 0000000..515c7d6 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_bbic_control.h @@ -0,0 +1,69 @@ +/** +* \file ads9_bbic_control.h +* \brief Contains ADI Transceiver Hardware Abstraction functions for ADS9 interface to FPGA (BBIC) control registers. +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef __ADS9_BBIC_CONTROL_H__ +#define __ADS9_BBIC_CONTROL_H__ + +#include +#include "adi_platform_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADS9_FPGA_UIO0_START_ADDRESS 0x40000000 +#define ADS9_FPGA_UIO0_STOP_ADDRESS 0x5FFFFFFF +#define ADS9_FPGA_UIO2_START_ADDRESS 0x44A00000 +#define ADS9_FPGA_UIO2_STOP_ADDRESS 0x44A00FFF + +int32_t ads9_BbicOpen(void* devHalCfg); + +int32_t ads9_BbicClose(void* devHalCfg); + +int32_t ads9_BbicInit(void* devHalCfg); + +int32_t ads9_BbicRegisterRead(void* devHalCfg, + uint32_t addr, + uint32_t* data); + +int32_t ads9_BbicRegisterWrite(void* devHalCfg, + uint32_t addr, + uint32_t data); + +int32_t ads9_BbicRegistersRead(void* devHalCfg, + uint32_t addr, + uint32_t data[], + uint32_t numDataWords); + +int32_t ads9_BbicRegistersWrite(void* devHalCfg, + uint32_t addr, + uint32_t data[], + uint32_t numDataWords); + +/* Local helper functions */ +/* TODO: remove these functions */ +int32_t ads9_fpga_AxiReadWrite(void* devHalCfg, + uint8_t writeFlag, + uint32_t addr, + uint32_t* data); + +int32_t ads9_fpga_AxiBulkReadWrite(void* devHalCfg, + uint8_t writeFlag, + uint32_t addr, + uint32_t data[], + const uint32_t numData); + +#ifdef __cplusplus +} +#endif +#endif /*__ADS9_BBIC_CONTROL_H__*/ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_i2c.c b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_i2c.c new file mode 100644 index 0000000..ef845a8 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_i2c.c @@ -0,0 +1,266 @@ +/** + * \file ads9_i2c.c + * Analog Devices ADS9 Platform + microzed hardware abstraction layer + * + * Copyright 2019 Analog Devices Inc. + * + * Support for linux layer I2C functions + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifdef __GNUC__ +#include +#endif /* __GNUC__ */ + +#include +#include +#include "ads9_i2c.h" + +/** +* \brief Function to open/allocate any necessary resources for the I2C +* functions below. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads9_I2cOpen(void* devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + adi_hal_I2cCfg_t* i2cCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS9 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + i2cCfg = &halCfg->i2cCfg; + + if (i2cCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + +#ifdef __GNUC__ + if (i2cCfg->fd <= 0) + { + i2cCfg->fd = open(i2cCfg->drvName, + O_RDWR); + + if (i2cCfg->fd < 0) + { + return (int32_t)ADI_HAL_I2C_FAIL; + } + } +#endif /* __GNUC__ */ + return halError; +} + +/** +* \brief Function to close/deallocate any necessary resources for the I2C +* functions below. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads9_I2cClose(void* devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + adi_hal_I2cCfg_t* i2cCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS9 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + i2cCfg = &halCfg->i2cCfg; + + if (i2cCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + +#ifdef __GNUC__ + if (i2cCfg->fd != 0) + { + halError = close(i2cCfg->fd); + if (halError < 0) + { + return (int32_t)ADI_HAL_I2C_FAIL; + } + + i2cCfg->fd = 0; + } +#endif /* __GNUC__ */ + + return halError; +} + +/** +* \brief Function to init any necessary resources for the I2C +* functions below. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads9_I2cInit(void* devHalCfg) +{ + (void)(devHalCfg); + return (int32_t)ADI_HAL_OK; +} + +/** +* \brief Function to write to an I2C device from the BBIC +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Byte array of data to write to the I2C device. First byte +* should be the I2C register address followed by one or more data bytes. +* \param numTxBytes Number of bytes in the txData array +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads9_I2cWrite(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + int retVal = 0; + adi_hal_Cfg_t* halCfg = NULL; + adi_hal_I2cCfg_t* i2cCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS9 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + i2cCfg = &halCfg->i2cCfg; + if (i2cCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + if ((numTxBytes > 0) && + (txData != NULL)) + { + if (i2cCfg->fd > 0) + { +#ifdef __GNUC__ + retVal = write(i2cCfg->fd, + &txData[0], + numTxBytes); + if (retVal != (int)numTxBytes) + { + perror("I2C : Failed to Write to device"); + return (int32_t)ADI_HAL_I2C_FAIL; + } +#endif + } + else + { + perror("I2C : Failed to Write to device, file descriptor invalid"); + return (int32_t)ADI_HAL_GEN_SW; + } + } + + return halError; +} + +/** +* \brief Function to read from an I2C device to the BBIC +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Byte array of data to write to the I2C device. Depending on the +* I2C device, this might just be 1 byte containing the register +* address to read +* \param numTxBytes Number of bytes in the txData array +* \param rxData Byte array to return the read back data +* \param numRxBytes Number of bytes to read back, and size of rxData array +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads9_I2cRead(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes, + uint8_t rxData[], + uint32_t numRxBytes) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + int retVal = 0; + adi_hal_Cfg_t* halCfg = NULL; + adi_hal_I2cCfg_t* i2cCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS9 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + i2cCfg = &halCfg->i2cCfg; + + if (i2cCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + if (i2cCfg->fd > 0) + { + /* Write Register address */ + if ((numTxBytes > 0) && + (txData != NULL)) + { +#ifdef __GNUC__ + retVal = write(i2cCfg->fd, + &txData[0], + numTxBytes); + if (retVal != (int)numTxBytes) + { + perror("I2C : Failed to Write to I2C device"); + return (int32_t)ADI_HAL_I2C_FAIL; + } +#endif + } + + /* Read data */ + if ((numRxBytes > 0) && + (rxData != NULL)) + { +#ifdef __GNUC__ + retVal = read(i2cCfg->fd, + &rxData[0], + numRxBytes); + if (retVal != (int)numRxBytes) + { + perror("I2C : Failed to Read from I2C device"); + return (int32_t)ADI_HAL_I2C_FAIL; + } +#endif + } + } + else + { + perror("I2C : Failed to Write to device, file descriptor invalid"); + return (int32_t)ADI_HAL_GEN_SW; + } + + return halError; +} diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_i2c.h b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_i2c.h new file mode 100644 index 0000000..3dd238b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_i2c.h @@ -0,0 +1,44 @@ +/** + * \file ads9_i2c.h + * Analog Devices ADS9 Platform + microzed hardware abstraction layer + * + * Copyright 2019 Analog Devices Inc. + * + * Support for linux layer I2C functions + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ +#ifndef __ADS9_I2C_H__ +#define __ADS9_I2C_H__ + +#include +#include "adi_platform_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t ads9_I2cOpen(void* devHalCfg); + +int32_t ads9_I2cClose(void* devHalCfg); + +int32_t ads9_I2cInit(void* devHalCfg); + +int32_t ads9_I2cWrite(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes); + +int32_t ads9_I2cRead(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes, + uint8_t rxData[], + uint32_t numRxBytes); + +#ifdef __cplusplus +} +#endif +#endif /* __ADS9_I2C_H__ */ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_init.c b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_init.c new file mode 100644 index 0000000..632c28a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_init.c @@ -0,0 +1,563 @@ +/** +* \file ads9_init.c +* \brief Contains ADI Transceiver Hardware Abstraction functions for hardware mode. +* Analog Devices maintains and provides updates to this code layer for the ADS9 platform. +* The end user should not modify this file or any code in this directory. The end user +* may provide a similar platform layer that can be used in place of this platform layer, +* that uses the same function prototypes. +*/ + +/** +* \Page Disclaimer Legal Disclaimer +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include +#include +#include +#include "ads9_init.h" +#include "ads9_spi.h" +#include "ads9_logging.h" +#include "ads9_timer.h" +#include "ads9_bbic_control.h" +#include "ads9_i2c.h" + +/** +* \brief Opens all necessary files and device drivers for a specific device +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +* \retval errors returned by other function calls. +*/ +int32_t ads9_HwOpen(void* devHalCfg) +{ + adi_hal_Cfg_t* halCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + char logMessage[ADI_HAL_MAX_LOG_LINE] = {0}; + int32_t result = 0; +#ifdef __GNUC__ + va_list empty_va_list; +#else + va_list empty_va_list = { 0 }; +#endif + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->logCfg.interfaceEnabled > 0) + { + if (halCfg->logCfg.logFileName[0] == '\0') + { + halError = ads9_LogFileOpen(devHalCfg, + "ads9_adihal.log"); + } + else + { + halError = ads9_LogFileOpen(devHalCfg, + NULL); + } + + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + result = snprintf(logMessage + strlen(logMessage), + ADI_HAL_MAX_LOG_LINE, + "ads9_LogFileOpen: device index %d\n", + halCfg->spiCfg.chipSelectIndex); + if (result < 0) + { + return (int32_t)ADI_HAL_LOGGING_FAIL; + } + + halError = ads9_LogWrite(devHalCfg, + ADI_HAL_LOG_MSG, + logMessage, + empty_va_list); + + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + } + + if (halCfg->spiCfg.interfaceEnabled > 0) + { + halError = ads9_SpiOpen(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads9_SpiInit(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + } + + if (halCfg->bbicCfg.interfaceEnabled > 0) + { + halError = ads9_BbicOpen(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads9_BbicInit(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + } + + if (halCfg->hwResetCfg.interfaceEnabled > 0) + { + /* ADS9 has nothing to open, as this interface is supported by the + * BBIC control interface */ + + /* Verify BBIC control interface was enabled */ + if (halCfg->bbicCfg.interfaceEnabled == 0) + { + halError = ADI_HAL_GEN_SW; + return halError; + } + } + + if (halCfg->i2cCfg.interfaceEnabled > 0) + { + halError = ads9_I2cOpen(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads9_I2cInit(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + } + + if (halCfg->timerCfg.interfaceEnabled > 0) + { + halError = ads9_TimerOpen(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads9_TimerInit(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + } + + /* ADS9 does not require any code to open /init timer support since using linux nanosleep function */ + + return halError; +} + +/** +* \brief Gracefully shuts down the the hardware closing any open resources +* such as log files, I2C, SPI, GPIO drivers, timer resources, etc. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +*/ +int32_t ads9_HwClose(void* devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halError = ads9_LogLevelSet(devHalCfg, + ADI_HAL_LOG_NONE); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads9_LogFileClose(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads9_SpiClose(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads9_BbicClose(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads9_I2cClose(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ads9_TimerClose(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + return halError; +} + +/** +* \brief This function control a BBIC GPIO pin that connects to the reset pin +* of each device. +* +* This function is called by each device API giving access to the Reset pin +* connected to each device. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param pinLevel The desired pin logic level 0=low, 1=high to set the GPIO pin to. +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +*/ +int32_t ads9_HwReset(void* devHalCfg, + uint8_t pinLevel) +{ + adi_hal_Cfg_t* halCfg = NULL; + adi_hal_HwResetCfg_t* hwResetCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + int32_t retVal = 0; + uint32_t readData = 0; + uint32_t writeData = 0; + uint32_t pinLevelBit = 0; + uint32_t resetPinBitPostion = 0; + static const uint32_t FPGA_RESETPIN_REGISTER = 0x43041004; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + hwResetCfg = &halCfg->hwResetCfg; + + if (hwResetCfg == NULL) + { + return ADI_HAL_NULL_PTR; + } + +#ifdef __GNUC__ + + if (hwResetCfg->interfaceEnabled > 0) + { + /* Note the pin level is inverted in the ADS9 FPGA...hence then logic inversion here */ + pinLevelBit = (pinLevel > 0) ? 0 : 1; + + /* hwResetCfg->resetPinIndex is the bit position in FPGA_RESETPIN_REGISTER + * for the reset pin of the requested device */ + switch (hwResetCfg->resetPinIndex) + { + case 1: /* ADRV9025: For ADS9 platform, FPGA register 0x43041004 bit 1 controls RESET pin */ + { + resetPinBitPostion = hwResetCfg->resetPinIndex; + break; + } + + case 2: /* AD9528: For ADS9 platform, FPGA register 0x43041004 bit 2 controls RESET pin */ + { + resetPinBitPostion = hwResetCfg->resetPinIndex; + break; + } + + default: + { + /* Invalid Hardware reset pin index for ADS9 Platform */ + return ADI_HAL_GPIO_FAIL; + } + } + + /* Perform read/modify/write to change the bit of interest in the FPGA + * register that controls the reset pins to each device */ + retVal = ads9_BbicRegisterRead(devHalCfg, + FPGA_RESETPIN_REGISTER, + &readData); + if (retVal != ADI_HAL_OK) + { + return ADI_HAL_GPIO_FAIL; + } + + writeData = readData & ~(1UL << resetPinBitPostion); + writeData |= (pinLevelBit << resetPinBitPostion); + + retVal = ads9_BbicRegisterWrite(devHalCfg, + FPGA_RESETPIN_REGISTER, + writeData); + if (retVal != ADI_HAL_OK) + { + return ADI_HAL_GPIO_FAIL; + } + } + +#endif /* __GNUC__ */ + + return halError; +} + +/** +* \brief This function is a helper function to fill out the members of the +* devHalCfg structure with driver names for this specific (ADS9) platform. +* +* This function allows keeping the platform specific knowledge of driver names +* in this layer of code. Higher layers of code can call this to fill out the +* devHalCfg structure correctly for the ADS9 platform. +* +* Each device gets a unique instance of the devHalCfg structure describing the +* device resources for that device, such as the SPI chip select, etc. +* +* \param interfaceMask A mask that represents which platform interfaces are required by a particular device (SPI, Logging, etc) +* \param spiChipSelect The chip select index describing the particular device this structure is for (0, 1, 2 valid on ADS9) +* \param logFilename The filename of the logfile for this device. +*/ +void* ads9_DevHalCfgCreate(uint32_t interfaceMask, + uint8_t spiChipSelect, + const char* logFilename) +{ + adi_hal_Cfg_t* halCfg = (adi_hal_Cfg_t*)calloc(1, + sizeof(adi_hal_Cfg_t)); + + if (halCfg == NULL) + { + return NULL; + } + + /* Disable all interfaces, and enable only if they are needed by the specific device */ + halCfg->spiCfg.interfaceEnabled = 0; + halCfg->logCfg.interfaceEnabled = 0; + halCfg->bbicCfg.interfaceEnabled = 0; + + /* If device requires SPI interface */ + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_SPI) > 0) + { + halCfg->spiCfg.interfaceEnabled = 1; + + switch (spiChipSelect) + { + case 0: + { + strncpy(halCfg->spiCfg.spidevName, + "/dev/spidev12345.0\0", + ADI_HAL_STRING_LENGTH); + halCfg->spiCfg.chipSelectIndex = spiChipSelect; + break; + } + case 1: + { + strncpy(halCfg->spiCfg.spidevName, + "/dev/spidev12345.1\0", + ADI_HAL_STRING_LENGTH); + halCfg->spiCfg.chipSelectIndex = spiChipSelect; + break; + } + case 2: + { + strncpy(halCfg->spiCfg.spidevName, + "/dev/spidev12345.2\0", + ADI_HAL_STRING_LENGTH); + halCfg->spiCfg.chipSelectIndex = spiChipSelect; + break; + } + default: + { + free(halCfg); + return NULL; + } + } + + /* Default SPI settings */ + halCfg->spiCfg.autoIncAddrUp = 1; + halCfg->spiCfg.CPHA = 0; + halCfg->spiCfg.CPOL = 0; + halCfg->spiCfg.enSpiStreaming = 0; + halCfg->spiCfg.fourWireMode = 1; + halCfg->spiCfg.spiActionDisable = 0; + halCfg->spiCfg.spiClkFreq_Hz = 25000000; + } + + /* If device requires Logging interface */ + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_LOG) > 0) + { + halCfg->logCfg.interfaceEnabled = 1; + halCfg->logCfg.logLevel = ADI_HAL_LOG_ALL; + strncpy(halCfg->logCfg.logFileName, + logFilename, + ADI_HAL_STRING_LENGTH); + /* ensure null termination */ + halCfg->logCfg.logFileName[sizeof(halCfg->logCfg.logFileName) - 1] = '\0'; + } + + /* If device requires FPGA register interface */ + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_BBICCTRL) > 0) + { + halCfg->bbicCfg.interfaceEnabled = (ADI_HAL_BBIC_CORE | ADI_HAL_BBIC_RAM | ADI_HAL_BBIC_SPI); + strncpy(halCfg->bbicCfg.coreRegsCfg.drvName, + "/dev/uio0\0", + ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.coreRegsCfg.mapSize = 0x20000000; /* 512MB */ + strncpy(halCfg->bbicCfg.ramCfg.drvName, + "/dev/uio1\0", + ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.ramCfg.mapSize = 0x40000000; /* 1GB */ + + strncpy(halCfg->bbicCfg.spiAdvRegsCfg.drvName, + "/dev/uio2\0", + ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.spiAdvRegsCfg.mapSize = 0x1000; /* 16MB */ + } + /* ADS9 HWRESET interface requires BBICCTRL interface */ + else if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_HWRESET) > 0) + { + halCfg->hwResetCfg.interfaceEnabled = 1; + halCfg->bbicCfg.interfaceEnabled = ADI_HAL_BBIC_CORE | ADI_HAL_BBIC_SPI; + + strncpy(halCfg->bbicCfg.coreRegsCfg.drvName, + "/dev/uio0\0", + ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.coreRegsCfg.mapSize = 0x3042000; /* 48MB to access hwReset TODO: include bitfields to get the correct address? */ + + strncpy(halCfg->bbicCfg.spiAdvRegsCfg.drvName, + "/dev/uio2\0", + ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.spiAdvRegsCfg.mapSize = 0x1000; /* 16MB */ + + switch (spiChipSelect) + { + case 0: + { + halCfg->hwResetCfg.resetPinIndex = 1; /* ADRV9025 reset pin bit position in FPGA register */ + break; + } + case 1: + { + halCfg->hwResetCfg.resetPinIndex = 2; /* AD9528 reset pin bit position in FPGA register */ + break; + } + case 2: + { + halCfg->hwResetCfg.resetPinIndex = 0; + /* SPI2 does not need hwReset, only access to Adv Spi. A 0 value here will not get past the hwReset range checks */ + break; + } + default: + free(halCfg); + return NULL; + } + } + + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_I2C) > 0) + { + /* TODO: Place holder for future support */ + halCfg->i2cCfg.interfaceEnabled = 0; + } + + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_TIMER) > 0) + { + halCfg->timerCfg.interfaceEnabled = 1; + /* Currently no timer config structure for ADS9 platform */ + } + halCfg->interfaceMask = interfaceMask; + return halCfg; +} + +int32_t ads9_DevHalCfgFree(void* devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + + free(devHalCfg); + + return halError; +} + +int32_t ads9_HwVerify(void *devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t *halCfg = NULL; + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + + /* interpret the interface mask */ + + /* ADI_HAL_INTERFACE_SPI */ + if ((halCfg->interfaceMask & (uint32_t)ADI_HAL_INTERFACE_SPI) > 0) /* Device requires spi interface */ + { + /* throw an error if pointer is NULL */ + if (halCfg->spiCfg.fd == 0) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + } + } + + /* ADI_HAL_INTERFACE_LOG */ + if ((halCfg->interfaceMask & (uint32_t)ADI_HAL_INTERFACE_LOG) > 0) /* Device requires logging interface */ + { + /* throw an error if pointer is NULL */ + if (halCfg->logCfg.logfd == 0) + { + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + } + } + + /* ADI_HAL_INTERFACE_BBICCTRL */ + if ((halCfg->interfaceMask & (uint32_t)ADI_HAL_INTERFACE_BBICCTRL) > 0) /* Device requires fpga register interface */ + { + /* throw an error if pointer is NULL */ + if (halCfg->bbicCfg.coreRegsCfg.fd == 0 || + halCfg->bbicCfg.ramCfg.fd == 0 || + halCfg->bbicCfg.spiAdvRegsCfg.fd == 0) + { + halError = (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + } + + /* ADI_HAL_HWRESET */ + /* Not affected by HwClose */ + + /* ADI_HAL_INTERFACE_TIMER */ + /* Not affected by HwClose */ + + /* ADI_HAL_INTERFACE_I2C */ + if ((halCfg->interfaceMask & (uint32_t)ADI_HAL_INTERFACE_I2C) > 0) /* Device requires i2c interface */ + { + /* throw an error if pointer is NULL */ + if (halCfg->i2cCfg.fd == 0) + { + halError = (int32_t)ADI_HAL_I2C_FAIL; + } + } + return halError; +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_init.h b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_init.h new file mode 100644 index 0000000..51dd94c --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_init.h @@ -0,0 +1,43 @@ +/** +* \file ads9_init.h +* \brief Contains ADI Transceiver Hardware Abstraction functions for the ADS9 Platform. +* Analog Devices maintains and provides updates to this code layer for the ADS9 platform. +* The end user should not modify this file or any code in this directory. The end user +* may provide a similar platform layer that can be used in place of this platform layer, +* that uses the same function prototypes. +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef __ADS9_INIT_H__ +#define __ADS9_INIT_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t ads9_HwOpen(void* devHalCfg); + +int32_t ads9_HwReset(void* devHalCfg, + uint8_t pinLevel); + +int32_t ads9_HwClose(void* devHalCfg); + +int32_t ads9_HwVerify(void *devHalCfg); + +void* ads9_DevHalCfgCreate(uint32_t interfaceMask, + uint8_t spiChipSelect, + const char* logFilename); + +int32_t ads9_DevHalCfgFree(void* devHalCfg); + +#ifdef __cplusplus +} +#endif +#endif /*__ADS9_INIT_H__*/ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_logging.c b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_logging.c new file mode 100644 index 0000000..542d40b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_logging.c @@ -0,0 +1,418 @@ +/* +* \file ads9_logging.c +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include +#include +#include +#include +#include +#include "ads9_logging.h" + +/** +* \brief Opens a logFile. If the file is already open it will be closed and reopened. +* +* This function opens the file for writing and saves the resulting file +* descriptor to the devHalCfg structure. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param filename The user provided name of the file to open. +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +* \retval ADI_HAL_LOGGING_FAIL If the function failed to open or write to the specified filename +*/ +int32_t ads9_LogFileOpen(void* devHalCfg, + const char* filename) +{ + (void)(filename); + int32_t halError = ADI_HAL_OK; + int32_t result = 0; + adi_hal_Cfg_t* halCfg = NULL; + FILE* logfd = NULL; + struct tm tm = {0}; + time_t t = {0}; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + logfd = (FILE*)halCfg->logCfg.logfd; + + //if logfile already open, close it + if (logfd != 0) + { + halError = ads9_LogFileClose(devHalCfg); + } + + /* open a new log file */ + logfd = fopen(halCfg->logCfg.logFileName, + "w+"); + if (logfd == NULL) + { + return (int32_t)ADI_HAL_LOGGING_FAIL; + } + + halCfg->logCfg.logfd = (uintptr_t)logfd; + + t = time(NULL); + + tm = *localtime(&t); + + result = fprintf(logfd, + "API log file \nStart date %04d-%02d-%02d %02d:%02d:%02d \nLogging level %d\n\n\n", + tm.tm_year + 1900, + tm.tm_mon + 1, + tm.tm_mday, + tm.tm_hour, + tm.tm_min, + tm.tm_sec, + halCfg->logCfg.logLevel); + if (result < 0) + { + return ADI_HAL_LOGGING_FAIL; + } + + result = fflush(logfd); + if (result < ADI_HAL_OK) + { + halError = ADI_HAL_LOGGING_FAIL; + } + + return halError; +} + +/** +* \brief Flushes the logFile buffer to the currently open log file. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +*/ +int32_t ads9_LogFileFlush(void* devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->logCfg.logfd != 0) + { + halError = fflush((FILE*)halCfg->logCfg.logfd); + } + else + { + /* File not open, can not flush, No Error */ + halError = (int32_t)ADI_HAL_OK; + } + + return halError; +} + +/** +* \brief Gracefully closes the log file(s). +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +* \retval ADI_HAL_LOGGING_FAIL Error while flushing or closing the log file. +*/ +int32_t ads9_LogFileClose(void* devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + int32_t result = 0; + adi_hal_Cfg_t* halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->logCfg.logfd != 0) + { + result = fflush((FILE*)halCfg->logCfg.logfd); + if (result < 0) + { + halError = ADI_HAL_LOGGING_FAIL; + } + + result = fclose((FILE*)halCfg->logCfg.logfd); + if (result < 0) + { + halError = ADI_HAL_LOGGING_FAIL; + } + + halCfg->logCfg.logfd = 0; + /* Log level reset was causing issues with the log files, logging was disabled */ + /* halCfg->logCfg.logLevel = 0; */ + } + else + { + /* Log file is not open, can not close the file - no error */ + halError = ADI_HAL_OK; + } + + return halError; +} + +/** +* \brief Sets the log level, allowing the end user to select the granularity of +* what events get logged. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param logLevel A mask of valid log levels to allow to be written to the log file. +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +*/ +int32_t ads9_LogLevelSet(void* devHalCfg, + int32_t logLevel) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + halCfg->logCfg.logLevel = (logLevel & (int32_t)ADI_HAL_LOG_ALL); + + return halError; +} + +/** + * \brief Gets the currently set log level: the mask of different types of log + * events that are currently enabled to be logged. + * + * \param devHalCfg Pointer to device instance specific platform settings + * \param logLevel Returns the current log level mask. + * + * \retval ADI_HAL_OK Function completed successfully, no action required + * \retval ADI_HAL_NULL_PTR The function has been called with a null pointer + */ +int32_t ads9_LogLevelGet(void* devHalCfg, + int32_t* logLevel) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + *logLevel = halCfg->logCfg.logLevel; + + return halError; +} + +/** +* \brief Writes a message to the currently open logFile specified in the +* adi_hal_LogCfg_t of the devHalCfg structure passed +* +* Uses the vfprintf functionality to allow the user to supply the format and +* the number of arguments that will be logged. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param logLevel the log level to be written into +* \param comment the string to include in the line added to the log. +* \param argp variable argument list to be printed +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +* \retval ADI_HAL_LOGGING_FAIL If the function failed to flush to write +*/ +int32_t ads9_LogWrite(void* devHalCfg, + int32_t logLevel, + const char* comment, + va_list argp) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + int32_t result = 0; + adi_hal_Cfg_t* halCfg = NULL; + time_t t = time(NULL); + struct tm tm = {0}; + FILE* logfd = NULL; + char logMessage[ADI_HAL_MAX_LOG_LINE] = {0}; + const char* logLevelChar = NULL; + logMessage[0] = 0; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if ((halCfg->logCfg.interfaceEnabled == 0) || (halCfg->logCfg.logLevel == (int32_t)ADI_HAL_LOG_NONE)) + { + /* If logging disabled, exit gracefully */ + halError = (int32_t)ADI_HAL_OK; + return halError; + } + + if (logLevel > (int32_t)ADI_HAL_LOG_ALL) + { + halError = (int32_t)ADI_HAL_LOGGGING_LEVEL_FAIL; + return halError; + } + + /* Auto Open of log file is currently disabled */ + if (halCfg->logCfg.logfd == 0) + { + /* Log file is not open */ + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + return halError; + } + else + { + logfd = (FILE *)halCfg->logCfg.logfd; + + if (halCfg->logCfg.currentLineNumber >= ADS9_LOG_MAX_NUM_LINES) + { + /* seek back to beginning of file */ + /* fseek(logfd, 2, SEEK_SET); */ + rewind(logfd); + halCfg->logCfg.currentLineNumber = 0; + } + + /* Print Log type */ + if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_MSG) && (logLevel == (int32_t)ADI_HAL_LOG_MSG)) + { + logLevelChar = "MESSAGE:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_WARN) && (logLevel == (int32_t)ADI_HAL_LOG_WARN)) + { + logLevelChar = "WARNING:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_ERR) && (logLevel == (int32_t)ADI_HAL_LOG_ERR)) + { + logLevelChar = "ERROR:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_API) && (logLevel == (int32_t)ADI_HAL_LOG_API)) + { + logLevelChar = "API_LOG:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_BF) && (logLevel == (int32_t)ADI_HAL_LOG_BF)) + { + logLevelChar = "BF_LOG:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_HAL) && (logLevel == (int32_t)ADI_HAL_LOG_HAL)) + { + logLevelChar = "ADI_HAL_LOG:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_SPI) && (logLevel == (int32_t)ADI_HAL_LOG_SPI)) + { + logLevelChar = "SPI_LOG:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_API_PRIV) && (logLevel == (int32_t)ADI_HAL_LOG_API_PRIV)) + { + logLevelChar = "API_PRIV_LOG:"; + } + else + { + /* Nothing to log - exit cleanly */ + return (int32_t)ADI_HAL_OK; + } + + tm = *localtime(&t); + /* Print timestamp */ + result = snprintf(logMessage, + ADI_HAL_MAX_LOG_LINE, + "%04d-%02d-%02d %02d:%02d:%02d: %s", + tm.tm_year + 1900, + tm.tm_mon + 1, + tm.tm_mday, + tm.tm_hour, + tm.tm_min, + tm.tm_sec, + logLevelChar); + if (result < 0) + { + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + return halError; + } + + result = vsnprintf(logMessage + strlen(logMessage), + ADI_HAL_MAX_LOG_LINE, + comment, + argp); + if (result < 0) + { + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + return halError; + } + + result = fprintf(logfd, + "%s\n", + logMessage); + if (result < 0) + { + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + return halError; + } + + result = fflush(logfd); + if (result < 0) + { + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + return halError; + } + + halCfg->logCfg.currentLineNumber += 1; + } + + return halError; +} + +/** +* \brief Disables the LogWrite functionality by returning ADI_HAL_OK +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param logLevel the log level to be written into +* \param comment the string to include in the line added to the log. +* \param argp variable argument list to be printed +* +* \retval ADI_HAL_OK Function completed successfully, no action required +*/ +int32_t ads9_LogWrite_NoAction(void* devHalCfg, + int32_t logLevel, + const char* comment, + va_list argp) +{ + (void)devHalCfg; + (void)logLevel; + (void)comment; + (void)argp; + + return ADI_HAL_OK; +} diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_logging.h b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_logging.h new file mode 100644 index 0000000..c050d25 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_logging.h @@ -0,0 +1,55 @@ +/** +* \file ads9_logging.h +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _ADS9_LOGGING_H_ +#define _ADS9_LOGGING_H_ + +#include +#include +#include "adi_platform_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* +* Only allow log file to have MAX_NUM_LINES to prevent it from growing too large +* If max lines reached, start back at line 0. +* */ +#define ADS9_LOG_MAX_NUM_LINES 250000 + +int32_t ads9_LogFileOpen(void* devHalCfg, + const char* filename); + +int32_t ads9_LogFileFlush(void* devHalCfg); + +int32_t ads9_LogFileClose(void* devHalCfg); + +int32_t ads9_LogLevelSet(void* devHalCfg, + int32_t logLevel); + +int32_t ads9_LogLevelGet(void* devHalCfg, + int32_t* logLevel); + +int32_t ads9_LogWrite(void* devHalCfg, + int32_t logLevel, + const char* comment, + va_list argp); + +int32_t ads9_LogWrite_NoAction(void* devHalCfg, + int32_t logLevel, + const char* comment, + va_list argp); + +#ifdef __cplusplus +} +#endif + +#endif /* _ADS9_LOGGING_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_spi.c b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_spi.c new file mode 100644 index 0000000..7dc641d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_spi.c @@ -0,0 +1,1122 @@ +/** + * \file ads9_spi.c + * Analog Devices ADS9 Platform + microzed hardware abstraction layer + * + * Copyright 2019 Analog Devices Inc. + * + * Support for linux layer SPI functions + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifdef __GNUC__ +#include +#include +#include +#endif /* __GNUC__ */ + +#include +#include +#include "ads9_spi.h" +#include "ads9_bbic_control.h" + +/** +* \brief Opens/allocates any necessary resources to communicate via SPI to a + particular device specified in the devHalCfg structure. +* +* This function should perform any necessary steps to open the SPI master resource +* on the BBIC to enable SPI communications to a particular SPI device. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the device driver was not opened successfully +*/ +int32_t ads9_SpiOpen(void* devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + adi_hal_SpiCfg_t* spiCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS9 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + spiCfg = &halCfg->spiCfg; + + if (spiCfg == NULL) + { + return ADI_HAL_NULL_PTR; + } + +#ifdef __GNUC__ + if (spiCfg->fd <= 0) + { + spiCfg->fd = open(spiCfg->spidevName, + O_RDWR); + + if (spiCfg->fd < 0) + { + return ADI_HAL_SPI_FAIL; + } + } +#endif /* __GNUC__ */ + return halError; +} + +/** +* \brief Closes any resources open/allocated for a specific SPI device +* +* Any information needed to close the particular SPI device should be passed in +* the devHalCfg structure. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the device driver was not closed successfully +*/ +int32_t ads9_SpiClose(void* devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS9 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.spiActionDisable == 0) + { + if (halCfg->spiCfg.fd != 0) + { +#ifdef __GNUC__ + halError = close(halCfg->spiCfg.fd); + if (halError < 0) + { + return ADI_HAL_SPI_FAIL; + } +#endif /* __GNUC__ */ + + halCfg->spiCfg.fd = 0; + } + } + return halError; +} + +/** +* \brief Initializes the SPI device driver mode, bits per word, and speed +* +* Any settings needed should be passed in the devHalCfg structure +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the SPI initialization failed +*/ +int32_t ads9_SpiInit(void* devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + uint8_t spiMode = 0; + uint32_t bitsPerWord = 0; + uint32_t speed = 0; + int32_t result = 0; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS9 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + /* Initialize SPI driver with clockrate, SPI mode, etc */ + if (halCfg->spiCfg.spiActionDisable == 0) + { + bitsPerWord = 8; + speed = halCfg->spiCfg.spiClkFreq_Hz; + + /*Get Chips SPI Driver File Descriptor*/ + if (halCfg->spiCfg.fd <= 0) + { + return ADI_HAL_SPI_FAIL; + } + + /* + * spi mode + */ + if ((halCfg->spiCfg.CPOL > 1) || (halCfg->spiCfg.CPHA > 1)) + { + /* + * Invalid SPI mode: CPOL and CPHA should be 1 or 0 + */ + return ADI_HAL_SPI_FAIL; + } + + spiMode = (halCfg->spiCfg.CPOL << 1) | halCfg->spiCfg.CPHA; + +#ifdef __GNUC__ + result = ioctl(halCfg->spiCfg.fd, + SPI_IOC_WR_MODE, + &spiMode); + if (result < 0) + { + /* + * Error settings requested SPI mode + */ + return ADI_HAL_SPI_FAIL; + } + + /* + * bits per word + */ + result = ioctl(halCfg->spiCfg.fd, + SPI_IOC_WR_BITS_PER_WORD, + &bitsPerWord); + if (result < 0) + { + /* + * Error setting the number of Bits per SPI word + */ + return ADI_HAL_SPI_FAIL; + } + + /* + * max speed hz + */ + result = ioctl(halCfg->spiCfg.fd, + SPI_IOC_WR_MAX_SPEED_HZ, + &speed); + if (result < 0) + { + /* + * Error Setting max SPI clock frequency for current chip select index. + */ + return ADI_HAL_SPI_FAIL; + } +#endif /* __GNUC__ */ + } /* If SPI hardware interface enabled */ + + return halError; +} + +/** +* \brief Write an array of 8-bit data to a SPI device +* +* The function will write numTxBytes number of bytes to the SPI device +* selected in the devHalCfg structure. +* +* \dep_begin +* \dep{adi_hal_SpiCfg_t} +* \dep{adi_hal_SpiCfg_t->fd} +* \dep_end +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array txData buffer that has numTxBytes number of bytes +* \param numTxBytes The length of txData array +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not written successfully +*/ +int32_t ads9_SpiWrite(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.spiActionDisable == 0) + { +#ifdef __GNUC__ + int32_t result = 0; + + if (halCfg->spiCfg.fd > 0) + { + result = write(halCfg->spiCfg.fd, + txData, + numTxBytes); + if (result <= 0) + { + halError = ADI_HAL_SPI_FAIL; + } + } + else + { + /* Invalid file descriptor */ + halError = ADI_HAL_SPI_FAIL; + } +#endif /* __GNUC__ */ + } + + return halError; +} + +/** +* \brief Write an array of 8-bit data to a SPI device +* +* The function will write numTxBytes number of bytes to the SPI device +* selected in the devHalCfg structure. + +* This function uses FPGA registers to manage spi transaction. It doesn't use spi device driver. +* +* \dep_begin +* \dep{adi_hal_SpiCfg_t} +* \dep{adi_hal_SpiCfg_t->fd} +* \dep_end +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array txData buffer that has numTxBytes number of bytes +* \param numTxBytes The length of txData array +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not written successfully +*/ +int32_t ads9_SpiWrite_v2(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes) +{ + static const uint16_t FPGA_FIFO_SIZE = 255; + static const uint32_t WAIT_FIFO_OCCUPANCY = 1024; + static const uint32_t SPI_CONTROL_REGISTER = 0x44A00060; + static const uint32_t SPI_TXFIFO_REGISTER = 0x44A00068; + static const uint32_t SPI_CS_REGISTER = 0x44A00070; + static const uint32_t SPI_TXFIFO_OCY_REGISTER = 0x44A00074; + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + uint32_t chipSelMask = 0xFFFFFFFF; //one hot active low active chip select + uint32_t i = 0; + uint32_t readData = 0; + uint16_t numOfChunks = 0; + uint16_t numFifoBytes = 0; + uint16_t remainder = 0; + uint16_t byteCounter = 0; + uint16_t k = 0; + + /* Calculate number of full FIFO transactions and remainder for last flush */ + remainder = numTxBytes % FPGA_FIFO_SIZE; + numOfChunks = (numTxBytes - remainder) / FPGA_FIFO_SIZE; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.spiActionDisable == 0) + { +#ifdef __GNUC__ + + /* This function requires access to advanced spi registers through BBIC */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_SPI) == ADI_HAL_BBIC_SPI)) + { + /* Reset Tx/Rx FIFO */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x64); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + chipSelMask = (0xFFFFFFFF & ~(1UL << halCfg->spiCfg.chipSelectIndex)); + + /* Write SS register */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CS_REGISTER, + chipSelMask); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + /* Write numOfChunks full chunks and remainder */ + numFifoBytes = FPGA_FIFO_SIZE; + for (k = 0; k < (numOfChunks + 1); k++) + { + /* If we're writing the remainder set numFifoBytes as remainder */ + if (k == numOfChunks) + { + numFifoBytes = remainder; + } + + for (i = 0; i < numFifoBytes; i++) + { + /* Write data bytes into Tx FIFO*/ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_TXFIFO_REGISTER, + (uint32_t)txData[byteCounter++]); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Enable SPI to start transmitting */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x06); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Wait until Tx FIFO is empty*/ + for (i = 0; i < WAIT_FIFO_OCCUPANCY; i++) + { + /* Read Tx FIFO Occupancy */ + halError = ads9_BbicRegisterRead(devHalCfg, + SPI_TXFIFO_OCY_REGISTER, + &readData); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + if (readData == 0) + { + break; + } + + if (i == (WAIT_FIFO_OCCUPANCY - 1)) + { + /* Timeout */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Reset Tx/Rx FIFO */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x64); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Write SS register */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CS_REGISTER, + 0xFFFFFFFF); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + else + { + /* Invalid file descriptor */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } +#endif /* __GNUC__ */ + } + + return halError; +} + +/** +* \brief Write an array of 8-bit data to a SPI device +* +* The function will write numTxBytes number of bytes to the SPI device +* selected in the devHalCfg structure. +* +* This function uses FPGA registers to manage spi transaction. It doesn't use spi device driver. +* It implements the spi transfer sequence provided by XILINX DS742 document It's still under test. +* +* \dep_begin +* \dep{adi_hal_SpiCfg_t} +* \dep{adi_hal_SpiCfg_t->fd} +* \dep_end +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array txData buffer that has numTxBytes number of bytes +* \param numTxBytes The length of txData array +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not written successfully +*/ +int32_t ads9_SpiWrite_v3(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes) +{ + static const uint16_t FPGA_FIFO_SIZE = 256; + static const uint32_t WAIT_FIFO_OCCUPANCY = 1024; + static const uint32_t SPI_CONTROL_REGISTER = 0x44A00060; + static const uint32_t SPI_TXFIFO_REGISTER = 0x44A00068; + static const uint32_t SPI_CS_REGISTER = 0x44A00070; + static const uint32_t SPI_TXFIFO_OCY_REGISTER = 0x44A00074; + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + uint32_t chipSelMask = 0xFFFFFFFF; //one hot active low active chip select + uint32_t i = 0; + uint32_t readData = 0; + uint16_t numOfChunks = 0; + uint16_t numFifoBytes = 0; + uint16_t remainder = 0; + uint16_t byteCounter = 0; + uint16_t k = 0; + + /* Calculate number of full FIFO transactions and remainder for last flush */ + remainder = numTxBytes % FPGA_FIFO_SIZE; + numOfChunks = (numTxBytes - remainder) / FPGA_FIFO_SIZE; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.spiActionDisable == 0) + { +# ifdef __GNUC__ + + /* This function requires access to advanced spi registers through BBIC */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_SPI) == ADI_HAL_BBIC_SPI)) + { + /* Reset Tx/Rx FIFO - Set Inhibit */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x1E4); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Write numOfChunks full chunks and remainder */ + numFifoBytes = FPGA_FIFO_SIZE; + for (k = 0; k < (numOfChunks + 1); k++) + { + /* If we're writing the remainder set numFifoBytes as remainder */ + if (k == numOfChunks) + { + numFifoBytes = remainder; + } + + for (i = 0; i < numFifoBytes; i++) + { + /* Write data bytes into Tx FIFO*/ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_TXFIFO_REGISTER, + (uint32_t)txData[byteCounter++]); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Enable SPI - Set Inhibit */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x186); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* CS low */ + chipSelMask = (0xFFFFFFFF & ~(1UL << halCfg->spiCfg.chipSelectIndex)); + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CS_REGISTER, + chipSelMask); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Clear Inhibit */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x86); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Wait until Tx FIFO is empty*/ + for (i = 0; i < WAIT_FIFO_OCCUPANCY; i++) + { + /* Read Tx FIFO Occupancy */ + halError = ads9_BbicRegisterRead(devHalCfg, + SPI_TXFIFO_OCY_REGISTER, + &readData); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + if (readData == 0) + { + break; + } + + if (i == (WAIT_FIFO_OCCUPANCY - 1)) + { + /* Timeout */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Reset Tx/Rx FIFO - Set Inhibit */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x1E6); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* CS High */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CS_REGISTER, + 0xFFFFFFFF); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Disable SPI - Set Inhibit */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x1E4); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + else + { + /* Invalid file descriptor */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + +# endif /* __GNUC__ */ + } + + return halError; +} + +/** +* \brief Read one or more bytes from the device specified by the devHalCfg structure +* +* The function will read numTxRxBytes number of bytes from the SPI device selected in +* the devHalCfg parameter and store the resulting data sent by the device in the rxData +* data buffer. +* +* For each byte in txData written to the device, a byte is read and returned by this +* function at the pointer provided by the rxData parameter. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array that has numTxRxBytes number of bytes +* \param rxData Pointer to byte array where read back data will be returned, that is at least numTxRxBytes in size. +* \param numTxBytes The length of txData and rxData arrays +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not read successfully +*/ +int32_t ads9_SpiRead(void* devHalCfg, + const uint8_t txData[], + uint8_t rxData[], + uint32_t numTxRxBytes) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + int32_t result = 0; + adi_hal_Cfg_t* halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.fd <= 0) + { + /* Invalid file descriptor */ + return ADI_HAL_SPI_FAIL; + } + + if (halCfg->spiCfg.spiActionDisable == 0) + { +#ifdef __GNUC__ + + /*Get device's SPI Driver File Descriptor*/ + struct spi_ioc_transfer tr = {0}; + + tr.tx_buf = (uintptr_t)&txData[0]; + tr.rx_buf = (uintptr_t)&rxData[0]; + tr.len = numTxRxBytes; + tr.delay_usecs = 0; + + result = ioctl(halCfg->spiCfg.fd, + SPI_IOC_MESSAGE(1), + &tr); + if (result <= 0) + { + halError = ADI_HAL_SPI_FAIL; + } +#endif /* __GNUC__ */ + } + + return halError; +} + +/** +* \brief Read one or more bytes from the device specified by the devHalCfg structure +* +* The function will read numTxRxBytes number of bytes from the SPI device selected in +* the devHalCfg parameter and store the resulting data sent by the device in the rxData +* data buffer. +* +* For each byte in txData written to the device, a byte is read and returned by this +* function at the pointer provided by the rxData parameter. +* +* This function uses FPGA registers to manage spi transaction. It doesn't use spi device driver. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array that has numTxRxBytes number of bytes +* \param rxData Pointer to byte array where read back data will be returned, that is at least numTxRxBytes in size. +* \param numTxBytes The length of txData and rxData arrays +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not read successfully +*/ +int32_t ads9_SpiRead_v2(void* devHalCfg, + const uint8_t txData[], + uint8_t rxData[], + uint32_t numTxRxBytes) +{ + static const uint16_t FPGA_FIFO_SIZE = 255; + static const uint32_t WAIT_FIFO_OCCUPANCY = 1024; + static const uint32_t SPI_CONTROL_REGISTER = 0x44A00060; + static const uint32_t SPI_TXFIFO_REGISTER = 0x44A00068; + static const uint32_t SPI_RXFIFO_REGISTER = 0x44A0006C; + static const uint32_t SPI_CS_REGISTER = 0x44A00070; + static const uint32_t SPI_TXFIFO_OCY_REGISTER = 0x44A00074; + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + uint32_t chipSelMask = 0xFFFFFFFF; //one hot active low active chip select + uint32_t i = 0; + uint32_t readData = 0; + uint16_t numOfChunks = 0; + uint16_t numFifoBytes = 0; + uint16_t remainder = 0; + uint16_t txByteCounter = 0; + uint16_t rxByteCounter = 0; + uint16_t k = 0; + + /* Calculate number of full FIFO transactions and remainder for last flush */ + remainder = numTxRxBytes % FPGA_FIFO_SIZE; + numOfChunks = (numTxRxBytes - remainder) / FPGA_FIFO_SIZE; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.spiActionDisable == 0) + { +# ifdef __GNUC__ + + /* This function requires access to advanced spi registers through BBIC */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_SPI) == ADI_HAL_BBIC_SPI)) + { + /* Reset Tx/Rx FIFO */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x64); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + chipSelMask = (0xFFFFFFFF & ~(1UL << halCfg->spiCfg.chipSelectIndex)); + + /* Write SS register */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CS_REGISTER, + chipSelMask); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Write numOfChunks full chunks and remainder */ + numFifoBytes = FPGA_FIFO_SIZE; + for (k = 0; k < (numOfChunks + 1); k++) + { + /* If we're writing the remainder set numFifoBytes as remainder */ + if (k == numOfChunks) + { + numFifoBytes = remainder; + } + + for (i = 0; i < numFifoBytes; i++) + { + /* Write data bytes into Tx FIFO*/ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_TXFIFO_REGISTER, + (uint32_t)txData[txByteCounter++]); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Enable SPI to start transmitting */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x06); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Wait until Tx FIFO is empty*/ + for (i = 0; i < WAIT_FIFO_OCCUPANCY; i++) + { + /* Read Tx FIFO Occupancy */ + halError = ads9_BbicRegisterRead(devHalCfg, + SPI_TXFIFO_OCY_REGISTER, + &readData); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + if (readData == 0) + { + break; + } + + if (i == (WAIT_FIFO_OCCUPANCY - 1)) + { + /* Timeout */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + for (i = 0; i < numFifoBytes; i++) + { + /* Read data bytes from Rx FIFO*/ + uint32_t dataTmp = 0; + halError = ads9_BbicRegisterRead(devHalCfg, + SPI_RXFIFO_REGISTER, + &dataTmp); + rxData[rxByteCounter++] = (uint8_t)(dataTmp & 0x000000FF); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x64); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Write SS register */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CS_REGISTER, + 0xFFFFFFFF); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + else + { + /* Invalid file descriptor */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + +# endif /* __GNUC__ */ + } + + return halError; +} + +/** +* \brief Read one or more bytes from the device specified by the devHalCfg structure +* +* The function will read numTxRxBytes number of bytes from the SPI device selected in +* the devHalCfg parameter and store the resulting data sent by the device in the rxData +* data buffer. +* +* For each byte in txData written to the device, a byte is read and returned by this +* function at the pointer provided by the rxData parameter. +* +* This function uses FPGA registers to manage spi transaction. It doesn't use spi device driver. +* It implements the spi transfer sequence provided by XILINX DS742 document It's still under test. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array that has numTxRxBytes number of bytes +* \param rxData Pointer to byte array where read back data will be returned, that is at least numTxRxBytes in size. +* \param numTxBytes The length of txData and rxData arrays +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not read successfully +*/ + +int32_t ads9_SpiRead_v3(void* devHalCfg, + const uint8_t txData[], + uint8_t rxData[], + uint32_t numTxRxBytes) +{ + static const uint16_t FPGA_FIFO_SIZE = 256; + static const uint32_t WAIT_FIFO_OCCUPANCY = 1024; + static const uint32_t SPI_CONTROL_REGISTER = 0x44A00060; + static const uint32_t SPI_TXFIFO_REGISTER = 0x44A00068; + static const uint32_t SPI_RXFIFO_REGISTER = 0x44A0006C; + static const uint32_t SPI_CS_REGISTER = 0x44A00070; + static const uint32_t SPI_TXFIFO_OCY_REGISTER = 0x44A00074; + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + uint32_t chipSelMask = 0xFFFFFFFF; //one hot active low active chip select + uint32_t i = 0; + uint32_t readData = 0; + uint16_t numOfChunks = 0; + uint16_t numFifoBytes = 0; + uint16_t remainder = 0; + uint16_t txByteCounter = 0; + uint16_t rxByteCounter = 0; + uint16_t k = 0; + + /* Calculate number of full FIFO transactions and remainder for last flush */ + remainder = numTxRxBytes % FPGA_FIFO_SIZE; + numOfChunks = (numTxRxBytes - remainder) / FPGA_FIFO_SIZE; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.spiActionDisable == 0) + { +# ifdef __GNUC__ + + /* This function requires access to advanced spi registers through BBIC */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_SPI) == ADI_HAL_BBIC_SPI)) + { + /* Reset Tx/Rx FIFO - Set Inhibit */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x1E4); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Write numOfChunks full chunks and remainder */ + numFifoBytes = FPGA_FIFO_SIZE; + for (k = 0; k < (numOfChunks + 1); k++) + { + /* If we're writing the remainder set numFifoBytes as remainder */ + if (k == numOfChunks) + { + numFifoBytes = remainder; + } + + for (i = 0; i < numFifoBytes; i++) + { + /* Write data bytes into Tx FIFO*/ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_TXFIFO_REGISTER, + (uint32_t)txData[txByteCounter++]); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Enable SPI - Set Inhibit */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x186); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* CS low */ + chipSelMask = (0xFFFFFFFF & ~(1UL << halCfg->spiCfg.chipSelectIndex)); + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CS_REGISTER, + chipSelMask); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Clear Inhibit */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x86); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Wait until Tx FIFO is empty*/ + for (i = 0; i < WAIT_FIFO_OCCUPANCY; i++) + { + /* Read Tx FIFO Occupancy */ + halError = ads9_BbicRegisterRead(devHalCfg, + SPI_TXFIFO_OCY_REGISTER, + &readData); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + if (readData == 0) + { + break; + } + + if (i == (WAIT_FIFO_OCCUPANCY - 1)) + { + /* Timeout */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + for (i = 0; i < numFifoBytes; i++) + { + /* Read data bytes from Rx FIFO*/ + uint32_t dataTmp = 0; + halError = ads9_BbicRegisterRead(devHalCfg, + SPI_RXFIFO_REGISTER, + &dataTmp); + rxData[rxByteCounter++] = dataTmp & 0xFF; + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Reset Tx/Rx FIFO - Set Inhibit */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x1E6); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* CS High */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CS_REGISTER, + 0xFFFFFFFF); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Disable SPI - Set Inhibit */ + halError = ads9_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x1E4); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + else + { + /* Invalid file descriptor */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + +# endif /* __GNUC__ */ + } + + return halError; +} diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_spi.h b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_spi.h new file mode 100644 index 0000000..fc2fea1 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_spi.h @@ -0,0 +1,61 @@ +/** + * \file ads9_spi.h + * Analog Devices ADS9 Platform + microzed hardware abstraction layer + * + * Copyright 2019 Analog Devices Inc. + * + * Support for linux layer SPI functions + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ +#ifndef __ADS9_SPI_H__ +#define __ADS9_SPI_H__ + +#include +#include "adi_platform_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t ads9_SpiOpen(void* devHalCfg); + +int32_t ads9_SpiClose(void* devHalCfg); + +int32_t ads9_SpiInit(void* devHalCfg); + +int32_t ads9_SpiWrite(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes); + +int32_t ads9_SpiWrite_v2(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes); + +int32_t ads9_SpiWrite_v3(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes); + +int32_t ads9_SpiRead(void* devHalCfg, + const uint8_t txData[], + uint8_t rxData[], + uint32_t numTxRxBytes); + +int32_t ads9_SpiRead_v2(void* devHalCfg, + const uint8_t txData[], + uint8_t rxData[], + uint32_t numTxRxBytes); + +int32_t ads9_SpiRead_v3(void* devHalCfg, + const uint8_t txData[], + uint8_t rxData[], + uint32_t numTxRxBytes); + +#ifdef __cplusplus +} +#endif +#endif /* __ADS9_SPI_H__ */ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_timer.c b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_timer.c new file mode 100644 index 0000000..79ea152 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_timer.c @@ -0,0 +1,154 @@ +/** + * \file ads9_timer.c + * Analog Devices ADS9 Platform + microzed hardware abstraction layer + * + * Copyright 2019 Analog Devices Inc. + * + * Support for linux layer timer functions + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include +#include +#include "ads9_timer.h" + +/** +* \brief Function to open/allocate any necessary resources for the timer wait +* functions below. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads9_TimerOpen(void* devHalCfg) +{ + (void)(devHalCfg); + /* ADI ADS9 platform does not require any timer open /close */ + return (int32_t)ADI_HAL_OK; +} + +/** +* \brief Function to close any necessary resources for the timer wait +* functions below. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads9_TimerClose(void* devHalCfg) +{ + (void)(devHalCfg); + /* ADI ADS9 platform does not require any timer open /close */ + return (int32_t)ADI_HAL_OK; +} + +/** +* \brief Function to initialize any necessary resources for the timer wait +* functions below. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ads9_TimerInit(void* devHalCfg) +{ + (void)(devHalCfg); + /* ADI ADS9 platform does not require any timer init */ + return (int32_t)ADI_HAL_OK; +} + +/** +* \brief Provides a blocking delay of the current thread +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param time_us the time to delay in mico seconds +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +*/ +int32_t ads9_TimerWait_us(void* devHalCfg, + uint32_t time_us) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + +#ifdef __GNUC__ + (void)(devHalCfg); + struct timespec t0; + struct timespec t1; + struct timespec* temp; + struct timespec* waitTime = &t0; + struct timespec* remaining = &t1; + + waitTime->tv_sec = time_us / 1000000; + waitTime->tv_nsec = (time_us % 1000000) * (1000); + + do + { + halError = nanosleep(waitTime, + remaining); + temp = waitTime; + waitTime = remaining; + remaining = temp; + } + while ((halError == -1) && (errno == EINTR)); + +#else + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + +#endif /* __GNUC__ */ + return halError; +} + +/** +* \brief Provides a blocking delay of the current thread +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param time_ms the Time to delay in milli seconds +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +*/ +int32_t ads9_TimerWait_ms(void* devHalCfg, + uint32_t time_ms) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + +#ifdef __GNUC__ + (void)(devHalCfg); + struct timespec t0; + struct timespec t1; + struct timespec* temp; + struct timespec* waitTime = &t0; + struct timespec* remaining = &t1; + + waitTime->tv_sec = time_ms / 1000; + waitTime->tv_nsec = (time_ms % 1000) * (1000000); + + do + { + halError = nanosleep(waitTime, + remaining); + temp = waitTime; + waitTime = remaining; + remaining = temp; + } + while ((halError == -1) && (errno == EINTR)); + +#else + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } +#endif /* __GNUC__ */ + return halError; +} diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_timer.h b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_timer.h new file mode 100644 index 0000000..acdcbbb --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/ads9_timer.h @@ -0,0 +1,40 @@ +/** + * \file ads9_timer.h + * Analog Devices ADS9 Platform + microzed hardware abstraction layer + * + * Copyright 2019 Analog Devices Inc. + * + * Support for linux layer timer functions + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ +#ifndef __ADS9_TIMER_H__ +#define __ADS9_TIMER_H__ + +#include +#include "adi_platform_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t ads9_TimerOpen(void* devHalCfg); + +int32_t ads9_TimerClose(void* devHalCfg); + +int32_t ads9_TimerInit(void* devHalCfg); + +int32_t ads9_TimerWait_ms(void* devHalCfg, + uint32_t time_ms); + +int32_t ads9_TimerWait_us(void* devHalCfg, + uint32_t time_us); + +#ifdef __cplusplus +} +#endif +#endif /* __ADS9_TIMER_H__ */ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ads9/makefile b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/makefile new file mode 100644 index 0000000..5f96948 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ads9/makefile @@ -0,0 +1,20 @@ +LIB_ADI_ADS9PLATFORM = libadi_ads9platform.a +#CC = aarch64-linux-gnu-gcc +ARFLAGS = -rv +CFLAGS = -Wall -Werror -I. -I../ +EXT = c + +SRC = $(wildcard *.$(EXT)) +OBJS = $(SRC:.$(EXT)=.o) + +all: $(SRC) $(LIB_ADI_ADS9PLATFORM) + +.$(EXT).o: + $(CC) $(CFLAGS) -o $@ -c $< + +$(LIB_ADI_ADS9PLATFORM): $(OBJS) + ar $(ARFLAGS) $(LIB_ADI_ADS9PLATFORM) $(OBJS) + +clean: + rm -rf *.o + rm -rf *.a \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/makefile b/driver/rfic/rf/adrv9025/c_src/platforms/makefile new file mode 100644 index 0000000..c82bf3a --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/makefile @@ -0,0 +1,39 @@ +LIB_ADI_PLATFORM = libadi_platform.a +ADI_ADS8PLATFORM_SRC = ./ads8 +ADI_ADS9PLATFORM_SRC = ./ads9 +ADI_UCP2PLATFORM_SRC = ./ucp2 +ADI_PLATFORM_UTILS_SRC = ./platform_utils + +#CC = aarch64-linux-gnu-gcc +ARFLAGS = -rv +CFLAGS = -Wall -Werror -I. -Iplatform_utils -I../../../ucp/inc +EXT = c + +SRC = ./adi_platform.$(EXT) \ + $(wildcard $(ADI_PLATFORM_UTILS_SRC)/*.$(EXT)) +OBJS = $(SRC:.$(EXT)=.o) + +all: ucp2_platform_lib \ + $(LIB_ADI_PLATFORM) + +.$(EXT).o: + $(CC) $(CFLAGS) -o $@ -c $< + +$(LIB_ADI_PLATFORM): $(OBJS) + ar $(ARFLAGS) $(LIB_ADI_PLATFORM) $(OBJS) + +ads8_platform_lib: + $(MAKE) -C $(ADI_ADS8PLATFORM_SRC) + +ads9_platform_lib: + $(MAKE) -C $(ADI_ADS9PLATFORM_SRC) + +ucp2_platform_lib: + $(MAKE) -C $(ADI_UCP2PLATFORM_SRC) + +clean: + rm -rf *.o + rm -rf *.a + $(MAKE) -C $(ADI_ADS8PLATFORM_SRC) clean + $(MAKE) -C $(ADI_ADS9PLATFORM_SRC) clean + $(MAKE) -C $(ADI_UCP2PLATFORM_SRC) clean \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_eeprom.c b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_eeprom.c new file mode 100644 index 0000000..0d5c87d --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_eeprom.c @@ -0,0 +1,929 @@ +/* + * Functions to read I2C EEPROM info based on FMC EEPROM format + */ + +#include "adi_fmc_eeprom.h" + +#include +#include +#include +#ifdef __GNUC__ +#include +#include +#include +#include +#else +#ifdef _WIN64 +#define ssize_t __int64 +#else +#define ssize_t long +#endif + +#define STDIN_FILENO 0 +#define STDOUT_FILENO 1 +#define STDERR_FILENO 2 +#define strncasecmp(x,y,z) _strnicmp(x,y,z) +#endif +#include +#include +/* #define __USE_XOPEN */ /* needed for strptime */ +#include +#include +#include +#include +#include "adi_platform_types.h" +#include "adi_fmc_fru.h" + +#define DUMP_BOARD (0x01) +#define DUMP_SUPPLY (0x02) +#define DUMP_CONNECTOR (0x04) +#define DUMP_I2C (0x08) + +static int quiet = 0; +static int verbose = 0; + +void printf_err(const char* fmt, + ...) +{ + va_list ap; + va_start(ap, + fmt); + vfprintf(stderr, + fmt, + ap); + va_end(ap); +} + +void* x_calloc(size_t nmemb, + size_t size) +{ + unsigned int* ptr; + + if ((ptr = (unsigned int *)calloc(nmemb, + size)) == NULL) + { + printf_err("ERROR: calloc could not allocate requested memory\n"); + } + + return (void *)ptr; +} + +void printf_warn(const char* fmt, + ...) +{ + va_list ap; + + if (quiet || !verbose) + { + return; + } + + va_start(ap, + fmt); + vprintf(fmt, + ap); + va_end(ap); +} + +void printf_info(const char* fmt, + ...) +{ + va_list ap; + + if (quiet) + { + return; + } + + va_start(ap, + fmt); + vprintf(fmt, + ap); + va_end(ap); +} + +/* + * Read in the file of the disk, or from the EEPROM + */ +unsigned char* read_file(const char* file_name) +{ + FILE* fp; + unsigned char* p; + size_t byteRead = 1; + + if ((fp = fopen(file_name, + "rb")) == NULL) + { + printf_err("Cannot open EEPROM file '%s'\n", + file_name); + return NULL; + } + + if ((p = (unsigned char *)x_calloc(1024, + 1)) == NULL) + { + if (fclose(fp) != 0) + { + printf_err("Cannot close file.\n"); + } + return NULL; + } + + byteRead = fread(p, + 1, + 1024, + fp); + + if ((byteRead < 256) || !feof(fp)) + { + printf("Didn't read the entire EEPROM input file %s, it's too long\n", + file_name); + } + + if (fclose(fp) != 0) + { + printf_err("Cannot close file.\n"); + } + return p; +} + +void write_FRU(struct FRU_DATA* fru, + char* file_name, + bool packed) +{ + size_t len; + unsigned char* buf = NULL; + FILE* fp; + + /* Build as ASCII output */ + buf = build_FRU_blob(fru, + &len, + packed); + + /* If it's too big, try again, with 6-bit packed */ + if (len >= 255 && !packed) + { + free(buf); + buf = build_FRU_blob(fru, + &len, + 1); + if (len >= 255) + { + free(buf); + printf_err("Not able to pack things into 255 char, no output\n"); + return; + } + } + + if (!strcmp("-", + file_name)) + { +#ifdef __GNUC__ + ssize_t tmp; + tmp = write(STDOUT_FILENO, + buf, + len); + if ((size_t)tmp != len) + printf_err("Didn't write entire file\n"); +#endif + } + else + { + if ((fp = fopen(file_name, + "wb")) == NULL) + { + printf_err("Cannot open file.\n"); + free(buf); + return; + } + + fwrite(buf, + 1, + len, + fp); + if (fclose(fp) != 0) + { + printf_err("Cannot close file.\n"); + } + } + printf_info("wrote %i bytes to %s\n", + len, + file_name); + + free(buf); +} + +static void dump_fru_field(const char* description, + size_t offset, + unsigned char* field) +{ + (void)(description); + /* does field exist, and have length? */ + if (field) + { + /*printf("%s\t: ", description);*/ + if (FIELD_LEN(field)) + { + if (TYPE_CODE(field) == FRU_STRING_ASCII || offset) + { + printf("%s", + &field[offset + 1]); /*first char is a field type byte*/ + } + else + { + printf("Non-ASCII\n"); + } + } + else + printf("Empty Field\n"); + } +} + +void dump_BOARD(struct BOARD_INFO* fru) +{ + uint32_t i, j; + /*time_t tmp = min2date(fru->mfg_date);*/ + + if (fru == NULL) + { + return; + } + + /*printf("Date of Man\t: %s", ctime(&tmp));*/ + dump_fru_field("Manufacture", + 0, + fru->manufacturer); + printf(":"); + dump_fru_field("Product Name", + 0, + fru->product_name); + printf(":"); + dump_fru_field("Serial Number", + 0, + fru->serial_number); + printf(":"); + dump_fru_field("Part Number", + 0, + fru->part_number); + /*dump_fru_field("FRU File ID", 0, fru->FRU_file_ID);*/ + printf(":"); + if (!strncasecmp((const char *)&fru->manufacturer[1], + "Analog Devices", + strlen("Analog Devices"))) + { + for (i = 0; i < CUSTOM_FIELDS; i++) + { + /* These are ADI custom fields */ + if (fru->custom[i] && (fru->custom[i][0] & 0x3F)) + { + switch (fru->custom[i][1]) + { + case 0: + /*dump_fru_field("PCB Rev ", 1, fru->custom[i]);*/ + break; + case 1: + dump_fru_field("PCB ID ", + 1, + fru->custom[i]); + break; + case 2: + /*dump_fru_field("BOM Rev ", 1, fru->custom[i]);*/ + break; + case 3: + /*dump_fru_field("Uses LVDS", 1, fru->custom[i]);*/ + break; + default: + /*dump_fru_field("Unknown ", 1, fru->custom[i]);*/ + break; + } + } + } + } + else + { + printf("Custom Fields:\n"); + for (i = 0; i < CUSTOM_FIELDS; i++) + { + if (fru->custom[i] && (fru->custom[i][0] & 0x3F)) + { + printf(" Field %i (len=%i):", + i, + fru->custom[i][0] & 0x3F); + for (j = 1; j <= (uint32_t)(fru->custom[i][0] & 0x3F); j++) + printf(" %02x", + fru->custom[i][j] & 0xFF); + printf(" |"); + for (j = 1; j <= (uint32_t)(fru->custom[i][0] & 0x3F); j++) + printf("%c", + ((fru->custom[i][j] < 32) || (fru->custom[i][j] >= 127)) ? '.' : fru->custom[i][j]); + printf("|\n"); + } + } + } +} + +/* + * DC Load and DC Output Multi-record Definitions + * Table 8 from the VITA/ANSI 57.1 Spec + */ +const char* DC_Loads[] = { + "P1 VADJ", + /* Load : 0 */ + "P1 3P3V", + /* Load : 1 */ + "P1 12P0V", + /* Load : 2 */ + "P1 VIO_B_M2C", + /* Output : 3 */ + "P1 VREF_A_M2C", + /* Output : 4 */ + "P1 VREF_B_M2C", + /* Output : 5 */ + "P2 VADJ", + /* Load : 6 */ + "P2 3P3V", + /* Load : 7 */ + "P2 12P0V", + /* Load : 8 */ + "P2 VIO_B_M2C", + /* Load : 9 */ + "P2 VREF_A_M2C", + /* Load : 10 */ + "P2 VREF_B_M2C", + /* Load : 11 */ +}; + +void dump_MULTIRECORD(struct MULTIRECORD_INFO* fru) +{ + unsigned char *p, *n, *z; + int i; + + z = (unsigned char *)x_calloc(1, + 12); + + for (i = 0; i <= NUM_SUPPLIES - 1; i++) + { + if (!fru->supplies[i]) + continue; + p = fru->supplies[i]; + n = p + 5; + switch (p[0]) + { + case 1: + printf("DC Output\n"); + printf(" Output Number: %d (%s)\n", + n[0] & 0xF, + DC_Loads[n[0] & 0xF]); + if (memcmp(&n[1], + z, + 11)) + { + printf(" Nominal volts: %d (mV)\n", + (n[1] | (n[2] << 8)) * 10); + printf(" Maximum negative deviation: %d (mV)\n", + (n[3] | (n[4] << 8)) * 10); + printf(" Maximum positive deviation: %d (mV)\n", + (n[5] | (n[6] << 8)) * 10); + printf(" Ripple and Noise pk-pk: %d (mV)\n", + n[7] | (n[8] << 8)); + printf(" Minimum current draw: %d (mA)\n", + n[9] | (n[10] << 8)); + printf(" Maximum current draw: %d (mA)\n", + n[11] | (n[12] << 8)); + } + else + printf(" All Zeros\n"); + break; + case 2: + printf("DC Load\n"); + printf(" Output number: %d (%s)\n", + n[0] & 0xF, + DC_Loads[n[0] & 0xF]); + printf(" Nominal volts: %04d (mV)\n", + (n[1] | (n[2] << 8)) * 10); + printf(" Minimum voltage: %04d (mV)\n", + (n[3] | (n[4] << 8)) * 10); + printf(" Maximum voltage: %04d (mV)\n", + (n[5] | (n[6] << 8)) * 10); + printf(" Ripple and Noise pk-pk: %04d (mV)\n", + n[7] | (n[8] << 8)); + printf(" Minimum current load: %04d (mA)\n", + n[9] | (n[10] << 8)); + printf(" Maximum current load: %04d (mA)\n", + n[11] | (n[12] << 8)); + break; + } + } + free(z); +} + +void dump_i2c(struct MULTIRECORD_INFO* fru) +{ + unsigned char *p, *n; + unsigned int shift; + + if (!fru->i2c_devices) + { + printf("No I2C information\n"); + return; + } + + p = fru->i2c_devices; + while (*p) + { + n = p; + /* skip address for now */ + while (*p < '0') + p++; + /* print name */ + while (*p >= '0') + { + printf("%c", + *p); + p++; + } + /* now print the address */ + printf("\t"); + while ((*n - 0x20) <= 0x0F) + { + printf("0x%02x|0x%02x (0b", + (*n - 0x20) << 4, + (*n - 0x20) << 3); + for (shift = 0x08; shift > 0; shift >>= 1) + printf("%s", + (((*n - 0x20) & shift) == shift) ? "1" : "0"); + printf("nnn[RW]); "); + n++; + } + printf("\n"); + } +} + +void dump_FmConnector(struct MULTIRECORD_INFO* fru) +{ + unsigned char *p, *n; + + if (!fru->connector) + { + printf("No Connector information\n"); + return; + } + + p = fru->connector; + n = p + 5; + + n += 3; + switch (n[1] >> 6) + { + case 0: + printf("Single Width Card\n"); + break; + case 1: + printf("Double Width Card\n"); + break; + default: + printf("error - not the right size\n"); + break; + } + switch ((n[1] >> 4) & 0x3) + { + case 0: + printf("P1 is LPC\n"); + break; + case 1: + printf("P1 is HPC\n"); + break; + default: + printf("P1 not legal size\n"); + break; + } + switch ((n[1] >> 2) & 0x3) + { + case 0: + printf("P2 is LPC\n"); + break; + case 1: + printf("P2 is HPC\n"); + break; + case 3: + if (n[1] >> 6 != 0) + printf("P2 is not populated\n"); + break; + default: + printf("P2 not legal size\n"); + break; + } + printf("P1 Bank A Signals needed %d\n", + n[2]); + printf("P1 Bank B Signals needed %d\n", + n[3]); + printf("P1 GBT Transceivers needed %d\n", + n[6] >> 4); + if (((n[1] >> 2) & 0x3) != 3) + { + printf("P2 Bank A Signals needed %d\n", + n[4]); + printf("P2 Bank B Signals needed %d\n", + n[5]); + printf("P2 GBT Transceivers needed %d\n", + n[6] & 0xF); + } + printf("Max JTAG Clock %d\n", + n[7]); +} + +/** +* \brief Read the FMC EEPROM on the daughtercard to identify a list of daughtercard information +* +* Print the FMC Manufacturer, Product Name, Serial number, Part number, and PCB ID in a ; separated list. +* +* \param fmcIndex Index used if the FMC carrier card has more than one daughter +* card FMC connector to specify which FMC daughtercard to read +* \param infoStr Character array that is used to return the daughtercard's product name +* \param infoStrSize Size of infoStr character array in bytes +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_GEN_SW If error reading EEPROM on daughtercard +*/ +int32_t adi_FmcEepromInfoGet(uint32_t fmcIndex, + char* infoStr, + int32_t infoStrSize) +{ + (void)(fmcIndex); + adi_hal_Err_e retVal = ADI_HAL_OK; + const char* input_file = "/sys/bus/i2c/devices/3-0050/eeprom"; + uint8_t* raw_input_data = NULL; + uint32_t i; + struct FRU_DATA* fru = NULL; + char tmp_str1[128] = {0}; + + if ((raw_input_data = read_file(input_file)) != NULL) + { + fru = parse_FRU(raw_input_data); + free(raw_input_data); + + /* The parse_FRU() will return a null pointer for fru if an error occurred during reading the EEPROM, so verify a non-NULL pointer */ + if (fru == NULL) + { + snprintf(infoStr, + infoStrSize, + "%s", + "ERROR: EEPROM not found or blank."); + retVal = ADI_HAL_GEN_SW; + } + else + { + snprintf(infoStr, + infoStrSize, + "%s%s%s%s%s%s%s%s", + "Manufacturer:", + (fru->Board_Area->manufacturer + 1), + ";Product Name:", + (fru->Board_Area->product_name + 1), + ";Serial Number:", + (fru->Board_Area->serial_number + 1), + ";Part Number:", + (fru->Board_Area->part_number + 1)); + + if (!strncasecmp((const char *)&fru->Board_Area->manufacturer[1], + "Analog Devices", + strlen("Analog Devices"))) + { + for (i = 0; i < CUSTOM_FIELDS; i++) + { + /* These are ADI custom fields */ + if (fru->Board_Area->custom[i] && (fru->Board_Area->custom[i][0] & 0x3F)) + { + switch (fru->Board_Area->custom[i][1]) + { + case 0: + //dump_fru_field("PCB Rev ", 1, fru->custom[i]); + break; + case 1: + + sprintf(tmp_str1, + "%s", + fru->Board_Area->custom[i]); + strncat(infoStr, + ";PCB ID:", + (infoStrSize - 1)); + strncat(infoStr, + &tmp_str1[2], + (infoStrSize - 1)); + break; + case 2: + sprintf(tmp_str1, + "%s", + fru->Board_Area->custom[i]); + strncat(infoStr, + ";BOM REV:", + (infoStrSize - 1)); + strncat(infoStr, + &tmp_str1[2], + (infoStrSize - 1)); + break; + case 3: + //dump_fru_field("Uses LVDS", 1, fru->custom[i]); + break; + default: + //dump_fru_field("Unknown ", 1, fru->custom[i]); + break; + } + } + } + } + + free_FRU(fru); + } /* if fru is a valid pointer */ + } /* if EEPROM file was readable, will still read even if daughter is not plugged on. */ + else + { + snprintf(infoStr, + infoStrSize, + "%s", + "ERROR: EEPROM not found or blank."); + retVal = ADI_HAL_GEN_SW; + } + + return (int32_t)retVal; +} + +/** +* \brief Read the FMC EEPROM on the daughtercard to identify the daughtercard's description/product name +* +* \param fmcIndex Index used if the FMC carrier card has more than one daughter +* card FMC connector to specify which FMC daughtercard to read +* \param descStr Character array that is used to return the daughtercard's product name +* \param descStrSize Size of descStr character array in bytes +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_GEN_SW If error reading EEPROM on daughtercard +*/ +int32_t adi_FmcEepromDescriptionGet(uint32_t fmcIndex, + char* descStr, + int32_t descStrSize) +{ + (void)(fmcIndex); + adi_hal_Err_e retVal = ADI_HAL_OK; + const char* input_file = "/sys/bus/i2c/devices/3-0050/eeprom"; + uint8_t* raw_input_data = NULL; + struct FRU_DATA* fru = NULL; + + if ((raw_input_data = read_file(input_file)) != NULL) + { + fru = parse_FRU(raw_input_data); + free(raw_input_data); + + /* The parse_FRU() will return a null pointer for fru if an error occurred during reading the EEPROM, so verify a non-NULL pointer */ + if (fru == NULL) + { + snprintf(descStr, + descStrSize, + "%s", + "ERROR: EEPROM not found or blank."); + retVal = ADI_HAL_GEN_SW; + } + else + { + snprintf(descStr, + descStrSize, + "%s", + (fru->Board_Area->product_name + 1)); + + free_FRU(fru); + } /* if fru is a valid pointer */ + } /* if EEPROM file was readable, will still read even if daughter is not plugged on. */ + else + { + snprintf(descStr, + descStrSize, + "%s", + "ERROR: EEPROM not found or blank."); + retVal = ADI_HAL_GEN_SW; + } + + return (int32_t)retVal; +} + +/** +* \brief Read the FMC EEPROM on the daughtercard to identify the daughtercard's part number +* +* \param fmcIndex Index used if the FMC carrier card has more than one daughter +* card FMC connector to specify which FMC daughtercard to read +* \param partNumStr Character array that is used to return the part number +* \param partNumStrSize Size of partNumStr character array in bytes +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_GEN_SW If error reading EEPROM on daughtercard +*/ +int32_t adi_FmcEepromPartNumGet(uint32_t fmcIndex, + char* partNumStr, + int32_t partNumStrSize) +{ + (void)(fmcIndex); + adi_hal_Err_e retVal = ADI_HAL_OK; + const char* input_file = "/sys/bus/i2c/devices/3-0050/eeprom"; + uint8_t* raw_input_data = NULL; + struct FRU_DATA* fru = NULL; + + if (input_file == NULL) + { + snprintf(partNumStr, + partNumStrSize, + "%s", + "ERROR: EEPROM not found or blank."); + retVal = ADI_HAL_GEN_SW; + } + else + { + if ((raw_input_data = read_file(input_file)) != NULL) + { + fru = parse_FRU(raw_input_data); + free(raw_input_data); + + /* The parse_FRU() will return a null pointer for fru if an error occurred during reading the EEPROM, so verify a non-NULL pointer */ + if (fru == NULL) + { + snprintf(partNumStr, + partNumStrSize, + "%s", + "ERROR: EEPROM not found or blank."); + retVal = ADI_HAL_GEN_SW; + } + else + { + snprintf(partNumStr, + partNumStrSize, + "%s", + (fru->Board_Area->part_number + 1)); + + free_FRU(fru); + } /* if fru is a valid pointer */ + } /* if EEPROM file was readable, will still read even if daughter is not plugged on. */ + else + { + snprintf(partNumStr, + partNumStrSize, + "%s", + "ERROR: EEPROM not found or blank."); + retVal = ADI_HAL_GEN_SW; + } + } + + return (int32_t)retVal; +} + +/** +* \brief Read the FMC EEPROM on the daughtercard to identify the PCB Serial Number +* +* \param fmcIndex Index used if the FMC carrier card has more than one daughter +* card FMC connector to specify which FMC daughtercard to read +* \param serialStr Character array that is used to return the PCB Serial Number +* \param serialStrSize Size of serialStr character array in bytes +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_GEN_SW If error reading EEPROM on daughtercard +*/ +int32_t adi_FmcEepromSerialNumGet(uint32_t fmcIndex, + char* serialStr, + int32_t serialStrSize) +{ + (void)(fmcIndex); + adi_hal_Err_e retVal = ADI_HAL_OK; + const char* input_file = "/sys/bus/i2c/devices/3-0050/eeprom"; + uint8_t* raw_input_data = NULL; + struct FRU_DATA* fru = NULL; + + if (input_file == NULL) + { + snprintf(serialStr, + serialStrSize, + "%s", + "ERROR: EEPROM not found or blank."); + retVal = ADI_HAL_GEN_SW; + } + else + { + if ((raw_input_data = read_file(input_file)) != NULL) + { + fru = parse_FRU(raw_input_data); + free(raw_input_data); + + /* The parse_FRU() will return a null pointer for fru if an error occurred during reading the EEPROM, so verify a non-NULL pointer */ + if (fru == NULL) + { + snprintf(serialStr, + serialStrSize, + "%s", + "ERROR: EEPROM not found or blank."); + retVal = ADI_HAL_GEN_SW; + } + else + { + snprintf(serialStr, + serialStrSize, + "%s", + (fru->Board_Area->serial_number + 1)); + + free_FRU(fru); + } /* if fru is a valid pointer */ + } /* if EEPROM file was readable, will still read even if daughter is not plugged on. */ + else + { + snprintf(serialStr, + serialStrSize, + "%s", + "ERROR: EEPROM not found or blank."); + retVal = ADI_HAL_GEN_SW; + } + } + return (int32_t)retVal; +} + +/** +* \brief Read the FMC EEPROM on the daughtercard to identify the PCB name +* +* \param fmcIndex Index used if the FMC carrier card has more than one daughter +* card FMC connector to specify which FMC daughtercard to read +* \param pcbIdStr Character array that is used to return the PCB name +* \param pcbIdStrSize Size of pcbIdStr character array in bytes +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_GEN_SW If error reading EEPROM on daughtercard +*/ +int32_t adi_FmcEepromNameGet(uint32_t fmcIndex, + char* pcbIdStr, + int32_t pcbIdStrSize) +{ + (void)(fmcIndex); + adi_hal_Err_e retVal = ADI_HAL_OK; + const char* input_file = "/sys/bus/i2c/devices/3-0050/eeprom"; + int i = 0; + unsigned char* raw_input_data = NULL; + struct FRU_DATA* fru = NULL; + + if (input_file == NULL) + { + snprintf(pcbIdStr, + pcbIdStrSize, + "%s", + "ERROR: EEPROM not found or blank."); + retVal = ADI_HAL_GEN_SW; + } + else + { + if ((raw_input_data = read_file(input_file)) != NULL) + { + fru = parse_FRU(raw_input_data); + free(raw_input_data); + + if (fru == NULL) + { + snprintf(pcbIdStr, + pcbIdStrSize, + "%s", + "ERROR: EEPROM not found or blank."); + retVal = ADI_HAL_GEN_SW; + } + else + { + if (!strncasecmp((const char *)&fru->Board_Area->manufacturer[1], + "Analog Devices", + strlen("Analog Devices"))) + { + for (i = 0; i < CUSTOM_FIELDS; i++) + { + /* These are ADI custom fields */ + if (fru->Board_Area->custom[i] && (fru->Board_Area->custom[i][0] & 0x3F)) + { + switch (fru->Board_Area->custom[i][1]) + { + case 1: + snprintf(pcbIdStr, + pcbIdStrSize, + "%s", + (fru->Board_Area->custom[i] + 2)); + break; + + default: + break; + } + } + } + } + + free_FRU(fru); + } + } + else + { + snprintf(pcbIdStr, + pcbIdStrSize, + "%s", + "ERROR: EEPROM not found or blank."); + retVal = ADI_HAL_GEN_SW; + } + } + + return (int32_t)retVal; +} diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_eeprom.h b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_eeprom.h new file mode 100644 index 0000000..6894131 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_eeprom.h @@ -0,0 +1,36 @@ +#ifndef _ADI_FMC_EEPROM_H__ +#define _ADI_FMC_EEPROM_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +unsigned char* read_file(const char* file_name); + +int32_t adi_FmcEepromInfoGet(uint32_t fmcIndex, + char* infoStr, + int32_t infoStrSize); + +int32_t adi_FmcEepromDescriptionGet(uint32_t fmcIndex, + char* descStr, + int32_t descStrSize); + +int32_t adi_FmcEepromPartNumGet(uint32_t fmcIndex, + char* partNumStr, + int32_t partNumStrSize); + +int32_t adi_FmcEepromSerialNumGet(uint32_t fmcIndex, + char* serialStr, + int32_t serialStrSize); + +int32_t adi_FmcEepromNameGet(uint32_t fmcIndex, + char* pcbIdStr, + int32_t pcbIdStrSize); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_eeprom.o b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_eeprom.o new file mode 100644 index 0000000..266f1e3 Binary files /dev/null and b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_eeprom.o differ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_fru.c b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_fru.c new file mode 100644 index 0000000..a81948b --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_fru.c @@ -0,0 +1,1063 @@ +/* + * adi_fmc_fru.c + * Copyright (C) 2012 Analog Devices + * Author : Robin Getz + * + * This file is maintained as part of: + * https://github.com/analogdevicesinc/fru_tools + * but is released under this license, so you can use it without having + * your software fall under the GPL. If you make improvements to this, + * although you are not required, it would be nice if you sent me a patch. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#include +#include +#include +#include + +#ifdef __GNUC__ +#include +#include +#else +typedef int ssize_t; +static __inline unsigned int +__bswap_32(unsigned int __bsx) +{ + return ((((__bsx) & 0xff000000) >> 24) | (((__bsx) & 0x00ff0000) >> 8) | + (((__bsx) & 0x0000ff00) << 8) | (((__bsx) & 0x000000ff) << 24)); +} +#define strncasecmp(x,y,z) _strnicmp(x,y,z) +#endif +#include +#include +#include +#include +#include +#include + +#include "adi_fmc_fru.h" + +/* + * This code is based from: + * Platform Management FRU Information + * Storage Definition + * Document Revision 1.1, September 27, 1999 + * Available at zero cost at: + * http://download.intel.com/design/servers/ipmi/FRU1011.pdf + * + * ANSI/VITA 57.1 + * FPGA Mezzanine Card (FMC) Standard + * Approved July 2008 (Revised February 2010) + * http://www.vita.com/fmc.html + * Available for a small fee + * https://vita.com/secure/online-store.html + * used with permission + * Most info is in section 5.5.1: IPMI Support + */ + +#if CHAR_BIT != 8 +#error "unsupported char size" +#endif + +/* + * FRU information uses a zero checksum everywhere. + * The modulo 256 sum of the preceding bytes (starting with the first byte + * of the header) plus the checksum byte equals zero. + * Platform Management FRU Information Storage Definition : section 16.2.[56] + */ +unsigned char calc_zero_checksum(unsigned char* data, + size_t len) +{ + size_t i; + unsigned char tmp = 0; + + for (i = 0; i <= len; i++) + tmp += data[i]; + + return tmp; +} + +/* + * FRU Board Area Mfg. Date / Time is the + * number of _minutes_ from 0:00 hrs 01Jan1996 + * Max is 0xFFFFFF (3 bytes worth) or + * 16777215 minutes; or + * 279620 hours, 15 minutes; or + * 11650 days, 20 hours, 15 minutes; or + * 31 years, 328 days, 7 hours, 56 minutes (assuming 525949 minutes in a year); or + * up to : Wed Nov 24 07:56 2027 + * See: + * section 11, Platform Management FRU Information Storage Definition + */ +time_t min2date(unsigned int mins) +{ + struct tm tm; + time_t tmp; + + /* Set up 01-Jan-1996 , and add the number of minutes to it */ + memset(&tm, + 0, + sizeof(struct tm)); + tm.tm_year = 96; + tm.tm_mday = 1; + tm.tm_min += mins; + tmp = mktime(&tm); + return tmp; +} + +#ifdef DEBUG +/* + * Used for debugging + */ +static void dump_str(unsigned char* p, + unsigned int size, + unsigned int space) +{ + size_t i, j = 0, k, m, shift; + unsigned char* t; + unsigned char mthis = 0; + unsigned char last = 0; + + t = p; + k = 8 - space; + for (i = 0; i < size; i++) + { + m = 0; + printf("%02zi: %02x : ", + i, + *t); + last = mthis; + mthis = *t; + for (shift = 0x80; shift > 0; shift >>= 1) + { + printf("%s", + ((*t & shift) == shift) ? "1" : "0"); + j++, m++; + if (k == m) + { + printf(" "); + k = 8 - space + m; + if (k >= 8) + k -= space; + m = space + 100; + } + } + if (space == 8) + { + if (*t) + printf(" (%c) %02x", + *t, + *t - 0x20); + else + printf(" (term) NULL"); + } + if (space == 6) + { + unsigned char x = 0, y = 0; + + if (k == 2) + { + y = (mthis >> 2) & 0x3F; + x = (last >> 4) | ((mthis & 0x3) << 4); + } + else if (k == 4) + { + x = mthis & 0x3F; + } + else if (k == 6) + { + x = (last >> 6) | ((mthis & 0xF) << 2); + } + + if (k == 4 || k == 6) + printf(" (%02x) %02x '%c'", + x, + x + 0x20, + x + 0x20); + if (k == 2) + printf(" (%02x) %02x '%c' | (%02x) %02x '%c'", + x, + x + 0x20, + x + 0x20, + y, + y + 0x20, + y + 0x20); + } + ++t; + printf("\n"); + } +} +#else +static void dump_str(unsigned char * UNUSED(p), unsigned int UNUSED(size), unsigned int UNUSED(space)) +{ + return; +} +#endif +/* + * 6-bit ASCII Packing + * Platform Management FRU Information Storage Definition: Section 13.[23] + */ +int ascii2six(unsigned char** dest, + unsigned char* src, + size_t size) +{ + size_t i = 0; + ssize_t j; + unsigned int k, m = 0; + unsigned char *p, *d, *e; + + if (!src || !size) + return 0; + + e = d = (unsigned char *)x_calloc(1, + size); + + p = src; + /* + * 6-bit requires uppercase chars, between 0 and 0x3f + */ + while (*p != '\0' && i <= size) + { + j = (ssize_t)toupper(*p) - 0x20; + if (j < 0 || j >= 0x40) + { + printf_warn("%s : trying to convert a string '%s'\n" + "\t\twhich includes char '%c (0x%x)', which can't be converted\n", + __func__, + src, + *p, + *p); + free(e); + return -1; + } + *d = (unsigned char)j; + ++p, ++d, i++; + } + /* dump_str(d, size, 4); */ + + /* the length of dest, should be 3/4 of size, it's zero padded at the end */ + *dest = (unsigned char *)x_calloc(1, + size + 1); + p = *dest; + + for (i = 0; i <= size; i += 4) + { + k = e[i]; + m++; + if ((i + 1) < size) + { + k |= e[i + 1] << 6; + m++; + } + if ((i + 2) < size) + { + k |= e[i + 2] << 12; + m++; + } + if ((i + 3) < size) + { + k |= e[i + 3] << 18; + } +#ifndef __MINGW32__ +#if __BYTE_ORDER == __BIG_ENDIAN + k = __bswap_32(k); +#endif +#endif + memcpy(p, + &k, + 3); + p += 3; + } + + /* dump_str(*dest, m, 6); */ + free(e); + + return m; +} + +/* + * * 6-bit ASCII Unpacking + * * Platform Management FRU Information Storage Definition: Section 13.[23] + */ +unsigned char* six2ascii(unsigned char* buf, + size_t size) +{ + unsigned char *p, *dest; + size_t i; + + if (!size) + return NULL; + + /*dump_str(buf, size, 6); */ + /* the length of dest, should be 4/3 of size + 1 for null termination char*/ + dest = (unsigned char *)x_calloc(1, + ((size * 4) / 3) + 2); + p = dest; + + for (i = 0; i < size; i += 3) + { + *dest = (buf[i] & 0x3F) + 0x20; + /* printf("1: %i: 0x%x (%c)\n", i, *dest, *dest); */ + dest++; + if ((i + 1) < size) + { + *dest = ((buf[i] & 0xC0) >> 6 | (buf[i + 1] & 0x0F) << 2) + 0x20; + /* printf("2: %i: 0x%x (%c)\n", i, *dest, *dest); */ + dest++; + } + if ((i + 2) < size) + { + *dest = ((buf[i + 1] & 0xF0) >> 4 | (buf[i + 2] & 0x03) << 4) + 0x20; + /* printf("3: %i: 0x%x (%c)\n", i, *dest, *dest); */ + dest++; + } + if ((i + 3) < size) + { + *dest = ((buf[i + 2] & 0xFC) >> 2) + 0x20; + /* printf("4: %i: 0x%x (%c)\n", i, *dest, *dest); */ + dest++; + } + } + /* make sure strings are null terminated */ + *dest = 0; + + /* Drop trailing spaces & null chars */ + dest--; + while ((*dest == 0 || *dest == ' ') && size) + { + *dest = 0; + dest--; + size--; + } + + return p; +} + +/* + * Extract strings from fields + * Section 13 TYPE/LENGTH BYTE FORMAT + * Platform Management FRU Information Storage Definition + */ +unsigned int parse_string(unsigned char* p, + unsigned char** str, + const char* field) +{ + unsigned int len, i, j; + + len = p[0] & 0x3F; + + if (!len) + { + *str = (unsigned char *)x_calloc(1, + 3); + *str[0] = (FRU_STRING_ASCII << 6); + return 1; + } + + switch ((p[0] >> 6) & 0x3) + { + case FRU_STRING_BINARY: + /* binary or unspecified */ + *str = (unsigned char *)x_calloc(1, + len + 2); + memcpy(*str, + p, + len + 1); + break; + case FRU_STRING_BCD: + /* BCD plus */ + printf_err("BCD - sorry\n"); + break; + case FRU_STRING_SIXBIT: + /* 6-bit ASCII, packed */ + { + unsigned char *tmp1, *tmp2; + size_t tlen; + + tmp1 = six2ascii(&p[1], + p[0] & 0x3F); + /* printf("str: %s\n", foo); */ + /* dump_str(foo, strlen(foo) + 1, 8); */ + tlen = strlen((char *)tmp1); + *str = (unsigned char *)x_calloc(1, + tlen + 2); + + tmp2 = *str; + tmp2++; + memcpy(tmp2, + tmp1, + tlen + 1); + if (tlen > 0x3F) + tlen = 0x3F; + + *str[0] = (unsigned char)((FRU_STRING_ASCII << 6) | tlen); + free(tmp1); + } + break; + case FRU_STRING_ASCII: + /* 8-bit ASCII */ + *str = (unsigned char *)x_calloc(1, + len + 2); + memcpy(*str, + p, + len + 1); + for (i = 1; i < len; i++) + { + if (p[i] < 0x20 || p[i] == 0x7F) + { + printf_warn("Field '%s' marked as ASCII, but contains non-printable " + "characters:\n", + field); + printf_warn(" Length/Type : 0x%x (length:%i; type:ASCII(%i)\n", + p[0], + p[0] & 0x3F, + FRU_STRING_ASCII); + printf_warn(" Contents : "); + for (j = 1; j < len + 1; j++) + printf_warn("0x%02x ", + p[j]); + printf_warn(" |"); + for (j = 0; j < len + 1; j++) + printf_warn("%c", + ((p[j] < 32) || (p[j] >= 127)) ? '.' : p[j]); + printf_warn("|\n"); + } + } + break; + } + return len + 1; +} + +/* + * Board Info Area Format + * Platform Management FRU Information Storage Definition: Section 11 + */ +struct BOARD_INFO* parse_board_area(unsigned char* data) +{ + struct BOARD_INFO* brdInfo; + unsigned char* p; + unsigned int len, i, j; + + brdInfo = (struct BOARD_INFO *)x_calloc(1, + sizeof(struct BOARD_INFO)); + + if (data[0] != 0x01) + { + printf_err("Board Area Format Version mismatch: 0x%02x should be 0x01\n", + data[0]); + goto err; + } + + len = (data[1] * 8) - 1; + if (calc_zero_checksum(data, + len)) + { + printf_err("Board Area Checksum failed"); + goto err; + } + + if (data[2] != 0 && data[2] != 25) + { + printf_err("Board Area is non-English - sorry: Lang code = %i\n", + data[2]); + goto err; + } + + len--; + while ((data[len] == 0x00) && (len != 0)) + len--; + if (len == 0 || data[len] != 0xC1) + { + printf_err("BOARD INFO not terminated properly, walking backwards len: " + "%i:0x%02x should be 0xC1\n", + len, + data[len]); + goto err; + } + + brdInfo->mfg_date = data[3] | (data[4] << 8) | (data[5] << 16); + + p = &data[6]; + len -= 6; + + i = parse_string(p, + &brdInfo->manufacturer, + "Manufacture"); + p += i, len -= i; + + i = parse_string(p, + &brdInfo->product_name, + "Product Name"); + p += i, len -= i; + + i = parse_string(p, + &brdInfo->serial_number, + "Serial Number"); + p += i, len -= i; + + i = parse_string(p, + &brdInfo->part_number, + "Part Number"); + p += i, len -= i; + + i = parse_string(p, + &brdInfo->FRU_file_ID, + "FRU File ID"); + p += i, len -= i; + + j = 0; + while (len != 0 && j < CUSTOM_FIELDS) + { + i = parse_string(p, + &brdInfo->custom[j], + "Custom Field"); + p += i, len -= i, j++; + } + + if (*p != 0xC1) + { + printf_err("BOARD INFO not terminated properly, " + "offset %02i(0x%02x) : %02i(0x%02x) should be 0xC1\n", + p - data, + p - data, + *p, + *p); + goto err; + } + + return brdInfo; + +err: + free(brdInfo->manufacturer); + free(brdInfo->product_name); + free(brdInfo->serial_number); + free(brdInfo->part_number); + free(brdInfo->FRU_file_ID); + for (j = 0; j < CUSTOM_FIELDS; j++) + free(brdInfo->custom[j]); + free(brdInfo); + + return NULL; +} + +/* + * Each record in this area begins with a pre-defined header as specified in the + * section 16 in the Platform Management FRU Information Storage Definition. + * This header contains a 'Type' field that identifies what information is + * contained in the record. * There are some FMC specific headers, defined + * in section 5.5.1 of the FMC specification "IPMI Support". These FMC specific + * sections have a 1 byte sub-type, and a 3 byte Unique Organization Identifier + */ +struct MULTIRECORD_INFO* parse_multiboard_area(unsigned char* data) +{ + int i = 0, tmp, type; + unsigned char* p; + struct MULTIRECORD_INFO* multi; + + multi = (struct MULTIRECORD_INFO *)x_calloc(1, + sizeof(struct MULTIRECORD_INFO)); + + p = data; + + do + { + if (i != 0) + p += 5 + p[2]; + if (p[0] >= 0x06 && p[0] <= 0xBF) + { + printf_err("MultiRecord Area %i: Invalid Record Header\n", + i); + free(multi); + return NULL; + } + if (calc_zero_checksum(p, + 4)) + { + printf_err("MultiRecord Area %i (Record Type 0x%x): " + "Header Checksum failed\n", + i, + p[0]); + free(multi); + return NULL; + } + + if (!p[2] || ((calc_zero_checksum(p + 5, + p[2] - 1) + p[3]) & 0xFF)) + { + printf_err("MultiRecord Area %i (Record Type 0x%x): " + "Record Checksum failed\n", + i, + p[0]); + free(multi); + return NULL; + } + + /* + * Record Type ID + */ + switch (p[0]) + { + case MULTIRECORD_DC_OUTPUT: + case MULTIRECORD_DC_INPUT: + tmp = p[5] & 0xF; + if ((tmp) >= NUM_SUPPLIES) + { + printf_err("Too many Supplies defined in Multirecords\n"); + free(multi); + return NULL; + } + + multi->supplies[tmp] = (unsigned char *)x_calloc(1, + p[2] + 6); + memcpy(multi->supplies[tmp], + p, + p[2] + 6); + multi->supplies[tmp][1] = multi->supplies[tmp][1] & 0x7F; + break; + case MULTIRECORD_FMC: + /* + * Use VITA's OUI: 0x0012a2 is specified in the FMC spec - Rule 5.77 + */ + if ((p[5] | p[6] << 8 | p[7] << 16) != VITA_OUI) + { + printf_err("OUI Doesn't match : is 0x%06X, " + "should be 0x%06x\n", + p[5] | p[6] << 8 | p[7] << 16, + VITA_OUI); + } + /* type field is located: Header + Manufacturer ID = 5 + 3 */ + type = p[8] >> 4; + + switch (type) + { + case MULTIRECORD_CONNECTOR: + /* see table 7 in FMC spec */ + multi->connector = (unsigned char *)x_calloc(1, + p[2] + 6); + memcpy(multi->connector, + p, + p[2] + 6); + /* This isn't the end 'til we re-assemble things */ + multi->connector[1] = multi->connector[1] & 0x7F; + break; + case MULTIRECORD_I2C: + if (p[2] <= 5) + { + printf_warn("I2C MultiRecord is too short (len:%i)\n" + " (at least 4 is needed for OUI and subtype)\n", + p[2]); + } + else + { + /* see table 9 in FMC spec */ + unsigned char* foo2; + foo2 = six2ascii(&p[9], + p[2] - 4); + + multi->i2c_devices = (unsigned char *)x_calloc(1, + strlen((char *)foo2) + 1); + strcpy((char *)multi->i2c_devices, + (char *)foo2); + free(foo2); + /* This isn't the end 'til we re-assemble things */ + multi->i2c_devices[1] = multi->i2c_devices[1] & 0x7F; + } + break; + default: + printf_err("Unknown multirecord type : %i\n", + type); + break; + } + + if (type == 1) + { + } + break; + default: + printf_err("Unknown MultiRecord Area\n"); + free(multi); + return NULL; + } + + i++; + } + while (!(p[1] & 0x80)); + + return multi; +} + +/* + * Common Header Format + * Section 8 in the Platform Management FRU Information Storage Definition + */ +struct FRU_DATA* parse_FRU(unsigned char* data) +{ + struct FRU_DATA* fru; + + fru = (struct FRU_DATA *)x_calloc(1, + sizeof(struct FRU_DATA)); + + /* Check FRU version */ + if (data[0] != 0x01) + { + printf_err("FRU Version number mismatch 0x%02x should be 0x01\n", + data[0]); + goto err; + } + + /* Check Padding */ + if (data[6] != 0x00) + { + printf_err("FRU byte 6 should be PAD, and be zero -- but it's not\n"); + goto err; + } + + /* Check header checksum */ + if (calc_zero_checksum(data, + 7)) + { + printf_err("Common Header Checksum failed\n"); + goto err; + } + + /* Parse Internal Use Area */ + if (data[1]) + { + printf_err("Internal Use Area not yet implemented - sorry\n"); + goto err; + } + + /* Parse Chassis Info Area */ + if (data[2]) + { + printf_err("Chassis Info Area not yet implemented - sorry\n"); + goto err; + } + + /* Parse Board Area */ + if (data[3]) + { + fru->Board_Area = parse_board_area(&data[data[3] * 8]); + if (!fru->Board_Area) + goto err; + } + + /* Parse Chassis Info Area */ + if (data[4]) + { + printf_err("Chassis Info Area parsing not yet implemented - sorry\n"); + goto err; + } + + /* Parse MultiRecord Area */ + if (data[5]) + fru->MultiRecord_Area = parse_multiboard_area(&data[data[5] * 8]); + + return fru; + +err: + free_FRU(fru); + return NULL; +} + +void free_FRU(struct FRU_DATA* fru) +{ + int j; + + if (fru != NULL) + { + if (fru->Board_Area != NULL) + { + free(fru->Board_Area->manufacturer); + free(fru->Board_Area->product_name); + free(fru->Board_Area->serial_number); + free(fru->Board_Area->part_number); + free(fru->Board_Area->FRU_file_ID); + + for (j = 0; j < CUSTOM_FIELDS; j++) + { + free(fru->Board_Area->custom[j]); + } + + free(fru->Board_Area); + } + + if (fru->MultiRecord_Area != NULL) + { + for (j = 0; j < NUM_SUPPLIES; j++) + { + free(fru->MultiRecord_Area->supplies[j]); + } + + free(fru->MultiRecord_Area->i2c_devices); + + free(fru->MultiRecord_Area->connector); + + free(fru->MultiRecord_Area); + } + + free(fru); + } +} + +/* + * take string, and put in into the buffer + * return the number of bytes copied + */ +static unsigned int insert_str(unsigned char* buf, + const unsigned char* str, + bool force) +{ + int tmp; + + if (TYPE_CODE(str) == FRU_STRING_ASCII) + tmp = (int)strlen((const char *)&str[1]); + else + tmp = FIELD_LEN(str); + + /* Turn ASCII into 6 bit if possible */ + if ((TYPE_CODE(str) != FRU_STRING_ASCII) || (tmp <= 0x3F && !force)) + { + /* It fits, so just leave it as ASCII/binary/whatever format it's in */ + buf[0] = (unsigned char)(tmp | (TYPE_CODE(str) << 6)); + memcpy(&buf[1], + &str[1], + tmp); + } + else + { + /* turn it into 6-bit ASCII */ + unsigned char* six = NULL; + + /* printf("six in : 0x%x : len: %2d : %s\n", (str[0] >> 6) && 0x3, str[0] & 0x3F , &str[1]); */ + /* dump_str((unsigned char*)&str[1], tmp + 1 , 8); */ + tmp = ascii2six(&six, + (unsigned char *)&str[1], + tmp); + if (tmp < 0) + { + /* Counldn't encode things */ + printf_warn("couldn't encode '%s' string\n", + &str[1]); + tmp = (int)strlen((const char *)&str[1]); + if (tmp > 0x3F) + { + printf_warn("fail : %d\n", + tmp); + printf_err("String too long to fit\n"); + } + buf[0] = (unsigned char)(tmp | (FRU_STRING_ASCII << 6)); + memcpy(&buf[1], + &str[1], + tmp); + return tmp + 1; + } + dump_str(six, + tmp, + 6); + if (tmp > 0x3F) + { + printf_warn("fail : %d\n", + tmp); + printf_err("String too long to fit\n"); + } + + buf[0] = (unsigned char)(tmp | (FRU_STRING_SIXBIT << 6)); + memcpy(&buf[1], + six, + tmp); + free(six); + } + + return (unsigned int)(tmp + 1); +} + +/* + * Takes the FRU structure, and builds the binary blob + */ +unsigned char* build_FRU_blob(struct FRU_DATA* fru, + size_t* length, + bool packed) +{ + unsigned char *p, *buf; + unsigned int st, len, tmp, last = 0, i = 0, j; + + buf = (unsigned char *)x_calloc(1, + 1024); + len = 256; + + buf[0] = 0x01; + i = 8; + if (fru->Internal_Area) + { + printf_err("Internal Use Area not yet implemented - sorry\n"); + free(buf); + return NULL; + } + + if (fru->Chassis_Info) + { + printf_err("Chassis Info not yet implemented - sorry\n"); + free(buf); + return NULL; + } + + if (fru->Board_Area) + { + len = st = i; + buf[3] = i / 8; + buf[i] = 0x1; /* Magic number */ + /* buf[i+1] = length, which needs to be determined later */ + buf[i + 2] = 25; /* English */ + buf[i + 3] = (fru->Board_Area->mfg_date) & 0xFF; + buf[i + 4] = (fru->Board_Area->mfg_date >> 8) & 0xFF; + buf[i + 5] = (fru->Board_Area->mfg_date >> 16) & 0xFF; + + i += 6; + i += insert_str(&buf[i], + fru->Board_Area->manufacturer, + packed); + i += insert_str(&buf[i], + fru->Board_Area->product_name, + packed); + i += insert_str(&buf[i], + fru->Board_Area->serial_number, + packed); + i += insert_str(&buf[i], + fru->Board_Area->part_number, + packed); + i += insert_str(&buf[i], + fru->Board_Area->FRU_file_ID, + packed); + for (j = 0; j < CUSTOM_FIELDS; j++) + { + if (fru->Board_Area->custom[j]) + { + i += insert_str(&buf[i], + fru->Board_Area->custom[j], + packed); + } + } + buf[i] = 0xC1; + i++; + i = (((i >> 3) + 1) << 3) - 1; + len = i - st; + buf[st + 1] = len / 8 + 1; + buf[i] = 256 - calc_zero_checksum(&buf[st], + len); + i++; + } + if (fru->Product_Info) + { + } + if (fru->MultiRecord_Area) + { + st = i; + buf[5] = st / 8; + for (tmp = 0; tmp < NUM_SUPPLIES; tmp++) + { + p = fru->MultiRecord_Area->supplies[tmp]; + if (!p) + continue; + memcpy(&buf[i], + p, + p[2] + 5); + last = i + 1; + i += p[2] + 5; + } + p = fru->MultiRecord_Area->connector; + if (p) + { + memcpy(&buf[i], + p, + p[2] + 5); + last = i + 1; + i += p[2] + 5; + } + p = fru->MultiRecord_Area->i2c_devices; + if (p) + { + unsigned int range = 0x00; + unsigned int oui = VITA_OUI; + unsigned char* six = NULL; + range = ascii2six(&six, p, strlen((char *)p)); + + if (six == NULL) + { + /* Error decoding ascii */ + free(buf); + return NULL; + } + + /* Type ID, Record Format version, Length, checksum, checksum */ + sprintf((char *)&buf[i], + "%c%c%c%c%c", + MULTIRECORD_FMC, + 0x02, + range + 4, + 0, + 0); + /* Store OUI */ +#ifndef __MINGW32__ +# if __BYTE_ORDER == __BIG_ENDIAN + oui = __bswap_32(oui); +#endif +#endif + memcpy(&buf[i + 5], &oui, 3); + /* Subtype & version - see Table 9 in FMC spec*/ + sprintf((char *)&buf[i + 8], "%c", (0x1 << 4) | (0)); + /* finally copy over the string */ + memcpy(&buf[i + 9], six, range); + /* Record Checksum */ + buf[i + 3] = 0x100 - calc_zero_checksum(&buf[i + 5], range + 3); + /* Header Checksum */ + buf[i + 4] = 0x100 - calc_zero_checksum(&buf[i], 4); + + last = i + 1; + i += range + 9; + + free(six); + } + if (last) + { + buf[last] = buf[last] | 0x80; + /* redo the header checksum, since we just changed the header :( */ + buf[last + 3] = 0; + buf[last + 3] = 0x100 - calc_zero_checksum(&buf[last - 1], 4); + } + } + buf[7] = 256 - calc_zero_checksum(buf, + 6); + + *length = i; + return buf; +} diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_fru.h b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_fru.h new file mode 100644 index 0000000..a70a8e0 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_fru.h @@ -0,0 +1,149 @@ +/* + * adi_fmc_fru.h + * Copyright (C) 2012 Analog Devices + * Author : Robin Getz + * + * This file is maintained as part of: + * https://github.com/analogdevicesinc/fru_tools + * but is released under this license, so you can use it without having + * your software fall under the GPL. If you make improvements to this, + * although you are not required, it would be nice if you sent me a patch. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + */ + +#ifndef _ADI_FMC_FRU_H__ +#define _ADI_FMC_FRU_H__ + +#include + +#ifndef UNUSED +# ifdef __GNUC__ +# define UNUSED(x) UNUSED_ ## x __attribute__((__unused__)) +# else +# define UNUSED(x) UNUSED_ ## x +# endif +#endif + +/* + * These structures/data are based from: + * Platform Management FRU Information + * Storage Definition + * Document Revision 1.1, September 27, 1999 + * http://download.intel.com/design/servers/ipmi/FRU1011.pdf + * + * ANSI/VITA 57.1 + * FPGA Mezzanine Card (FMC) Standard + * Approved July 2008 (Revised February 2010) + * Used with permission + */ + +#define CUSTOM_FIELDS 10 + +/* Defines from section 13 "TYPE/LENGTH BYTE FORMAT" of FRU spec) */ +#define FRU_STRING_BINARY 0 +#define FRU_STRING_BCD 1 +#define FRU_STRING_SIXBIT 2 +#define FRU_STRING_ASCII 3 + +#define TYPE_CODE(x) ((x[0] >> 6) & 0x3) +#define FIELD_LEN(x) (x[0] & 0x3F) + +struct BOARD_INFO +{ + unsigned char language_code; + unsigned int mfg_date; + unsigned char* manufacturer; + unsigned char* product_name; + unsigned char* serial_number; + unsigned char* part_number; + unsigned char* FRU_file_ID; + unsigned char* custom[CUSTOM_FIELDS]; +}; + +#define NUM_MULTI 3 +#define NUM_SUPPLIES 12 + +struct MULTIRECORD_INFO +{ + unsigned char* supplies[NUM_SUPPLIES]; + unsigned char* connector; + unsigned char* i2c_devices; +}; + +#define MULTIRECORD_I2C 1 +#define MULTIRECORD_CONNECTOR 0 + +#define MULTIRECORD_DC_OUTPUT 1 +#define MULTIRECORD_DC_INPUT 2 +/* 0xfa is the FMC-specific MultiRecords, see Rule Rule 5.77 in the FMC spec */ +#define MULTIRECORD_FMC 0xFA +/* VITA's Organizationally Unique Identifier - see rule 5.77 in the FMC spec */ +#define VITA_OUI 0x0012A2 + +typedef struct FRU_DATA +{ + char* Internal_Area; + char* Chassis_Info; + struct BOARD_INFO* Board_Area; + char* Product_Info; + struct MULTIRECORD_INFO* MultiRecord_Area; +} FRU_DATA_t; + +extern void printf_err(const char*, + ...); + +extern void printf_warn(const char*, + ...); + +extern void printf_info(const char*, + ...); + +extern struct FRU_DATA* parse_FRU(unsigned char*); + +/*extern unsigned char *read_file(const char *); */ +extern unsigned char calc_zero_checksum(unsigned char*, + size_t ); + +extern struct BOARD_INFO* parse_board_area(unsigned char*); + +extern struct MULTIRECORD_INFO* parse_multiboard_area(unsigned char*); + +extern void free_FRU(struct FRU_DATA* fru); + +extern unsigned char* build_FRU_blob(struct FRU_DATA*, + size_t* , + bool ); + +//extern time_t min2date(unsigned int mins); +extern void* x_calloc(size_t, + size_t); + +#endif /* _ADS8_FMC_FRU_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_fru.o b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_fru.o new file mode 100644 index 0000000..33b061c Binary files /dev/null and b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_fmc_fru.o differ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_platform_identify.c b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_platform_identify.c new file mode 100644 index 0000000..6413b3f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_platform_identify.c @@ -0,0 +1,77 @@ +#include +#include +#include +#ifdef __GNUC__ +#include +#include +#include +#include +#else +#ifdef _WIN64 +#define ssize_t __int64 +#else +#define ssize_t long +#endif + +#define STDIN_FILENO 0 +#define STDOUT_FILENO 1 +#define STDERR_FILENO 2 +#define strncasecmp(x,y,z) _strnicmp(x,y,z) +#endif +#include +#include +/* #define __USE_XOPEN */ /* needed for strptime */ +#include +#include +#include +#include + +#include "adi_platform_identify.h" +#include "adi_fmc_eeprom.h" +#include "adi_fmc_fru.h" + +int32_t adi_platform_Identify(uint32_t* platform) +{ + adi_hal_Err_e retVal = ADI_HAL_OK; + char bufStr[128] = {0}; + FILE* identityFD = NULL; + + + if ((identityFD = fopen(MOTHERBOARD_NAME_PATH, + "r")) == NULL) + { + return (ADI_HAL_GEN_SW); + } + + if (fgets(bufStr, + 64, + identityFD) == NULL) + { + return (ADI_HAL_GEN_SW); + } + + if (strstr(bufStr, + "9025") != NULL) + { + *platform = (uint32_t)ADI_ADS9_PLATFORM; + } + else if (strstr(bufStr, + "9010") != NULL) + { + *platform = (uint32_t)ADI_ADS8_PLATFORM; + } + else if (strstr(bufStr, + "tokelau") != NULL) + { + *platform = (uint32_t)ADI_ADS8_PLATFORM; + } + else + { + printf("ERROR: %s:%u has failed.\n", + __func__, + __LINE__); + return (ADI_HAL_GEN_SW); + } + + return (int32_t)retVal; +} diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_platform_identify.h b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_platform_identify.h new file mode 100644 index 0000000..c6f91a3 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_platform_identify.h @@ -0,0 +1,42 @@ +/** +* \file adi_board_identify.h +* \brief Contains ADI Transceiver Hardware Abstraction functions interface +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +*/ + +/** +* \Page Disclaimer Legal Disclaimer +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef __ADI_PLATFORM_IDENTIFY_H__ +#define __ADI_PLATFORM_IDENTIFY_H__ + +#include "adi_platform_types.h" + +#ifdef __cplusplus +extern "C" { +#endif +/** +* \brief Probe and identity the motherboard. +* +* \pre +* +* \dep_begin +* \dep_end +* +* +* \param platform Pointer to return the platform identification +* +* \retval ADI_HAL_GEN_SW Recovery action for bad parameter check +* \retval ADI_HAL_OK Function completed successfully, no action required +*/ +int32_t adi_platform_Identify(uint32_t* platform); + +#ifdef __cplusplus +} +#endif +#endif /* __ADI_PLATFORM_IDENTIFY_H__ */ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_platform_identify.o b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_platform_identify.o new file mode 100644 index 0000000..0d00d8f Binary files /dev/null and b/driver/rfic/rf/adrv9025/c_src/platforms/platform_utils/adi_platform_identify.o differ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/include/linux/spi/spi.h b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/include/linux/spi/spi.h new file mode 100644 index 0000000..236a85f --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/include/linux/spi/spi.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ +#ifndef _UAPI_SPI_H +#define _UAPI_SPI_H + +#include + +#define SPI_CPHA _BITUL(0) /* clock phase */ +#define SPI_CPOL _BITUL(1) /* clock polarity */ + +#define SPI_MODE_0 (0|0) /* (original MicroWire) */ +#define SPI_MODE_1 (0|SPI_CPHA) +#define SPI_MODE_2 (SPI_CPOL|0) +#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) +#define SPI_MODE_X_MASK (SPI_CPOL|SPI_CPHA) + +#define SPI_CS_HIGH _BITUL(2) /* chipselect active high? */ +#define SPI_LSB_FIRST _BITUL(3) /* per-word bits-on-wire */ +#define SPI_3WIRE _BITUL(4) /* SI/SO signals shared */ +#define SPI_LOOP _BITUL(5) /* loopback mode */ +#define SPI_NO_CS _BITUL(6) /* 1 dev/bus, no chipselect */ +#define SPI_READY _BITUL(7) /* slave pulls low to pause */ +#define SPI_TX_DUAL _BITUL(8) /* transmit with 2 wires */ +#define SPI_TX_QUAD _BITUL(9) /* transmit with 4 wires */ +#define SPI_RX_DUAL _BITUL(10) /* receive with 2 wires */ +#define SPI_RX_QUAD _BITUL(11) /* receive with 4 wires */ +#define SPI_CS_WORD _BITUL(12) /* toggle cs after each word */ +#define SPI_TX_OCTAL _BITUL(13) /* transmit with 8 wires */ +#define SPI_RX_OCTAL _BITUL(14) /* receive with 8 wires */ +#define SPI_3WIRE_HIZ _BITUL(15) /* high impedance turnaround */ + +/* + * All the bits defined above should be covered by SPI_MODE_USER_MASK. + * The SPI_MODE_USER_MASK has the SPI_MODE_KERNEL_MASK counterpart in + * 'include/linux/spi/spi.h'. The bits defined here are from bit 0 upwards + * while in SPI_MODE_KERNEL_MASK they are from the other end downwards. + * These bits must not overlap. A static assert check should make sure of that. + * If adding extra bits, make sure to increase the bit index below as well. + */ +#define SPI_MODE_USER_MASK (_BITUL(16) - 1) + +#endif /* _UAPI_SPI_H */ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/include/linux/spi/spidev.h b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/include/linux/spi/spidev.h new file mode 100644 index 0000000..0c3da08 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/include/linux/spi/spidev.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ +/* + * include/linux/spi/spidev.h + * + * Copyright (C) 2006 SWAPP + * Andrea Paterniani + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef SPIDEV_H +#define SPIDEV_H + +#include +#include +#include + +/* IOCTL commands */ + +#define SPI_IOC_MAGIC 'k' + +/** + * struct spi_ioc_transfer - describes a single SPI transfer + * @tx_buf: Holds pointer to userspace buffer with transmit data, or null. + * If no data is provided, zeroes are shifted out. + * @rx_buf: Holds pointer to userspace buffer for receive data, or null. + * @len: Length of tx and rx buffers, in bytes. + * @speed_hz: Temporary override of the device's bitrate. + * @bits_per_word: Temporary override of the device's wordsize. + * @delay_usecs: If nonzero, how long to delay after the last bit transfer + * before optionally deselecting the device before the next transfer. + * @cs_change: True to deselect device before starting the next transfer. + * @word_delay_usecs: If nonzero, how long to wait between words within one + * transfer. This property needs explicit support in the SPI controller, + * otherwise it is silently ignored. + * + * This structure is mapped directly to the kernel spi_transfer structure; + * the fields have the same meanings, except of course that the pointers + * are in a different address space (and may be of different sizes in some + * cases, such as 32-bit i386 userspace over a 64-bit x86_64 kernel). + * Zero-initialize the structure, including currently unused fields, to + * accommodate potential future updates. + * + * SPI_IOC_MESSAGE gives userspace the equivalent of kernel spi_sync(). + * Pass it an array of related transfers, they'll execute together. + * Each transfer may be half duplex (either direction) or full duplex. + * + * struct spi_ioc_transfer mesg[4]; + * ... + * status = ioctl(fd, SPI_IOC_MESSAGE(4), mesg); + * + * So for example one transfer might send a nine bit command (right aligned + * in a 16-bit word), the next could read a block of 8-bit data before + * terminating that command by temporarily deselecting the chip; the next + * could send a different nine bit command (re-selecting the chip), and the + * last transfer might write some register values. + */ +struct spi_ioc_transfer { + __u64 tx_buf; + __u64 rx_buf; + + __u32 len; + __u32 speed_hz; + + __u16 delay_usecs; + __u8 bits_per_word; + __u8 cs_change; + __u8 tx_nbits; + __u8 rx_nbits; + __u8 word_delay_usecs; + __u8 pad; + + /* If the contents of 'struct spi_ioc_transfer' ever change + * incompatibly, then the ioctl number (currently 0) must change; + * ioctls with constant size fields get a bit more in the way of + * error checking than ones (like this) where that field varies. + * + * NOTE: struct layout is the same in 64bit and 32bit userspace. + */ +}; + +/* not all platforms use or _IOC_TYPECHECK() ... */ +#define SPI_MSGSIZE(N) \ + ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ + ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0) +#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) + + +/* Read / Write of SPI mode (SPI_MODE_0..SPI_MODE_3) (limited to 8 bits) */ +#define SPI_IOC_RD_MODE _IOR(SPI_IOC_MAGIC, 1, __u8) +#define SPI_IOC_WR_MODE _IOW(SPI_IOC_MAGIC, 1, __u8) + +/* Read / Write SPI bit justification */ +#define SPI_IOC_RD_LSB_FIRST _IOR(SPI_IOC_MAGIC, 2, __u8) +#define SPI_IOC_WR_LSB_FIRST _IOW(SPI_IOC_MAGIC, 2, __u8) + +/* Read / Write SPI device word length (1..N) */ +#define SPI_IOC_RD_BITS_PER_WORD _IOR(SPI_IOC_MAGIC, 3, __u8) +#define SPI_IOC_WR_BITS_PER_WORD _IOW(SPI_IOC_MAGIC, 3, __u8) + +/* Read / Write SPI device default max speed hz */ +#define SPI_IOC_RD_MAX_SPEED_HZ _IOR(SPI_IOC_MAGIC, 4, __u32) +#define SPI_IOC_WR_MAX_SPEED_HZ _IOW(SPI_IOC_MAGIC, 4, __u32) + +/* Read / Write of the SPI mode field */ +#define SPI_IOC_RD_MODE32 _IOR(SPI_IOC_MAGIC, 5, __u32) +#define SPI_IOC_WR_MODE32 _IOW(SPI_IOC_MAGIC, 5, __u32) + + + +#endif /* SPIDEV_H */ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/makefile b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/makefile new file mode 100644 index 0000000..85d38eb --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/makefile @@ -0,0 +1,21 @@ +LIB_ADI_UCP2PLATFORM = libadi_ucp2platform.a +#CC = aarch64-linux-gnu-gcc + +ARFLAGS = -rv +CFLAGS = -Wall -I. -I../ -I./include -I../../../../ucp/inc -I../../../../api/inc -Werror +EXT = c + +SRC = $(wildcard *.$(EXT)) +OBJS = $(SRC:.$(EXT)=.o) + +all: $(SRC) $(LIB_ADI_UCP2PLATFORM) + +.$(EXT).o: + $(CC) $(CFLAGS) -o $@ -c $< + +$(LIB_ADI_UCP2PLATFORM): $(OBJS) + ar $(ARFLAGS) $(LIB_ADI_UCP2PLATFORM) $(OBJS) + +clean: + rm -rf *.o + rm -rf *.a \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_bbic_control.c b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_bbic_control.c new file mode 100644 index 0000000..4977b55 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_bbic_control.c @@ -0,0 +1,514 @@ +/** +* \file ucp2_bbic_control.c +* \brief Contains ADI Transceiver Hardware Abstraction functions for ADS9 interface to FPGA (BBIC) control registers. +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include +#include +#include + +#ifdef __GNUC__ +#include +#include +#endif + +#include +#include "ucp2_bbic_control.h" + +/********************/ +/* Public functions */ +/********************/ + +/** +* \brief Function to open any necessary resources for the BBIC + interface functions in this file. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_NULL_PTR If devHalCfg pointer is NULL +* \retval ADI_HAL_BBICCTRL_FAIL If critical error trying to open resources +*/ +int32_t ucp2_BbicOpen(void* devHalCfg) +{ + adi_hal_Cfg_t* halCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS9 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + +#ifdef __GNUC__ + /* Open UIO driver to FPGA register interface */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_CORE) > 0) && halCfg->bbicCfg.coreRegsCfg.fd <= 0) + { + halCfg->bbicCfg.coreRegsCfg.fd = open(halCfg->bbicCfg.coreRegsCfg.drvName, + O_RDWR); + + if (halCfg->bbicCfg.coreRegsCfg.fd < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + /* offset must be page aligned */ + halCfg->bbicCfg.coreRegsCfg.mappedMemoryPtr = (uintptr_t)mmap(NULL, + halCfg->bbicCfg.coreRegsCfg.mapSize, + PROT_READ | PROT_WRITE, + MAP_SHARED, + halCfg->bbicCfg.coreRegsCfg.fd, + 0); + + if ((void *)halCfg->bbicCfg.coreRegsCfg.mappedMemoryPtr == MAP_FAILED) + { + perror("Error mapping the file for fpga core registers."); + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + } + + /* Open UIO driver to FPGA Data capture memory RAM interface */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_RAM) > 0) && halCfg->bbicCfg.ramCfg.fd <= 0) + { + halCfg->bbicCfg.ramCfg.fd = open(halCfg->bbicCfg.ramCfg.drvName, + O_RDWR); + + if (halCfg->bbicCfg.ramCfg.fd < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + /* offset must be page aligned */ + halCfg->bbicCfg.ramCfg.mappedMemoryPtr = (uintptr_t)mmap(NULL, + halCfg->bbicCfg.ramCfg.mapSize, + PROT_READ | PROT_WRITE, + MAP_SHARED, + halCfg->bbicCfg.ramCfg.fd, + 0); + + if ((void *)halCfg->bbicCfg.ramCfg.mappedMemoryPtr == MAP_FAILED) + { + perror("Error mapping the file for fpga ram."); + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + } + + /* Open UIO driver to FPGA Advanced SPI settings interface */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_SPI) > 0) && halCfg->bbicCfg.spiAdvRegsCfg.fd <= 0) + { + halCfg->bbicCfg.spiAdvRegsCfg.fd = open(halCfg->bbicCfg.spiAdvRegsCfg.drvName, + O_RDWR); + + if (halCfg->bbicCfg.spiAdvRegsCfg.fd < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + /* offset must be page aligned */ + halCfg->bbicCfg.spiAdvRegsCfg.mappedMemoryPtr = (uintptr_t)mmap(NULL, + halCfg->bbicCfg.spiAdvRegsCfg.mapSize, + PROT_READ | PROT_WRITE, + MAP_SHARED, + halCfg->bbicCfg.spiAdvRegsCfg.fd, + 0); + + if ((void *)halCfg->bbicCfg.spiAdvRegsCfg.mappedMemoryPtr == MAP_FAILED) + { + perror("Error mapping the file for fpga spiAdvRegsCfg registers."); + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + } + +#endif /* __GNUC__ */ + return halError; +} + +/** +* \brief Function to close any necessary resources for the BBIC + interface functions in this file. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_NULL_PTR If devHalCfg pointer is NULL +* \retval ADI_HAL_BBICCTRL_FAIL If critical error trying to close resources +*/ +int32_t ucp2_BbicClose(void* devHalCfg) +{ + adi_hal_Cfg_t* halCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ADS9 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + +#ifdef __GNUC__ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_CORE) > 0) && halCfg->bbicCfg.coreRegsCfg.fd != 0) + { + halError = munmap((void *)halCfg->bbicCfg.coreRegsCfg.mappedMemoryPtr, + halCfg->bbicCfg.coreRegsCfg.mapSize); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + halError = close(halCfg->bbicCfg.coreRegsCfg.fd); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + halCfg->bbicCfg.coreRegsCfg.fd = 0; + } + + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_RAM) > 0) && halCfg->bbicCfg.ramCfg.fd != 0) + { + halError = munmap((void *)halCfg->bbicCfg.ramCfg.mappedMemoryPtr, + halCfg->bbicCfg.ramCfg.mapSize); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + halError = close(halCfg->bbicCfg.ramCfg.fd); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + halCfg->bbicCfg.ramCfg.fd = 0; + } + + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_SPI) > 0) && halCfg->bbicCfg.spiAdvRegsCfg.fd != 0) + { + halError = munmap((void *)halCfg->bbicCfg.spiAdvRegsCfg.mappedMemoryPtr, + halCfg->bbicCfg.spiAdvRegsCfg.mapSize); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + halError = close(halCfg->bbicCfg.spiAdvRegsCfg.fd); + if (halError < 0) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + halCfg->bbicCfg.spiAdvRegsCfg.fd = 0; + } +#endif /* __GNUC__ */ + + return halError; +} + +/** +* \brief Function to initialize any necessary resources for the BBIC + interface functions in this file. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ucp2_BbicInit(void* devHalCfg) +{ + (void)(devHalCfg); + /* ADI ADS9 platform does not require any BBIC register/control init */ + return (int32_t)ADI_HAL_OK; +} + +/** + * \brief Function to read a single BBIC control register + * + * \param devHalCfg Pointer to device instance specific platform settings + * \param addr 32bit address of BBIC register to read + * \param data 32bit Pointer to store return value representing the data of the register at the specified address + * + * \retval ADI_HAL_OK Function completed successfully + * \retval ADI_HAL_NULL_PTR devHalCfg pointer is NULL or data pointer is NULL + */ +int32_t ucp2_BbicRegisterRead(void* devHalCfg, + uint32_t addr, + uint32_t* data) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + static const uint8_t READ_REG = 0; + + if ((devHalCfg == NULL) || (data == NULL)) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + halError = ucp2_fpga_AxiReadWrite(devHalCfg, + READ_REG, + addr, + data); + + return halError; +} + +/** + * \brief Function to write a single BBIC control register + * + * \param devHalCfg Pointer to device instance specific platform settings + * \param addr 32bit address of BBIC register to write + * \param data 32bit data to write to the register at the specified address + * + * \retval ADI_HAL_OK Function completed successfully + * \retval ADI_HAL_NULL_PTR devHalCfg pointer is NULL + */ +int32_t ucp2_BbicRegisterWrite(void* devHalCfg, + uint32_t addr, + uint32_t data) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + static const uint8_t WRITE_REG = 1; + + if (devHalCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + halError = ucp2_fpga_AxiReadWrite(devHalCfg, + WRITE_REG, + addr, + &data); + + return halError; +} + +/** + * \brief Function to read multiple consecutive BBIC control registers starting at a specified register address. + * + * \param devHalCfg Pointer to device instance specific platform settings + * \param addr 32bit address of BBIC register to start reading from + * \param data 32bit Pointer to store return array representing the data starting at the specified register address + and ending at (addr + numDataWords -1) + * \param numDataWords Number of elements in the data array + * + * \retval ADI_HAL_OK Function completed successfully + * \retval ADI_HAL_NULL_PTR devHalCfg pointer is NULL + */ +int32_t ucp2_BbicRegistersRead(void* devHalCfg, + uint32_t addr, + uint32_t data[], + uint32_t numDataWords) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + static const uint8_t READ_REG = 0; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halError = ucp2_fpga_AxiBulkReadWrite(devHalCfg, + READ_REG, + addr, + data, + numDataWords); + + return halError; +} + +/** + * \brief Function to write multiple consecutive BBIC control registers starting at a specified register address. + * + * \param devHalCfg Pointer to device instance specific platform settings + * \param addr 32bit address of BBIC register to start writing to + * \param data 32bit Pointer to array representing the data to write starting at the specified register address + and ending at (addr + numDataWords -1) + * \param numDataWords Number of elements in the data array + * + * \retval ADI_HAL_OK Function completed successfully + * \retval ADI_HAL_NULL_PTR devHalCfg pointer is NULL + */ +int32_t ucp2_BbicRegistersWrite(void* devHalCfg, + uint32_t addr, + uint32_t data[], + uint32_t numDataWords) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + static const uint8_t WRITE_REG = 1; + + if (devHalCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + halError = ucp2_fpga_AxiBulkReadWrite(devHalCfg, + WRITE_REG, + addr, + data, + numDataWords); + + return halError; +} + +/*********************/ +/* Private functions */ +/*********************/ + +/** +* \brief Writes and reads to the BBIC (FPGA) AXI memory mapped registers. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param writeFlag (Hi) tells the function to write the data to address addr +* \Param writeFlag 1 = write, 0 = read. +* \param data the data to write to address addr. +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_GEN_SW If addr is out of valid range +* \retval ADI_HAL_BBICCTRL_FAIL If critical error during read or write operation +*/ +int32_t ucp2_fpga_AxiReadWrite(void* devHalCfg, + uint8_t writeFlag, + uint32_t addr, + uint32_t* data) +{ + adi_hal_Cfg_t* halCfg = NULL; + adi_hal_fpga_AxiCfg_t* axiCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + uint32_t offsetAddr = 0; + void* ptr = NULL; + + if (devHalCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if ((addr >= ADS9_FPGA_UIO2_START_ADDRESS) && + (addr <= ADS9_FPGA_UIO2_STOP_ADDRESS)) + { + offsetAddr = addr - ADS9_FPGA_UIO2_START_ADDRESS; + axiCfg = &halCfg->bbicCfg.spiAdvRegsCfg; + } + else if ((addr >= ADS9_FPGA_UIO0_START_ADDRESS) && + (addr <= ADS9_FPGA_UIO0_STOP_ADDRESS)) + { + offsetAddr = addr - ADS9_FPGA_UIO0_START_ADDRESS; + axiCfg = &halCfg->bbicCfg.coreRegsCfg; + } + else + { + /* The offset parameter is the actual fpga memory address. Range check to make sure it's valid */ + halError = (int32_t)ADI_HAL_GEN_SW; + return halError; + } + +#ifdef __GNUC__ + + if (axiCfg == NULL) + { + return (int32_t)ADI_HAL_NULL_PTR; + } + + ptr = (void *)axiCfg->mappedMemoryPtr; + + if (ptr == MAP_FAILED || ptr == NULL) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + if (writeFlag) + { + *((uint32_t *)((uintptr_t)ptr + offsetAddr)) = *data; + } + else + { + *data = *((uint32_t*)((uintptr_t)ptr + offsetAddr)); + } + +#endif /* __GNUC__ */ + + return halError; +} + +/** +* \brief Writes and reads to the BBIC (FPGA) AXI memory mapped registers. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \Param writeFlag 1 = write, 0 = read. +* \param addr the address to write the data to. +* \param data the data to write to address addr. +* \param numData number of data words (unit32_t). +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_BBICCTRL_FAIL If critcal error during read or write transaction +*/ +int32_t ucp2_fpga_AxiBulkReadWrite(void* devHalCfg, + uint8_t writeFlag, + uint32_t addr, + uint32_t data[], + const uint32_t numData) +{ + adi_hal_Cfg_t* halCfg = NULL; + adi_hal_fpga_AxiCfg_t* ramCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + /* uint32_t offsetAddr = 0; */ + void* ptr = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + ramCfg = &halCfg->bbicCfg.ramCfg; + + if (ramCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + if (addr + numData > ramCfg->mapSize) + { + halError = (int32_t)ADI_HAL_BBICCTRL_FAIL; + return halError; + } + +#ifdef __GNUC__ + + ptr = (void *)ramCfg->mappedMemoryPtr; + + if (ptr == MAP_FAILED || ptr == NULL) + { + return (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + + if (writeFlag) + { + memcpy((void *)((uintptr_t)ptr + addr), + data, + numData * sizeof(uint32_t)); + } + else + { + memcpy(data, + (void *)((uintptr_t)ptr + addr), + numData * sizeof(uint32_t)); + } + +#endif /* __GNUC__ */ + + return halError; +} diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_bbic_control.h b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_bbic_control.h new file mode 100644 index 0000000..1af5532 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_bbic_control.h @@ -0,0 +1,69 @@ +/** +* \file ucp2_bbic_control.h +* \brief Contains ADI Transceiver Hardware Abstraction functions for ucp2 interface to FPGA (BBIC) control registers. +* Analog Devices maintains and provides updates to this code layer. +* The end user should not modify this file or any code in this directory. +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef __UCP2_BBIC_CONTROL_H__ +#define __UCP2_BBIC_CONTROL_H__ + +#include +#include "adi_platform_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADS9_FPGA_UIO0_START_ADDRESS 0x40000000 +#define ADS9_FPGA_UIO0_STOP_ADDRESS 0x5FFFFFFF +#define ADS9_FPGA_UIO2_START_ADDRESS 0x44A00000 +#define ADS9_FPGA_UIO2_STOP_ADDRESS 0x44A00FFF + +int32_t ucp2_BbicOpen(void* devHalCfg); + +int32_t ucp2_BbicClose(void* devHalCfg); + +int32_t ucp2_BbicInit(void* devHalCfg); + +int32_t ucp2_BbicRegisterRead(void* devHalCfg, + uint32_t addr, + uint32_t* data); + +int32_t ucp2_BbicRegisterWrite(void* devHalCfg, + uint32_t addr, + uint32_t data); + +int32_t ucp2_BbicRegistersRead(void* devHalCfg, + uint32_t addr, + uint32_t data[], + uint32_t numDataWords); + +int32_t ucp2_BbicRegistersWrite(void* devHalCfg, + uint32_t addr, + uint32_t data[], + uint32_t numDataWords); + +/* Local helper functions */ +/* TODO: remove these functions */ +int32_t ucp2_fpga_AxiReadWrite(void* devHalCfg, + uint8_t writeFlag, + uint32_t addr, + uint32_t* data); + +int32_t ucp2_fpga_AxiBulkReadWrite(void* devHalCfg, + uint8_t writeFlag, + uint32_t addr, + uint32_t data[], + const uint32_t numData); + +#ifdef __cplusplus +} +#endif +#endif /*__ADS9_BBIC_CONTROL_H__*/ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_init.c b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_init.c new file mode 100644 index 0000000..ffb7d93 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_init.c @@ -0,0 +1,523 @@ +/** +* \file ucp2_init.c +* \brief Contains ADI Transceiver Hardware Abstraction functions for hardware mode. +* Analog Devices maintains and provides updates to this code layer for the ADS9 platform. +* The end user should not modify this file or any code in this directory. The end user +* may provide a similar platform layer that can be used in place of this platform layer, +* that uses the same function prototypes. +*/ + +/** +* \Page Disclaimer Legal Disclaimer +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include +#include +#include +#include "ucp2_init.h" +#include "ucp2_spi.h" +#include "ucp2_logging.h" +#include "ucp2_timer.h" +#include "ucp2_bbic_control.h" + +#include +#include "ucp_jesd_gpio.h" +#include "ucp_rfic_gpio.h" + +/** +* \brief Opens all necessary files and device drivers for a specific device +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +* \retval errors returned by other function calls. +*/ +int32_t ucp2_HwOpen(void* devHalCfg) +{ + adi_hal_Cfg_t* halCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + char logMessage[ADI_HAL_MAX_LOG_LINE] = {0}; + int32_t result = 0; +#ifdef __GNUC__ + va_list empty_va_list; +#else + va_list empty_va_list = { 0 }; +#endif + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->logCfg.interfaceEnabled > 0) + { + if (halCfg->logCfg.logFileName[0] == '\0') + { + halError = ucp2_LogFileOpen(devHalCfg, + "ucp2_adihal.log"); + } + else + { + halError = ucp2_LogFileOpen(devHalCfg, + NULL); + } + + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + result = snprintf(logMessage + strlen(logMessage), + ADI_HAL_MAX_LOG_LINE, + "ucp2_LogFileOpen: device index %d\n", + halCfg->spiCfg.chipSelectIndex); + if (result < 0) + { + return (int32_t)ADI_HAL_LOGGING_FAIL; + } + + halError = ucp2_LogWrite(devHalCfg, + ADI_HAL_LOG_MSG, + logMessage, + empty_va_list); + + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + } + + if (halCfg->spiCfg.interfaceEnabled > 0) + { + halError = ucp2_SpiOpen(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ucp2_SpiInit(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + } + + if (halCfg->bbicCfg.interfaceEnabled > 0) + { + halError = ucp2_BbicOpen(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ucp2_BbicInit(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + } + + if (halCfg->hwResetCfg.interfaceEnabled > 0) + { + /* ADS9 has nothing to open, as this interface is supported by the + * BBIC control interface */ + + #if 0 + /* Verify BBIC control interface was enabled */ + if (halCfg->bbicCfg.interfaceEnabled == 0) + { + halError = ADI_HAL_GEN_SW; + return halError; + } + #endif + } + + if (halCfg->timerCfg.interfaceEnabled > 0) + { + halError = ucp2_TimerOpen(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ucp2_TimerInit(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + } + + /* ADS9 does not require any code to open /init timer support since using linux nanosleep function */ + + return halError; +} + +/** +* \brief Gracefully shuts down the the hardware closing any open resources +* such as log files, I2C, SPI, GPIO drivers, timer resources, etc. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +*/ +int32_t ucp2_HwClose(void* devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halError = ucp2_LogLevelSet(devHalCfg, + ADI_HAL_LOG_NONE); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ucp2_LogFileClose(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ucp2_SpiClose(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ucp2_BbicClose(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + halError = ucp2_TimerClose(devHalCfg); + if (halError != (int32_t)ADI_HAL_OK) + { + return halError; + } + + return halError; +} + +/** +* \brief This function control a BBIC GPIO pin that connects to the reset pin +* of each device. +* +* This function is called by each device API giving access to the Reset pin +* connected to each device. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param pinLevel The desired pin logic level 0=low, 1=high to set the GPIO pin to. +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +*/ +int32_t ucp2_HwReset(void* devHalCfg, + uint8_t pinLevel) +{ + adi_hal_Cfg_t* halCfg = NULL; + adi_hal_HwResetCfg_t* hwResetCfg = NULL; + int32_t halError = (int32_t)ADI_HAL_OK; + int32_t retVal = 0; + + int32_t resetPin; + int32_t pinValue; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + hwResetCfg = &halCfg->hwResetCfg; + + if (hwResetCfg == NULL) + { + return ADI_HAL_NULL_PTR; + } + +#ifdef __GNUC__ + + if (hwResetCfg->interfaceEnabled > 0) + { + /* Note the pin level is inverted in the ADS9 FPGA...hence then logic inversion here */ + // pinLevelBit = (pinLevel > 0) ? 0 : 1; + pinValue = pinLevel; + + /* hwResetCfg->resetPinIndex is the bit position in FPGA_RESETPIN_REGISTER + * for the reset pin of the requested device */ + switch (hwResetCfg->resetPinIndex) + { + case 1: /* ADRV9025: For ADS9 platform, FPGA register 0x43041004 bit 1 controls RESET pin */ + { + // resetPinBitPostion = hwResetCfg->resetPinIndex; + resetPin = GPIO_INDEX_9025RESET; + break; + } + + case 2: /* AD9528: For ADS9 platform, FPGA register 0x43041004 bit 2 controls RESET pin */ + { + // resetPinBitPostion = hwResetCfg->resetPinIndex; + resetPin = GPIO_INDEX_9528RESET; + break; + } + + default: + { + /* Invalid Hardware reset pin index for ADS9 Platform */ + return ADI_HAL_GPIO_FAIL; + } + } + + retVal = ucp_jesd_gpioSet(resetPin, pinValue); + + if (retVal != true) + { + return ADI_HAL_GPIO_FAIL; + } + } + +#endif /* __GNUC__ */ + + return ADI_HAL_OK; +} + +/** +* \brief This function is a helper function to fill out the members of the +* devHalCfg structure with driver names for this specific (ADS9) platform. +* +* This function allows keeping the platform specific knowledge of driver names +* in this layer of code. Higher layers of code can call this to fill out the +* devHalCfg structure correctly for the ADS9 platform. +* +* Each device gets a unique instance of the devHalCfg structure describing the +* device resources for that device, such as the SPI chip select, etc. +* +* \param interfaceMask A mask that represents which platform interfaces are required by a particular device (SPI, Logging, etc) +* \param spiChipSelect The chip select index describing the particular device this structure is for (0, 1, 2 valid on ADS9) +* \param logFilename The filename of the logfile for this device. +*/ +void* ucp2_DevHalCfgCreate(uint32_t interfaceMask, + uint8_t spiChipSelect, + const char* logFilename) +{ + adi_hal_Cfg_t* halCfg = (adi_hal_Cfg_t*)calloc(1, + sizeof(adi_hal_Cfg_t)); + + if (halCfg == NULL) + { + return NULL; + } + + /* Disable all interfaces, and enable only if they are needed by the specific device */ + halCfg->spiCfg.interfaceEnabled = 0; + halCfg->logCfg.interfaceEnabled = 0; + halCfg->bbicCfg.interfaceEnabled = 0; + + /* If device requires SPI interface */ + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_SPI) > 0) + { + halCfg->spiCfg.interfaceEnabled = 1; + + switch (spiChipSelect) + { + case 0: + { + strncpy(halCfg->spiCfg.spidevName, + "/dev/spidev0.0\0", + ADI_HAL_STRING_LENGTH); + halCfg->spiCfg.chipSelectIndex = spiChipSelect; + break; + } + case 1: + { + strncpy(halCfg->spiCfg.spidevName, + "/dev/spidev0.0\0", + ADI_HAL_STRING_LENGTH); + halCfg->spiCfg.chipSelectIndex = spiChipSelect; + break; + } + case 2: + { + strncpy(halCfg->spiCfg.spidevName, + "/dev/spidev0.0\0", + ADI_HAL_STRING_LENGTH); + halCfg->spiCfg.chipSelectIndex = spiChipSelect; + break; + } + default: + { + free(halCfg); + return NULL; + } + } + + /* Default SPI settings */ + halCfg->spiCfg.autoIncAddrUp = 1; + halCfg->spiCfg.CPHA = 0; + halCfg->spiCfg.CPOL = 0; + halCfg->spiCfg.enSpiStreaming = 0; + halCfg->spiCfg.fourWireMode = 1; + halCfg->spiCfg.spiActionDisable = 0; + halCfg->spiCfg.spiClkFreq_Hz = 25000000; + } + + /* If device requires Logging interface */ + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_LOG) > 0) + { + halCfg->logCfg.interfaceEnabled = 1; + halCfg->logCfg.logLevel = ADI_HAL_LOG_ALL; + strncpy(halCfg->logCfg.logFileName, + logFilename, + ADI_HAL_STRING_LENGTH); + /* ensure null termination */ + halCfg->logCfg.logFileName[sizeof(halCfg->logCfg.logFileName) - 1] = '\0'; + } + + /* If device requires FPGA register interface */ + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_BBICCTRL) > 0) + { +#if 0 + halCfg->bbicCfg.interfaceEnabled = (ADI_HAL_BBIC_CORE | ADI_HAL_BBIC_RAM | ADI_HAL_BBIC_SPI); + strncpy(halCfg->bbicCfg.coreRegsCfg.drvName, + "/dev/uio0\0", + ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.coreRegsCfg.mapSize = 0x20000000; /* 512MB */ + strncpy(halCfg->bbicCfg.ramCfg.drvName, + "/dev/uio1\0", + ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.ramCfg.mapSize = 0x40000000; /* 1GB */ + + strncpy(halCfg->bbicCfg.spiAdvRegsCfg.drvName, + "/dev/uio2\0", + ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.spiAdvRegsCfg.mapSize = 0x1000; /* 16MB */ +#endif + } + /* ADS9 HWRESET interface requires BBICCTRL interface */ + else if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_HWRESET) > 0) + { + halCfg->hwResetCfg.interfaceEnabled = 1; +#if 0 + halCfg->bbicCfg.interfaceEnabled = ADI_HAL_BBIC_CORE | ADI_HAL_BBIC_SPI; + + strncpy(halCfg->bbicCfg.coreRegsCfg.drvName, + "/dev/uio0\0", + ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.coreRegsCfg.mapSize = 0x3042000; /* 48MB to access hwReset TODO: include bitfields to get the correct address? */ + + strncpy(halCfg->bbicCfg.spiAdvRegsCfg.drvName, + "/dev/uio2\0", + ADI_HAL_STRING_LENGTH); + halCfg->bbicCfg.spiAdvRegsCfg.mapSize = 0x1000; /* 16MB */ +#endif + + switch (spiChipSelect) + { + case 0: + { + halCfg->hwResetCfg.resetPinIndex = 1; /* ADRV9025 reset pin bit position in FPGA register */ + break; + } + case 1: + { + halCfg->hwResetCfg.resetPinIndex = 2; /* AD9528 reset pin bit position in FPGA register */ + break; + } + case 2: + { + halCfg->hwResetCfg.resetPinIndex = 0; + /* SPI2 does not need hwReset, only access to Adv Spi. A 0 value here will not get past the hwReset range checks */ + break; + } + default: + free(halCfg); + return NULL; + } + } + + if ((interfaceMask & (uint32_t)ADI_HAL_INTERFACE_TIMER) > 0) + { + halCfg->timerCfg.interfaceEnabled = 1; + /* Currently no timer config structure for ADS9 platform */ + } + halCfg->interfaceMask = interfaceMask; + return halCfg; +} + +int32_t ucp2_DevHalCfgFree(void* devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + + free(devHalCfg); + + return halError; +} + +int32_t ucp2_HwVerify(void *devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t *halCfg = NULL; + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + + /* interpret the interface mask */ + + /* ADI_HAL_INTERFACE_SPI */ + if ((halCfg->interfaceMask & (uint32_t)ADI_HAL_INTERFACE_SPI) > 0) /* Device requires spi interface */ + { + /* throw an error if pointer is NULL */ + if (halCfg->spiCfg.fd == 0) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + } + } + + /* ADI_HAL_INTERFACE_LOG */ + if ((halCfg->interfaceMask & (uint32_t)ADI_HAL_INTERFACE_LOG) > 0) /* Device requires logging interface */ + { + /* throw an error if pointer is NULL */ + if (halCfg->logCfg.logfd == 0) + { + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + } + } + + /* ADI_HAL_INTERFACE_BBICCTRL */ + if ((halCfg->interfaceMask & (uint32_t)ADI_HAL_INTERFACE_BBICCTRL) > 0) /* Device requires fpga register interface */ + { + /* throw an error if pointer is NULL */ + if (halCfg->bbicCfg.coreRegsCfg.fd == 0 || + halCfg->bbicCfg.ramCfg.fd == 0 || + halCfg->bbicCfg.spiAdvRegsCfg.fd == 0) + { + halError = (int32_t)ADI_HAL_BBICCTRL_FAIL; + } + } + + /* ADI_HAL_HWRESET */ + /* Not affected by HwClose */ + + /* ADI_HAL_INTERFACE_TIMER */ + /* Not affected by HwClose */ + + return halError; +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_init.h b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_init.h new file mode 100644 index 0000000..54506ae --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_init.h @@ -0,0 +1,43 @@ +/** +* \file ucp2_init.h +* \brief Contains ADI Transceiver Hardware Abstraction functions for the ADS9 Platform. +* Analog Devices maintains and provides updates to this code layer for the ADS9 platform. +* The end user should not modify this file or any code in this directory. The end user +* may provide a similar platform layer that can be used in place of this platform layer, +* that uses the same function prototypes. +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef __UCP2_INIT_H__ +#define __UCP2_INIT_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t ucp2_HwOpen(void* devHalCfg); + +int32_t ucp2_HwReset(void* devHalCfg, + uint8_t pinLevel); + +int32_t ucp2_HwClose(void* devHalCfg); + +int32_t ucp2_HwVerify(void *devHalCfg); + +void* ucp2_DevHalCfgCreate(uint32_t interfaceMask, + uint8_t spiChipSelect, + const char* logFilename); + +int32_t ucp2_DevHalCfgFree(void* devHalCfg); + +#ifdef __cplusplus +} +#endif +#endif /*__ADS9_INIT_H__*/ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_logging.c b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_logging.c new file mode 100644 index 0000000..b867751 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_logging.c @@ -0,0 +1,420 @@ +/* +* \file ucp2_logging.c +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include +#include +#include +#include +#include +#include "ucp2_logging.h" + +/** +* \brief Opens a logFile. If the file is already open it will be closed and reopened. +* +* This function opens the file for writing and saves the resulting file +* descriptor to the devHalCfg structure. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param filename The user provided name of the file to open. +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +* \retval ADI_HAL_LOGGING_FAIL If the function failed to open or write to the specified filename +*/ +int32_t ucp2_LogFileOpen(void* devHalCfg, + const char* filename) +{ + (void)(filename); + int32_t halError = ADI_HAL_OK; + int32_t result = 0; + adi_hal_Cfg_t* halCfg = NULL; + FILE* logfd = NULL; + struct tm tm = {0}; + time_t t = {0}; + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + logfd = (FILE*)halCfg->logCfg.logfd; + + //if logfile already open, close it + if (logfd != 0) + { + halError = ucp2_LogFileClose(devHalCfg); + } + + /* open a new log file */ + logfd = fopen(halCfg->logCfg.logFileName, + "w+"); + if (logfd == NULL) + { + return (int32_t)ADI_HAL_LOGGING_FAIL; + } + + halCfg->logCfg.logfd = (uintptr_t)logfd; + + t = time(NULL); + + tm = *localtime(&t); + + result = fprintf(logfd, + "API log file \nStart date %04d-%02d-%02d %02d:%02d:%02d \nLogging level %d\n\n\n", + tm.tm_year + 1900, + tm.tm_mon + 1, + tm.tm_mday, + tm.tm_hour, + tm.tm_min, + tm.tm_sec, + halCfg->logCfg.logLevel); + if (result < 0) + { + return ADI_HAL_LOGGING_FAIL; + } + + result = fflush(logfd); + if (result < ADI_HAL_OK) + { + halError = ADI_HAL_LOGGING_FAIL; + } + + return halError; +} + +/** +* \brief Flushes the logFile buffer to the currently open log file. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +*/ +int32_t ucp2_LogFileFlush(void* devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->logCfg.logfd != 0) + { + halError = fflush((FILE*)halCfg->logCfg.logfd); + } + else + { + /* File not open, can not flush, No Error */ + halError = (int32_t)ADI_HAL_OK; + } + + return halError; +} + +/** +* \brief Gracefully closes the log file(s). +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +* \retval ADI_HAL_LOGGING_FAIL Error while flushing or closing the log file. +*/ +int32_t ucp2_LogFileClose(void* devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + int32_t result = 0; + adi_hal_Cfg_t* halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->logCfg.logfd != 0) + { + result = fflush((FILE*)halCfg->logCfg.logfd); + if (result < 0) + { + halError = ADI_HAL_LOGGING_FAIL; + } + + result = fclose((FILE*)halCfg->logCfg.logfd); + if (result < 0) + { + halError = ADI_HAL_LOGGING_FAIL; + } + + halCfg->logCfg.logfd = 0; + /* Log level reset was causing issues with the log files, logging was disabled */ + /* halCfg->logCfg.logLevel = 0; */ + } + else + { + /* Log file is not open, can not close the file - no error */ + halError = ADI_HAL_OK; + } + + return halError; +} + +/** +* \brief Sets the log level, allowing the end user to select the granularity of +* what events get logged. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param logLevel A mask of valid log levels to allow to be written to the log file. +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +*/ +int32_t ucp2_LogLevelSet(void* devHalCfg, + int32_t logLevel) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + halCfg->logCfg.logLevel = (logLevel & (int32_t)ADI_HAL_LOG_ALL); + + return halError; +} + +/** + * \brief Gets the currently set log level: the mask of different types of log + * events that are currently enabled to be logged. + * + * \param devHalCfg Pointer to device instance specific platform settings + * \param logLevel Returns the current log level mask. + * + * \retval ADI_HAL_OK Function completed successfully, no action required + * \retval ADI_HAL_NULL_PTR The function has been called with a null pointer + */ +int32_t ucp2_LogLevelGet(void* devHalCfg, + int32_t* logLevel) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + *logLevel = halCfg->logCfg.logLevel; + + return halError; +} + +/** +* \brief Writes a message to the currently open logFile specified in the +* adi_hal_LogCfg_t of the devHalCfg structure passed +* +* Uses the vfprintf functionality to allow the user to supply the format and +* the number of arguments that will be logged. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param logLevel the log level to be written into +* \param comment the string to include in the line added to the log. +* \param argp variable argument list to be printed +* +* \retval ADI_HAL_OK Function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR The function has been called with a null pointer +* \retval ADI_HAL_LOGGING_FAIL If the function failed to flush to write +*/ +int32_t ucp2_LogWrite(void* devHalCfg, + int32_t logLevel, + const char* comment, + va_list argp) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + int32_t result = 0; + adi_hal_Cfg_t* halCfg = NULL; + time_t t = time(NULL); + struct tm tm = {0}; + FILE* logfd = NULL; + char logMessage[ADI_HAL_MAX_LOG_LINE] = {0}; + const char* logLevelChar = NULL; + logMessage[0] = 0; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if ((halCfg->logCfg.interfaceEnabled == 0) || (halCfg->logCfg.logLevel == (int32_t)ADI_HAL_LOG_NONE)) + { + /* If logging disabled, exit gracefully */ + halError = (int32_t)ADI_HAL_OK; + return halError; + } + + if (logLevel > (int32_t)ADI_HAL_LOG_ALL) + { + halError = (int32_t)ADI_HAL_LOGGGING_LEVEL_FAIL; + return halError; + } + + /* Auto Open of log file is currently disabled */ + if (halCfg->logCfg.logfd == 0) + { + /* Log file is not open */ + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + return halError; + } + else + { + logfd = (FILE *)halCfg->logCfg.logfd; + + if (halCfg->logCfg.currentLineNumber >= UCP2_LOG_MAX_NUM_LINES) + { + /* seek back to beginning of file */ + /* fseek(logfd, 2, SEEK_SET); */ + rewind(logfd); + halCfg->logCfg.currentLineNumber = 0; + } + + /* Print Log type */ + if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_MSG) && (logLevel == (int32_t)ADI_HAL_LOG_MSG)) + { + logLevelChar = "MESSAGE:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_WARN) && (logLevel == (int32_t)ADI_HAL_LOG_WARN)) + { + logLevelChar = "WARNING:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_ERR) && (logLevel == (int32_t)ADI_HAL_LOG_ERR)) + { + logLevelChar = "ERROR:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_API) && (logLevel == (int32_t)ADI_HAL_LOG_API)) + { + logLevelChar = "API_LOG:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_BF) && (logLevel == (int32_t)ADI_HAL_LOG_BF)) + { + logLevelChar = "BF_LOG:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_HAL) && (logLevel == (int32_t)ADI_HAL_LOG_HAL)) + { + logLevelChar = "ADI_HAL_LOG:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_SPI) && (logLevel == (int32_t)ADI_HAL_LOG_SPI)) + { + logLevelChar = "SPI_LOG:"; + } + else if ((halCfg->logCfg.logLevel & ADI_HAL_LOG_API_PRIV) && (logLevel == (int32_t)ADI_HAL_LOG_API_PRIV)) + { + logLevelChar = "API_PRIV_LOG:"; + } + else + { + /* Nothing to log - exit cleanly */ + return (int32_t)ADI_HAL_OK; + } + + tm = *localtime(&t); + /* Print timestamp */ + result = snprintf(logMessage, + ADI_HAL_MAX_LOG_LINE, + "%04d-%02d-%02d %02d:%02d:%02d: %s", + tm.tm_year + 1900, + tm.tm_mon + 1, + tm.tm_mday, + tm.tm_hour, + tm.tm_min, + tm.tm_sec, + logLevelChar); + if (result < 0) + { + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + return halError; + } + + result = vsnprintf(logMessage + strlen(logMessage), + ADI_HAL_MAX_LOG_LINE, + comment, + argp); + if (result < 0) + { + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + return halError; + } + + result = fprintf(logfd, + "%s\n", + logMessage); + if (result < 0) + { + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + return halError; + } + + result = fflush(logfd); + if (result < 0) + { + halError = (int32_t)ADI_HAL_LOGGING_FAIL; + return halError; + } + + halCfg->logCfg.currentLineNumber += 1; + } + + return halError; +} + +/** +* \brief Disables the LogWrite functionality by returning ADI_HAL_OK +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param logLevel the log level to be written into +* \param comment the string to include in the line added to the log. +* \param argp variable argument list to be printed +* +* \retval ADI_HAL_OK Function completed successfully, no action required +*/ +int32_t ucp2_LogWrite_NoAction(void* devHalCfg, + int32_t logLevel, + const char* comment, + va_list argp) +{ + (void)devHalCfg; + (void)logLevel; + (void)comment; + (void)argp; + + return ADI_HAL_OK; +} diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_logging.h b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_logging.h new file mode 100644 index 0000000..ea6bf02 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_logging.h @@ -0,0 +1,55 @@ +/** +* \file ucp2_logging.h +*/ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#ifndef _UCP2_LOGGING_H_ +#define _UCP2_LOGGING_H_ + +#include +#include +#include "adi_platform_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* +* Only allow log file to have MAX_NUM_LINES to prevent it from growing too large +* If max lines reached, start back at line 0. +* */ +#define UCP2_LOG_MAX_NUM_LINES 250000 + +int32_t ucp2_LogFileOpen(void* devHalCfg, + const char* filename); + +int32_t ucp2_LogFileFlush(void* devHalCfg); + +int32_t ucp2_LogFileClose(void* devHalCfg); + +int32_t ucp2_LogLevelSet(void* devHalCfg, + int32_t logLevel); + +int32_t ucp2_LogLevelGet(void* devHalCfg, + int32_t* logLevel); + +int32_t ucp2_LogWrite(void* devHalCfg, + int32_t logLevel, + const char* comment, + va_list argp); + +int32_t ucp2_LogWrite_NoAction(void* devHalCfg, + int32_t logLevel, + const char* comment, + va_list argp); + +#ifdef __cplusplus +} +#endif + +#endif /* _ucp2_LOGGING_H_ */ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_spi.c b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_spi.c new file mode 100644 index 0000000..6bdf0e7 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_spi.c @@ -0,0 +1,941 @@ +/** + * \file ucp2_spi.c + * Analog Devices ucp2 Platform + microzed hardware abstraction layer + * + * Copyright 2019 Analog Devices Inc. + * + * Support for linux layer SPI functions + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ucp2_spi.h" +#include "ucp2_bbic_control.h" +#include "ucp_jesd_gpio.h" +#include "ucp_rfic_gpio.h" +#include "ucp_api_rfic.h" + +static int spifd = 0, spiInited = 0; + +/** +* \brief Opens/allocates any necessary resources to communicate via SPI to a + particular device specified in the devHalCfg structure. +* +* This function should perform any necessary steps to open the SPI master resource +* on the BBIC to enable SPI communications to a particular SPI device. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the device driver was not opened successfully +*/ +int32_t ucp2_SpiOpen(void* devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + adi_hal_SpiCfg_t* spiCfg = NULL; + uint8_t boardType; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ucp2 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + spiCfg = &halCfg->spiCfg; + + if (spiCfg == NULL) + { + return ADI_HAL_NULL_PTR; + } + +#ifdef __GNUC__ + boardType = UCP_API_RFIC_GetBoardInfo(); + if ((HW_EVMT == boardType) || (HW_EVMF == boardType) || (HW_EVB == boardType)) + { + if (spiCfg->fd <= 0) + { + if (0 == spifd) { + spiCfg->fd = open(spiCfg->spidevName, O_RDWR); + spifd = spiCfg->fd; + } + else { + spiCfg->fd = spifd; + } + + if (spiCfg->fd < 0) + { + return ADI_HAL_SPI_FAIL; + } + } + } + else if (HW_EVMY == boardType) + { + spiCfg->fd = open(spiCfg->spidevName, O_RDWR); + if (spiCfg->fd < 0) + { + return ADI_HAL_SPI_FAIL; + } + } + else + { + printf("error, unknow spi config. @%s, %d\n", __FILE__, __LINE__); + } +#endif /* __GNUC__ */ + return halError; +} + +/** +* \brief Closes any resources open/allocated for a specific SPI device +* +* Any information needed to close the particular SPI device should be passed in +* the devHalCfg structure. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the device driver was not closed successfully +*/ +int32_t ucp2_SpiClose(void* devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + /* Cast void *devHalCfg structure to the specific structure for ucp2 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.spiActionDisable == 0) + { + if (halCfg->spiCfg.fd != 0) + { +#ifdef __GNUC__ + if (0 != spifd) + { + halError = close(halCfg->spiCfg.fd); + } + if (halError < 0) + { + return ADI_HAL_SPI_FAIL; + } +#endif /* __GNUC__ */ + + halCfg->spiCfg.fd = 0; + spifd = 0; + } + } + return halError; +} + +/** +* \brief Initializes the SPI device driver mode, bits per word, and speed +* +* Any settings needed should be passed in the devHalCfg structure +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the SPI initialization failed +*/ +int32_t ucp2_SpiInit(void* devHalCfg) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + uint8_t spiMode = 0; + uint32_t bitsPerWord = 0; + uint32_t speed = 0; + int32_t result = 0; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + if (spiInited) { + return ADI_HAL_OK; + } + spiInited = 1; + + /* Cast void *devHalCfg structure to the specific structure for ucp2 platform */ + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + /* Initialize SPI driver with clockrate, SPI mode, etc */ + if (halCfg->spiCfg.spiActionDisable == 0) + { + bitsPerWord = 8; + speed = halCfg->spiCfg.spiClkFreq_Hz; + + /*Get Chips SPI Driver File Descriptor*/ + if (halCfg->spiCfg.fd <= 0) + { + return ADI_HAL_SPI_FAIL; + } + + /* + * spi mode + */ + if ((halCfg->spiCfg.CPOL > 1) || (halCfg->spiCfg.CPHA > 1)) + { + /* + * Invalid SPI mode: CPOL and CPHA should be 1 or 0 + */ + return ADI_HAL_SPI_FAIL; + } + + spiMode = (halCfg->spiCfg.CPOL << 1) | halCfg->spiCfg.CPHA; + +#ifdef __GNUC__ + result = ioctl(halCfg->spiCfg.fd, + SPI_IOC_WR_MODE, + &spiMode); + if (result < 0) + { + /* + * Error settings requested SPI mode + */ + return ADI_HAL_SPI_FAIL; + } + + /* + * bits per word + */ + result = ioctl(halCfg->spiCfg.fd, + SPI_IOC_WR_BITS_PER_WORD, + &bitsPerWord); + if (result < 0) + { + /* + * Error setting the number of Bits per SPI word + */ + return ADI_HAL_SPI_FAIL; + } + + /* + * max speed hz + */ + result = ioctl(halCfg->spiCfg.fd, + SPI_IOC_WR_MAX_SPEED_HZ, + &speed); + if (result < 0) + { + /* + * Error Setting max SPI clock frequency for current chip select index. + */ + return ADI_HAL_SPI_FAIL; + } +#endif /* __GNUC__ */ + } /* If SPI hardware interface enabled */ + + return halError; +} + +static void transfer(int fd, uint8_t const *tx, uint8_t const *rx, size_t len) +{ + int ret; + static uint32_t mode = 0; + #define JUDGE(a, mask) (((a&mask) > 0)?'Y':'N') + struct spi_ioc_transfer tr = { + .tx_buf = (unsigned long)tx, + .rx_buf = (unsigned long)rx, + .len = len, + .delay_usecs = 100, + .speed_hz = 1000000, + .bits_per_word = 8, + }; + + if (mode & SPI_TX_OCTAL) + tr.tx_nbits = 8; + else if (mode & SPI_TX_QUAD) + tr.tx_nbits = 4; + else if (mode & SPI_TX_DUAL) + tr.tx_nbits = 2; + if (mode & SPI_RX_OCTAL) + tr.rx_nbits = 8; + else if (mode & SPI_RX_QUAD) + tr.rx_nbits = 4; + else if (mode & SPI_RX_DUAL) + tr.rx_nbits = 2; + if (!(mode & SPI_LOOP)) { + if (mode & (SPI_TX_OCTAL | SPI_TX_QUAD | SPI_TX_DUAL)) { + tr.rx_buf = 0; + } + else if (mode & (SPI_RX_OCTAL | SPI_RX_QUAD | SPI_RX_DUAL)) { + tr.tx_buf = 0; + } + } + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + if (ret < 1) + printf("can't send spi message @ %s %d\n", __FILE__, __LINE__); + + return; +} + +/** +* \brief Write an array of 8-bit data to a SPI device +* +* The function will write numTxBytes number of bytes to the SPI device +* selected in the devHalCfg structure. +* +* \dep_begin +* \dep{adi_hal_SpiCfg_t} +* \dep{adi_hal_SpiCfg_t->fd} +* \dep_end +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array txData buffer that has numTxBytes number of bytes +* \param numTxBytes The length of txData array +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not written successfully +*/ +int32_t ucp2_SpiWrite(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.spiActionDisable == 0) + { +#ifdef __GNUC__ + int32_t result = 0; + + if (halCfg->spiCfg.fd > 0) + { + result = write(halCfg->spiCfg.fd, + txData, + numTxBytes); + if (result <= 0) + { + halError = ADI_HAL_SPI_FAIL; + } + } + else + { + /* Invalid file descriptor */ + halError = ADI_HAL_SPI_FAIL; + } +#endif /* __GNUC__ */ + } + + return halError; +} + +/** +* \brief Write an array of 8-bit data to a SPI device +* +* The function will write numTxBytes number of bytes to the SPI device +* selected in the devHalCfg structure. + +* This function uses FPGA registers to manage spi transaction. It doesn't use spi device driver. +* +* \dep_begin +* \dep{adi_hal_SpiCfg_t} +* \dep{adi_hal_SpiCfg_t->fd} +* \dep_end +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array txData buffer that has numTxBytes number of bytes +* \param numTxBytes The length of txData array +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not written successfully +*/ +int32_t ucp2_SpiWrite_v2(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes) +{ + /* Calculate number of full FIFO transactions and remainder for last flush */ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + int pinIndex = 0; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + pinIndex = (SPI_CHIP_SELECT_0 == halCfg->spiCfg.chipSelectIndex) ? GPIO_INDEX_9025CS : GPIO_INDEX_9528CS; + ucp_jesd_gpioSet(pinIndex, 0); + + if (halCfg->spiCfg.spiActionDisable == 0) + { + transfer(halCfg->spiCfg.fd, txData, txData, numTxBytes); + } + + ucp_jesd_gpioSet(pinIndex, 1); + + return halError; +} + +/** +* \brief Write an array of 8-bit data to a SPI device +* +* The function will write numTxBytes number of bytes to the SPI device +* selected in the devHalCfg structure. +* +* This function uses FPGA registers to manage spi transaction. It doesn't use spi device driver. +* It implements the spi transfer sequence provided by XILINX DS742 document It's still under test. +* +* \dep_begin +* \dep{adi_hal_SpiCfg_t} +* \dep{adi_hal_SpiCfg_t->fd} +* \dep_end +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array txData buffer that has numTxBytes number of bytes +* \param numTxBytes The length of txData array +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not written successfully +*/ +int32_t ucp2_SpiWrite_v3(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes) +{ + static const uint16_t FPGA_FIFO_SIZE = 256; + static const uint32_t WAIT_FIFO_OCCUPANCY = 1024; + static const uint32_t SPI_CONTROL_REGISTER = 0x44A00060; + static const uint32_t SPI_TXFIFO_REGISTER = 0x44A00068; + static const uint32_t SPI_CS_REGISTER = 0x44A00070; + static const uint32_t SPI_TXFIFO_OCY_REGISTER = 0x44A00074; + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + uint32_t chipSelMask = 0xFFFFFFFF; //one hot active low active chip select + uint32_t i = 0; + uint32_t readData = 0; + uint16_t numOfChunks = 0; + uint16_t numFifoBytes = 0; + uint16_t remainder = 0; + uint16_t byteCounter = 0; + uint16_t k = 0; + + /* Calculate number of full FIFO transactions and remainder for last flush */ + remainder = numTxBytes % FPGA_FIFO_SIZE; + numOfChunks = (numTxBytes - remainder) / FPGA_FIFO_SIZE; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.spiActionDisable == 0) + { +# ifdef __GNUC__ + + /* This function requires access to advanced spi registers through BBIC */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_SPI) == ADI_HAL_BBIC_SPI)) + { + /* Reset Tx/Rx FIFO - Set Inhibit */ + halError = ucp2_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x1E4); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Write numOfChunks full chunks and remainder */ + numFifoBytes = FPGA_FIFO_SIZE; + for (k = 0; k < (numOfChunks + 1); k++) + { + /* If we're writing the remainder set numFifoBytes as remainder */ + if (k == numOfChunks) + { + numFifoBytes = remainder; + } + + for (i = 0; i < numFifoBytes; i++) + { + /* Write data bytes into Tx FIFO*/ + halError = ucp2_BbicRegisterWrite(devHalCfg, + SPI_TXFIFO_REGISTER, + (uint32_t)txData[byteCounter++]); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Enable SPI - Set Inhibit */ + halError = ucp2_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x186); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* CS low */ + chipSelMask = (0xFFFFFFFF & ~(1UL << halCfg->spiCfg.chipSelectIndex)); + halError = ucp2_BbicRegisterWrite(devHalCfg, + SPI_CS_REGISTER, + chipSelMask); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Clear Inhibit */ + halError = ucp2_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x86); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Wait until Tx FIFO is empty*/ + for (i = 0; i < WAIT_FIFO_OCCUPANCY; i++) + { + /* Read Tx FIFO Occupancy */ + halError = ucp2_BbicRegisterRead(devHalCfg, + SPI_TXFIFO_OCY_REGISTER, + &readData); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + if (readData == 0) + { + break; + } + + if (i == (WAIT_FIFO_OCCUPANCY - 1)) + { + /* Timeout */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Reset Tx/Rx FIFO - Set Inhibit */ + halError = ucp2_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x1E6); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* CS High */ + halError = ucp2_BbicRegisterWrite(devHalCfg, + SPI_CS_REGISTER, + 0xFFFFFFFF); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Disable SPI - Set Inhibit */ + halError = ucp2_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x1E4); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + else + { + /* Invalid file descriptor */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + +# endif /* __GNUC__ */ + } + + return halError; +} + +/** +* \brief Read one or more bytes from the device specified by the devHalCfg structure +* +* The function will read numTxRxBytes number of bytes from the SPI device selected in +* the devHalCfg parameter and store the resulting data sent by the device in the rxData +* data buffer. +* +* For each byte in txData written to the device, a byte is read and returned by this +* function at the pointer provided by the rxData parameter. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array that has numTxRxBytes number of bytes +* \param rxData Pointer to byte array where read back data will be returned, that is at least numTxRxBytes in size. +* \param numTxBytes The length of txData and rxData arrays +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not read successfully +*/ +int32_t ucp2_SpiRead(void* devHalCfg, + const uint8_t txData[], + uint8_t rxData[], + uint32_t numTxRxBytes) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + int32_t result = 0; + adi_hal_Cfg_t* halCfg = NULL; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.fd <= 0) + { + /* Invalid file descriptor */ + return ADI_HAL_SPI_FAIL; + } + + if (halCfg->spiCfg.spiActionDisable == 0) + { +#ifdef __GNUC__ + + /*Get device's SPI Driver File Descriptor*/ + struct spi_ioc_transfer tr = {0}; + + tr.tx_buf = (uintptr_t)&txData[0]; + tr.rx_buf = (uintptr_t)&rxData[0]; + tr.len = numTxRxBytes; + tr.delay_usecs = 0; + + result = ioctl(halCfg->spiCfg.fd, + SPI_IOC_MESSAGE(1), + &tr); + if (result <= 0) + { + halError = ADI_HAL_SPI_FAIL; + } +#endif /* __GNUC__ */ + } + + return halError; +} + +/** +* \brief Read one or more bytes from the device specified by the devHalCfg structure +* +* The function will read numTxRxBytes number of bytes from the SPI device selected in +* the devHalCfg parameter and store the resulting data sent by the device in the rxData +* data buffer. +* +* For each byte in txData written to the device, a byte is read and returned by this +* function at the pointer provided by the rxData parameter. +* +* This function uses FPGA registers to manage spi transaction. It doesn't use spi device driver. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array that has numTxRxBytes number of bytes +* \param rxData Pointer to byte array where read back data will be returned, that is at least numTxRxBytes in size. +* \param numTxBytes The length of txData and rxData arrays +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not read successfully +*/ +int32_t ucp2_SpiRead_v2(void* devHalCfg, + const uint8_t txData[], + uint8_t rxData[], + uint32_t numTxRxBytes) +{ + /* Calculate number of full FIFO transactions and remainder for last flush */ + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + int pinIndex; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + pinIndex = (SPI_CHIP_SELECT_0 == halCfg->spiCfg.chipSelectIndex) ? GPIO_INDEX_9025CS : GPIO_INDEX_9528CS; + ucp_jesd_gpioSet(pinIndex, 0); + + if (halCfg->spiCfg.spiActionDisable == 0) + { + transfer(halCfg->spiCfg.fd, txData, rxData, numTxRxBytes); + } + + ucp_jesd_gpioSet(pinIndex, 1); + return halError; +} + +/** +* \brief Read one or more bytes from the device specified by the devHalCfg structure +* +* The function will read numTxRxBytes number of bytes from the SPI device selected in +* the devHalCfg parameter and store the resulting data sent by the device in the rxData +* data buffer. +* +* For each byte in txData written to the device, a byte is read and returned by this +* function at the pointer provided by the rxData parameter. +* +* This function uses FPGA registers to manage spi transaction. It doesn't use spi device driver. +* It implements the spi transfer sequence provided by XILINX DS742 document It's still under test. +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param txData Pointer to byte array that has numTxRxBytes number of bytes +* \param rxData Pointer to byte array where read back data will be returned, that is at least numTxRxBytes in size. +* \param numTxBytes The length of txData and rxData arrays +* +* \retval ADI_HAL_OK function completed successfully, no action required +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +* \retval ADI_HAL_SPI_FAIL the data was not read successfully +*/ + +int32_t ucp2_SpiRead_v3(void* devHalCfg, + const uint8_t txData[], + uint8_t rxData[], + uint32_t numTxRxBytes) +{ + static const uint16_t FPGA_FIFO_SIZE = 256; + static const uint32_t WAIT_FIFO_OCCUPANCY = 1024; + static const uint32_t SPI_CONTROL_REGISTER = 0x44A00060; + static const uint32_t SPI_TXFIFO_REGISTER = 0x44A00068; + static const uint32_t SPI_RXFIFO_REGISTER = 0x44A0006C; + static const uint32_t SPI_CS_REGISTER = 0x44A00070; + static const uint32_t SPI_TXFIFO_OCY_REGISTER = 0x44A00074; + int32_t halError = (int32_t)ADI_HAL_OK; + adi_hal_Cfg_t* halCfg = NULL; + uint32_t chipSelMask = 0xFFFFFFFF; //one hot active low active chip select + uint32_t i = 0; + uint32_t readData = 0; + uint16_t numOfChunks = 0; + uint16_t numFifoBytes = 0; + uint16_t remainder = 0; + uint16_t txByteCounter = 0; + uint16_t rxByteCounter = 0; + uint16_t k = 0; + + /* Calculate number of full FIFO transactions and remainder for last flush */ + remainder = numTxRxBytes % FPGA_FIFO_SIZE; + numOfChunks = (numTxRxBytes - remainder) / FPGA_FIFO_SIZE; + + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + + halCfg = (adi_hal_Cfg_t *)devHalCfg; + + if (halCfg->spiCfg.spiActionDisable == 0) + { +# ifdef __GNUC__ + + /* This function requires access to advanced spi registers through BBIC */ + if (((halCfg->bbicCfg.interfaceEnabled & ADI_HAL_BBIC_SPI) == ADI_HAL_BBIC_SPI)) + { + /* Reset Tx/Rx FIFO - Set Inhibit */ + halError = ucp2_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x1E4); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Write numOfChunks full chunks and remainder */ + numFifoBytes = FPGA_FIFO_SIZE; + for (k = 0; k < (numOfChunks + 1); k++) + { + /* If we're writing the remainder set numFifoBytes as remainder */ + if (k == numOfChunks) + { + numFifoBytes = remainder; + } + + for (i = 0; i < numFifoBytes; i++) + { + /* Write data bytes into Tx FIFO*/ + halError = ucp2_BbicRegisterWrite(devHalCfg, + SPI_TXFIFO_REGISTER, + (uint32_t)txData[txByteCounter++]); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Enable SPI - Set Inhibit */ + halError = ucp2_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x186); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* CS low */ + chipSelMask = (0xFFFFFFFF & ~(1UL << halCfg->spiCfg.chipSelectIndex)); + halError = ucp2_BbicRegisterWrite(devHalCfg, + SPI_CS_REGISTER, + chipSelMask); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Clear Inhibit */ + halError = ucp2_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x86); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Wait until Tx FIFO is empty*/ + for (i = 0; i < WAIT_FIFO_OCCUPANCY; i++) + { + /* Read Tx FIFO Occupancy */ + halError = ucp2_BbicRegisterRead(devHalCfg, + SPI_TXFIFO_OCY_REGISTER, + &readData); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + if (readData == 0) + { + break; + } + + if (i == (WAIT_FIFO_OCCUPANCY - 1)) + { + /* Timeout */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + for (i = 0; i < numFifoBytes; i++) + { + /* Read data bytes from Rx FIFO*/ + uint32_t dataTmp = 0; + halError = ucp2_BbicRegisterRead(devHalCfg, + SPI_RXFIFO_REGISTER, + &dataTmp); + rxData[rxByteCounter++] = dataTmp & 0xFF; + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* Reset Tx/Rx FIFO - Set Inhibit */ + halError = ucp2_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x1E6); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + + /* CS High */ + halError = ucp2_BbicRegisterWrite(devHalCfg, + SPI_CS_REGISTER, + 0xFFFFFFFF); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + + /* Disable SPI - Set Inhibit */ + halError = ucp2_BbicRegisterWrite(devHalCfg, + SPI_CONTROL_REGISTER, + 0x1E4); + if (halError != (int32_t)ADI_HAL_OK) + { + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + } + else + { + /* Invalid file descriptor */ + halError = (int32_t)ADI_HAL_SPI_FAIL; + return halError; + } + +# endif /* __GNUC__ */ + } + + return halError; +} diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_spi.h b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_spi.h new file mode 100644 index 0000000..65a1bb3 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_spi.h @@ -0,0 +1,61 @@ +/** + * \file ucp2_spi.h + * Analog Devices ADS9 Platform + microzed hardware abstraction layer + * + * Copyright 2019 Analog Devices Inc. + * + * Support for linux layer SPI functions + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ +#ifndef __UCP2_SPI_H__ +#define __UCP2_SPI_H__ + +#include +#include "adi_platform_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t ucp2_SpiOpen(void* devHalCfg); + +int32_t ucp2_SpiClose(void* devHalCfg); + +int32_t ucp2_SpiInit(void* devHalCfg); + +int32_t ucp2_SpiWrite(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes); + +int32_t ucp2_SpiWrite_v2(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes); + +int32_t ucp2_SpiWrite_v3(void* devHalCfg, + const uint8_t txData[], + uint32_t numTxBytes); + +int32_t ucp2_SpiRead(void* devHalCfg, + const uint8_t txData[], + uint8_t rxData[], + uint32_t numTxRxBytes); + +int32_t ucp2_SpiRead_v2(void* devHalCfg, + const uint8_t txData[], + uint8_t rxData[], + uint32_t numTxRxBytes); + +int32_t ucp2_SpiRead_v3(void* devHalCfg, + const uint8_t txData[], + uint8_t rxData[], + uint32_t numTxRxBytes); + +#ifdef __cplusplus +} +#endif +#endif /* __UCP2_SPI_H__ */ diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_timer.c b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_timer.c new file mode 100644 index 0000000..914a8ae --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_timer.c @@ -0,0 +1,154 @@ +/** + * \file ucp2_timer.c + * Analog Devices ADS9 Platform + microzed hardware abstraction layer + * + * Copyright 2019 Analog Devices Inc. + * + * Support for linux layer timer functions + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ + +#include +#include +#include "ucp2_timer.h" + +/** +* \brief Function to open/allocate any necessary resources for the timer wait +* functions below. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ucp2_TimerOpen(void* devHalCfg) +{ + (void)(devHalCfg); + /* ADI ADS9 platform does not require any timer open /close */ + return (int32_t)ADI_HAL_OK; +} + +/** +* \brief Function to close any necessary resources for the timer wait +* functions below. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ucp2_TimerClose(void* devHalCfg) +{ + (void)(devHalCfg); + /* ADI ADS9 platform does not require any timer open /close */ + return (int32_t)ADI_HAL_OK; +} + +/** +* \brief Function to initialize any necessary resources for the timer wait +* functions below. +* +* \param devHalCfg Pointer to device instance specific platform settings +* +* \retval ADI_HAL_OK Function completed successfully +*/ +int32_t ucp2_TimerInit(void* devHalCfg) +{ + (void)(devHalCfg); + /* ADI ADS9 platform does not require any timer init */ + return (int32_t)ADI_HAL_OK; +} + +/** +* \brief Provides a blocking delay of the current thread +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param time_us the time to delay in mico seconds +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +*/ +int32_t ucp2_TimerWait_us(void* devHalCfg, + uint32_t time_us) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + +#ifdef __GNUC__ + (void)(devHalCfg); + struct timespec t0; + struct timespec t1; + struct timespec* temp; + struct timespec* waitTime = &t0; + struct timespec* remaining = &t1; + + waitTime->tv_sec = time_us / 1000000; + waitTime->tv_nsec = (time_us % 1000000) * (1000); + + do + { + halError = nanosleep(waitTime, + remaining); + temp = waitTime; + waitTime = remaining; + remaining = temp; + } + while ((halError == -1) && (errno == EINTR)); + +#else + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } + +#endif /* __GNUC__ */ + return halError; +} + +/** +* \brief Provides a blocking delay of the current thread +* +* \param devHalCfg Pointer to device instance specific platform settings +* \param time_ms the Time to delay in milli seconds +* +* \retval ADI_HAL_OK Function completed successfully +* \retval ADI_HAL_NULL_PTR the function has been called with a null pointer +*/ +int32_t ucp2_TimerWait_ms(void* devHalCfg, + uint32_t time_ms) +{ + int32_t halError = (int32_t)ADI_HAL_OK; + +#ifdef __GNUC__ + (void)(devHalCfg); + struct timespec t0; + struct timespec t1; + struct timespec* temp; + struct timespec* waitTime = &t0; + struct timespec* remaining = &t1; + + waitTime->tv_sec = time_ms / 1000; + waitTime->tv_nsec = (time_ms % 1000) * (1000000); + + do + { + halError = nanosleep(waitTime, + remaining); + temp = waitTime; + waitTime = remaining; + remaining = temp; + } + while ((halError == -1) && (errno == EINTR)); + +#else + if (devHalCfg == NULL) + { + halError = (int32_t)ADI_HAL_NULL_PTR; + return halError; + } +#endif /* __GNUC__ */ + return halError; +} diff --git a/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_timer.h b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_timer.h new file mode 100644 index 0000000..acf29c9 --- /dev/null +++ b/driver/rfic/rf/adrv9025/c_src/platforms/ucp2/ucp2_timer.h @@ -0,0 +1,40 @@ +/** + * \file ucp2_timer.h + * Analog Devices UCP2 Platform + microzed hardware abstraction layer + * + * Copyright 2019 Analog Devices Inc. + * + * Support for linux layer timer functions + */ + +/** +* Copyright 2015 - 2020 Analog Devices Inc. +* Released under the ADRV9025 API license, for more information. +* see the "LICENSE.pdf" file in this zip file. +*/ +#ifndef __UCP2_TIMER_H__ +#define __UCP2_TIMER_H__ + +#include +#include "adi_platform_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t ucp2_TimerOpen(void* devHalCfg); + +int32_t ucp2_TimerClose(void* devHalCfg); + +int32_t ucp2_TimerInit(void* devHalCfg); + +int32_t ucp2_TimerWait_ms(void* devHalCfg, + uint32_t time_ms); + +int32_t ucp2_TimerWait_us(void* devHalCfg, + uint32_t time_us); + +#ifdef __cplusplus +} +#endif +#endif /* __UCP2_TIMER_H__ */ diff --git a/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/ADRV9025_DPDCORE_FW.bin b/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/ADRV9025_DPDCORE_FW.bin new file mode 100644 index 0000000..84b5611 Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/ADRV9025_DPDCORE_FW.bin differ diff --git a/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/ADRV9025_FW.bin b/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/ADRV9025_FW.bin new file mode 100644 index 0000000..840d7b9 Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/ADRV9025_FW.bin differ diff --git a/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/stream_image_357E871D1928C2A67823336885ACA3E3.bin b/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/stream_image_357E871D1928C2A67823336885ACA3E3.bin new file mode 100644 index 0000000..e7f2676 Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/stream_image_357E871D1928C2A67823336885ACA3E3.bin differ diff --git a/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/stream_image_A765B7BD35316E73B32BCC926235B95A.bin b/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/stream_image_A765B7BD35316E73B32BCC926235B95A.bin new file mode 100644 index 0000000..a0148ea Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/stream_image_A765B7BD35316E73B32BCC926235B95A.bin differ diff --git a/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/stream_options_357E871D1928C2A67823336885ACA3E3.txt b/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/stream_options_357E871D1928C2A67823336885ACA3E3.txt new file mode 100644 index 0000000..132db96 --- /dev/null +++ b/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/stream_options_357E871D1928C2A67823336885ACA3E3.txt @@ -0,0 +1,51 @@ +{ + "OrxLink": 0, + "SwitchXbarOnORxLow": false, + "SwitchXbarOnRxLow": false, + "LinkSharingRx1": false, + "LinkSharingRx2": false, + "LinkSharingRx3": false, + "LinkSharingRx4": false, + "LinkSharingORx": false, + "DualORxChannel": true, + "LinkSharingRxOrxSameRate": false, + "DummyRead": true, + "KeepRxEnableHighForAGC": false, + "ExternalDpdEnabled": false, + "LateMaskingOfFrmData": false, + "CfrDelay": 255, + "OrxTiaOn": false, + "OrxAdcOn": false, + "EnableAllLanesInORxMode": false, + "CustomDataOrderingOrx1": false, + "CustomDataOrderingOrx2": false, + "ORx1AdcSmplXBar": "AAECAwQFBgcICQoLDA0ODxAREhM=", + "ORx2AdcSmplXBar": "AAECAwQFBgcICQoLDA0ODxAREhM=", + "DefaultTxToORxMapping12": 50, + "DefaultTxToORxMapping34": 50, + "OrxGainCtrlMode2To2": false, + "OrxGainCtrlMode4To1": false, + "OrxGainCtrlSideOrx12": true, + "StopExtTimerForDpdCap": false, + "Gpio0Selection": 255, + "Gpio1Selection": 255, + "Gpio2Selection": 255, + "Gpio3Selection": 255, + "Gpio4Selection": 255, + "Gpio5Selection": 255, + "Gpio6Selection": 255, + "Gpio7Selection": 255, + "Gpio8Selection": 255, + "Gpio9Selection": 255, + "Gpio10Selection": 255, + "Gpio11Selection": 255, + "Gpio12Selection": 255, + "Gpio13Selection": 255, + "Gpio14Selection": 255, + "Gpio15Selection": 255, + "CaptureDelay1": 1, + "CaptureDelay2": 1, + "CaptureDelay3": 1, + "DpdModelSwitchDelay": 49402, + "CoreStmExtTimerWait": 360 +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/stream_options_A765B7BD35316E73B32BCC926235B95A.txt b/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/stream_options_A765B7BD35316E73B32BCC926235B95A.txt new file mode 100644 index 0000000..9525700 --- /dev/null +++ b/driver/rfic/rf/adrv9025/resources/adrv9025/arm_firmware/stream_options_A765B7BD35316E73B32BCC926235B95A.txt @@ -0,0 +1,51 @@ +{ + "OrxLink": 1, + "SwitchXbarOnORxLow": true, + "SwitchXbarOnRxLow": false, + "LinkSharingRx1": false, + "LinkSharingRx2": false, + "LinkSharingRx3": false, + "LinkSharingRx4": false, + "LinkSharingORx": false, + "DualORxChannel": false, + "LinkSharingRxOrxSameRate": false, + "DummyRead": true, + "KeepRxEnableHighForAGC": true, + "ExternalDpdEnabled": false, + "LateMaskingOfFrmData": false, + "CfrDelay": 255, + "OrxTiaOn": false, + "OrxAdcOn": false, + "EnableAllLanesInORxMode": false, + "CustomDataOrderingOrx1": false, + "CustomDataOrderingOrx2": false, + "ORx1AdcSmplXBar": "AAECAwQFBgcICQoLDA0ODxAREhM=", + "ORx2AdcSmplXBar": "AAECAwQFBgcICQoLDA0ODxAREhM=", + "DefaultTxToORxMapping12": 50, + "DefaultTxToORxMapping34": 50, + "OrxGainCtrlMode2To2": false, + "OrxGainCtrlMode4To1": false, + "OrxGainCtrlSideOrx12": true, + "StopExtTimerForDpdCap": false, + "Gpio0Selection": 9, + "Gpio1Selection": 255, + "Gpio2Selection": 255, + "Gpio3Selection": 255, + "Gpio4Selection": 255, + "Gpio5Selection": 10, + "Gpio6Selection": 255, + "Gpio7Selection": 255, + "Gpio8Selection": 255, + "Gpio9Selection": 255, + "Gpio10Selection": 255, + "Gpio11Selection": 255, + "Gpio12Selection": 255, + "Gpio13Selection": 255, + "Gpio14Selection": 255, + "Gpio15Selection": 255, + "CaptureDelay1": 1, + "CaptureDelay2": 1, + "CaptureDelay3": 1, + "DpdModelSwitchDelay": 49402, + "CoreStmExtTimerWait": 360 +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/resources/adrv9025/gain_tables/RxGainTable.csv b/driver/rfic/rf/adrv9025/resources/adrv9025/gain_tables/RxGainTable.csv new file mode 100644 index 0000000..e27e0cb --- /dev/null +++ b/driver/rfic/rf/adrv9025/resources/adrv9025/gain_tables/RxGainTable.csv @@ -0,0 +1,257 @@ +Gain Index,FE Control Word,TIA Control,ADC Control,Ext Control,Phase Offset,Digital Gain +0,0,0,0,0,0,0 +1,0,0,0,0,0,0 +2,0,0,0,0,0,0 +3,0,0,0,0,0,0 +4,0,0,0,0,0,0 +5,0,0,0,0,0,0 +6,0,0,0,0,0,0 +7,0,0,0,0,0,0 +8,0,0,0,0,0,0 +9,0,0,0,0,0,0 +10,0,0,0,0,0,0 +11,0,0,0,0,0,0 +12,0,0,0,0,0,0 +13,0,0,0,0,0,0 +14,0,0,0,0,0,0 +15,0,0,0,0,0,0 +16,0,0,0,0,0,0 +17,0,0,0,0,0,0 +18,0,0,0,0,0,0 +19,0,0,0,0,0,0 +20,0,0,0,0,0,0 +21,0,0,0,0,0,0 +22,0,0,0,0,0,0 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0, + 0 + ], + "OrxChannel1Index": 0, + "OrxChannel2Index": 0 + } +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/resources/adrv9025/profiles/ActiveUtilInit.profile b/driver/rfic/rf/adrv9025/resources/adrv9025/profiles/ActiveUtilInit.profile new file mode 100644 index 0000000..88f52c6 --- /dev/null +++ b/driver/rfic/rf/adrv9025/resources/adrv9025/profiles/ActiveUtilInit.profile @@ -0,0 +1,56 @@ +{ + "radioCtrlInit": { + "radioCtrlModeCfg": { + "txRadioCtrlModeCfg": { + "txEnableMode": 0, + "txChannelMask": 15 + }, + "rxRadioCtrlModeCfg": { + "rxEnableMode": 0, + "rxChannelMask": 255 + }, + "orxRadioCtrlModeCfg": { + "orxEnableMode": 0, + "orxPinSelectSettlingDelay_armClkCycles": 0, + "singleChannel1PinModeOrxSel": 0, + "singleChannel2PinModeLowOrxSel": 0, + "singleChannel2PinModeHighOrxSel": 0, + "dualChannel2PinModeOrxSel": 0 + } + }, + "txToOrxMapping": { + "orx1Map": 2, + "orx2Map": 3, + "orx3Map": 2, + "orx4Map": 3 + }, + "streamGpioCfg": { + "streamGpInput0": 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a/driver/rfic/rf/adrv9025/resources/configure/ucp_rfic_cfg_evmt.json b/driver/rfic/rf/adrv9025/resources/configure/ucp_rfic_cfg_evmt.json new file mode 100644 index 0000000..582e4f0 --- /dev/null +++ b/driver/rfic/rf/adrv9025/resources/configure/ucp_rfic_cfg_evmt.json @@ -0,0 +1,25 @@ +{ + "common": { + "txLo": 2566890000, + "rxLo": 2566890000, + "auxLo": 0, + "initAtt": 0, + "initGain": 255 + }, + "para": { + "sampleRate": 122880000, + "bw": 100000000, + "antNumb": 4, + "enFdd": 0, + "enOrx": 0, + "en204C": 0, + "enUcpLog": 0, + "calOrxGainIndex": 240, + "calChAttPara": { + "ch1": 15000, + "ch2": 14500, + "ch3": 14500, + "ch4": 16450 + } + } +} diff --git a/driver/rfic/rf/adrv9025/resources/configure/ucp_trx_gpioCfg_evb_2.0.json b/driver/rfic/rf/adrv9025/resources/configure/ucp_trx_gpioCfg_evb_2.0.json new file mode 100644 index 0000000..a7a24e0 --- /dev/null +++ b/driver/rfic/rf/adrv9025/resources/configure/ucp_trx_gpioCfg_evb_2.0.json @@ -0,0 +1,128 @@ +{ + "common": { + "board": "EVB", + "version": 2, + "maxCh": 4, + "devClkSrc": 2, + "uldelay": 0, + "dldelay": 0, + "lvdsCoupling": "AC" + }, + "config": [{ + "tx_trx_port": 0, + "tx_trx_pin": 0, + "tx_trx_enableLevel": 0, + "tx_rf_port": 3, + "tx_rf_pin": 12, + "tx_rf_enableLevel": 2, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 0, + "rx_trx_pin": 0, + "rx_trx_enableLevel": 0, + "rx_rf_port": 3, + "rx_rf_pin": 17, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 21, + "orx_trx_enableLevel": 1, + "orx_rf_port": 0, + "orx_rf_pin": 0, + "orx_rf_enableLevel": 0, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "tx_trx_port": 0, + "tx_trx_pin": 0, + "tx_trx_enableLevel": 0, + "tx_rf_port": 3, + "tx_rf_pin": 13, + "tx_rf_enableLevel": 2, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 0, + "rx_trx_pin": 0, + "rx_trx_enableLevel": 0, + "rx_rf_port": 3, + "rx_rf_pin": 16, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 20, + "orx_trx_enableLevel": 1, + "orx_rf_port": 0, + "orx_rf_pin": 0, + "orx_rf_enableLevel": 0, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "tx_trx_port": 0, + "tx_trx_pin": 0, + "tx_trx_enableLevel": 0, + "tx_rf_port": 3, + "tx_rf_pin": 15, + "tx_rf_enableLevel": 2, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 0, + "rx_trx_pin": 0, + "rx_trx_enableLevel": 0, + "rx_rf_port": 3, + "rx_rf_pin": 19, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 23, + "orx_trx_enableLevel": 1, + "orx_rf_port": 0, + "orx_rf_pin": 0, + "orx_rf_enableLevel": 0, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "tx_trx_port": 0, + "tx_trx_pin": 0, + "tx_trx_enableLevel": 0, + "tx_rf_port": 3, + "tx_rf_pin": 14, + "tx_rf_enableLevel": 2, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 0, + "rx_trx_pin": 0, + "rx_trx_enableLevel": 0, + "rx_rf_port": 3, + "rx_rf_pin": 18, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 22, + "orx_trx_enableLevel": 1, + "orx_rf_port": 0, + "orx_rf_pin": 0, + "orx_rf_enableLevel": 0, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "triger_port": 3, + "triger_pin": 25, + "triger_enableLevel": 1 + }] +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/resources/configure/ucp_trx_gpioCfg_evmf_2.0.json b/driver/rfic/rf/adrv9025/resources/configure/ucp_trx_gpioCfg_evmf_2.0.json new file mode 100644 index 0000000..c7a4407 --- /dev/null +++ b/driver/rfic/rf/adrv9025/resources/configure/ucp_trx_gpioCfg_evmf_2.0.json @@ -0,0 +1,128 @@ +{ + "common": { + "board": "EVMF", + "version": 2, + "maxCh": 4, + "devClkSrc": 2, + "uldelay": 0, + "dldelay": 0, + "lvdsCoupling": "AC" + }, + "config": [{ + "tx_trx_port": 3, + "tx_trx_pin": 5, + "tx_trx_enableLevel": 1, + "tx_rf_port": 3, + "tx_rf_pin": 17, + "tx_rf_enableLevel": 1, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 3, + "rx_trx_pin": 9, + "rx_trx_enableLevel": 1, + "rx_rf_port": 3, + "rx_rf_pin": 21, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 13, + "orx_trx_enableLevel": 0, + "orx_rf_port": 0, + "orx_rf_pin": 0, + "orx_rf_enableLevel": 0, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "tx_trx_port": 3, + "tx_trx_pin": 4, + "tx_trx_enableLevel": 1, + "tx_rf_port": 3, + "tx_rf_pin": 16, + "tx_rf_enableLevel": 1, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 3, + "rx_trx_pin": 8, + "rx_trx_enableLevel": 1, + "rx_rf_port": 3, + "rx_rf_pin": 20, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 12, + "orx_trx_enableLevel": 0, + "orx_rf_port": 0, + "orx_rf_pin": 0, + "orx_rf_enableLevel": 0, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "tx_trx_port": 3, + "tx_trx_pin": 7, + "tx_trx_enableLevel": 1, + "tx_rf_port": 3, + "tx_rf_pin": 19, + "tx_rf_enableLevel": 1, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 3, + "rx_trx_pin": 11, + "rx_trx_enableLevel": 1, + "rx_rf_port": 3, + "rx_rf_pin": 23, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 15, + "orx_trx_enableLevel": 0, + "orx_rf_port": 0, + "orx_rf_pin": 0, + "orx_rf_enableLevel": 0, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "tx_trx_port": 3, + "tx_trx_pin": 6, + "tx_trx_enableLevel": 1, + "tx_rf_port": 3, + "tx_rf_pin": 18, + "tx_rf_enableLevel": 1, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 3, + "rx_trx_pin": 10, + "rx_trx_enableLevel": 1, + "rx_rf_port": 3, + "rx_rf_pin": 22, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 14, + "orx_trx_enableLevel": 0, + "orx_rf_port": 0, + "orx_rf_pin": 0, + "orx_rf_enableLevel": 0, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "triger_port": 3, + "triger_pin": 28, + "triger_enableLevel": 1 + }] +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/resources/configure/ucp_trx_gpioCfg_evmt_2.0.json b/driver/rfic/rf/adrv9025/resources/configure/ucp_trx_gpioCfg_evmt_2.0.json new file mode 100644 index 0000000..ba05d28 --- /dev/null +++ b/driver/rfic/rf/adrv9025/resources/configure/ucp_trx_gpioCfg_evmt_2.0.json @@ -0,0 +1,128 @@ +{ + "common": { + "board": "EVMT", + "version": 2, + "maxCh": 4, + "devClkSrc": 2, + "uldelay": 0, + "dldelay": 0, + "lvdsCoupling": "AC" + }, + "config": [{ + "tx_trx_port": 3, + "tx_trx_pin": 5, + "tx_trx_enableLevel": 1, + "tx_rf_port": 3, + "tx_rf_pin": 17, + "tx_rf_enableLevel": 1, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 3, + "rx_trx_pin": 9, + "rx_trx_enableLevel": 1, + "rx_rf_port": 3, + "rx_rf_pin": 26, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 13, + "orx_trx_enableLevel": 1, + "orx_rf_port": 3, + "orx_rf_pin": 1, + "orx_rf_enableLevel": 1, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "tx_trx_port": 3, + "tx_trx_pin": 4, + "tx_trx_enableLevel": 1, + "tx_rf_port": 3, + "tx_rf_pin": 16, + "tx_rf_enableLevel": 1, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 3, + "rx_trx_pin": 8, + "rx_trx_enableLevel": 1, + "rx_rf_port": 3, + "rx_rf_pin": 26, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 12, + "orx_trx_enableLevel": 1, + "orx_rf_port": 3, + "orx_rf_pin": 0, + "orx_rf_enableLevel": 1, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "tx_trx_port": 3, + "tx_trx_pin": 7, + "tx_trx_enableLevel": 1, + "tx_rf_port": 3, + "tx_rf_pin": 19, + "tx_rf_enableLevel": 1, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 3, + "rx_trx_pin": 11, + "rx_trx_enableLevel": 1, + "rx_rf_port": 3, + "rx_rf_pin": 27, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 15, + "orx_trx_enableLevel": 1, + "orx_rf_port": 0, + "orx_rf_pin": 0, + "orx_rf_enableLevel": 0, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "tx_trx_port": 3, + "tx_trx_pin": 6, + "tx_trx_enableLevel": 1, + "tx_rf_port": 3, + "tx_rf_pin": 18, + "tx_rf_enableLevel": 1, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 3, + "rx_trx_pin": 10, + "rx_trx_enableLevel": 1, + "rx_rf_port": 3, + "rx_rf_pin": 27, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 14, + "orx_trx_enableLevel": 1, + "orx_rf_port": 0, + "orx_rf_pin": 0, + "orx_rf_enableLevel": 0, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "triger_port": 3, + "triger_pin": 28, + "triger_enableLevel": 1 + }] +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/resources/configure/ucp_trx_gpioCfg_evmy_2.0.json b/driver/rfic/rf/adrv9025/resources/configure/ucp_trx_gpioCfg_evmy_2.0.json new file mode 100644 index 0000000..b94d7b7 --- /dev/null +++ b/driver/rfic/rf/adrv9025/resources/configure/ucp_trx_gpioCfg_evmy_2.0.json @@ -0,0 +1,128 @@ +{ + "common": { + "board": "EVMY", + "version": 2, + "maxCh": 4, + "devClkSrc": 2, + "uldelay": 0, + "dldelay": 0, + "lvdsCoupling": "AC" + }, + "config": [{ + "tx_trx_port": 3, + "tx_trx_pin": 17, + "tx_trx_enableLevel": 1, + "tx_rf_port": 3, + "tx_rf_pin": 5, + "tx_rf_enableLevel": 1, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 3, + "rx_trx_pin": 21, + "rx_trx_enableLevel": 1, + "rx_rf_port": 3, + "rx_rf_pin": 24, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 0, + "orx_trx_pin": 0, + "orx_trx_enableLevel": 0, + "orx_rf_port": 3, + "orx_rf_pin": 29, + "orx_rf_enableLevel": 1, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "tx_trx_port": 3, + "tx_trx_pin": 16, + "tx_trx_enableLevel": 1, + "tx_rf_port": 3, + "tx_rf_pin": 4, + "tx_rf_enableLevel": 1, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 3, + "rx_trx_pin": 20, + "rx_trx_enableLevel": 1, + "rx_rf_port": 3, + "rx_rf_pin": 24, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 0, + "orx_trx_pin": 0, + "orx_trx_enableLevel": 0, + "orx_rf_port": 3, + "orx_rf_pin": 29, + "orx_rf_enableLevel": 1, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "tx_trx_port": 3, + "tx_trx_pin": 19, + "tx_trx_enableLevel": 1, + "tx_rf_port": 3, + "tx_rf_pin": 7, + "tx_rf_enableLevel": 1, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 3, + "rx_trx_pin": 23, + "rx_trx_enableLevel": 1, + "rx_rf_port": 3, + "rx_rf_pin": 25, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 22, + "orx_trx_enableLevel": 1, + "orx_rf_port": 3, + "orx_rf_pin": 30, + "orx_rf_enableLevel": 1, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "tx_trx_port": 3, + "tx_trx_pin": 18, + "tx_trx_enableLevel": 1, + "tx_rf_port": 3, + "tx_rf_pin": 6, + "tx_rf_enableLevel": 1, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 3, + "rx_trx_pin": 22, + "rx_trx_enableLevel": 1, + "rx_rf_port": 3, + "rx_rf_pin": 25, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 0, + "orx_trx_pin": 0, + "orx_trx_enableLevel": 0, + "orx_rf_port": 3, + "orx_rf_pin": 30, + "orx_rf_enableLevel": 1, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "triger_port": 3, + "triger_pin": 8, + "triger_enableLevel": 1 + }] +} \ No newline at end of file diff --git a/driver/rfic/rf/adrv9025/resources/csubin/256QAM/256QAM.bmp b/driver/rfic/rf/adrv9025/resources/csubin/256QAM/256QAM.bmp new file mode 100644 index 0000000..fbcedf7 Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/csubin/256QAM/256QAM.bmp differ diff --git a/driver/rfic/rf/adrv9025/resources/csubin/256QAM/ape_spu0.out b/driver/rfic/rf/adrv9025/resources/csubin/256QAM/ape_spu0.out new file mode 100644 index 0000000..58800bb Binary files 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a/driver/rfic/rf/adrv9025/resources/csubin/256QAM/pet_rfm_spu0.out b/driver/rfic/rf/adrv9025/resources/csubin/256QAM/pet_rfm_spu0.out new file mode 100644 index 0000000..f0f6e01 Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/csubin/256QAM/pet_rfm_spu0.out differ diff --git a/driver/rfic/rf/adrv9025/resources/csubin/256QAM/pet_rfm_spu1.out b/driver/rfic/rf/adrv9025/resources/csubin/256QAM/pet_rfm_spu1.out new file mode 100644 index 0000000..e3c7f7d Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/csubin/256QAM/pet_rfm_spu1.out differ diff --git a/driver/rfic/rf/adrv9025/resources/csubin/256QAM/start_jesd_test.sh b/driver/rfic/rf/adrv9025/resources/csubin/256QAM/start_jesd_test.sh new file mode 100644 index 0000000..a66e19b --- /dev/null +++ b/driver/rfic/rf/adrv9025/resources/csubin/256QAM/start_jesd_test.sh @@ -0,0 +1,45 @@ +echo start!!! +chmod -R 777 . + +ls -l + +echo start loading ape rfm!!! + +loadelf -ape ape_spu0.out 0 1 +usleep 30 + +loadelf -ape ape_spu1.out 1 1 +usleep 30 + +loadelf -ape ape_spu2.out 2 1 +usleep 30 + +loadelf -ape ape_spu3.out 3 1 +usleep 30 + +loadelf -ape ape_spu0.out 4 1 +usleep 30 + +loadelf -ape ape_spu1.out 5 1 +usleep 30 + +loadelf -ape ape_spu2.out 6 1 +usleep 30 + +loadelf -ape ape_spu3.out 7 1 +usleep 30 + +loadelf -rfm pet_rfm_spu1.out 1 1 +usleep 30 + +loadelf -rfm ecs_rfm_spu0.out 2 1 +usleep 30 + +loadelf -rfm ecs_rfm_spu1.out 3 1 +usleep 30 + +chmod 777 ./rfic.out +./rfic.out + +chmod 777 ./msgtransfer.out +./msgtransfer.out diff --git a/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu0.out b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu0.out new file mode 100644 index 0000000..41ca3c0 Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu0.out differ diff --git a/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu1.out b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu1.out new file mode 100644 index 0000000..3a1a191 Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu1.out differ diff --git a/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu2.out b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu2.out new file mode 100644 index 0000000..465657b Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu2.out differ diff --git a/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu3.out b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu3.out new file mode 100644 index 0000000..7adab33 Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu3.out differ diff --git a/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu4.out b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu4.out new file mode 100644 index 0000000..d73041d Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu4.out differ diff --git a/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu5.out b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu5.out new file mode 100644 index 0000000..14628fa Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu5.out differ diff --git a/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu6.out b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu6.out new file mode 100644 index 0000000..1507390 Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu6.out differ diff --git a/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu7.out b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu7.out new file mode 100644 index 0000000..d7b5b47 Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ape_spu7.out differ diff --git a/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ecs_rfm_spu0.out b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ecs_rfm_spu0.out new file mode 100644 index 0000000..0ab705d Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ecs_rfm_spu0.out differ diff --git a/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ecs_rfm_spu1.out b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ecs_rfm_spu1.out new file mode 100644 index 0000000..ac46722 Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/ecs_rfm_spu1.out differ diff --git a/driver/rfic/rf/adrv9025/resources/csubin/orx_out/msgtransfer_jesd_orx.out b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/msgtransfer_jesd_orx.out new file mode 100644 index 0000000..ead9ab8 Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/msgtransfer_jesd_orx.out differ diff --git a/driver/rfic/rf/adrv9025/resources/csubin/orx_out/pet_rfm_spu0.out b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/pet_rfm_spu0.out new file mode 100644 index 0000000..eaf7ef6 Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/pet_rfm_spu0.out differ diff --git a/driver/rfic/rf/adrv9025/resources/csubin/orx_out/pet_rfm_spu1.out b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/pet_rfm_spu1.out new file mode 100644 index 0000000..c95147e Binary files /dev/null and b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/pet_rfm_spu1.out differ diff --git a/driver/rfic/rf/adrv9025/resources/csubin/orx_out/start_jesd_orx_test.sh b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/start_jesd_orx_test.sh new file mode 100644 index 0000000..a161b85 --- /dev/null +++ b/driver/rfic/rf/adrv9025/resources/csubin/orx_out/start_jesd_orx_test.sh @@ -0,0 +1,48 @@ +echo start!!! +chmod -R 777 . + +ls -l + +echo start loading ape rfm!!! + +loadelf -ape ape_spu0.out 0 1 +usleep 30 + +loadelf -ape ape_spu1.out 1 1 +usleep 30 + +loadelf -ape ape_spu2.out 2 1 +usleep 30 + +loadelf -ape ape_spu3.out 3 1 +usleep 30 + +loadelf -ape ape_spu0.out 4 1 +usleep 30 + +loadelf -ape ape_spu1.out 5 1 +usleep 30 + +loadelf -ape ape_spu2.out 6 1 +usleep 30 + +loadelf -ape ape_spu3.out 7 1 +usleep 30 + +loadelf -rfm pet_rfm_spu1.out 1 1 +usleep 30 + +loadelf -rfm ecs_rfm_spu0.out 2 1 +usleep 30 + +loadelf -rfm ecs_rfm_spu1.out 3 1 +usleep 30 + +chmod 777 ./rfic.out +./rfic.out + +chmod 777 ./msgtransfer_jesd_orx.out +./msgtransfer_jesd_orx.out + +chmod 777 ./stc_ublox.out +./stc_ublox.out diff --git a/driver/rfic/rf/adrv9025/resources/ucp_rfic_cfg.json b/driver/rfic/rf/adrv9025/resources/ucp_rfic_cfg.json new file mode 100644 index 0000000..5317cdd --- /dev/null +++ b/driver/rfic/rf/adrv9025/resources/ucp_rfic_cfg.json @@ -0,0 +1,25 @@ +{ + "common": { + "txLo": 2566890000, + "rxLo": 2566890000, + "auxLo": 0, + "initAtt": 0, + "initGain": 255 + }, + "para": { + "sampleRate": 122880000, + "bw": 100000000, + "antNumb": 4, + "enFdd": 0, + "enOrx": 0, + "en204C": 0, + "enUcpLog": 0, + "calOrxGainIndex": 240, + "calChAttPara": { + "ch1": 15000, + "ch2": 14500, + "ch3": 14500, + "ch4": 16450 + } + } +} diff --git a/driver/rfic/rf/adrv9025/resources/ucp_trx_gpioCfg.json b/driver/rfic/rf/adrv9025/resources/ucp_trx_gpioCfg.json new file mode 100644 index 0000000..ba05d28 --- /dev/null +++ b/driver/rfic/rf/adrv9025/resources/ucp_trx_gpioCfg.json @@ -0,0 +1,128 @@ +{ + "common": { + "board": "EVMT", + "version": 2, + "maxCh": 4, + "devClkSrc": 2, + "uldelay": 0, + "dldelay": 0, + "lvdsCoupling": "AC" + }, + "config": [{ + "tx_trx_port": 3, + "tx_trx_pin": 5, + "tx_trx_enableLevel": 1, + "tx_rf_port": 3, + "tx_rf_pin": 17, + "tx_rf_enableLevel": 1, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 3, + "rx_trx_pin": 9, + "rx_trx_enableLevel": 1, + "rx_rf_port": 3, + "rx_rf_pin": 26, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 13, + "orx_trx_enableLevel": 1, + "orx_rf_port": 3, + "orx_rf_pin": 1, + "orx_rf_enableLevel": 1, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "tx_trx_port": 3, + "tx_trx_pin": 4, + "tx_trx_enableLevel": 1, + "tx_rf_port": 3, + "tx_rf_pin": 16, + "tx_rf_enableLevel": 1, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 3, + "rx_trx_pin": 8, + "rx_trx_enableLevel": 1, + "rx_rf_port": 3, + "rx_rf_pin": 26, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 12, + "orx_trx_enableLevel": 1, + "orx_rf_port": 3, + "orx_rf_pin": 0, + "orx_rf_enableLevel": 1, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "tx_trx_port": 3, + "tx_trx_pin": 7, + "tx_trx_enableLevel": 1, + "tx_rf_port": 3, + "tx_rf_pin": 19, + "tx_rf_enableLevel": 1, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 3, + "rx_trx_pin": 11, + "rx_trx_enableLevel": 1, + "rx_rf_port": 3, + "rx_rf_pin": 27, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 15, + "orx_trx_enableLevel": 1, + "orx_rf_port": 0, + "orx_rf_pin": 0, + "orx_rf_enableLevel": 0, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "tx_trx_port": 3, + "tx_trx_pin": 6, + "tx_trx_enableLevel": 1, + "tx_rf_port": 3, + "tx_rf_pin": 18, + "tx_rf_enableLevel": 1, + "tx_sw_port": 0, + "tx_sw_pin": 0, + "tx_sw_enableLevel": 0, + "rx_trx_port": 3, + "rx_trx_pin": 10, + "rx_trx_enableLevel": 1, + "rx_rf_port": 3, + "rx_rf_pin": 27, + "rx_rf_enableLevel": 2, + "rx_sw_port": 0, + "rx_sw_pin": 0, + "rx_sw_enableLevel": 0, + "orx_trx_port": 3, + "orx_trx_pin": 14, + "orx_trx_enableLevel": 1, + "orx_rf_port": 0, + "orx_rf_pin": 0, + "orx_rf_enableLevel": 0, + "orx_sw_port": 0, + "orx_sw_pin": 0, + "orx_sw_enableLevel": 0 + }, { + "triger_port": 3, + "triger_pin": 28, + "triger_enableLevel": 1 + }] +} \ No newline at end of file diff --git a/driver/rfic/rf/api/inc/ucp_api_rfic.h b/driver/rfic/rf/api/inc/ucp_api_rfic.h new file mode 100644 index 0000000..5379255 --- /dev/null +++ b/driver/rfic/rf/api/inc/ucp_api_rfic.h @@ -0,0 +1,267 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_api_rfic.h +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-03-04 17:39:00 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef UCP_API_RFIC_H_ +#define UCP_API_RFIC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief define board type + */ + enum { + HW_UNKNOW = 0, + HW_EVMT, + HW_EVMF, + HW_EVB, + HW_EVMY, + HW_OTHER = 254, + HW_MAX = 255 +}; + +/** + * \brief define some paras for cell init + */ +enum { + CFG_SAMPLERATE_61_44MHZ = 61440000, + CFG_SAMPLERATE_122_88MHZ = 122880000, + CFG_SAMPLERATE_245_76MHZ = 245760000 +}; + +enum { + CFG_BW_20MHZ = 20000000, + CFG_BW_50MHZ = 50000000, + CFG_BW_100MHZ = 100000000, + CFG_BW_200MHZ = 200000000, + CFG_BW_240MHZ = 240000000 +}; + +enum { + CFG_1ANT = 1, + CFG_2ANT = 2, + CFG_3ANT = 3, + CFG_4ANT = 4, + CFG_5ANT = 5, + CFG_6ANT = 6, + CFG_7ANT = 7, + CFG_8ANT = 8 +}; + +enum { + CFG_TDD = 0, + CFG_FDD = 1 +}; + +enum { + CFG_NORX = 0, + CFG_TLO_ORX = 1, + CFG_ALO_ORX = 2, + CFG_RLO_ORX = 3 +}; + +enum { + CFG_204B= 0, + CFG_204C = 1 +}; + +enum { + CFG_NONE_LOG = 0, + CFG_LOG = 1 +}; + +/** + * \brief define cal para struct + */ + +typedef struct ucp_rfic_calPara +{ + int16_t calOrxGainIndex; + int16_t calChAttPara[16]; +} ucp_rfic_calPara_t; + +//********************************************************************************** +// system option layer +/** +* \brief Sets up the cell's default config +* +* \param sampleRate is Transceiver's sample Rate (Unit hz. 122.88Mhz 245.76Mhz or 61.44Mhz). +* \param bw is bandwidth (Unit hz). +* \param antNumb is the number of antennas (range 1 ~ 8). +* \param enFdd (0: TDD mode, 1: FDD mode). +* \param enOrx (0: disable orx, 1: orx Lo follows Tx Lo, 2: orx Lo follows aux Lo). +* \param en204C(0: 204B mode, 1: 204C mode). +* \param enUcpLog(0: disable configture Log, 1: enable configture Log). +* +* \retval 0. +*/ +extern int32_t UCP_API_RFIC_CellInit(uint64_t sampleRate, + uint64_t bw, + uint16_t antNumb, + uint16_t enFdd, + uint16_t enOrx, + uint16_t en204C, + uint16_t enUcpLog); +/** +* \brief Sets up the transceiver's tx rx LO frenq, bandwidth, Initialize attenuation. +* then process Initialize transceiver +* +* \param txLo is Transmit local frequency (Unit hz). +* \param rxLo is Receive local frequency (Unit hz). +* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20). +* \param initGain is Initialize rx Gain index (Unit db, range 183 ~ 255). +* \param auxLo is orx local frequency (Unit hz). +* \param calPara is paras for RX QEC、TX att cal and so on +* \param enOrx (0: disable orx, 1: orx Lo follows Tx Lo, 2: orx Lo follows aux Lo). +* +* \retval 0. +*/ +extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint16_t initAtt, + uint16_t initGain, uint64_t auxLo, uint16_t enOrx, + ucp_rfic_calPara_t calPara); + +/** +* \brief delete cell. +* +* \param void. +* +* \retval void. +*/ +extern int32_t UCP_API_RFIC_CellDelete(void); + +//********************************************************************************** +// chip option layer +// TRANSCEIVER +/** +* \brief transceiver chip hardware reset. +* +* \param void. +* +* \retval void. +*/ +extern int32_t UCP_API_TRANSCEIVER_Reset(void); + +/** +* \brief Sets up the transceiver's MGC Mod. +* +* \param en, if set 1, MGC Mode; set 0, AGC Mode. +* +* \retval 0. +*/ +extern int32_t UCP_API_TRANSCEIVER_MGC_Cfg(uint8_t en); + +/** +* \brief Sets up the transceiver's rx gain at MGC mode. +* +* \param gain_db (Unit db, range 0~36, step 0.5db). +* +* \retval 0. +*/ +extern int32_t UCP_API_TRANSCEIVER_Gain_Set(double gain_db); + +/** +* \brief Get the transceiver's rx gain. +* +* \param gain_db (Unit db, range 0~36, step 0.5db). +* +* \retval gain_db (Unit db, range 0~36, step 0.5db). +*/ +extern double UCP_API_TRANSCEIVER_Gain_Get(void); + +/** +* \brief Set up the transceiver's tx attenuation. +* +* \param att_db (Unit db, range 0~20). +* +* \retval 0. +*/ +extern int32_t UCP_API_TRANSCEIVER_Att_Set(uint8_t att_db); + +/** +* \brief Get the transceiver's tx attenuation. +* +* \retval att_db (Unit db, range 0~20). +*/ +extern uint8_t UCP_API_TRANSCEIVER_Att_Get(void); + +//********************************************************************************** +// CLOCKGEN +/** +* \brief clockGen chip hardware reset. +* +* \param void. +* +* \retval void. +*/ +extern void UCP_API_CLOCKGEN_Reset(void); + +/** +* \brief clockGen chip init function. +* +* \param void. +* +* \retval void. +*/ +extern int32_t UCP_API_CLOCKGEN_Init(void); + +/** +* \brief Get the status of clockGen chip's pll. +* +* \param void. +* +* \retval lock code. +*/ +extern uint8_t UCP_API_CLOCKGEN_LockStatus(void); + +/** +* \brief gpio of rf controlling +* +* \param setting +* +* \retval none. +*/ +extern void UCP_API_GPIO_Tx (void); +extern void UCP_API_GPIO_Rx (void); +extern void UCP_API_GPIO_Off (void); +extern void UCP_API_GPIO_OrxOn (void); +extern void UCP_API_GPIO_OrxOff (void); +extern void UCP_API_GPIO_TrigOn (void); +extern void UCP_API_GPIO_TrigOff (void); + +/** +* \brief Get board's indx +* +* \param void +* +* \retval + + HW_UNKNOW = 0 + HW_EVMT = 1 + HW_EVMF = 2 + HW_EVB = 3 + HW_EVMY = 4 + HW_OTHER = 254 + HW_MAX = 255 + +*/ +extern uint8_t UCP_API_RFIC_GetBoardInfo (void); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef UCP_API_RFIC_H_ */ + diff --git a/driver/rfic/rf/api/inc/ucp_jesd_gpio.h b/driver/rfic/rf/api/inc/ucp_jesd_gpio.h new file mode 100644 index 0000000..a285af4 --- /dev/null +++ b/driver/rfic/rf/api/inc/ucp_jesd_gpio.h @@ -0,0 +1,121 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_jesd_gpio.h (ap side) +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2022-09-08 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef __UCP_JESD_GPIO__ +#define __UCP_JESD_GPIO__ + +#include "ucp_api_jesd.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define GPIO_INDEX_MAX (64) +#define UCP_GPIO(port, pin) ((tUcpGpioRegTable_t *)&pUcpGpioTable[port][pin]) + +typedef struct tUcpGpioRegTable_tag { + uint32_t pinMuxReg; + uint32_t muxValue; + uint32_t muxMask; + uint32_t dirReg; + uint32_t valueReg; + uint32_t bitMask; +} tUcpGpioRegTable_t; + +typedef struct tGpioInfRegTable_tag { + uint8_t index; + uint8_t enable; + uint8_t dir; + uint8_t value; + tUcpGpioRegTable_t *gpio; +} tGpioInfRegTable; + +enum { + GPIO_PORT0A = 0, + GPIO_PORT0B, + GPIO_PORT1A, + GPIO_PORT1B +}; + +typedef enum eGpioDir_tag { + GPIO_DIR_IN = 0, + GPIO_DIR_OUT +} eGpioDir; + +enum { + GPIO_INDEX_TRX_TX1 = 0, + GPIO_INDEX_TRX_TX2, + GPIO_INDEX_TRX_TX3, + GPIO_INDEX_TRX_TX4, + GPIO_INDEX_RF_TX1, + GPIO_INDEX_RF_TX2, + GPIO_INDEX_RF_TX3, + GPIO_INDEX_RF_TX4, + GPIO_INDEX_SW_TX1, + GPIO_INDEX_SW_TX2, + GPIO_INDEX_SW_TX3, + GPIO_INDEX_SW_TX4, + + GPIO_INDEX_TRX_RX1, + GPIO_INDEX_TRX_RX2, + GPIO_INDEX_TRX_RX3, + GPIO_INDEX_TRX_RX4, + GPIO_INDEX_RF_RX1, + GPIO_INDEX_RF_RX2, + GPIO_INDEX_RF_RX3, + GPIO_INDEX_RF_RX4, + GPIO_INDEX_SW_RX1, + GPIO_INDEX_SW_RX2, + GPIO_INDEX_SW_RX3, + GPIO_INDEX_SW_RX4, + + GPIO_INDEX_TRX_ORX1, + GPIO_INDEX_TRX_ORX2, + GPIO_INDEX_TRX_ORX3, + GPIO_INDEX_TRX_ORX4, + GPIO_INDEX_RF_ORX1, + GPIO_INDEX_RF_ORX2, + GPIO_INDEX_RF_ORX3, + GPIO_INDEX_RF_ORX4, + GPIO_INDEX_SW_ORX1, + GPIO_INDEX_SW_ORX2, + GPIO_INDEX_SW_ORX3, + GPIO_INDEX_SW_ORX4, + + GPIO_INDEX_TRIGER, + + GPIO_INDEX_TR_MAX +}; + +extern const tUcpGpioRegTable_t *pUcpGpioTable[]; +extern ucp_jesd_TrxGpioCfg_t ucp_jesd_gpioInit (const char *trxGpioConfigFile, uint16_t enLog); +extern int ucp_jesd_gpioConfig (const int pinIdex, uint8_t dir, uint8_t enable, tUcpGpioRegTable_t *gpio); +extern int ucp_jesd_gpioSetDir(const int pinIdex, eGpioDir dir); +extern eGpioDir ucp_jesd_gpioGetDir(const int pinIdex); +extern int ucp_jesd_gpioSet(const int pinIdex, int value); +extern int ucp_jesd_gpioGet(const int pinIdex); +extern void ucp_jesd_gpio_tx (void); +extern void ucp_jesd_gpio_rx (void); +extern void ucp_jesd_gpio_on (void); +extern void ucp_jesd_gpio_off (void); +extern void ucp_jesd_gpio_orxOn (void); +extern void ucp_jesd_gpio_orxOff (void); +extern void ucp_jesd_gpio_trigOn (void); +extern void ucp_jesd_gpio_trigOff (void); + +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/driver/rfic/rf/api/inc/ucp_param.h b/driver/rfic/rf/api/inc/ucp_param.h new file mode 100644 index 0000000..62a820d --- /dev/null +++ b/driver/rfic/rf/api/inc/ucp_param.h @@ -0,0 +1,1353 @@ +//******************** (C) COPYRIGHT 2019 SmartLogic******************************* +// FileName : ucp_param.h +// Author : lijian, jian.li@smartlogictech.com +// Date First Issued : 2019-03-29 02:37:50 PM +// Last Modified : 2022-06-29 10:05:40 PM +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef __PARAM_UCP_H__ +#define __PARAM_UCP_H__ + +#include + +typedef uint8_t UINT8; +typedef uint16_t UINT16; +typedef uint32_t UINT32; +typedef uint64_t UINT64; + +#define BIT0 (0x1<<0ul) +#define BIT1 (0x1<<1ul) +#define BIT2 (0x1<<2ul) +#define BIT3 (0x1<<3ul) +#define BIT4 (0x1<<4ul) +#define BIT5 (0x1<<5ul) +#define BIT6 (0x1<<6ul) +#define BIT7 (0x1<<7ul) +#define BIT8 (0x1<<8ul) +#define BIT9 (0x1<<9ul) +#define BIT10 (0x1<<10ul) +#define BIT11 (0x1<<11ul) +#define BIT12 (0x1<<12ul) +#define BIT13 (0x1<<13ul) +#define BIT14 (0x1<<14ul) +#define BIT15 (0x1<<15ul) +#define BIT16 (0x1<<16ul) +#define BIT17 (0x1<<17ul) +#define BIT18 (0x1<<18ul) +#define BIT19 (0x1<<19ul) +#define BIT20 (0x1<<20ul) +#define BIT21 (0x1<<21ul) +#define BIT22 (0x1<<22ul) +#define BIT23 (0x1<<23ul) +#define BIT24 (0x1<<24ul) +#define BIT25 (0x1<<25ul) +#define BIT26 (0x1<<26ul) +#define BIT27 (0x1<<27ul) +#define BIT28 (0x1<<28ul) +#define BIT29 (0x1<<29ul) +#define BIT30 (0x1<<30ul) +#define BIT31 (0x1<<31ul) + +#define S64B 0x00000040ul +#define S128B 0x00000080ul +#define S256B 0x00000100ul +#define S512B 0x00000200ul +#define S1KB 0x00000400ul +#define S2KB 0x00000800ul +#define S4KB 0x00001000ul +#define S8KB 0x00002000ul +#define S16KB 0x00004000ul +#define S32KB 0x00008000ul +#define S64KB 0x00010000ul +#define S128KB 0x00020000ul +#define S256KB 0x00040000ul +#define S512KB 0x00080000ul +#define S1MB 0x00100000ul +#define S15MB 0x00180000ul +#define S2MB 0x00200000ul +#define S4MB 0x00400000ul + +//m3 -> apsm0 apsm -> apsm1 +#define M3_SRAM_BASE 0x043c8000ul +#define APSM0_BASE 0x04768000ul +#define APSM1_BASE 0x04778000ul +#define CPSM_BASE 0x09300000ul +#define DDR_BASE 0x10000000ul +#define APSM0_SIZE S64KB +#define APSM1_SIZE S64KB +#define CPSM_SIZE S128KB +#define M3_SRAM_SIZE S32KB + + +#define JS_SM_BASE 0x04d80000ul +#define JECS_SM_BASE 0x07200000ul +#define PET_SM_BASE 0x08700000ul +#define JS_SM_SIZE S128KB +#define JECS_SM_SIZE S128KB +#define PET_SM_SIZE S128KB + + + +#define SM0_BASE 0x09d00000ul +#define SM1_BASE 0x09e00000ul +#define SM2_BASE 0x09f00000ul +#define SM3_BASE 0x0a080000ul +#define SM4_BASE 0x0a200000ul +#define SM5_BASE 0x0a380000ul +#define SM0_SIZE S1MB +#define SM1_SIZE S1MB +#define SM2_SIZE S15MB +#define SM3_SIZE S15MB +#define SM4_SIZE S15MB +#define SM5_SIZE S15MB + +#define PET_PET_CTC_INTER 0 +#define JECS_JECS_CTC_INTER 0 + +#define APC_CPSPACC0_INTR 0 +#define APC_TMAC_INTR 1 +#define APC_JESD204A_WRAPPER_INTR 2 +#define APC_JESD204B_WRAPPER_INTR 3 +#define APC_JS_SM_EMPTY_INTR0 4 +#define APC_JS_SM_EMPTY_INTR1 5 +#define APC_JS_SM_EMPTY_INTR2 6 +#define APC_JS_SM_EMPTY_INTR3 7 +#define APC_JS_SM_EMPTY_INTR4 8 +#define APC_JS_SM_EMPTY_INTR5 9 +#define APC_JS_SM_EMPTY_INTR6 10 +#define APC_JS_SM_EMPTY_INTR7 11 +#define APC_JS_SM_FULL_INTR0 12 +#define APC_JS_SM_FULL_INTR1 13 +#define APC_JS_SM_FULL_INTR2 14 +#define APC_JS_SM_FULL_INTR3 15 +#define APC_JS_SM_FULL_INTR4 16 +#define APC_JS_SM_FULL_INTR5 17 +#define APC_JS_SM_FULL_INTR6 18 +#define APC_JS_SM_FULL_INTR7 19 +#define APC_SRIO_SUB0_INTR 20 +#define APC_SRIO_SUB1_INTR 21 +#define APC_PPS_OUT_INTR 22 +#define APC_PET_SM_EMPTY_INTR0 23 +#define APC_PET_SM_EMPTY_INTR1 24 +#define APC_PET_SM_EMPTY_INTR2 25 +#define APC_PET_SM_EMPTY_INTR3 26 +#define APC_PET_SM_EMPTY_INTR4 27 +#define APC_PET_SM_EMPTY_INTR5 28 +#define APC_PET_SM_EMPTY_INTR6 29 +#define APC_PET_SM_EMPTY_INTR7 30 +#define APC_PET_SM_FULL_INTR0 31 +#define APC_PET_SM_FULL_INTR1 32 +#define APC_PET_SM_FULL_INTR2 33 +#define APC_PET_SM_FULL_INTR3 34 +#define APC_PET_SM_FULL_INTR4 35 +#define APC_PET_SM_FULL_INTR5 36 +#define APC_PET_SM_FULL_INTR6 37 +#define APC_PET_SM_FULL_INTR7 38 +#define APC_JECS_SM_EMPTY_INTR0 39 +#define APC_JECS_SM_EMPTY_INTR1 40 +#define APC_JECS_SM_EMPTY_INTR2 41 +#define APC_JECS_SM_EMPTY_INTR3 42 +#define APC_JECS_SM_EMPTY_INTR4 43 +#define APC_JECS_SM_EMPTY_INTR5 44 +#define APC_JECS_SM_EMPTY_INTR6 45 +#define APC_JECS_SM_EMPTY_INTR7 46 +#define APC_JECS_SM_FULL_INTR0 47 +#define APC_JECS_SM_FULL_INTR1 48 +#define APC_JECS_SM_FULL_INTR2 49 +#define APC_JECS_SM_FULL_INTR3 50 +#define APC_JECS_SM_FULL_INTR4 51 +#define APC_JECS_SM_FULL_INTR5 52 +#define APC_JECS_SM_FULL_INTR6 53 +#define APC_JECS_SM_FULL_INTR7 54 +#define APC_MBX0_HPRI_INTR0 55 +#define APC_MBX0_HPRI_INTR1 56 +#define APC_MBX0_HPRI_INTR2 57 +#define APC_MBX0_HPRI_INTR3 58 +#define APC_MBX0_LPRI_INTR0 59 +#define APC_MBX0_LPRI_INTR1 60 +#define APC_MBX0_LPRI_INTR2 61 +#define APC_MBX0_LPRI_INTR3 62 +#define APC_MBX1_HPRI_INTR0 63 +#define APC_MBX1_HPRI_INTR1 64 +#define APC_MBX1_HPRI_INTR2 65 +#define APC_MBX1_HPRI_INTR3 66 +#define APC_MBX1_LPRI_INTR0 67 +#define APC_MBX1_LPRI_INTR1 68 +#define APC_MBX1_LPRI_INTR2 69 +#define APC_MBX1_LPRI_INTR3 70 +#define APC_SSI2_INTR 71 +#define APC_SSI3_INTR 72 +#define APC_TIMER10_INTR 73 +#define APC_TIMER11_INTR 74 +#define APC_TIMER12_INTR 75 +#define APC_TIMER13_INTR 76 +#define APC_TIMER14_INTR 77 +#define APC_TIMER15_INTR 78 +#define APC_TIMER16_INTR 79 +#define APC_TIMER17_INTR 80 +#define APC_TIMER20_INTR 81 +#define APC_TIMER21_INTR 82 +#define APC_TIMER22_INTR 83 +#define APC_TIMER23_INTR 84 +#define APC_TIMER24_INTR 85 +#define APC_TIMER25_INTR 86 +#define APC_TIMER26_INTR 87 +#define APC_TIMER27_INTR 88 +#define APC_JS_CRG_INTR 89 +#define APC_RFC_INTR0 90 +#define APC_RFC_INTR1 91 +#define APC_RFC_INTR2 92 +#define APC_PETSPACC0_INTR 93 +#define APC_RFCSU_RX_INTR 94 +#define APC_RFCSU_TX_INTR 95 +#define APC_JESD_RX0_SBU0_TMR_INTR0 96 +#define APC_JESD_RX0_SBU0_TMR_INTR1 97 +#define APC_JESD_RX0_SBU0_TMR_INTR2 98 +#define APC_JESD_RX0_SBU0_TMR_INTR3 99 +#define APC_JESD_RX0_SBU0_TMR_INTR4 100 +#define APC_JESD_RX0_SBU0_TMR_INTR5 101 +#define APC_JESD_RX0_SBU0_TMR_INTR6 102 +#define APC_JESD_RX0_SBU0_TMR_INTR7 103 +#define APC_JESD_RX0_SBU0_TMR_INTR8 104 +#define APC_JESD_RX0_SBU0_TMR_INTR9 105 +#define APC_JESD_RX0_SBU0_TMR_INTR10 106 +#define APC_JESD_RX0_SBU0_TMR_INTR11 107 +#define APC_SLAVE_INTERRUPT_204B_RX0 108 +#define APC_SLAVE_INTERRUPT_204B_RX1 109 +#define APC_SLAVE_INTERRUPT_204B_TX0 110 +#define APC_SLAVE_INTERRUPT_204C_RX0 111 +#define APC_SLAVE_INTERRUPT_204C_RX1 112 +#define APC_SLAVE_INTERRUPT_204C_TX0 113 +#define APC_JECS_CTC_INTER 114 +#define APC_PET_CTC_INTER 115 +#define APC_SPACC0_INTR 116 +#define APC_CPSM_EMPTY_INTR0 120 +#define APC_CPSM_EMPTY_INTR1 121 +#define APC_CPSM_EMPTY_INTR2 122 +#define APC_CPSM_EMPTY_INTR3 123 +#define APC_CPSM_EMPTY_INTR4 124 +#define APC_CPSM_EMPTY_INTR5 125 +#define APC_CPSM_EMPTY_INTR6 126 +#define APC_CPSM_EMPTY_INTR7 127 +#define APC_CPSM_FULL_INTR0 128 +#define APC_CPSM_FULL_INTR1 129 +#define APC_CPSM_FULL_INTR2 130 +#define APC_CPSM_FULL_INTR3 131 +#define APC_CPSM_FULL_INTR4 132 +#define APC_CPSM_FULL_INTR5 133 +#define APC_CPSM_FULL_INTR6 134 +#define APC_CPSM_FULL_INTR7 135 +#define APC_RFC_DMA_INTR 136 +#define APC_JESD_CSU_RX0_INTR 137 +#define APC_JESD_CSU_TX_INTR 138 +#define APC_JESD_CSU_RX1_INTR 139 +#define APC_JESDA_CSU_TX_INTR1 140 +#define APC_JESDB_CSU_RX_INTR0 141 +#define APC_JESDB_CSU_RX_INTR1 142 +#define APC_JESDB_CSU_TX_INTR0 143 +#define APC_JESDB_CSU_TX_INTR1 144 + +#define APC_PETRFM_OUT_INTR0 205 +#define APC_PETRFM_OUT_INTR1 206 +#define APC_PETRFM_OUT_INTR2 207 +#define APC_PETRFM_OUT_INTR3 208 +#define APC_PETRFM_OUT_INTR4 209 +#define APC_PETRFM_OUT_INTR5 210 +#define APC_PETRFM_OUT_INTR6 211 +#define APC_PETRFM_OUT_INTR7 212 +#define APC_PETRFM_OUT_INTR8 213 +#define APC_PETRFM_OUT_INTR9 214 +#define APC_PETRFM_OUT_INTR10 215 +#define APC_PETRFM_OUT_INTR11 216 +#define APC_PETRFM_OUT_INTR12 217 +#define APC_PETRFM_OUT_INTR13 218 +#define APC_PETRFM_OUT_INTR14 219 +#define APC_PETRFM_OUT_INTR15 220 +#define APC_PETRFM_OUT_INTR16 221 +#define APC_PETRFM_OUT_INTR17 222 +#define APC_PETRFM_OUT_INTR18 223 +#define APC_PETRFM_OUT_INTR19 224 +#define APC_JECSRFM_OUT_INTR0 225 +#define APC_JECSRFM_OUT_INTR1 226 +#define APC_JECSRFM_OUT_INTR2 227 +#define APC_JECSRFM_OUT_INTR3 228 +#define APC_JECSRFM_OUT_INTR4 229 +#define APC_JECSRFM_OUT_INTR5 230 +#define APC_JECSRFM_OUT_INTR6 231 +#define APC_JECSRFM_OUT_INTR7 232 +#define APC_JECSRFM_OUT_INTR8 233 +#define APC_JECSRFM_OUT_INTR9 234 +#define APC_JECSRFM_OUT_INTR10 235 +#define APC_JECSRFM_OUT_INTR11 236 +#define APC_JECSRFM_OUT_INTR12 237 +#define APC_JECSRFM_OUT_INTR13 238 +#define APC_JECSRFM_OUT_INTR14 239 +#define APC_JECSRFM_OUT_INTR15 240 +#define APC_JECSRFM_OUT_INTR16 241 +#define APC_JECSRFM_OUT_INTR17 242 +#define APC_JECSRFM_OUT_INTR18 243 +#define APC_JECSRFM_OUT_INTR19 244 +#define APC_ECPRI_SUB_INTR0 245 +#define APC_ECPRI_SUB_INTR1 246 +#define APC_ECPRI_SUB_INTR2 247 +#define APC_ECPRI_SUB_INTR3 248 +#define APC_ECPRI_SUB_INTR4 249 +#define APC_ECPRI_SUB_INTR5 250 +#define APC_ECPRI_SUB_INTR6 251 +#define APC_ECPRI_SUB_INTR7 252 +#define APC_ECPRI_SUB_INTR8 253 +#define APC_ECPRI_SUB_INTR9 254 +#define APC_ECPRI_SUB_INTR10 255 +#define APC_ECPRI_SUB_INTR11 256 +#define APC_ECPRI_SUB_INTR12 257 +#define APC_ECPRI_SUB_INTR13 258 +#define APC_ECPRI_SUB_INTR14 259 +#define APC_ECPRI_SUB_INTR15 260 +#define APC_ECPRI_SUB_INTR16 261 +#define APC_ECPRI_SUB_INTR17 262 +#define APC_ECPRI_SUB_INTR18 263 +#define APC_ECPRI_SUB_INTR19 264 +#define APC_ECPRI_SUB_INTR20 265 +#define APC_ECPRI_SUB_INTR21 266 +#define APC_ECPRI_SUB_INTR22 267 +#define APC_ECPRI_SUB_INTR23 268 +#define APC_ECPRI_SUB_INTR24 269 +#define APC_ECPRI_SUB_INTR25 270 +#define APC_ECPRI_SUB_INTR26 271 +#define APC_ECPRI_SUB_INTR27 272 +#define APC_ECPRI_SUB_INTR28 273 +#define APC_ECPRI_SUB_INTR29 274 +#define APC_ECPRI_SUB_INTR30 275 +#define APC_ECPRI_SUB_INTR31 276 +#define APC_PETSPACC1_INTR 277 +#define APC_CPRI_SUB_INTR0 278 +#define APC_CPRI_SUB_INTR1 279 +#define APC_STC_INTR0 280 +#define APC_STC_INTR1 281 +#define APC_STC_INTR2 282 +#define APC_STC_INTR3 283 +#define APC_STC_INTR4 284 +#define APC_STC_INTR5 285 +#define APC_STC_INTR6 286 +#define APC_STC_INTR7 287 +#define APC_STC_INTR8 288 +#define APC_STC_INTR9 289 +#define APC_STC_INTR10 290 + +#define APC_CPRI_TMR_INTR0 291 +#define APC_CPRI_TMR_INTR1 292 +#define APC_CPRI_TMR_INTR2 293 +#define APC_CPRI_TMR_INTR3 294 +#define APC_CPRI_TMR_INTR4 295 +#define APC_CPRI_TMR_INTR5 296 +#define APC_CPRI_TMR_INTR6 297 +#define APC_CPRI_TMR_INTR7 298 +#define APC_CPRI_TMR_INTR8 299 +#define APC_CPRI_TMR_INTR9 300 +#define APC_CPRI_TMR_INTR10 301 +#define APC_CPRI_TMR_INTR11 302 + +#define APC_SSI0_INTR (310+0) +#define APC_SSI1_INTR (310+1) +#define APC_UART0_INTR (310+2) +#define APC_UART1_INTR (310+3) +#define APC_WDT0_INTR (310+4) +#define APC_WDT1_INTR (310+5) +#define APC_TIMER0_INTR (310+6) +#define APC_GPIO0_INTR (310+7) + +#define APC_GPIO1_INTR (467) +#define APC_PEREST_INTR 466 + +#define APC_APSM1_EMPTY_INTR0 (310+4+4) +#define APC_APSM1_EMPTY_INTR1 (310+4+5) +#define APC_APSM1_EMPTY_INTR2 (310+4+6) +#define APC_APSM1_EMPTY_INTR3 (310+4+7) +#define APC_APSM1_EMPTY_INTR4 (310+4+8) +#define APC_APSM1_EMPTY_INTR5 (310+4+9) +#define APC_APSM1_EMPTY_INTR6 (310+4+10) +#define APC_APSM1_EMPTY_INTR7 (310+4+11) +#define APC_APSM1_FULL_INTR0 (310+4+12) +#define APC_APSM1_FULL_INTR1 (310+4+13) +#define APC_APSM1_FULL_INTR2 (310+4+14) +#define APC_APSM1_FULL_INTR3 (310+4+15) +#define APC_APSM1_FULL_INTR4 (310+4+16) +#define APC_APSM1_FULL_INTR5 (310+4+17) +#define APC_APSM1_FULL_INTR6 (310+4+18) +#define APC_APSM1_FULL_INTR7 (310+4+19) + +#define APC_AP_CSU_INTR0 (310+28) +#define APC_AP_CSU_INTR1 (310+29) +#define APC_AP_CSU_INTR2 (310+30) +#define APC_AP_CSU_INTR3 (310+31) +#define APC_AP_CSU_INTR4 (310+32) +#define APC_AP_CSU_INTR5 (310+33) +#define APC_AP_CSU_INTR6 (310+34) +#define APC_AP_CSU_INTR7 (310+35) +#define APC_SYSC_CTC10_INTR0 (310+36) +#define APC_SYSC_CTC11_INTR0 (310+37) +#define APC_SYSC_CTC12_INTR0 (310+38) +#define APC_SYSC_CTC13_INTR0 (310+39) +#define APC_SYSC_CTC14_INTR0 (310+40) +#define APC_SYSC_CTC15_INTR0 (310+41) +#define APC_SYSC_CTC16_INTR0 (310+42) +#define APC_SYSC_CTC17_INTR0 (310+43) +#define APC_SYSC_CTC18_INTR0 (310+44) +#define APC_SYSC_CTC19_INTR0 (310+45) +#define APC_SYSC_CTC20_INTR0 (310+46) +#define APC_SYSC_CTC21_INTR0 (310+47) +#define APC_SYSC_CTC22_INTR0 (310+48) +#define APC_SYSC_CTC23_INTR0 (310+49) +#define APC_SYSC_CTC24_INTR0 (310+50) +#define APC_SYSC_CTC25_INTR0 (310+51) +#define APC_SYSC_CTC26_INTR0 (310+52) +#define APC_SYSC_CTC27_INTR0 (310+53) +#define APC_SYSC_CTC28_INTR0 (310+54) +#define APC_SYSC_CTC29_INTR0 (310+55) +#define APC_SYSC_CTC30_INTR0 (310+56) +#define APC_SYSC_CTC31_INTR0 (310+57) +#define APC_SYSC_CTC32_INTR0 (310+58) +#define APC_SYSC_CTC33_INTR0 (310+59) +#define APC_SYSC_CTC34_INTR0 (310+60) +#define APC_SYSC_CTC35_INTR0 (310+61) +#define APC_SYSC_CTC36_INTR0 (310+62) +#define APC_SYSC_CTC37_INTR0 (310+63) +#define APC_SYSC_CTC38_INTR0 (310+64) +#define APC_SYSC_CTC39_INTR0 (310+65) +#define APC_SYSC_CTC40_INTR0 (310+66) +#define APC_SYSC_CTC41_INTR0 (310+67) +#define APC_SYSC_CTC42_INTR0 (310+68) +#define APC_SYSC_CTC43_INTR0 (310+69) +#define APC_SYSC_CTC44_INTR0 (310+70) +#define APC_SYSC_CTC45_INTR0 (310+71) +#define APC_SYSC_CTC46_INTR0 (310+72) +#define APC_SYSC_CTC47_INTR0 (310+73) +#define APC_SYSC_CTC48_INTR0 (310+74) +#define APC_SYSC_CTC49_INTR0 (310+75) +#define APC_SYSC_CTC50_INTR0 (310+76) +#define APC_SYSC_CTC51_INTR0 (310+77) +#define APC_SYSC_CTC52_INTR0 (310+78) +#define APC_SYSC_CTC53_INTR0 (310+79) +#define APC_SYSC_CTC54_INTR0 (310+80) +#define APC_SYSC_CTC55_INTR0 (310+81) +#define APC_SYSC_CTC56_INTR0 (310+82) +#define APC_SYSC_CTC57_INTR0 (310+83) +#define APC_SYSC_CTC58_INTR0 (310+84) +#define APC_SYSC_CTC59_INTR0 (310+85) +#define APC_SYSC_CTC60_INTR0 (310+86) +#define APC_SYSC_CTC61_INTR0 (310+87) +#define APC_SYSC_CTC62_INTR0 (310+88) +#define APC_SYSC_CTC63_INTR0 (310+89) +#define APC_SYSC_CTC64_INTR0 (310+90) +#define APC_SYSC_CTC65_INTR0 (310+91) +#define APC_SYSC_CTC66_INTR0 (310+92) +#define APC_SYSC_CTC67_INTR0 (310+93) +#define APC_SYSC_CTC68_INTR0 (310+94) +#define APC_SYSC_CTC69_INTR0 (310+95) +#define APC_SYSC_CTC70_INTR0 (310+96) +#define APC_SYSC_CTC71_INTR0 (310+97) + +#define APC_JESD_TX0_SBU0_TMR_INTR0 408 +#define APC_JESD_TX0_SBU0_TMR_INTR1 409 +#define APC_JESD_TX0_SBU0_TMR_INTR2 410 +#define APC_JESD_TX0_SBU0_TMR_INTR3 411 +#define APC_JESD_TX0_SBU0_TMR_INTR4 412 +#define APC_JESD_TX0_SBU0_TMR_INTR5 413 +#define APC_JESD_TX0_SBU0_TMR_INTR6 414 +#define APC_JESD_TX0_SBU0_TMR_INTR7 415 +#define APC_JESD_TX0_SBU0_TMR_INTR8 416 +#define APC_JESD_TX0_SBU0_TMR_INTR9 417 +#define APC_JESD_TX0_SBU0_TMR_INTR10 418 +#define APC_JESD_TX0_SBU0_TMR_INTR11 419 + +#define APC_JESD_TX_SBU1_TMR_INTR0 420 +#define APC_JESD_TX_SBU1_TMR_INTR1 421 +#define APC_JESD_TX_SBU1_TMR_INTR2 422 +#define APC_JESD_TX_SBU1_TMR_INTR3 423 +#define APC_JESD_TX_SBU1_TMR_INTR4 424 +#define APC_JESD_TX_SBU1_TMR_INTR5 425 +#define APC_JESD_TX_SBU1_TMR_INTR6 426 +#define APC_JESD_TX_SBU1_TMR_INTR7 427 +#define APC_JESD_TX_SBU1_TMR_INTR8 428 +#define APC_JESD_TX_SBU1_TMR_INTR9 429 +#define APC_JESD_TX_SBU1_TMR_INTR10 430 +#define APC_JESD_TX_SBU1_TMR_INTR11 431 + +#define APC_JESD_TX1_SBU0_TMR_INTR0 266 +#define APC_JESD_TX1_SBU0_TMR_INTR1 267 +#define APC_JESD_TX1_SBU0_TMR_INTR2 268 +#define APC_JESD_TX1_SBU0_TMR_INTR3 269 +#define APC_JESD_TX1_SBU0_TMR_INTR4 270 +#define APC_JESD_TX1_SBU0_TMR_INTR5 271 +#define APC_JESD_TX1_SBU0_TMR_INTR6 272 +#define APC_JESD_TX1_SBU0_TMR_INTR7 273 +#define APC_JESD_TX1_SBU0_TMR_INTR8 274 +#define APC_JESD_TX1_SBU0_TMR_INTR9 275 +#define APC_JESD_TX1_SBU0_TMR_INTR10 276 +#define APC_JESD_TX1_SBU0_TMR_INTR11 277 + +#define APC_JS_CSU_TXRX1_INTR0 432 +#define APC_JS_CSU_TXRX1_INTR1 433 +#define APC_JS_CSU_TXRX1_INTR2 434 +#define APC_JS_CSU_TXRX1_INTR3 435 +#define APC_JS_CSU_TXRX1_INTR4 436 +#define APC_JS_CSU_TXRX1_INTR5 437 +#define APC_JS_CSU_TXRX1_INTR6 438 +#define APC_JS_CSU_TXRX1_INTR7 439 + +#define APC_JECS_CSU_INTR0 440 +#define APC_JECS_CSU_INTR1 441 +#define APC_JECS_CSU_INTR2 442 +#define APC_JECS_CSU_INTR3 443 +#define APC_JECS_CSU_INTR4 444 +#define APC_JECS_CSU_INTR5 445 +#define APC_JECS_CSU_INTR6 446 +#define APC_JECS_CSU_INTR7 447 + +#define APC_JECS_CSU_TXRX1_INTR0 448 +#define APC_JECS_CSU_TXRX1_INTR1 449 +#define APC_JECS_CSU_TXRX1_INTR2 450 +#define APC_JECS_CSU_TXRX1_INTR3 451 +#define APC_JECS_CSU_TXRX1_INTR4 452 +#define APC_JECS_CSU_TXRX1_INTR5 453 +#define APC_JECS_CSU_TXRX1_INTR6 454 +#define APC_JECS_CSU_TXRX1_INTR7 455 + + +#define APC_EIP0_GLOBLE_INT 117 +#define APC_EIP0_RING0_INT 118 +#define APC_EIP0_RING1_INT 119 +#define APC_EIP0_RING2_INT 456 +#define APC_EIP0_RING3_INT 457 +#define APC_EIP1_GLOBLE_INT 458 +#define APC_EIP1_RING0_INT 459 +#define APC_EIP1_RING1_INT 460 +#define APC_EIP1_RING2_INT 461 +#define APC_EIP1_RING3_INT 462 + +#define APC_GMAC0SDB_INT 463 +#define APC_GMAC0PMT_INT 464 +#define APC_GMAC0LPI_INT 465 + + + +#define APC_JESD_RX0_SBU1_TMR_INTR0 471 +#define APC_JESD_RX0_SBU1_TMR_INTR1 472 +#define APC_JESD_RX0_SBU1_TMR_INTR2 473 +#define APC_JESD_RX0_SBU1_TMR_INTR3 474 +#define APC_JESD_RX0_SBU1_TMR_INTR4 475 +#define APC_JESD_RX0_SBU1_TMR_INTR5 476 +#define APC_JESD_RX0_SBU1_TMR_INTR6 477 +#define APC_JESD_RX0_SBU1_TMR_INTR7 478 +#define APC_JESD_RX0_SBU1_TMR_INTR8 479 +#define APC_JESD_RX0_SBU1_TMR_INTR9 480 +#define APC_JESD_RX0_SBU1_TMR_INTR10 481 +#define APC_JESD_RX0_SBU1_TMR_INTR11 482 + +#define APC_JESD_RX1_SBU0_TMR_INTR0 483 +#define APC_JESD_RX1_SBU0_TMR_INTR1 484 +#define APC_JESD_RX1_SBU0_TMR_INTR2 485 +#define APC_JESD_RX1_SBU0_TMR_INTR3 486 +#define APC_JESD_RX1_SBU0_TMR_INTR4 487 +#define APC_JESD_RX1_SBU0_TMR_INTR5 488 +#define APC_JESD_RX1_SBU0_TMR_INTR6 489 +#define APC_JESD_RX1_SBU0_TMR_INTR7 490 +#define APC_JESD_RX1_SBU0_TMR_INTR8 491 +#define APC_JESD_RX1_SBU0_TMR_INTR9 492 +#define APC_JESD_RX1_SBU0_TMR_INTR10 493 +#define APC_JESD_RX1_SBU0_TMR_INTR11 494 + +#define APC_JESD_RX1_SBU1_TMR_INTR0 495 +#define APC_JESD_RX1_SBU1_TMR_INTR1 496 +#define APC_JESD_RX1_SBU1_TMR_INTR2 497 +#define APC_JESD_RX1_SBU1_TMR_INTR3 498 +#define APC_JESD_RX1_SBU1_TMR_INTR4 499 +#define APC_JESD_RX1_SBU1_TMR_INTR5 500 +#define APC_JESD_RX1_SBU1_TMR_INTR6 501 +#define APC_JESD_RX1_SBU1_TMR_INTR7 502 +#define APC_JESD_RX1_SBU1_TMR_INTR8 503 +#define APC_JESD_RX1_SBU1_TMR_INTR9 504 +#define APC_JESD_RX1_SBU1_TMR_INTR10 505 +#define APC_JESD_RX1_SBU1_TMR_INTR11 506 + + +#define APC_EIP2_GLOBLE_INT 93 +#define APC_EIP2_RING0_INT 507 +#define APC_EIP2_RING1_INT 508 +#define APC_EIP2_RING2_INT 509 +#define APC_EIP2_RING3_INT 510 + +#define APC_PCIE_INTR 511 + + + +#define APC_INPUT0 145 +#define APC_INPUT1 165 +#define APC_INPUT2 185 +#define APC_INPUT3 205 +#define APC_INPUT4 225 +#define APC_INPUT5 310+8 + +//APC interconnect int +#define APC_INPUT0_INTR0 (0+ APC_INPUT0) +#define APC_INPUT0_INTR1 (1+ APC_INPUT0) +#define APC_INPUT0_INTR2 (2+ APC_INPUT0) +#define APC_INPUT0_INTR3 (3+ APC_INPUT0) +#define APC_INPUT0_INTR4 (4+ APC_INPUT0) +#define APC_INPUT0_INTR5 (5+ APC_INPUT0) +#define APC_INPUT0_INTR6 (6+ APC_INPUT0) +#define APC_INPUT0_INTR7 (7+ APC_INPUT0) +#define APC_INPUT0_INTR8 (8+ APC_INPUT0) +#define APC_INPUT0_INTR9 (9+ APC_INPUT0) +#define APC_INPUT0_INTR10 (10+APC_INPUT0) +#define APC_INPUT0_INTR11 (11+APC_INPUT0) +#define APC_INPUT0_INTR12 (12+APC_INPUT0) +#define APC_INPUT0_INTR13 (13+APC_INPUT0) +#define APC_INPUT0_INTR14 (14+APC_INPUT0) +#define APC_INPUT0_INTR15 (15+APC_INPUT0) +#define APC_INPUT0_INTR16 (16+APC_INPUT0) +#define APC_INPUT0_INTR17 (17+APC_INPUT0) +#define APC_INPUT0_INTR18 (18+APC_INPUT0) +#define APC_INPUT0_INTR19 (19+APC_INPUT0) + +#define APC_INPUT1_INTR0 (0+ APC_INPUT1) +#define APC_INPUT1_INTR1 (1+ APC_INPUT1) +#define APC_INPUT1_INTR2 (2+ APC_INPUT1) +#define APC_INPUT1_INTR3 (3+ APC_INPUT1) +#define APC_INPUT1_INTR4 (4+ APC_INPUT1) +#define APC_INPUT1_INTR5 (5+ APC_INPUT1) +#define APC_INPUT1_INTR6 (6+ APC_INPUT1) +#define APC_INPUT1_INTR7 (7+ APC_INPUT1) +#define APC_INPUT1_INTR8 (8+ APC_INPUT1) +#define APC_INPUT1_INTR9 (9+ APC_INPUT1) +#define APC_INPUT1_INTR10 (10+APC_INPUT1) +#define APC_INPUT1_INTR11 (11+APC_INPUT1) +#define APC_INPUT1_INTR12 (12+APC_INPUT1) +#define APC_INPUT1_INTR13 (13+APC_INPUT1) +#define APC_INPUT1_INTR14 (14+APC_INPUT1) +#define APC_INPUT1_INTR15 (15+APC_INPUT1) +#define APC_INPUT1_INTR16 (16+APC_INPUT1) +#define APC_INPUT1_INTR17 (17+APC_INPUT1) +#define APC_INPUT1_INTR18 (18+APC_INPUT1) +#define APC_INPUT1_INTR19 (19+APC_INPUT1) + +#define APC_INPUT2_INTR0 (0+ APC_INPUT2) +#define APC_INPUT2_INTR1 (1+ APC_INPUT2) +#define APC_INPUT2_INTR2 (2+ APC_INPUT2) +#define APC_INPUT2_INTR3 (3+ APC_INPUT2) +#define APC_INPUT2_INTR4 (4+ APC_INPUT2) +#define APC_INPUT2_INTR5 (5+ APC_INPUT2) +#define APC_INPUT2_INTR6 (6+ APC_INPUT2) +#define APC_INPUT2_INTR7 (7+ APC_INPUT2) +#define APC_INPUT2_INTR8 (8+ APC_INPUT2) +#define APC_INPUT2_INTR9 (9+ APC_INPUT2) +#define APC_INPUT2_INTR10 (10+APC_INPUT2) +#define APC_INPUT2_INTR11 (11+APC_INPUT2) +#define APC_INPUT2_INTR12 (12+APC_INPUT2) +#define APC_INPUT2_INTR13 (13+APC_INPUT2) +#define APC_INPUT2_INTR14 (14+APC_INPUT2) +#define APC_INPUT2_INTR15 (15+APC_INPUT2) +#define APC_INPUT2_INTR16 (16+APC_INPUT2) +#define APC_INPUT2_INTR17 (17+APC_INPUT2) +#define APC_INPUT2_INTR18 (18+APC_INPUT2) +#define APC_INPUT2_INTR19 (19+APC_INPUT2) + +#define APC_INPUT3_INTR0 (0+ APC_INPUT3) +#define APC_INPUT3_INTR1 (1+ APC_INPUT3) +#define APC_INPUT3_INTR2 (2+ APC_INPUT3) +#define APC_INPUT3_INTR3 (3+ APC_INPUT3) +#define APC_INPUT3_INTR4 (4+ APC_INPUT3) +#define APC_INPUT3_INTR5 (5+ APC_INPUT3) +#define APC_INPUT3_INTR6 (6+ APC_INPUT3) +#define APC_INPUT3_INTR7 (7+ APC_INPUT3) +#define APC_INPUT3_INTR8 (8+ APC_INPUT3) +#define APC_INPUT3_INTR9 (9+ APC_INPUT3) +#define APC_INPUT3_INTR10 (10+APC_INPUT3) +#define APC_INPUT3_INTR11 (11+APC_INPUT3) +#define APC_INPUT3_INTR12 (12+APC_INPUT3) +#define APC_INPUT3_INTR13 (13+APC_INPUT3) +#define APC_INPUT3_INTR14 (14+APC_INPUT3) +#define APC_INPUT3_INTR15 (15+APC_INPUT3) +#define APC_INPUT3_INTR16 (16+APC_INPUT3) +#define APC_INPUT3_INTR17 (17+APC_INPUT3) +#define APC_INPUT3_INTR18 (18+APC_INPUT3) +#define APC_INPUT3_INTR19 (19+APC_INPUT3) + +#define APC_INPUT4_INTR0 (0+ APC_INPUT4) +#define APC_INPUT4_INTR1 (1+ APC_INPUT4) +#define APC_INPUT4_INTR2 (2+ APC_INPUT4) +#define APC_INPUT4_INTR3 (3+ APC_INPUT4) +#define APC_INPUT4_INTR4 (4+ APC_INPUT4) +#define APC_INPUT4_INTR5 (5+ APC_INPUT4) +#define APC_INPUT4_INTR6 (6+ APC_INPUT4) +#define APC_INPUT4_INTR7 (7+ APC_INPUT4) +#define APC_INPUT4_INTR8 (8+ APC_INPUT4) +#define APC_INPUT4_INTR9 (9+ APC_INPUT4) +#define APC_INPUT4_INTR10 (10+APC_INPUT4) +#define APC_INPUT4_INTR11 (11+APC_INPUT4) +#define APC_INPUT4_INTR12 (12+APC_INPUT4) +#define APC_INPUT4_INTR13 (13+APC_INPUT4) +#define APC_INPUT4_INTR14 (14+APC_INPUT4) +#define APC_INPUT4_INTR15 (15+APC_INPUT4) +#define APC_INPUT4_INTR16 (16+APC_INPUT4) +#define APC_INPUT4_INTR17 (17+APC_INPUT4) +#define APC_INPUT4_INTR18 (18+APC_INPUT4) +#define APC_INPUT4_INTR19 (19+APC_INPUT4) + +#define APC_INPUT5_INTR0 (0+ APC_INPUT5) +#define APC_INPUT5_INTR1 (1+ APC_INPUT5) +#define APC_INPUT5_INTR2 (2+ APC_INPUT5) +#define APC_INPUT5_INTR3 (3+ APC_INPUT5) +#define APC_INPUT5_INTR4 (4+ APC_INPUT5) +#define APC_INPUT5_INTR5 (5+ APC_INPUT5) +#define APC_INPUT5_INTR6 (6+ APC_INPUT5) +#define APC_INPUT5_INTR7 (7+ APC_INPUT5) +#define APC_INPUT5_INTR8 (8+ APC_INPUT5) +#define APC_INPUT5_INTR9 (9+ APC_INPUT5) +#define APC_INPUT5_INTR10 (10+APC_INPUT5) +#define APC_INPUT5_INTR11 (11+APC_INPUT5) +#define APC_INPUT5_INTR12 (12+APC_INPUT5) +#define APC_INPUT5_INTR13 (13+APC_INPUT5) +#define APC_INPUT5_INTR14 (14+APC_INPUT5) +#define APC_INPUT5_INTR15 (15+APC_INPUT5) +#define APC_INPUT5_INTR16 (16+APC_INPUT5) +#define APC_INPUT5_INTR17 (17+APC_INPUT5) +#define APC_INPUT5_INTR18 (18+APC_INPUT5) +#define APC_INPUT5_INTR19 (19+APC_INPUT5) + + +#define APRFM_SYSC_CTC8_INTR0 570 +#define APRFM_SYSC_CTC9_INTR0 571 +#define APRFM_SYSC_CTC10_INTR0 572 +#define APRFM_SYSC_CTC11_INTR0 573 +#define APRFM_SYSC_CTC12_INTR0 574 +#define APRFM_SYSC_CTC13_INTR0 575 +#define APRFM_SYSC_CTC14_INTR0 576 +#define APRFM_SYSC_CTC15_INTR0 577 + + +#define PPS_OUT_INTR (175+460) +//define ARM INTERRUPT NUM +#define PETRFM2SYS_INTR0 (175+280) +#define PETRFM2SYS_INTR1 (175+281) +#define PETRFM2SYS_INTR2 (175+282) +#define PETRFM2SYS_INTR3 (175+283) +#define PETRFM2SYS_INTR4 (175+284) +#define PETRFM2SYS_INTR5 (175+285) +#define PETRFM2SYS_INTR6 (175+286) +#define PETRFM2SYS_INTR7 (175+287) +#define PETRFM2SYS_INTR8 (175+288) +#define PETRFM2SYS_INTR9 (175+289) +#define PETRFM2SYS_INTR10 (175+290) +#define PETRFM2SYS_INTR11 (175+291) +#define PETRFM2SYS_INTR12 (175+292) +#define PETRFM2SYS_INTR13 (175+293) +#define PETRFM2SYS_INTR14 (175+294) +#define PETRFM2SYS_INTR15 (175+295) +#define PETRFM2SYS_INTR16 (175+296) +#define PETRFM2SYS_INTR17 (175+297) +#define PETRFM2SYS_INTR18 (175+298) +#define PETRFM2SYS_INTR19 (175+299) +#define JECS_RFM_OUT_INTR0 (175+300) +#define JECS_RFM_OUT_INTR1 (175+301) +#define JECS_RFM_OUT_INTR2 (175+302) +#define JECS_RFM_OUT_INTR3 (175+303) +#define JECS_RFM_OUT_INTR4 (175+304) +#define JECS_RFM_OUT_INTR5 (175+305) +#define JECS_RFM_OUT_INTR6 (175+306) +#define JECS_RFM_OUT_INTR7 (175+307) +#define JECS_RFM_OUT_INTR8 (175+308) +#define JECS_RFM_OUT_INTR9 (175+309) +#define JECS_RFM_OUT_INTR10 (175+310) +#define JECS_RFM_OUT_INTR11 (175+311) +#define JECS_RFM_OUT_INTR12 (175+312) +#define JECS_RFM_OUT_INTR13 (175+313) +#define JECS_RFM_OUT_INTR14 (175+314) +#define JECS_RFM_OUT_INTR15 (175+315) +#define JECS_RFM_OUT_INTR16 (175+316) +#define JECS_RFM_OUT_INTR17 (175+317) +#define JECS_RFM_OUT_INTR18 (175+318) +#define JECS_RFM_OUT_INTR19 (175+319) +#define RFC_INTR0 (175+320) +#define RFC_INTR1 (175+321) +#define RFC_INTR2 (175+322) +#define RFCSU_RX_INTR (175+323) +#define RFCSU_TX_INTR (175+324) + +#define JESD_RX0_SBU0_TMR_INTR0 (175+162+325-162) +#define JESD_RX0_SBU0_TMR_INTR1 (175+163+325-162) +#define JESD_RX0_SBU0_TMR_INTR2 (175+164+325-162) +#define JESD_RX0_SBU0_TMR_INTR3 (175+165+325-162) +#define JESD_RX0_SBU0_TMR_INTR4 (175+166+325-162) +#define JESD_RX0_SBU0_TMR_INTR5 (175+167+325-162) +#define JESD_RX0_SBU0_TMR_INTR6 (175+168+325-162) +#define JESD_RX0_SBU0_TMR_INTR7 (175+169+325-162) +#define JESD_RX0_SBU0_TMR_INTR8 (175+170+325-162) +#define JESD_RX0_SBU0_TMR_INTR9 (175+171+325-162) +#define JESD_RX0_SBU0_TMR_INTR10 (175+172+325-162) +#define JESD_RX0_SBU0_TMR_INTR11 (175+173+325-162) +//#define JESD_RX0_SBU1_TMR_INTR0 (175+162+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR1 (175+163+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR2 (175+164+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR3 (175+165+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR4 (175+166+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR5 (175+167+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR6 (175+168+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR7 (175+169+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR8 (175+170+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR9 (175+171+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR10 (175+172+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR11 (175+173+424-162)tie 0 +#define JESD_RX1_SBU0_TMR_INTR0 (175+162+436-162) +#define JESD_RX1_SBU0_TMR_INTR1 (175+163+436-162) +#define JESD_RX1_SBU0_TMR_INTR2 (175+164+436-162) +#define JESD_RX1_SBU0_TMR_INTR3 (175+165+436-162) +#define JESD_RX1_SBU0_TMR_INTR4 (175+166+436-162) +#define JESD_RX1_SBU0_TMR_INTR5 (175+167+436-162) +#define JESD_RX1_SBU0_TMR_INTR6 (175+168+436-162) +#define JESD_RX1_SBU0_TMR_INTR7 (175+169+436-162) +#define JESD_RX1_SBU0_TMR_INTR8 (175+170+436-162) +#define JESD_RX1_SBU0_TMR_INTR9 (175+171+436-162) +#define JESD_RX1_SBU0_TMR_INTR10 (175+172+436-162) +#define JESD_RX1_SBU0_TMR_INTR11 (175+173+436-162) +//#define JESD_RX1_SBU1_TMR_INTR0 (175+162+448-162) +//#define JESD_RX1_SBU1_TMR_INTR1 (175+163+448-162) +//#define JESD_RX1_SBU1_TMR_INTR2 (175+164+448-162) +//#define JESD_RX1_SBU1_TMR_INTR3 (175+165+448-162) +//#define JESD_RX1_SBU1_TMR_INTR4 (175+166+448-162) +//#define JESD_RX1_SBU1_TMR_INTR5 (175+167+448-162) +//#define JESD_RX1_SBU1_TMR_INTR6 (175+168+448-162) +//#define JESD_RX1_SBU1_TMR_INTR7 (175+169+448-162) +//#define JESD_RX1_SBU1_TMR_INTR8 (175+170+448-162) +//#define JESD_RX1_SBU1_TMR_INTR9 (175+171+448-162) +//#define JESD_RX1_SBU1_TMR_INTR10 (175+172+448-162) +//#define JESD_RX1_SBU1_TMR_INTR11 (175+173+448-162) +#define SLAVE_INTERRUPT_204B_RX0 (175+337) +#define SLAVE_INTERRUPT_204B_RX1 (175+339) +#define SLAVE_INTERRUPT_204B_TX0 (175+341) +#define SLAVE_INTERRUPT_204C_RX0 (175+368) +#define SLAVE_INTERRUPT_204C_RX1 (175+369) +#define SLAVE_INTERRUPT_204C_TX0 (175+370) +#define JECS_CTC_INTR0 (175+343) +#define JECS_CTC_INTR1 (175+344) +#define PET_CTC_INTR0 (175+345) +#define PET_CTC_INTR1 (175+346) +#define EIP2_RING2_INT (175+347) +#define EIP2_RING3_INT (175+348) +#define RFC_DMA_INTR (175+349) +#define JESDA_CSU_INTR (175+350) +#define JESDA_CSU_TX_INTR (175+351) +#define JECS_CSU_INTR (175+352) +#define JESDB_CSU_TX_INTR (175+353) +#define ECPRI_SUB_INTR0 (175+360) +#define ECPRI_SUB_INTR1 (175+361) +#define ECPRI_SUB_INTR2 (175+362) +#define ECPRI_SUB_INTR3 (175+363) +#define ECPRI_SUB_INTR4 (175+364) +#define ECPRI_SUB_INTR5 (175+365) +//#define ECPRI_SUB_INTR6 (175+366) +//#define ECPRI_SUB_INTR7 (175+367) +#define JESD_204B_SUBCTRL_INTR (175+366) +#define JESD_204C_SUBCTRL_INTR (175+367) +//#define ECPRI_SUB_INTR8 (175+368) +//#define ECPRI_SUB_INTR9 (175+369) +//#define ECPRI_SUB_INTR10 (175+370) +#define ECPRI_SUB_INTR11 (175+371) +#define ECPRI_SUB_INTR12 (175+372) +#define ECPRI_SUB_INTR13 (175+373) +#define ECPRI_SUB_INTR14 (175+374) +#define ECPRI_SUB_INTR15 (175+375) +#define ECPRI_SUB_INTR16 (175+376) +#define ECPRI_SUB_INTR17 (175+377) +#define ECPRI_SUB_INTR18 (175+378) +#define ECPRI_SUB_INTR19 (175+379) +#define ECPRI_SUB_INTR20 (175+380) +#define ECPRI_SUB_INTR21 (175+381) +#define ECPRI_SUB_INTR22 (175+382) +#define ECPRI_SUB_INTR23 (175+383) +#define ECPRI_SUB_INTR24 (175+384) +#define ECPRI_SUB_INTR25 (175+385) +#define ECPRI_SUB_INTR26 (175+386) +#define ECPRI_SUB_INTR27 (175+387) +#define ECPRI_SUB_INTR28 (175+388) +#define ECPRI_SUB_INTR29 (175+389) +#define ECPRI_SUB_INTR30 (175+390) +#define ECPRI_SUB_INTR31 (175+391) +#define CPRI_SUB_INTR0 (175+392) +#define CPRI_SUB_INTR1 (175+393) +#define STC_INTR0 (175+394) +#define STC_INTR1 (175+395) +#define STC_INTR2 (175+396) +#define STC_INTR3 (175+397) +#define STC_INTR4 (175+398) +#define STC_INTR5 (175+399) +#define STC_INTR6 (175+400) +#define STC_INTR7 (175+401) +#define STC_INTR8 (175+402) +#define STC_INTR9 (175+403) +#define STC_INTR10 (175+404) + +#define CPRI_TMR_INTR0 (175+405) +#define CPRI_TMR_INTR1 (175+406) +#define CPRI_TMR_INTR2 (175+407) +#define CPRI_TMR_INTR3 (175+408) +#define CPRI_TMR_INTR4 (175+409) +#define CPRI_TMR_INTR5 (175+410) +#define CPRI_TMR_INTR6 (175+411) +#define CPRI_TMR_INTR7 (175+412) +#define CPRI_TMR_INTR8 (175+413) +#define CPRI_TMR_INTR9 (175+414) +#define CPRI_TMR_INTR10 (175+415) +#define CPRI_TMR_INTR11 (175+416) +#define APC3OUT_INTR0 (175+260) +#define APC3OUT_INTR1 (175+261) +#define APC3OUT_INTR2 (175+262) +#define APC3OUT_INTR3 (175+263) +#define APC3OUT_INTR4 (175+264) +#define APC3OUT_INTR5 (175+265) +#define APC3OUT_INTR6 (175+266) +#define APC3OUT_INTR7 (175+267) +#define APC3OUT_INTR8 (175+268) +#define APC3OUT_INTR9 (175+269) +#define APC3OUT_INTR10 (175+270) +#define APC3OUT_INTR11 (175+271) +#define APC3OUT_INTR12 (175+272) +#define APC3OUT_INTR13 (175+273) +#define APC3OUT_INTR14 (175+274) +#define APC3OUT_INTR15 (175+275) +#define APC3OUT_INTR16 (175+276) +#define APC3OUT_INTR17 (175+277) +#define APC3OUT_INTR18 (175+278) +#define APC3OUT_INTR19 (175+279) +#define APC2OUT_INTR0 (175+240) +#define APC2OUT_INTR1 (175+241) +#define APC2OUT_INTR2 (175+242) +#define APC2OUT_INTR3 (175+243) +#define APC2OUT_INTR4 (175+244) +#define APC2OUT_INTR5 (175+245) +#define APC2OUT_INTR6 (175+246) +#define APC2OUT_INTR7 (175+247) +#define APC2OUT_INTR8 (175+248) +#define APC2OUT_INTR9 (175+249) +#define APC2OUT_INTR10 (175+250) +#define APC2OUT_INTR11 (175+251) +#define APC2OUT_INTR12 (175+252) +#define APC2OUT_INTR13 (175+253) +#define APC2OUT_INTR14 (175+254) +#define APC2OUT_INTR15 (175+255) +#define APC2OUT_INTR16 (175+256) +#define APC2OUT_INTR17 (175+257) +#define APC2OUT_INTR18 (175+258) +#define APC2OUT_INTR19 (175+259) +#define APC1OUT_INTR0 (175+220) +#define APC1OUT_INTR1 (175+221) +#define APC1OUT_INTR2 (175+222) +#define APC1OUT_INTR3 (175+223) +#define APC1OUT_INTR4 (175+224) +#define APC1OUT_INTR5 (175+225) +#define APC1OUT_INTR6 (175+226) +#define APC1OUT_INTR7 (175+227) +#define APC1OUT_INTR8 (175+228) +#define APC1OUT_INTR9 (175+229) +#define APC1OUT_INTR10 (175+230) +#define APC1OUT_INTR11 (175+231) +#define APC1OUT_INTR12 (175+232) +#define APC1OUT_INTR13 (175+233) +#define APC1OUT_INTR14 (175+234) +#define APC1OUT_INTR15 (175+235) +#define APC1OUT_INTR16 (175+236) +#define APC1OUT_INTR17 (175+237) +#define APC1OUT_INTR18 (175+238) +#define APC1OUT_INTR19 (175+239) +#define APC0OUT_INTR0 (175+200) +#define APC0OUT_INTR1 (175+201) +#define APC0OUT_INTR2 (175+202) +#define APC0OUT_INTR3 (175+203) +#define APC0OUT_INTR4 (175+204) +#define APC0OUT_INTR5 (175+205) +#define APC0OUT_INTR6 (175+206) +#define APC0OUT_INTR7 (175+207) +#define APC0OUT_INTR8 (175+208) +#define APC0OUT_INTR9 (175+209) +#define APC0OUT_INTR10 (175+210) +#define APC0OUT_INTR11 (175+211) +#define APC0OUT_INTR12 (175+212) +#define APC0OUT_INTR13 (175+213) +#define APC0OUT_INTR14 (175+214) +#define APC0OUT_INTR15 (175+215) +#define APC0OUT_INTR16 (175+216) +#define APC0OUT_INTR17 (175+217) +#define APC0OUT_INTR18 (175+218) +#define APC0OUT_INTR19 (175+219) +#define UART3_INTR (175+197) +#define UART2_INTR (175+196) +#define TIMER27_INTR (175+195) +#define TIMER26_INTR (175+194) +#define TIMER25_INTR (175+193) +#define TIMER24_INTR (175+192) +#define TIMER23_INTR (175+191) +#define TIMER22_INTR (175+190) +#define TIMER21_INTR (175+189) +#define TIMER20_INTR (175+188) +#define TIMER17_INTR (175+187) +#define TIMER16_INTR (175+186) +#define TIMER15_INTR (175+185) +#define TIMER14_INTR (175+184) +#define TIMER13_INTR (175+183) +#define TIMER12_INTR (175+182) +#define TIMER11_INTR (175+181) +#define TIMER10_INTR (175+180) +#define SPI3_INTR (175+179) +#define SPI2_INTR (175+178) +//175+174 175+177 tie 0 +#define JESD_TX0_SBU0_TMR_INTR0 (175+162) +#define JESD_TX0_SBU0_TMR_INTR1 (175+163) +#define JESD_TX0_SBU0_TMR_INTR2 (175+164) +#define JESD_TX0_SBU0_TMR_INTR3 (175+165) +#define JESD_TX0_SBU0_TMR_INTR4 (175+166) +#define JESD_TX0_SBU0_TMR_INTR5 (175+167) +#define JESD_TX0_SBU0_TMR_INTR6 (175+168) +#define JESD_TX0_SBU0_TMR_INTR7 (175+169) +#define JESD_TX0_SBU0_TMR_INTR8 (175+170) +#define JESD_TX0_SBU0_TMR_INTR9 (175+171) +#define JESD_TX0_SBU0_TMR_INTR10 (175+172) +#define JESD_TX0_SBU0_TMR_INTR11 (175+173) +#define JESD_TX_SBU1_TMR_INTR0 (175+174) +#define JESD_TX_SBU1_TMR_INTR1 (175+175) +#define JESD_TX_SBU1_TMR_INTR2 (175+176) +#define JESD_TX_SBU1_TMR_INTR3 (175+177) +#define JESD_TX_SBU1_TMR_INTR4 (175+198) +#define JESD_TX_SBU1_TMR_INTR5 (175+199) +#define JESD_TX_SBU1_TMR_INTR6 (175+354) +#define JESD_TX_SBU1_TMR_INTR7 (175+355) +#define JESD_TX_SBU1_TMR_INTR8 (175+356) +#define JESD_TX_SBU1_TMR_INTR9 (175+357) +#define JESD_TX_SBU1_TMR_INTR10 (175+358) +#define JESD_TX_SBU1_TMR_INTR11 (175+359) + +#define JESD_TX1_SBU0_TMR_INTR0 (175+371) +#define JESD_TX1_SBU0_TMR_INTR1 (175+372) +#define JESD_TX1_SBU0_TMR_INTR2 (175+373) +#define JESD_TX1_SBU0_TMR_INTR3 (175+374) +#define JESD_TX1_SBU0_TMR_INTR4 (175+375) +#define JESD_TX1_SBU0_TMR_INTR5 (175+376) +#define JESD_TX1_SBU0_TMR_INTR6 (175+377) +#define JESD_TX1_SBU0_TMR_INTR7 (175+378) +#define JESD_TX1_SBU0_TMR_INTR8 (175+379) +#define JESD_TX1_SBU0_TMR_INTR9 (175+380) +#define JESD_TX1_SBU0_TMR_INTR10 (175+381) +#define JESD_TX1_SBU0_TMR_INTR11 (175+382) + + +#define MBX1_LPRI_INTR24 (175+164-16) +#define MBX1_LPRI_INTR25 (175+165-16) +#define MBX1_LPRI_INTR26 (175+166-16) +#define MBX1_LPRI_INTR27 (175+167-16) +#define MBX1_LPRI_INTR28 (175+168-16) +#define MBX1_LPRI_INTR29 (175+169-16) +#define MBX1_LPRI_INTR30 (175+170-16) +#define MBX1_LPRI_INTR31 (175+171-16) +#define MBX1_LPRI_INTR32 (175+172-16) +#define MBX1_LPRI_INTR33 (175+173-16) +#define MBX1_LPRI_INTR34 (175+174-16) +#define MBX1_LPRI_INTR35 (175+175-16) +#define MBX1_LPRI_INTR36 (175+176-16) +#define MBX1_LPRI_INTR37 (175+177-16) + + +#define MBX1_HPRI_INTR24 (175+146-12) +#define MBX1_HPRI_INTR25 (175+147-12) +#define MBX1_HPRI_INTR26 (175+148-12) +#define MBX1_HPRI_INTR27 (175+149-12) +#define MBX1_HPRI_INTR28 (175+150-12) +#define MBX1_HPRI_INTR29 (175+151-12) +#define MBX1_HPRI_INTR30 (175+152-12) +#define MBX1_HPRI_INTR31 (175+153-12) +#define MBX1_HPRI_INTR32 (175+154-12) +#define MBX1_HPRI_INTR33 (175+155-12) +#define MBX1_HPRI_INTR34 (175+156-12) +#define MBX1_HPRI_INTR35 (175+157-12) +#define MBX1_HPRI_INTR36 (175+158-12) +#define MBX1_HPRI_INTR37 (175+159-12) + +#define MBX0_LPRI_INTR24 (175+128-8) +#define MBX0_LPRI_INTR25 (175+129-8) +#define MBX0_LPRI_INTR26 (175+130-8) +#define MBX0_LPRI_INTR27 (175+131-8) +#define MBX0_LPRI_INTR28 (175+132-8) +#define MBX0_LPRI_INTR29 (175+133-8) +#define MBX0_LPRI_INTR30 (175+134-8) +#define MBX0_LPRI_INTR31 (175+135-8) +#define MBX0_LPRI_INTR32 (175+136-8) +#define MBX0_LPRI_INTR33 (175+137-8) +#define MBX0_LPRI_INTR34 (175+138-8) +#define MBX0_LPRI_INTR35 (175+139-8) +#define MBX0_LPRI_INTR36 (175+140-8) +#define MBX0_LPRI_INTR37 (175+141-8) + +#define MBX0_HPRI_INTR24 (175+110-4) +#define MBX0_HPRI_INTR25 (175+111-4) +#define MBX0_HPRI_INTR26 (175+112-4) +#define MBX0_HPRI_INTR27 (175+113-4) +#define MBX0_HPRI_INTR28 (175+114-4) +#define MBX0_HPRI_INTR29 (175+115-4) +#define MBX0_HPRI_INTR30 (175+116-4) +#define MBX0_HPRI_INTR31 (175+117-4) +#define MBX0_HPRI_INTR32 (175+118-4) +#define MBX0_HPRI_INTR33 (175+119-4) +#define MBX0_HPRI_INTR34 (175+120-4) +#define MBX0_HPRI_INTR35 (175+121-4) +#define MBX0_HPRI_INTR36 (175+122-4) +#define MBX0_HPRI_INTR37 (175+123-4) +#define GPIO1_INTR0 (175+74) +#define GPIO1_INTR1 (175+75) +#define GPIO1_INTR2 (175+76) +#define GPIO1_INTR3 (175+77) +#define GPIO1_INTR4 (175+78) +#define GPIO1_INTR5 (175+79) +#define GPIO1_INTR6 (175+80) +#define GPIO1_INTR7 (175+81) +#define GPIO1_INTR8 (175+82) +#define GPIO1_INTR9 (175+83) +#define GPIO1_INTR10 (175+84) +#define GPIO1_INTR11 (175+85) +#define GPIO1_INTR12 (175+86) +#define GPIO1_INTR13 (175+87) +#define GPIO1_INTR14 (175+88) +#define GPIO1_INTR15 (175+89) +#define GPIO1_INTR16 (175+90) +#define GPIO1_INTR17 (175+91) +#define GPIO1_INTR18 (175+92) +#define GPIO1_INTR19 (175+93) +#define GPIO1_INTR20 (175+94) +#define GPIO1_INTR21 (175+95) +#define GPIO1_INTR22 (175+96) +#define GPIO1_INTR23 (175+97) +#define GPIO1_INTR24 (175+98) +#define GPIO1_INTR25 (175+99) +#define GPIO1_INTR26 (175+100) +#define GPIO1_INTR27 (175+101) +#define GPIO1_INTR28 (175+102) +#define GPIO1_INTR29 (175+103) +#define GPIO1_INTR30 (175+104) +#define GPIO1_INTR31 (175+105) +#define DMAS1_INTR (175+73) +#define DPLL_LOCK_INTR (175+72) +#define CPSM_FULL7_INTR (175+71) +#define CPSM_FULL6_INTR (175+70) +#define CPSM_FULL5_INTR (175+69) +#define CPSM_FULL4_INTR (175+68) +#define CPSM_FULL3_INTR (175+67) +#define CPSM_FULL2_INTR (175+66) +#define CPSM_FULL1_INTR (175+65) +#define CPSM_FULL0_INTR (175+64) +#define CPSM_EMPTY7_INTR (175+63) +#define CPSM_EMPTY6_INTR (175+62) +#define CPSM_EMPTY5_INTR (175+61) +#define CPSM_EMPTY4_INTR (175+60) +#define CPSM_EMPTY3_INTR (175+59) +#define CPSM_EMPTY2_INTR (175+58) +#define CPSM_EMPTY1_INTR (175+57) +#define CPSM_EMPTY0_INTR (175+56) +#define JECSSM_FULL7_INTR (175+54+1) +#define JECSSM_FULL6_INTR (175+53+1) +#define JECSSM_FULL5_INTR (175+52+1) +#define JECSSM_FULL4_INTR (175+51+1) +#define JECSSM_FULL3_INTR (175+50+1) +#define JECSSM_FULL2_INTR (175+49+1) +#define JECSSM_FULL1_INTR (175+48+1) +#define JECSSM_FULL0_INTR (175+47+1) +#define JECSSM_EMPTY7_INTR (175+46+1) +#define JECSSM_EMPTY6_INTR (175+45+1) +#define JECSSM_EMPTY5_INTR (175+44+1) +#define JECSSM_EMPTY4_INTR (175+43+1) +#define JECSSM_EMPTY3_INTR (175+42+1) +#define JECSSM_EMPTY2_INTR (175+41+1) +#define JECSSM_EMPTY1_INTR (175+40+1) +#define JECSSM_EMPTY0_INTR (175+39+1) +#define PETSM_FULL7_INTR (175+38+1) +#define PETSM_FULL6_INTR (175+37+1) +#define PETSM_FULL5_INTR (175+36+1) +#define PETSM_FULL4_INTR (175+35+1) +#define PETSM_FULL3_INTR (175+34+1) +#define PETSM_FULL2_INTR (175+33+1) +#define PETSM_FULL1_INTR (175+32+1) +#define PETSM_FULL0_INTR (175+31+1) +#define PETSM_EMPTY7_INTR (175+30+1) +#define PETSM_EMPTY6_INTR (175+29+1) +#define PETSM_EMPTY5_INTR (175+28+1) +#define PETSM_EMPTY4_INTR (175+27+1) +#define PETSM_EMPTY3_INTR (175+26+1) +#define PETSM_EMPTY2_INTR (175+25+1) +#define PETSM_EMPTY1_INTR (175+24+1) +#define PETSM_EMPTY0_INTR (175+23+1) +#define ES_ETHPLL_LOCK_INTR (175+23) +#define EIP2_RING0_INT (175+21) +#define EIP2_RING1_INT (175+22) +#define PET_TMAC_INTR (175+20) +#define PET_PCIE_INTR (175+19) +#define PEREST_INTR (175+383) +#define EIP2_GLOBLE_INT (175+18) +#define SRIO1_RAB_INTR (175+17) +#define SRIO0_RAB_INTR (175+16) +#define JSSM_FULL7_INTR (175+15) +#define JSSM_FULL6_INTR (175+14) +#define JSSM_FULL5_INTR (175+13) +#define JSSM_FULL4_INTR (175+12) +#define JSSM_FULL3_INTR (175+11) +#define JSSM_FULL2_INTR (175+10) +#define JSSM_FULL1_INTR (175+9) +#define JSSM_FULL0_INTR (175+8) +#define JSSM_EMPTY7_INTR (175+7) +#define JSSM_EMPTY6_INTR (175+6) +#define JSSM_EMPTY5_INTR (175+5) +#define JSSM_EMPTY4_INTR (175+4) +#define JSSM_EMPTY3_INTR (175+3) +#define JSSM_EMPTY2_INTR (175+2) +#define JSSM_EMPTY1_INTR (175+1) +#define JSSM_EMPTY0_INTR (175+0) +#define TRNG_INTR 174 +#define SPACC0_INTR 173 +#define PKA_INTR 172 +#define SYSC_CTC9_INTR1 171 +#define SYSC_CTC9_INTR0 170 +#define SYSC_CTC8_INTR1 169 +#define SYSC_CTC8_INTR0 168 +#define SYSC_CTC7_INTR1 167 +#define SYSC_CTC7_INTR0 166 +#define SYSC_CTC6_INTR1 165 +#define SYSC_CTC6_INTR0 164 +#define SYSC_CTC5_INTR1 163 +#define SYSC_CTC5_INTR0 162 +#define SYSC_CTC4_INTR1 161 +#define SYSC_CTC4_INTR0 160 +#define SYSC_CTC3_INTR1 159 +#define SYSC_CTC3_INTR0 158 +#define SYSC_CTC2_INTR1 157 +#define SYSC_CTC2_INTR0 156 +#define SYSC_CTC1_INTR1 155 +#define SYSC_CTC1_INTR0 154 +#define SYSC_CTC0_INTR1 153 +#define SYSC_CTC0_INTR0 152 +#define SYSCTRL_INTR 151 +#define SDIOH_INTR 150 +#define PVT_INTR 149 +#define SMMU_S_INTR 148 +#define SMMU_NS_INTR 147 +#define GICECCFATAL_INTR 146 +#define GICAXIERR_INTR 145 +#define CCINERR_INTR 144 +//112-143 tie0 +#define WDT1_INTR 111 +#define WDT0_INTR 110 +#define USB_INTR 109 +#define UART1_INTR 108 +#define UART0_INTR 107 +#define TIMER07_INTR 106 +#define TIMER06_INTR 105 +#define TIMER05_INTR 104 +#define TIMER04_INTR 103 +#define TIMER03_INTR 102 +#define TIMER02_INTR 101 +#define TIMER01_INTR 100 +#define TIMER00_INTR 99 +#define SPI1_INTR 98 +#define SPI0_INTR 97 +#define RTC_INTR 96 +#define I2C1_INTR 95 +#define I2C0_INTR 94 +#define GPIO0_INTR0 62 +#define GPIO0_INTR1 63 +#define GPIO0_INTR2 64 +#define GPIO0_INTR3 65 +#define GPIO0_INTR4 66 +#define GPIO0_INTR5 67 +#define GPIO0_INTR6 68 +#define GPIO0_INTR7 69 +#define GPIO0_INTR8 70 +#define GPIO0_INTR9 71 +#define GPIO0_INTR10 72 +#define GPIO0_INTR11 73 +#define GPIO0_INTR12 74 +#define GPIO0_INTR13 75 +#define GPIO0_INTR14 76 +#define GPIO0_INTR15 77 +#define GPIO0_INTR16 78 +#define GPIO0_INTR17 79 +#define GPIO0_INTR18 80 +#define GPIO0_INTR19 81 +#define GPIO0_INTR20 82 +#define GPIO0_INTR21 83 +#define GPIO0_INTR22 84 +#define GPIO0_INTR23 85 +#define GPIO0_INTR24 86 +#define GPIO0_INTR25 87 +#define GPIO0_INTR26 88 +#define GPIO0_INTR27 89 +#define GPIO0_INTR28 90 +#define GPIO0_INTR29 91 +#define GPIO0_INTR30 92 +#define GPIO0_INTR31 93 +//53 - 61 tie 0 +#define EIP0_GLOBLE_INT 43 +#define EIP0_RING0_INT 44 +#define EIP0_RING1_INT 45 +#define EIP0_RING2_INT 46 +#define EIP0_RING3_INT 47 +#define EIP1_GLOBLE_INT 48 +#define EIP1_RING0_INT 49 +#define EIP1_RING1_INT 50 +#define EIP1_RING2_INT 51 +#define EIP1_RING3_INT 52 +//#define SPACC1_INTR 38 TIE0 +//#define SPACC2_INTR 39 TIE0 +//#define SPACC3_INTR 40 TIE0 +#define A72NEXTERR_INTR_1 42 +#define A72NINTERR_INTR_1 41 +#define APCSU_INTR0 30 +#define APCSU_INTR1 31 +#define APCSU_INTR2 32 +#define APCSU_INTR3 33 +#define APCSU_INTR4 34 +#define APCSU_INTR5 35 +#define APCSU_INTR6 36 +#define APCSU_INTR7 37 +#define GMAC1SDB_INTR 29 +#define GMAC1PMT_INTR 28 +#define GMAC1LPI_INTR 27 +#define GMAC0SDB_INTR 26 +#define GMAC0PMT_INTR 25 +#define GMAC0LPI_INTR 24 +#define EFUSE_INTR 23 +#define DDRPHY_INTR 22 +#define DDRC_INTR 21 +#define DMAS0_INTR 20 +//#define CSUDMA_INTR 19 tie 0 +#define CRG_INTR 18 +#define APSM1_FULL7_INTR 17 +#define APSM1_FULL6_INTR 16 +#define APSM1_FULL5_INTR 15 +#define APSM1_FULL4_INTR 14 +#define APSM1_FULL3_INTR 13 +#define APSM1_FULL2_INTR 12 +#define APSM1_FULL1_INTR 11 +#define APSM1_FULL0_INTR 10 +#define APSM1_EMPTY7_INTR 9 +#define APSM1_EMPTY6_INTR 8 +#define APSM1_EMPTY5_INTR 7 +#define APSM1_EMPTY4_INTR 6 +#define APSM1_EMPTY3_INTR 5 +#define APSM1_EMPTY2_INTR 4 +#define APSM1_EMPTY1_INTR 3 +#define APSM1_EMPTY0_INTR 2 +#define A72NEXTERR_INTR 1 +#define A72NINTERR_INTR 0 + +extern void wno_unused_myheadername(void); + +#endif /* End of __IO_UCP_H */ diff --git a/driver/rfic/rf/api/inc/ucp_reg_io.h b/driver/rfic/rf/api/inc/ucp_reg_io.h new file mode 100644 index 0000000..57f9172 --- /dev/null +++ b/driver/rfic/rf/api/inc/ucp_reg_io.h @@ -0,0 +1,39 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_reg_io.h +// Author : boheng.lin@smartlogictech.com +// Date First Issued : 2022-09-08 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef __UCP_REG_IO__ +#define __UCP_REG_IO__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern int ucp_reg_init (void); +extern void ucp_reg32_or_write(uint64_t reg, uint32_t mask); +extern void ucp_reg32_and_write(uint64_t reg, uint32_t mask); +extern uint32_t ucp_reg32_and_read(uint64_t reg, uint32_t mask); +extern void ucp_reg16_write(uint64_t reg, uint16_t data); +extern uint16_t ucp_reg16_read(uint64_t reg); +extern void ucp_reg32_write(uint64_t reg, uint32_t data); +extern uint32_t ucp_reg32_read(uint64_t reg); + +extern void ucp_reg_test(void); + +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/driver/rfic/rf/api/inc/ucp_rfic_gpio.h b/driver/rfic/rf/api/inc/ucp_rfic_gpio.h new file mode 100644 index 0000000..3edd821 --- /dev/null +++ b/driver/rfic/rf/api/inc/ucp_rfic_gpio.h @@ -0,0 +1,51 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_rfic_gpio.h +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-10-18 10:02:00 AM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef UCP_RFIC_GPIO_H_ +#define UCP_RFIC_GPIO_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +enum { + // trx + GPIO_INDEX_9025RESET = 40, + GPIO_INDEX_9025CS, + + // clock Gen + GPIO_INDEX_9528RESET, + GPIO_INDEX_9528CS, + GPIO_INDEX_SYSREF, + GPIO_INDEX_9528STATUS0, + GPIO_INDEX_9528STATUS1, + + // HW_EVMT & HW_EVMY + GPIO_INDEX_SWCAL, + GPIO_INDEX_ORX0CTRL, + GPIO_INDEX_ORX1CTRL, + GPIO_INDEX_LNAVPD, + + // HW_EVMY + GPIO_INDEX_SPI1_SEL, + GPIO_INDEX_SPI3_SEL, + GPIO_INDEX_PLL_SEL +}; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef UCP_RFIC_GPIO_H_ */ diff --git a/driver/rfic/rf/api/makefile b/driver/rfic/rf/api/makefile new file mode 100644 index 0000000..0682c2d --- /dev/null +++ b/driver/rfic/rf/api/makefile @@ -0,0 +1,30 @@ +LIB_API = libapi.a +#CC = aarch64-linux-gnu-gcc + +API_SRC = ./src +ARFLAGS = -rv +CFLAGS = -Wall -I./inc -I./src \ + -I../adrv9025/c_src/platforms \ + -I../adrv9025/c_src/common/adi_error \ + -I../adrv9025/c_src/common/adi_hal \ + -I../adrv9025/c_src/common/adi_logging \ + -I../adrv9025/c_src/common \ + -I../adrv9025/c_src/app/example \ + -I../adrv9025/c_src/devices/adrv9025/public/include \ + -I../ucp/inc -Werror +EXT = c + +SRC = $(wildcard $(API_SRC)/*.$(EXT)) +OBJS = $(SRC:.$(EXT)=.o) + +all: $(LIB_API) + +.$(EXT).o: + $(CC) $(CFLAGS) -o $@ -c $< + +$(LIB_API): $(OBJS) + ar $(ARFLAGS) $(LIB_API) $(OBJS) + +clean: + rm -rf $(API_SRC)/*.o + rm -rf *.a \ No newline at end of file diff --git a/driver/rfic/rf/api/src/ucp_api_clockGen.c b/driver/rfic/rf/api/src/ucp_api_clockGen.c new file mode 100644 index 0000000..34c4965 --- /dev/null +++ b/driver/rfic/rf/api/src/ucp_api_clockGen.c @@ -0,0 +1,42 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_api_clockGen.c +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-03-04 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#include +#include "adi_ad9528Lib.h" +#include "adi_adrv9025Lib.h" + +void UCP_API_CLOCKGEN_Reset(void) +{ + ucp_api_ad9528_Reset(); + return; +} + +int32_t UCP_API_CLOCKGEN_Init(void) +{ + int32_t ret; + + ret = ucp_api_ad9528_Init(); + + return ret; +} + +uint8_t UCP_API_CLOCKGEN_LockStatus(void) +{ + return ucp_api_ad9528_LockStatus(); +} + +void UCP_API_CLOCKGEN_OnePluse(uint8_t enable) +{ + ucp_api_ad9528_OnePluse(enable); + return; +} + diff --git a/driver/rfic/rf/api/src/ucp_api_rfic.c b/driver/rfic/rf/api/src/ucp_api_rfic.c new file mode 100644 index 0000000..c72864e --- /dev/null +++ b/driver/rfic/rf/api/src/ucp_api_rfic.c @@ -0,0 +1,371 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_api_clockGen.c +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-03-04 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#include +#include +#include "ucp_api_transceiver.h" +#include "ucp_api_jesd.h" +#include "ucp_api_rfic.h" +#include "ucp_jesd_gpio.h" +#include "ucp_rfic_gpio.h" +#include "initdata.h" + +#define UCP_TXR_CONFIG_FILE "/lib/firmware/resources/ucp_trx_gpioCfg.json" +#define NR_BW (100000000u) +#define MAX_BOARD 5 + +extern ucp_jesd_Init_t ucpJesdInitInstNr; +extern ucp_jesd_Init_t ucpJesdInitInstNr_bandwidth200M; +extern ucp_jesd_Init_t ucpJesdInitInstNrFdd2Ant; +extern ucp_jesd_Init_t ucpJesdInitInstLte2Ant; +extern ucp_jesd_Init_t ucpJesdInitInstLte4Ant; +extern ucp_jesd_Init_t ucpJesdInitInstNr_orx; +extern ucp_jesd_Init_t ucpJesdInitInstNr204C; + +typedef struct tRficConfigList { + char *item; + uint64_t sampleRate; + uint64_t bw; + uint16_t antNumb; + uint16_t enFdd; + uint16_t enOrx; + uint16_t en204C; + void *ucpInitStru; + void *adiInitStru; + void *adiPostMcsStru; +} tRficConfigList_t; + +const char *boardTypeString[MAX_BOARD] = +{ + "Unknow\0", + "EVMT\0", + "EVMF\0", + "EVB\0", + "EVMY\0" +}; + +tRficConfigList_t gRficConfigList[] = { + {"122.88M/100M/4ANT/TDD/NORX/204B", CFG_SAMPLERATE_122_88MHZ, CFG_BW_100MHZ, CFG_4ANT, CFG_TDD, CFG_NORX, CFG_204B, (void*)&ucpJesdInitInstNr, (void*)&deviceInitInst_122_88M_4_9152G, (void*)&devicePostMcsInitInst_122_88M_4_9152G}, + {"122.88M/100M/4ANT/TDD/TORX/204B", CFG_SAMPLERATE_122_88MHZ, CFG_BW_100MHZ, CFG_4ANT, CFG_TDD, CFG_TLO_ORX, CFG_204B, (void*)&ucpJesdInitInstNr_orx, (void*)&deviceInitInst_122_88M_9_8304G_ORX, (void*)&devicePostMcsInitInst_122_88M_9_8304G_ORX}, + {"122.88M/100M/4ANT/TDD/AORX/204B", CFG_SAMPLERATE_122_88MHZ, CFG_BW_100MHZ, CFG_4ANT, CFG_TDD, CFG_ALO_ORX, CFG_204B, (void*)&ucpJesdInitInstNr_orx, (void*)&deviceInitInst_122_88M_9_8304G_ORX, (void*)&devicePostMcsInitInst_122_88M_9_8304G_ORX}, + {"245.76M/200M/4ANT/TDD/NORX/204B", CFG_SAMPLERATE_245_76MHZ, CFG_BW_200MHZ, CFG_4ANT, CFG_TDD, CFG_NORX, CFG_204B, (void*)&ucpJesdInitInstNr_bandwidth200M, (void*)&deviceInitInst_245_76M_9_8304G, (void*)&devicePostMcsInitInst_245_76M_9_8304G}, + {"122.88M/100M/2ANT/FDD/NORX/204B", CFG_SAMPLERATE_122_88MHZ, CFG_BW_100MHZ, CFG_2ANT, CFG_FDD, CFG_NORX, CFG_204B, (void*)&ucpJesdInitInstNrFdd2Ant, (void*)&deviceInitInst_122_88M_4_9152G_FDD2ANT, (void*)&devicePostMcsInitInst_122_88M_4_9152G_FDD2ANT}, + {"122.88M/100M/4ANT/FDD/NORX/204B", CFG_SAMPLERATE_122_88MHZ, CFG_BW_100MHZ, CFG_4ANT, CFG_FDD, CFG_NORX, CFG_204B, (void*)&ucpJesdInitInstNr, (void*)&deviceInitInst_122_88M_4_9152G, (void*)&devicePostMcsInitInst_122_88M_4_9152G}, + {"61.44M/50M/2ANT/FDD/NORX/204B", CFG_SAMPLERATE_61_44MHZ, CFG_BW_50MHZ, CFG_2ANT, CFG_FDD, CFG_NORX, CFG_204B, (void*)&ucpJesdInitInstLte2Ant, (void*)&deviceInitInst_61_44M_4_9152G_FDD2ANT, (void*)&devicePostMcsInitInst_61_44M_4_9152G_FDD2ANT}, + {"61.44M/50M/4ANT/FDD/NORX/204B", CFG_SAMPLERATE_61_44MHZ, CFG_BW_50MHZ, CFG_4ANT, CFG_FDD, CFG_NORX, CFG_204B, (void*)&ucpJesdInitInstLte4Ant, (void*)&deviceInitInst_61_44M_4_9152G_FDD4ANT, (void*)&devicePostMcsInitInst_61_44M_4_9152G_FDD4ANT}, + {"122.88M/100M/4ANT/TDD/NORX/204C", CFG_SAMPLERATE_122_88MHZ, CFG_BW_100MHZ, CFG_4ANT, CFG_TDD, CFG_NORX, CFG_204C, (void*)&ucpJesdInitInstNr204C, (void*)&deviceInitInst_122_88M_8_11008G, (void*)&devicePostMcsInitInst_122_88M_8_11008G}, + {"122.88M/240M/4ANT/TDD/NORX/204B", CFG_SAMPLERATE_122_88MHZ, CFG_BW_240MHZ, CFG_4ANT, CFG_TDD, CFG_NORX, CFG_204B, (void*)&ucpJesdInitInstNr_bandwidth200M, (void*)&deviceInitInst_240M, (void*)&devicePostMcsInitInst_240M}, +}; + +static uint8_t gBoardType = HW_UNKNOW; +static uint16_t gConfigIndex = 0; +static uint8_t evmtGpio[][2] = +{ +/* PD11/AP_GPIOB24 "9025reset" */ {GPIO_PORT0B, 24}, +/* PA6/AP_GPIOA6 "9025cs" */ {GPIO_PORT0A, 6}, + +/* PD13/AP_GPIOB26 "9528reset" */ {GPIO_PORT0B, 26}, +/* PD6/AP_GPIOB19 "9528cs" */ {GPIO_PORT0B, 19}, +/* PD4/AP_GPIOB17 "sysref" */ {GPIO_PORT0B, 17}, +/* LVDS_RF_D15_P/CP_GPIOB27 "9528status0" */ {GPIO_PORT1B, 27}, +/* LVDS_RF_D15_N/CP_GPIOB26 "9528status1" */ {GPIO_PORT1B, 26}, + +/* LVDS_RF_RXFRM_P/CP_GPIOB01 "orx0ctrl" */ {GPIO_PORT1B, 1}, +/* LVDS_RF_RXFRM_N/CP_GPIOB00 "orx1ctrl" */ {GPIO_PORT1B, 0}, +/* LVDS_RF_TXFRM_N/CP_GPIOB02 "switchcal" */ {GPIO_PORT1B, 2}, +/* LVDS_RF_TXFRM_P/CP_GPIOB03 "lnavpd" */ {GPIO_PORT1B, 3} +}; + +static uint8_t evmfGpio[][2] = +{ +/* PB11/AP_GPIOB24 "9026reset" */ {GPIO_PORT0B, 24}, +/* PA6/AP_GPIOA6 "9026cs" */ {GPIO_PORT0A, 6}, + +/* LVDS_RF_D03_P/CP_GPIOB11 "9528reset" */ {GPIO_PORT1B, 11}, +/* PD6/AP_GPIOB19 "9528cs" */ {GPIO_PORT0B, 19}, +/* PD4/AP_GPIOB17 "sysref" */ {GPIO_PORT0B, 17}, +/* LVDS_RF_D15_P/CP_GPIOB27 "9528status0" */ {GPIO_PORT1B, 27}, +/* LVDS_RF_D15_N/CP_GPIOB26 "9528status1" */ {GPIO_PORT1B, 26} +}; + +static uint8_t evbGpio[][2] = +{ +/* LVDS_RF_D02_P/CP_GPIOB9 "9026reset" */ {GPIO_PORT1B, 9}, +/* PA6/AP_GPIOA6 "9026cs" */ {GPIO_PORT0A, 6}, + +/* LVDS_RF_D03_P/CP_GPIOB11 "9528reset" */ {GPIO_PORT1B, 11}, +/* PD6/AP_GPIOB19 "9528cs" */ {GPIO_PORT0B, 19}, +/* LVDS_RF_D03_N/CP_GPIOB10 "sysref" */ {GPIO_PORT1B, 10}, +/* LVDS_RF_D15_P/CP_GPIOB27 "9528status0" */ {GPIO_PORT1B, 27}, +/* LVDS_RF_D15_N/CP_GPIOB26 "9528status1" */ {GPIO_PORT1B, 26} +}; + +static uint8_t evmyGpio[][2] = +{ +/* PD20/CP_GPIOA1 "9026reset" */ {GPIO_PORT1A, 1}, +/* PA2/AP_GPIOA2 "9026cs" */ {GPIO_PORT0A, 2}, + +/* PD4/AP_GPIOB17 "9528reset" */ {GPIO_PORT0B, 17}, +/* PA6/AP_GPIOA6 "9528cs" */ {GPIO_PORT0A, 6}, +/* PD21/CP_GPIOA2 "sysref" */ {GPIO_PORT1A, 2}, +/* LVDS_RF_D15_P/CP_GPIOB27 "9528status0"*/ {GPIO_PORT1B, 27}, +/* LVDS_RF_D15_N/CP_GPIOB26 "9528status1"*/ {GPIO_PORT1B, 26}, + +/* LVDS_RF_RXFRM_P/CP_GPIOB01 "orx0ctrl" */ {GPIO_PORT1B, 29}, +/* LVDS_RF_RXFRM_N/CP_GPIOB00 "orx1ctrl" */ {GPIO_PORT1B, 30}, +/* LVDS_RF_D03_P/CP_GPIOB11 "switchcal" */ {GPIO_PORT1B, 11}, +/* LVDS_RF_TXFRM_P/CP_GPIOB03 "lnavpd" */ {GPIO_PORT1B, 9}, + +/* PA0/AP_GPIOA0 "spi1sel" */ {GPIO_PORT0A, 0}, +/* PA1/AP_GPIOA1 "spi3sel" */ {GPIO_PORT0A, 1}, +/* PD13/AP_GPIOB26 "pllsel" */ {GPIO_PORT0B, 26} +}; + +static void ucp_rfic_SaveBoardInfo (ucp_jesd_TrxGpioCfg_t *trxGpio) +{ + uint8_t i; + + gBoardType = 0; + for (i = 0; i < MAX_BOARD;i++) + { + if (!strncmp(trxGpio->board, (const char*)boardTypeString[i], 16)) + { + gBoardType = i; + break; + } + } + + printf("BOARD: %s\n", boardTypeString[gBoardType]); +} + +static int32_t ucp_rfic_pickCofigIndex (uint64_t sampleRate, + uint64_t bw, + uint16_t antNumb, + uint16_t enFdd, + uint16_t enOrx, + uint16_t en204C) +{ + + uint16_t maxIndex, i; + + maxIndex = sizeof(gRficConfigList)/sizeof(tRficConfigList_t); + printf("TotalCofig: %d\n", maxIndex); + + for (i = 0;i < maxIndex; i++) + { + if ((gRficConfigList[i].sampleRate == sampleRate) \ + && (gRficConfigList[i].bw == bw) \ + && (gRficConfigList[i].antNumb == antNumb) \ + && (gRficConfigList[i].enFdd == enFdd) \ + && (gRficConfigList[i].enOrx == enOrx) \ + && (gRficConfigList[i].en204C == en204C)) + { + printf("Configture: %s\n", gRficConfigList[i].item); + gConfigIndex = i; + return gConfigIndex; + } + } + + printf("\nError: Can't find configture: (sampleRate)%.5fM / (bw)%.5fM / (antNumb)%d / (enFdd)%d / (enOrx)%d / (en204C)%d\n\n", \ + sampleRate*1.0/1e6, bw*1.0/1e6, antNumb, enFdd, enOrx, en204C); + printf("Please change to:\n\n"); + printf(" sampleRate/bw/antNumb/enFdd/enOrx/en204C\n\n"); + for (i = 0;i < maxIndex; i++) + { + printf(" %s\n", gRficConfigList[i].item); + } + + printf("\n"); + + printf("NOTE:\n\nsampleRate keyValue:\n"); + printf(" CFG_SAMPLERATE_61_44MHZ: 61440000\n"); + printf(" CFG_SAMPLERATE_122_88MHZ: 122880000\n"); + printf(" CFG_SAMPLERATE_245_76MHZ: 245760000\n\n"); + + printf("bw keyValue:\n"); + printf(" CFG_BW_20MHZ: 20000000\n"); + printf(" CFG_BW_50MHZ: 50000000\n"); + printf(" CFG_BW_100MHZ: 100000000\n"); + printf(" CFG_BW_200MHZ: 200000000\n"); + printf(" CFG_BW_240MHZ: 240000000\n\n"); + + printf("antNumb keyValue:\n"); + printf(" CFG_1ANT: 1\n"); + printf(" CFG_2ANT: 2\n"); + printf(" CFG_3ANT: 3\n"); + printf(" CFG_4ANT: 4\n"); + printf(" CFG_5ANT: 5\n"); + printf(" CFG_6ANT: 6\n"); + printf(" CFG_7ANT: 7\n"); + printf(" CFG_8ANT: 8\n\n"); + + printf("enFdd keyValue:\n"); + printf(" CFG_TDD: 0\n"); + printf(" CFG_FDD: 1\n\n"); + + printf("enOrx keyValue:\n"); + printf(" CFG_NORX: 0\n"); + printf(" CFG_TLO_ORX: 1\n"); + printf(" CFG_ALO_ORX: 2\n"); + printf(" CFG_RLO_ORX: 3\n\n"); + + printf("en204C keyValue:\n"); + printf(" CFG_204B: 0\n"); + printf(" CFG_204C: 1\n\n"); + + printf("enUcpLog keyValue:\n"); + printf(" CFG_NONE_LOG: 0\n"); + printf(" CFG_LOG: 1\n\n"); + + printf("\n"); + exit(1); + + return -1; + +} + +static void ucp_rfic_GpioInit(void) +{ + uint8_t (*pGpio)[2], boardType; + + boardType = UCP_API_RFIC_GetBoardInfo(); + switch (boardType) + { + case HW_EVMT: + pGpio = evmtGpio; + break; + + case HW_EVMF: + pGpio = evmfGpio; + break; + + case HW_EVMY: + pGpio = evmyGpio; + break; + + case HW_EVB: + pGpio = evbGpio; + break; + + default: + printf("error, unknow board. @%s, %d\n", __FILE__, __LINE__); + exit(1); + break; + } + + + // config adrv9025 + ucp_jesd_gpioConfig(GPIO_INDEX_9025RESET, GPIO_DIR_OUT, UCP_JESD_TRX_GPIO_VALID_HIGH, UCP_GPIO(pGpio[0][0], pGpio[0][1])); + ucp_jesd_gpioConfig(GPIO_INDEX_9025CS, GPIO_DIR_OUT, UCP_JESD_TRX_GPIO_VALID_HIGH, UCP_GPIO(pGpio[1][0], pGpio[1][1])); + + // config ad9528 + ucp_jesd_gpioConfig(GPIO_INDEX_9528RESET, GPIO_DIR_OUT, UCP_JESD_TRX_GPIO_VALID_HIGH, UCP_GPIO(pGpio[2][0], pGpio[2][1])); + ucp_jesd_gpioConfig(GPIO_INDEX_9528CS, GPIO_DIR_OUT, UCP_JESD_TRX_GPIO_VALID_HIGH, UCP_GPIO(pGpio[3][0], pGpio[3][1])); + ucp_jesd_gpioConfig(GPIO_INDEX_SYSREF, GPIO_DIR_OUT, UCP_JESD_TRX_GPIO_VALID_HIGH, UCP_GPIO(pGpio[4][0], pGpio[4][1])); + ucp_jesd_gpioConfig(GPIO_INDEX_9528STATUS0, GPIO_DIR_IN, UCP_JESD_TRX_GPIO_VALID_LOW, UCP_GPIO(pGpio[5][0], pGpio[5][1])); + ucp_jesd_gpioConfig(GPIO_INDEX_9528STATUS1, GPIO_DIR_IN, UCP_JESD_TRX_GPIO_VALID_LOW, UCP_GPIO(pGpio[6][0], pGpio[6][1])); + + if ((HW_EVMT == boardType) || (HW_EVMY == boardType)) + { + ucp_jesd_gpioConfig(GPIO_INDEX_ORX0CTRL, GPIO_DIR_OUT, UCP_JESD_TRX_GPIO_VALID_HIGH, UCP_GPIO(pGpio[7][0], pGpio[7][1])); + ucp_jesd_gpioConfig(GPIO_INDEX_ORX1CTRL, GPIO_DIR_OUT, UCP_JESD_TRX_GPIO_VALID_HIGH, UCP_GPIO(pGpio[8][0], pGpio[8][1])); + ucp_jesd_gpioConfig(GPIO_INDEX_SWCAL, GPIO_DIR_OUT, UCP_JESD_TRX_GPIO_VALID_LOW, UCP_GPIO(pGpio[9][0], pGpio[9][1])); + ucp_jesd_gpioConfig(GPIO_INDEX_LNAVPD, GPIO_DIR_OUT, UCP_JESD_TRX_GPIO_VALID_HIGH, UCP_GPIO(pGpio[10][0], pGpio[10][1])); + } + + if (HW_EVMY == boardType) + { + ucp_jesd_gpioConfig(GPIO_INDEX_SPI1_SEL, GPIO_DIR_OUT, UCP_JESD_TRX_GPIO_VALID_LOW, UCP_GPIO(pGpio[11][0], pGpio[11][1])); + ucp_jesd_gpioConfig(GPIO_INDEX_SPI3_SEL, GPIO_DIR_OUT, UCP_JESD_TRX_GPIO_VALID_LOW, UCP_GPIO(pGpio[12][0], pGpio[12][1])); + ucp_jesd_gpioConfig(GPIO_INDEX_PLL_SEL, GPIO_DIR_OUT, UCP_JESD_TRX_GPIO_VALID_LOW, UCP_GPIO(pGpio[13][0], pGpio[13][1])); + //*---------------------------------------------------------------- + // (boardType == HW_EVMY) // ioremap can't contorl AP_GPIOB26 (GPIO_INDEX_PLL_SEL) + { + #include + #include + + static int export_fd, dir_fd, value_fd; + + export_fd = open("/sys/class/gpio/export", O_WRONLY); + char export_buf[32] = { 0 }; + int len = sprintf(export_buf, "%d", 474); + if (export_fd > 0) { + write(export_fd, export_buf, len); + } + + dir_fd = open("/sys/class/gpio/gpio474/direction" , O_RDWR); + value_fd = open("/sys/class/gpio/gpio474/value", O_RDWR); + + write(dir_fd , "/sys/class/gpio/gpio474/direction", 4); + write(value_fd , "0", 1); + + close(export_fd); + close(dir_fd); + close(value_fd); + } + } + //----------------------------------------------------------------*/ +} + +int32_t UCP_API_RFIC_CellInit(uint64_t sampleRate, + uint64_t bw, + uint16_t antNumb, + uint16_t enFdd, + uint16_t enOrx, + uint16_t en204C, + uint16_t enUcpLog) +{ + ucp_jesd_TrxGpioCfg_t *pTrxGpio; + + UCP_API_JESD_ApeWorkStep(UCP_JESD_APE_POWERONRESET); + UCP_API_JESD_Version(); + UCP_API_JESD_TrxGpioSetup((const char *)UCP_TXR_CONFIG_FILE, enUcpLog); + + pTrxGpio = UCP_API_JESD_TrxGpioGet(); + ucp_rfic_SaveBoardInfo(pTrxGpio); + ucp_rfic_GpioInit(); + ucp_rfic_pickCofigIndex(sampleRate, bw, antNumb, enFdd, enOrx, en204C); + + UCP_API_CLOCKGEN_Init(); + UCP_API_JESD_Init((ucp_jesd_Init_t*)gRficConfigList[gConfigIndex].ucpInitStru); + UCP_API_JESD_ApeWorkStep(UCP_JESD_APE_CLOCKGENRUN); + + return 0; +} + +int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint16_t initAtt, + uint16_t initGain, uint64_t auxLo, uint16_t enOrx, + ucp_rfic_calPara_t calPara) +{ + UCP_API_TRANSCEIVER_Init((void*)gRficConfigList[gConfigIndex].adiInitStru, + (void*)gRficConfigList[gConfigIndex].adiPostMcsStru, + txLo, rxLo, initAtt, initGain, auxLo, enOrx, calPara); + UCP_API_JESD_ApeWorkStep(UCP_JESD_APE_CELLRUN); + + return 0; +} + +int32_t UCP_API_RFIC_CellDelete(void) +{ + UCP_API_JESD_ApeWorkStep(UCP_JESD_APE_POWERONRESET); + UCP_API_JESD_CellDelete(); + UCP_API_CLOCKGEN_Reset(); + UCP_API_TRANSCEIVER_Reset(); + + return 0; +} + +uint8_t UCP_API_RFIC_GetBoardInfo (void) +{ + return gBoardType; +} + diff --git a/driver/rfic/rf/api/src/ucp_api_transceiver.c b/driver/rfic/rf/api/src/ucp_api_transceiver.c new file mode 100644 index 0000000..e669d26 --- /dev/null +++ b/driver/rfic/rf/api/src/ucp_api_transceiver.c @@ -0,0 +1,58 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_api_transceiver.c +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-03-04 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#include +#include +#include "adi_ad9528Lib.h" +#include "adi_adrv9025Lib.h" + +int32_t UCP_API_TRANSCEIVER_Reset(void) +{ + ucp_api_adrv9025_Reset(); + return 0; +} + +int32_t UCP_API_TRANSCEIVER_Init(void *adiInit, void *adiPostMcsStru, uint64_t txLo, uint64_t rxLo, uint16_t initAtt, + uint16_t initGain, uint64_t auxLo, uint16_t enOrx, + ucp_rfic_calPara_t calPara) +{ + adrv9025_setup_platform(adiInit, adiPostMcsStru); + adrv9025_init(txLo, rxLo, initAtt, initGain, auxLo, enOrx, calPara); + + return 0; +} + +int32_t UCP_API_TRANSCEIVER_MGC_Cfg(uint8_t en) +{ + return ad9025_MGC_Cfg(en); +} + +int32_t UCP_API_TRANSCEIVER_Gain_Set(double gain_db) +{ + return ad9025_Gain_Set(gain_db); +} + +double UCP_API_TRANSCEIVER_Gain_Get(void) +{ + return ad9025_Gain_Get(); +} + +int32_t UCP_API_TRANSCEIVER_Att_Set(uint8_t att_db) +{ + return ad9025_Att_Set(att_db); +} + +uint8_t UCP_API_TRANSCEIVER_Att_Get(void) +{ + return ad9025_Att_Get(); +} + diff --git a/driver/rfic/rf/api/src/ucp_api_transceiver.h b/driver/rfic/rf/api/src/ucp_api_transceiver.h new file mode 100644 index 0000000..3d735bb --- /dev/null +++ b/driver/rfic/rf/api/src/ucp_api_transceiver.h @@ -0,0 +1,38 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_api_transceiver.h +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-03-04 17:39:00 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef UCP_API_TRANSCEIVER_H_ +#define UCP_API_TRANSCEIVER_H_ + +#include +#include +#include "ucp_api_rfic.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern int32_t UCP_API_TRANSCEIVER_Reset(void); +extern int32_t UCP_API_TRANSCEIVER_Init(void *adiInit, void *adiPostMcsStru, uint64_t txLo, uint64_t rxLo, uint16_t initAtt, + uint16_t initGain, uint64_t auxLo, uint16_t enOrx, + ucp_rfic_calPara_t calPara); +extern int32_t UCP_API_TRANSCEIVER_MGC_Cfg(uint8_t en); +extern int32_t UCP_API_TRANSCEIVER_Gain_Set(double gain_db); +extern double UCP_API_TRANSCEIVER_Gain_Get(void); +extern int32_t UCP_API_TRANSCEIVER_Att_Set(uint8_t att_db); +extern uint8_t UCP_API_TRANSCEIVER_Att_Get(void); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef UCP_API_TRANSCEIVER_H_ */ diff --git a/driver/rfic/rf/api/src/ucp_jesd_initdata.c b/driver/rfic/rf/api/src/ucp_jesd_initdata.c new file mode 100644 index 0000000..4359c17 --- /dev/null +++ b/driver/rfic/rf/api/src/ucp_jesd_initdata.c @@ -0,0 +1,347 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_jesd_initdata.c +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-07-11 18:21:00 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#include +#include +#include "ucp_api_jesd.h" + +ucp_jesd_Init_t ucpJesdInitInstNr = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 122880, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 122880, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 122880, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + +ucp_jesd_Init_t ucpJesdInitInstNr_bandwidth200M = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 245760, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 245760, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 245760, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + +ucp_jesd_Init_t ucpJesdInitInstLte2Ant = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 61440, // sampleClock_kHz; + 4, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 1, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 61440, // sampleClock_kHz; + 4, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 1, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 61440, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + +ucp_jesd_Init_t ucpJesdInitInstLte4Ant = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 61440, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 61440, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 61440, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + + +ucp_jesd_Init_t ucpJesdInitInstNr_orx = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 122880, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 122880, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 1, // enable + 245760, // sampleClock_kHz; + 2, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 4, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + +ucp_jesd_Init_t ucpJesdInitInstNrFdd2Ant = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 122880, // sampleClock_kHz; + 4, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 122880, // sampleClock_kHz; + 4, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 122880, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + +ucp_jesd_Init_t ucpJesdInitInstNr204C = +{ + { // common + 122880, // devClock_kHz; + 1, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 245760, // sampleClock_kHz; + 8, // jesd204M + 64, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 1, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 245760, // sampleClock_kHz; + 8, // jesd204M + 64, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 1, // jesd204E + 1, // scramble + 15, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 245760, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + + diff --git a/driver/rfic/rf/demo/rfic.c b/driver/rfic/rf/demo/rfic.c new file mode 100644 index 0000000..e68b15d --- /dev/null +++ b/driver/rfic/rf/demo/rfic.c @@ -0,0 +1,71 @@ +#include +#include +#include +#include +#include +#include + +#include "../ucp/inc/ucp_api_jesd.h" +#include "../api/inc/ucp_api_rfic.h" +#include "adi_adrv9025Lib.h" + +typedef struct ucp_rfic_cfg +{ + uint64_t txLo; + uint64_t rxLo; + uint64_t auxLo; + uint16_t initAtt; + uint16_t initGain; + + uint64_t sampleRate; + uint64_t bw; + uint16_t antNumb; + uint16_t enFdd; + uint16_t enOrx; + uint16_t en204C; + uint16_t enUcpLog; + + int16_t calOrxGainIndex; + int16_t calChAttPara[4]; + + uint16_t padding; +} ucp_rfic_cfg_t; + +extern ucp_rfic_cfg_t ucp_GetRficCfgInfo(void); + +int32_t main(int32_t argc, char* argv[]) +{ + ucp_rfic_cfg_t rficConfig; + ucp_rfic_calPara_t calPara; + + rficConfig = ucp_GetRficCfgInfo(); + calPara.calOrxGainIndex = rficConfig.calOrxGainIndex; + calPara.calChAttPara[0] = rficConfig.calChAttPara[0]; + calPara.calChAttPara[1] = rficConfig.calChAttPara[1]; + calPara.calChAttPara[2] = rficConfig.calChAttPara[2]; + calPara.calChAttPara[3] = rficConfig.calChAttPara[3]; + + UCP_API_RFIC_CellInit(rficConfig.sampleRate, rficConfig.bw, rficConfig.antNumb, rficConfig.enFdd, rficConfig.enOrx, rficConfig.en204C, rficConfig.enUcpLog); + UCP_API_RFIC_CellSetup(rficConfig.txLo, rficConfig.rxLo, rficConfig.initAtt, rficConfig.initGain, rficConfig.auxLo, rficConfig.enOrx, calPara); + + if (argc < 2) + { + return 0; + } + + if (!strcmp("tone", argv[1])) + { + UCP_API_GPIO_Tx(); + adrv9025_tone(1); + } + + if (!strcmp("rssi", argv[1])) + { + UCP_API_GPIO_Rx(); + ad9025_rssi(); + } + + return 1; +} + + diff --git a/driver/rfic/rf/demo/rfic.o b/driver/rfic/rf/demo/rfic.o new file mode 100644 index 0000000..32f7c53 Binary files /dev/null and b/driver/rfic/rf/demo/rfic.o differ diff --git a/driver/rfic/rf/makefile b/driver/rfic/rf/makefile new file mode 100644 index 0000000..9e4e965 --- /dev/null +++ b/driver/rfic/rf/makefile @@ -0,0 +1,164 @@ +#example source paths +API_PATH = api +ADI_PATH = adrv9025 +UCP4008_PATH = ucp + +#Include paths +UCP4008_INCL = $(UCP4008_PATH)/inc +ADI_APP_INCL = $(ADI_PATH)/c_src/app/example +ADI_ADRV9025_INCL = $(ADI_PATH)/c_src/devices/adrv9025/public/include +ADI_AD9528_INCL = $(ADI_PATH)/c_src/devices/ad9528/public/include +ADI_COMMON_INCL = $(ADI_PATH)/c_src/common +ADI_COMMON_ERROR_INCL = $(ADI_PATH)/c_src/common/adi_error +ADI_COMMON_LOGGING_INCL = $(ADI_PATH)/c_src/common/adi_logging +ADI_COMMON_HAL_INCL = $(ADI_PATH)/c_src/common/adi_hal +ADI_PLATFORM_INCL = $(ADI_PATH)/c_src/platforms +ADI_PLATFORM_UTILS_INCL = $(ADI_PATH)/c_src/platforms/platform_utils + +#src paths +UCP4008_SRC = $(UCP4008_PATH)/ +API_SRC = $(API_PATH) +ADI_APP_SRC = $(ADI_PATH)/c_src/app/ +ADI_PLATFORM_SRC = $(ADI_PATH)/c_src/platforms +ADI_UCP2PLATFORM_SRC = $(ADI_PATH)/c_src/platforms/ucp2/ +ADI_COMMON_SRC = $(ADI_PATH)/c_src/common +ADI_COMMON_ERROR_SRC = $(ADI_PATH)/c_src/common/adi_error +ADI_COMMON_LOGGING_SRC = $(ADI_PATH)/c_src/common/adi_logging +ADI_COMMON_HAL_SRC = $(ADI_PATH)/c_src/common/adi_hal +ADI_AD9528_SRC = $(ADI_PATH)/c_src/devices/ad9528 +ADI_ADRV9025_SRC = $(ADI_PATH)/c_src/devices/adrv9025 + +#LIBs to link +LIB_UCP4008 = $(UCP4008_PATH)/libjesd.a +LIB_API = $(API_PATH)/libapi.a +LIB_ADI_APP = $(ADI_PATH)/c_src/app/libadi_app.a +LIB_ADI_ADRV9025_DEVICE = $(ADI_PATH)/c_src/devices/adrv9025/libadi_adrv9025.a +LIB_ADI_COMMON_DEVICE = $(ADI_PATH)/c_src/common/libadi_common.a +LIB_ADI_PLATFORM = $(ADI_PATH)/c_src/platforms/libadi_platform.a +LIB_ADI_UCP2PLATFORM = $(ADI_PATH)/c_src/platforms/ucp2/libadi_ucp2platform.a +LIB_ADI_AD9528 = $(ADI_PATH)/c_src/devices/ad9528/libadi_ad9528.a + +arch = arm64 +CROSS_CC ?= aarch64-linux-gnu- + +ifeq ($(arch),x86) + CC = gcc + LD = gcc +else + CC = $(CROSS_CC)gcc + LD = $(CROSS_CC)gcc +endif + +ARFLAGS = -rv +CFLAGS = -Wall -Wchar-subscripts -Wshadow -DDEBUG=1 -DGTEST=1 \ + -I$(UCP4008_INCL) \ + -I$(JSON_INCL) \ + -I$(API_INCL) \ + -I$(ADI_APP_INCL) \ + -I$(ADI_ADRV9025_INCL) \ + -I$(ADI_AD9528_INCL) \ + -I$(ADI_COMMON_INCL) \ + -I$(ADI_COMMON_ERROR_INCL) \ + -I$(ADI_COMMON_LOGGING_INCL) \ + -I$(ADI_COMMON_HAL_INCL) \ + -I$(ADI_PLATFORM_INCL) \ + -I$(ADI_PLATFORM_UTILS_INCL) \ + -Werror + +TARGET = rfic.out +TARGET_LIB = librfic.a + +SRC_RFIC = $(wildcard ./demo/rfic.c) +OBJS_RFIC = $(SRC_RFIC:.c=.o) + +#All DEPS are built by adi_adrv9025_board_lib +DEPS = $(LIB_UCP4008) \ + $(LIB_API) \ + $(LIB_ADI_APP) \ + $(LIB_ADI_ADRV9025_DEVICE) \ + $(LIB_ADI_COMMON_DEVICE) \ + $(LIB_ADI_PLATFORM) \ + $(LIB_ADI_UCP2PLATFORM) \ + $(LIB_ADI_AD9528) + +all: lib $(TARGET) + +.c.o: + $(CC) $(CFLAGS) -o $@ -c $< + +lib: $(TARGET_LIB) + +$(TARGET): $(OBJS_RFIC) $(OBJS_JESD) + $(LD) -o $@ $(OBJS_RFIC) $(TARGET_LIB) -lm + mkdir -p ./out/jesd + cp ./ucp/libjesd.a ./out/jesd/ + cp ./ucp/inc/ucp_api_jesd.h ./out/jesd/ + cp ./api/src/ucp_jesd_initdata.c ./out/jesd/ + mkdir -p ./out/rfic + mv librfic.a ./out/rfic/ + cp ./api/inc/ucp_api_rfic.h ./out/rfic/ + cp ./api/src/ucp_jesd_initdata.c ./out/rfic/ + mkdir -p ./out/app + mv rfic.out ./out/app + +$(TARGET_LIB): adi_lib api_lib + mkdir -p ./out/obj + ar x $(LIB_UCP4008) + ar x $(LIB_API) + ar x $(LIB_ADI_APP) + ar x $(LIB_ADI_ADRV9025_DEVICE) + ar x $(LIB_ADI_COMMON_DEVICE) + ar x $(LIB_ADI_PLATFORM) + ar x $(LIB_ADI_UCP2PLATFORM) + ar x $(LIB_ADI_AD9528) + mv *.o ./out/obj + ar -rv $@ ./out/obj/*.o + rm -rf demo/*.o + $(MAKE) -C $(API_SRC) clean + $(MAKE) -C $(ADI_APP_SRC) clean + $(MAKE) -C $(ADI_PLATFORM_SRC) clean + $(MAKE) -C $(ADI_UCP2PLATFORM_SRC) clean + $(MAKE) -C $(ADI_COMMON_SRC) clean + $(MAKE) -C $(ADI_AD9528_SRC) clean + $(MAKE) -C $(ADI_ADRV9025_SRC) clean + +adi_lib: adi_app_lib \ + adi_platform_lib \ + adi_common_lib \ + adi_ad9528_lib \ + adi_adrv9025_lib + +api_lib: + $(MAKE) -C $(API_SRC) CC=$(CC) + +adi_app_lib: + $(MAKE) -C $(ADI_APP_SRC) CC=$(CC) + +adi_platform_lib: + $(MAKE) -C $(ADI_PLATFORM_SRC) CC=$(CC) + +adi_common_lib: + $(MAKE) -C $(ADI_COMMON_SRC) CC=$(CC) + +adi_ad9528_lib: + $(MAKE) -C $(ADI_AD9528_SRC) CC=$(CC) + +adi_adrv9025_lib: + $(MAKE) -C $(ADI_ADRV9025_SRC) CC=$(CC) + +clean: + $(MAKE) -C $(API_SRC) clean + $(MAKE) -C $(ADI_PLATFORM_SRC) clean + $(MAKE) -C $(ADI_UCP2PLATFORM_SRC) clean + $(MAKE) -C $(ADI_COMMON_SRC) clean + $(MAKE) -C $(ADI_AD9528_SRC) clean + $(MAKE) -C $(ADI_ADRV9025_SRC) clean + rm -rf demo/*.o + rm -rf ./out + rm -rf ./api/*.a + +clr: + $(MAKE) clean + rm -rf ./out + + \ No newline at end of file diff --git a/driver/rfic/rf/out/app/rfic.out b/driver/rfic/rf/out/app/rfic.out new file mode 100644 index 0000000..034ed36 Binary files /dev/null and b/driver/rfic/rf/out/app/rfic.out differ diff --git a/driver/rfic/rf/out/jesd/libjesd.a b/driver/rfic/rf/out/jesd/libjesd.a new file mode 100644 index 0000000..34304f0 Binary files /dev/null and b/driver/rfic/rf/out/jesd/libjesd.a differ diff --git a/driver/rfic/rf/out/jesd/ucp_api_jesd.h b/driver/rfic/rf/out/jesd/ucp_api_jesd.h new file mode 100644 index 0000000..4b9b503 --- /dev/null +++ b/driver/rfic/rf/out/jesd/ucp_api_jesd.h @@ -0,0 +1,293 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_api_jesd.h +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-03-04 14:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef UCP_API_JESD_H_ +#define UCP_API_JESD_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief the max channels of trx + */ +#define MAX_UCP_JESD_TRX_CH (4) + +/** + * \brief Data structure to hold UCP API State + */ +typedef enum ucp_jesd_States +{ + UCP_JESD_STATE_POWERONRESET = 0x00, + UCP_JESD_STATE_JSCTRLOK = 0x01, + UCP_JESD_STATE_CRGOK = 0x02, + UCP_JESD_STATE_SUBCTRLOK = 0x04, + UCP_JESD_STATE_204COREOK = 0x08, + UCP_JESD_STATE_PMAOK = 0x10, + UCP_JESD_STATE_TIMEROK = 0x20, + UCP_JESD_STATE_RUN = 0x40 +} ucp_jesd_States_e; + +/** + * \brief Data structure to ape working step + */ +typedef enum ucp_jesd_ApeWorkStep +{ + UCP_JESD_APE_POWERONRESET = 0x00, + UCP_JESD_APE_CLOCKGENRUN = 0x01, + UCP_JESD_APE_CELLRUN = 0x02, +} ucp_jesd_ApeWorkStep_e; + +/** + * \brief Data structure to the level status of trx's control pins. + */ +typedef enum ucp_jesd_gpioEnableLevel +{ + UCP_JESD_TRX_GPIO_DISABLE = 0x00, + UCP_JESD_TRX_GPIO_VALID_HIGH = 0x01, + UCP_JESD_TRX_GPIO_VALID_LOW = 0x02, +} ucp_jesd_gpioEnableLevel_e; + +/** + * \brief Index of trx's control pins. + */ +enum { + GPIO_TRX_TX1 = 0, + GPIO_TRX_TX2, + GPIO_TRX_TX3, + GPIO_TRX_TX4, + GPIO_RF_TX1, + GPIO_RF_TX2, + GPIO_RF_TX3, + GPIO_RF_TX4, + GPIO_SW_TX1, + GPIO_SW_TX2, + GPIO_SW_TX3, + GPIO_SW_TX4, + + GPIO_TRX_RX1, + GPIO_TRX_RX2, + GPIO_TRX_RX3, + GPIO_TRX_RX4, + GPIO_RF_RX1, + GPIO_RF_RX2, + GPIO_RF_RX3, + GPIO_RF_RX4, + GPIO_SW_RX1, + GPIO_SW_RX2, + GPIO_SW_RX3, + GPIO_SW_RX4, + + GPIO_TRX_ORX1, + GPIO_TRX_ORX2, + GPIO_TRX_ORX3, + GPIO_TRX_ORX4, + GPIO_RF_ORX1, + GPIO_RF_ORX2, + GPIO_RF_ORX3, + GPIO_RF_ORX4, + GPIO_SW_ORX1, + GPIO_SW_ORX2, + GPIO_SW_ORX3, + GPIO_SW_ORX4, + + GPIO_TRIGER, + + GPIO_TR_MAX = 40 +}; + +/** + * \brief Data structure to contrl pins of rf's trx + */ + typedef struct ucp_jesd_gpio { + uint8_t port; + uint8_t pin; + uint8_t enableLevel; +} ucp_jesd_gpio_t; + +typedef struct ucp_jesd_tr_gpio { + ucp_jesd_gpio_t trx; + ucp_jesd_gpio_t rf; + ucp_jesd_gpio_t sw; +} ucp_jesd_tr_gpio_t; + +typedef struct ucp_jesd_TrxGpio { + ucp_jesd_tr_gpio_t tx; + ucp_jesd_tr_gpio_t rx; + ucp_jesd_tr_gpio_t orx; +} ucp_jesd_TrxGpio_t; + +/** + * \brief Data structure to configure of trx's contrl pins + */ +typedef struct ucp_jesd_TrxGpioCfg { + char board[16]; + uint32_t version; + uint8_t maxCh; + uint8_t devClkSrc; + int32_t uldelay; + int32_t dldelay; + char lvdsCoupling[16]; + ucp_jesd_gpio_t triger; + ucp_jesd_TrxGpio_t ch[MAX_UCP_JESD_TRX_CH]; +} ucp_jesd_TrxGpioCfg_t; + +/** + * \brief Data structure to hold digital clock settings + */ +typedef struct ucp_jesd_CommonSettings +{ + uint32_t devClock_kHz; /*!< Device clock frequency in kHz */ + uint8_t enableJesd204C; /*!< 1= Enable JESD204C framer, 0 = use JESD204B framer */ + uint8_t jesdSubClass; +} ucp_jesd_CommonSettings_t; + +/** +* \brief Data structure to hold UCP JESD204b Framer configuration settings +*/ +typedef struct ucp_jesd_FrmCfg +{ + uint8_t enable; + uint32_t sampleClock_kHz; /*!< Sample clock frequency in kHz */ + uint8_t jesd204M; /*!< Number of ADCs (0, 2, or 4) where 2 ADCs are required per receive chain (I and Q). */ + uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K must be modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C). */ + uint8_t jesd204F; /*!< Number of bytes(octets) per frame (Valid 1, 2, 4, 8). */ + uint8_t jesd204Np; /*!< converter sample resolution (12, 16, 24). */ + uint8_t jesd204E; /*!< JESD204C E parameter */ + uint8_t scramble; /*!< Scrambling off if framerScramble = 0, if framerScramble > 0 scrambling is enabled */ + uint8_t serializerLanesEnabled; /*!< Serializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ + uint8_t syncbInSelect; /*!< Selects SYNCb input source. Where, 0 = use SYNCBIN0 for this framer, 1 = use SYNCBIN1 for this framer, 2 = use SYNCBIN2 */ + +} ucp_jesd_FrmCfg_t; + +/** +* \brief Data structure to hold the settings for the deframer configuration +*/ +typedef struct ucp_jesd_DfrmCfg +{ + uint8_t enable; + uint32_t sampleClock_kHz; /*!< Sample clock frequency in kHz */ + uint8_t jesd204M; /*!< Number of DACs (0, 2, or 4) - 2 DACs per transmit chain (I and Q) */ + uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K = modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C) */ + uint8_t jesd204F; /*!< Number of bytes(octets) per frame . */ + uint8_t jesd204Np; /*!< converter sample resolution (12, 16) */ + uint8_t jesd204E; /*!< JESD204C E parameter */ + uint8_t scramble; /*!< Scrambling off if scramble = 0, if framerScramble > 0 scrambling is enabled */ + uint8_t deserializerLanesEnabled; /*!< Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ + uint8_t syncbOutSelect; /*!< Selects deframer SYNCBOUT pin (0 = SYNCBOUT0, 1 = SYNCBOUT1, 2 = output SYNCB to SYNCBOUT0 and SYNCBOUT1) */ +} ucp_jesd_DfrmCfg_t; + +/** +* \brief Data structure to hold ucp JESD Framer and Deframer configuration information +*/ +typedef struct ucp_jesd_Init +{ + ucp_jesd_CommonSettings_t common; /*!< Holds settings for CLKPLL and reference clock */ + ucp_jesd_FrmCfg_t framer; /*!< Framer 0 configuration data structures */ + ucp_jesd_DfrmCfg_t deframer[2]; /*!< Deframer 0/1 configuration data structures */ +} ucp_jesd_Init_t; + +/** +* \brief get jesd module's version +* +* \param void +* +* \retval version. +*/ +extern uint32_t UCP_API_JESD_Version(void); + +/** +* \brief Sets up the ape work step +* +* \param step +* UCP_JESD_APE_POWERONRESET: when jesd reset or power up, set this value +* UCP_JESD_APE_CLOCKGENRUN: when clock gen chip sets up, set this value +* UCP_JESD_APE_CELLRUN: when cell and trx set up, set this value +* +* \retval none. +*/ +extern void UCP_API_JESD_ApeWorkStep(ucp_jesd_ApeWorkStep_e step); + +/** +* \brief Sets up the gpios of tx and rx +* +* \param setting +* +* \retval none. +*/ +extern void UCP_API_JESD_TrxGpioSetup (const char *trxGpioConfigFile, uint16_t enLog); + +/** +* \brief Gets the gpio's inf of tx and rx +* +* \param void +* +* \retval TrxGpioCfg point. +*/ +extern ucp_jesd_TrxGpioCfg_t* UCP_API_JESD_TrxGpioGet (void); + + +/** +* \brief Sets up the ucp4008 jesd's para setting +* +* \param setting +* +* \retval none. +*/ +extern ucp_jesd_States_e UCP_API_JESD_Init (ucp_jesd_Init_t *setting); + +/** +* \brief Sets up the ucp4008 jesd's para setting +* +* \param setting +* +* \retval none. +*/ +extern ucp_jesd_States_e UCP_API_JESD_CellSetup (ucp_jesd_Init_t *setting); + +/** +* \brief Sets up the ucp4008 jesd's para setting +* +* \param setting +* +* \retval none. +*/ +extern void UCP_API_JESD_CellDelete (void); + +/** +* \brief gpio of rf controlling +* +* \param setting +* +* \retval none. +*/ +extern int ucp_jesd_gpioSet(const int pinIdex, int value); +extern int ucp_jesd_gpioGet(const int pinIdex); +extern void UCP_API_GPIO_Tx (void); +extern void UCP_API_GPIO_Rx (void); +extern void UCP_API_GPIO_On (void); +extern void UCP_API_GPIO_Off (void); +extern void UCP_API_GPIO_OrxOn (void); +extern void UCP_API_GPIO_OrxOff (void); +extern void UCP_API_GPIO_TrigOn (void); +extern void UCP_API_GPIO_TrigOff (void); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef UCP_API_JESD_H_ */ + diff --git a/driver/rfic/rf/out/jesd/ucp_jesd_initdata.c b/driver/rfic/rf/out/jesd/ucp_jesd_initdata.c new file mode 100644 index 0000000..4359c17 --- /dev/null +++ b/driver/rfic/rf/out/jesd/ucp_jesd_initdata.c @@ -0,0 +1,347 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_jesd_initdata.c +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-07-11 18:21:00 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#include +#include +#include "ucp_api_jesd.h" + +ucp_jesd_Init_t ucpJesdInitInstNr = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 122880, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 122880, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 122880, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + +ucp_jesd_Init_t ucpJesdInitInstNr_bandwidth200M = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 245760, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 245760, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 245760, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + +ucp_jesd_Init_t ucpJesdInitInstLte2Ant = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 61440, // sampleClock_kHz; + 4, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 1, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 61440, // sampleClock_kHz; + 4, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 1, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 61440, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + +ucp_jesd_Init_t ucpJesdInitInstLte4Ant = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 61440, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 61440, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 61440, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + + +ucp_jesd_Init_t ucpJesdInitInstNr_orx = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 122880, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 122880, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 1, // enable + 245760, // sampleClock_kHz; + 2, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 4, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + +ucp_jesd_Init_t ucpJesdInitInstNrFdd2Ant = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 122880, // sampleClock_kHz; + 4, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 122880, // sampleClock_kHz; + 4, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 122880, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + +ucp_jesd_Init_t ucpJesdInitInstNr204C = +{ + { // common + 122880, // devClock_kHz; + 1, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 245760, // sampleClock_kHz; + 8, // jesd204M + 64, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 1, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 245760, // sampleClock_kHz; + 8, // jesd204M + 64, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 1, // jesd204E + 1, // scramble + 15, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 245760, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + + diff --git a/driver/rfic/rf/out/obj/adi_ad9528.o b/driver/rfic/rf/out/obj/adi_ad9528.o new file mode 100644 index 0000000..0988914 Binary files /dev/null and b/driver/rfic/rf/out/obj/adi_ad9528.o differ diff --git a/driver/rfic/rf/out/obj/adi_ad9528Lib.o b/driver/rfic/rf/out/obj/adi_ad9528Lib.o new file mode 100644 index 0000000..d2c05e2 Binary files /dev/null and b/driver/rfic/rf/out/obj/adi_ad9528Lib.o differ diff --git a/driver/rfic/rf/out/obj/adi_ad9528_hal.o b/driver/rfic/rf/out/obj/adi_ad9528_hal.o new file mode 100644 index 0000000..4374296 Binary files /dev/null and b/driver/rfic/rf/out/obj/adi_ad9528_hal.o differ diff --git a/driver/rfic/rf/out/obj/adi_ad9528_utilities.o b/driver/rfic/rf/out/obj/adi_ad9528_utilities.o new file mode 100644 index 0000000..56515da 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files /dev/null and b/driver/rfic/rf/out/rfic/librfic.a differ diff --git a/driver/rfic/rf/out/rfic/ucp_api_rfic.h b/driver/rfic/rf/out/rfic/ucp_api_rfic.h new file mode 100644 index 0000000..5379255 --- /dev/null +++ b/driver/rfic/rf/out/rfic/ucp_api_rfic.h @@ -0,0 +1,267 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_api_rfic.h +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-03-04 17:39:00 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef UCP_API_RFIC_H_ +#define UCP_API_RFIC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief define board type + */ + enum { + HW_UNKNOW = 0, + HW_EVMT, + HW_EVMF, + HW_EVB, + HW_EVMY, + HW_OTHER = 254, + HW_MAX = 255 +}; + +/** + * \brief define some paras for cell init + */ +enum { + CFG_SAMPLERATE_61_44MHZ = 61440000, + CFG_SAMPLERATE_122_88MHZ = 122880000, + CFG_SAMPLERATE_245_76MHZ = 245760000 +}; + +enum { + CFG_BW_20MHZ = 20000000, + CFG_BW_50MHZ = 50000000, + CFG_BW_100MHZ = 100000000, + CFG_BW_200MHZ = 200000000, + CFG_BW_240MHZ = 240000000 +}; + +enum { + CFG_1ANT = 1, + CFG_2ANT = 2, + CFG_3ANT = 3, + CFG_4ANT = 4, + CFG_5ANT = 5, + CFG_6ANT = 6, + CFG_7ANT = 7, + CFG_8ANT = 8 +}; + +enum { + CFG_TDD = 0, + CFG_FDD = 1 +}; + +enum { + CFG_NORX = 0, + CFG_TLO_ORX = 1, + CFG_ALO_ORX = 2, + CFG_RLO_ORX = 3 +}; + +enum { + CFG_204B= 0, + CFG_204C = 1 +}; + +enum { + CFG_NONE_LOG = 0, + CFG_LOG = 1 +}; + +/** + * \brief define cal para struct + */ + +typedef struct ucp_rfic_calPara +{ + int16_t calOrxGainIndex; + int16_t calChAttPara[16]; +} ucp_rfic_calPara_t; + +//********************************************************************************** +// system option layer +/** +* \brief Sets up the cell's default config +* +* \param sampleRate is Transceiver's sample Rate (Unit hz. 122.88Mhz 245.76Mhz or 61.44Mhz). +* \param bw is bandwidth (Unit hz). +* \param antNumb is the number of antennas (range 1 ~ 8). +* \param enFdd (0: TDD mode, 1: FDD mode). +* \param enOrx (0: disable orx, 1: orx Lo follows Tx Lo, 2: orx Lo follows aux Lo). +* \param en204C(0: 204B mode, 1: 204C mode). +* \param enUcpLog(0: disable configture Log, 1: enable configture Log). +* +* \retval 0. +*/ +extern int32_t UCP_API_RFIC_CellInit(uint64_t sampleRate, + uint64_t bw, + uint16_t antNumb, + uint16_t enFdd, + uint16_t enOrx, + uint16_t en204C, + uint16_t enUcpLog); +/** +* \brief Sets up the transceiver's tx rx LO frenq, bandwidth, Initialize attenuation. +* then process Initialize transceiver +* +* \param txLo is Transmit local frequency (Unit hz). +* \param rxLo is Receive local frequency (Unit hz). +* \param initAtt is Initialize attenuation (Unit db, range 0 ~ 20). +* \param initGain is Initialize rx Gain index (Unit db, range 183 ~ 255). +* \param auxLo is orx local frequency (Unit hz). +* \param calPara is paras for RX QEC、TX att cal and so on +* \param enOrx (0: disable orx, 1: orx Lo follows Tx Lo, 2: orx Lo follows aux Lo). +* +* \retval 0. +*/ +extern int32_t UCP_API_RFIC_CellSetup(uint64_t txLo, uint64_t rxLo, uint16_t initAtt, + uint16_t initGain, uint64_t auxLo, uint16_t enOrx, + ucp_rfic_calPara_t calPara); + +/** +* \brief delete cell. +* +* \param void. +* +* \retval void. +*/ +extern int32_t UCP_API_RFIC_CellDelete(void); + +//********************************************************************************** +// chip option layer +// TRANSCEIVER +/** +* \brief transceiver chip hardware reset. +* +* \param void. +* +* \retval void. +*/ +extern int32_t UCP_API_TRANSCEIVER_Reset(void); + +/** +* \brief Sets up the transceiver's MGC Mod. +* +* \param en, if set 1, MGC Mode; set 0, AGC Mode. +* +* \retval 0. +*/ +extern int32_t UCP_API_TRANSCEIVER_MGC_Cfg(uint8_t en); + +/** +* \brief Sets up the transceiver's rx gain at MGC mode. +* +* \param gain_db (Unit db, range 0~36, step 0.5db). +* +* \retval 0. +*/ +extern int32_t UCP_API_TRANSCEIVER_Gain_Set(double gain_db); + +/** +* \brief Get the transceiver's rx gain. +* +* \param gain_db (Unit db, range 0~36, step 0.5db). +* +* \retval gain_db (Unit db, range 0~36, step 0.5db). +*/ +extern double UCP_API_TRANSCEIVER_Gain_Get(void); + +/** +* \brief Set up the transceiver's tx attenuation. +* +* \param att_db (Unit db, range 0~20). +* +* \retval 0. +*/ +extern int32_t UCP_API_TRANSCEIVER_Att_Set(uint8_t att_db); + +/** +* \brief Get the transceiver's tx attenuation. +* +* \retval att_db (Unit db, range 0~20). +*/ +extern uint8_t UCP_API_TRANSCEIVER_Att_Get(void); + +//********************************************************************************** +// CLOCKGEN +/** +* \brief clockGen chip hardware reset. +* +* \param void. +* +* \retval void. +*/ +extern void UCP_API_CLOCKGEN_Reset(void); + +/** +* \brief clockGen chip init function. +* +* \param void. +* +* \retval void. +*/ +extern int32_t UCP_API_CLOCKGEN_Init(void); + +/** +* \brief Get the status of clockGen chip's pll. +* +* \param void. +* +* \retval lock code. +*/ +extern uint8_t UCP_API_CLOCKGEN_LockStatus(void); + +/** +* \brief gpio of rf controlling +* +* \param setting +* +* \retval none. +*/ +extern void UCP_API_GPIO_Tx (void); +extern void UCP_API_GPIO_Rx (void); +extern void UCP_API_GPIO_Off (void); +extern void UCP_API_GPIO_OrxOn (void); +extern void UCP_API_GPIO_OrxOff (void); +extern void UCP_API_GPIO_TrigOn (void); +extern void UCP_API_GPIO_TrigOff (void); + +/** +* \brief Get board's indx +* +* \param void +* +* \retval + + HW_UNKNOW = 0 + HW_EVMT = 1 + HW_EVMF = 2 + HW_EVB = 3 + HW_EVMY = 4 + HW_OTHER = 254 + HW_MAX = 255 + +*/ +extern uint8_t UCP_API_RFIC_GetBoardInfo (void); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef UCP_API_RFIC_H_ */ + diff --git a/driver/rfic/rf/out/rfic/ucp_jesd_initdata.c b/driver/rfic/rf/out/rfic/ucp_jesd_initdata.c new file mode 100644 index 0000000..4359c17 --- /dev/null +++ b/driver/rfic/rf/out/rfic/ucp_jesd_initdata.c @@ -0,0 +1,347 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_jesd_initdata.c +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-07-11 18:21:00 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#include +#include +#include "ucp_api_jesd.h" + +ucp_jesd_Init_t ucpJesdInitInstNr = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 122880, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 122880, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 122880, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + +ucp_jesd_Init_t ucpJesdInitInstNr_bandwidth200M = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 245760, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 245760, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 245760, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + +ucp_jesd_Init_t ucpJesdInitInstLte2Ant = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 61440, // sampleClock_kHz; + 4, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 1, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 61440, // sampleClock_kHz; + 4, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 1, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 61440, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + +ucp_jesd_Init_t ucpJesdInitInstLte4Ant = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 61440, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 61440, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 61440, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + + +ucp_jesd_Init_t ucpJesdInitInstNr_orx = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 122880, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 122880, // sampleClock_kHz; + 8, // jesd204M + 32, // jesd204K + 8, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 1, // enable + 245760, // sampleClock_kHz; + 2, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 4, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + +ucp_jesd_Init_t ucpJesdInitInstNrFdd2Ant = +{ + { // common + 122880, // devClock_kHz; + 0, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 122880, // sampleClock_kHz; + 4, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 122880, // sampleClock_kHz; + 4, // jesd204M + 32, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 0, // jesd204E + 1, // scramble + 3, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 122880, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + +ucp_jesd_Init_t ucpJesdInitInstNr204C = +{ + { // common + 122880, // devClock_kHz; + 1, // enableJesd204C; + 1 // jesdSubClass; + }, + { // framer + 1, // enable; + 245760, // sampleClock_kHz; + 8, // jesd204M + 64, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 1, // jesd204E + 1, // scramble + 15, // serializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer + { // deframer[0] + 1, // enable + 245760, // sampleClock_kHz; + 8, // jesd204M + 64, // jesd204K + 4, // jesd204F + 16, // jesd204Np + 1, // jesd204E + 1, // scramble + 15, // deserializerLanesEnabled + 0 // syncbOutSelect + }, + { // deframer[1] + 0, // enable + 245760, // sampleClock_kHz; + 0, // jesd204M + 0, // jesd204K + 0, // jesd204F + 0, // jesd204Np + 0, // jesd204E + 0, // scramble + 0, // deserializerLanesEnabled + 1 // syncbOutSelect + } + } +}; + + diff --git a/driver/rfic/rf/ucp/inc/ucp_api_jesd.h b/driver/rfic/rf/ucp/inc/ucp_api_jesd.h new file mode 100644 index 0000000..4b9b503 --- /dev/null +++ b/driver/rfic/rf/ucp/inc/ucp_api_jesd.h @@ -0,0 +1,293 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_api_jesd.h +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-03-04 14:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef UCP_API_JESD_H_ +#define UCP_API_JESD_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief the max channels of trx + */ +#define MAX_UCP_JESD_TRX_CH (4) + +/** + * \brief Data structure to hold UCP API State + */ +typedef enum ucp_jesd_States +{ + UCP_JESD_STATE_POWERONRESET = 0x00, + UCP_JESD_STATE_JSCTRLOK = 0x01, + UCP_JESD_STATE_CRGOK = 0x02, + UCP_JESD_STATE_SUBCTRLOK = 0x04, + UCP_JESD_STATE_204COREOK = 0x08, + UCP_JESD_STATE_PMAOK = 0x10, + UCP_JESD_STATE_TIMEROK = 0x20, + UCP_JESD_STATE_RUN = 0x40 +} ucp_jesd_States_e; + +/** + * \brief Data structure to ape working step + */ +typedef enum ucp_jesd_ApeWorkStep +{ + UCP_JESD_APE_POWERONRESET = 0x00, + UCP_JESD_APE_CLOCKGENRUN = 0x01, + UCP_JESD_APE_CELLRUN = 0x02, +} ucp_jesd_ApeWorkStep_e; + +/** + * \brief Data structure to the level status of trx's control pins. + */ +typedef enum ucp_jesd_gpioEnableLevel +{ + UCP_JESD_TRX_GPIO_DISABLE = 0x00, + UCP_JESD_TRX_GPIO_VALID_HIGH = 0x01, + UCP_JESD_TRX_GPIO_VALID_LOW = 0x02, +} ucp_jesd_gpioEnableLevel_e; + +/** + * \brief Index of trx's control pins. + */ +enum { + GPIO_TRX_TX1 = 0, + GPIO_TRX_TX2, + GPIO_TRX_TX3, + GPIO_TRX_TX4, + GPIO_RF_TX1, + GPIO_RF_TX2, + GPIO_RF_TX3, + GPIO_RF_TX4, + GPIO_SW_TX1, + GPIO_SW_TX2, + GPIO_SW_TX3, + GPIO_SW_TX4, + + GPIO_TRX_RX1, + GPIO_TRX_RX2, + GPIO_TRX_RX3, + GPIO_TRX_RX4, + GPIO_RF_RX1, + GPIO_RF_RX2, + GPIO_RF_RX3, + GPIO_RF_RX4, + GPIO_SW_RX1, + GPIO_SW_RX2, + GPIO_SW_RX3, + GPIO_SW_RX4, + + GPIO_TRX_ORX1, + GPIO_TRX_ORX2, + GPIO_TRX_ORX3, + GPIO_TRX_ORX4, + GPIO_RF_ORX1, + GPIO_RF_ORX2, + GPIO_RF_ORX3, + GPIO_RF_ORX4, + GPIO_SW_ORX1, + GPIO_SW_ORX2, + GPIO_SW_ORX3, + GPIO_SW_ORX4, + + GPIO_TRIGER, + + GPIO_TR_MAX = 40 +}; + +/** + * \brief Data structure to contrl pins of rf's trx + */ + typedef struct ucp_jesd_gpio { + uint8_t port; + uint8_t pin; + uint8_t enableLevel; +} ucp_jesd_gpio_t; + +typedef struct ucp_jesd_tr_gpio { + ucp_jesd_gpio_t trx; + ucp_jesd_gpio_t rf; + ucp_jesd_gpio_t sw; +} ucp_jesd_tr_gpio_t; + +typedef struct ucp_jesd_TrxGpio { + ucp_jesd_tr_gpio_t tx; + ucp_jesd_tr_gpio_t rx; + ucp_jesd_tr_gpio_t orx; +} ucp_jesd_TrxGpio_t; + +/** + * \brief Data structure to configure of trx's contrl pins + */ +typedef struct ucp_jesd_TrxGpioCfg { + char board[16]; + uint32_t version; + uint8_t maxCh; + uint8_t devClkSrc; + int32_t uldelay; + int32_t dldelay; + char lvdsCoupling[16]; + ucp_jesd_gpio_t triger; + ucp_jesd_TrxGpio_t ch[MAX_UCP_JESD_TRX_CH]; +} ucp_jesd_TrxGpioCfg_t; + +/** + * \brief Data structure to hold digital clock settings + */ +typedef struct ucp_jesd_CommonSettings +{ + uint32_t devClock_kHz; /*!< Device clock frequency in kHz */ + uint8_t enableJesd204C; /*!< 1= Enable JESD204C framer, 0 = use JESD204B framer */ + uint8_t jesdSubClass; +} ucp_jesd_CommonSettings_t; + +/** +* \brief Data structure to hold UCP JESD204b Framer configuration settings +*/ +typedef struct ucp_jesd_FrmCfg +{ + uint8_t enable; + uint32_t sampleClock_kHz; /*!< Sample clock frequency in kHz */ + uint8_t jesd204M; /*!< Number of ADCs (0, 2, or 4) where 2 ADCs are required per receive chain (I and Q). */ + uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K must be modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C). */ + uint8_t jesd204F; /*!< Number of bytes(octets) per frame (Valid 1, 2, 4, 8). */ + uint8_t jesd204Np; /*!< converter sample resolution (12, 16, 24). */ + uint8_t jesd204E; /*!< JESD204C E parameter */ + uint8_t scramble; /*!< Scrambling off if framerScramble = 0, if framerScramble > 0 scrambling is enabled */ + uint8_t serializerLanesEnabled; /*!< Serializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ + uint8_t syncbInSelect; /*!< Selects SYNCb input source. Where, 0 = use SYNCBIN0 for this framer, 1 = use SYNCBIN1 for this framer, 2 = use SYNCBIN2 */ + +} ucp_jesd_FrmCfg_t; + +/** +* \brief Data structure to hold the settings for the deframer configuration +*/ +typedef struct ucp_jesd_DfrmCfg +{ + uint8_t enable; + uint32_t sampleClock_kHz; /*!< Sample clock frequency in kHz */ + uint8_t jesd204M; /*!< Number of DACs (0, 2, or 4) - 2 DACs per transmit chain (I and Q) */ + uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K = modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C) */ + uint8_t jesd204F; /*!< Number of bytes(octets) per frame . */ + uint8_t jesd204Np; /*!< converter sample resolution (12, 16) */ + uint8_t jesd204E; /*!< JESD204C E parameter */ + uint8_t scramble; /*!< Scrambling off if scramble = 0, if framerScramble > 0 scrambling is enabled */ + uint8_t deserializerLanesEnabled; /*!< Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ + uint8_t syncbOutSelect; /*!< Selects deframer SYNCBOUT pin (0 = SYNCBOUT0, 1 = SYNCBOUT1, 2 = output SYNCB to SYNCBOUT0 and SYNCBOUT1) */ +} ucp_jesd_DfrmCfg_t; + +/** +* \brief Data structure to hold ucp JESD Framer and Deframer configuration information +*/ +typedef struct ucp_jesd_Init +{ + ucp_jesd_CommonSettings_t common; /*!< Holds settings for CLKPLL and reference clock */ + ucp_jesd_FrmCfg_t framer; /*!< Framer 0 configuration data structures */ + ucp_jesd_DfrmCfg_t deframer[2]; /*!< Deframer 0/1 configuration data structures */ +} ucp_jesd_Init_t; + +/** +* \brief get jesd module's version +* +* \param void +* +* \retval version. +*/ +extern uint32_t UCP_API_JESD_Version(void); + +/** +* \brief Sets up the ape work step +* +* \param step +* UCP_JESD_APE_POWERONRESET: when jesd reset or power up, set this value +* UCP_JESD_APE_CLOCKGENRUN: when clock gen chip sets up, set this value +* UCP_JESD_APE_CELLRUN: when cell and trx set up, set this value +* +* \retval none. +*/ +extern void UCP_API_JESD_ApeWorkStep(ucp_jesd_ApeWorkStep_e step); + +/** +* \brief Sets up the gpios of tx and rx +* +* \param setting +* +* \retval none. +*/ +extern void UCP_API_JESD_TrxGpioSetup (const char *trxGpioConfigFile, uint16_t enLog); + +/** +* \brief Gets the gpio's inf of tx and rx +* +* \param void +* +* \retval TrxGpioCfg point. +*/ +extern ucp_jesd_TrxGpioCfg_t* UCP_API_JESD_TrxGpioGet (void); + + +/** +* \brief Sets up the ucp4008 jesd's para setting +* +* \param setting +* +* \retval none. +*/ +extern ucp_jesd_States_e UCP_API_JESD_Init (ucp_jesd_Init_t *setting); + +/** +* \brief Sets up the ucp4008 jesd's para setting +* +* \param setting +* +* \retval none. +*/ +extern ucp_jesd_States_e UCP_API_JESD_CellSetup (ucp_jesd_Init_t *setting); + +/** +* \brief Sets up the ucp4008 jesd's para setting +* +* \param setting +* +* \retval none. +*/ +extern void UCP_API_JESD_CellDelete (void); + +/** +* \brief gpio of rf controlling +* +* \param setting +* +* \retval none. +*/ +extern int ucp_jesd_gpioSet(const int pinIdex, int value); +extern int ucp_jesd_gpioGet(const int pinIdex); +extern void UCP_API_GPIO_Tx (void); +extern void UCP_API_GPIO_Rx (void); +extern void UCP_API_GPIO_On (void); +extern void UCP_API_GPIO_Off (void); +extern void UCP_API_GPIO_OrxOn (void); +extern void UCP_API_GPIO_OrxOff (void); +extern void UCP_API_GPIO_TrigOn (void); +extern void UCP_API_GPIO_TrigOff (void); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef UCP_API_JESD_H_ */ + diff --git a/driver/rfic/rf/ucp/libjesd.a b/driver/rfic/rf/ucp/libjesd.a new file mode 100644 index 0000000..34304f0 Binary files /dev/null and b/driver/rfic/rf/ucp/libjesd.a differ diff --git a/driver/rfic/script/app_download.exp b/driver/rfic/script/app_download.exp new file mode 100644 index 0000000..05560ca --- /dev/null +++ b/driver/rfic/script/app_download.exp @@ -0,0 +1,28 @@ +#!/usr/bin/expect + +set port [lindex $argv 0] +set ip 172.29.118 + +set timeout -1 +spawn ssh root@$ip.$port rm -rf /root/rfic.out *.txt +expect { + "password" {send "root\r"} +} +expect eof + +set timeout -1 +spawn scp -r ../rf/out/app/rfic.out root@$ip.$port:/root/ +expect { + "password" {send "root\r"} +} +expect eof + +set timeout -1 +spawn ssh root@$ip.$port sync; +expect { + "password" {send "root\r"} +} +expect eof + + + diff --git a/driver/rfic/script/b b/driver/rfic/script/b new file mode 100644 index 0000000..fd8b796 --- /dev/null +++ b/driver/rfic/script/b @@ -0,0 +1,6 @@ +#!/usr/bin/sh + +make -C ../ clr +make -C ../ + + diff --git a/driver/rfic/script/bd b/driver/rfic/script/bd new file mode 100644 index 0000000..9a3c4a5 --- /dev/null +++ b/driver/rfic/script/bd @@ -0,0 +1,8 @@ +#!/usr/bin/sh + +make -C ../ clr +make -C ../ +expect app_download.exp $1 + +echo '\n\n--------------------- download app ok ------------------------------------\n\n' + diff --git a/driver/rfic/script/c b/driver/rfic/script/c new file mode 100644 index 0000000..8c95886 --- /dev/null +++ b/driver/rfic/script/c @@ -0,0 +1,3 @@ +#!/usr/bin/sh + +make -C ../ clr \ No newline at end of file diff --git a/driver/rfic/script/commit b/driver/rfic/script/commit new file mode 100644 index 0000000..a05008d --- /dev/null +++ b/driver/rfic/script/commit @@ -0,0 +1,2 @@ +make -C ../ clr +rsync -avuz --exclude ".svn" --exclude ".git" --delete /home/daya/work/ucp2/ucp4008_rfic/ /mnt/d/work/Smartlogic/UCP2.0/project/ucp4008_rfic/ \ No newline at end of file diff --git a/driver/rfic/script/d b/driver/rfic/script/d new file mode 100644 index 0000000..99e3cab --- /dev/null +++ b/driver/rfic/script/d @@ -0,0 +1,3 @@ +#!/usr/bin/sh + +expect app_download.exp $1 \ No newline at end of file diff --git a/driver/rfic/script/debuginf.exp b/driver/rfic/script/debuginf.exp new file mode 100644 index 0000000..ab8e2ed --- /dev/null +++ b/driver/rfic/script/debuginf.exp @@ -0,0 +1,8 @@ +#!/usr/bin/expect + +set timeout -1 +spawn scp -r ssh@192.168.20.240:/root/*.txt /mnt/d/work/Smartlogic/UCP2.0/ucp4008_nr_integrated_small_cell/driver/rfic/ +expect { + "password" {send "111111\r"} +} +expect eof \ No newline at end of file diff --git a/driver/rfic/script/download.exp b/driver/rfic/script/download.exp new file mode 100644 index 0000000..972e86b --- /dev/null +++ b/driver/rfic/script/download.exp @@ -0,0 +1,43 @@ +#!/usr/bin/expect + +set port [lindex $argv 0] +#set ip 172.29.118 +set ip 192.168.20 + +set timeout -1 +spawn ssh root@$ip.$port rm -rf /root/rfic +expect { + "password" {send "root\r"} +} +expect eof + +set timeout -1 +spawn ssh root@$ip.$port rm -rf /root/*.txt; +expect { + "password" {send "root\r"} +} +expect eof + +set timeout -1 +spawn scp -r ./build/msgtransfer.out ./driver/rfic/csubin/256QAM/ ./driver/rfic/csubin/256QAM/start.sh root@$ip.$port:/root/ +expect { + "password" {send "root\r"} +} +expect eof + +set timeout -1 +spawn scp -r ./driver/rfic/resources/ucp_trx_gpioCfg_evmy.json ./driver/rfic/resources/ucp_trx_gpioCfg_evb.json root@$ip.$port:/lib/firmware/resources/ +expect { + "password" {send "root\r"} +} +expect eof + +set timeout -1 +spawn ssh root@$ip.$port sync; +expect { + "password" {send "root\r"} +} +expect eof + + + diff --git a/driver/rfic/script/r b/driver/rfic/script/r new file mode 100644 index 0000000..f91b932 --- /dev/null +++ b/driver/rfic/script/r @@ -0,0 +1,3 @@ +#!/usr/bin/sh + +expect root.exp $1 \ No newline at end of file diff --git a/driver/rfic/script/rbd b/driver/rfic/script/rbd new file mode 100644 index 0000000..19d93e2 --- /dev/null +++ b/driver/rfic/script/rbd @@ -0,0 +1,10 @@ +#!/usr/bin/sh + +expect root.exp $1 + +make -C ../ clr +make -C ../ +expect app_download.exp $1 + +echo '\n\n--------------------- download app ok ------------------------------------\n\n' + diff --git a/driver/rfic/script/rd b/driver/rfic/script/rd new file mode 100644 index 0000000..68d197d --- /dev/null +++ b/driver/rfic/script/rd @@ -0,0 +1,4 @@ +#!/usr/bin/sh + +expect root.exp $1 +expect app_download.exp $1 \ No newline at end of file diff --git a/driver/rfic/script/root.exp b/driver/rfic/script/root.exp new file mode 100644 index 0000000..a19d64e --- /dev/null +++ b/driver/rfic/script/root.exp @@ -0,0 +1,19 @@ +#!/usr/bin/expect + +set port [lindex $argv 0] +set ip 172.29.118 +set hosts /home/daya/.ssh/known_hosts + +spawn rm $hosts + +set timeout -1 +spawn ssh root@$ip.$port +expect { + "yes/no" {send "yes\r"} +} + +set timeout 3 +expect { + "password" {send "root\r"} +} +expect eof \ No newline at end of file diff --git a/driver/rfic/ucp/api/inc/ucp_api_jesd.h b/driver/rfic/ucp/api/inc/ucp_api_jesd.h new file mode 100644 index 0000000..4b9b503 --- /dev/null +++ b/driver/rfic/ucp/api/inc/ucp_api_jesd.h @@ -0,0 +1,293 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_api_jesd.h +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-03-04 14:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef UCP_API_JESD_H_ +#define UCP_API_JESD_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief the max channels of trx + */ +#define MAX_UCP_JESD_TRX_CH (4) + +/** + * \brief Data structure to hold UCP API State + */ +typedef enum ucp_jesd_States +{ + UCP_JESD_STATE_POWERONRESET = 0x00, + UCP_JESD_STATE_JSCTRLOK = 0x01, + UCP_JESD_STATE_CRGOK = 0x02, + UCP_JESD_STATE_SUBCTRLOK = 0x04, + UCP_JESD_STATE_204COREOK = 0x08, + UCP_JESD_STATE_PMAOK = 0x10, + UCP_JESD_STATE_TIMEROK = 0x20, + UCP_JESD_STATE_RUN = 0x40 +} ucp_jesd_States_e; + +/** + * \brief Data structure to ape working step + */ +typedef enum ucp_jesd_ApeWorkStep +{ + UCP_JESD_APE_POWERONRESET = 0x00, + UCP_JESD_APE_CLOCKGENRUN = 0x01, + UCP_JESD_APE_CELLRUN = 0x02, +} ucp_jesd_ApeWorkStep_e; + +/** + * \brief Data structure to the level status of trx's control pins. + */ +typedef enum ucp_jesd_gpioEnableLevel +{ + UCP_JESD_TRX_GPIO_DISABLE = 0x00, + UCP_JESD_TRX_GPIO_VALID_HIGH = 0x01, + UCP_JESD_TRX_GPIO_VALID_LOW = 0x02, +} ucp_jesd_gpioEnableLevel_e; + +/** + * \brief Index of trx's control pins. + */ +enum { + GPIO_TRX_TX1 = 0, + GPIO_TRX_TX2, + GPIO_TRX_TX3, + GPIO_TRX_TX4, + GPIO_RF_TX1, + GPIO_RF_TX2, + GPIO_RF_TX3, + GPIO_RF_TX4, + GPIO_SW_TX1, + GPIO_SW_TX2, + GPIO_SW_TX3, + GPIO_SW_TX4, + + GPIO_TRX_RX1, + GPIO_TRX_RX2, + GPIO_TRX_RX3, + GPIO_TRX_RX4, + GPIO_RF_RX1, + GPIO_RF_RX2, + GPIO_RF_RX3, + GPIO_RF_RX4, + GPIO_SW_RX1, + GPIO_SW_RX2, + GPIO_SW_RX3, + GPIO_SW_RX4, + + GPIO_TRX_ORX1, + GPIO_TRX_ORX2, + GPIO_TRX_ORX3, + GPIO_TRX_ORX4, + GPIO_RF_ORX1, + GPIO_RF_ORX2, + GPIO_RF_ORX3, + GPIO_RF_ORX4, + GPIO_SW_ORX1, + GPIO_SW_ORX2, + GPIO_SW_ORX3, + GPIO_SW_ORX4, + + GPIO_TRIGER, + + GPIO_TR_MAX = 40 +}; + +/** + * \brief Data structure to contrl pins of rf's trx + */ + typedef struct ucp_jesd_gpio { + uint8_t port; + uint8_t pin; + uint8_t enableLevel; +} ucp_jesd_gpio_t; + +typedef struct ucp_jesd_tr_gpio { + ucp_jesd_gpio_t trx; + ucp_jesd_gpio_t rf; + ucp_jesd_gpio_t sw; +} ucp_jesd_tr_gpio_t; + +typedef struct ucp_jesd_TrxGpio { + ucp_jesd_tr_gpio_t tx; + ucp_jesd_tr_gpio_t rx; + ucp_jesd_tr_gpio_t orx; +} ucp_jesd_TrxGpio_t; + +/** + * \brief Data structure to configure of trx's contrl pins + */ +typedef struct ucp_jesd_TrxGpioCfg { + char board[16]; + uint32_t version; + uint8_t maxCh; + uint8_t devClkSrc; + int32_t uldelay; + int32_t dldelay; + char lvdsCoupling[16]; + ucp_jesd_gpio_t triger; + ucp_jesd_TrxGpio_t ch[MAX_UCP_JESD_TRX_CH]; +} ucp_jesd_TrxGpioCfg_t; + +/** + * \brief Data structure to hold digital clock settings + */ +typedef struct ucp_jesd_CommonSettings +{ + uint32_t devClock_kHz; /*!< Device clock frequency in kHz */ + uint8_t enableJesd204C; /*!< 1= Enable JESD204C framer, 0 = use JESD204B framer */ + uint8_t jesdSubClass; +} ucp_jesd_CommonSettings_t; + +/** +* \brief Data structure to hold UCP JESD204b Framer configuration settings +*/ +typedef struct ucp_jesd_FrmCfg +{ + uint8_t enable; + uint32_t sampleClock_kHz; /*!< Sample clock frequency in kHz */ + uint8_t jesd204M; /*!< Number of ADCs (0, 2, or 4) where 2 ADCs are required per receive chain (I and Q). */ + uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K must be modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C). */ + uint8_t jesd204F; /*!< Number of bytes(octets) per frame (Valid 1, 2, 4, 8). */ + uint8_t jesd204Np; /*!< converter sample resolution (12, 16, 24). */ + uint8_t jesd204E; /*!< JESD204C E parameter */ + uint8_t scramble; /*!< Scrambling off if framerScramble = 0, if framerScramble > 0 scrambling is enabled */ + uint8_t serializerLanesEnabled; /*!< Serializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ + uint8_t syncbInSelect; /*!< Selects SYNCb input source. Where, 0 = use SYNCBIN0 for this framer, 1 = use SYNCBIN1 for this framer, 2 = use SYNCBIN2 */ + +} ucp_jesd_FrmCfg_t; + +/** +* \brief Data structure to hold the settings for the deframer configuration +*/ +typedef struct ucp_jesd_DfrmCfg +{ + uint8_t enable; + uint32_t sampleClock_kHz; /*!< Sample clock frequency in kHz */ + uint8_t jesd204M; /*!< Number of DACs (0, 2, or 4) - 2 DACs per transmit chain (I and Q) */ + uint16_t jesd204K; /*!< Number of frames in a multiframe. Default = 32, F*K = modulo 4. Where, F=2*M/numberOfLanes (Max 32 for JESD204B, Max 256 for JESD204C) */ + uint8_t jesd204F; /*!< Number of bytes(octets) per frame . */ + uint8_t jesd204Np; /*!< converter sample resolution (12, 16) */ + uint8_t jesd204E; /*!< JESD204C E parameter */ + uint8_t scramble; /*!< Scrambling off if scramble = 0, if framerScramble > 0 scrambling is enabled */ + uint8_t deserializerLanesEnabled; /*!< Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ + uint8_t syncbOutSelect; /*!< Selects deframer SYNCBOUT pin (0 = SYNCBOUT0, 1 = SYNCBOUT1, 2 = output SYNCB to SYNCBOUT0 and SYNCBOUT1) */ +} ucp_jesd_DfrmCfg_t; + +/** +* \brief Data structure to hold ucp JESD Framer and Deframer configuration information +*/ +typedef struct ucp_jesd_Init +{ + ucp_jesd_CommonSettings_t common; /*!< Holds settings for CLKPLL and reference clock */ + ucp_jesd_FrmCfg_t framer; /*!< Framer 0 configuration data structures */ + ucp_jesd_DfrmCfg_t deframer[2]; /*!< Deframer 0/1 configuration data structures */ +} ucp_jesd_Init_t; + +/** +* \brief get jesd module's version +* +* \param void +* +* \retval version. +*/ +extern uint32_t UCP_API_JESD_Version(void); + +/** +* \brief Sets up the ape work step +* +* \param step +* UCP_JESD_APE_POWERONRESET: when jesd reset or power up, set this value +* UCP_JESD_APE_CLOCKGENRUN: when clock gen chip sets up, set this value +* UCP_JESD_APE_CELLRUN: when cell and trx set up, set this value +* +* \retval none. +*/ +extern void UCP_API_JESD_ApeWorkStep(ucp_jesd_ApeWorkStep_e step); + +/** +* \brief Sets up the gpios of tx and rx +* +* \param setting +* +* \retval none. +*/ +extern void UCP_API_JESD_TrxGpioSetup (const char *trxGpioConfigFile, uint16_t enLog); + +/** +* \brief Gets the gpio's inf of tx and rx +* +* \param void +* +* \retval TrxGpioCfg point. +*/ +extern ucp_jesd_TrxGpioCfg_t* UCP_API_JESD_TrxGpioGet (void); + + +/** +* \brief Sets up the ucp4008 jesd's para setting +* +* \param setting +* +* \retval none. +*/ +extern ucp_jesd_States_e UCP_API_JESD_Init (ucp_jesd_Init_t *setting); + +/** +* \brief Sets up the ucp4008 jesd's para setting +* +* \param setting +* +* \retval none. +*/ +extern ucp_jesd_States_e UCP_API_JESD_CellSetup (ucp_jesd_Init_t *setting); + +/** +* \brief Sets up the ucp4008 jesd's para setting +* +* \param setting +* +* \retval none. +*/ +extern void UCP_API_JESD_CellDelete (void); + +/** +* \brief gpio of rf controlling +* +* \param setting +* +* \retval none. +*/ +extern int ucp_jesd_gpioSet(const int pinIdex, int value); +extern int ucp_jesd_gpioGet(const int pinIdex); +extern void UCP_API_GPIO_Tx (void); +extern void UCP_API_GPIO_Rx (void); +extern void UCP_API_GPIO_On (void); +extern void UCP_API_GPIO_Off (void); +extern void UCP_API_GPIO_OrxOn (void); +extern void UCP_API_GPIO_OrxOff (void); +extern void UCP_API_GPIO_TrigOn (void); +extern void UCP_API_GPIO_TrigOff (void); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef UCP_API_JESD_H_ */ + diff --git a/driver/rfic/ucp/api/src/ucp_api_jesd.c b/driver/rfic/ucp/api/src/ucp_api_jesd.c new file mode 100644 index 0000000..8554701 --- /dev/null +++ b/driver/rfic/ucp/api/src/ucp_api_jesd.c @@ -0,0 +1,148 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_api_jesd.c +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-03-04 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#include +#include +#include +#include "ucp_reg_io.h" +#include "ucp_api_jesd.h" +#include "ucp_jesd_gpio.h" +#include "../../base/inc/ucp_hardware.h" + +#define API_VERSION 1 +#define MAJOR_VERSION 1 +#define MINOR_VERSION 17 +#define CUSTOM_VERSION 0 + +#define VER_INF \ +"version 001: 2023.05.26 - 合并9.8G\n", \ +"version 002: 2023.06.06 - lte OK\n", \ +"version 003: 2023.06.09 - power 在 251 上拉齐到 20dbm\n", \ +"version 004: 2023.06.26 - new interface\n", \ +"version 005: 2023.07.06 - 时钟与 TR 初始化分离\n", \ +"version 006: 2023.07.24 - new api，NR OK\n", \ +"version 007: 2023.08.08 - new api，LTE OK. 添加编译开关 signal=NR(LTE)\n", \ +"version 008: 2023.09.01 - 修正 evmy 板 RF 控制引脚错配到 TRX 控制引脚的问题，解决 251 evmy 板配置失败问题\n", \ +"version 009: 2023.09.04 - 修正 tx rx rf 默认配置，使其上电不使能\n", \ +"version 010: 2023.09.27 - 修改共享内存地址\n", \ +"version 011: 2023.10.18 - 添加 ORX， JSON 可配时钟源\n", \ +"version 012: 2023.10.25 - 添加 EVMYF 分支\n", \ +"version 1.1.5.0: 2023.10.31 - 正确配置 NR、NR200、LTE、ORX\n" \ +"version 1.1.6.0: 2023.10.31 - RF GPIO 控制逻辑来自于配置文件 \n" \ +"version 1.1.7.0: 2023.11.01 - 修改共享参数基地址 \n" \ +"version 1.1.8.0: 2023.11.01 - 修改 EVMT、EVMF 不匹配的 GPIO \n" \ +"version 1.1.9.0: 2023.11.08 - 修改 EVMT、EVMF 不匹配的 GPIO \n" \ +"version 1.1.10.0: 2023.11.09 - 更新 evmt 校准参数 \n" \ +"version 1.1.11.0: 2023.11.14 - 添加 TRX、RF、SW 控制 GPIO JSON \n" \ +"version 1.1.12.0: 2023.11.21 - 板卡解耦, EVMY JSON 添加 TRX GPIO \n" \ +"version 1.1.13.0: 2023.11.24 - EVMT、EVMY ORX 添加 sniff 切换逻辑，EVB TRX 收发采用 SPI 模式 \n" \ +"version 1.1.14.0: 2023.11.29 - 调整源码组织格式 \n" \ +"version 1.1.15.0: 2024.01.02 - 修改 rfic 配置 json \n" \ +"version 1.1.16.0: 2024.01.18 - 修改共享参数错误 \n" \ +"version 1.1.17.0: 2024.04.24 - 添加 lvdsCoupling 解析 \n" + +extern void ucp_jesd_pcsReset(void); +extern void ucp_jesd_init(ucp_jesd_Init_t *setting); +static ucp_jesd_TrxGpioCfg_t gTrxGpioCfg; + +uint32_t UCP_API_JESD_Version(void) +{ + printf("JesdVersion: %d.%d.%d.%d\n", API_VERSION, MAJOR_VERSION, MINOR_VERSION, CUSTOM_VERSION); + printf("Compile @%s, %s\n", __TIME__, __DATE__); + + return ((API_VERSION << 24) + (MAJOR_VERSION << 16) + (MINOR_VERSION << 8) + CUSTOM_VERSION); +} + +void UCP_API_JESD_ApeWorkStep(ucp_jesd_ApeWorkStep_e step) +{ + ucp_reg32_write(SERDES_INIT_FLAG_ADDR, step); + if (step > 0) + { + printf("ApeWorkStep@ %d\n", step); + } +} + +void UCP_API_JESD_TrxGpioSetup (const char *trxGpioConfigFile, uint16_t enLog) +{ + ucp_reg_init(); + memset(&gTrxGpioCfg, 0, sizeof(gTrxGpioCfg)); + gTrxGpioCfg = ucp_jesd_gpioInit(trxGpioConfigFile, enLog); +} + +ucp_jesd_TrxGpioCfg_t* UCP_API_JESD_TrxGpioGet (void) +{ + return (ucp_jesd_TrxGpioCfg_t*)&gTrxGpioCfg; +} + +ucp_jesd_States_e UCP_API_JESD_Init (ucp_jesd_Init_t *setting) +{ + ucp_jesd_pcsReset(); + ucp_jesd_init(setting); + + return UCP_JESD_STATE_POWERONRESET; +} + +ucp_jesd_States_e UCP_API_JESD_CellSetup (ucp_jesd_Init_t *setting) +{ + return UCP_API_JESD_Init(setting); +} + +void UCP_API_JESD_CellDelete (void) +{ + ucp_jesd_pcsReset(); + + return; +} + +void UCP_API_GPIO_Tx (void) +{ + ucp_jesd_gpio_tx(); +} + +void UCP_API_GPIO_Rx (void) +{ + ucp_jesd_gpio_rx(); +} + +void UCP_API_GPIO_On (void) +{ + ucp_jesd_gpio_on(); +} + +void UCP_API_GPIO_Off (void) +{ + ucp_jesd_gpio_off(); +} + +void UCP_API_GPIO_OrxOn (void) +{ + ucp_jesd_gpio_orxOn(); +} + +void UCP_API_GPIO_OrxOff (void) +{ + ucp_jesd_gpio_orxOff(); +} + +void UCP_API_GPIO_TrigOn (void) +{ + ucp_jesd_gpio_trigOn(); +} + +void UCP_API_GPIO_TrigOff (void) +{ + ucp_jesd_gpio_trigOff(); +} + + + + diff --git a/driver/rfic/ucp/api/src/ucp_api_jesd.o b/driver/rfic/ucp/api/src/ucp_api_jesd.o new file mode 100644 index 0000000..549a095 Binary files /dev/null and b/driver/rfic/ucp/api/src/ucp_api_jesd.o differ diff --git a/driver/rfic/ucp/base/inc/csu.h b/driver/rfic/ucp/base/inc/csu.h new file mode 100644 index 0000000..97abcd6 --- /dev/null +++ b/driver/rfic/ucp/base/inc/csu.h @@ -0,0 +1,4002 @@ +//******************** (C) COPYRIGHT 2019 SmartLogic******************************* +// FileName : csu.h +// Author : chenwl, weilu.chen@smartlogictech.com +// Date First Issued : 2021-11-23 02:49:13 PM +// Last Modified : 2021-11-23 08:11:05 AM +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** +#ifndef __CSU_H__ +#define __CSU_H__ + + +#define APC_CSU_BASE 0x00400000 //SPU config +#define APC0_CSU_BASE 0x04A90000 +#define APC1_CSU_BASE 0x04AE0000 +#define APC2_CSU_BASE 0x04B30000 +#define APC3_CSU_BASE 0x04B80000 +#define ECSRFM_CSU_BASE 0x08610000 +#define PETRFM_CSU_BASE 0x08F50000 +#define AP_CSU_BASE 0x04258000 +#define RFC_CSU_BASE 0x04DE0000 +#define JS_CSU_BASE 0x05F60000 +#define JECS_CSU_BASE 0x08470000 + + +#define APC_CSU_ALLPENDEVENTMASK0 (APC_CSU_BASE+0x000*4) +#define APC_CSU_ALLPENDEVENTMASK1 (APC_CSU_BASE+0x001*4) +#define APC_CSU_EVENTMASKL (APC_CSU_BASE+0x002*4) +#define APC_CSU_EVENTMASKH (APC_CSU_BASE+0x003*4) +#define APC_CSU_INTMASKL (APC_CSU_BASE+0x004*4) +#define APC_CSU_INTMASKH (APC_CSU_BASE+0x005*4) +#define APC_CSU_TAGMASK (APC_CSU_BASE+0x007*4) +#define APC_CSU_DMATYPE (APC_CSU_BASE+0x008*4) +#define APC_CSU_ARMCMDRECV (APC_CSU_BASE+0x00A*4) +#define APC_CSU_ALLPENDEVENT0 (APC_CSU_BASE+0x00C*4) +#define APC_CSU_ALLPENDEVENT1 (APC_CSU_BASE+0x00D*4) +#define APC_CSU_EM_BS_SMSEL_PREDATANUM (APC_CSU_BASE+0x010*4) +#define APC_CSU_CACHEINFO_EM_BS_SPURWCACHE_SMSEL_PDNUM (APC_CSU_BASE+0x010*4) +#define APC_CSU_ALMOSTFULLSENDTHRED (APC_CSU_BASE+0x011*4) +#define APC_CSU_FINDDMATAG (APC_CSU_BASE+0x014*4) +#define APC_CSU_CMDFIFO0_CMD (APC_CSU_BASE+0x018*4) +#define APC_CSU_CMDFIFO1_CMD (APC_CSU_BASE+0x019*4) +#define APC_CSU_CMDFIFO2_CMD (APC_CSU_BASE+0x01A*4) +#define APC_CSU_CMDFIFO3_CMD (APC_CSU_BASE+0x01B*4) +#define APC_CSU_CMDFIFO0_NUM (APC_CSU_BASE+0x01C*4) +#define APC_CSU_CMDFIFO1_NUM (APC_CSU_BASE+0x01D*4) +#define APC_CSU_CMDFIFO2_NUM (APC_CSU_BASE+0x01E*4) +#define APC_CSU_CMDFIFO3_NUM (APC_CSU_BASE+0x01F*4) +#define APC_CSU_PRICMDVALID0 (APC_CSU_BASE+0x020*4) +#define APC_CSU_PRICMDVALID1 (APC_CSU_BASE+0x021*4) +#define APC_CSU_PRICMDVALID2 (APC_CSU_BASE+0x022*4) +#define APC_CSU_PRICMDVALID3 (APC_CSU_BASE+0x023*4) +#define APC_CSU_CMDECODATAL32BIT0 (APC_CSU_BASE+0x024*4) +#define APC_CSU_CMDECODATAL32BIT1 (APC_CSU_BASE+0x025*4) +#define APC_CSU_CMDECODATAL32BIT2 (APC_CSU_BASE+0x026*4) +#define APC_CSU_CMDECODATAL32BIT3 (APC_CSU_BASE+0x027*4) +#define APC_CSU_CMDHIGHDATA (APC_CSU_BASE+0x028*4) +#define APC_CSU_CMDFIFO0 (APC_CSU_BASE+0x02C*4) +#define APC_CSU_CMDFIFO1 (APC_CSU_BASE+0x02D*4) +#define APC_CSU_CMDFIFO2 (APC_CSU_BASE+0x02E*4) +#define APC_CSU_CMDFIFO3 (APC_CSU_BASE+0x02F*4) +#define APC_CSU_READYLISTNUM (APC_CSU_BASE+0x030*4) +#define APC_CSU_CMDFIFO0_TAGNUM (APC_CSU_BASE+0x034*4) +#define APC_CSU_CMDFIFO1_TAGNUM (APC_CSU_BASE+0x035*4) +#define APC_CSU_CMDFIFO2_TAGNUM (APC_CSU_BASE+0x036*4) +#define APC_CSU_CMDFIFO3_TAGNUM (APC_CSU_BASE+0x037*4) +#define APC_CSU_DMASTATUS (APC_CSU_BASE+0x038*4) +#define APC_CSU_CMDSTALL_LISTSTALL (APC_CSU_BASE+0x039*4) +#define APC_CSU_QOUSTATUS (APC_CSU_BASE+0x03A*4) +#define APC_CSU_EVENTINTCLEAR (APC_CSU_BASE+0x03C*4) +#define APC_CSU_MAILBOX_PRIDATAREG0 (APC_CSU_BASE+0x100*4) +#define APC_CSU_MAILBOX_PRIDATAREG1 (APC_CSU_BASE+0x101*4) +#define APC_CSU_MAILBOX_PRIDATAREG2 (APC_CSU_BASE+0x102*4) +#define APC_CSU_MAILBOX_PRIDATAREG3 (APC_CSU_BASE+0x103*4) +#define APC_CSU_MAILBOX_PRIDATAREG4 (APC_CSU_BASE+0x104*4) +#define APC_CSU_MAILBOX_PRIDATAREG5 (APC_CSU_BASE+0x105*4) +#define APC_CSU_MAILBOX_PRIDATAREG6 (APC_CSU_BASE+0x106*4) +#define APC_CSU_MAILBOX_PRIDATAREG7 (APC_CSU_BASE+0x107*4) +#define APC_CSU_MAILBOX_PRIDATAREG8 (APC_CSU_BASE+0x108*4) +#define APC_CSU_MAILBOX_PRIDATAREG9 (APC_CSU_BASE+0x109*4) +#define APC_CSU_MAILBOX_PRIDATAREG10 (APC_CSU_BASE+0x10A*4) +#define APC_CSU_MAILBOX_PRIDATAREG11 (APC_CSU_BASE+0x10B*4) +#define APC_CSU_MAILBOX_PRIDATAREG12 (APC_CSU_BASE+0x10C*4) +#define APC_CSU_MAILBOX_PRIDATAREG13 (APC_CSU_BASE+0x10D*4) +#define APC_CSU_MAILBOX_PRIDATAREG14 (APC_CSU_BASE+0x10E*4) +#define APC_CSU_MAILBOX_PRIDATAREG15 (APC_CSU_BASE+0x10F*4) +#define APC_CSU_MAILBOX_BASENUM (APC_CSU_BASE+0x120*4) +#define APC_CSU_MAILBOX_BASECNT (APC_CSU_BASE+0x121*4) +#define APC_CSU_MAILBOX_VALIDREG (APC_CSU_BASE+0x122*4) +#define APC_CSU_MAILBOX_INTMASK0 (APC_CSU_BASE+0x124*4) +#define APC_CSU_MAILBOX_INTMASK1 (APC_CSU_BASE+0x125*4) +#define APC_CSU_MAILBOX_INTMASK2 (APC_CSU_BASE+0x126*4) +#define APC_CSU_MAILBOX_INTMASK3 (APC_CSU_BASE+0x127*4) +#define APC_CSU_MAILBOX_EVENTMASK0 (APC_CSU_BASE+0x130*4) +#define APC_CSU_MAILBOX_EVENTMASK1 (APC_CSU_BASE+0x131*4) +#define APC_CSU_MAILBOX_CNTREG0 (APC_CSU_BASE+0x180*4) +#define APC_CSU_MAILBOX_CNTREG1 (APC_CSU_BASE+0x181*4) +#define APC_CSU_MAILBOX_CNTREG2 (APC_CSU_BASE+0x182*4) +#define APC_CSU_MAILBOX_CNTREG3 (APC_CSU_BASE+0x183*4) +#define APC_CSU_MAILBOX_CNTREG4 (APC_CSU_BASE+0x184*4) +#define APC_CSU_MAILBOX_CNTREG5 (APC_CSU_BASE+0x185*4) +#define APC_CSU_MAILBOX_CNTREG6 (APC_CSU_BASE+0x186*4) +#define APC_CSU_MAILBOX_CNTREG7 (APC_CSU_BASE+0x187*4) +#define APC_CSU_MAILBOX_CNTREG8 (APC_CSU_BASE+0x188*4) +#define APC_CSU_MAILBOX_CNTREG9 (APC_CSU_BASE+0x189*4) +#define APC_CSU_MAILBOX_CNTREG10 (APC_CSU_BASE+0x18A*4) +#define APC_CSU_MAILBOX_CNTREG11 (APC_CSU_BASE+0x18B*4) +#define APC_CSU_MAILBOX_CNTREG12 (APC_CSU_BASE+0x18C*4) +#define APC_CSU_MAILBOX_CNTREG13 (APC_CSU_BASE+0x18D*4) +#define APC_CSU_MAILBOX_CNTREG14 (APC_CSU_BASE+0x18E*4) +#define APC_CSU_MAILBOX_CNTREG15 (APC_CSU_BASE+0x18F*4) +#define APC_CSU_DMAADDRL0 (APC_CSU_BASE+0x200*4) +#define APC_CSU_DMAADDRH0 (APC_CSU_BASE+0x201*4) +#define APC_CSU_DMAYSTEPL0 (APC_CSU_BASE+0x202*4) +#define APC_CSU_DMAYSTEPH0 (APC_CSU_BASE+0x203*4) +#define APC_CSU_DMAZSTEPL0 (APC_CSU_BASE+0x204*4) +#define APC_CSU_DMAZSTEPH0 (APC_CSU_BASE+0x205*4) +#define APC_CSU_DMAYNUMXNUM0 (APC_CSU_BASE+0x206*4) +#define APC_CSU_DMASIZEGRANALLNUM0 (APC_CSU_BASE+0x207*4) +#define APC_CSU_DMAADDRL1 (APC_CSU_BASE+0x208*4) +#define APC_CSU_DMAADDRH1 (APC_CSU_BASE+0x209*4) +#define APC_CSU_DMAYSTEPL1 (APC_CSU_BASE+0x20A*4) +#define APC_CSU_DMAYSTEPH1 (APC_CSU_BASE+0x20B*4) +#define APC_CSU_DMAZSTEPL1 (APC_CSU_BASE+0x20C*4) +#define APC_CSU_DMAZSTEPH1 (APC_CSU_BASE+0x20D*4) +#define APC_CSU_DMAYNUMXNUM1 (APC_CSU_BASE+0x20E*4) +#define APC_CSU_DMASIZEGRANALLNUM1 (APC_CSU_BASE+0x20F*4) +#define APC_CSU_DMAADDRL2 (APC_CSU_BASE+0x210*4) +#define APC_CSU_DMAADDRH2 (APC_CSU_BASE+0x211*4) +#define APC_CSU_DMAYSTEPL2 (APC_CSU_BASE+0x212*4) +#define APC_CSU_DMAYSTEPH2 (APC_CSU_BASE+0x213*4) +#define APC_CSU_DMAZSTEPL2 (APC_CSU_BASE+0x214*4) +#define APC_CSU_DMAZSTEPH2 (APC_CSU_BASE+0x215*4) +#define APC_CSU_DMAYNUMXNUM2 (APC_CSU_BASE+0x216*4) +#define APC_CSU_DMASIZEGRANALLNUM2 (APC_CSU_BASE+0x217*4) +#define APC_CSU_DMAADDRL3 (APC_CSU_BASE+0x218*4) +#define APC_CSU_DMAADDRH3 (APC_CSU_BASE+0x219*4) +#define APC_CSU_DMAYSTEPL3 (APC_CSU_BASE+0x21A*4) +#define APC_CSU_DMAYSTEPH3 (APC_CSU_BASE+0x21B*4) +#define APC_CSU_DMAZSTEPL3 (APC_CSU_BASE+0x21C*4) +#define APC_CSU_DMAZSTEPH3 (APC_CSU_BASE+0x21D*4) +#define APC_CSU_DMAYNUMXNUM3 (APC_CSU_BASE+0x21E*4) +#define APC_CSU_DMASIZEGRANALLNUM3 (APC_CSU_BASE+0x21F*4) +#define APC_CSU_DMAADDRL4 (APC_CSU_BASE+0x220*4) +#define APC_CSU_DMAADDRH4 (APC_CSU_BASE+0x221*4) +#define APC_CSU_DMAYSTEPL4 (APC_CSU_BASE+0x222*4) +#define APC_CSU_DMAYSTEPH4 (APC_CSU_BASE+0x223*4) +#define APC_CSU_DMAZSTEPL4 (APC_CSU_BASE+0x224*4) +#define APC_CSU_DMAZSTEPH4 (APC_CSU_BASE+0x225*4) +#define APC_CSU_DMAYNUMXNUM4 (APC_CSU_BASE+0x226*4) +#define APC_CSU_DMASIZEGRANALLNUM4 (APC_CSU_BASE+0x227*4) +#define APC_CSU_DMAADDRL5 (APC_CSU_BASE+0x228*4) +#define APC_CSU_DMAADDRH5 (APC_CSU_BASE+0x229*4) +#define APC_CSU_DMAYSTEPL5 (APC_CSU_BASE+0x22A*4) +#define APC_CSU_DMAYSTEPH5 (APC_CSU_BASE+0x22B*4) +#define APC_CSU_DMAZSTEPL5 (APC_CSU_BASE+0x22C*4) +#define APC_CSU_DMAZSTEPH5 (APC_CSU_BASE+0x22D*4) +#define APC_CSU_DMAYNUMXNUM5 (APC_CSU_BASE+0x22E*4) +#define APC_CSU_DMASIZEGRANALLNUM5 (APC_CSU_BASE+0x22F*4) +#define APC_CSU_DMAADDRL6 (APC_CSU_BASE+0x230*4) +#define APC_CSU_DMAADDRH6 (APC_CSU_BASE+0x231*4) +#define APC_CSU_DMAYSTEPL6 (APC_CSU_BASE+0x232*4) +#define APC_CSU_DMAYSTEPH6 (APC_CSU_BASE+0x233*4) +#define APC_CSU_DMAZSTEPL6 (APC_CSU_BASE+0x234*4) +#define APC_CSU_DMAZSTEPH6 (APC_CSU_BASE+0x235*4) +#define APC_CSU_DMAYNUMXNUM6 (APC_CSU_BASE+0x236*4) +#define APC_CSU_DMASIZEGRANALLNUM6 (APC_CSU_BASE+0x237*4) +#define APC_CSU_DMAADDRL7 (APC_CSU_BASE+0x238*4) +#define APC_CSU_DMAADDRH7 (APC_CSU_BASE+0x239*4) +#define APC_CSU_DMAYSTEPL7 (APC_CSU_BASE+0x23A*4) +#define APC_CSU_DMAYSTEPH7 (APC_CSU_BASE+0x23B*4) +#define APC_CSU_DMAZSTEPL7 (APC_CSU_BASE+0x23C*4) +#define APC_CSU_DMAZSTEPH7 (APC_CSU_BASE+0x23D*4) +#define APC_CSU_DMAYNUMXNUM7 (APC_CSU_BASE+0x23E*4) +#define APC_CSU_DMASIZEGRANALLNUM7 (APC_CSU_BASE+0x23F*4) +#define APC_CSU_DMAADDRL8 (APC_CSU_BASE+0x240*4) +#define APC_CSU_DMAADDRH8 (APC_CSU_BASE+0x241*4) +#define APC_CSU_DMAYSTEPL8 (APC_CSU_BASE+0x242*4) +#define APC_CSU_DMAYSTEPH8 (APC_CSU_BASE+0x243*4) +#define APC_CSU_DMAZSTEPL8 (APC_CSU_BASE+0x244*4) +#define APC_CSU_DMAZSTEPH8 (APC_CSU_BASE+0x245*4) +#define APC_CSU_DMAYNUMXNUM8 (APC_CSU_BASE+0x246*4) +#define APC_CSU_DMASIZEGRANALLNUM8 (APC_CSU_BASE+0x247*4) +#define APC_CSU_DMAADDRL9 (APC_CSU_BASE+0x248*4) +#define APC_CSU_DMAADDRH9 (APC_CSU_BASE+0x249*4) +#define APC_CSU_DMAYSTEPL9 (APC_CSU_BASE+0x24A*4) +#define APC_CSU_DMAYSTEPH9 (APC_CSU_BASE+0x24B*4) +#define APC_CSU_DMAZSTEPL9 (APC_CSU_BASE+0x24C*4) +#define APC_CSU_DMAZSTEPH9 (APC_CSU_BASE+0x24D*4) +#define APC_CSU_DMAYNUMXNUM9 (APC_CSU_BASE+0x24E*4) +#define APC_CSU_DMASIZEGRANALLNUM9 (APC_CSU_BASE+0x24F*4) +#define APC_CSU_DMAADDRL10 (APC_CSU_BASE+0x250*4) +#define APC_CSU_DMAADDRH10 (APC_CSU_BASE+0x251*4) +#define APC_CSU_DMAYSTEPL10 (APC_CSU_BASE+0x252*4) +#define APC_CSU_DMAYSTEPH10 (APC_CSU_BASE+0x253*4) +#define APC_CSU_DMAZSTEPL10 (APC_CSU_BASE+0x254*4) +#define APC_CSU_DMAZSTEPH10 (APC_CSU_BASE+0x255*4) +#define APC_CSU_DMAYNUMXNUM10 (APC_CSU_BASE+0x256*4) +#define APC_CSU_DMASIZEGRANALLNUM10 (APC_CSU_BASE+0x257*4) +#define APC_CSU_DMAADDRL11 (APC_CSU_BASE+0x258*4) +#define APC_CSU_DMAADDRH11 (APC_CSU_BASE+0x259*4) +#define APC_CSU_DMAYSTEPL11 (APC_CSU_BASE+0x25A*4) +#define APC_CSU_DMAYSTEPH11 (APC_CSU_BASE+0x25B*4) +#define APC_CSU_DMAZSTEPL11 (APC_CSU_BASE+0x25C*4) +#define APC_CSU_DMAZSTEPH11 (APC_CSU_BASE+0x25D*4) +#define APC_CSU_DMAYNUMXNUM11 (APC_CSU_BASE+0x25E*4) +#define APC_CSU_DMASIZEGRANALLNUM11 (APC_CSU_BASE+0x25F*4) +#define APC_CSU_DMAADDRL12 (APC_CSU_BASE+0x260*4) +#define APC_CSU_DMAADDRH12 (APC_CSU_BASE+0x261*4) +#define APC_CSU_DMAYSTEPL12 (APC_CSU_BASE+0x262*4) +#define APC_CSU_DMAYSTEPH12 (APC_CSU_BASE+0x263*4) +#define APC_CSU_DMAZSTEPL12 (APC_CSU_BASE+0x264*4) +#define APC_CSU_DMAZSTEPH12 (APC_CSU_BASE+0x265*4) +#define APC_CSU_DMAYNUMXNUM12 (APC_CSU_BASE+0x266*4) +#define APC_CSU_DMASIZEGRANALLNUM12 (APC_CSU_BASE+0x267*4) +#define APC_CSU_DMAADDRL13 (APC_CSU_BASE+0x268*4) +#define APC_CSU_DMAADDRH13 (APC_CSU_BASE+0x269*4) +#define APC_CSU_DMAYSTEPL13 (APC_CSU_BASE+0x26A*4) +#define APC_CSU_DMAYSTEPH13 (APC_CSU_BASE+0x26B*4) +#define APC_CSU_DMAZSTEPL13 (APC_CSU_BASE+0x26C*4) +#define APC_CSU_DMAZSTEPH13 (APC_CSU_BASE+0x26D*4) +#define APC_CSU_DMAYNUMXNUM13 (APC_CSU_BASE+0x26E*4) +#define APC_CSU_DMASIZEGRANALLNUM13 (APC_CSU_BASE+0x26F*4) +#define APC_CSU_DMAADDRL14 (APC_CSU_BASE+0x270*4) +#define APC_CSU_DMAADDRH14 (APC_CSU_BASE+0x271*4) +#define APC_CSU_DMAYSTEPL14 (APC_CSU_BASE+0x272*4) +#define APC_CSU_DMAYSTEPH14 (APC_CSU_BASE+0x273*4) +#define APC_CSU_DMAZSTEPL14 (APC_CSU_BASE+0x274*4) +#define APC_CSU_DMAZSTEPH14 (APC_CSU_BASE+0x275*4) +#define APC_CSU_DMAYNUMXNUM14 (APC_CSU_BASE+0x276*4) +#define APC_CSU_DMASIZEGRANALLNUM14 (APC_CSU_BASE+0x277*4) +#define APC_CSU_DMAADDRL15 (APC_CSU_BASE+0x278*4) +#define APC_CSU_DMAADDRH15 (APC_CSU_BASE+0x279*4) +#define APC_CSU_DMAYSTEPL15 (APC_CSU_BASE+0x27A*4) +#define APC_CSU_DMAYSTEPH15 (APC_CSU_BASE+0x27B*4) +#define APC_CSU_DMAZSTEPL15 (APC_CSU_BASE+0x27C*4) +#define APC_CSU_DMAZSTEPH15 (APC_CSU_BASE+0x27D*4) +#define APC_CSU_DMAYNUMXNUM15 (APC_CSU_BASE+0x27E*4) +#define APC_CSU_DMASIZEGRANALLNUM15 (APC_CSU_BASE+0x27F*4) +#define APC_CSU_QOUCMDNUM_QOUCMDPOS (APC_CSU_BASE+0x300*4) +#define APC_CSU_QOUCMDADDR (APC_CSU_BASE+0x301*4) +#define APC_CSU_QOUCMDDATA (APC_CSU_BASE+0x302*4) +#define APC_CSU_QOUSTATUSPOPDATA (APC_CSU_BASE+0x303*4) +#define APC_CSU_QOUCMPDATA0 (APC_CSU_BASE+0x304*4) +#define APC_CSU_QOUCMPDATA1 (APC_CSU_BASE+0x305*4) +#define APC_CSU_QOUCMPDATA2 (APC_CSU_BASE+0x306*4) +#define APC_CSU_QOUCMPDATA3 (APC_CSU_BASE+0x307*4) +#define APC_CSU_SPUID (APC_CSU_BASE+0x30B*4) +#define APC_CSU_PRICMDDATA_L32BIT0 (APC_CSU_BASE+0x310*4) +#define APC_CSU_PRICMDDATA_H14BIT0 (APC_CSU_BASE+0x311*4) +#define APC_CSU_PRICMDDATA_L32BIT1 (APC_CSU_BASE+0x312*4) +#define APC_CSU_PRICMDDATA_H14BIT1 (APC_CSU_BASE+0x313*4) +#define APC_CSU_PRICMDDATA_L32BIT2 (APC_CSU_BASE+0x314*4) +#define APC_CSU_PRICMDDATA_H14BIT2 (APC_CSU_BASE+0x315*4) +#define APC_CSU_PRICMDDATA_L32BIT3 (APC_CSU_BASE+0x316*4) +#define APC_CSU_PRICMDDATA_H14BIT3 (APC_CSU_BASE+0x317*4) +#define APC_CSU_SORTDATA_NUM (APC_CSU_BASE+0x380*4) +#define APC_CSU_SORTDATA_DATA0 (APC_CSU_BASE+0x3C0*4) +#define APC_CSU_SORTDATA_DATA1 (APC_CSU_BASE+0x3C1*4) +#define APC_CSU_SORTDATA_DATA2 (APC_CSU_BASE+0x3C2*4) +#define APC_CSU_SORTDATA_DATA3 (APC_CSU_BASE+0x3C3*4) +#define APC_CSU_SORTDATA_DATA4 (APC_CSU_BASE+0x3C4*4) +#define APC_CSU_SORTDATA_DATA5 (APC_CSU_BASE+0x3C5*4) +#define APC_CSU_SORTDATA_DATA6 (APC_CSU_BASE+0x3C6*4) +#define APC_CSU_SORTDATA_DATA7 (APC_CSU_BASE+0x3C7*4) +#define APC_CSU_SORTDATA_DATA8 (APC_CSU_BASE+0x3C8*4) +#define APC_CSU_SORTDATA_DATA9 (APC_CSU_BASE+0x3C9*4) +#define APC_CSU_SORTDATA_DATA10 (APC_CSU_BASE+0x3CA*4) +#define APC_CSU_SORTDATA_DATA11 (APC_CSU_BASE+0x3CB*4) +#define APC_CSU_SORTDATA_DATA12 (APC_CSU_BASE+0x3CC*4) +#define APC_CSU_SORTDATA_DATA13 (APC_CSU_BASE+0x3CD*4) +#define APC_CSU_SORTDATA_DATA14 (APC_CSU_BASE+0x3CE*4) +#define APC_CSU_SORTDATA_DATA15 (APC_CSU_BASE+0x3CF*4) +#define APC_CSU_SORTDATA_DATA16 (APC_CSU_BASE+0x3D0*4) +#define APC_CSU_SORTDATA_DATA17 (APC_CSU_BASE+0x3D1*4) +#define APC_CSU_SORTDATA_DATA18 (APC_CSU_BASE+0x3D2*4) +#define APC_CSU_SORTDATA_DATA19 (APC_CSU_BASE+0x3D3*4) +#define APC_CSU_SORTDATA_DATA20 (APC_CSU_BASE+0x3D4*4) +#define APC_CSU_SORTDATA_DATA21 (APC_CSU_BASE+0x3D5*4) +#define APC_CSU_SORTDATA_DATA22 (APC_CSU_BASE+0x3D6*4) +#define APC_CSU_SORTDATA_DATA23 (APC_CSU_BASE+0x3D7*4) +#define APC_CSU_SORTDATA_DATA24 (APC_CSU_BASE+0x3D8*4) +#define APC_CSU_SORTDATA_DATA25 (APC_CSU_BASE+0x3D9*4) +#define APC_CSU_SORTDATA_DATA26 (APC_CSU_BASE+0x3DA*4) +#define APC_CSU_SORTDATA_DATA27 (APC_CSU_BASE+0x3DB*4) +#define APC_CSU_SORTDATA_DATA28 (APC_CSU_BASE+0x3DC*4) +#define APC_CSU_SORTDATA_DATA29 (APC_CSU_BASE+0x3DD*4) +#define APC_CSU_SORTDATA_DATA30 (APC_CSU_BASE+0x3DE*4) +#define APC_CSU_SORTDATA_DATA31 (APC_CSU_BASE+0x3DF*4) +#define APC_CSU_SORTDATA_ID0 (APC_CSU_BASE+0x3E0*4) +#define APC_CSU_SORTDATA_ID1 (APC_CSU_BASE+0x3E1*4) +#define APC_CSU_SORTDATA_ID2 (APC_CSU_BASE+0x3E2*4) +#define APC_CSU_SORTDATA_ID3 (APC_CSU_BASE+0x3E3*4) +#define APC_CSU_SORTDATA_ID4 (APC_CSU_BASE+0x3E4*4) +#define APC_CSU_SORTDATA_ID5 (APC_CSU_BASE+0x3E5*4) +#define APC_CSU_SORTDATA_ID6 (APC_CSU_BASE+0x3E6*4) +#define APC_CSU_SORTDATA_ID7 (APC_CSU_BASE+0x3E7*4) +#define APC_CSU_SORTDATA_ID8 (APC_CSU_BASE+0x3E8*4) +#define APC_CSU_SORTDATA_ID9 (APC_CSU_BASE+0x3E9*4) +#define APC_CSU_SORTDATA_ID10 (APC_CSU_BASE+0x3EA*4) +#define APC_CSU_SORTDATA_ID11 (APC_CSU_BASE+0x3EB*4) +#define APC_CSU_SORTDATA_ID12 (APC_CSU_BASE+0x3EC*4) +#define APC_CSU_SORTDATA_ID13 (APC_CSU_BASE+0x3ED*4) +#define APC_CSU_SORTDATA_ID14 (APC_CSU_BASE+0x3EE*4) +#define APC_CSU_SORTDATA_ID15 (APC_CSU_BASE+0x3EF*4) +#define APC_CSU_SORTDATA_ID16 (APC_CSU_BASE+0x3F0*4) +#define APC_CSU_SORTDATA_ID17 (APC_CSU_BASE+0x3F1*4) +#define APC_CSU_SORTDATA_ID18 (APC_CSU_BASE+0x3F2*4) +#define APC_CSU_SORTDATA_ID19 (APC_CSU_BASE+0x3F3*4) +#define APC_CSU_SORTDATA_ID20 (APC_CSU_BASE+0x3F4*4) +#define APC_CSU_SORTDATA_ID21 (APC_CSU_BASE+0x3F5*4) +#define APC_CSU_SORTDATA_ID22 (APC_CSU_BASE+0x3F6*4) +#define APC_CSU_SORTDATA_ID23 (APC_CSU_BASE+0x3F7*4) +#define APC_CSU_SORTDATA_ID24 (APC_CSU_BASE+0x3F8*4) +#define APC_CSU_SORTDATA_ID25 (APC_CSU_BASE+0x3F9*4) +#define APC_CSU_SORTDATA_ID26 (APC_CSU_BASE+0x3FA*4) +#define APC_CSU_SORTDATA_ID27 (APC_CSU_BASE+0x3FB*4) +#define APC_CSU_SORTDATA_ID28 (APC_CSU_BASE+0x3FC*4) +#define APC_CSU_SORTDATA_ID29 (APC_CSU_BASE+0x3FD*4) +#define APC_CSU_SORTDATA_ID30 (APC_CSU_BASE+0x3FE*4) +#define APC_CSU_SORTDATA_ID31 (APC_CSU_BASE+0x3FF*4) + + +#define APC0_CSU_STARTSPU0 (APC0_CSU_BASE+0x000*4) +#define APC0_CSU_ALLPENDEVENTMASK (APC0_CSU_BASE+0x000*4) +#define APC0_CSU_STARTSPU1 (APC0_CSU_BASE+0x001*4) +#define APC0_CSU_EVENTMASK (APC0_CSU_BASE+0x002*4) +#define APC0_CSU_INTMASK (APC0_CSU_BASE+0x004*4) +#define APC0_CSU_ELEVELMASK (APC0_CSU_BASE+0x005*4) +#define APC0_CSU_TAGMASK0 (APC0_CSU_BASE+0x006*4) +#define APC0_CSU_TAGMASK1 (APC0_CSU_BASE+0x007*4) +#define APC0_CSU_TAGMASK2 (APC0_CSU_BASE+0x008*4) +#define APC0_CSU_TAGMASK3 (APC0_CSU_BASE+0x009*4) +#define APC0_CSU_ARMCMDRECV (APC0_CSU_BASE+0x00A*4) +#define APC0_CSU_FETCHMODE_CACHEMODE (APC0_CSU_BASE+0x00B*4) +#define APC0_CSU_ALLPENDEVENT0 (APC0_CSU_BASE+0x00C*4) +#define APC0_CSU_ALLPENDEVENT1 (APC0_CSU_BASE+0x00D*4) +#define APC0_CSU_EM_BS_SMSEL_PREDATANUM (APC0_CSU_BASE+0x010*4) +#define APC0_CSU_CACHEINFO_EM_BS_SPURWCACHE_SMSEL_PDNUM (APC0_CSU_BASE+0x010*4) +#define APC0_CSU_ALMOSTFULLSENDTHRED (APC0_CSU_BASE+0x011*4) +#define APC0_CSU_FINDDMATAG (APC0_CSU_BASE+0x014*4) +#define APC0_CSU_CMDFIFO0_CMD (APC0_CSU_BASE+0x018*4) +#define APC0_CSU_CMDFIFO1_CMD (APC0_CSU_BASE+0x019*4) +#define APC0_CSU_CMDFIFO2_CMD (APC0_CSU_BASE+0x01A*4) +#define APC0_CSU_CMDFIFO3_CMD (APC0_CSU_BASE+0x01B*4) +#define APC0_CSU_CMDFIFO0_NUM (APC0_CSU_BASE+0x01C*4) +#define APC0_CSU_CMDFIFO1_NUM (APC0_CSU_BASE+0x01D*4) +#define APC0_CSU_CMDFIFO2_NUM (APC0_CSU_BASE+0x01E*4) +#define APC0_CSU_CMDFIFO3_NUM (APC0_CSU_BASE+0x01F*4) +#define APC0_CSU_PRICMDVALID0 (APC0_CSU_BASE+0x020*4) +#define APC0_CSU_PRICMDVALID1 (APC0_CSU_BASE+0x021*4) +#define APC0_CSU_PRICMDVALID2 (APC0_CSU_BASE+0x022*4) +#define APC0_CSU_PRICMDVALID3 (APC0_CSU_BASE+0x023*4) +#define APC0_CSU_CMDECODATAL32BIT0 (APC0_CSU_BASE+0x024*4) +#define APC0_CSU_CMDECODATAL32BIT1 (APC0_CSU_BASE+0x025*4) +#define APC0_CSU_CMDECODATAL32BIT2 (APC0_CSU_BASE+0x026*4) +#define APC0_CSU_CMDECODATAL32BIT3 (APC0_CSU_BASE+0x027*4) +#define APC0_CSU_CMDHIGHDATA (APC0_CSU_BASE+0x028*4) +#define APC0_CSU_CMDFIFO0 (APC0_CSU_BASE+0x02C*4) +#define APC0_CSU_CMDFIFO1 (APC0_CSU_BASE+0x02D*4) +#define APC0_CSU_CMDFIFO2 (APC0_CSU_BASE+0x02E*4) +#define APC0_CSU_CMDFIFO3 (APC0_CSU_BASE+0x02F*4) +#define APC0_CSU_READYLISTNUM (APC0_CSU_BASE+0x030*4) +#define APC0_CSU_CMDFIFO0_TAGNUM (APC0_CSU_BASE+0x034*4) +#define APC0_CSU_CMDFIFO1_TAGNUM (APC0_CSU_BASE+0x035*4) +#define APC0_CSU_CMDFIFO2_TAGNUM (APC0_CSU_BASE+0x036*4) +#define APC0_CSU_CMDFIFO3_TAGNUM (APC0_CSU_BASE+0x037*4) +#define APC0_CSU_DMASTATUS (APC0_CSU_BASE+0x038*4) +#define APC0_CSU_CMDSTALL_LISTSTALL (APC0_CSU_BASE+0x039*4) +#define APC0_CSU_QOUSTATUS (APC0_CSU_BASE+0x03A*4) +#define APC0_CSU_EVENTINTCLEAR (APC0_CSU_BASE+0x03C*4) +#define APC0_CSU_MAILBOX_PRIDATAREG0 (APC0_CSU_BASE+0x100*4) +#define APC0_CSU_MAILBOX_PRIDATAREG1 (APC0_CSU_BASE+0x101*4) +#define APC0_CSU_MAILBOX_PRIDATAREG2 (APC0_CSU_BASE+0x102*4) +#define APC0_CSU_MAILBOX_PRIDATAREG3 (APC0_CSU_BASE+0x103*4) +#define APC0_CSU_MAILBOX_PRIDATAREG4 (APC0_CSU_BASE+0x104*4) +#define APC0_CSU_MAILBOX_PRIDATAREG5 (APC0_CSU_BASE+0x105*4) +#define APC0_CSU_MAILBOX_PRIDATAREG6 (APC0_CSU_BASE+0x106*4) +#define APC0_CSU_MAILBOX_PRIDATAREG7 (APC0_CSU_BASE+0x107*4) +#define APC0_CSU_MAILBOX_PRIDATAREG8 (APC0_CSU_BASE+0x108*4) +#define APC0_CSU_MAILBOX_PRIDATAREG9 (APC0_CSU_BASE+0x109*4) +#define APC0_CSU_MAILBOX_PRIDATAREG10 (APC0_CSU_BASE+0x10A*4) +#define APC0_CSU_MAILBOX_PRIDATAREG11 (APC0_CSU_BASE+0x10B*4) +#define APC0_CSU_MAILBOX_PRIDATAREG12 (APC0_CSU_BASE+0x10C*4) +#define APC0_CSU_MAILBOX_PRIDATAREG13 (APC0_CSU_BASE+0x10D*4) +#define APC0_CSU_MAILBOX_PRIDATAREG14 (APC0_CSU_BASE+0x10E*4) +#define APC0_CSU_MAILBOX_PRIDATAREG15 (APC0_CSU_BASE+0x10F*4) +#define APC0_CSU_MAILBOX_BASENUM (APC0_CSU_BASE+0x120*4) +#define APC0_CSU_MAILBOX_BASECNT (APC0_CSU_BASE+0x121*4) +#define APC0_CSU_MAILBOX_VALIDREG (APC0_CSU_BASE+0x122*4) +#define APC0_CSU_MAILBOX_INTMASK0 (APC0_CSU_BASE+0x124*4) +#define APC0_CSU_MAILBOX_INTMASK1 (APC0_CSU_BASE+0x125*4) +#define APC0_CSU_MAILBOX_INTMASK2 (APC0_CSU_BASE+0x126*4) +#define APC0_CSU_MAILBOX_INTMASK3 (APC0_CSU_BASE+0x127*4) +#define APC0_CSU_MAILBOX_EVENTMASK0 (APC0_CSU_BASE+0x130*4) +#define APC0_CSU_MAILBOX_EVENTMASK1 (APC0_CSU_BASE+0x131*4) +#define APC0_CSU_MAILBOX_CNTREG0 (APC0_CSU_BASE+0x180*4) +#define APC0_CSU_MAILBOX_CNTREG1 (APC0_CSU_BASE+0x181*4) +#define APC0_CSU_MAILBOX_CNTREG2 (APC0_CSU_BASE+0x182*4) +#define APC0_CSU_MAILBOX_CNTREG3 (APC0_CSU_BASE+0x183*4) +#define APC0_CSU_MAILBOX_CNTREG4 (APC0_CSU_BASE+0x184*4) +#define APC0_CSU_MAILBOX_CNTREG5 (APC0_CSU_BASE+0x185*4) +#define APC0_CSU_MAILBOX_CNTREG6 (APC0_CSU_BASE+0x186*4) +#define APC0_CSU_MAILBOX_CNTREG7 (APC0_CSU_BASE+0x187*4) +#define APC0_CSU_MAILBOX_CNTREG8 (APC0_CSU_BASE+0x188*4) +#define APC0_CSU_MAILBOX_CNTREG9 (APC0_CSU_BASE+0x189*4) +#define APC0_CSU_MAILBOX_CNTREG10 (APC0_CSU_BASE+0x18A*4) +#define APC0_CSU_MAILBOX_CNTREG11 (APC0_CSU_BASE+0x18B*4) +#define APC0_CSU_MAILBOX_CNTREG12 (APC0_CSU_BASE+0x18C*4) +#define APC0_CSU_MAILBOX_CNTREG13 (APC0_CSU_BASE+0x18D*4) +#define APC0_CSU_MAILBOX_CNTREG14 (APC0_CSU_BASE+0x18E*4) +#define APC0_CSU_MAILBOX_CNTREG15 (APC0_CSU_BASE+0x18F*4) +#define APC0_CSU_DMAADDRL0 (APC0_CSU_BASE+0x200*4) +#define APC0_CSU_DMAADDRH0 (APC0_CSU_BASE+0x201*4) +#define APC0_CSU_DMAYSTEPL0 (APC0_CSU_BASE+0x202*4) +#define APC0_CSU_DMAYSTEPH0 (APC0_CSU_BASE+0x203*4) +#define APC0_CSU_DMAZSTEPL0 (APC0_CSU_BASE+0x204*4) +#define APC0_CSU_DMAZSTEPH0 (APC0_CSU_BASE+0x205*4) +#define APC0_CSU_DMAYNUMXNUM0 (APC0_CSU_BASE+0x206*4) +#define APC0_CSU_DMASIZEGRANALLNUM0 (APC0_CSU_BASE+0x207*4) +#define APC0_CSU_DMAADDRL1 (APC0_CSU_BASE+0x208*4) +#define APC0_CSU_DMAADDRH1 (APC0_CSU_BASE+0x209*4) +#define APC0_CSU_DMAYSTEPL1 (APC0_CSU_BASE+0x20A*4) +#define APC0_CSU_DMAYSTEPH1 (APC0_CSU_BASE+0x20B*4) +#define APC0_CSU_DMAZSTEPL1 (APC0_CSU_BASE+0x20C*4) +#define APC0_CSU_DMAZSTEPH1 (APC0_CSU_BASE+0x20D*4) +#define APC0_CSU_DMAYNUMXNUM1 (APC0_CSU_BASE+0x20E*4) +#define APC0_CSU_DMASIZEGRANALLNUM1 (APC0_CSU_BASE+0x20F*4) +#define APC0_CSU_DMAADDRL2 (APC0_CSU_BASE+0x210*4) +#define APC0_CSU_DMAADDRH2 (APC0_CSU_BASE+0x211*4) +#define APC0_CSU_DMAYSTEPL2 (APC0_CSU_BASE+0x212*4) +#define APC0_CSU_DMAYSTEPH2 (APC0_CSU_BASE+0x213*4) +#define APC0_CSU_DMAZSTEPL2 (APC0_CSU_BASE+0x214*4) +#define APC0_CSU_DMAZSTEPH2 (APC0_CSU_BASE+0x215*4) +#define APC0_CSU_DMAYNUMXNUM2 (APC0_CSU_BASE+0x216*4) +#define APC0_CSU_DMASIZEGRANALLNUM2 (APC0_CSU_BASE+0x217*4) +#define APC0_CSU_DMAADDRL3 (APC0_CSU_BASE+0x218*4) +#define APC0_CSU_DMAADDRH3 (APC0_CSU_BASE+0x219*4) +#define APC0_CSU_DMAYSTEPL3 (APC0_CSU_BASE+0x21A*4) +#define APC0_CSU_DMAYSTEPH3 (APC0_CSU_BASE+0x21B*4) +#define APC0_CSU_DMAZSTEPL3 (APC0_CSU_BASE+0x21C*4) +#define APC0_CSU_DMAZSTEPH3 (APC0_CSU_BASE+0x21D*4) +#define APC0_CSU_DMAYNUMXNUM3 (APC0_CSU_BASE+0x21E*4) +#define APC0_CSU_DMASIZEGRANALLNUM3 (APC0_CSU_BASE+0x21F*4) +#define APC0_CSU_DMAADDRL4 (APC0_CSU_BASE+0x220*4) +#define APC0_CSU_DMAADDRH4 (APC0_CSU_BASE+0x221*4) +#define APC0_CSU_DMAYSTEPL4 (APC0_CSU_BASE+0x222*4) +#define APC0_CSU_DMAYSTEPH4 (APC0_CSU_BASE+0x223*4) +#define APC0_CSU_DMAZSTEPL4 (APC0_CSU_BASE+0x224*4) +#define APC0_CSU_DMAZSTEPH4 (APC0_CSU_BASE+0x225*4) +#define APC0_CSU_DMAYNUMXNUM4 (APC0_CSU_BASE+0x226*4) +#define APC0_CSU_DMASIZEGRANALLNUM4 (APC0_CSU_BASE+0x227*4) +#define APC0_CSU_DMAADDRL5 (APC0_CSU_BASE+0x228*4) +#define APC0_CSU_DMAADDRH5 (APC0_CSU_BASE+0x229*4) +#define APC0_CSU_DMAYSTEPL5 (APC0_CSU_BASE+0x22A*4) +#define APC0_CSU_DMAYSTEPH5 (APC0_CSU_BASE+0x22B*4) +#define APC0_CSU_DMAZSTEPL5 (APC0_CSU_BASE+0x22C*4) +#define APC0_CSU_DMAZSTEPH5 (APC0_CSU_BASE+0x22D*4) +#define APC0_CSU_DMAYNUMXNUM5 (APC0_CSU_BASE+0x22E*4) +#define APC0_CSU_DMASIZEGRANALLNUM5 (APC0_CSU_BASE+0x22F*4) +#define APC0_CSU_DMAADDRL6 (APC0_CSU_BASE+0x230*4) +#define APC0_CSU_DMAADDRH6 (APC0_CSU_BASE+0x231*4) +#define APC0_CSU_DMAYSTEPL6 (APC0_CSU_BASE+0x232*4) +#define APC0_CSU_DMAYSTEPH6 (APC0_CSU_BASE+0x233*4) +#define APC0_CSU_DMAZSTEPL6 (APC0_CSU_BASE+0x234*4) +#define APC0_CSU_DMAZSTEPH6 (APC0_CSU_BASE+0x235*4) +#define APC0_CSU_DMAYNUMXNUM6 (APC0_CSU_BASE+0x236*4) +#define APC0_CSU_DMASIZEGRANALLNUM6 (APC0_CSU_BASE+0x237*4) +#define APC0_CSU_DMAADDRL7 (APC0_CSU_BASE+0x238*4) +#define APC0_CSU_DMAADDRH7 (APC0_CSU_BASE+0x239*4) +#define APC0_CSU_DMAYSTEPL7 (APC0_CSU_BASE+0x23A*4) +#define APC0_CSU_DMAYSTEPH7 (APC0_CSU_BASE+0x23B*4) +#define APC0_CSU_DMAZSTEPL7 (APC0_CSU_BASE+0x23C*4) +#define APC0_CSU_DMAZSTEPH7 (APC0_CSU_BASE+0x23D*4) +#define APC0_CSU_DMAYNUMXNUM7 (APC0_CSU_BASE+0x23E*4) +#define APC0_CSU_DMASIZEGRANALLNUM7 (APC0_CSU_BASE+0x23F*4) +#define APC0_CSU_DMAADDRL8 (APC0_CSU_BASE+0x240*4) +#define APC0_CSU_DMAADDRH8 (APC0_CSU_BASE+0x241*4) +#define APC0_CSU_DMAYSTEPL8 (APC0_CSU_BASE+0x242*4) +#define APC0_CSU_DMAYSTEPH8 (APC0_CSU_BASE+0x243*4) +#define APC0_CSU_DMAZSTEPL8 (APC0_CSU_BASE+0x244*4) +#define APC0_CSU_DMAZSTEPH8 (APC0_CSU_BASE+0x245*4) +#define APC0_CSU_DMAYNUMXNUM8 (APC0_CSU_BASE+0x246*4) +#define APC0_CSU_DMASIZEGRANALLNUM8 (APC0_CSU_BASE+0x247*4) +#define APC0_CSU_DMAADDRL9 (APC0_CSU_BASE+0x248*4) +#define APC0_CSU_DMAADDRH9 (APC0_CSU_BASE+0x249*4) +#define APC0_CSU_DMAYSTEPL9 (APC0_CSU_BASE+0x24A*4) +#define APC0_CSU_DMAYSTEPH9 (APC0_CSU_BASE+0x24B*4) +#define APC0_CSU_DMAZSTEPL9 (APC0_CSU_BASE+0x24C*4) +#define APC0_CSU_DMAZSTEPH9 (APC0_CSU_BASE+0x24D*4) +#define APC0_CSU_DMAYNUMXNUM9 (APC0_CSU_BASE+0x24E*4) +#define APC0_CSU_DMASIZEGRANALLNUM9 (APC0_CSU_BASE+0x24F*4) +#define APC0_CSU_DMAADDRL10 (APC0_CSU_BASE+0x250*4) +#define APC0_CSU_DMAADDRH10 (APC0_CSU_BASE+0x251*4) +#define APC0_CSU_DMAYSTEPL10 (APC0_CSU_BASE+0x252*4) +#define APC0_CSU_DMAYSTEPH10 (APC0_CSU_BASE+0x253*4) +#define APC0_CSU_DMAZSTEPL10 (APC0_CSU_BASE+0x254*4) +#define APC0_CSU_DMAZSTEPH10 (APC0_CSU_BASE+0x255*4) +#define APC0_CSU_DMAYNUMXNUM10 (APC0_CSU_BASE+0x256*4) +#define APC0_CSU_DMASIZEGRANALLNUM10 (APC0_CSU_BASE+0x257*4) +#define APC0_CSU_DMAADDRL11 (APC0_CSU_BASE+0x258*4) +#define APC0_CSU_DMAADDRH11 (APC0_CSU_BASE+0x259*4) +#define APC0_CSU_DMAYSTEPL11 (APC0_CSU_BASE+0x25A*4) +#define APC0_CSU_DMAYSTEPH11 (APC0_CSU_BASE+0x25B*4) +#define APC0_CSU_DMAZSTEPL11 (APC0_CSU_BASE+0x25C*4) +#define APC0_CSU_DMAZSTEPH11 (APC0_CSU_BASE+0x25D*4) +#define APC0_CSU_DMAYNUMXNUM11 (APC0_CSU_BASE+0x25E*4) +#define APC0_CSU_DMASIZEGRANALLNUM11 (APC0_CSU_BASE+0x25F*4) +#define APC0_CSU_DMAADDRL12 (APC0_CSU_BASE+0x260*4) +#define APC0_CSU_DMAADDRH12 (APC0_CSU_BASE+0x261*4) +#define APC0_CSU_DMAYSTEPL12 (APC0_CSU_BASE+0x262*4) +#define APC0_CSU_DMAYSTEPH12 (APC0_CSU_BASE+0x263*4) +#define APC0_CSU_DMAZSTEPL12 (APC0_CSU_BASE+0x264*4) +#define APC0_CSU_DMAZSTEPH12 (APC0_CSU_BASE+0x265*4) +#define APC0_CSU_DMAYNUMXNUM12 (APC0_CSU_BASE+0x266*4) +#define APC0_CSU_DMASIZEGRANALLNUM12 (APC0_CSU_BASE+0x267*4) +#define APC0_CSU_DMAADDRL13 (APC0_CSU_BASE+0x268*4) +#define APC0_CSU_DMAADDRH13 (APC0_CSU_BASE+0x269*4) +#define APC0_CSU_DMAYSTEPL13 (APC0_CSU_BASE+0x26A*4) +#define APC0_CSU_DMAYSTEPH13 (APC0_CSU_BASE+0x26B*4) +#define APC0_CSU_DMAZSTEPL13 (APC0_CSU_BASE+0x26C*4) +#define APC0_CSU_DMAZSTEPH13 (APC0_CSU_BASE+0x26D*4) +#define APC0_CSU_DMAYNUMXNUM13 (APC0_CSU_BASE+0x26E*4) +#define APC0_CSU_DMASIZEGRANALLNUM13 (APC0_CSU_BASE+0x26F*4) +#define APC0_CSU_DMAADDRL14 (APC0_CSU_BASE+0x270*4) +#define APC0_CSU_DMAADDRH14 (APC0_CSU_BASE+0x271*4) +#define APC0_CSU_DMAYSTEPL14 (APC0_CSU_BASE+0x272*4) +#define APC0_CSU_DMAYSTEPH14 (APC0_CSU_BASE+0x273*4) +#define APC0_CSU_DMAZSTEPL14 (APC0_CSU_BASE+0x274*4) +#define APC0_CSU_DMAZSTEPH14 (APC0_CSU_BASE+0x275*4) +#define APC0_CSU_DMAYNUMXNUM14 (APC0_CSU_BASE+0x276*4) +#define APC0_CSU_DMASIZEGRANALLNUM14 (APC0_CSU_BASE+0x277*4) +#define APC0_CSU_DMAADDRL15 (APC0_CSU_BASE+0x278*4) +#define APC0_CSU_DMAADDRH15 (APC0_CSU_BASE+0x279*4) +#define APC0_CSU_DMAYSTEPL15 (APC0_CSU_BASE+0x27A*4) +#define APC0_CSU_DMAYSTEPH15 (APC0_CSU_BASE+0x27B*4) +#define APC0_CSU_DMAZSTEPL15 (APC0_CSU_BASE+0x27C*4) +#define APC0_CSU_DMAZSTEPH15 (APC0_CSU_BASE+0x27D*4) +#define APC0_CSU_DMAYNUMXNUM15 (APC0_CSU_BASE+0x27E*4) +#define APC0_CSU_DMASIZEGRANALLNUM15 (APC0_CSU_BASE+0x27F*4) +#define APC0_CSU_QOUCMDNUM_QOUCMDPOS (APC0_CSU_BASE+0x300*4) +#define APC0_CSU_QOUCMDADDR (APC0_CSU_BASE+0x301*4) +#define APC0_CSU_QOUCMDDATA (APC0_CSU_BASE+0x302*4) +#define APC0_CSU_QOUSTATUSPOPDATA (APC0_CSU_BASE+0x303*4) +#define APC0_CSU_QOUCMPDATA0 (APC0_CSU_BASE+0x304*4) +#define APC0_CSU_QOUCMPDATA1 (APC0_CSU_BASE+0x305*4) +#define APC0_CSU_QOUCMPDATA2 (APC0_CSU_BASE+0x306*4) +#define APC0_CSU_QOUCMPDATA3 (APC0_CSU_BASE+0x307*4) +#define APC0_CSU_SPUID (APC0_CSU_BASE+0x30B*4) +#define APC0_CSU_PRICMDDATA_L32BIT0 (APC0_CSU_BASE+0x310*4) +#define APC0_CSU_PRICMDDATA_H14BIT0 (APC0_CSU_BASE+0x311*4) +#define APC0_CSU_PRICMDDATA_L32BIT1 (APC0_CSU_BASE+0x312*4) +#define APC0_CSU_PRICMDDATA_H14BIT1 (APC0_CSU_BASE+0x313*4) +#define APC0_CSU_PRICMDDATA_L32BIT2 (APC0_CSU_BASE+0x314*4) +#define APC0_CSU_PRICMDDATA_H14BIT2 (APC0_CSU_BASE+0x315*4) +#define APC0_CSU_PRICMDDATA_L32BIT3 (APC0_CSU_BASE+0x316*4) +#define APC0_CSU_PRICMDDATA_H14BIT3 (APC0_CSU_BASE+0x317*4) +#define APC0_CSU_SORTDATA_NUM (APC0_CSU_BASE+0x380*4) +#define APC0_CSU_SORTDATA_DATA0 (APC0_CSU_BASE+0x3C0*4) +#define APC0_CSU_SORTDATA_DATA1 (APC0_CSU_BASE+0x3C1*4) +#define APC0_CSU_SORTDATA_DATA2 (APC0_CSU_BASE+0x3C2*4) +#define APC0_CSU_SORTDATA_DATA3 (APC0_CSU_BASE+0x3C3*4) +#define APC0_CSU_SORTDATA_DATA4 (APC0_CSU_BASE+0x3C4*4) +#define APC0_CSU_SORTDATA_DATA5 (APC0_CSU_BASE+0x3C5*4) +#define APC0_CSU_SORTDATA_DATA6 (APC0_CSU_BASE+0x3C6*4) +#define APC0_CSU_SORTDATA_DATA7 (APC0_CSU_BASE+0x3C7*4) +#define APC0_CSU_SORTDATA_DATA8 (APC0_CSU_BASE+0x3C8*4) +#define APC0_CSU_SORTDATA_DATA9 (APC0_CSU_BASE+0x3C9*4) +#define APC0_CSU_SORTDATA_DATA10 (APC0_CSU_BASE+0x3CA*4) +#define APC0_CSU_SORTDATA_DATA11 (APC0_CSU_BASE+0x3CB*4) +#define APC0_CSU_SORTDATA_DATA12 (APC0_CSU_BASE+0x3CC*4) +#define APC0_CSU_SORTDATA_DATA13 (APC0_CSU_BASE+0x3CD*4) +#define APC0_CSU_SORTDATA_DATA14 (APC0_CSU_BASE+0x3CE*4) +#define APC0_CSU_SORTDATA_DATA15 (APC0_CSU_BASE+0x3CF*4) +#define APC0_CSU_SORTDATA_DATA16 (APC0_CSU_BASE+0x3D0*4) +#define APC0_CSU_SORTDATA_DATA17 (APC0_CSU_BASE+0x3D1*4) +#define APC0_CSU_SORTDATA_DATA18 (APC0_CSU_BASE+0x3D2*4) +#define APC0_CSU_SORTDATA_DATA19 (APC0_CSU_BASE+0x3D3*4) +#define APC0_CSU_SORTDATA_DATA20 (APC0_CSU_BASE+0x3D4*4) +#define APC0_CSU_SORTDATA_DATA21 (APC0_CSU_BASE+0x3D5*4) +#define APC0_CSU_SORTDATA_DATA22 (APC0_CSU_BASE+0x3D6*4) +#define APC0_CSU_SORTDATA_DATA23 (APC0_CSU_BASE+0x3D7*4) +#define APC0_CSU_SORTDATA_DATA24 (APC0_CSU_BASE+0x3D8*4) +#define APC0_CSU_SORTDATA_DATA25 (APC0_CSU_BASE+0x3D9*4) +#define APC0_CSU_SORTDATA_DATA26 (APC0_CSU_BASE+0x3DA*4) +#define APC0_CSU_SORTDATA_DATA27 (APC0_CSU_BASE+0x3DB*4) +#define APC0_CSU_SORTDATA_DATA28 (APC0_CSU_BASE+0x3DC*4) +#define APC0_CSU_SORTDATA_DATA29 (APC0_CSU_BASE+0x3DD*4) +#define APC0_CSU_SORTDATA_DATA30 (APC0_CSU_BASE+0x3DE*4) +#define APC0_CSU_SORTDATA_DATA31 (APC0_CSU_BASE+0x3DF*4) +#define APC0_CSU_SORTDATA_ID0 (APC0_CSU_BASE+0x3E0*4) +#define APC0_CSU_SORTDATA_ID1 (APC0_CSU_BASE+0x3E1*4) +#define APC0_CSU_SORTDATA_ID2 (APC0_CSU_BASE+0x3E2*4) +#define APC0_CSU_SORTDATA_ID3 (APC0_CSU_BASE+0x3E3*4) +#define APC0_CSU_SORTDATA_ID4 (APC0_CSU_BASE+0x3E4*4) +#define APC0_CSU_SORTDATA_ID5 (APC0_CSU_BASE+0x3E5*4) +#define APC0_CSU_SORTDATA_ID6 (APC0_CSU_BASE+0x3E6*4) +#define APC0_CSU_SORTDATA_ID7 (APC0_CSU_BASE+0x3E7*4) +#define APC0_CSU_SORTDATA_ID8 (APC0_CSU_BASE+0x3E8*4) +#define APC0_CSU_SORTDATA_ID9 (APC0_CSU_BASE+0x3E9*4) +#define APC0_CSU_SORTDATA_ID10 (APC0_CSU_BASE+0x3EA*4) +#define APC0_CSU_SORTDATA_ID11 (APC0_CSU_BASE+0x3EB*4) +#define APC0_CSU_SORTDATA_ID12 (APC0_CSU_BASE+0x3EC*4) +#define APC0_CSU_SORTDATA_ID13 (APC0_CSU_BASE+0x3ED*4) +#define APC0_CSU_SORTDATA_ID14 (APC0_CSU_BASE+0x3EE*4) +#define APC0_CSU_SORTDATA_ID15 (APC0_CSU_BASE+0x3EF*4) +#define APC0_CSU_SORTDATA_ID16 (APC0_CSU_BASE+0x3F0*4) +#define APC0_CSU_SORTDATA_ID17 (APC0_CSU_BASE+0x3F1*4) +#define APC0_CSU_SORTDATA_ID18 (APC0_CSU_BASE+0x3F2*4) +#define APC0_CSU_SORTDATA_ID19 (APC0_CSU_BASE+0x3F3*4) +#define APC0_CSU_SORTDATA_ID20 (APC0_CSU_BASE+0x3F4*4) +#define APC0_CSU_SORTDATA_ID21 (APC0_CSU_BASE+0x3F5*4) +#define APC0_CSU_SORTDATA_ID22 (APC0_CSU_BASE+0x3F6*4) +#define APC0_CSU_SORTDATA_ID23 (APC0_CSU_BASE+0x3F7*4) +#define APC0_CSU_SORTDATA_ID24 (APC0_CSU_BASE+0x3F8*4) +#define APC0_CSU_SORTDATA_ID25 (APC0_CSU_BASE+0x3F9*4) +#define APC0_CSU_SORTDATA_ID26 (APC0_CSU_BASE+0x3FA*4) +#define APC0_CSU_SORTDATA_ID27 (APC0_CSU_BASE+0x3FB*4) +#define APC0_CSU_SORTDATA_ID28 (APC0_CSU_BASE+0x3FC*4) +#define APC0_CSU_SORTDATA_ID29 (APC0_CSU_BASE+0x3FD*4) +#define APC0_CSU_SORTDATA_ID30 (APC0_CSU_BASE+0x3FE*4) +#define APC0_CSU_SORTDATA_ID31 (APC0_CSU_BASE+0x3FF*4) + + +#define APC1_CSU_STARTSPU0 (APC1_CSU_BASE+0x000*4) +#define APC1_CSU_ALLPENDEVENTMASK (APC1_CSU_BASE+0x000*4) +#define APC1_CSU_STARTSPU1 (APC1_CSU_BASE+0x001*4) +#define APC1_CSU_EVENTMASK (APC1_CSU_BASE+0x002*4) +#define APC1_CSU_INTMASK (APC1_CSU_BASE+0x004*4) +#define APC1_CSU_ELEVELMASK (APC1_CSU_BASE+0x005*4) +#define APC1_CSU_TAGMASK0 (APC1_CSU_BASE+0x006*4) +#define APC1_CSU_TAGMASK1 (APC1_CSU_BASE+0x007*4) +#define APC1_CSU_TAGMASK2 (APC1_CSU_BASE+0x008*4) +#define APC1_CSU_TAGMASK3 (APC1_CSU_BASE+0x009*4) +#define APC1_CSU_ARMCMDRECV (APC1_CSU_BASE+0x00A*4) +#define APC1_CSU_FETCHMODE_CACHEMODE (APC1_CSU_BASE+0x00B*4) +#define APC1_CSU_ALLPENDEVENT0 (APC1_CSU_BASE+0x00C*4) +#define APC1_CSU_ALLPENDEVENT1 (APC1_CSU_BASE+0x00D*4) +#define APC1_CSU_EM_BS_SMSEL_PREDATANUM (APC1_CSU_BASE+0x010*4) +#define APC1_CSU_CACHEINFO_EM_BS_SPURWCACHE_SMSEL_PDNUM (APC1_CSU_BASE+0x010*4) +#define APC1_CSU_ALMOSTFULLSENDTHRED (APC1_CSU_BASE+0x011*4) +#define APC1_CSU_FINDDMATAG (APC1_CSU_BASE+0x014*4) +#define APC1_CSU_CMDFIFO0_CMD (APC1_CSU_BASE+0x018*4) +#define APC1_CSU_CMDFIFO1_CMD (APC1_CSU_BASE+0x019*4) +#define APC1_CSU_CMDFIFO2_CMD (APC1_CSU_BASE+0x01A*4) +#define APC1_CSU_CMDFIFO3_CMD (APC1_CSU_BASE+0x01B*4) +#define APC1_CSU_CMDFIFO0_NUM (APC1_CSU_BASE+0x01C*4) +#define APC1_CSU_CMDFIFO1_NUM (APC1_CSU_BASE+0x01D*4) +#define APC1_CSU_CMDFIFO2_NUM (APC1_CSU_BASE+0x01E*4) +#define APC1_CSU_CMDFIFO3_NUM (APC1_CSU_BASE+0x01F*4) +#define APC1_CSU_PRICMDVALID0 (APC1_CSU_BASE+0x020*4) +#define APC1_CSU_PRICMDVALID1 (APC1_CSU_BASE+0x021*4) +#define APC1_CSU_PRICMDVALID2 (APC1_CSU_BASE+0x022*4) +#define APC1_CSU_PRICMDVALID3 (APC1_CSU_BASE+0x023*4) +#define APC1_CSU_CMDECODATAL32BIT0 (APC1_CSU_BASE+0x024*4) +#define APC1_CSU_CMDECODATAL32BIT1 (APC1_CSU_BASE+0x025*4) +#define APC1_CSU_CMDECODATAL32BIT2 (APC1_CSU_BASE+0x026*4) +#define APC1_CSU_CMDECODATAL32BIT3 (APC1_CSU_BASE+0x027*4) +#define APC1_CSU_CMDHIGHDATA (APC1_CSU_BASE+0x028*4) +#define APC1_CSU_CMDFIFO0 (APC1_CSU_BASE+0x02C*4) +#define APC1_CSU_CMDFIFO1 (APC1_CSU_BASE+0x02D*4) +#define APC1_CSU_CMDFIFO2 (APC1_CSU_BASE+0x02E*4) +#define APC1_CSU_CMDFIFO3 (APC1_CSU_BASE+0x02F*4) +#define APC1_CSU_READYLISTNUM (APC1_CSU_BASE+0x030*4) +#define APC1_CSU_CMDFIFO0_TAGNUM (APC1_CSU_BASE+0x034*4) +#define APC1_CSU_CMDFIFO1_TAGNUM (APC1_CSU_BASE+0x035*4) +#define APC1_CSU_CMDFIFO2_TAGNUM (APC1_CSU_BASE+0x036*4) +#define APC1_CSU_CMDFIFO3_TAGNUM (APC1_CSU_BASE+0x037*4) +#define APC1_CSU_DMASTATUS (APC1_CSU_BASE+0x038*4) +#define APC1_CSU_CMDSTALL_LISTSTALL (APC1_CSU_BASE+0x039*4) +#define APC1_CSU_QOUSTATUS (APC1_CSU_BASE+0x03A*4) +#define APC1_CSU_EVENTINTCLEAR (APC1_CSU_BASE+0x03C*4) +#define APC1_CSU_MAILBOX_PRIDATAREG0 (APC1_CSU_BASE+0x100*4) +#define APC1_CSU_MAILBOX_PRIDATAREG1 (APC1_CSU_BASE+0x101*4) +#define APC1_CSU_MAILBOX_PRIDATAREG2 (APC1_CSU_BASE+0x102*4) +#define APC1_CSU_MAILBOX_PRIDATAREG3 (APC1_CSU_BASE+0x103*4) +#define APC1_CSU_MAILBOX_PRIDATAREG4 (APC1_CSU_BASE+0x104*4) +#define APC1_CSU_MAILBOX_PRIDATAREG5 (APC1_CSU_BASE+0x105*4) +#define APC1_CSU_MAILBOX_PRIDATAREG6 (APC1_CSU_BASE+0x106*4) +#define APC1_CSU_MAILBOX_PRIDATAREG7 (APC1_CSU_BASE+0x107*4) +#define APC1_CSU_MAILBOX_PRIDATAREG8 (APC1_CSU_BASE+0x108*4) +#define APC1_CSU_MAILBOX_PRIDATAREG9 (APC1_CSU_BASE+0x109*4) +#define APC1_CSU_MAILBOX_PRIDATAREG10 (APC1_CSU_BASE+0x10A*4) +#define APC1_CSU_MAILBOX_PRIDATAREG11 (APC1_CSU_BASE+0x10B*4) +#define APC1_CSU_MAILBOX_PRIDATAREG12 (APC1_CSU_BASE+0x10C*4) +#define APC1_CSU_MAILBOX_PRIDATAREG13 (APC1_CSU_BASE+0x10D*4) +#define APC1_CSU_MAILBOX_PRIDATAREG14 (APC1_CSU_BASE+0x10E*4) +#define APC1_CSU_MAILBOX_PRIDATAREG15 (APC1_CSU_BASE+0x10F*4) +#define APC1_CSU_MAILBOX_BASENUM (APC1_CSU_BASE+0x120*4) +#define APC1_CSU_MAILBOX_BASECNT (APC1_CSU_BASE+0x121*4) +#define APC1_CSU_MAILBOX_VALIDREG (APC1_CSU_BASE+0x122*4) +#define APC1_CSU_MAILBOX_INTMASK0 (APC1_CSU_BASE+0x124*4) +#define APC1_CSU_MAILBOX_INTMASK1 (APC1_CSU_BASE+0x125*4) +#define APC1_CSU_MAILBOX_INTMASK2 (APC1_CSU_BASE+0x126*4) +#define APC1_CSU_MAILBOX_INTMASK3 (APC1_CSU_BASE+0x127*4) +#define APC1_CSU_MAILBOX_EVENTMASK0 (APC1_CSU_BASE+0x130*4) +#define APC1_CSU_MAILBOX_EVENTMASK1 (APC1_CSU_BASE+0x131*4) +#define APC1_CSU_MAILBOX_CNTREG0 (APC1_CSU_BASE+0x180*4) +#define APC1_CSU_MAILBOX_CNTREG1 (APC1_CSU_BASE+0x181*4) +#define APC1_CSU_MAILBOX_CNTREG2 (APC1_CSU_BASE+0x182*4) +#define APC1_CSU_MAILBOX_CNTREG3 (APC1_CSU_BASE+0x183*4) +#define APC1_CSU_MAILBOX_CNTREG4 (APC1_CSU_BASE+0x184*4) +#define APC1_CSU_MAILBOX_CNTREG5 (APC1_CSU_BASE+0x185*4) +#define APC1_CSU_MAILBOX_CNTREG6 (APC1_CSU_BASE+0x186*4) +#define APC1_CSU_MAILBOX_CNTREG7 (APC1_CSU_BASE+0x187*4) +#define APC1_CSU_MAILBOX_CNTREG8 (APC1_CSU_BASE+0x188*4) +#define APC1_CSU_MAILBOX_CNTREG9 (APC1_CSU_BASE+0x189*4) +#define APC1_CSU_MAILBOX_CNTREG10 (APC1_CSU_BASE+0x18A*4) +#define APC1_CSU_MAILBOX_CNTREG11 (APC1_CSU_BASE+0x18B*4) +#define APC1_CSU_MAILBOX_CNTREG12 (APC1_CSU_BASE+0x18C*4) +#define APC1_CSU_MAILBOX_CNTREG13 (APC1_CSU_BASE+0x18D*4) +#define APC1_CSU_MAILBOX_CNTREG14 (APC1_CSU_BASE+0x18E*4) +#define APC1_CSU_MAILBOX_CNTREG15 (APC1_CSU_BASE+0x18F*4) +#define APC1_CSU_DMAADDRL0 (APC1_CSU_BASE+0x200*4) +#define APC1_CSU_DMAADDRH0 (APC1_CSU_BASE+0x201*4) +#define APC1_CSU_DMAYSTEPL0 (APC1_CSU_BASE+0x202*4) +#define APC1_CSU_DMAYSTEPH0 (APC1_CSU_BASE+0x203*4) +#define APC1_CSU_DMAZSTEPL0 (APC1_CSU_BASE+0x204*4) +#define APC1_CSU_DMAZSTEPH0 (APC1_CSU_BASE+0x205*4) +#define APC1_CSU_DMAYNUMXNUM0 (APC1_CSU_BASE+0x206*4) +#define APC1_CSU_DMASIZEGRANALLNUM0 (APC1_CSU_BASE+0x207*4) +#define APC1_CSU_DMAADDRL1 (APC1_CSU_BASE+0x208*4) +#define APC1_CSU_DMAADDRH1 (APC1_CSU_BASE+0x209*4) +#define APC1_CSU_DMAYSTEPL1 (APC1_CSU_BASE+0x20A*4) +#define APC1_CSU_DMAYSTEPH1 (APC1_CSU_BASE+0x20B*4) +#define APC1_CSU_DMAZSTEPL1 (APC1_CSU_BASE+0x20C*4) +#define APC1_CSU_DMAZSTEPH1 (APC1_CSU_BASE+0x20D*4) +#define APC1_CSU_DMAYNUMXNUM1 (APC1_CSU_BASE+0x20E*4) +#define APC1_CSU_DMASIZEGRANALLNUM1 (APC1_CSU_BASE+0x20F*4) +#define APC1_CSU_DMAADDRL2 (APC1_CSU_BASE+0x210*4) +#define APC1_CSU_DMAADDRH2 (APC1_CSU_BASE+0x211*4) +#define APC1_CSU_DMAYSTEPL2 (APC1_CSU_BASE+0x212*4) +#define APC1_CSU_DMAYSTEPH2 (APC1_CSU_BASE+0x213*4) +#define APC1_CSU_DMAZSTEPL2 (APC1_CSU_BASE+0x214*4) +#define APC1_CSU_DMAZSTEPH2 (APC1_CSU_BASE+0x215*4) +#define APC1_CSU_DMAYNUMXNUM2 (APC1_CSU_BASE+0x216*4) +#define APC1_CSU_DMASIZEGRANALLNUM2 (APC1_CSU_BASE+0x217*4) +#define APC1_CSU_DMAADDRL3 (APC1_CSU_BASE+0x218*4) +#define APC1_CSU_DMAADDRH3 (APC1_CSU_BASE+0x219*4) +#define APC1_CSU_DMAYSTEPL3 (APC1_CSU_BASE+0x21A*4) +#define APC1_CSU_DMAYSTEPH3 (APC1_CSU_BASE+0x21B*4) +#define APC1_CSU_DMAZSTEPL3 (APC1_CSU_BASE+0x21C*4) +#define APC1_CSU_DMAZSTEPH3 (APC1_CSU_BASE+0x21D*4) +#define APC1_CSU_DMAYNUMXNUM3 (APC1_CSU_BASE+0x21E*4) +#define APC1_CSU_DMASIZEGRANALLNUM3 (APC1_CSU_BASE+0x21F*4) +#define APC1_CSU_DMAADDRL4 (APC1_CSU_BASE+0x220*4) +#define APC1_CSU_DMAADDRH4 (APC1_CSU_BASE+0x221*4) +#define APC1_CSU_DMAYSTEPL4 (APC1_CSU_BASE+0x222*4) +#define APC1_CSU_DMAYSTEPH4 (APC1_CSU_BASE+0x223*4) +#define APC1_CSU_DMAZSTEPL4 (APC1_CSU_BASE+0x224*4) +#define APC1_CSU_DMAZSTEPH4 (APC1_CSU_BASE+0x225*4) +#define APC1_CSU_DMAYNUMXNUM4 (APC1_CSU_BASE+0x226*4) +#define APC1_CSU_DMASIZEGRANALLNUM4 (APC1_CSU_BASE+0x227*4) +#define APC1_CSU_DMAADDRL5 (APC1_CSU_BASE+0x228*4) +#define APC1_CSU_DMAADDRH5 (APC1_CSU_BASE+0x229*4) +#define APC1_CSU_DMAYSTEPL5 (APC1_CSU_BASE+0x22A*4) +#define APC1_CSU_DMAYSTEPH5 (APC1_CSU_BASE+0x22B*4) +#define APC1_CSU_DMAZSTEPL5 (APC1_CSU_BASE+0x22C*4) +#define APC1_CSU_DMAZSTEPH5 (APC1_CSU_BASE+0x22D*4) +#define APC1_CSU_DMAYNUMXNUM5 (APC1_CSU_BASE+0x22E*4) +#define APC1_CSU_DMASIZEGRANALLNUM5 (APC1_CSU_BASE+0x22F*4) +#define APC1_CSU_DMAADDRL6 (APC1_CSU_BASE+0x230*4) +#define APC1_CSU_DMAADDRH6 (APC1_CSU_BASE+0x231*4) +#define APC1_CSU_DMAYSTEPL6 (APC1_CSU_BASE+0x232*4) +#define APC1_CSU_DMAYSTEPH6 (APC1_CSU_BASE+0x233*4) +#define APC1_CSU_DMAZSTEPL6 (APC1_CSU_BASE+0x234*4) +#define APC1_CSU_DMAZSTEPH6 (APC1_CSU_BASE+0x235*4) +#define APC1_CSU_DMAYNUMXNUM6 (APC1_CSU_BASE+0x236*4) +#define APC1_CSU_DMASIZEGRANALLNUM6 (APC1_CSU_BASE+0x237*4) +#define APC1_CSU_DMAADDRL7 (APC1_CSU_BASE+0x238*4) +#define APC1_CSU_DMAADDRH7 (APC1_CSU_BASE+0x239*4) +#define APC1_CSU_DMAYSTEPL7 (APC1_CSU_BASE+0x23A*4) +#define APC1_CSU_DMAYSTEPH7 (APC1_CSU_BASE+0x23B*4) +#define APC1_CSU_DMAZSTEPL7 (APC1_CSU_BASE+0x23C*4) +#define APC1_CSU_DMAZSTEPH7 (APC1_CSU_BASE+0x23D*4) +#define APC1_CSU_DMAYNUMXNUM7 (APC1_CSU_BASE+0x23E*4) +#define APC1_CSU_DMASIZEGRANALLNUM7 (APC1_CSU_BASE+0x23F*4) +#define APC1_CSU_DMAADDRL8 (APC1_CSU_BASE+0x240*4) +#define APC1_CSU_DMAADDRH8 (APC1_CSU_BASE+0x241*4) +#define APC1_CSU_DMAYSTEPL8 (APC1_CSU_BASE+0x242*4) +#define APC1_CSU_DMAYSTEPH8 (APC1_CSU_BASE+0x243*4) +#define APC1_CSU_DMAZSTEPL8 (APC1_CSU_BASE+0x244*4) +#define APC1_CSU_DMAZSTEPH8 (APC1_CSU_BASE+0x245*4) +#define APC1_CSU_DMAYNUMXNUM8 (APC1_CSU_BASE+0x246*4) +#define APC1_CSU_DMASIZEGRANALLNUM8 (APC1_CSU_BASE+0x247*4) +#define APC1_CSU_DMAADDRL9 (APC1_CSU_BASE+0x248*4) +#define APC1_CSU_DMAADDRH9 (APC1_CSU_BASE+0x249*4) +#define APC1_CSU_DMAYSTEPL9 (APC1_CSU_BASE+0x24A*4) +#define APC1_CSU_DMAYSTEPH9 (APC1_CSU_BASE+0x24B*4) +#define APC1_CSU_DMAZSTEPL9 (APC1_CSU_BASE+0x24C*4) +#define APC1_CSU_DMAZSTEPH9 (APC1_CSU_BASE+0x24D*4) +#define APC1_CSU_DMAYNUMXNUM9 (APC1_CSU_BASE+0x24E*4) +#define APC1_CSU_DMASIZEGRANALLNUM9 (APC1_CSU_BASE+0x24F*4) +#define APC1_CSU_DMAADDRL10 (APC1_CSU_BASE+0x250*4) +#define APC1_CSU_DMAADDRH10 (APC1_CSU_BASE+0x251*4) +#define APC1_CSU_DMAYSTEPL10 (APC1_CSU_BASE+0x252*4) +#define APC1_CSU_DMAYSTEPH10 (APC1_CSU_BASE+0x253*4) +#define APC1_CSU_DMAZSTEPL10 (APC1_CSU_BASE+0x254*4) +#define APC1_CSU_DMAZSTEPH10 (APC1_CSU_BASE+0x255*4) +#define APC1_CSU_DMAYNUMXNUM10 (APC1_CSU_BASE+0x256*4) +#define APC1_CSU_DMASIZEGRANALLNUM10 (APC1_CSU_BASE+0x257*4) +#define APC1_CSU_DMAADDRL11 (APC1_CSU_BASE+0x258*4) +#define APC1_CSU_DMAADDRH11 (APC1_CSU_BASE+0x259*4) +#define APC1_CSU_DMAYSTEPL11 (APC1_CSU_BASE+0x25A*4) +#define APC1_CSU_DMAYSTEPH11 (APC1_CSU_BASE+0x25B*4) +#define APC1_CSU_DMAZSTEPL11 (APC1_CSU_BASE+0x25C*4) +#define APC1_CSU_DMAZSTEPH11 (APC1_CSU_BASE+0x25D*4) +#define APC1_CSU_DMAYNUMXNUM11 (APC1_CSU_BASE+0x25E*4) +#define APC1_CSU_DMASIZEGRANALLNUM11 (APC1_CSU_BASE+0x25F*4) +#define APC1_CSU_DMAADDRL12 (APC1_CSU_BASE+0x260*4) +#define APC1_CSU_DMAADDRH12 (APC1_CSU_BASE+0x261*4) +#define APC1_CSU_DMAYSTEPL12 (APC1_CSU_BASE+0x262*4) +#define APC1_CSU_DMAYSTEPH12 (APC1_CSU_BASE+0x263*4) +#define APC1_CSU_DMAZSTEPL12 (APC1_CSU_BASE+0x264*4) +#define APC1_CSU_DMAZSTEPH12 (APC1_CSU_BASE+0x265*4) +#define APC1_CSU_DMAYNUMXNUM12 (APC1_CSU_BASE+0x266*4) +#define APC1_CSU_DMASIZEGRANALLNUM12 (APC1_CSU_BASE+0x267*4) +#define APC1_CSU_DMAADDRL13 (APC1_CSU_BASE+0x268*4) +#define APC1_CSU_DMAADDRH13 (APC1_CSU_BASE+0x269*4) +#define APC1_CSU_DMAYSTEPL13 (APC1_CSU_BASE+0x26A*4) +#define APC1_CSU_DMAYSTEPH13 (APC1_CSU_BASE+0x26B*4) +#define APC1_CSU_DMAZSTEPL13 (APC1_CSU_BASE+0x26C*4) +#define APC1_CSU_DMAZSTEPH13 (APC1_CSU_BASE+0x26D*4) +#define APC1_CSU_DMAYNUMXNUM13 (APC1_CSU_BASE+0x26E*4) +#define APC1_CSU_DMASIZEGRANALLNUM13 (APC1_CSU_BASE+0x26F*4) +#define APC1_CSU_DMAADDRL14 (APC1_CSU_BASE+0x270*4) +#define APC1_CSU_DMAADDRH14 (APC1_CSU_BASE+0x271*4) +#define APC1_CSU_DMAYSTEPL14 (APC1_CSU_BASE+0x272*4) +#define APC1_CSU_DMAYSTEPH14 (APC1_CSU_BASE+0x273*4) +#define APC1_CSU_DMAZSTEPL14 (APC1_CSU_BASE+0x274*4) +#define APC1_CSU_DMAZSTEPH14 (APC1_CSU_BASE+0x275*4) +#define APC1_CSU_DMAYNUMXNUM14 (APC1_CSU_BASE+0x276*4) +#define APC1_CSU_DMASIZEGRANALLNUM14 (APC1_CSU_BASE+0x277*4) +#define APC1_CSU_DMAADDRL15 (APC1_CSU_BASE+0x278*4) +#define APC1_CSU_DMAADDRH15 (APC1_CSU_BASE+0x279*4) +#define APC1_CSU_DMAYSTEPL15 (APC1_CSU_BASE+0x27A*4) +#define APC1_CSU_DMAYSTEPH15 (APC1_CSU_BASE+0x27B*4) +#define APC1_CSU_DMAZSTEPL15 (APC1_CSU_BASE+0x27C*4) +#define APC1_CSU_DMAZSTEPH15 (APC1_CSU_BASE+0x27D*4) +#define APC1_CSU_DMAYNUMXNUM15 (APC1_CSU_BASE+0x27E*4) +#define APC1_CSU_DMASIZEGRANALLNUM15 (APC1_CSU_BASE+0x27F*4) +#define APC1_CSU_QOUCMDNUM_QOUCMDPOS (APC1_CSU_BASE+0x300*4) +#define APC1_CSU_QOUCMDADDR (APC1_CSU_BASE+0x301*4) +#define APC1_CSU_QOUCMDDATA (APC1_CSU_BASE+0x302*4) +#define APC1_CSU_QOUSTATUSPOPDATA (APC1_CSU_BASE+0x303*4) +#define APC1_CSU_QOUCMPDATA0 (APC1_CSU_BASE+0x304*4) +#define APC1_CSU_QOUCMPDATA1 (APC1_CSU_BASE+0x305*4) +#define APC1_CSU_QOUCMPDATA2 (APC1_CSU_BASE+0x306*4) +#define APC1_CSU_QOUCMPDATA3 (APC1_CSU_BASE+0x307*4) +#define APC1_CSU_SPUID (APC1_CSU_BASE+0x30B*4) +#define APC1_CSU_PRICMDDATA_L32BIT0 (APC1_CSU_BASE+0x310*4) +#define APC1_CSU_PRICMDDATA_H14BIT0 (APC1_CSU_BASE+0x311*4) +#define APC1_CSU_PRICMDDATA_L32BIT1 (APC1_CSU_BASE+0x312*4) +#define APC1_CSU_PRICMDDATA_H14BIT1 (APC1_CSU_BASE+0x313*4) +#define APC1_CSU_PRICMDDATA_L32BIT2 (APC1_CSU_BASE+0x314*4) +#define APC1_CSU_PRICMDDATA_H14BIT2 (APC1_CSU_BASE+0x315*4) +#define APC1_CSU_PRICMDDATA_L32BIT3 (APC1_CSU_BASE+0x316*4) +#define APC1_CSU_PRICMDDATA_H14BIT3 (APC1_CSU_BASE+0x317*4) +#define APC1_CSU_SORTDATA_NUM (APC1_CSU_BASE+0x380*4) +#define APC1_CSU_SORTDATA_DATA0 (APC1_CSU_BASE+0x3C0*4) +#define APC1_CSU_SORTDATA_DATA1 (APC1_CSU_BASE+0x3C1*4) +#define APC1_CSU_SORTDATA_DATA2 (APC1_CSU_BASE+0x3C2*4) +#define APC1_CSU_SORTDATA_DATA3 (APC1_CSU_BASE+0x3C3*4) +#define APC1_CSU_SORTDATA_DATA4 (APC1_CSU_BASE+0x3C4*4) +#define APC1_CSU_SORTDATA_DATA5 (APC1_CSU_BASE+0x3C5*4) +#define APC1_CSU_SORTDATA_DATA6 (APC1_CSU_BASE+0x3C6*4) +#define APC1_CSU_SORTDATA_DATA7 (APC1_CSU_BASE+0x3C7*4) +#define APC1_CSU_SORTDATA_DATA8 (APC1_CSU_BASE+0x3C8*4) +#define APC1_CSU_SORTDATA_DATA9 (APC1_CSU_BASE+0x3C9*4) +#define APC1_CSU_SORTDATA_DATA10 (APC1_CSU_BASE+0x3CA*4) +#define APC1_CSU_SORTDATA_DATA11 (APC1_CSU_BASE+0x3CB*4) +#define APC1_CSU_SORTDATA_DATA12 (APC1_CSU_BASE+0x3CC*4) +#define APC1_CSU_SORTDATA_DATA13 (APC1_CSU_BASE+0x3CD*4) +#define APC1_CSU_SORTDATA_DATA14 (APC1_CSU_BASE+0x3CE*4) +#define APC1_CSU_SORTDATA_DATA15 (APC1_CSU_BASE+0x3CF*4) +#define APC1_CSU_SORTDATA_DATA16 (APC1_CSU_BASE+0x3D0*4) +#define APC1_CSU_SORTDATA_DATA17 (APC1_CSU_BASE+0x3D1*4) +#define APC1_CSU_SORTDATA_DATA18 (APC1_CSU_BASE+0x3D2*4) +#define APC1_CSU_SORTDATA_DATA19 (APC1_CSU_BASE+0x3D3*4) +#define APC1_CSU_SORTDATA_DATA20 (APC1_CSU_BASE+0x3D4*4) +#define APC1_CSU_SORTDATA_DATA21 (APC1_CSU_BASE+0x3D5*4) +#define APC1_CSU_SORTDATA_DATA22 (APC1_CSU_BASE+0x3D6*4) +#define APC1_CSU_SORTDATA_DATA23 (APC1_CSU_BASE+0x3D7*4) +#define APC1_CSU_SORTDATA_DATA24 (APC1_CSU_BASE+0x3D8*4) +#define APC1_CSU_SORTDATA_DATA25 (APC1_CSU_BASE+0x3D9*4) +#define APC1_CSU_SORTDATA_DATA26 (APC1_CSU_BASE+0x3DA*4) +#define APC1_CSU_SORTDATA_DATA27 (APC1_CSU_BASE+0x3DB*4) +#define APC1_CSU_SORTDATA_DATA28 (APC1_CSU_BASE+0x3DC*4) +#define APC1_CSU_SORTDATA_DATA29 (APC1_CSU_BASE+0x3DD*4) +#define APC1_CSU_SORTDATA_DATA30 (APC1_CSU_BASE+0x3DE*4) +#define APC1_CSU_SORTDATA_DATA31 (APC1_CSU_BASE+0x3DF*4) +#define APC1_CSU_SORTDATA_ID0 (APC1_CSU_BASE+0x3E0*4) +#define APC1_CSU_SORTDATA_ID1 (APC1_CSU_BASE+0x3E1*4) +#define APC1_CSU_SORTDATA_ID2 (APC1_CSU_BASE+0x3E2*4) +#define APC1_CSU_SORTDATA_ID3 (APC1_CSU_BASE+0x3E3*4) +#define APC1_CSU_SORTDATA_ID4 (APC1_CSU_BASE+0x3E4*4) +#define APC1_CSU_SORTDATA_ID5 (APC1_CSU_BASE+0x3E5*4) +#define APC1_CSU_SORTDATA_ID6 (APC1_CSU_BASE+0x3E6*4) +#define APC1_CSU_SORTDATA_ID7 (APC1_CSU_BASE+0x3E7*4) +#define APC1_CSU_SORTDATA_ID8 (APC1_CSU_BASE+0x3E8*4) +#define APC1_CSU_SORTDATA_ID9 (APC1_CSU_BASE+0x3E9*4) +#define APC1_CSU_SORTDATA_ID10 (APC1_CSU_BASE+0x3EA*4) +#define APC1_CSU_SORTDATA_ID11 (APC1_CSU_BASE+0x3EB*4) +#define APC1_CSU_SORTDATA_ID12 (APC1_CSU_BASE+0x3EC*4) +#define APC1_CSU_SORTDATA_ID13 (APC1_CSU_BASE+0x3ED*4) +#define APC1_CSU_SORTDATA_ID14 (APC1_CSU_BASE+0x3EE*4) +#define APC1_CSU_SORTDATA_ID15 (APC1_CSU_BASE+0x3EF*4) +#define APC1_CSU_SORTDATA_ID16 (APC1_CSU_BASE+0x3F0*4) +#define APC1_CSU_SORTDATA_ID17 (APC1_CSU_BASE+0x3F1*4) +#define APC1_CSU_SORTDATA_ID18 (APC1_CSU_BASE+0x3F2*4) +#define APC1_CSU_SORTDATA_ID19 (APC1_CSU_BASE+0x3F3*4) +#define APC1_CSU_SORTDATA_ID20 (APC1_CSU_BASE+0x3F4*4) +#define APC1_CSU_SORTDATA_ID21 (APC1_CSU_BASE+0x3F5*4) +#define APC1_CSU_SORTDATA_ID22 (APC1_CSU_BASE+0x3F6*4) +#define APC1_CSU_SORTDATA_ID23 (APC1_CSU_BASE+0x3F7*4) +#define APC1_CSU_SORTDATA_ID24 (APC1_CSU_BASE+0x3F8*4) +#define APC1_CSU_SORTDATA_ID25 (APC1_CSU_BASE+0x3F9*4) +#define APC1_CSU_SORTDATA_ID26 (APC1_CSU_BASE+0x3FA*4) +#define APC1_CSU_SORTDATA_ID27 (APC1_CSU_BASE+0x3FB*4) +#define APC1_CSU_SORTDATA_ID28 (APC1_CSU_BASE+0x3FC*4) +#define APC1_CSU_SORTDATA_ID29 (APC1_CSU_BASE+0x3FD*4) +#define APC1_CSU_SORTDATA_ID30 (APC1_CSU_BASE+0x3FE*4) +#define APC1_CSU_SORTDATA_ID31 (APC1_CSU_BASE+0x3FF*4) + + +#define APC2_CSU_STARTSPU0 (APC2_CSU_BASE+0x000*4) +#define APC2_CSU_ALLPENDEVENTMASK (APC2_CSU_BASE+0x000*4) +#define APC2_CSU_STARTSPU1 (APC2_CSU_BASE+0x001*4) +#define APC2_CSU_EVENTMASK (APC2_CSU_BASE+0x002*4) +#define APC2_CSU_INTMASK (APC2_CSU_BASE+0x004*4) +#define APC2_CSU_ELEVELMASK (APC2_CSU_BASE+0x005*4) +#define APC2_CSU_TAGMASK0 (APC2_CSU_BASE+0x006*4) +#define APC2_CSU_TAGMASK1 (APC2_CSU_BASE+0x007*4) +#define APC2_CSU_TAGMASK2 (APC2_CSU_BASE+0x008*4) +#define APC2_CSU_TAGMASK3 (APC2_CSU_BASE+0x009*4) +#define APC2_CSU_ARMCMDRECV (APC2_CSU_BASE+0x00A*4) +#define APC2_CSU_FETCHMODE_CACHEMODE (APC2_CSU_BASE+0x00B*4) +#define APC2_CSU_ALLPENDEVENT0 (APC2_CSU_BASE+0x00C*4) +#define APC2_CSU_ALLPENDEVENT1 (APC2_CSU_BASE+0x00D*4) +#define APC2_CSU_EM_BS_SMSEL_PREDATANUM (APC2_CSU_BASE+0x010*4) +#define APC2_CSU_CACHEINFO_EM_BS_SPURWCACHE_SMSEL_PDNUM (APC2_CSU_BASE+0x010*4) +#define APC2_CSU_ALMOSTFULLSENDTHRED (APC2_CSU_BASE+0x011*4) +#define APC2_CSU_FINDDMATAG (APC2_CSU_BASE+0x014*4) +#define APC2_CSU_CMDFIFO0_CMD (APC2_CSU_BASE+0x018*4) +#define APC2_CSU_CMDFIFO1_CMD (APC2_CSU_BASE+0x019*4) +#define APC2_CSU_CMDFIFO2_CMD (APC2_CSU_BASE+0x01A*4) +#define APC2_CSU_CMDFIFO3_CMD (APC2_CSU_BASE+0x01B*4) +#define APC2_CSU_CMDFIFO0_NUM (APC2_CSU_BASE+0x01C*4) +#define APC2_CSU_CMDFIFO1_NUM (APC2_CSU_BASE+0x01D*4) +#define APC2_CSU_CMDFIFO2_NUM (APC2_CSU_BASE+0x01E*4) +#define APC2_CSU_CMDFIFO3_NUM (APC2_CSU_BASE+0x01F*4) +#define APC2_CSU_PRICMDVALID0 (APC2_CSU_BASE+0x020*4) +#define APC2_CSU_PRICMDVALID1 (APC2_CSU_BASE+0x021*4) +#define APC2_CSU_PRICMDVALID2 (APC2_CSU_BASE+0x022*4) +#define APC2_CSU_PRICMDVALID3 (APC2_CSU_BASE+0x023*4) +#define APC2_CSU_CMDECODATAL32BIT0 (APC2_CSU_BASE+0x024*4) +#define APC2_CSU_CMDECODATAL32BIT1 (APC2_CSU_BASE+0x025*4) +#define APC2_CSU_CMDECODATAL32BIT2 (APC2_CSU_BASE+0x026*4) +#define APC2_CSU_CMDECODATAL32BIT3 (APC2_CSU_BASE+0x027*4) +#define APC2_CSU_CMDHIGHDATA (APC2_CSU_BASE+0x028*4) +#define APC2_CSU_CMDFIFO0 (APC2_CSU_BASE+0x02C*4) +#define APC2_CSU_CMDFIFO1 (APC2_CSU_BASE+0x02D*4) +#define APC2_CSU_CMDFIFO2 (APC2_CSU_BASE+0x02E*4) +#define APC2_CSU_CMDFIFO3 (APC2_CSU_BASE+0x02F*4) +#define APC2_CSU_READYLISTNUM (APC2_CSU_BASE+0x030*4) +#define APC2_CSU_CMDFIFO0_TAGNUM (APC2_CSU_BASE+0x034*4) +#define APC2_CSU_CMDFIFO1_TAGNUM (APC2_CSU_BASE+0x035*4) +#define APC2_CSU_CMDFIFO2_TAGNUM (APC2_CSU_BASE+0x036*4) +#define APC2_CSU_CMDFIFO3_TAGNUM (APC2_CSU_BASE+0x037*4) +#define APC2_CSU_DMASTATUS (APC2_CSU_BASE+0x038*4) +#define APC2_CSU_CMDSTALL_LISTSTALL (APC2_CSU_BASE+0x039*4) +#define APC2_CSU_QOUSTATUS (APC2_CSU_BASE+0x03A*4) +#define APC2_CSU_EVENTINTCLEAR (APC2_CSU_BASE+0x03C*4) +#define APC2_CSU_MAILBOX_PRIDATAREG0 (APC2_CSU_BASE+0x100*4) +#define APC2_CSU_MAILBOX_PRIDATAREG1 (APC2_CSU_BASE+0x101*4) +#define APC2_CSU_MAILBOX_PRIDATAREG2 (APC2_CSU_BASE+0x102*4) +#define APC2_CSU_MAILBOX_PRIDATAREG3 (APC2_CSU_BASE+0x103*4) +#define APC2_CSU_MAILBOX_PRIDATAREG4 (APC2_CSU_BASE+0x104*4) +#define APC2_CSU_MAILBOX_PRIDATAREG5 (APC2_CSU_BASE+0x105*4) +#define APC2_CSU_MAILBOX_PRIDATAREG6 (APC2_CSU_BASE+0x106*4) +#define APC2_CSU_MAILBOX_PRIDATAREG7 (APC2_CSU_BASE+0x107*4) +#define APC2_CSU_MAILBOX_PRIDATAREG8 (APC2_CSU_BASE+0x108*4) +#define APC2_CSU_MAILBOX_PRIDATAREG9 (APC2_CSU_BASE+0x109*4) +#define APC2_CSU_MAILBOX_PRIDATAREG10 (APC2_CSU_BASE+0x10A*4) +#define APC2_CSU_MAILBOX_PRIDATAREG11 (APC2_CSU_BASE+0x10B*4) +#define APC2_CSU_MAILBOX_PRIDATAREG12 (APC2_CSU_BASE+0x10C*4) +#define APC2_CSU_MAILBOX_PRIDATAREG13 (APC2_CSU_BASE+0x10D*4) +#define APC2_CSU_MAILBOX_PRIDATAREG14 (APC2_CSU_BASE+0x10E*4) +#define APC2_CSU_MAILBOX_PRIDATAREG15 (APC2_CSU_BASE+0x10F*4) +#define APC2_CSU_MAILBOX_BASENUM (APC2_CSU_BASE+0x120*4) +#define APC2_CSU_MAILBOX_BASECNT (APC2_CSU_BASE+0x121*4) +#define APC2_CSU_MAILBOX_VALIDREG (APC2_CSU_BASE+0x122*4) +#define APC2_CSU_MAILBOX_INTMASK0 (APC2_CSU_BASE+0x124*4) +#define APC2_CSU_MAILBOX_INTMASK1 (APC2_CSU_BASE+0x125*4) +#define APC2_CSU_MAILBOX_INTMASK2 (APC2_CSU_BASE+0x126*4) +#define APC2_CSU_MAILBOX_INTMASK3 (APC2_CSU_BASE+0x127*4) +#define APC2_CSU_MAILBOX_EVENTMASK0 (APC2_CSU_BASE+0x130*4) +#define APC2_CSU_MAILBOX_EVENTMASK1 (APC2_CSU_BASE+0x131*4) +#define APC2_CSU_MAILBOX_CNTREG0 (APC2_CSU_BASE+0x180*4) +#define APC2_CSU_MAILBOX_CNTREG1 (APC2_CSU_BASE+0x181*4) +#define APC2_CSU_MAILBOX_CNTREG2 (APC2_CSU_BASE+0x182*4) +#define APC2_CSU_MAILBOX_CNTREG3 (APC2_CSU_BASE+0x183*4) +#define APC2_CSU_MAILBOX_CNTREG4 (APC2_CSU_BASE+0x184*4) +#define APC2_CSU_MAILBOX_CNTREG5 (APC2_CSU_BASE+0x185*4) +#define APC2_CSU_MAILBOX_CNTREG6 (APC2_CSU_BASE+0x186*4) +#define APC2_CSU_MAILBOX_CNTREG7 (APC2_CSU_BASE+0x187*4) +#define APC2_CSU_MAILBOX_CNTREG8 (APC2_CSU_BASE+0x188*4) +#define APC2_CSU_MAILBOX_CNTREG9 (APC2_CSU_BASE+0x189*4) +#define APC2_CSU_MAILBOX_CNTREG10 (APC2_CSU_BASE+0x18A*4) +#define APC2_CSU_MAILBOX_CNTREG11 (APC2_CSU_BASE+0x18B*4) +#define APC2_CSU_MAILBOX_CNTREG12 (APC2_CSU_BASE+0x18C*4) +#define APC2_CSU_MAILBOX_CNTREG13 (APC2_CSU_BASE+0x18D*4) +#define APC2_CSU_MAILBOX_CNTREG14 (APC2_CSU_BASE+0x18E*4) +#define APC2_CSU_MAILBOX_CNTREG15 (APC2_CSU_BASE+0x18F*4) +#define APC2_CSU_DMAADDRL0 (APC2_CSU_BASE+0x200*4) +#define APC2_CSU_DMAADDRH0 (APC2_CSU_BASE+0x201*4) +#define APC2_CSU_DMAYSTEPL0 (APC2_CSU_BASE+0x202*4) +#define APC2_CSU_DMAYSTEPH0 (APC2_CSU_BASE+0x203*4) +#define APC2_CSU_DMAZSTEPL0 (APC2_CSU_BASE+0x204*4) +#define APC2_CSU_DMAZSTEPH0 (APC2_CSU_BASE+0x205*4) +#define APC2_CSU_DMAYNUMXNUM0 (APC2_CSU_BASE+0x206*4) +#define APC2_CSU_DMASIZEGRANALLNUM0 (APC2_CSU_BASE+0x207*4) +#define APC2_CSU_DMAADDRL1 (APC2_CSU_BASE+0x208*4) +#define APC2_CSU_DMAADDRH1 (APC2_CSU_BASE+0x209*4) +#define APC2_CSU_DMAYSTEPL1 (APC2_CSU_BASE+0x20A*4) +#define APC2_CSU_DMAYSTEPH1 (APC2_CSU_BASE+0x20B*4) +#define APC2_CSU_DMAZSTEPL1 (APC2_CSU_BASE+0x20C*4) +#define APC2_CSU_DMAZSTEPH1 (APC2_CSU_BASE+0x20D*4) +#define APC2_CSU_DMAYNUMXNUM1 (APC2_CSU_BASE+0x20E*4) +#define APC2_CSU_DMASIZEGRANALLNUM1 (APC2_CSU_BASE+0x20F*4) +#define APC2_CSU_DMAADDRL2 (APC2_CSU_BASE+0x210*4) +#define APC2_CSU_DMAADDRH2 (APC2_CSU_BASE+0x211*4) +#define APC2_CSU_DMAYSTEPL2 (APC2_CSU_BASE+0x212*4) +#define APC2_CSU_DMAYSTEPH2 (APC2_CSU_BASE+0x213*4) +#define APC2_CSU_DMAZSTEPL2 (APC2_CSU_BASE+0x214*4) +#define APC2_CSU_DMAZSTEPH2 (APC2_CSU_BASE+0x215*4) +#define APC2_CSU_DMAYNUMXNUM2 (APC2_CSU_BASE+0x216*4) +#define APC2_CSU_DMASIZEGRANALLNUM2 (APC2_CSU_BASE+0x217*4) +#define APC2_CSU_DMAADDRL3 (APC2_CSU_BASE+0x218*4) +#define APC2_CSU_DMAADDRH3 (APC2_CSU_BASE+0x219*4) +#define APC2_CSU_DMAYSTEPL3 (APC2_CSU_BASE+0x21A*4) +#define APC2_CSU_DMAYSTEPH3 (APC2_CSU_BASE+0x21B*4) +#define APC2_CSU_DMAZSTEPL3 (APC2_CSU_BASE+0x21C*4) +#define APC2_CSU_DMAZSTEPH3 (APC2_CSU_BASE+0x21D*4) +#define APC2_CSU_DMAYNUMXNUM3 (APC2_CSU_BASE+0x21E*4) +#define APC2_CSU_DMASIZEGRANALLNUM3 (APC2_CSU_BASE+0x21F*4) +#define APC2_CSU_DMAADDRL4 (APC2_CSU_BASE+0x220*4) +#define APC2_CSU_DMAADDRH4 (APC2_CSU_BASE+0x221*4) +#define APC2_CSU_DMAYSTEPL4 (APC2_CSU_BASE+0x222*4) +#define APC2_CSU_DMAYSTEPH4 (APC2_CSU_BASE+0x223*4) +#define APC2_CSU_DMAZSTEPL4 (APC2_CSU_BASE+0x224*4) +#define APC2_CSU_DMAZSTEPH4 (APC2_CSU_BASE+0x225*4) +#define APC2_CSU_DMAYNUMXNUM4 (APC2_CSU_BASE+0x226*4) +#define APC2_CSU_DMASIZEGRANALLNUM4 (APC2_CSU_BASE+0x227*4) +#define APC2_CSU_DMAADDRL5 (APC2_CSU_BASE+0x228*4) +#define APC2_CSU_DMAADDRH5 (APC2_CSU_BASE+0x229*4) +#define APC2_CSU_DMAYSTEPL5 (APC2_CSU_BASE+0x22A*4) +#define APC2_CSU_DMAYSTEPH5 (APC2_CSU_BASE+0x22B*4) +#define APC2_CSU_DMAZSTEPL5 (APC2_CSU_BASE+0x22C*4) +#define APC2_CSU_DMAZSTEPH5 (APC2_CSU_BASE+0x22D*4) +#define APC2_CSU_DMAYNUMXNUM5 (APC2_CSU_BASE+0x22E*4) +#define APC2_CSU_DMASIZEGRANALLNUM5 (APC2_CSU_BASE+0x22F*4) +#define APC2_CSU_DMAADDRL6 (APC2_CSU_BASE+0x230*4) +#define APC2_CSU_DMAADDRH6 (APC2_CSU_BASE+0x231*4) +#define APC2_CSU_DMAYSTEPL6 (APC2_CSU_BASE+0x232*4) +#define APC2_CSU_DMAYSTEPH6 (APC2_CSU_BASE+0x233*4) +#define APC2_CSU_DMAZSTEPL6 (APC2_CSU_BASE+0x234*4) +#define APC2_CSU_DMAZSTEPH6 (APC2_CSU_BASE+0x235*4) +#define APC2_CSU_DMAYNUMXNUM6 (APC2_CSU_BASE+0x236*4) +#define APC2_CSU_DMASIZEGRANALLNUM6 (APC2_CSU_BASE+0x237*4) +#define APC2_CSU_DMAADDRL7 (APC2_CSU_BASE+0x238*4) +#define APC2_CSU_DMAADDRH7 (APC2_CSU_BASE+0x239*4) +#define APC2_CSU_DMAYSTEPL7 (APC2_CSU_BASE+0x23A*4) +#define APC2_CSU_DMAYSTEPH7 (APC2_CSU_BASE+0x23B*4) +#define APC2_CSU_DMAZSTEPL7 (APC2_CSU_BASE+0x23C*4) +#define APC2_CSU_DMAZSTEPH7 (APC2_CSU_BASE+0x23D*4) +#define APC2_CSU_DMAYNUMXNUM7 (APC2_CSU_BASE+0x23E*4) +#define APC2_CSU_DMASIZEGRANALLNUM7 (APC2_CSU_BASE+0x23F*4) +#define APC2_CSU_DMAADDRL8 (APC2_CSU_BASE+0x240*4) +#define APC2_CSU_DMAADDRH8 (APC2_CSU_BASE+0x241*4) +#define APC2_CSU_DMAYSTEPL8 (APC2_CSU_BASE+0x242*4) +#define APC2_CSU_DMAYSTEPH8 (APC2_CSU_BASE+0x243*4) +#define APC2_CSU_DMAZSTEPL8 (APC2_CSU_BASE+0x244*4) +#define APC2_CSU_DMAZSTEPH8 (APC2_CSU_BASE+0x245*4) +#define APC2_CSU_DMAYNUMXNUM8 (APC2_CSU_BASE+0x246*4) +#define APC2_CSU_DMASIZEGRANALLNUM8 (APC2_CSU_BASE+0x247*4) +#define APC2_CSU_DMAADDRL9 (APC2_CSU_BASE+0x248*4) +#define APC2_CSU_DMAADDRH9 (APC2_CSU_BASE+0x249*4) +#define APC2_CSU_DMAYSTEPL9 (APC2_CSU_BASE+0x24A*4) +#define APC2_CSU_DMAYSTEPH9 (APC2_CSU_BASE+0x24B*4) +#define APC2_CSU_DMAZSTEPL9 (APC2_CSU_BASE+0x24C*4) +#define APC2_CSU_DMAZSTEPH9 (APC2_CSU_BASE+0x24D*4) +#define APC2_CSU_DMAYNUMXNUM9 (APC2_CSU_BASE+0x24E*4) +#define APC2_CSU_DMASIZEGRANALLNUM9 (APC2_CSU_BASE+0x24F*4) +#define APC2_CSU_DMAADDRL10 (APC2_CSU_BASE+0x250*4) +#define APC2_CSU_DMAADDRH10 (APC2_CSU_BASE+0x251*4) +#define APC2_CSU_DMAYSTEPL10 (APC2_CSU_BASE+0x252*4) +#define APC2_CSU_DMAYSTEPH10 (APC2_CSU_BASE+0x253*4) +#define APC2_CSU_DMAZSTEPL10 (APC2_CSU_BASE+0x254*4) +#define APC2_CSU_DMAZSTEPH10 (APC2_CSU_BASE+0x255*4) +#define APC2_CSU_DMAYNUMXNUM10 (APC2_CSU_BASE+0x256*4) +#define APC2_CSU_DMASIZEGRANALLNUM10 (APC2_CSU_BASE+0x257*4) +#define APC2_CSU_DMAADDRL11 (APC2_CSU_BASE+0x258*4) +#define APC2_CSU_DMAADDRH11 (APC2_CSU_BASE+0x259*4) +#define APC2_CSU_DMAYSTEPL11 (APC2_CSU_BASE+0x25A*4) +#define APC2_CSU_DMAYSTEPH11 (APC2_CSU_BASE+0x25B*4) +#define APC2_CSU_DMAZSTEPL11 (APC2_CSU_BASE+0x25C*4) +#define APC2_CSU_DMAZSTEPH11 (APC2_CSU_BASE+0x25D*4) +#define APC2_CSU_DMAYNUMXNUM11 (APC2_CSU_BASE+0x25E*4) +#define APC2_CSU_DMASIZEGRANALLNUM11 (APC2_CSU_BASE+0x25F*4) +#define APC2_CSU_DMAADDRL12 (APC2_CSU_BASE+0x260*4) +#define APC2_CSU_DMAADDRH12 (APC2_CSU_BASE+0x261*4) +#define APC2_CSU_DMAYSTEPL12 (APC2_CSU_BASE+0x262*4) +#define APC2_CSU_DMAYSTEPH12 (APC2_CSU_BASE+0x263*4) +#define APC2_CSU_DMAZSTEPL12 (APC2_CSU_BASE+0x264*4) +#define APC2_CSU_DMAZSTEPH12 (APC2_CSU_BASE+0x265*4) +#define APC2_CSU_DMAYNUMXNUM12 (APC2_CSU_BASE+0x266*4) +#define APC2_CSU_DMASIZEGRANALLNUM12 (APC2_CSU_BASE+0x267*4) +#define APC2_CSU_DMAADDRL13 (APC2_CSU_BASE+0x268*4) +#define APC2_CSU_DMAADDRH13 (APC2_CSU_BASE+0x269*4) +#define APC2_CSU_DMAYSTEPL13 (APC2_CSU_BASE+0x26A*4) +#define APC2_CSU_DMAYSTEPH13 (APC2_CSU_BASE+0x26B*4) +#define APC2_CSU_DMAZSTEPL13 (APC2_CSU_BASE+0x26C*4) +#define APC2_CSU_DMAZSTEPH13 (APC2_CSU_BASE+0x26D*4) +#define APC2_CSU_DMAYNUMXNUM13 (APC2_CSU_BASE+0x26E*4) +#define APC2_CSU_DMASIZEGRANALLNUM13 (APC2_CSU_BASE+0x26F*4) +#define APC2_CSU_DMAADDRL14 (APC2_CSU_BASE+0x270*4) +#define APC2_CSU_DMAADDRH14 (APC2_CSU_BASE+0x271*4) +#define APC2_CSU_DMAYSTEPL14 (APC2_CSU_BASE+0x272*4) +#define APC2_CSU_DMAYSTEPH14 (APC2_CSU_BASE+0x273*4) +#define APC2_CSU_DMAZSTEPL14 (APC2_CSU_BASE+0x274*4) +#define APC2_CSU_DMAZSTEPH14 (APC2_CSU_BASE+0x275*4) +#define APC2_CSU_DMAYNUMXNUM14 (APC2_CSU_BASE+0x276*4) +#define APC2_CSU_DMASIZEGRANALLNUM14 (APC2_CSU_BASE+0x277*4) +#define APC2_CSU_DMAADDRL15 (APC2_CSU_BASE+0x278*4) +#define APC2_CSU_DMAADDRH15 (APC2_CSU_BASE+0x279*4) +#define APC2_CSU_DMAYSTEPL15 (APC2_CSU_BASE+0x27A*4) +#define APC2_CSU_DMAYSTEPH15 (APC2_CSU_BASE+0x27B*4) +#define APC2_CSU_DMAZSTEPL15 (APC2_CSU_BASE+0x27C*4) +#define APC2_CSU_DMAZSTEPH15 (APC2_CSU_BASE+0x27D*4) +#define APC2_CSU_DMAYNUMXNUM15 (APC2_CSU_BASE+0x27E*4) +#define APC2_CSU_DMASIZEGRANALLNUM15 (APC2_CSU_BASE+0x27F*4) +#define APC2_CSU_QOUCMDNUM_QOUCMDPOS (APC2_CSU_BASE+0x300*4) +#define APC2_CSU_QOUCMDADDR (APC2_CSU_BASE+0x301*4) +#define APC2_CSU_QOUCMDDATA (APC2_CSU_BASE+0x302*4) +#define APC2_CSU_QOUSTATUSPOPDATA (APC2_CSU_BASE+0x303*4) +#define APC2_CSU_QOUCMPDATA0 (APC2_CSU_BASE+0x304*4) +#define APC2_CSU_QOUCMPDATA1 (APC2_CSU_BASE+0x305*4) +#define APC2_CSU_QOUCMPDATA2 (APC2_CSU_BASE+0x306*4) +#define APC2_CSU_QOUCMPDATA3 (APC2_CSU_BASE+0x307*4) +#define APC2_CSU_SPUID (APC2_CSU_BASE+0x30B*4) +#define APC2_CSU_PRICMDDATA_L32BIT0 (APC2_CSU_BASE+0x310*4) +#define APC2_CSU_PRICMDDATA_H14BIT0 (APC2_CSU_BASE+0x311*4) +#define APC2_CSU_PRICMDDATA_L32BIT1 (APC2_CSU_BASE+0x312*4) +#define APC2_CSU_PRICMDDATA_H14BIT1 (APC2_CSU_BASE+0x313*4) +#define APC2_CSU_PRICMDDATA_L32BIT2 (APC2_CSU_BASE+0x314*4) +#define APC2_CSU_PRICMDDATA_H14BIT2 (APC2_CSU_BASE+0x315*4) +#define APC2_CSU_PRICMDDATA_L32BIT3 (APC2_CSU_BASE+0x316*4) +#define APC2_CSU_PRICMDDATA_H14BIT3 (APC2_CSU_BASE+0x317*4) +#define APC2_CSU_SORTDATA_NUM (APC2_CSU_BASE+0x380*4) +#define APC2_CSU_SORTDATA_DATA0 (APC2_CSU_BASE+0x3C0*4) +#define APC2_CSU_SORTDATA_DATA1 (APC2_CSU_BASE+0x3C1*4) +#define APC2_CSU_SORTDATA_DATA2 (APC2_CSU_BASE+0x3C2*4) +#define APC2_CSU_SORTDATA_DATA3 (APC2_CSU_BASE+0x3C3*4) +#define APC2_CSU_SORTDATA_DATA4 (APC2_CSU_BASE+0x3C4*4) +#define APC2_CSU_SORTDATA_DATA5 (APC2_CSU_BASE+0x3C5*4) +#define APC2_CSU_SORTDATA_DATA6 (APC2_CSU_BASE+0x3C6*4) +#define APC2_CSU_SORTDATA_DATA7 (APC2_CSU_BASE+0x3C7*4) +#define APC2_CSU_SORTDATA_DATA8 (APC2_CSU_BASE+0x3C8*4) +#define APC2_CSU_SORTDATA_DATA9 (APC2_CSU_BASE+0x3C9*4) +#define APC2_CSU_SORTDATA_DATA10 (APC2_CSU_BASE+0x3CA*4) +#define APC2_CSU_SORTDATA_DATA11 (APC2_CSU_BASE+0x3CB*4) +#define APC2_CSU_SORTDATA_DATA12 (APC2_CSU_BASE+0x3CC*4) +#define APC2_CSU_SORTDATA_DATA13 (APC2_CSU_BASE+0x3CD*4) +#define APC2_CSU_SORTDATA_DATA14 (APC2_CSU_BASE+0x3CE*4) +#define APC2_CSU_SORTDATA_DATA15 (APC2_CSU_BASE+0x3CF*4) +#define APC2_CSU_SORTDATA_DATA16 (APC2_CSU_BASE+0x3D0*4) +#define APC2_CSU_SORTDATA_DATA17 (APC2_CSU_BASE+0x3D1*4) +#define APC2_CSU_SORTDATA_DATA18 (APC2_CSU_BASE+0x3D2*4) +#define APC2_CSU_SORTDATA_DATA19 (APC2_CSU_BASE+0x3D3*4) +#define APC2_CSU_SORTDATA_DATA20 (APC2_CSU_BASE+0x3D4*4) +#define APC2_CSU_SORTDATA_DATA21 (APC2_CSU_BASE+0x3D5*4) +#define APC2_CSU_SORTDATA_DATA22 (APC2_CSU_BASE+0x3D6*4) +#define APC2_CSU_SORTDATA_DATA23 (APC2_CSU_BASE+0x3D7*4) +#define APC2_CSU_SORTDATA_DATA24 (APC2_CSU_BASE+0x3D8*4) +#define APC2_CSU_SORTDATA_DATA25 (APC2_CSU_BASE+0x3D9*4) +#define APC2_CSU_SORTDATA_DATA26 (APC2_CSU_BASE+0x3DA*4) +#define APC2_CSU_SORTDATA_DATA27 (APC2_CSU_BASE+0x3DB*4) +#define APC2_CSU_SORTDATA_DATA28 (APC2_CSU_BASE+0x3DC*4) +#define APC2_CSU_SORTDATA_DATA29 (APC2_CSU_BASE+0x3DD*4) +#define APC2_CSU_SORTDATA_DATA30 (APC2_CSU_BASE+0x3DE*4) +#define APC2_CSU_SORTDATA_DATA31 (APC2_CSU_BASE+0x3DF*4) +#define APC2_CSU_SORTDATA_ID0 (APC2_CSU_BASE+0x3E0*4) +#define APC2_CSU_SORTDATA_ID1 (APC2_CSU_BASE+0x3E1*4) +#define APC2_CSU_SORTDATA_ID2 (APC2_CSU_BASE+0x3E2*4) +#define APC2_CSU_SORTDATA_ID3 (APC2_CSU_BASE+0x3E3*4) +#define APC2_CSU_SORTDATA_ID4 (APC2_CSU_BASE+0x3E4*4) +#define APC2_CSU_SORTDATA_ID5 (APC2_CSU_BASE+0x3E5*4) +#define APC2_CSU_SORTDATA_ID6 (APC2_CSU_BASE+0x3E6*4) +#define APC2_CSU_SORTDATA_ID7 (APC2_CSU_BASE+0x3E7*4) +#define APC2_CSU_SORTDATA_ID8 (APC2_CSU_BASE+0x3E8*4) +#define APC2_CSU_SORTDATA_ID9 (APC2_CSU_BASE+0x3E9*4) +#define APC2_CSU_SORTDATA_ID10 (APC2_CSU_BASE+0x3EA*4) +#define APC2_CSU_SORTDATA_ID11 (APC2_CSU_BASE+0x3EB*4) +#define APC2_CSU_SORTDATA_ID12 (APC2_CSU_BASE+0x3EC*4) +#define APC2_CSU_SORTDATA_ID13 (APC2_CSU_BASE+0x3ED*4) +#define APC2_CSU_SORTDATA_ID14 (APC2_CSU_BASE+0x3EE*4) +#define APC2_CSU_SORTDATA_ID15 (APC2_CSU_BASE+0x3EF*4) +#define APC2_CSU_SORTDATA_ID16 (APC2_CSU_BASE+0x3F0*4) +#define APC2_CSU_SORTDATA_ID17 (APC2_CSU_BASE+0x3F1*4) +#define APC2_CSU_SORTDATA_ID18 (APC2_CSU_BASE+0x3F2*4) +#define APC2_CSU_SORTDATA_ID19 (APC2_CSU_BASE+0x3F3*4) +#define APC2_CSU_SORTDATA_ID20 (APC2_CSU_BASE+0x3F4*4) +#define APC2_CSU_SORTDATA_ID21 (APC2_CSU_BASE+0x3F5*4) +#define APC2_CSU_SORTDATA_ID22 (APC2_CSU_BASE+0x3F6*4) +#define APC2_CSU_SORTDATA_ID23 (APC2_CSU_BASE+0x3F7*4) +#define APC2_CSU_SORTDATA_ID24 (APC2_CSU_BASE+0x3F8*4) +#define APC2_CSU_SORTDATA_ID25 (APC2_CSU_BASE+0x3F9*4) +#define APC2_CSU_SORTDATA_ID26 (APC2_CSU_BASE+0x3FA*4) +#define APC2_CSU_SORTDATA_ID27 (APC2_CSU_BASE+0x3FB*4) +#define APC2_CSU_SORTDATA_ID28 (APC2_CSU_BASE+0x3FC*4) +#define APC2_CSU_SORTDATA_ID29 (APC2_CSU_BASE+0x3FD*4) +#define APC2_CSU_SORTDATA_ID30 (APC2_CSU_BASE+0x3FE*4) +#define APC2_CSU_SORTDATA_ID31 (APC2_CSU_BASE+0x3FF*4) + + +#define APC3_CSU_STARTSPU0 (APC3_CSU_BASE+0x000*4) +#define APC3_CSU_ALLPENDEVENTMASK (APC3_CSU_BASE+0x000*4) +#define APC3_CSU_STARTSPU1 (APC3_CSU_BASE+0x001*4) +#define APC3_CSU_EVENTMASK (APC3_CSU_BASE+0x002*4) +#define APC3_CSU_INTMASK (APC3_CSU_BASE+0x004*4) +#define APC3_CSU_ELEVELMASK (APC3_CSU_BASE+0x005*4) +#define APC3_CSU_TAGMASK0 (APC3_CSU_BASE+0x006*4) +#define APC3_CSU_TAGMASK1 (APC3_CSU_BASE+0x007*4) +#define APC3_CSU_TAGMASK2 (APC3_CSU_BASE+0x008*4) +#define APC3_CSU_TAGMASK3 (APC3_CSU_BASE+0x009*4) +#define APC3_CSU_ARMCMDRECV (APC3_CSU_BASE+0x00A*4) +#define APC3_CSU_FETCHMODE_CACHEMODE (APC3_CSU_BASE+0x00B*4) +#define APC3_CSU_ALLPENDEVENT0 (APC3_CSU_BASE+0x00C*4) +#define APC3_CSU_ALLPENDEVENT1 (APC3_CSU_BASE+0x00D*4) +#define APC3_CSU_EM_BS_SMSEL_PREDATANUM (APC3_CSU_BASE+0x010*4) +#define APC3_CSU_CACHEINFO_EM_BS_SPURWCACHE_SMSEL_PDNUM (APC3_CSU_BASE+0x010*4) +#define APC3_CSU_FINDDMATAG (APC3_CSU_BASE+0x014*4) +#define APC3_CSU_CMDFIFO0_CMD (APC3_CSU_BASE+0x018*4) +#define APC3_CSU_CMDFIFO1_CMD (APC3_CSU_BASE+0x019*4) +#define APC3_CSU_CMDFIFO2_CMD (APC3_CSU_BASE+0x01A*4) +#define APC3_CSU_CMDFIFO3_CMD (APC3_CSU_BASE+0x01B*4) +#define APC3_CSU_CMDFIFO0_NUM (APC3_CSU_BASE+0x01C*4) +#define APC3_CSU_CMDFIFO1_NUM (APC3_CSU_BASE+0x01D*4) +#define APC3_CSU_CMDFIFO2_NUM (APC3_CSU_BASE+0x01E*4) +#define APC3_CSU_CMDFIFO3_NUM (APC3_CSU_BASE+0x01F*4) +#define APC3_CSU_PRICMDVALID0 (APC3_CSU_BASE+0x020*4) +#define APC3_CSU_PRICMDVALID1 (APC3_CSU_BASE+0x021*4) +#define APC3_CSU_PRICMDVALID2 (APC3_CSU_BASE+0x022*4) +#define APC3_CSU_PRICMDVALID3 (APC3_CSU_BASE+0x023*4) +#define APC3_CSU_CMDECODATAL32BIT0 (APC3_CSU_BASE+0x024*4) +#define APC3_CSU_CMDECODATAL32BIT1 (APC3_CSU_BASE+0x025*4) +#define APC3_CSU_CMDECODATAL32BIT2 (APC3_CSU_BASE+0x026*4) +#define APC3_CSU_CMDECODATAL32BIT3 (APC3_CSU_BASE+0x027*4) +#define APC3_CSU_CMDHIGHDATA (APC3_CSU_BASE+0x028*4) +#define APC3_CSU_CMDFIFO0 (APC3_CSU_BASE+0x02C*4) +#define APC3_CSU_CMDFIFO1 (APC3_CSU_BASE+0x02D*4) +#define APC3_CSU_CMDFIFO2 (APC3_CSU_BASE+0x02E*4) +#define APC3_CSU_CMDFIFO3 (APC3_CSU_BASE+0x02F*4) +#define APC3_CSU_READYLISTNUM (APC3_CSU_BASE+0x030*4) +#define APC3_CSU_CMDFIFO0_TAGNUM (APC3_CSU_BASE+0x034*4) +#define APC3_CSU_CMDFIFO1_TAGNUM (APC3_CSU_BASE+0x035*4) +#define APC3_CSU_CMDFIFO2_TAGNUM (APC3_CSU_BASE+0x036*4) +#define APC3_CSU_CMDFIFO3_TAGNUM (APC3_CSU_BASE+0x037*4) +#define APC3_CSU_DMASTATUS (APC3_CSU_BASE+0x038*4) +#define APC3_CSU_CMDSTALL_LISTSTALL (APC3_CSU_BASE+0x039*4) +#define APC3_CSU_QOUSTATUS (APC3_CSU_BASE+0x03A*4) +#define APC3_CSU_EVENTINTCLEAR (APC3_CSU_BASE+0x03C*4) +#define APC3_CSU_MAILBOX_PRIDATAREG0 (APC3_CSU_BASE+0x100*4) +#define APC3_CSU_MAILBOX_PRIDATAREG1 (APC3_CSU_BASE+0x101*4) +#define APC3_CSU_MAILBOX_PRIDATAREG2 (APC3_CSU_BASE+0x102*4) +#define APC3_CSU_MAILBOX_PRIDATAREG3 (APC3_CSU_BASE+0x103*4) +#define APC3_CSU_MAILBOX_PRIDATAREG4 (APC3_CSU_BASE+0x104*4) +#define APC3_CSU_MAILBOX_PRIDATAREG5 (APC3_CSU_BASE+0x105*4) +#define APC3_CSU_MAILBOX_PRIDATAREG6 (APC3_CSU_BASE+0x106*4) +#define APC3_CSU_MAILBOX_PRIDATAREG7 (APC3_CSU_BASE+0x107*4) +#define APC3_CSU_MAILBOX_PRIDATAREG8 (APC3_CSU_BASE+0x108*4) +#define APC3_CSU_MAILBOX_PRIDATAREG9 (APC3_CSU_BASE+0x109*4) +#define APC3_CSU_MAILBOX_PRIDATAREG10 (APC3_CSU_BASE+0x10A*4) +#define APC3_CSU_MAILBOX_PRIDATAREG11 (APC3_CSU_BASE+0x10B*4) +#define APC3_CSU_MAILBOX_PRIDATAREG12 (APC3_CSU_BASE+0x10C*4) +#define APC3_CSU_MAILBOX_PRIDATAREG13 (APC3_CSU_BASE+0x10D*4) +#define APC3_CSU_MAILBOX_PRIDATAREG14 (APC3_CSU_BASE+0x10E*4) +#define APC3_CSU_MAILBOX_PRIDATAREG15 (APC3_CSU_BASE+0x10F*4) +#define APC3_CSU_MAILBOX_BASENUM (APC3_CSU_BASE+0x120*4) +#define APC3_CSU_MAILBOX_BASECNT (APC3_CSU_BASE+0x121*4) +#define APC3_CSU_MAILBOX_VALIDREG (APC3_CSU_BASE+0x122*4) +#define APC3_CSU_MAILBOX_INTMASK0 (APC3_CSU_BASE+0x124*4) +#define APC3_CSU_MAILBOX_INTMASK1 (APC3_CSU_BASE+0x125*4) +#define APC3_CSU_MAILBOX_INTMASK2 (APC3_CSU_BASE+0x126*4) +#define APC3_CSU_MAILBOX_INTMASK3 (APC3_CSU_BASE+0x127*4) +#define APC3_CSU_MAILBOX_EVENTMASK0 (APC3_CSU_BASE+0x130*4) +#define APC3_CSU_MAILBOX_EVENTMASK1 (APC3_CSU_BASE+0x131*4) +#define APC3_CSU_MAILBOX_CNTREG0 (APC3_CSU_BASE+0x180*4) +#define APC3_CSU_MAILBOX_CNTREG1 (APC3_CSU_BASE+0x181*4) +#define APC3_CSU_MAILBOX_CNTREG2 (APC3_CSU_BASE+0x182*4) +#define APC3_CSU_MAILBOX_CNTREG3 (APC3_CSU_BASE+0x183*4) +#define APC3_CSU_MAILBOX_CNTREG4 (APC3_CSU_BASE+0x184*4) +#define APC3_CSU_MAILBOX_CNTREG5 (APC3_CSU_BASE+0x185*4) +#define APC3_CSU_MAILBOX_CNTREG6 (APC3_CSU_BASE+0x186*4) +#define APC3_CSU_MAILBOX_CNTREG7 (APC3_CSU_BASE+0x187*4) +#define APC3_CSU_MAILBOX_CNTREG8 (APC3_CSU_BASE+0x188*4) +#define APC3_CSU_MAILBOX_CNTREG9 (APC3_CSU_BASE+0x189*4) +#define APC3_CSU_MAILBOX_CNTREG10 (APC3_CSU_BASE+0x18A*4) +#define APC3_CSU_MAILBOX_CNTREG11 (APC3_CSU_BASE+0x18B*4) +#define APC3_CSU_MAILBOX_CNTREG12 (APC3_CSU_BASE+0x18C*4) +#define APC3_CSU_MAILBOX_CNTREG13 (APC3_CSU_BASE+0x18D*4) +#define APC3_CSU_MAILBOX_CNTREG14 (APC3_CSU_BASE+0x18E*4) +#define APC3_CSU_MAILBOX_CNTREG15 (APC3_CSU_BASE+0x18F*4) +#define APC3_CSU_DMAADDRL0 (APC3_CSU_BASE+0x200*4) +#define APC3_CSU_DMAADDRH0 (APC3_CSU_BASE+0x201*4) +#define APC3_CSU_DMAYSTEPL0 (APC3_CSU_BASE+0x202*4) +#define APC3_CSU_DMAYSTEPH0 (APC3_CSU_BASE+0x203*4) +#define APC3_CSU_DMAZSTEPL0 (APC3_CSU_BASE+0x204*4) +#define APC3_CSU_DMAZSTEPH0 (APC3_CSU_BASE+0x205*4) +#define APC3_CSU_DMAYNUMXNUM0 (APC3_CSU_BASE+0x206*4) +#define APC3_CSU_DMASIZEGRANALLNUM0 (APC3_CSU_BASE+0x207*4) +#define APC3_CSU_DMAADDRL1 (APC3_CSU_BASE+0x208*4) +#define APC3_CSU_DMAADDRH1 (APC3_CSU_BASE+0x209*4) +#define APC3_CSU_DMAYSTEPL1 (APC3_CSU_BASE+0x20A*4) +#define APC3_CSU_DMAYSTEPH1 (APC3_CSU_BASE+0x20B*4) +#define APC3_CSU_DMAZSTEPL1 (APC3_CSU_BASE+0x20C*4) +#define APC3_CSU_DMAZSTEPH1 (APC3_CSU_BASE+0x20D*4) +#define APC3_CSU_DMAYNUMXNUM1 (APC3_CSU_BASE+0x20E*4) +#define APC3_CSU_DMASIZEGRANALLNUM1 (APC3_CSU_BASE+0x20F*4) +#define APC3_CSU_DMAADDRL2 (APC3_CSU_BASE+0x210*4) +#define APC3_CSU_DMAADDRH2 (APC3_CSU_BASE+0x211*4) +#define APC3_CSU_DMAYSTEPL2 (APC3_CSU_BASE+0x212*4) +#define APC3_CSU_DMAYSTEPH2 (APC3_CSU_BASE+0x213*4) +#define APC3_CSU_DMAZSTEPL2 (APC3_CSU_BASE+0x214*4) +#define APC3_CSU_DMAZSTEPH2 (APC3_CSU_BASE+0x215*4) +#define APC3_CSU_DMAYNUMXNUM2 (APC3_CSU_BASE+0x216*4) +#define APC3_CSU_DMASIZEGRANALLNUM2 (APC3_CSU_BASE+0x217*4) +#define APC3_CSU_DMAADDRL3 (APC3_CSU_BASE+0x218*4) +#define APC3_CSU_DMAADDRH3 (APC3_CSU_BASE+0x219*4) +#define APC3_CSU_DMAYSTEPL3 (APC3_CSU_BASE+0x21A*4) +#define APC3_CSU_DMAYSTEPH3 (APC3_CSU_BASE+0x21B*4) +#define APC3_CSU_DMAZSTEPL3 (APC3_CSU_BASE+0x21C*4) +#define APC3_CSU_DMAZSTEPH3 (APC3_CSU_BASE+0x21D*4) +#define APC3_CSU_DMAYNUMXNUM3 (APC3_CSU_BASE+0x21E*4) +#define APC3_CSU_DMASIZEGRANALLNUM3 (APC3_CSU_BASE+0x21F*4) +#define APC3_CSU_DMAADDRL4 (APC3_CSU_BASE+0x220*4) +#define APC3_CSU_DMAADDRH4 (APC3_CSU_BASE+0x221*4) +#define APC3_CSU_DMAYSTEPL4 (APC3_CSU_BASE+0x222*4) +#define APC3_CSU_DMAYSTEPH4 (APC3_CSU_BASE+0x223*4) +#define APC3_CSU_DMAZSTEPL4 (APC3_CSU_BASE+0x224*4) +#define APC3_CSU_DMAZSTEPH4 (APC3_CSU_BASE+0x225*4) +#define APC3_CSU_DMAYNUMXNUM4 (APC3_CSU_BASE+0x226*4) +#define APC3_CSU_DMASIZEGRANALLNUM4 (APC3_CSU_BASE+0x227*4) +#define APC3_CSU_DMAADDRL5 (APC3_CSU_BASE+0x228*4) +#define APC3_CSU_DMAADDRH5 (APC3_CSU_BASE+0x229*4) +#define APC3_CSU_DMAYSTEPL5 (APC3_CSU_BASE+0x22A*4) +#define APC3_CSU_DMAYSTEPH5 (APC3_CSU_BASE+0x22B*4) +#define APC3_CSU_DMAZSTEPL5 (APC3_CSU_BASE+0x22C*4) +#define APC3_CSU_DMAZSTEPH5 (APC3_CSU_BASE+0x22D*4) +#define APC3_CSU_DMAYNUMXNUM5 (APC3_CSU_BASE+0x22E*4) +#define APC3_CSU_DMASIZEGRANALLNUM5 (APC3_CSU_BASE+0x22F*4) +#define APC3_CSU_DMAADDRL6 (APC3_CSU_BASE+0x230*4) +#define APC3_CSU_DMAADDRH6 (APC3_CSU_BASE+0x231*4) +#define APC3_CSU_DMAYSTEPL6 (APC3_CSU_BASE+0x232*4) +#define APC3_CSU_DMAYSTEPH6 (APC3_CSU_BASE+0x233*4) +#define APC3_CSU_DMAZSTEPL6 (APC3_CSU_BASE+0x234*4) +#define APC3_CSU_DMAZSTEPH6 (APC3_CSU_BASE+0x235*4) +#define APC3_CSU_DMAYNUMXNUM6 (APC3_CSU_BASE+0x236*4) +#define APC3_CSU_DMASIZEGRANALLNUM6 (APC3_CSU_BASE+0x237*4) +#define APC3_CSU_DMAADDRL7 (APC3_CSU_BASE+0x238*4) +#define APC3_CSU_DMAADDRH7 (APC3_CSU_BASE+0x239*4) +#define APC3_CSU_DMAYSTEPL7 (APC3_CSU_BASE+0x23A*4) +#define APC3_CSU_DMAYSTEPH7 (APC3_CSU_BASE+0x23B*4) +#define APC3_CSU_DMAZSTEPL7 (APC3_CSU_BASE+0x23C*4) +#define APC3_CSU_DMAZSTEPH7 (APC3_CSU_BASE+0x23D*4) +#define APC3_CSU_DMAYNUMXNUM7 (APC3_CSU_BASE+0x23E*4) +#define APC3_CSU_DMASIZEGRANALLNUM7 (APC3_CSU_BASE+0x23F*4) +#define APC3_CSU_DMAADDRL8 (APC3_CSU_BASE+0x240*4) +#define APC3_CSU_DMAADDRH8 (APC3_CSU_BASE+0x241*4) +#define APC3_CSU_DMAYSTEPL8 (APC3_CSU_BASE+0x242*4) +#define APC3_CSU_DMAYSTEPH8 (APC3_CSU_BASE+0x243*4) +#define APC3_CSU_DMAZSTEPL8 (APC3_CSU_BASE+0x244*4) +#define APC3_CSU_DMAZSTEPH8 (APC3_CSU_BASE+0x245*4) +#define APC3_CSU_DMAYNUMXNUM8 (APC3_CSU_BASE+0x246*4) +#define APC3_CSU_DMASIZEGRANALLNUM8 (APC3_CSU_BASE+0x247*4) +#define APC3_CSU_DMAADDRL9 (APC3_CSU_BASE+0x248*4) +#define APC3_CSU_DMAADDRH9 (APC3_CSU_BASE+0x249*4) +#define APC3_CSU_DMAYSTEPL9 (APC3_CSU_BASE+0x24A*4) +#define APC3_CSU_DMAYSTEPH9 (APC3_CSU_BASE+0x24B*4) +#define APC3_CSU_DMAZSTEPL9 (APC3_CSU_BASE+0x24C*4) +#define APC3_CSU_DMAZSTEPH9 (APC3_CSU_BASE+0x24D*4) +#define APC3_CSU_DMAYNUMXNUM9 (APC3_CSU_BASE+0x24E*4) +#define APC3_CSU_DMASIZEGRANALLNUM9 (APC3_CSU_BASE+0x24F*4) +#define APC3_CSU_DMAADDRL10 (APC3_CSU_BASE+0x250*4) +#define APC3_CSU_DMAADDRH10 (APC3_CSU_BASE+0x251*4) +#define APC3_CSU_DMAYSTEPL10 (APC3_CSU_BASE+0x252*4) +#define APC3_CSU_DMAYSTEPH10 (APC3_CSU_BASE+0x253*4) +#define APC3_CSU_DMAZSTEPL10 (APC3_CSU_BASE+0x254*4) +#define APC3_CSU_DMAZSTEPH10 (APC3_CSU_BASE+0x255*4) +#define APC3_CSU_DMAYNUMXNUM10 (APC3_CSU_BASE+0x256*4) +#define APC3_CSU_DMASIZEGRANALLNUM10 (APC3_CSU_BASE+0x257*4) +#define APC3_CSU_DMAADDRL11 (APC3_CSU_BASE+0x258*4) +#define APC3_CSU_DMAADDRH11 (APC3_CSU_BASE+0x259*4) +#define APC3_CSU_DMAYSTEPL11 (APC3_CSU_BASE+0x25A*4) +#define APC3_CSU_DMAYSTEPH11 (APC3_CSU_BASE+0x25B*4) +#define APC3_CSU_DMAZSTEPL11 (APC3_CSU_BASE+0x25C*4) +#define APC3_CSU_DMAZSTEPH11 (APC3_CSU_BASE+0x25D*4) +#define APC3_CSU_DMAYNUMXNUM11 (APC3_CSU_BASE+0x25E*4) +#define APC3_CSU_DMASIZEGRANALLNUM11 (APC3_CSU_BASE+0x25F*4) +#define APC3_CSU_DMAADDRL12 (APC3_CSU_BASE+0x260*4) +#define APC3_CSU_DMAADDRH12 (APC3_CSU_BASE+0x261*4) +#define APC3_CSU_DMAYSTEPL12 (APC3_CSU_BASE+0x262*4) +#define APC3_CSU_DMAYSTEPH12 (APC3_CSU_BASE+0x263*4) +#define APC3_CSU_DMAZSTEPL12 (APC3_CSU_BASE+0x264*4) +#define APC3_CSU_DMAZSTEPH12 (APC3_CSU_BASE+0x265*4) +#define APC3_CSU_DMAYNUMXNUM12 (APC3_CSU_BASE+0x266*4) +#define APC3_CSU_DMASIZEGRANALLNUM12 (APC3_CSU_BASE+0x267*4) +#define APC3_CSU_DMAADDRL13 (APC3_CSU_BASE+0x268*4) +#define APC3_CSU_DMAADDRH13 (APC3_CSU_BASE+0x269*4) +#define APC3_CSU_DMAYSTEPL13 (APC3_CSU_BASE+0x26A*4) +#define APC3_CSU_DMAYSTEPH13 (APC3_CSU_BASE+0x26B*4) +#define APC3_CSU_DMAZSTEPL13 (APC3_CSU_BASE+0x26C*4) +#define APC3_CSU_DMAZSTEPH13 (APC3_CSU_BASE+0x26D*4) +#define APC3_CSU_DMAYNUMXNUM13 (APC3_CSU_BASE+0x26E*4) +#define APC3_CSU_DMASIZEGRANALLNUM13 (APC3_CSU_BASE+0x26F*4) +#define APC3_CSU_DMAADDRL14 (APC3_CSU_BASE+0x270*4) +#define APC3_CSU_DMAADDRH14 (APC3_CSU_BASE+0x271*4) +#define APC3_CSU_DMAYSTEPL14 (APC3_CSU_BASE+0x272*4) +#define APC3_CSU_DMAYSTEPH14 (APC3_CSU_BASE+0x273*4) +#define APC3_CSU_DMAZSTEPL14 (APC3_CSU_BASE+0x274*4) +#define APC3_CSU_DMAZSTEPH14 (APC3_CSU_BASE+0x275*4) +#define APC3_CSU_DMAYNUMXNUM14 (APC3_CSU_BASE+0x276*4) +#define APC3_CSU_DMASIZEGRANALLNUM14 (APC3_CSU_BASE+0x277*4) +#define APC3_CSU_DMAADDRL15 (APC3_CSU_BASE+0x278*4) +#define APC3_CSU_DMAADDRH15 (APC3_CSU_BASE+0x279*4) +#define APC3_CSU_DMAYSTEPL15 (APC3_CSU_BASE+0x27A*4) +#define APC3_CSU_DMAYSTEPH15 (APC3_CSU_BASE+0x27B*4) +#define APC3_CSU_DMAZSTEPL15 (APC3_CSU_BASE+0x27C*4) +#define APC3_CSU_DMAZSTEPH15 (APC3_CSU_BASE+0x27D*4) +#define APC3_CSU_DMAYNUMXNUM15 (APC3_CSU_BASE+0x27E*4) +#define APC3_CSU_DMASIZEGRANALLNUM15 (APC3_CSU_BASE+0x27F*4) +#define APC3_CSU_QOUCMDNUM_QOUCMDPOS (APC3_CSU_BASE+0x300*4) +#define APC3_CSU_QOUCMDADDR (APC3_CSU_BASE+0x301*4) +#define APC3_CSU_QOUCMDDATA (APC3_CSU_BASE+0x302*4) +#define APC3_CSU_QOUSTATUSPOPDATA (APC3_CSU_BASE+0x303*4) +#define APC3_CSU_QOUCMPDATA0 (APC3_CSU_BASE+0x304*4) +#define APC3_CSU_QOUCMPDATA1 (APC3_CSU_BASE+0x305*4) +#define APC3_CSU_QOUCMPDATA2 (APC3_CSU_BASE+0x306*4) +#define APC3_CSU_QOUCMPDATA3 (APC3_CSU_BASE+0x307*4) +#define APC3_CSU_SPUID (APC3_CSU_BASE+0x30B*4) +#define APC3_CSU_PRICMDDATA_L32BIT0 (APC3_CSU_BASE+0x310*4) +#define APC3_CSU_PRICMDDATA_H14BIT0 (APC3_CSU_BASE+0x311*4) +#define APC3_CSU_PRICMDDATA_L32BIT1 (APC3_CSU_BASE+0x312*4) +#define APC3_CSU_PRICMDDATA_H14BIT1 (APC3_CSU_BASE+0x313*4) +#define APC3_CSU_PRICMDDATA_L32BIT2 (APC3_CSU_BASE+0x314*4) +#define APC3_CSU_PRICMDDATA_H14BIT2 (APC3_CSU_BASE+0x315*4) +#define APC3_CSU_PRICMDDATA_L32BIT3 (APC3_CSU_BASE+0x316*4) +#define APC3_CSU_PRICMDDATA_H14BIT3 (APC3_CSU_BASE+0x317*4) +#define APC3_CSU_SORTDATA_NUM (APC3_CSU_BASE+0x380*4) +#define APC3_CSU_SORTDATA_DATA0 (APC3_CSU_BASE+0x3C0*4) +#define APC3_CSU_SORTDATA_DATA1 (APC3_CSU_BASE+0x3C1*4) +#define APC3_CSU_SORTDATA_DATA2 (APC3_CSU_BASE+0x3C2*4) +#define APC3_CSU_SORTDATA_DATA3 (APC3_CSU_BASE+0x3C3*4) +#define APC3_CSU_SORTDATA_DATA4 (APC3_CSU_BASE+0x3C4*4) +#define APC3_CSU_SORTDATA_DATA5 (APC3_CSU_BASE+0x3C5*4) +#define APC3_CSU_SORTDATA_DATA6 (APC3_CSU_BASE+0x3C6*4) +#define APC3_CSU_SORTDATA_DATA7 (APC3_CSU_BASE+0x3C7*4) +#define APC3_CSU_SORTDATA_DATA8 (APC3_CSU_BASE+0x3C8*4) +#define APC3_CSU_SORTDATA_DATA9 (APC3_CSU_BASE+0x3C9*4) +#define APC3_CSU_SORTDATA_DATA10 (APC3_CSU_BASE+0x3CA*4) +#define APC3_CSU_SORTDATA_DATA11 (APC3_CSU_BASE+0x3CB*4) +#define APC3_CSU_SORTDATA_DATA12 (APC3_CSU_BASE+0x3CC*4) +#define APC3_CSU_SORTDATA_DATA13 (APC3_CSU_BASE+0x3CD*4) +#define APC3_CSU_SORTDATA_DATA14 (APC3_CSU_BASE+0x3CE*4) +#define APC3_CSU_SORTDATA_DATA15 (APC3_CSU_BASE+0x3CF*4) +#define APC3_CSU_SORTDATA_DATA16 (APC3_CSU_BASE+0x3D0*4) +#define APC3_CSU_SORTDATA_DATA17 (APC3_CSU_BASE+0x3D1*4) +#define APC3_CSU_SORTDATA_DATA18 (APC3_CSU_BASE+0x3D2*4) +#define APC3_CSU_SORTDATA_DATA19 (APC3_CSU_BASE+0x3D3*4) +#define APC3_CSU_SORTDATA_DATA20 (APC3_CSU_BASE+0x3D4*4) +#define APC3_CSU_SORTDATA_DATA21 (APC3_CSU_BASE+0x3D5*4) +#define APC3_CSU_SORTDATA_DATA22 (APC3_CSU_BASE+0x3D6*4) +#define APC3_CSU_SORTDATA_DATA23 (APC3_CSU_BASE+0x3D7*4) +#define APC3_CSU_SORTDATA_DATA24 (APC3_CSU_BASE+0x3D8*4) +#define APC3_CSU_SORTDATA_DATA25 (APC3_CSU_BASE+0x3D9*4) +#define APC3_CSU_SORTDATA_DATA26 (APC3_CSU_BASE+0x3DA*4) +#define APC3_CSU_SORTDATA_DATA27 (APC3_CSU_BASE+0x3DB*4) +#define APC3_CSU_SORTDATA_DATA28 (APC3_CSU_BASE+0x3DC*4) +#define APC3_CSU_SORTDATA_DATA29 (APC3_CSU_BASE+0x3DD*4) +#define APC3_CSU_SORTDATA_DATA30 (APC3_CSU_BASE+0x3DE*4) +#define APC3_CSU_SORTDATA_DATA31 (APC3_CSU_BASE+0x3DF*4) +#define APC3_CSU_SORTDATA_ID0 (APC3_CSU_BASE+0x3E0*4) +#define APC3_CSU_SORTDATA_ID1 (APC3_CSU_BASE+0x3E1*4) +#define APC3_CSU_SORTDATA_ID2 (APC3_CSU_BASE+0x3E2*4) +#define APC3_CSU_SORTDATA_ID3 (APC3_CSU_BASE+0x3E3*4) +#define APC3_CSU_SORTDATA_ID4 (APC3_CSU_BASE+0x3E4*4) +#define APC3_CSU_SORTDATA_ID5 (APC3_CSU_BASE+0x3E5*4) +#define APC3_CSU_SORTDATA_ID6 (APC3_CSU_BASE+0x3E6*4) +#define APC3_CSU_SORTDATA_ID7 (APC3_CSU_BASE+0x3E7*4) +#define APC3_CSU_SORTDATA_ID8 (APC3_CSU_BASE+0x3E8*4) +#define APC3_CSU_SORTDATA_ID9 (APC3_CSU_BASE+0x3E9*4) +#define APC3_CSU_SORTDATA_ID10 (APC3_CSU_BASE+0x3EA*4) +#define APC3_CSU_SORTDATA_ID11 (APC3_CSU_BASE+0x3EB*4) +#define APC3_CSU_SORTDATA_ID12 (APC3_CSU_BASE+0x3EC*4) +#define APC3_CSU_SORTDATA_ID13 (APC3_CSU_BASE+0x3ED*4) +#define APC3_CSU_SORTDATA_ID14 (APC3_CSU_BASE+0x3EE*4) +#define APC3_CSU_SORTDATA_ID15 (APC3_CSU_BASE+0x3EF*4) +#define APC3_CSU_SORTDATA_ID16 (APC3_CSU_BASE+0x3F0*4) +#define APC3_CSU_SORTDATA_ID17 (APC3_CSU_BASE+0x3F1*4) +#define APC3_CSU_SORTDATA_ID18 (APC3_CSU_BASE+0x3F2*4) +#define APC3_CSU_SORTDATA_ID19 (APC3_CSU_BASE+0x3F3*4) +#define APC3_CSU_SORTDATA_ID20 (APC3_CSU_BASE+0x3F4*4) +#define APC3_CSU_SORTDATA_ID21 (APC3_CSU_BASE+0x3F5*4) +#define APC3_CSU_SORTDATA_ID22 (APC3_CSU_BASE+0x3F6*4) +#define APC3_CSU_SORTDATA_ID23 (APC3_CSU_BASE+0x3F7*4) +#define APC3_CSU_SORTDATA_ID24 (APC3_CSU_BASE+0x3F8*4) +#define APC3_CSU_SORTDATA_ID25 (APC3_CSU_BASE+0x3F9*4) +#define APC3_CSU_SORTDATA_ID26 (APC3_CSU_BASE+0x3FA*4) +#define APC3_CSU_SORTDATA_ID27 (APC3_CSU_BASE+0x3FB*4) +#define APC3_CSU_SORTDATA_ID28 (APC3_CSU_BASE+0x3FC*4) +#define APC3_CSU_SORTDATA_ID29 (APC3_CSU_BASE+0x3FD*4) +#define APC3_CSU_SORTDATA_ID30 (APC3_CSU_BASE+0x3FE*4) +#define APC3_CSU_SORTDATA_ID31 (APC3_CSU_BASE+0x3FF*4) + + +#define ECSRFM_CSU_STARTSPU0 (ECSRFM_CSU_BASE+0x000*4) +#define ECSRFM_CSU_ALLPENDEVENTMASK (ECSRFM_CSU_BASE+0x000*4) +#define ECSRFM_CSU_STARTSPU1 (ECSRFM_CSU_BASE+0x001*4) +#define ECSRFM_CSU_EVENTMASK (ECSRFM_CSU_BASE+0x002*4) +#define ECSRFM_CSU_INTMASK (ECSRFM_CSU_BASE+0x004*4) +#define ECSRFM_CSU_ELEVELMASK (ECSRFM_CSU_BASE+0x005*4) +#define ECSRFM_CSU_TAGMASK0 (ECSRFM_CSU_BASE+0x006*4) +#define ECSRFM_CSU_TAGMASK1 (ECSRFM_CSU_BASE+0x007*4) +#define ECSRFM_CSU_TAGMASK2 (ECSRFM_CSU_BASE+0x008*4) +#define ECSRFM_CSU_TAGMASK3 (ECSRFM_CSU_BASE+0x009*4) +#define ECSRFM_CSU_ARMCMDRECV (ECSRFM_CSU_BASE+0x00A*4) +#define ECSRFM_CSU_FETCHMODE_CACHEMODE (ECSRFM_CSU_BASE+0x00B*4) +#define ECSRFM_CSU_ALLPENDEVENT0 (ECSRFM_CSU_BASE+0x00C*4) +#define ECSRFM_CSU_ALLPENDEVENT1 (ECSRFM_CSU_BASE+0x00D*4) +#define ECSRFM_CSU_EM_BS_SMSEL_PREDATANUM (ECSRFM_CSU_BASE+0x010*4) +#define ECSRFM_CSU_CACHEINFO_EM_BS_SPURWCACHE_SMSEL_PDNUM (ECSRFM_CSU_BASE+0x010*4) +#define ECSRFM_CSU_ALMOSTFULLSENDTHRED (ECSRFM_CSU_BASE+0x011*4) +#define ECSRFM_CSU_FINDDMATAG (ECSRFM_CSU_BASE+0x014*4) +#define ECSRFM_CSU_CMDFIFO0_CMD (ECSRFM_CSU_BASE+0x018*4) +#define ECSRFM_CSU_CMDFIFO1_CMD (ECSRFM_CSU_BASE+0x019*4) +#define ECSRFM_CSU_CMDFIFO2_CMD (ECSRFM_CSU_BASE+0x01A*4) +#define ECSRFM_CSU_CMDFIFO3_CMD (ECSRFM_CSU_BASE+0x01B*4) +#define ECSRFM_CSU_CMDFIFO0_NUM (ECSRFM_CSU_BASE+0x01C*4) +#define ECSRFM_CSU_CMDFIFO1_NUM (ECSRFM_CSU_BASE+0x01D*4) +#define ECSRFM_CSU_CMDFIFO2_NUM (ECSRFM_CSU_BASE+0x01E*4) +#define ECSRFM_CSU_CMDFIFO3_NUM (ECSRFM_CSU_BASE+0x01F*4) +#define ECSRFM_CSU_PRICMDVALID0 (ECSRFM_CSU_BASE+0x020*4) +#define ECSRFM_CSU_PRICMDVALID1 (ECSRFM_CSU_BASE+0x021*4) +#define ECSRFM_CSU_PRICMDVALID2 (ECSRFM_CSU_BASE+0x022*4) +#define ECSRFM_CSU_PRICMDVALID3 (ECSRFM_CSU_BASE+0x023*4) +#define ECSRFM_CSU_CMDECODATAL32BIT0 (ECSRFM_CSU_BASE+0x024*4) +#define ECSRFM_CSU_CMDECODATAL32BIT1 (ECSRFM_CSU_BASE+0x025*4) +#define ECSRFM_CSU_CMDECODATAL32BIT2 (ECSRFM_CSU_BASE+0x026*4) +#define ECSRFM_CSU_CMDECODATAL32BIT3 (ECSRFM_CSU_BASE+0x027*4) +#define ECSRFM_CSU_CMDHIGHDATA (ECSRFM_CSU_BASE+0x028*4) +#define ECSRFM_CSU_CMDFIFO0 (ECSRFM_CSU_BASE+0x02C*4) +#define ECSRFM_CSU_CMDFIFO1 (ECSRFM_CSU_BASE+0x02D*4) +#define ECSRFM_CSU_CMDFIFO2 (ECSRFM_CSU_BASE+0x02E*4) +#define ECSRFM_CSU_CMDFIFO3 (ECSRFM_CSU_BASE+0x02F*4) +#define ECSRFM_CSU_READYLISTNUM (ECSRFM_CSU_BASE+0x030*4) +#define ECSRFM_CSU_CMDFIFO0_TAGNUM (ECSRFM_CSU_BASE+0x034*4) +#define ECSRFM_CSU_CMDFIFO1_TAGNUM (ECSRFM_CSU_BASE+0x035*4) +#define ECSRFM_CSU_CMDFIFO2_TAGNUM (ECSRFM_CSU_BASE+0x036*4) +#define ECSRFM_CSU_CMDFIFO3_TAGNUM (ECSRFM_CSU_BASE+0x037*4) +#define ECSRFM_CSU_DMASTATUS (ECSRFM_CSU_BASE+0x038*4) +#define ECSRFM_CSU_CMDSTALL_LISTSTALL (ECSRFM_CSU_BASE+0x039*4) +#define ECSRFM_CSU_QOUSTATUS (ECSRFM_CSU_BASE+0x03A*4) +#define ECSRFM_CSU_EVENTINTCLEAR (ECSRFM_CSU_BASE+0x03C*4) +#define ECSRFM_CSU_MAILBOX_PRIDATAREG0 (ECSRFM_CSU_BASE+0x100*4) +#define ECSRFM_CSU_MAILBOX_PRIDATAREG1 (ECSRFM_CSU_BASE+0x101*4) +#define ECSRFM_CSU_MAILBOX_PRIDATAREG2 (ECSRFM_CSU_BASE+0x102*4) +#define ECSRFM_CSU_MAILBOX_PRIDATAREG3 (ECSRFM_CSU_BASE+0x103*4) +#define ECSRFM_CSU_MAILBOX_PRIDATAREG4 (ECSRFM_CSU_BASE+0x104*4) +#define ECSRFM_CSU_MAILBOX_PRIDATAREG5 (ECSRFM_CSU_BASE+0x105*4) +#define ECSRFM_CSU_MAILBOX_PRIDATAREG6 (ECSRFM_CSU_BASE+0x106*4) +#define ECSRFM_CSU_MAILBOX_PRIDATAREG7 (ECSRFM_CSU_BASE+0x107*4) +#define ECSRFM_CSU_MAILBOX_PRIDATAREG8 (ECSRFM_CSU_BASE+0x108*4) +#define ECSRFM_CSU_MAILBOX_PRIDATAREG9 (ECSRFM_CSU_BASE+0x109*4) +#define ECSRFM_CSU_MAILBOX_PRIDATAREG10 (ECSRFM_CSU_BASE+0x10A*4) +#define ECSRFM_CSU_MAILBOX_PRIDATAREG11 (ECSRFM_CSU_BASE+0x10B*4) +#define ECSRFM_CSU_MAILBOX_PRIDATAREG12 (ECSRFM_CSU_BASE+0x10C*4) +#define ECSRFM_CSU_MAILBOX_PRIDATAREG13 (ECSRFM_CSU_BASE+0x10D*4) +#define ECSRFM_CSU_MAILBOX_PRIDATAREG14 (ECSRFM_CSU_BASE+0x10E*4) +#define ECSRFM_CSU_MAILBOX_PRIDATAREG15 (ECSRFM_CSU_BASE+0x10F*4) +#define ECSRFM_CSU_MAILBOX_BASENUM (ECSRFM_CSU_BASE+0x120*4) +#define ECSRFM_CSU_MAILBOX_BASECNT (ECSRFM_CSU_BASE+0x121*4) +#define ECSRFM_CSU_MAILBOX_VALIDREG (ECSRFM_CSU_BASE+0x122*4) +#define ECSRFM_CSU_MAILBOX_INTMASK0 (ECSRFM_CSU_BASE+0x124*4) +#define ECSRFM_CSU_MAILBOX_INTMASK1 (ECSRFM_CSU_BASE+0x125*4) +#define ECSRFM_CSU_MAILBOX_INTMASK2 (ECSRFM_CSU_BASE+0x126*4) +#define ECSRFM_CSU_MAILBOX_INTMASK3 (ECSRFM_CSU_BASE+0x127*4) +#define ECSRFM_CSU_MAILBOX_EVENTMASK0 (ECSRFM_CSU_BASE+0x130*4) +#define ECSRFM_CSU_MAILBOX_EVENTMASK1 (ECSRFM_CSU_BASE+0x131*4) +#define ECSRFM_CSU_MAILBOX_CNTREG0 (ECSRFM_CSU_BASE+0x180*4) +#define ECSRFM_CSU_MAILBOX_CNTREG1 (ECSRFM_CSU_BASE+0x181*4) +#define ECSRFM_CSU_MAILBOX_CNTREG2 (ECSRFM_CSU_BASE+0x182*4) +#define ECSRFM_CSU_MAILBOX_CNTREG3 (ECSRFM_CSU_BASE+0x183*4) +#define ECSRFM_CSU_MAILBOX_CNTREG4 (ECSRFM_CSU_BASE+0x184*4) +#define ECSRFM_CSU_MAILBOX_CNTREG5 (ECSRFM_CSU_BASE+0x185*4) +#define ECSRFM_CSU_MAILBOX_CNTREG6 (ECSRFM_CSU_BASE+0x186*4) +#define ECSRFM_CSU_MAILBOX_CNTREG7 (ECSRFM_CSU_BASE+0x187*4) +#define ECSRFM_CSU_MAILBOX_CNTREG8 (ECSRFM_CSU_BASE+0x188*4) +#define ECSRFM_CSU_MAILBOX_CNTREG9 (ECSRFM_CSU_BASE+0x189*4) +#define ECSRFM_CSU_MAILBOX_CNTREG10 (ECSRFM_CSU_BASE+0x18A*4) +#define ECSRFM_CSU_MAILBOX_CNTREG11 (ECSRFM_CSU_BASE+0x18B*4) +#define ECSRFM_CSU_MAILBOX_CNTREG12 (ECSRFM_CSU_BASE+0x18C*4) +#define ECSRFM_CSU_MAILBOX_CNTREG13 (ECSRFM_CSU_BASE+0x18D*4) +#define ECSRFM_CSU_MAILBOX_CNTREG14 (ECSRFM_CSU_BASE+0x18E*4) +#define ECSRFM_CSU_MAILBOX_CNTREG15 (ECSRFM_CSU_BASE+0x18F*4) +#define ECSRFM_CSU_DMAADDRL0 (ECSRFM_CSU_BASE+0x200*4) +#define ECSRFM_CSU_DMAADDRH0 (ECSRFM_CSU_BASE+0x201*4) +#define ECSRFM_CSU_DMAYSTEPL0 (ECSRFM_CSU_BASE+0x202*4) +#define ECSRFM_CSU_DMAYSTEPH0 (ECSRFM_CSU_BASE+0x203*4) +#define ECSRFM_CSU_DMAZSTEPL0 (ECSRFM_CSU_BASE+0x204*4) +#define ECSRFM_CSU_DMAZSTEPH0 (ECSRFM_CSU_BASE+0x205*4) +#define ECSRFM_CSU_DMAYNUMXNUM0 (ECSRFM_CSU_BASE+0x206*4) +#define ECSRFM_CSU_DMASIZEGRANALLNUM0 (ECSRFM_CSU_BASE+0x207*4) +#define ECSRFM_CSU_DMAADDRL1 (ECSRFM_CSU_BASE+0x208*4) +#define ECSRFM_CSU_DMAADDRH1 (ECSRFM_CSU_BASE+0x209*4) +#define ECSRFM_CSU_DMAYSTEPL1 (ECSRFM_CSU_BASE+0x20A*4) +#define ECSRFM_CSU_DMAYSTEPH1 (ECSRFM_CSU_BASE+0x20B*4) +#define ECSRFM_CSU_DMAZSTEPL1 (ECSRFM_CSU_BASE+0x20C*4) +#define ECSRFM_CSU_DMAZSTEPH1 (ECSRFM_CSU_BASE+0x20D*4) +#define ECSRFM_CSU_DMAYNUMXNUM1 (ECSRFM_CSU_BASE+0x20E*4) +#define ECSRFM_CSU_DMASIZEGRANALLNUM1 (ECSRFM_CSU_BASE+0x20F*4) +#define ECSRFM_CSU_DMAADDRL2 (ECSRFM_CSU_BASE+0x210*4) +#define ECSRFM_CSU_DMAADDRH2 (ECSRFM_CSU_BASE+0x211*4) +#define ECSRFM_CSU_DMAYSTEPL2 (ECSRFM_CSU_BASE+0x212*4) +#define ECSRFM_CSU_DMAYSTEPH2 (ECSRFM_CSU_BASE+0x213*4) +#define ECSRFM_CSU_DMAZSTEPL2 (ECSRFM_CSU_BASE+0x214*4) +#define ECSRFM_CSU_DMAZSTEPH2 (ECSRFM_CSU_BASE+0x215*4) +#define ECSRFM_CSU_DMAYNUMXNUM2 (ECSRFM_CSU_BASE+0x216*4) +#define ECSRFM_CSU_DMASIZEGRANALLNUM2 (ECSRFM_CSU_BASE+0x217*4) +#define ECSRFM_CSU_DMAADDRL3 (ECSRFM_CSU_BASE+0x218*4) +#define ECSRFM_CSU_DMAADDRH3 (ECSRFM_CSU_BASE+0x219*4) +#define ECSRFM_CSU_DMAYSTEPL3 (ECSRFM_CSU_BASE+0x21A*4) +#define ECSRFM_CSU_DMAYSTEPH3 (ECSRFM_CSU_BASE+0x21B*4) +#define ECSRFM_CSU_DMAZSTEPL3 (ECSRFM_CSU_BASE+0x21C*4) +#define ECSRFM_CSU_DMAZSTEPH3 (ECSRFM_CSU_BASE+0x21D*4) +#define ECSRFM_CSU_DMAYNUMXNUM3 (ECSRFM_CSU_BASE+0x21E*4) +#define ECSRFM_CSU_DMASIZEGRANALLNUM3 (ECSRFM_CSU_BASE+0x21F*4) +#define ECSRFM_CSU_DMAADDRL4 (ECSRFM_CSU_BASE+0x220*4) +#define ECSRFM_CSU_DMAADDRH4 (ECSRFM_CSU_BASE+0x221*4) +#define ECSRFM_CSU_DMAYSTEPL4 (ECSRFM_CSU_BASE+0x222*4) +#define ECSRFM_CSU_DMAYSTEPH4 (ECSRFM_CSU_BASE+0x223*4) +#define ECSRFM_CSU_DMAZSTEPL4 (ECSRFM_CSU_BASE+0x224*4) +#define ECSRFM_CSU_DMAZSTEPH4 (ECSRFM_CSU_BASE+0x225*4) +#define ECSRFM_CSU_DMAYNUMXNUM4 (ECSRFM_CSU_BASE+0x226*4) +#define ECSRFM_CSU_DMASIZEGRANALLNUM4 (ECSRFM_CSU_BASE+0x227*4) +#define ECSRFM_CSU_DMAADDRL5 (ECSRFM_CSU_BASE+0x228*4) +#define ECSRFM_CSU_DMAADDRH5 (ECSRFM_CSU_BASE+0x229*4) +#define ECSRFM_CSU_DMAYSTEPL5 (ECSRFM_CSU_BASE+0x22A*4) +#define ECSRFM_CSU_DMAYSTEPH5 (ECSRFM_CSU_BASE+0x22B*4) +#define ECSRFM_CSU_DMAZSTEPL5 (ECSRFM_CSU_BASE+0x22C*4) +#define ECSRFM_CSU_DMAZSTEPH5 (ECSRFM_CSU_BASE+0x22D*4) +#define ECSRFM_CSU_DMAYNUMXNUM5 (ECSRFM_CSU_BASE+0x22E*4) +#define ECSRFM_CSU_DMASIZEGRANALLNUM5 (ECSRFM_CSU_BASE+0x22F*4) +#define ECSRFM_CSU_DMAADDRL6 (ECSRFM_CSU_BASE+0x230*4) +#define ECSRFM_CSU_DMAADDRH6 (ECSRFM_CSU_BASE+0x231*4) +#define ECSRFM_CSU_DMAYSTEPL6 (ECSRFM_CSU_BASE+0x232*4) +#define ECSRFM_CSU_DMAYSTEPH6 (ECSRFM_CSU_BASE+0x233*4) +#define ECSRFM_CSU_DMAZSTEPL6 (ECSRFM_CSU_BASE+0x234*4) +#define ECSRFM_CSU_DMAZSTEPH6 (ECSRFM_CSU_BASE+0x235*4) +#define ECSRFM_CSU_DMAYNUMXNUM6 (ECSRFM_CSU_BASE+0x236*4) +#define ECSRFM_CSU_DMASIZEGRANALLNUM6 (ECSRFM_CSU_BASE+0x237*4) +#define ECSRFM_CSU_DMAADDRL7 (ECSRFM_CSU_BASE+0x238*4) +#define ECSRFM_CSU_DMAADDRH7 (ECSRFM_CSU_BASE+0x239*4) +#define ECSRFM_CSU_DMAYSTEPL7 (ECSRFM_CSU_BASE+0x23A*4) +#define ECSRFM_CSU_DMAYSTEPH7 (ECSRFM_CSU_BASE+0x23B*4) +#define ECSRFM_CSU_DMAZSTEPL7 (ECSRFM_CSU_BASE+0x23C*4) +#define ECSRFM_CSU_DMAZSTEPH7 (ECSRFM_CSU_BASE+0x23D*4) +#define ECSRFM_CSU_DMAYNUMXNUM7 (ECSRFM_CSU_BASE+0x23E*4) +#define ECSRFM_CSU_DMASIZEGRANALLNUM7 (ECSRFM_CSU_BASE+0x23F*4) +#define ECSRFM_CSU_DMAADDRL8 (ECSRFM_CSU_BASE+0x240*4) +#define ECSRFM_CSU_DMAADDRH8 (ECSRFM_CSU_BASE+0x241*4) +#define ECSRFM_CSU_DMAYSTEPL8 (ECSRFM_CSU_BASE+0x242*4) +#define ECSRFM_CSU_DMAYSTEPH8 (ECSRFM_CSU_BASE+0x243*4) +#define ECSRFM_CSU_DMAZSTEPL8 (ECSRFM_CSU_BASE+0x244*4) +#define ECSRFM_CSU_DMAZSTEPH8 (ECSRFM_CSU_BASE+0x245*4) +#define ECSRFM_CSU_DMAYNUMXNUM8 (ECSRFM_CSU_BASE+0x246*4) +#define ECSRFM_CSU_DMASIZEGRANALLNUM8 (ECSRFM_CSU_BASE+0x247*4) +#define ECSRFM_CSU_DMAADDRL9 (ECSRFM_CSU_BASE+0x248*4) +#define ECSRFM_CSU_DMAADDRH9 (ECSRFM_CSU_BASE+0x249*4) +#define ECSRFM_CSU_DMAYSTEPL9 (ECSRFM_CSU_BASE+0x24A*4) +#define ECSRFM_CSU_DMAYSTEPH9 (ECSRFM_CSU_BASE+0x24B*4) +#define ECSRFM_CSU_DMAZSTEPL9 (ECSRFM_CSU_BASE+0x24C*4) +#define ECSRFM_CSU_DMAZSTEPH9 (ECSRFM_CSU_BASE+0x24D*4) +#define ECSRFM_CSU_DMAYNUMXNUM9 (ECSRFM_CSU_BASE+0x24E*4) +#define ECSRFM_CSU_DMASIZEGRANALLNUM9 (ECSRFM_CSU_BASE+0x24F*4) +#define ECSRFM_CSU_DMAADDRL10 (ECSRFM_CSU_BASE+0x250*4) +#define ECSRFM_CSU_DMAADDRH10 (ECSRFM_CSU_BASE+0x251*4) +#define ECSRFM_CSU_DMAYSTEPL10 (ECSRFM_CSU_BASE+0x252*4) +#define ECSRFM_CSU_DMAYSTEPH10 (ECSRFM_CSU_BASE+0x253*4) +#define ECSRFM_CSU_DMAZSTEPL10 (ECSRFM_CSU_BASE+0x254*4) +#define ECSRFM_CSU_DMAZSTEPH10 (ECSRFM_CSU_BASE+0x255*4) +#define ECSRFM_CSU_DMAYNUMXNUM10 (ECSRFM_CSU_BASE+0x256*4) +#define ECSRFM_CSU_DMASIZEGRANALLNUM10 (ECSRFM_CSU_BASE+0x257*4) +#define ECSRFM_CSU_DMAADDRL11 (ECSRFM_CSU_BASE+0x258*4) +#define ECSRFM_CSU_DMAADDRH11 (ECSRFM_CSU_BASE+0x259*4) +#define ECSRFM_CSU_DMAYSTEPL11 (ECSRFM_CSU_BASE+0x25A*4) +#define ECSRFM_CSU_DMAYSTEPH11 (ECSRFM_CSU_BASE+0x25B*4) +#define ECSRFM_CSU_DMAZSTEPL11 (ECSRFM_CSU_BASE+0x25C*4) +#define ECSRFM_CSU_DMAZSTEPH11 (ECSRFM_CSU_BASE+0x25D*4) +#define ECSRFM_CSU_DMAYNUMXNUM11 (ECSRFM_CSU_BASE+0x25E*4) +#define ECSRFM_CSU_DMASIZEGRANALLNUM11 (ECSRFM_CSU_BASE+0x25F*4) +#define ECSRFM_CSU_DMAADDRL12 (ECSRFM_CSU_BASE+0x260*4) +#define ECSRFM_CSU_DMAADDRH12 (ECSRFM_CSU_BASE+0x261*4) +#define ECSRFM_CSU_DMAYSTEPL12 (ECSRFM_CSU_BASE+0x262*4) +#define ECSRFM_CSU_DMAYSTEPH12 (ECSRFM_CSU_BASE+0x263*4) +#define ECSRFM_CSU_DMAZSTEPL12 (ECSRFM_CSU_BASE+0x264*4) +#define ECSRFM_CSU_DMAZSTEPH12 (ECSRFM_CSU_BASE+0x265*4) +#define ECSRFM_CSU_DMAYNUMXNUM12 (ECSRFM_CSU_BASE+0x266*4) +#define ECSRFM_CSU_DMASIZEGRANALLNUM12 (ECSRFM_CSU_BASE+0x267*4) +#define ECSRFM_CSU_DMAADDRL13 (ECSRFM_CSU_BASE+0x268*4) +#define ECSRFM_CSU_DMAADDRH13 (ECSRFM_CSU_BASE+0x269*4) +#define ECSRFM_CSU_DMAYSTEPL13 (ECSRFM_CSU_BASE+0x26A*4) +#define ECSRFM_CSU_DMAYSTEPH13 (ECSRFM_CSU_BASE+0x26B*4) +#define ECSRFM_CSU_DMAZSTEPL13 (ECSRFM_CSU_BASE+0x26C*4) +#define ECSRFM_CSU_DMAZSTEPH13 (ECSRFM_CSU_BASE+0x26D*4) +#define ECSRFM_CSU_DMAYNUMXNUM13 (ECSRFM_CSU_BASE+0x26E*4) +#define ECSRFM_CSU_DMASIZEGRANALLNUM13 (ECSRFM_CSU_BASE+0x26F*4) +#define ECSRFM_CSU_DMAADDRL14 (ECSRFM_CSU_BASE+0x270*4) +#define ECSRFM_CSU_DMAADDRH14 (ECSRFM_CSU_BASE+0x271*4) +#define ECSRFM_CSU_DMAYSTEPL14 (ECSRFM_CSU_BASE+0x272*4) +#define ECSRFM_CSU_DMAYSTEPH14 (ECSRFM_CSU_BASE+0x273*4) +#define ECSRFM_CSU_DMAZSTEPL14 (ECSRFM_CSU_BASE+0x274*4) +#define ECSRFM_CSU_DMAZSTEPH14 (ECSRFM_CSU_BASE+0x275*4) +#define ECSRFM_CSU_DMAYNUMXNUM14 (ECSRFM_CSU_BASE+0x276*4) +#define ECSRFM_CSU_DMASIZEGRANALLNUM14 (ECSRFM_CSU_BASE+0x277*4) +#define ECSRFM_CSU_DMAADDRL15 (ECSRFM_CSU_BASE+0x278*4) +#define ECSRFM_CSU_DMAADDRH15 (ECSRFM_CSU_BASE+0x279*4) +#define ECSRFM_CSU_DMAYSTEPL15 (ECSRFM_CSU_BASE+0x27A*4) +#define ECSRFM_CSU_DMAYSTEPH15 (ECSRFM_CSU_BASE+0x27B*4) +#define ECSRFM_CSU_DMAZSTEPL15 (ECSRFM_CSU_BASE+0x27C*4) +#define ECSRFM_CSU_DMAZSTEPH15 (ECSRFM_CSU_BASE+0x27D*4) +#define ECSRFM_CSU_DMAYNUMXNUM15 (ECSRFM_CSU_BASE+0x27E*4) +#define ECSRFM_CSU_DMASIZEGRANALLNUM15 (ECSRFM_CSU_BASE+0x27F*4) +#define ECSRFM_CSU_QOUCMDNUM_QOUCMDPOS (ECSRFM_CSU_BASE+0x300*4) +#define ECSRFM_CSU_QOUCMDADDR (ECSRFM_CSU_BASE+0x301*4) +#define ECSRFM_CSU_QOUCMDDATA (ECSRFM_CSU_BASE+0x302*4) +#define ECSRFM_CSU_QOUSTATUSPOPDATA (ECSRFM_CSU_BASE+0x303*4) +#define ECSRFM_CSU_QOUCMPDATA0 (ECSRFM_CSU_BASE+0x304*4) +#define ECSRFM_CSU_QOUCMPDATA1 (ECSRFM_CSU_BASE+0x305*4) +#define ECSRFM_CSU_QOUCMPDATA2 (ECSRFM_CSU_BASE+0x306*4) +#define ECSRFM_CSU_QOUCMPDATA3 (ECSRFM_CSU_BASE+0x307*4) +#define ECSRFM_CSU_SPUID (ECSRFM_CSU_BASE+0x30B*4) +#define ECSRFM_CSU_PRICMDDATA_L32BIT0 (ECSRFM_CSU_BASE+0x310*4) +#define ECSRFM_CSU_PRICMDDATA_H14BIT0 (ECSRFM_CSU_BASE+0x311*4) +#define ECSRFM_CSU_PRICMDDATA_L32BIT1 (ECSRFM_CSU_BASE+0x312*4) +#define ECSRFM_CSU_PRICMDDATA_H14BIT1 (ECSRFM_CSU_BASE+0x313*4) +#define ECSRFM_CSU_PRICMDDATA_L32BIT2 (ECSRFM_CSU_BASE+0x314*4) +#define ECSRFM_CSU_PRICMDDATA_H14BIT2 (ECSRFM_CSU_BASE+0x315*4) +#define ECSRFM_CSU_PRICMDDATA_L32BIT3 (ECSRFM_CSU_BASE+0x316*4) +#define ECSRFM_CSU_PRICMDDATA_H14BIT3 (ECSRFM_CSU_BASE+0x317*4) +#define ECSRFM_CSU_SORTDATA_NUM (ECSRFM_CSU_BASE+0x380*4) +#define ECSRFM_CSU_SORTDATA_DATA0 (ECSRFM_CSU_BASE+0x3C0*4) +#define ECSRFM_CSU_SORTDATA_DATA1 (ECSRFM_CSU_BASE+0x3C1*4) +#define ECSRFM_CSU_SORTDATA_DATA2 (ECSRFM_CSU_BASE+0x3C2*4) +#define ECSRFM_CSU_SORTDATA_DATA3 (ECSRFM_CSU_BASE+0x3C3*4) +#define ECSRFM_CSU_SORTDATA_DATA4 (ECSRFM_CSU_BASE+0x3C4*4) +#define ECSRFM_CSU_SORTDATA_DATA5 (ECSRFM_CSU_BASE+0x3C5*4) +#define ECSRFM_CSU_SORTDATA_DATA6 (ECSRFM_CSU_BASE+0x3C6*4) +#define ECSRFM_CSU_SORTDATA_DATA7 (ECSRFM_CSU_BASE+0x3C7*4) +#define ECSRFM_CSU_SORTDATA_DATA8 (ECSRFM_CSU_BASE+0x3C8*4) +#define ECSRFM_CSU_SORTDATA_DATA9 (ECSRFM_CSU_BASE+0x3C9*4) +#define ECSRFM_CSU_SORTDATA_DATA10 (ECSRFM_CSU_BASE+0x3CA*4) +#define ECSRFM_CSU_SORTDATA_DATA11 (ECSRFM_CSU_BASE+0x3CB*4) +#define ECSRFM_CSU_SORTDATA_DATA12 (ECSRFM_CSU_BASE+0x3CC*4) +#define ECSRFM_CSU_SORTDATA_DATA13 (ECSRFM_CSU_BASE+0x3CD*4) +#define ECSRFM_CSU_SORTDATA_DATA14 (ECSRFM_CSU_BASE+0x3CE*4) +#define ECSRFM_CSU_SORTDATA_DATA15 (ECSRFM_CSU_BASE+0x3CF*4) +#define ECSRFM_CSU_SORTDATA_DATA16 (ECSRFM_CSU_BASE+0x3D0*4) +#define ECSRFM_CSU_SORTDATA_DATA17 (ECSRFM_CSU_BASE+0x3D1*4) +#define ECSRFM_CSU_SORTDATA_DATA18 (ECSRFM_CSU_BASE+0x3D2*4) +#define ECSRFM_CSU_SORTDATA_DATA19 (ECSRFM_CSU_BASE+0x3D3*4) +#define ECSRFM_CSU_SORTDATA_DATA20 (ECSRFM_CSU_BASE+0x3D4*4) +#define ECSRFM_CSU_SORTDATA_DATA21 (ECSRFM_CSU_BASE+0x3D5*4) +#define ECSRFM_CSU_SORTDATA_DATA22 (ECSRFM_CSU_BASE+0x3D6*4) +#define ECSRFM_CSU_SORTDATA_DATA23 (ECSRFM_CSU_BASE+0x3D7*4) +#define ECSRFM_CSU_SORTDATA_DATA24 (ECSRFM_CSU_BASE+0x3D8*4) +#define ECSRFM_CSU_SORTDATA_DATA25 (ECSRFM_CSU_BASE+0x3D9*4) +#define ECSRFM_CSU_SORTDATA_DATA26 (ECSRFM_CSU_BASE+0x3DA*4) +#define ECSRFM_CSU_SORTDATA_DATA27 (ECSRFM_CSU_BASE+0x3DB*4) +#define ECSRFM_CSU_SORTDATA_DATA28 (ECSRFM_CSU_BASE+0x3DC*4) +#define ECSRFM_CSU_SORTDATA_DATA29 (ECSRFM_CSU_BASE+0x3DD*4) +#define ECSRFM_CSU_SORTDATA_DATA30 (ECSRFM_CSU_BASE+0x3DE*4) +#define ECSRFM_CSU_SORTDATA_DATA31 (ECSRFM_CSU_BASE+0x3DF*4) +#define ECSRFM_CSU_SORTDATA_ID0 (ECSRFM_CSU_BASE+0x3E0*4) +#define ECSRFM_CSU_SORTDATA_ID1 (ECSRFM_CSU_BASE+0x3E1*4) +#define ECSRFM_CSU_SORTDATA_ID2 (ECSRFM_CSU_BASE+0x3E2*4) +#define ECSRFM_CSU_SORTDATA_ID3 (ECSRFM_CSU_BASE+0x3E3*4) +#define ECSRFM_CSU_SORTDATA_ID4 (ECSRFM_CSU_BASE+0x3E4*4) +#define ECSRFM_CSU_SORTDATA_ID5 (ECSRFM_CSU_BASE+0x3E5*4) +#define ECSRFM_CSU_SORTDATA_ID6 (ECSRFM_CSU_BASE+0x3E6*4) +#define ECSRFM_CSU_SORTDATA_ID7 (ECSRFM_CSU_BASE+0x3E7*4) +#define ECSRFM_CSU_SORTDATA_ID8 (ECSRFM_CSU_BASE+0x3E8*4) +#define ECSRFM_CSU_SORTDATA_ID9 (ECSRFM_CSU_BASE+0x3E9*4) +#define ECSRFM_CSU_SORTDATA_ID10 (ECSRFM_CSU_BASE+0x3EA*4) +#define ECSRFM_CSU_SORTDATA_ID11 (ECSRFM_CSU_BASE+0x3EB*4) +#define ECSRFM_CSU_SORTDATA_ID12 (ECSRFM_CSU_BASE+0x3EC*4) +#define ECSRFM_CSU_SORTDATA_ID13 (ECSRFM_CSU_BASE+0x3ED*4) +#define ECSRFM_CSU_SORTDATA_ID14 (ECSRFM_CSU_BASE+0x3EE*4) +#define ECSRFM_CSU_SORTDATA_ID15 (ECSRFM_CSU_BASE+0x3EF*4) +#define ECSRFM_CSU_SORTDATA_ID16 (ECSRFM_CSU_BASE+0x3F0*4) +#define ECSRFM_CSU_SORTDATA_ID17 (ECSRFM_CSU_BASE+0x3F1*4) +#define ECSRFM_CSU_SORTDATA_ID18 (ECSRFM_CSU_BASE+0x3F2*4) +#define ECSRFM_CSU_SORTDATA_ID19 (ECSRFM_CSU_BASE+0x3F3*4) +#define ECSRFM_CSU_SORTDATA_ID20 (ECSRFM_CSU_BASE+0x3F4*4) +#define ECSRFM_CSU_SORTDATA_ID21 (ECSRFM_CSU_BASE+0x3F5*4) +#define ECSRFM_CSU_SORTDATA_ID22 (ECSRFM_CSU_BASE+0x3F6*4) +#define ECSRFM_CSU_SORTDATA_ID23 (ECSRFM_CSU_BASE+0x3F7*4) +#define ECSRFM_CSU_SORTDATA_ID24 (ECSRFM_CSU_BASE+0x3F8*4) +#define ECSRFM_CSU_SORTDATA_ID25 (ECSRFM_CSU_BASE+0x3F9*4) +#define ECSRFM_CSU_SORTDATA_ID26 (ECSRFM_CSU_BASE+0x3FA*4) +#define ECSRFM_CSU_SORTDATA_ID27 (ECSRFM_CSU_BASE+0x3FB*4) +#define ECSRFM_CSU_SORTDATA_ID28 (ECSRFM_CSU_BASE+0x3FC*4) +#define ECSRFM_CSU_SORTDATA_ID29 (ECSRFM_CSU_BASE+0x3FD*4) +#define ECSRFM_CSU_SORTDATA_ID30 (ECSRFM_CSU_BASE+0x3FE*4) +#define ECSRFM_CSU_SORTDATA_ID31 (ECSRFM_CSU_BASE+0x3FF*4) + + +#define PETRFM_CSU_STARTSPU0 (PETRFM_CSU_BASE+0x000*4) +#define PETRFM_CSU_ALLPENDEVENTMASK (PETRFM_CSU_BASE+0x000*4) +#define PETRFM_CSU_STARTSPU1 (PETRFM_CSU_BASE+0x001*4) +#define PETRFM_CSU_EVENTMASK (PETRFM_CSU_BASE+0x002*4) +#define PETRFM_CSU_INTMASK (PETRFM_CSU_BASE+0x004*4) +#define PETRFM_CSU_ELEVELMASK (PETRFM_CSU_BASE+0x005*4) +#define PETRFM_CSU_TAGMASK0 (PETRFM_CSU_BASE+0x006*4) +#define PETRFM_CSU_TAGMASK1 (PETRFM_CSU_BASE+0x007*4) +#define PETRFM_CSU_TAGMASK2 (PETRFM_CSU_BASE+0x008*4) +#define PETRFM_CSU_TAGMASK3 (PETRFM_CSU_BASE+0x009*4) +#define PETRFM_CSU_ARMCMDRECV (PETRFM_CSU_BASE+0x00A*4) +#define PETRFM_CSU_FETCHMODE_CACHEMODE (PETRFM_CSU_BASE+0x00B*4) +#define PETRFM_CSU_ALLPENDEVENT0 (PETRFM_CSU_BASE+0x00C*4) +#define PETRFM_CSU_ALLPENDEVENT1 (PETRFM_CSU_BASE+0x00D*4) +#define PETRFM_CSU_EM_BS_SMSEL_PREDATANUM (PETRFM_CSU_BASE+0x010*4) +#define PETRFM_CSU_CACHEINFO_EM_BS_SPURWCACHE_SMSEL_PDNUM (PETRFM_CSU_BASE+0x010*4) +#define PETRFM_CSU_ALMOSTFULLSENDTHRED (PETRFM_CSU_BASE+0x011*4) +#define PETRFM_CSU_FINDDMATAG (PETRFM_CSU_BASE+0x014*4) +#define PETRFM_CSU_CMDFIFO0_CMD (PETRFM_CSU_BASE+0x018*4) +#define PETRFM_CSU_CMDFIFO1_CMD (PETRFM_CSU_BASE+0x019*4) +#define PETRFM_CSU_CMDFIFO0_NUM (PETRFM_CSU_BASE+0x01C*4) +#define PETRFM_CSU_CMDFIFO1_NUM (PETRFM_CSU_BASE+0x01D*4) +#define PETRFM_CSU_PRICMDVALID0 (PETRFM_CSU_BASE+0x020*4) +#define PETRFM_CSU_PRICMDVALID1 (PETRFM_CSU_BASE+0x021*4) +#define PETRFM_CSU_CMDECODATAL32BIT0 (PETRFM_CSU_BASE+0x024*4) +#define PETRFM_CSU_CMDECODATAL32BIT1 (PETRFM_CSU_BASE+0x025*4) +#define PETRFM_CSU_CMDHIGHDATA (PETRFM_CSU_BASE+0x028*4) +#define PETRFM_CSU_CMDFIFO0 (PETRFM_CSU_BASE+0x02C*4) +#define PETRFM_CSU_CMDFIFO1 (PETRFM_CSU_BASE+0x02D*4) +#define PETRFM_CSU_READYLISTNUM (PETRFM_CSU_BASE+0x030*4) +#define PETRFM_CSU_CMDFIFO0_TAGNUM (PETRFM_CSU_BASE+0x034*4) +#define PETRFM_CSU_CMDFIFO1_TAGNUM (PETRFM_CSU_BASE+0x035*4) +#define PETRFM_CSU_DMASTATUS (PETRFM_CSU_BASE+0x038*4) +#define PETRFM_CSU_CMDSTALL_LISTSTALL (PETRFM_CSU_BASE+0x039*4) +#define PETRFM_CSU_QOUSTATUS (PETRFM_CSU_BASE+0x03A*4) +#define PETRFM_CSU_EVENTINTCLEAR (PETRFM_CSU_BASE+0x03C*4) +#define PETRFM_CSU_MAILBOX_PRIDATAREG0 (PETRFM_CSU_BASE+0x100*4) +#define PETRFM_CSU_MAILBOX_PRIDATAREG1 (PETRFM_CSU_BASE+0x101*4) +#define PETRFM_CSU_MAILBOX_PRIDATAREG2 (PETRFM_CSU_BASE+0x102*4) +#define PETRFM_CSU_MAILBOX_PRIDATAREG3 (PETRFM_CSU_BASE+0x103*4) +#define PETRFM_CSU_MAILBOX_PRIDATAREG4 (PETRFM_CSU_BASE+0x104*4) +#define PETRFM_CSU_MAILBOX_PRIDATAREG5 (PETRFM_CSU_BASE+0x105*4) +#define PETRFM_CSU_MAILBOX_PRIDATAREG6 (PETRFM_CSU_BASE+0x106*4) +#define PETRFM_CSU_MAILBOX_PRIDATAREG7 (PETRFM_CSU_BASE+0x107*4) +#define PETRFM_CSU_MAILBOX_PRIDATAREG8 (PETRFM_CSU_BASE+0x108*4) +#define PETRFM_CSU_MAILBOX_PRIDATAREG9 (PETRFM_CSU_BASE+0x109*4) +#define PETRFM_CSU_MAILBOX_PRIDATAREG10 (PETRFM_CSU_BASE+0x10A*4) +#define PETRFM_CSU_MAILBOX_PRIDATAREG11 (PETRFM_CSU_BASE+0x10B*4) +#define PETRFM_CSU_MAILBOX_PRIDATAREG12 (PETRFM_CSU_BASE+0x10C*4) +#define PETRFM_CSU_MAILBOX_PRIDATAREG13 (PETRFM_CSU_BASE+0x10D*4) +#define PETRFM_CSU_MAILBOX_PRIDATAREG14 (PETRFM_CSU_BASE+0x10E*4) +#define PETRFM_CSU_MAILBOX_PRIDATAREG15 (PETRFM_CSU_BASE+0x10F*4) +#define PETRFM_CSU_MAILBOX_BASENUM (PETRFM_CSU_BASE+0x120*4) +#define PETRFM_CSU_MAILBOX_BASECNT (PETRFM_CSU_BASE+0x121*4) +#define PETRFM_CSU_MAILBOX_VALIDREG (PETRFM_CSU_BASE+0x122*4) +#define PETRFM_CSU_MAILBOX_INTMASK0 (PETRFM_CSU_BASE+0x124*4) +#define PETRFM_CSU_MAILBOX_INTMASK1 (PETRFM_CSU_BASE+0x125*4) +#define PETRFM_CSU_MAILBOX_INTMASK2 (PETRFM_CSU_BASE+0x126*4) +#define PETRFM_CSU_MAILBOX_INTMASK3 (PETRFM_CSU_BASE+0x127*4) +#define PETRFM_CSU_MAILBOX_EVENTMASK0 (PETRFM_CSU_BASE+0x130*4) +#define PETRFM_CSU_MAILBOX_EVENTMASK1 (PETRFM_CSU_BASE+0x131*4) +#define PETRFM_CSU_MAILBOX_CNTREG0 (PETRFM_CSU_BASE+0x180*4) +#define PETRFM_CSU_MAILBOX_CNTREG1 (PETRFM_CSU_BASE+0x181*4) +#define PETRFM_CSU_MAILBOX_CNTREG2 (PETRFM_CSU_BASE+0x182*4) +#define PETRFM_CSU_MAILBOX_CNTREG3 (PETRFM_CSU_BASE+0x183*4) +#define PETRFM_CSU_MAILBOX_CNTREG4 (PETRFM_CSU_BASE+0x184*4) +#define PETRFM_CSU_MAILBOX_CNTREG5 (PETRFM_CSU_BASE+0x185*4) +#define PETRFM_CSU_MAILBOX_CNTREG6 (PETRFM_CSU_BASE+0x186*4) +#define PETRFM_CSU_MAILBOX_CNTREG7 (PETRFM_CSU_BASE+0x187*4) +#define PETRFM_CSU_MAILBOX_CNTREG8 (PETRFM_CSU_BASE+0x188*4) +#define PETRFM_CSU_MAILBOX_CNTREG9 (PETRFM_CSU_BASE+0x189*4) +#define PETRFM_CSU_MAILBOX_CNTREG10 (PETRFM_CSU_BASE+0x18A*4) +#define PETRFM_CSU_MAILBOX_CNTREG11 (PETRFM_CSU_BASE+0x18B*4) +#define PETRFM_CSU_MAILBOX_CNTREG12 (PETRFM_CSU_BASE+0x18C*4) +#define PETRFM_CSU_MAILBOX_CNTREG13 (PETRFM_CSU_BASE+0x18D*4) +#define PETRFM_CSU_MAILBOX_CNTREG14 (PETRFM_CSU_BASE+0x18E*4) +#define PETRFM_CSU_MAILBOX_CNTREG15 (PETRFM_CSU_BASE+0x18F*4) +#define PETRFM_CSU_DMAADDRL0 (PETRFM_CSU_BASE+0x200*4) +#define PETRFM_CSU_DMAADDRH0 (PETRFM_CSU_BASE+0x201*4) +#define PETRFM_CSU_DMAYSTEPL0 (PETRFM_CSU_BASE+0x202*4) +#define PETRFM_CSU_DMAYSTEPH0 (PETRFM_CSU_BASE+0x203*4) +#define PETRFM_CSU_DMAZSTEPL0 (PETRFM_CSU_BASE+0x204*4) +#define PETRFM_CSU_DMAZSTEPH0 (PETRFM_CSU_BASE+0x205*4) +#define PETRFM_CSU_DMAYNUMXNUM0 (PETRFM_CSU_BASE+0x206*4) +#define PETRFM_CSU_DMASIZEGRANALLNUM0 (PETRFM_CSU_BASE+0x207*4) +#define PETRFM_CSU_DMAADDRL1 (PETRFM_CSU_BASE+0x208*4) +#define PETRFM_CSU_DMAADDRH1 (PETRFM_CSU_BASE+0x209*4) +#define PETRFM_CSU_DMAYSTEPL1 (PETRFM_CSU_BASE+0x20A*4) +#define PETRFM_CSU_DMAYSTEPH1 (PETRFM_CSU_BASE+0x20B*4) +#define PETRFM_CSU_DMAZSTEPL1 (PETRFM_CSU_BASE+0x20C*4) +#define PETRFM_CSU_DMAZSTEPH1 (PETRFM_CSU_BASE+0x20D*4) +#define PETRFM_CSU_DMAYNUMXNUM1 (PETRFM_CSU_BASE+0x20E*4) +#define PETRFM_CSU_DMASIZEGRANALLNUM1 (PETRFM_CSU_BASE+0x20F*4) +#define PETRFM_CSU_DMAADDRL2 (PETRFM_CSU_BASE+0x210*4) +#define PETRFM_CSU_DMAADDRH2 (PETRFM_CSU_BASE+0x211*4) +#define PETRFM_CSU_DMAYSTEPL2 (PETRFM_CSU_BASE+0x212*4) +#define PETRFM_CSU_DMAYSTEPH2 (PETRFM_CSU_BASE+0x213*4) +#define PETRFM_CSU_DMAZSTEPL2 (PETRFM_CSU_BASE+0x214*4) +#define PETRFM_CSU_DMAZSTEPH2 (PETRFM_CSU_BASE+0x215*4) +#define PETRFM_CSU_DMAYNUMXNUM2 (PETRFM_CSU_BASE+0x216*4) +#define PETRFM_CSU_DMASIZEGRANALLNUM2 (PETRFM_CSU_BASE+0x217*4) +#define PETRFM_CSU_DMAADDRL3 (PETRFM_CSU_BASE+0x218*4) +#define PETRFM_CSU_DMAADDRH3 (PETRFM_CSU_BASE+0x219*4) +#define PETRFM_CSU_DMAYSTEPL3 (PETRFM_CSU_BASE+0x21A*4) +#define PETRFM_CSU_DMAYSTEPH3 (PETRFM_CSU_BASE+0x21B*4) +#define PETRFM_CSU_DMAZSTEPL3 (PETRFM_CSU_BASE+0x21C*4) +#define PETRFM_CSU_DMAZSTEPH3 (PETRFM_CSU_BASE+0x21D*4) +#define PETRFM_CSU_DMAYNUMXNUM3 (PETRFM_CSU_BASE+0x21E*4) +#define PETRFM_CSU_DMASIZEGRANALLNUM3 (PETRFM_CSU_BASE+0x21F*4) +#define PETRFM_CSU_DMAADDRL4 (PETRFM_CSU_BASE+0x220*4) +#define PETRFM_CSU_DMAADDRH4 (PETRFM_CSU_BASE+0x221*4) +#define PETRFM_CSU_DMAYSTEPL4 (PETRFM_CSU_BASE+0x222*4) +#define PETRFM_CSU_DMAYSTEPH4 (PETRFM_CSU_BASE+0x223*4) +#define PETRFM_CSU_DMAZSTEPL4 (PETRFM_CSU_BASE+0x224*4) +#define PETRFM_CSU_DMAZSTEPH4 (PETRFM_CSU_BASE+0x225*4) +#define PETRFM_CSU_DMAYNUMXNUM4 (PETRFM_CSU_BASE+0x226*4) +#define PETRFM_CSU_DMASIZEGRANALLNUM4 (PETRFM_CSU_BASE+0x227*4) +#define PETRFM_CSU_DMAADDRL5 (PETRFM_CSU_BASE+0x228*4) +#define PETRFM_CSU_DMAADDRH5 (PETRFM_CSU_BASE+0x229*4) +#define PETRFM_CSU_DMAYSTEPL5 (PETRFM_CSU_BASE+0x22A*4) +#define PETRFM_CSU_DMAYSTEPH5 (PETRFM_CSU_BASE+0x22B*4) +#define PETRFM_CSU_DMAZSTEPL5 (PETRFM_CSU_BASE+0x22C*4) +#define PETRFM_CSU_DMAZSTEPH5 (PETRFM_CSU_BASE+0x22D*4) +#define PETRFM_CSU_DMAYNUMXNUM5 (PETRFM_CSU_BASE+0x22E*4) +#define PETRFM_CSU_DMASIZEGRANALLNUM5 (PETRFM_CSU_BASE+0x22F*4) +#define PETRFM_CSU_DMAADDRL6 (PETRFM_CSU_BASE+0x230*4) +#define PETRFM_CSU_DMAADDRH6 (PETRFM_CSU_BASE+0x231*4) +#define PETRFM_CSU_DMAYSTEPL6 (PETRFM_CSU_BASE+0x232*4) +#define PETRFM_CSU_DMAYSTEPH6 (PETRFM_CSU_BASE+0x233*4) +#define PETRFM_CSU_DMAZSTEPL6 (PETRFM_CSU_BASE+0x234*4) +#define PETRFM_CSU_DMAZSTEPH6 (PETRFM_CSU_BASE+0x235*4) +#define PETRFM_CSU_DMAYNUMXNUM6 (PETRFM_CSU_BASE+0x236*4) +#define PETRFM_CSU_DMASIZEGRANALLNUM6 (PETRFM_CSU_BASE+0x237*4) +#define PETRFM_CSU_DMAADDRL7 (PETRFM_CSU_BASE+0x238*4) +#define PETRFM_CSU_DMAADDRH7 (PETRFM_CSU_BASE+0x239*4) +#define PETRFM_CSU_DMAYSTEPL7 (PETRFM_CSU_BASE+0x23A*4) +#define PETRFM_CSU_DMAYSTEPH7 (PETRFM_CSU_BASE+0x23B*4) +#define PETRFM_CSU_DMAZSTEPL7 (PETRFM_CSU_BASE+0x23C*4) +#define PETRFM_CSU_DMAZSTEPH7 (PETRFM_CSU_BASE+0x23D*4) +#define PETRFM_CSU_DMAYNUMXNUM7 (PETRFM_CSU_BASE+0x23E*4) +#define PETRFM_CSU_DMASIZEGRANALLNUM7 (PETRFM_CSU_BASE+0x23F*4) +#define PETRFM_CSU_DMAADDRL8 (PETRFM_CSU_BASE+0x240*4) +#define PETRFM_CSU_DMAADDRH8 (PETRFM_CSU_BASE+0x241*4) +#define PETRFM_CSU_DMAYSTEPL8 (PETRFM_CSU_BASE+0x242*4) +#define PETRFM_CSU_DMAYSTEPH8 (PETRFM_CSU_BASE+0x243*4) +#define PETRFM_CSU_DMAZSTEPL8 (PETRFM_CSU_BASE+0x244*4) +#define PETRFM_CSU_DMAZSTEPH8 (PETRFM_CSU_BASE+0x245*4) +#define PETRFM_CSU_DMAYNUMXNUM8 (PETRFM_CSU_BASE+0x246*4) +#define PETRFM_CSU_DMASIZEGRANALLNUM8 (PETRFM_CSU_BASE+0x247*4) +#define PETRFM_CSU_DMAADDRL9 (PETRFM_CSU_BASE+0x248*4) +#define PETRFM_CSU_DMAADDRH9 (PETRFM_CSU_BASE+0x249*4) +#define PETRFM_CSU_DMAYSTEPL9 (PETRFM_CSU_BASE+0x24A*4) +#define PETRFM_CSU_DMAYSTEPH9 (PETRFM_CSU_BASE+0x24B*4) +#define PETRFM_CSU_DMAZSTEPL9 (PETRFM_CSU_BASE+0x24C*4) +#define PETRFM_CSU_DMAZSTEPH9 (PETRFM_CSU_BASE+0x24D*4) +#define PETRFM_CSU_DMAYNUMXNUM9 (PETRFM_CSU_BASE+0x24E*4) +#define PETRFM_CSU_DMASIZEGRANALLNUM9 (PETRFM_CSU_BASE+0x24F*4) +#define PETRFM_CSU_DMAADDRL10 (PETRFM_CSU_BASE+0x250*4) +#define PETRFM_CSU_DMAADDRH10 (PETRFM_CSU_BASE+0x251*4) +#define PETRFM_CSU_DMAYSTEPL10 (PETRFM_CSU_BASE+0x252*4) +#define PETRFM_CSU_DMAYSTEPH10 (PETRFM_CSU_BASE+0x253*4) +#define PETRFM_CSU_DMAZSTEPL10 (PETRFM_CSU_BASE+0x254*4) +#define PETRFM_CSU_DMAZSTEPH10 (PETRFM_CSU_BASE+0x255*4) +#define PETRFM_CSU_DMAYNUMXNUM10 (PETRFM_CSU_BASE+0x256*4) +#define PETRFM_CSU_DMASIZEGRANALLNUM10 (PETRFM_CSU_BASE+0x257*4) +#define PETRFM_CSU_DMAADDRL11 (PETRFM_CSU_BASE+0x258*4) +#define PETRFM_CSU_DMAADDRH11 (PETRFM_CSU_BASE+0x259*4) +#define PETRFM_CSU_DMAYSTEPL11 (PETRFM_CSU_BASE+0x25A*4) +#define PETRFM_CSU_DMAYSTEPH11 (PETRFM_CSU_BASE+0x25B*4) +#define PETRFM_CSU_DMAZSTEPL11 (PETRFM_CSU_BASE+0x25C*4) +#define PETRFM_CSU_DMAZSTEPH11 (PETRFM_CSU_BASE+0x25D*4) +#define PETRFM_CSU_DMAYNUMXNUM11 (PETRFM_CSU_BASE+0x25E*4) +#define PETRFM_CSU_DMASIZEGRANALLNUM11 (PETRFM_CSU_BASE+0x25F*4) +#define PETRFM_CSU_DMAADDRL12 (PETRFM_CSU_BASE+0x260*4) +#define PETRFM_CSU_DMAADDRH12 (PETRFM_CSU_BASE+0x261*4) +#define PETRFM_CSU_DMAYSTEPL12 (PETRFM_CSU_BASE+0x262*4) +#define PETRFM_CSU_DMAYSTEPH12 (PETRFM_CSU_BASE+0x263*4) +#define PETRFM_CSU_DMAZSTEPL12 (PETRFM_CSU_BASE+0x264*4) +#define PETRFM_CSU_DMAZSTEPH12 (PETRFM_CSU_BASE+0x265*4) +#define PETRFM_CSU_DMAYNUMXNUM12 (PETRFM_CSU_BASE+0x266*4) +#define PETRFM_CSU_DMASIZEGRANALLNUM12 (PETRFM_CSU_BASE+0x267*4) +#define PETRFM_CSU_DMAADDRL13 (PETRFM_CSU_BASE+0x268*4) +#define PETRFM_CSU_DMAADDRH13 (PETRFM_CSU_BASE+0x269*4) +#define PETRFM_CSU_DMAYSTEPL13 (PETRFM_CSU_BASE+0x26A*4) +#define PETRFM_CSU_DMAYSTEPH13 (PETRFM_CSU_BASE+0x26B*4) +#define PETRFM_CSU_DMAZSTEPL13 (PETRFM_CSU_BASE+0x26C*4) +#define PETRFM_CSU_DMAZSTEPH13 (PETRFM_CSU_BASE+0x26D*4) +#define PETRFM_CSU_DMAYNUMXNUM13 (PETRFM_CSU_BASE+0x26E*4) +#define PETRFM_CSU_DMASIZEGRANALLNUM13 (PETRFM_CSU_BASE+0x26F*4) +#define PETRFM_CSU_DMAADDRL14 (PETRFM_CSU_BASE+0x270*4) +#define PETRFM_CSU_DMAADDRH14 (PETRFM_CSU_BASE+0x271*4) +#define PETRFM_CSU_DMAYSTEPL14 (PETRFM_CSU_BASE+0x272*4) +#define PETRFM_CSU_DMAYSTEPH14 (PETRFM_CSU_BASE+0x273*4) +#define PETRFM_CSU_DMAZSTEPL14 (PETRFM_CSU_BASE+0x274*4) +#define PETRFM_CSU_DMAZSTEPH14 (PETRFM_CSU_BASE+0x275*4) +#define PETRFM_CSU_DMAYNUMXNUM14 (PETRFM_CSU_BASE+0x276*4) +#define PETRFM_CSU_DMASIZEGRANALLNUM14 (PETRFM_CSU_BASE+0x277*4) +#define PETRFM_CSU_DMAADDRL15 (PETRFM_CSU_BASE+0x278*4) +#define PETRFM_CSU_DMAADDRH15 (PETRFM_CSU_BASE+0x279*4) +#define PETRFM_CSU_DMAYSTEPL15 (PETRFM_CSU_BASE+0x27A*4) +#define PETRFM_CSU_DMAYSTEPH15 (PETRFM_CSU_BASE+0x27B*4) +#define PETRFM_CSU_DMAZSTEPL15 (PETRFM_CSU_BASE+0x27C*4) +#define PETRFM_CSU_DMAZSTEPH15 (PETRFM_CSU_BASE+0x27D*4) +#define PETRFM_CSU_DMAYNUMXNUM15 (PETRFM_CSU_BASE+0x27E*4) +#define PETRFM_CSU_DMASIZEGRANALLNUM15 (PETRFM_CSU_BASE+0x27F*4) +#define PETRFM_CSU_QOUCMDNUM_QOUCMDPOS (PETRFM_CSU_BASE+0x300*4) +#define PETRFM_CSU_QOUCMDADDR (PETRFM_CSU_BASE+0x301*4) +#define PETRFM_CSU_QOUCMDDATA (PETRFM_CSU_BASE+0x302*4) +#define PETRFM_CSU_QOUSTATUSPOPDATA (PETRFM_CSU_BASE+0x303*4) +#define PETRFM_CSU_QOUCMPDATA0 (PETRFM_CSU_BASE+0x304*4) +#define PETRFM_CSU_QOUCMPDATA1 (PETRFM_CSU_BASE+0x305*4) +#define PETRFM_CSU_QOUCMPDATA2 (PETRFM_CSU_BASE+0x306*4) +#define PETRFM_CSU_QOUCMPDATA3 (PETRFM_CSU_BASE+0x307*4) +#define PETRFM_CSU_SPUID (PETRFM_CSU_BASE+0x30B*4) +#define PETRFM_CSU_PRICMDDATA_L32BIT0 (PETRFM_CSU_BASE+0x310*4) +#define PETRFM_CSU_PRICMDDATA_H14BIT0 (PETRFM_CSU_BASE+0x311*4) +#define PETRFM_CSU_PRICMDDATA_L32BIT1 (PETRFM_CSU_BASE+0x312*4) +#define PETRFM_CSU_PRICMDDATA_H14BIT1 (PETRFM_CSU_BASE+0x313*4) +#define PETRFM_CSU_PRICMDDATA_L32BIT2 (PETRFM_CSU_BASE+0x314*4) +#define PETRFM_CSU_PRICMDDATA_H14BIT2 (PETRFM_CSU_BASE+0x315*4) +#define PETRFM_CSU_PRICMDDATA_L32BIT3 (PETRFM_CSU_BASE+0x316*4) +#define PETRFM_CSU_PRICMDDATA_H14BIT3 (PETRFM_CSU_BASE+0x317*4) +#define PETRFM_CSU_SORTDATA_NUM (PETRFM_CSU_BASE+0x380*4) +#define PETRFM_CSU_SORTDATA_DATA0 (PETRFM_CSU_BASE+0x3C0*4) +#define PETRFM_CSU_SORTDATA_DATA1 (PETRFM_CSU_BASE+0x3C1*4) +#define PETRFM_CSU_SORTDATA_DATA2 (PETRFM_CSU_BASE+0x3C2*4) +#define PETRFM_CSU_SORTDATA_DATA3 (PETRFM_CSU_BASE+0x3C3*4) +#define PETRFM_CSU_SORTDATA_DATA4 (PETRFM_CSU_BASE+0x3C4*4) +#define PETRFM_CSU_SORTDATA_DATA5 (PETRFM_CSU_BASE+0x3C5*4) +#define PETRFM_CSU_SORTDATA_DATA6 (PETRFM_CSU_BASE+0x3C6*4) +#define PETRFM_CSU_SORTDATA_DATA7 (PETRFM_CSU_BASE+0x3C7*4) +#define PETRFM_CSU_SORTDATA_DATA8 (PETRFM_CSU_BASE+0x3C8*4) +#define PETRFM_CSU_SORTDATA_DATA9 (PETRFM_CSU_BASE+0x3C9*4) +#define PETRFM_CSU_SORTDATA_DATA10 (PETRFM_CSU_BASE+0x3CA*4) +#define PETRFM_CSU_SORTDATA_DATA11 (PETRFM_CSU_BASE+0x3CB*4) +#define PETRFM_CSU_SORTDATA_DATA12 (PETRFM_CSU_BASE+0x3CC*4) +#define PETRFM_CSU_SORTDATA_DATA13 (PETRFM_CSU_BASE+0x3CD*4) +#define PETRFM_CSU_SORTDATA_DATA14 (PETRFM_CSU_BASE+0x3CE*4) +#define PETRFM_CSU_SORTDATA_DATA15 (PETRFM_CSU_BASE+0x3CF*4) +#define PETRFM_CSU_SORTDATA_DATA16 (PETRFM_CSU_BASE+0x3D0*4) +#define PETRFM_CSU_SORTDATA_DATA17 (PETRFM_CSU_BASE+0x3D1*4) +#define PETRFM_CSU_SORTDATA_DATA18 (PETRFM_CSU_BASE+0x3D2*4) +#define PETRFM_CSU_SORTDATA_DATA19 (PETRFM_CSU_BASE+0x3D3*4) +#define PETRFM_CSU_SORTDATA_DATA20 (PETRFM_CSU_BASE+0x3D4*4) +#define PETRFM_CSU_SORTDATA_DATA21 (PETRFM_CSU_BASE+0x3D5*4) +#define PETRFM_CSU_SORTDATA_DATA22 (PETRFM_CSU_BASE+0x3D6*4) +#define PETRFM_CSU_SORTDATA_DATA23 (PETRFM_CSU_BASE+0x3D7*4) +#define PETRFM_CSU_SORTDATA_DATA24 (PETRFM_CSU_BASE+0x3D8*4) +#define PETRFM_CSU_SORTDATA_DATA25 (PETRFM_CSU_BASE+0x3D9*4) +#define PETRFM_CSU_SORTDATA_DATA26 (PETRFM_CSU_BASE+0x3DA*4) +#define PETRFM_CSU_SORTDATA_DATA27 (PETRFM_CSU_BASE+0x3DB*4) +#define PETRFM_CSU_SORTDATA_DATA28 (PETRFM_CSU_BASE+0x3DC*4) +#define PETRFM_CSU_SORTDATA_DATA29 (PETRFM_CSU_BASE+0x3DD*4) +#define PETRFM_CSU_SORTDATA_DATA30 (PETRFM_CSU_BASE+0x3DE*4) +#define PETRFM_CSU_SORTDATA_DATA31 (PETRFM_CSU_BASE+0x3DF*4) +#define PETRFM_CSU_SORTDATA_ID0 (PETRFM_CSU_BASE+0x3E0*4) +#define PETRFM_CSU_SORTDATA_ID1 (PETRFM_CSU_BASE+0x3E1*4) +#define PETRFM_CSU_SORTDATA_ID2 (PETRFM_CSU_BASE+0x3E2*4) +#define PETRFM_CSU_SORTDATA_ID3 (PETRFM_CSU_BASE+0x3E3*4) +#define PETRFM_CSU_SORTDATA_ID4 (PETRFM_CSU_BASE+0x3E4*4) +#define PETRFM_CSU_SORTDATA_ID5 (PETRFM_CSU_BASE+0x3E5*4) +#define PETRFM_CSU_SORTDATA_ID6 (PETRFM_CSU_BASE+0x3E6*4) +#define PETRFM_CSU_SORTDATA_ID7 (PETRFM_CSU_BASE+0x3E7*4) +#define PETRFM_CSU_SORTDATA_ID8 (PETRFM_CSU_BASE+0x3E8*4) +#define PETRFM_CSU_SORTDATA_ID9 (PETRFM_CSU_BASE+0x3E9*4) +#define PETRFM_CSU_SORTDATA_ID10 (PETRFM_CSU_BASE+0x3EA*4) +#define PETRFM_CSU_SORTDATA_ID11 (PETRFM_CSU_BASE+0x3EB*4) +#define PETRFM_CSU_SORTDATA_ID12 (PETRFM_CSU_BASE+0x3EC*4) +#define PETRFM_CSU_SORTDATA_ID13 (PETRFM_CSU_BASE+0x3ED*4) +#define PETRFM_CSU_SORTDATA_ID14 (PETRFM_CSU_BASE+0x3EE*4) +#define PETRFM_CSU_SORTDATA_ID15 (PETRFM_CSU_BASE+0x3EF*4) +#define PETRFM_CSU_SORTDATA_ID16 (PETRFM_CSU_BASE+0x3F0*4) +#define PETRFM_CSU_SORTDATA_ID17 (PETRFM_CSU_BASE+0x3F1*4) +#define PETRFM_CSU_SORTDATA_ID18 (PETRFM_CSU_BASE+0x3F2*4) +#define PETRFM_CSU_SORTDATA_ID19 (PETRFM_CSU_BASE+0x3F3*4) +#define PETRFM_CSU_SORTDATA_ID20 (PETRFM_CSU_BASE+0x3F4*4) +#define PETRFM_CSU_SORTDATA_ID21 (PETRFM_CSU_BASE+0x3F5*4) +#define PETRFM_CSU_SORTDATA_ID22 (PETRFM_CSU_BASE+0x3F6*4) +#define PETRFM_CSU_SORTDATA_ID23 (PETRFM_CSU_BASE+0x3F7*4) +#define PETRFM_CSU_SORTDATA_ID24 (PETRFM_CSU_BASE+0x3F8*4) +#define PETRFM_CSU_SORTDATA_ID25 (PETRFM_CSU_BASE+0x3F9*4) +#define PETRFM_CSU_SORTDATA_ID26 (PETRFM_CSU_BASE+0x3FA*4) +#define PETRFM_CSU_SORTDATA_ID27 (PETRFM_CSU_BASE+0x3FB*4) +#define PETRFM_CSU_SORTDATA_ID28 (PETRFM_CSU_BASE+0x3FC*4) +#define PETRFM_CSU_SORTDATA_ID29 (PETRFM_CSU_BASE+0x3FD*4) +#define PETRFM_CSU_SORTDATA_ID30 (PETRFM_CSU_BASE+0x3FE*4) +#define PETRFM_CSU_SORTDATA_ID31 (PETRFM_CSU_BASE+0x3FF*4) + + +#define AP_CSU_ALLPENDEVENTMASK (AP_CSU_BASE+0x000*4) +#define AP_CSU_EVENTMASK (AP_CSU_BASE+0x002*4) +#define AP_CSU_INTMASK (AP_CSU_BASE+0x004*4) +#define AP_CSU_ELEVELMASK (AP_CSU_BASE+0x005*4) +#define AP_CSU_TAGMASK0 (AP_CSU_BASE+0x006*4) +#define AP_CSU_TAGMASK1 (AP_CSU_BASE+0x007*4) +#define AP_CSU_TAGMASK2 (AP_CSU_BASE+0x008*4) +#define AP_CSU_TAGMASK3 (AP_CSU_BASE+0x009*4) +#define AP_CSU_ARMCMDRECV (AP_CSU_BASE+0x00A*4) +#define AP_CSU_FETCHMODE_CACHEMODE (AP_CSU_BASE+0x00B*4) +#define AP_CSU_ALLPENDEVENT0 (AP_CSU_BASE+0x00C*4) +#define AP_CSU_ALLPENDEVENT1 (AP_CSU_BASE+0x00D*4) +#define AP_CSU_EM_BS_SMSEL_PREDATANUM (AP_CSU_BASE+0x010*4) +#define AP_CSU_CACHEINFO_EM_BS_SPURWCACHE_SMSEL_PDNUM (AP_CSU_BASE+0x010*4) +#define AP_CSU_FINDDMATAG (AP_CSU_BASE+0x014*4) +#define AP_CSU_CMDFIFO0_CMD (AP_CSU_BASE+0x018*4) +#define AP_CSU_CMDFIFO1_CMD (AP_CSU_BASE+0x019*4) +#define AP_CSU_CMDFIFO2_CMD (AP_CSU_BASE+0x01A*4) +#define AP_CSU_CMDFIFO3_CMD (AP_CSU_BASE+0x01B*4) +#define AP_CSU_CMDFIFO0_NUM (AP_CSU_BASE+0x01C*4) +#define AP_CSU_CMDFIFO1_NUM (AP_CSU_BASE+0x01D*4) +#define AP_CSU_CMDFIFO2_NUM (AP_CSU_BASE+0x01E*4) +#define AP_CSU_CMDFIFO3_NUM (AP_CSU_BASE+0x01F*4) +#define AP_CSU_PRICMDVALID0 (AP_CSU_BASE+0x020*4) +#define AP_CSU_PRICMDVALID1 (AP_CSU_BASE+0x021*4) +#define AP_CSU_CMDECODATAL32BIT0 (AP_CSU_BASE+0x024*4) +#define AP_CSU_CMDECODATAL32BIT1 (AP_CSU_BASE+0x025*4) +#define AP_CSU_CMDHIGHDATA (AP_CSU_BASE+0x028*4) +#define AP_CSU_CMDFIFO0 (AP_CSU_BASE+0x02C*4) +#define AP_CSU_CMDFIFO1 (AP_CSU_BASE+0x02D*4) +#define AP_CSU_CMDFIFO2 (AP_CSU_BASE+0x02E*4) +#define AP_CSU_CMDFIFO3 (AP_CSU_BASE+0x02F*4) +#define AP_CSU_READYLISTNUM (AP_CSU_BASE+0x030*4) +#define AP_CSU_CMDFIFO0_TAGNUM (AP_CSU_BASE+0x034*4) +#define AP_CSU_CMDFIFO1_TAGNUM (AP_CSU_BASE+0x035*4) +#define AP_CSU_CMDFIFO2_TAGNUM (AP_CSU_BASE+0x036*4) +#define AP_CSU_CMDFIFO3_TAGNUM (AP_CSU_BASE+0x037*4) +#define AP_CSU_DMASTATUS (AP_CSU_BASE+0x038*4) +#define AP_CSU_CMDSTALL_LISTSTALL (AP_CSU_BASE+0x039*4) +#define AP_CSU_QOUSTATUS (AP_CSU_BASE+0x03A*4) +#define AP_CSU_EVENTINTCLEAR (AP_CSU_BASE+0x03C*4) +#define AP_CSU_DMAADDRL0 (AP_CSU_BASE+0x200*4) +#define AP_CSU_DMAADDRH0 (AP_CSU_BASE+0x201*4) +#define AP_CSU_DMAYSTEPL0 (AP_CSU_BASE+0x202*4) +#define AP_CSU_DMAYSTEPH0 (AP_CSU_BASE+0x203*4) +#define AP_CSU_DMAZSTEPL0 (AP_CSU_BASE+0x204*4) +#define AP_CSU_DMAZSTEPH0 (AP_CSU_BASE+0x205*4) +#define AP_CSU_DMAYNUMXNUM0 (AP_CSU_BASE+0x206*4) +#define AP_CSU_DMASIZEGRANALLNUM0 (AP_CSU_BASE+0x207*4) +#define AP_CSU_DMAADDRL1 (AP_CSU_BASE+0x208*4) +#define AP_CSU_DMAADDRH1 (AP_CSU_BASE+0x209*4) +#define AP_CSU_DMAYSTEPL1 (AP_CSU_BASE+0x20A*4) +#define AP_CSU_DMAYSTEPH1 (AP_CSU_BASE+0x20B*4) +#define AP_CSU_DMAZSTEPL1 (AP_CSU_BASE+0x20C*4) +#define AP_CSU_DMAZSTEPH1 (AP_CSU_BASE+0x20D*4) +#define AP_CSU_DMAYNUMXNUM1 (AP_CSU_BASE+0x20E*4) +#define AP_CSU_DMASIZEGRANALLNUM1 (AP_CSU_BASE+0x20F*4) +#define AP_CSU_DMAADDRL2 (AP_CSU_BASE+0x210*4) +#define AP_CSU_DMAADDRH2 (AP_CSU_BASE+0x211*4) +#define AP_CSU_DMAYSTEPL2 (AP_CSU_BASE+0x212*4) +#define AP_CSU_DMAYSTEPH2 (AP_CSU_BASE+0x213*4) +#define AP_CSU_DMAZSTEPL2 (AP_CSU_BASE+0x214*4) +#define AP_CSU_DMAZSTEPH2 (AP_CSU_BASE+0x215*4) +#define AP_CSU_DMAYNUMXNUM2 (AP_CSU_BASE+0x216*4) +#define AP_CSU_DMASIZEGRANALLNUM2 (AP_CSU_BASE+0x217*4) +#define AP_CSU_DMAADDRL3 (AP_CSU_BASE+0x218*4) +#define AP_CSU_DMAADDRH3 (AP_CSU_BASE+0x219*4) +#define AP_CSU_DMAYSTEPL3 (AP_CSU_BASE+0x21A*4) +#define AP_CSU_DMAYSTEPH3 (AP_CSU_BASE+0x21B*4) +#define AP_CSU_DMAZSTEPL3 (AP_CSU_BASE+0x21C*4) +#define AP_CSU_DMAZSTEPH3 (AP_CSU_BASE+0x21D*4) +#define AP_CSU_DMAYNUMXNUM3 (AP_CSU_BASE+0x21E*4) +#define AP_CSU_DMASIZEGRANALLNUM3 (AP_CSU_BASE+0x21F*4) +#define AP_CSU_DMAADDRL4 (AP_CSU_BASE+0x220*4) +#define AP_CSU_DMAADDRH4 (AP_CSU_BASE+0x221*4) +#define AP_CSU_DMAYSTEPL4 (AP_CSU_BASE+0x222*4) +#define AP_CSU_DMAYSTEPH4 (AP_CSU_BASE+0x223*4) +#define AP_CSU_DMAZSTEPL4 (AP_CSU_BASE+0x224*4) +#define AP_CSU_DMAZSTEPH4 (AP_CSU_BASE+0x225*4) +#define AP_CSU_DMAYNUMXNUM4 (AP_CSU_BASE+0x226*4) +#define AP_CSU_DMASIZEGRANALLNUM4 (AP_CSU_BASE+0x227*4) +#define AP_CSU_DMAADDRL5 (AP_CSU_BASE+0x228*4) +#define AP_CSU_DMAADDRH5 (AP_CSU_BASE+0x229*4) +#define AP_CSU_DMAYSTEPL5 (AP_CSU_BASE+0x22A*4) +#define AP_CSU_DMAYSTEPH5 (AP_CSU_BASE+0x22B*4) +#define AP_CSU_DMAZSTEPL5 (AP_CSU_BASE+0x22C*4) +#define AP_CSU_DMAZSTEPH5 (AP_CSU_BASE+0x22D*4) +#define AP_CSU_DMAYNUMXNUM5 (AP_CSU_BASE+0x22E*4) +#define AP_CSU_DMASIZEGRANALLNUM5 (AP_CSU_BASE+0x22F*4) +#define AP_CSU_DMAADDRL6 (AP_CSU_BASE+0x230*4) +#define AP_CSU_DMAADDRH6 (AP_CSU_BASE+0x231*4) +#define AP_CSU_DMAYSTEPL6 (AP_CSU_BASE+0x232*4) +#define AP_CSU_DMAYSTEPH6 (AP_CSU_BASE+0x233*4) +#define AP_CSU_DMAZSTEPL6 (AP_CSU_BASE+0x234*4) +#define AP_CSU_DMAZSTEPH6 (AP_CSU_BASE+0x235*4) +#define AP_CSU_DMAYNUMXNUM6 (AP_CSU_BASE+0x236*4) +#define AP_CSU_DMASIZEGRANALLNUM6 (AP_CSU_BASE+0x237*4) +#define AP_CSU_DMAADDRL7 (AP_CSU_BASE+0x238*4) +#define AP_CSU_DMAADDRH7 (AP_CSU_BASE+0x239*4) +#define AP_CSU_DMAYSTEPL7 (AP_CSU_BASE+0x23A*4) +#define AP_CSU_DMAYSTEPH7 (AP_CSU_BASE+0x23B*4) +#define AP_CSU_DMAZSTEPL7 (AP_CSU_BASE+0x23C*4) +#define AP_CSU_DMAZSTEPH7 (AP_CSU_BASE+0x23D*4) +#define AP_CSU_DMAYNUMXNUM7 (AP_CSU_BASE+0x23E*4) +#define AP_CSU_DMASIZEGRANALLNUM7 (AP_CSU_BASE+0x23F*4) +#define AP_CSU_DMAADDRL8 (AP_CSU_BASE+0x240*4) +#define AP_CSU_DMAADDRH8 (AP_CSU_BASE+0x241*4) +#define AP_CSU_DMAYSTEPL8 (AP_CSU_BASE+0x242*4) +#define AP_CSU_DMAYSTEPH8 (AP_CSU_BASE+0x243*4) +#define AP_CSU_DMAZSTEPL8 (AP_CSU_BASE+0x244*4) +#define AP_CSU_DMAZSTEPH8 (AP_CSU_BASE+0x245*4) +#define AP_CSU_DMAYNUMXNUM8 (AP_CSU_BASE+0x246*4) +#define AP_CSU_DMASIZEGRANALLNUM8 (AP_CSU_BASE+0x247*4) +#define AP_CSU_DMAADDRL9 (AP_CSU_BASE+0x248*4) +#define AP_CSU_DMAADDRH9 (AP_CSU_BASE+0x249*4) +#define AP_CSU_DMAYSTEPL9 (AP_CSU_BASE+0x24A*4) +#define AP_CSU_DMAYSTEPH9 (AP_CSU_BASE+0x24B*4) +#define AP_CSU_DMAZSTEPL9 (AP_CSU_BASE+0x24C*4) +#define AP_CSU_DMAZSTEPH9 (AP_CSU_BASE+0x24D*4) +#define AP_CSU_DMAYNUMXNUM9 (AP_CSU_BASE+0x24E*4) +#define AP_CSU_DMASIZEGRANALLNUM9 (AP_CSU_BASE+0x24F*4) +#define AP_CSU_DMAADDRL10 (AP_CSU_BASE+0x250*4) +#define AP_CSU_DMAADDRH10 (AP_CSU_BASE+0x251*4) +#define AP_CSU_DMAYSTEPL10 (AP_CSU_BASE+0x252*4) +#define AP_CSU_DMAYSTEPH10 (AP_CSU_BASE+0x253*4) +#define AP_CSU_DMAZSTEPL10 (AP_CSU_BASE+0x254*4) +#define AP_CSU_DMAZSTEPH10 (AP_CSU_BASE+0x255*4) +#define AP_CSU_DMAYNUMXNUM10 (AP_CSU_BASE+0x256*4) +#define AP_CSU_DMASIZEGRANALLNUM10 (AP_CSU_BASE+0x257*4) +#define AP_CSU_DMAADDRL11 (AP_CSU_BASE+0x258*4) +#define AP_CSU_DMAADDRH11 (AP_CSU_BASE+0x259*4) +#define AP_CSU_DMAYSTEPL11 (AP_CSU_BASE+0x25A*4) +#define AP_CSU_DMAYSTEPH11 (AP_CSU_BASE+0x25B*4) +#define AP_CSU_DMAZSTEPL11 (AP_CSU_BASE+0x25C*4) +#define AP_CSU_DMAZSTEPH11 (AP_CSU_BASE+0x25D*4) +#define AP_CSU_DMAYNUMXNUM11 (AP_CSU_BASE+0x25E*4) +#define AP_CSU_DMASIZEGRANALLNUM11 (AP_CSU_BASE+0x25F*4) +#define AP_CSU_DMAADDRL12 (AP_CSU_BASE+0x260*4) +#define AP_CSU_DMAADDRH12 (AP_CSU_BASE+0x261*4) +#define AP_CSU_DMAYSTEPL12 (AP_CSU_BASE+0x262*4) +#define AP_CSU_DMAYSTEPH12 (AP_CSU_BASE+0x263*4) +#define AP_CSU_DMAZSTEPL12 (AP_CSU_BASE+0x264*4) +#define AP_CSU_DMAZSTEPH12 (AP_CSU_BASE+0x265*4) +#define AP_CSU_DMAYNUMXNUM12 (AP_CSU_BASE+0x266*4) +#define AP_CSU_DMASIZEGRANALLNUM12 (AP_CSU_BASE+0x267*4) +#define AP_CSU_DMAADDRL13 (AP_CSU_BASE+0x268*4) +#define AP_CSU_DMAADDRH13 (AP_CSU_BASE+0x269*4) +#define AP_CSU_DMAYSTEPL13 (AP_CSU_BASE+0x26A*4) +#define AP_CSU_DMAYSTEPH13 (AP_CSU_BASE+0x26B*4) +#define AP_CSU_DMAZSTEPL13 (AP_CSU_BASE+0x26C*4) +#define AP_CSU_DMAZSTEPH13 (AP_CSU_BASE+0x26D*4) +#define AP_CSU_DMAYNUMXNUM13 (AP_CSU_BASE+0x26E*4) +#define AP_CSU_DMASIZEGRANALLNUM13 (AP_CSU_BASE+0x26F*4) +#define AP_CSU_DMAADDRL14 (AP_CSU_BASE+0x270*4) +#define AP_CSU_DMAADDRH14 (AP_CSU_BASE+0x271*4) +#define AP_CSU_DMAYSTEPL14 (AP_CSU_BASE+0x272*4) +#define AP_CSU_DMAYSTEPH14 (AP_CSU_BASE+0x273*4) +#define AP_CSU_DMAZSTEPL14 (AP_CSU_BASE+0x274*4) +#define AP_CSU_DMAZSTEPH14 (AP_CSU_BASE+0x275*4) +#define AP_CSU_DMAYNUMXNUM14 (AP_CSU_BASE+0x276*4) +#define AP_CSU_DMASIZEGRANALLNUM14 (AP_CSU_BASE+0x277*4) +#define AP_CSU_DMAADDRL15 (AP_CSU_BASE+0x278*4) +#define AP_CSU_DMAADDRH15 (AP_CSU_BASE+0x279*4) +#define AP_CSU_DMAYSTEPL15 (AP_CSU_BASE+0x27A*4) +#define AP_CSU_DMAYSTEPH15 (AP_CSU_BASE+0x27B*4) +#define AP_CSU_DMAZSTEPL15 (AP_CSU_BASE+0x27C*4) +#define AP_CSU_DMAZSTEPH15 (AP_CSU_BASE+0x27D*4) +#define AP_CSU_DMAYNUMXNUM15 (AP_CSU_BASE+0x27E*4) +#define AP_CSU_DMASIZEGRANALLNUM15 (AP_CSU_BASE+0x27F*4) +#define AP_CSU_QOUCMDNUM_QOUCMDPOS (AP_CSU_BASE+0x300*4) +#define AP_CSU_QOUCMDADDR (AP_CSU_BASE+0x301*4) +#define AP_CSU_QOUCMDDATA (AP_CSU_BASE+0x302*4) +#define AP_CSU_QOUSTATUSPOPDATA (AP_CSU_BASE+0x303*4) +#define AP_CSU_QOUCMPDATA0 (AP_CSU_BASE+0x304*4) +#define AP_CSU_QOUCMPDATA1 (AP_CSU_BASE+0x305*4) +#define AP_CSU_QOUCMPDATA2 (AP_CSU_BASE+0x306*4) +#define AP_CSU_QOUCMPDATA3 (AP_CSU_BASE+0x307*4) +#define AP_CSU_PRICMDDATA_L32BIT0 (AP_CSU_BASE+0x310*4) +#define AP_CSU_PRICMDDATA_H14BIT0 (AP_CSU_BASE+0x311*4) +#define AP_CSU_PRICMDDATA_L32BIT1 (AP_CSU_BASE+0x312*4) +#define AP_CSU_PRICMDDATA_H14BIT1 (AP_CSU_BASE+0x313*4) +#define AP_CSU_PRICMDDATA_L32BIT2 (AP_CSU_BASE+0x314*4) +#define AP_CSU_PRICMDDATA_H14BIT2 (AP_CSU_BASE+0x315*4) +#define AP_CSU_PRICMDDATA_L32BIT3 (AP_CSU_BASE+0x316*4) +#define AP_CSU_PRICMDDATA_H14BIT3 (AP_CSU_BASE+0x317*4) +#define AP_CSU_SORTDATA_NUM (AP_CSU_BASE+0x380*4) +#define AP_CSU_SORTDATA_DATA0 (AP_CSU_BASE+0x3C0*4) +#define AP_CSU_SORTDATA_DATA1 (AP_CSU_BASE+0x3C1*4) +#define AP_CSU_SORTDATA_DATA2 (AP_CSU_BASE+0x3C2*4) +#define AP_CSU_SORTDATA_DATA3 (AP_CSU_BASE+0x3C3*4) +#define AP_CSU_SORTDATA_DATA4 (AP_CSU_BASE+0x3C4*4) +#define AP_CSU_SORTDATA_DATA5 (AP_CSU_BASE+0x3C5*4) +#define AP_CSU_SORTDATA_DATA6 (AP_CSU_BASE+0x3C6*4) +#define AP_CSU_SORTDATA_DATA7 (AP_CSU_BASE+0x3C7*4) +#define AP_CSU_SORTDATA_DATA8 (AP_CSU_BASE+0x3C8*4) +#define AP_CSU_SORTDATA_DATA9 (AP_CSU_BASE+0x3C9*4) +#define AP_CSU_SORTDATA_DATA10 (AP_CSU_BASE+0x3CA*4) +#define AP_CSU_SORTDATA_DATA11 (AP_CSU_BASE+0x3CB*4) +#define AP_CSU_SORTDATA_DATA12 (AP_CSU_BASE+0x3CC*4) +#define AP_CSU_SORTDATA_DATA13 (AP_CSU_BASE+0x3CD*4) +#define AP_CSU_SORTDATA_DATA14 (AP_CSU_BASE+0x3CE*4) +#define AP_CSU_SORTDATA_DATA15 (AP_CSU_BASE+0x3CF*4) +#define AP_CSU_SORTDATA_DATA16 (AP_CSU_BASE+0x3D0*4) +#define AP_CSU_SORTDATA_DATA17 (AP_CSU_BASE+0x3D1*4) +#define AP_CSU_SORTDATA_DATA18 (AP_CSU_BASE+0x3D2*4) +#define AP_CSU_SORTDATA_DATA19 (AP_CSU_BASE+0x3D3*4) +#define AP_CSU_SORTDATA_DATA20 (AP_CSU_BASE+0x3D4*4) +#define AP_CSU_SORTDATA_DATA21 (AP_CSU_BASE+0x3D5*4) +#define AP_CSU_SORTDATA_DATA22 (AP_CSU_BASE+0x3D6*4) +#define AP_CSU_SORTDATA_DATA23 (AP_CSU_BASE+0x3D7*4) +#define AP_CSU_SORTDATA_DATA24 (AP_CSU_BASE+0x3D8*4) +#define AP_CSU_SORTDATA_DATA25 (AP_CSU_BASE+0x3D9*4) +#define AP_CSU_SORTDATA_DATA26 (AP_CSU_BASE+0x3DA*4) +#define AP_CSU_SORTDATA_DATA27 (AP_CSU_BASE+0x3DB*4) +#define AP_CSU_SORTDATA_DATA28 (AP_CSU_BASE+0x3DC*4) +#define AP_CSU_SORTDATA_DATA29 (AP_CSU_BASE+0x3DD*4) +#define AP_CSU_SORTDATA_DATA30 (AP_CSU_BASE+0x3DE*4) +#define AP_CSU_SORTDATA_DATA31 (AP_CSU_BASE+0x3DF*4) +#define AP_CSU_SORTDATA_ID0 (AP_CSU_BASE+0x3E0*4) +#define AP_CSU_SORTDATA_ID1 (AP_CSU_BASE+0x3E1*4) +#define AP_CSU_SORTDATA_ID2 (AP_CSU_BASE+0x3E2*4) +#define AP_CSU_SORTDATA_ID3 (AP_CSU_BASE+0x3E3*4) +#define AP_CSU_SORTDATA_ID4 (AP_CSU_BASE+0x3E4*4) +#define AP_CSU_SORTDATA_ID5 (AP_CSU_BASE+0x3E5*4) +#define AP_CSU_SORTDATA_ID6 (AP_CSU_BASE+0x3E6*4) +#define AP_CSU_SORTDATA_ID7 (AP_CSU_BASE+0x3E7*4) +#define AP_CSU_SORTDATA_ID8 (AP_CSU_BASE+0x3E8*4) +#define AP_CSU_SORTDATA_ID9 (AP_CSU_BASE+0x3E9*4) +#define AP_CSU_SORTDATA_ID10 (AP_CSU_BASE+0x3EA*4) +#define AP_CSU_SORTDATA_ID11 (AP_CSU_BASE+0x3EB*4) +#define AP_CSU_SORTDATA_ID12 (AP_CSU_BASE+0x3EC*4) +#define AP_CSU_SORTDATA_ID13 (AP_CSU_BASE+0x3ED*4) +#define AP_CSU_SORTDATA_ID14 (AP_CSU_BASE+0x3EE*4) +#define AP_CSU_SORTDATA_ID15 (AP_CSU_BASE+0x3EF*4) +#define AP_CSU_SORTDATA_ID16 (AP_CSU_BASE+0x3F0*4) +#define AP_CSU_SORTDATA_ID17 (AP_CSU_BASE+0x3F1*4) +#define AP_CSU_SORTDATA_ID18 (AP_CSU_BASE+0x3F2*4) +#define AP_CSU_SORTDATA_ID19 (AP_CSU_BASE+0x3F3*4) +#define AP_CSU_SORTDATA_ID20 (AP_CSU_BASE+0x3F4*4) +#define AP_CSU_SORTDATA_ID21 (AP_CSU_BASE+0x3F5*4) +#define AP_CSU_SORTDATA_ID22 (AP_CSU_BASE+0x3F6*4) +#define AP_CSU_SORTDATA_ID23 (AP_CSU_BASE+0x3F7*4) +#define AP_CSU_SORTDATA_ID24 (AP_CSU_BASE+0x3F8*4) +#define AP_CSU_SORTDATA_ID25 (AP_CSU_BASE+0x3F9*4) +#define AP_CSU_SORTDATA_ID26 (AP_CSU_BASE+0x3FA*4) +#define AP_CSU_SORTDATA_ID27 (AP_CSU_BASE+0x3FB*4) +#define AP_CSU_SORTDATA_ID28 (AP_CSU_BASE+0x3FC*4) +#define AP_CSU_SORTDATA_ID29 (AP_CSU_BASE+0x3FD*4) +#define AP_CSU_SORTDATA_ID30 (AP_CSU_BASE+0x3FE*4) +#define AP_CSU_SORTDATA_ID31 (AP_CSU_BASE+0x3FF*4) + + +#define RFC_CSU_ALLPENDEVENTMASK (RFC_CSU_BASE+0x000*4) +#define RFC_CSU_EVENTMASK (RFC_CSU_BASE+0x002*4) +#define RFC_CSU_LATCHALFULL (RFC_CSU_BASE+0x003*4) +#define RFC_CSU_INTMASK (RFC_CSU_BASE+0x004*4) +#define RFC_CSU_ELEVELMASK (RFC_CSU_BASE+0x005*4) +#define RFC_CSU_TAGMASK0 (RFC_CSU_BASE+0x006*4) +#define RFC_CSU_TAGMASK1 (RFC_CSU_BASE+0x007*4) +#define RFC_CSU_TAGMASK2 (RFC_CSU_BASE+0x008*4) +#define RFC_CSU_TAGMASK3 (RFC_CSU_BASE+0x009*4) +#define RFC_CSU_ARMCMDRECV (RFC_CSU_BASE+0x00A*4) +#define RFC_CSU_ALLPENDEVENT0 (RFC_CSU_BASE+0x00C*4) +#define RFC_CSU_ALLPENDEVENT1 (RFC_CSU_BASE+0x00D*4) +#define RFC_CSU_EM_BS_SMSEL_PREDATANUM (RFC_CSU_BASE+0x010*4) +#define RFC_CSU_ALMOSTFULLSENDTHRED (RFC_CSU_BASE+0x011*4) +#define RFC_CSU_RFCTXSET (RFC_CSU_BASE+0x012*4) +#define RFC_CSU_RFCRXSET (RFC_CSU_BASE+0x013*4) +#define RFC_CSU_FINDDMATAG (RFC_CSU_BASE+0x014*4) +#define RFC_CSU_CMDFIFO0_CMD (RFC_CSU_BASE+0x018*4) +#define RFC_CSU_CMDFIFO1_CMD (RFC_CSU_BASE+0x019*4) +#define RFC_CSU_CMDFIFO0_NUM (RFC_CSU_BASE+0x01C*4) +#define RFC_CSU_CMDFIFO1_NUM (RFC_CSU_BASE+0x01D*4) +#define RFC_CSU_PRICMDVALID0 (RFC_CSU_BASE+0x020*4) +#define RFC_CSU_PRICMDVALID1 (RFC_CSU_BASE+0x021*4) +#define RFC_CSU_CMDECODATAL32BIT0 (RFC_CSU_BASE+0x024*4) +#define RFC_CSU_CMDECODATAL32BIT1 (RFC_CSU_BASE+0x025*4) +#define RFC_CSU_CMDHIGHDATA (RFC_CSU_BASE+0x028*4) +#define RFC_CSU_CMDFIFO0 (RFC_CSU_BASE+0x02C*4) +#define RFC_CSU_CMDFIFO1 (RFC_CSU_BASE+0x02D*4) +#define RFC_CSU_READYLISTNUM (RFC_CSU_BASE+0x030*4) +#define RFC_CSU_CMDFIFO0_TAGNUM (RFC_CSU_BASE+0x034*4) +#define RFC_CSU_CMDFIFO1_TAGNUM (RFC_CSU_BASE+0x035*4) +#define RFC_CSU_DMASTATUS (RFC_CSU_BASE+0x038*4) +#define RFC_CSU_CMDSTALL_LISTSTALL (RFC_CSU_BASE+0x039*4) +#define RFC_CSU_QOUSTATUS (RFC_CSU_BASE+0x03A*4) +#define RFC_CSU_EVENTINTCLEAR (RFC_CSU_BASE+0x03C*4) +#define RFC_CSU_DMAADDRL0 (RFC_CSU_BASE+0x200*4) +#define RFC_CSU_DMAADDRH0 (RFC_CSU_BASE+0x201*4) +#define RFC_CSU_DMAYSTEPL0 (RFC_CSU_BASE+0x202*4) +#define RFC_CSU_DMAYSTEPH0 (RFC_CSU_BASE+0x203*4) +#define RFC_CSU_DMAZSTEPL0 (RFC_CSU_BASE+0x204*4) +#define RFC_CSU_DMAZSTEPH0 (RFC_CSU_BASE+0x205*4) +#define RFC_CSU_DMAYNUMXNUM0 (RFC_CSU_BASE+0x206*4) +#define RFC_CSU_DMASIZEGRANALLNUM0 (RFC_CSU_BASE+0x207*4) +#define RFC_CSU_DMAADDRL1 (RFC_CSU_BASE+0x208*4) +#define RFC_CSU_DMAADDRH1 (RFC_CSU_BASE+0x209*4) +#define RFC_CSU_DMAYSTEPL1 (RFC_CSU_BASE+0x20A*4) +#define RFC_CSU_DMAYSTEPH1 (RFC_CSU_BASE+0x20B*4) +#define RFC_CSU_DMAZSTEPL1 (RFC_CSU_BASE+0x20C*4) +#define RFC_CSU_DMAZSTEPH1 (RFC_CSU_BASE+0x20D*4) +#define RFC_CSU_DMAYNUMXNUM1 (RFC_CSU_BASE+0x20E*4) +#define RFC_CSU_DMASIZEGRANALLNUM1 (RFC_CSU_BASE+0x20F*4) +#define RFC_CSU_DMAADDRL2 (RFC_CSU_BASE+0x210*4) +#define RFC_CSU_DMAADDRH2 (RFC_CSU_BASE+0x211*4) +#define RFC_CSU_DMAYSTEPL2 (RFC_CSU_BASE+0x212*4) +#define RFC_CSU_DMAYSTEPH2 (RFC_CSU_BASE+0x213*4) +#define RFC_CSU_DMAZSTEPL2 (RFC_CSU_BASE+0x214*4) +#define RFC_CSU_DMAZSTEPH2 (RFC_CSU_BASE+0x215*4) +#define RFC_CSU_DMAYNUMXNUM2 (RFC_CSU_BASE+0x216*4) +#define RFC_CSU_DMASIZEGRANALLNUM2 (RFC_CSU_BASE+0x217*4) +#define RFC_CSU_DMAADDRL3 (RFC_CSU_BASE+0x218*4) +#define RFC_CSU_DMAADDRH3 (RFC_CSU_BASE+0x219*4) +#define RFC_CSU_DMAYSTEPL3 (RFC_CSU_BASE+0x21A*4) +#define RFC_CSU_DMAYSTEPH3 (RFC_CSU_BASE+0x21B*4) +#define RFC_CSU_DMAZSTEPL3 (RFC_CSU_BASE+0x21C*4) +#define RFC_CSU_DMAZSTEPH3 (RFC_CSU_BASE+0x21D*4) +#define RFC_CSU_DMAYNUMXNUM3 (RFC_CSU_BASE+0x21E*4) +#define RFC_CSU_DMASIZEGRANALLNUM3 (RFC_CSU_BASE+0x21F*4) +#define RFC_CSU_DMAADDRL4 (RFC_CSU_BASE+0x220*4) +#define RFC_CSU_DMAADDRH4 (RFC_CSU_BASE+0x221*4) +#define RFC_CSU_DMAYSTEPL4 (RFC_CSU_BASE+0x222*4) +#define RFC_CSU_DMAYSTEPH4 (RFC_CSU_BASE+0x223*4) +#define RFC_CSU_DMAZSTEPL4 (RFC_CSU_BASE+0x224*4) +#define RFC_CSU_DMAZSTEPH4 (RFC_CSU_BASE+0x225*4) +#define RFC_CSU_DMAYNUMXNUM4 (RFC_CSU_BASE+0x226*4) +#define RFC_CSU_DMASIZEGRANALLNUM4 (RFC_CSU_BASE+0x227*4) +#define RFC_CSU_DMAADDRL5 (RFC_CSU_BASE+0x228*4) +#define RFC_CSU_DMAADDRH5 (RFC_CSU_BASE+0x229*4) +#define RFC_CSU_DMAYSTEPL5 (RFC_CSU_BASE+0x22A*4) +#define RFC_CSU_DMAYSTEPH5 (RFC_CSU_BASE+0x22B*4) +#define RFC_CSU_DMAZSTEPL5 (RFC_CSU_BASE+0x22C*4) +#define RFC_CSU_DMAZSTEPH5 (RFC_CSU_BASE+0x22D*4) +#define RFC_CSU_DMAYNUMXNUM5 (RFC_CSU_BASE+0x22E*4) +#define RFC_CSU_DMASIZEGRANALLNUM5 (RFC_CSU_BASE+0x22F*4) +#define RFC_CSU_DMAADDRL6 (RFC_CSU_BASE+0x230*4) +#define RFC_CSU_DMAADDRH6 (RFC_CSU_BASE+0x231*4) +#define RFC_CSU_DMAYSTEPL6 (RFC_CSU_BASE+0x232*4) +#define RFC_CSU_DMAYSTEPH6 (RFC_CSU_BASE+0x233*4) +#define RFC_CSU_DMAZSTEPL6 (RFC_CSU_BASE+0x234*4) +#define RFC_CSU_DMAZSTEPH6 (RFC_CSU_BASE+0x235*4) +#define RFC_CSU_DMAYNUMXNUM6 (RFC_CSU_BASE+0x236*4) +#define RFC_CSU_DMASIZEGRANALLNUM6 (RFC_CSU_BASE+0x237*4) +#define RFC_CSU_DMAADDRL7 (RFC_CSU_BASE+0x238*4) +#define RFC_CSU_DMAADDRH7 (RFC_CSU_BASE+0x239*4) +#define RFC_CSU_DMAYSTEPL7 (RFC_CSU_BASE+0x23A*4) +#define RFC_CSU_DMAYSTEPH7 (RFC_CSU_BASE+0x23B*4) +#define RFC_CSU_DMAZSTEPL7 (RFC_CSU_BASE+0x23C*4) +#define RFC_CSU_DMAZSTEPH7 (RFC_CSU_BASE+0x23D*4) +#define RFC_CSU_DMAYNUMXNUM7 (RFC_CSU_BASE+0x23E*4) +#define RFC_CSU_DMASIZEGRANALLNUM7 (RFC_CSU_BASE+0x23F*4) +#define RFC_CSU_DMAADDRL8 (RFC_CSU_BASE+0x240*4) +#define RFC_CSU_DMAADDRH8 (RFC_CSU_BASE+0x241*4) +#define RFC_CSU_DMAYSTEPL8 (RFC_CSU_BASE+0x242*4) +#define RFC_CSU_DMAYSTEPH8 (RFC_CSU_BASE+0x243*4) +#define RFC_CSU_DMAZSTEPL8 (RFC_CSU_BASE+0x244*4) +#define RFC_CSU_DMAZSTEPH8 (RFC_CSU_BASE+0x245*4) +#define RFC_CSU_DMAYNUMXNUM8 (RFC_CSU_BASE+0x246*4) +#define RFC_CSU_DMASIZEGRANALLNUM8 (RFC_CSU_BASE+0x247*4) +#define RFC_CSU_DMAADDRL9 (RFC_CSU_BASE+0x248*4) +#define RFC_CSU_DMAADDRH9 (RFC_CSU_BASE+0x249*4) +#define RFC_CSU_DMAYSTEPL9 (RFC_CSU_BASE+0x24A*4) +#define RFC_CSU_DMAYSTEPH9 (RFC_CSU_BASE+0x24B*4) +#define RFC_CSU_DMAZSTEPL9 (RFC_CSU_BASE+0x24C*4) +#define RFC_CSU_DMAZSTEPH9 (RFC_CSU_BASE+0x24D*4) +#define RFC_CSU_DMAYNUMXNUM9 (RFC_CSU_BASE+0x24E*4) +#define RFC_CSU_DMASIZEGRANALLNUM9 (RFC_CSU_BASE+0x24F*4) +#define RFC_CSU_DMAADDRL10 (RFC_CSU_BASE+0x250*4) +#define RFC_CSU_DMAADDRH10 (RFC_CSU_BASE+0x251*4) +#define RFC_CSU_DMAYSTEPL10 (RFC_CSU_BASE+0x252*4) +#define RFC_CSU_DMAYSTEPH10 (RFC_CSU_BASE+0x253*4) +#define RFC_CSU_DMAZSTEPL10 (RFC_CSU_BASE+0x254*4) +#define RFC_CSU_DMAZSTEPH10 (RFC_CSU_BASE+0x255*4) +#define RFC_CSU_DMAYNUMXNUM10 (RFC_CSU_BASE+0x256*4) +#define RFC_CSU_DMASIZEGRANALLNUM10 (RFC_CSU_BASE+0x257*4) +#define RFC_CSU_DMAADDRL11 (RFC_CSU_BASE+0x258*4) +#define RFC_CSU_DMAADDRH11 (RFC_CSU_BASE+0x259*4) +#define RFC_CSU_DMAYSTEPL11 (RFC_CSU_BASE+0x25A*4) +#define RFC_CSU_DMAYSTEPH11 (RFC_CSU_BASE+0x25B*4) +#define RFC_CSU_DMAZSTEPL11 (RFC_CSU_BASE+0x25C*4) +#define RFC_CSU_DMAZSTEPH11 (RFC_CSU_BASE+0x25D*4) +#define RFC_CSU_DMAYNUMXNUM11 (RFC_CSU_BASE+0x25E*4) +#define RFC_CSU_DMASIZEGRANALLNUM11 (RFC_CSU_BASE+0x25F*4) +#define RFC_CSU_DMAADDRL12 (RFC_CSU_BASE+0x260*4) +#define RFC_CSU_DMAADDRH12 (RFC_CSU_BASE+0x261*4) +#define RFC_CSU_DMAYSTEPL12 (RFC_CSU_BASE+0x262*4) +#define RFC_CSU_DMAYSTEPH12 (RFC_CSU_BASE+0x263*4) +#define RFC_CSU_DMAZSTEPL12 (RFC_CSU_BASE+0x264*4) +#define RFC_CSU_DMAZSTEPH12 (RFC_CSU_BASE+0x265*4) +#define RFC_CSU_DMAYNUMXNUM12 (RFC_CSU_BASE+0x266*4) +#define RFC_CSU_DMASIZEGRANALLNUM12 (RFC_CSU_BASE+0x267*4) +#define RFC_CSU_DMAADDRL13 (RFC_CSU_BASE+0x268*4) +#define RFC_CSU_DMAADDRH13 (RFC_CSU_BASE+0x269*4) +#define RFC_CSU_DMAYSTEPL13 (RFC_CSU_BASE+0x26A*4) +#define RFC_CSU_DMAYSTEPH13 (RFC_CSU_BASE+0x26B*4) +#define RFC_CSU_DMAZSTEPL13 (RFC_CSU_BASE+0x26C*4) +#define RFC_CSU_DMAZSTEPH13 (RFC_CSU_BASE+0x26D*4) +#define RFC_CSU_DMAYNUMXNUM13 (RFC_CSU_BASE+0x26E*4) +#define RFC_CSU_DMASIZEGRANALLNUM13 (RFC_CSU_BASE+0x26F*4) +#define RFC_CSU_DMAADDRL14 (RFC_CSU_BASE+0x270*4) +#define RFC_CSU_DMAADDRH14 (RFC_CSU_BASE+0x271*4) +#define RFC_CSU_DMAYSTEPL14 (RFC_CSU_BASE+0x272*4) +#define RFC_CSU_DMAYSTEPH14 (RFC_CSU_BASE+0x273*4) +#define RFC_CSU_DMAZSTEPL14 (RFC_CSU_BASE+0x274*4) +#define RFC_CSU_DMAZSTEPH14 (RFC_CSU_BASE+0x275*4) +#define RFC_CSU_DMAYNUMXNUM14 (RFC_CSU_BASE+0x276*4) +#define RFC_CSU_DMASIZEGRANALLNUM14 (RFC_CSU_BASE+0x277*4) +#define RFC_CSU_DMAADDRL15 (RFC_CSU_BASE+0x278*4) +#define RFC_CSU_DMAADDRH15 (RFC_CSU_BASE+0x279*4) +#define RFC_CSU_DMAYSTEPL15 (RFC_CSU_BASE+0x27A*4) +#define RFC_CSU_DMAYSTEPH15 (RFC_CSU_BASE+0x27B*4) +#define RFC_CSU_DMAZSTEPL15 (RFC_CSU_BASE+0x27C*4) +#define RFC_CSU_DMAZSTEPH15 (RFC_CSU_BASE+0x27D*4) +#define RFC_CSU_DMAYNUMXNUM15 (RFC_CSU_BASE+0x27E*4) +#define RFC_CSU_DMASIZEGRANALLNUM15 (RFC_CSU_BASE+0x27F*4) +#define RFC_CSU_QOUCMDNUM_QOUCMDPOS (RFC_CSU_BASE+0x300*4) +#define RFC_CSU_QOUCMDADDR (RFC_CSU_BASE+0x301*4) +#define RFC_CSU_QOUCMDDATA (RFC_CSU_BASE+0x302*4) +#define RFC_CSU_QOUSTATUSPOPDATA (RFC_CSU_BASE+0x303*4) +#define RFC_CSU_QOUCMPDATA0 (RFC_CSU_BASE+0x304*4) +#define RFC_CSU_QOUCMPDATA1 (RFC_CSU_BASE+0x305*4) +#define RFC_CSU_QOUCMPDATA2 (RFC_CSU_BASE+0x306*4) +#define RFC_CSU_PRICMDDATA_L32BIT0 (RFC_CSU_BASE+0x310*4) +#define RFC_CSU_PRICMDDATA_H14BIT0 (RFC_CSU_BASE+0x311*4) +#define RFC_CSU_PRICMDDATA_L32BIT1 (RFC_CSU_BASE+0x312*4) +#define RFC_CSU_PRICMDDATA_H14BIT1 (RFC_CSU_BASE+0x313*4) +#define RFC_CSU_PRICMDDATA_L32BIT2 (RFC_CSU_BASE+0x314*4) +#define RFC_CSU_PRICMDDATA_H14BIT2 (RFC_CSU_BASE+0x315*4) +#define RFC_CSU_SORTDATA_NUM (RFC_CSU_BASE+0x380*4) +#define RFC_CSU_SORTDATA_DATA0 (RFC_CSU_BASE+0x3C0*4) +#define RFC_CSU_SORTDATA_DATA1 (RFC_CSU_BASE+0x3C1*4) +#define RFC_CSU_SORTDATA_DATA2 (RFC_CSU_BASE+0x3C2*4) +#define RFC_CSU_SORTDATA_DATA3 (RFC_CSU_BASE+0x3C3*4) +#define RFC_CSU_SORTDATA_DATA4 (RFC_CSU_BASE+0x3C4*4) +#define RFC_CSU_SORTDATA_DATA5 (RFC_CSU_BASE+0x3C5*4) +#define RFC_CSU_SORTDATA_DATA6 (RFC_CSU_BASE+0x3C6*4) +#define RFC_CSU_SORTDATA_DATA7 (RFC_CSU_BASE+0x3C7*4) +#define RFC_CSU_SORTDATA_DATA8 (RFC_CSU_BASE+0x3C8*4) +#define RFC_CSU_SORTDATA_DATA9 (RFC_CSU_BASE+0x3C9*4) +#define RFC_CSU_SORTDATA_DATA10 (RFC_CSU_BASE+0x3CA*4) +#define RFC_CSU_SORTDATA_DATA11 (RFC_CSU_BASE+0x3CB*4) +#define RFC_CSU_SORTDATA_DATA12 (RFC_CSU_BASE+0x3CC*4) +#define RFC_CSU_SORTDATA_DATA13 (RFC_CSU_BASE+0x3CD*4) +#define RFC_CSU_SORTDATA_DATA14 (RFC_CSU_BASE+0x3CE*4) +#define RFC_CSU_SORTDATA_DATA15 (RFC_CSU_BASE+0x3CF*4) +#define RFC_CSU_SORTDATA_DATA16 (RFC_CSU_BASE+0x3D0*4) +#define RFC_CSU_SORTDATA_DATA17 (RFC_CSU_BASE+0x3D1*4) +#define RFC_CSU_SORTDATA_DATA18 (RFC_CSU_BASE+0x3D2*4) +#define RFC_CSU_SORTDATA_DATA19 (RFC_CSU_BASE+0x3D3*4) +#define RFC_CSU_SORTDATA_DATA20 (RFC_CSU_BASE+0x3D4*4) +#define RFC_CSU_SORTDATA_DATA21 (RFC_CSU_BASE+0x3D5*4) +#define RFC_CSU_SORTDATA_DATA22 (RFC_CSU_BASE+0x3D6*4) +#define RFC_CSU_SORTDATA_DATA23 (RFC_CSU_BASE+0x3D7*4) +#define RFC_CSU_SORTDATA_DATA24 (RFC_CSU_BASE+0x3D8*4) +#define RFC_CSU_SORTDATA_DATA25 (RFC_CSU_BASE+0x3D9*4) +#define RFC_CSU_SORTDATA_DATA26 (RFC_CSU_BASE+0x3DA*4) +#define RFC_CSU_SORTDATA_DATA27 (RFC_CSU_BASE+0x3DB*4) +#define RFC_CSU_SORTDATA_DATA28 (RFC_CSU_BASE+0x3DC*4) +#define RFC_CSU_SORTDATA_DATA29 (RFC_CSU_BASE+0x3DD*4) +#define RFC_CSU_SORTDATA_DATA30 (RFC_CSU_BASE+0x3DE*4) +#define RFC_CSU_SORTDATA_DATA31 (RFC_CSU_BASE+0x3DF*4) +#define RFC_CSU_SORTDATA_ID0 (RFC_CSU_BASE+0x3E0*4) +#define RFC_CSU_SORTDATA_ID1 (RFC_CSU_BASE+0x3E1*4) +#define RFC_CSU_SORTDATA_ID2 (RFC_CSU_BASE+0x3E2*4) +#define RFC_CSU_SORTDATA_ID3 (RFC_CSU_BASE+0x3E3*4) +#define RFC_CSU_SORTDATA_ID4 (RFC_CSU_BASE+0x3E4*4) +#define RFC_CSU_SORTDATA_ID5 (RFC_CSU_BASE+0x3E5*4) +#define RFC_CSU_SORTDATA_ID6 (RFC_CSU_BASE+0x3E6*4) +#define RFC_CSU_SORTDATA_ID7 (RFC_CSU_BASE+0x3E7*4) +#define RFC_CSU_SORTDATA_ID8 (RFC_CSU_BASE+0x3E8*4) +#define RFC_CSU_SORTDATA_ID9 (RFC_CSU_BASE+0x3E9*4) +#define RFC_CSU_SORTDATA_ID10 (RFC_CSU_BASE+0x3EA*4) +#define RFC_CSU_SORTDATA_ID11 (RFC_CSU_BASE+0x3EB*4) +#define RFC_CSU_SORTDATA_ID12 (RFC_CSU_BASE+0x3EC*4) +#define RFC_CSU_SORTDATA_ID13 (RFC_CSU_BASE+0x3ED*4) +#define RFC_CSU_SORTDATA_ID14 (RFC_CSU_BASE+0x3EE*4) +#define RFC_CSU_SORTDATA_ID15 (RFC_CSU_BASE+0x3EF*4) +#define RFC_CSU_SORTDATA_ID16 (RFC_CSU_BASE+0x3F0*4) +#define RFC_CSU_SORTDATA_ID17 (RFC_CSU_BASE+0x3F1*4) +#define RFC_CSU_SORTDATA_ID18 (RFC_CSU_BASE+0x3F2*4) +#define RFC_CSU_SORTDATA_ID19 (RFC_CSU_BASE+0x3F3*4) +#define RFC_CSU_SORTDATA_ID20 (RFC_CSU_BASE+0x3F4*4) +#define RFC_CSU_SORTDATA_ID21 (RFC_CSU_BASE+0x3F5*4) +#define RFC_CSU_SORTDATA_ID22 (RFC_CSU_BASE+0x3F6*4) +#define RFC_CSU_SORTDATA_ID23 (RFC_CSU_BASE+0x3F7*4) +#define RFC_CSU_SORTDATA_ID24 (RFC_CSU_BASE+0x3F8*4) +#define RFC_CSU_SORTDATA_ID25 (RFC_CSU_BASE+0x3F9*4) +#define RFC_CSU_SORTDATA_ID26 (RFC_CSU_BASE+0x3FA*4) +#define RFC_CSU_SORTDATA_ID27 (RFC_CSU_BASE+0x3FB*4) +#define RFC_CSU_SORTDATA_ID28 (RFC_CSU_BASE+0x3FC*4) +#define RFC_CSU_SORTDATA_ID29 (RFC_CSU_BASE+0x3FD*4) +#define RFC_CSU_SORTDATA_ID30 (RFC_CSU_BASE+0x3FE*4) +#define RFC_CSU_SORTDATA_ID31 (RFC_CSU_BASE+0x3FF*4) + + +#define JS_CSU_ALLPENDEVENTMASK (JS_CSU_BASE+0x000*4) +#define JS_CSU_EVENTMASK (JS_CSU_BASE+0x002*4) +#define JS_CSU_LATCHALFULL (JS_CSU_BASE+0x003*4) +#define JS_CSU_INTMASK (JS_CSU_BASE+0x004*4) +#define JS_CSU_ELEVELMASK (JS_CSU_BASE+0x005*4) +#define JS_CSU_TAGMASK0 (JS_CSU_BASE+0x006*4) +#define JS_CSU_TAGMASK1 (JS_CSU_BASE+0x007*4) +#define JS_CSU_TAGMASK2 (JS_CSU_BASE+0x008*4) +#define JS_CSU_TAGMASK3 (JS_CSU_BASE+0x009*4) +#define JS_CSU_ARMCMDRECV (JS_CSU_BASE+0x00A*4) +#define JS_CSU_ALLPENDEVENT0 (JS_CSU_BASE+0x00C*4) +#define JS_CSU_ALLPENDEVENT1 (JS_CSU_BASE+0x00D*4) +#define JS_CSU_EM_BS_SMSEL_PREDATANUM (JS_CSU_BASE+0x010*4) +#define JS_CSU_ALMOSTFULLSENDTHRED (JS_CSU_BASE+0x011*4) +#define JS_CSU_JESDTXSET (JS_CSU_BASE+0x012*4) +#define JS_CSU_JESDRX0SET (JS_CSU_BASE+0x013*4) +#define JS_CSU_FINDDMATAG (JS_CSU_BASE+0x014*4) +#define JS_CSU_JESDTX1SET (JS_CSU_BASE+0x016*4) +#define JS_CSU_JESDRX1SET (JS_CSU_BASE+0x017*4) +#define JS_CSU_CMDFIFO0_CMD (JS_CSU_BASE+0x018*4) +#define JS_CSU_CMDFIFO1_CMD (JS_CSU_BASE+0x019*4) +#define JS_CSU_CMDFIFO2_CMD (JS_CSU_BASE+0x01A*4) +#define JS_CSU_CMDFIFO3_CMD (JS_CSU_BASE+0x01B*4) +#define JS_CSU_CMDFIFO0_NUM (JS_CSU_BASE+0x01C*4) +#define JS_CSU_CMDFIFO1_NUM (JS_CSU_BASE+0x01D*4) +#define JS_CSU_CMDFIFO2_NUM (JS_CSU_BASE+0x01E*4) +#define JS_CSU_CMDFIFO3_NUM (JS_CSU_BASE+0x01F*4) +#define JS_CSU_PRICMDVALID0 (JS_CSU_BASE+0x020*4) +#define JS_CSU_PRICMDVALID1 (JS_CSU_BASE+0x021*4) +#define JS_CSU_PRICMDVALID2 (JS_CSU_BASE+0x022*4) +#define JS_CSU_PRICMDVALID3 (JS_CSU_BASE+0x023*4) +#define JS_CSU_CMDECODATAL32BIT0 (JS_CSU_BASE+0x024*4) +#define JS_CSU_CMDECODATAL32BIT1 (JS_CSU_BASE+0x025*4) +#define JS_CSU_CMDECODATAL32BIT2 (JS_CSU_BASE+0x026*4) +#define JS_CSU_CMDECODATAL32BIT3 (JS_CSU_BASE+0x027*4) +#define JS_CSU_CMDHIGHDATA (JS_CSU_BASE+0x028*4) +#define JS_CSU_CMDFIFO0 (JS_CSU_BASE+0x02C*4) +#define JS_CSU_CMDFIFO1 (JS_CSU_BASE+0x02D*4) +#define JS_CSU_CMDFIFO2 (JS_CSU_BASE+0x02E*4) +#define JS_CSU_CMDFIFO3 (JS_CSU_BASE+0x02F*4) +#define JS_CSU_READYLISTNUM (JS_CSU_BASE+0x030*4) +#define JS_CSU_CMDFIFO0_TAGNUM (JS_CSU_BASE+0x034*4) +#define JS_CSU_CMDFIFO1_TAGNUM (JS_CSU_BASE+0x035*4) +#define JS_CSU_CMDFIFO2_TAGNUM (JS_CSU_BASE+0x036*4) +#define JS_CSU_CMDFIFO3_TAGNUM (JS_CSU_BASE+0x037*4) +#define JS_CSU_DMASTATUS (JS_CSU_BASE+0x038*4) +#define JS_CSU_CMDSTALL_LISTSTALL (JS_CSU_BASE+0x039*4) +#define JS_CSU_QOUSTATUS (JS_CSU_BASE+0x03A*4) +#define JS_CSU_EVENTINTCLEAR (JS_CSU_BASE+0x03C*4) +#define JS_CSU_DMAADDRL0 (JS_CSU_BASE+0x200*4) +#define JS_CSU_DMAADDRH0 (JS_CSU_BASE+0x201*4) +#define JS_CSU_DMAYSTEPL0 (JS_CSU_BASE+0x202*4) +#define JS_CSU_DMAYSTEPH0 (JS_CSU_BASE+0x203*4) +#define JS_CSU_DMAZSTEPL0 (JS_CSU_BASE+0x204*4) +#define JS_CSU_DMAZSTEPH0 (JS_CSU_BASE+0x205*4) +#define JS_CSU_DMAYNUMXNUM0 (JS_CSU_BASE+0x206*4) +#define JS_CSU_DMASIZEGRANALLNUM0 (JS_CSU_BASE+0x207*4) +#define JS_CSU_DMAADDRL1 (JS_CSU_BASE+0x208*4) +#define JS_CSU_DMAADDRH1 (JS_CSU_BASE+0x209*4) +#define JS_CSU_DMAYSTEPL1 (JS_CSU_BASE+0x20A*4) +#define JS_CSU_DMAYSTEPH1 (JS_CSU_BASE+0x20B*4) +#define JS_CSU_DMAZSTEPL1 (JS_CSU_BASE+0x20C*4) +#define JS_CSU_DMAZSTEPH1 (JS_CSU_BASE+0x20D*4) +#define JS_CSU_DMAYNUMXNUM1 (JS_CSU_BASE+0x20E*4) +#define JS_CSU_DMASIZEGRANALLNUM1 (JS_CSU_BASE+0x20F*4) +#define JS_CSU_DMAADDRL2 (JS_CSU_BASE+0x210*4) +#define JS_CSU_DMAADDRH2 (JS_CSU_BASE+0x211*4) +#define JS_CSU_DMAYSTEPL2 (JS_CSU_BASE+0x212*4) +#define JS_CSU_DMAYSTEPH2 (JS_CSU_BASE+0x213*4) +#define JS_CSU_DMAZSTEPL2 (JS_CSU_BASE+0x214*4) +#define JS_CSU_DMAZSTEPH2 (JS_CSU_BASE+0x215*4) +#define JS_CSU_DMAYNUMXNUM2 (JS_CSU_BASE+0x216*4) +#define JS_CSU_DMASIZEGRANALLNUM2 (JS_CSU_BASE+0x217*4) +#define JS_CSU_DMAADDRL3 (JS_CSU_BASE+0x218*4) +#define JS_CSU_DMAADDRH3 (JS_CSU_BASE+0x219*4) +#define JS_CSU_DMAYSTEPL3 (JS_CSU_BASE+0x21A*4) +#define JS_CSU_DMAYSTEPH3 (JS_CSU_BASE+0x21B*4) +#define JS_CSU_DMAZSTEPL3 (JS_CSU_BASE+0x21C*4) +#define JS_CSU_DMAZSTEPH3 (JS_CSU_BASE+0x21D*4) +#define JS_CSU_DMAYNUMXNUM3 (JS_CSU_BASE+0x21E*4) +#define JS_CSU_DMASIZEGRANALLNUM3 (JS_CSU_BASE+0x21F*4) +#define JS_CSU_DMAADDRL4 (JS_CSU_BASE+0x220*4) +#define JS_CSU_DMAADDRH4 (JS_CSU_BASE+0x221*4) +#define JS_CSU_DMAYSTEPL4 (JS_CSU_BASE+0x222*4) +#define JS_CSU_DMAYSTEPH4 (JS_CSU_BASE+0x223*4) +#define JS_CSU_DMAZSTEPL4 (JS_CSU_BASE+0x224*4) +#define JS_CSU_DMAZSTEPH4 (JS_CSU_BASE+0x225*4) +#define JS_CSU_DMAYNUMXNUM4 (JS_CSU_BASE+0x226*4) +#define JS_CSU_DMASIZEGRANALLNUM4 (JS_CSU_BASE+0x227*4) +#define JS_CSU_DMAADDRL5 (JS_CSU_BASE+0x228*4) +#define JS_CSU_DMAADDRH5 (JS_CSU_BASE+0x229*4) +#define JS_CSU_DMAYSTEPL5 (JS_CSU_BASE+0x22A*4) +#define JS_CSU_DMAYSTEPH5 (JS_CSU_BASE+0x22B*4) +#define JS_CSU_DMAZSTEPL5 (JS_CSU_BASE+0x22C*4) +#define JS_CSU_DMAZSTEPH5 (JS_CSU_BASE+0x22D*4) +#define JS_CSU_DMAYNUMXNUM5 (JS_CSU_BASE+0x22E*4) +#define JS_CSU_DMASIZEGRANALLNUM5 (JS_CSU_BASE+0x22F*4) +#define JS_CSU_DMAADDRL6 (JS_CSU_BASE+0x230*4) +#define JS_CSU_DMAADDRH6 (JS_CSU_BASE+0x231*4) +#define JS_CSU_DMAYSTEPL6 (JS_CSU_BASE+0x232*4) +#define JS_CSU_DMAYSTEPH6 (JS_CSU_BASE+0x233*4) +#define JS_CSU_DMAZSTEPL6 (JS_CSU_BASE+0x234*4) +#define JS_CSU_DMAZSTEPH6 (JS_CSU_BASE+0x235*4) +#define JS_CSU_DMAYNUMXNUM6 (JS_CSU_BASE+0x236*4) +#define JS_CSU_DMASIZEGRANALLNUM6 (JS_CSU_BASE+0x237*4) +#define JS_CSU_DMAADDRL7 (JS_CSU_BASE+0x238*4) +#define JS_CSU_DMAADDRH7 (JS_CSU_BASE+0x239*4) +#define JS_CSU_DMAYSTEPL7 (JS_CSU_BASE+0x23A*4) +#define JS_CSU_DMAYSTEPH7 (JS_CSU_BASE+0x23B*4) +#define JS_CSU_DMAZSTEPL7 (JS_CSU_BASE+0x23C*4) +#define JS_CSU_DMAZSTEPH7 (JS_CSU_BASE+0x23D*4) +#define JS_CSU_DMAYNUMXNUM7 (JS_CSU_BASE+0x23E*4) +#define JS_CSU_DMASIZEGRANALLNUM7 (JS_CSU_BASE+0x23F*4) +#define JS_CSU_DMAADDRL8 (JS_CSU_BASE+0x240*4) +#define JS_CSU_DMAADDRH8 (JS_CSU_BASE+0x241*4) +#define JS_CSU_DMAYSTEPL8 (JS_CSU_BASE+0x242*4) +#define JS_CSU_DMAYSTEPH8 (JS_CSU_BASE+0x243*4) +#define JS_CSU_DMAZSTEPL8 (JS_CSU_BASE+0x244*4) +#define JS_CSU_DMAZSTEPH8 (JS_CSU_BASE+0x245*4) +#define JS_CSU_DMAYNUMXNUM8 (JS_CSU_BASE+0x246*4) +#define JS_CSU_DMASIZEGRANALLNUM8 (JS_CSU_BASE+0x247*4) +#define JS_CSU_DMAADDRL9 (JS_CSU_BASE+0x248*4) +#define JS_CSU_DMAADDRH9 (JS_CSU_BASE+0x249*4) +#define JS_CSU_DMAYSTEPL9 (JS_CSU_BASE+0x24A*4) +#define JS_CSU_DMAYSTEPH9 (JS_CSU_BASE+0x24B*4) +#define JS_CSU_DMAZSTEPL9 (JS_CSU_BASE+0x24C*4) +#define JS_CSU_DMAZSTEPH9 (JS_CSU_BASE+0x24D*4) +#define JS_CSU_DMAYNUMXNUM9 (JS_CSU_BASE+0x24E*4) +#define JS_CSU_DMASIZEGRANALLNUM9 (JS_CSU_BASE+0x24F*4) +#define JS_CSU_DMAADDRL10 (JS_CSU_BASE+0x250*4) +#define JS_CSU_DMAADDRH10 (JS_CSU_BASE+0x251*4) +#define JS_CSU_DMAYSTEPL10 (JS_CSU_BASE+0x252*4) +#define JS_CSU_DMAYSTEPH10 (JS_CSU_BASE+0x253*4) +#define JS_CSU_DMAZSTEPL10 (JS_CSU_BASE+0x254*4) +#define JS_CSU_DMAZSTEPH10 (JS_CSU_BASE+0x255*4) +#define JS_CSU_DMAYNUMXNUM10 (JS_CSU_BASE+0x256*4) +#define JS_CSU_DMASIZEGRANALLNUM10 (JS_CSU_BASE+0x257*4) +#define JS_CSU_DMAADDRL11 (JS_CSU_BASE+0x258*4) +#define JS_CSU_DMAADDRH11 (JS_CSU_BASE+0x259*4) +#define JS_CSU_DMAYSTEPL11 (JS_CSU_BASE+0x25A*4) +#define JS_CSU_DMAYSTEPH11 (JS_CSU_BASE+0x25B*4) +#define JS_CSU_DMAZSTEPL11 (JS_CSU_BASE+0x25C*4) +#define JS_CSU_DMAZSTEPH11 (JS_CSU_BASE+0x25D*4) +#define JS_CSU_DMAYNUMXNUM11 (JS_CSU_BASE+0x25E*4) +#define JS_CSU_DMASIZEGRANALLNUM11 (JS_CSU_BASE+0x25F*4) +#define JS_CSU_DMAADDRL12 (JS_CSU_BASE+0x260*4) +#define JS_CSU_DMAADDRH12 (JS_CSU_BASE+0x261*4) +#define JS_CSU_DMAYSTEPL12 (JS_CSU_BASE+0x262*4) +#define JS_CSU_DMAYSTEPH12 (JS_CSU_BASE+0x263*4) +#define JS_CSU_DMAZSTEPL12 (JS_CSU_BASE+0x264*4) +#define JS_CSU_DMAZSTEPH12 (JS_CSU_BASE+0x265*4) +#define JS_CSU_DMAYNUMXNUM12 (JS_CSU_BASE+0x266*4) +#define JS_CSU_DMASIZEGRANALLNUM12 (JS_CSU_BASE+0x267*4) +#define JS_CSU_DMAADDRL13 (JS_CSU_BASE+0x268*4) +#define JS_CSU_DMAADDRH13 (JS_CSU_BASE+0x269*4) +#define JS_CSU_DMAYSTEPL13 (JS_CSU_BASE+0x26A*4) +#define JS_CSU_DMAYSTEPH13 (JS_CSU_BASE+0x26B*4) +#define JS_CSU_DMAZSTEPL13 (JS_CSU_BASE+0x26C*4) +#define JS_CSU_DMAZSTEPH13 (JS_CSU_BASE+0x26D*4) +#define JS_CSU_DMAYNUMXNUM13 (JS_CSU_BASE+0x26E*4) +#define JS_CSU_DMASIZEGRANALLNUM13 (JS_CSU_BASE+0x26F*4) +#define JS_CSU_DMAADDRL14 (JS_CSU_BASE+0x270*4) +#define JS_CSU_DMAADDRH14 (JS_CSU_BASE+0x271*4) +#define JS_CSU_DMAYSTEPL14 (JS_CSU_BASE+0x272*4) +#define JS_CSU_DMAYSTEPH14 (JS_CSU_BASE+0x273*4) +#define JS_CSU_DMAZSTEPL14 (JS_CSU_BASE+0x274*4) +#define JS_CSU_DMAZSTEPH14 (JS_CSU_BASE+0x275*4) +#define JS_CSU_DMAYNUMXNUM14 (JS_CSU_BASE+0x276*4) +#define JS_CSU_DMASIZEGRANALLNUM14 (JS_CSU_BASE+0x277*4) +#define JS_CSU_DMAADDRL15 (JS_CSU_BASE+0x278*4) +#define JS_CSU_DMAADDRH15 (JS_CSU_BASE+0x279*4) +#define JS_CSU_DMAYSTEPL15 (JS_CSU_BASE+0x27A*4) +#define JS_CSU_DMAYSTEPH15 (JS_CSU_BASE+0x27B*4) +#define JS_CSU_DMAZSTEPL15 (JS_CSU_BASE+0x27C*4) +#define JS_CSU_DMAZSTEPH15 (JS_CSU_BASE+0x27D*4) +#define JS_CSU_DMAYNUMXNUM15 (JS_CSU_BASE+0x27E*4) +#define JS_CSU_DMASIZEGRANALLNUM15 (JS_CSU_BASE+0x27F*4) +#define JS_CSU_QOUCMDNUM_QOUCMDPOS (JS_CSU_BASE+0x300*4) +#define JS_CSU_QOUCMDADDR (JS_CSU_BASE+0x301*4) +#define JS_CSU_QOUCMDDATA (JS_CSU_BASE+0x302*4) +#define JS_CSU_QOUSTATUSPOPDATA (JS_CSU_BASE+0x303*4) +#define JS_CSU_QOUCMPDATA0 (JS_CSU_BASE+0x304*4) +#define JS_CSU_QOUCMPDATA1 (JS_CSU_BASE+0x305*4) +#define JS_CSU_QOUCMPDATA2 (JS_CSU_BASE+0x306*4) +#define JS_CSU_PRICMDDATA_L32BIT0 (JS_CSU_BASE+0x310*4) +#define JS_CSU_PRICMDDATA_H14BIT0 (JS_CSU_BASE+0x311*4) +#define JS_CSU_PRICMDDATA_L32BIT1 (JS_CSU_BASE+0x312*4) +#define JS_CSU_PRICMDDATA_H14BIT1 (JS_CSU_BASE+0x313*4) +#define JS_CSU_PRICMDDATA_L32BIT2 (JS_CSU_BASE+0x314*4) +#define JS_CSU_PRICMDDATA_H14BIT2 (JS_CSU_BASE+0x315*4) +#define JS_CSU_SORTDATA_NUM (JS_CSU_BASE+0x380*4) +#define JS_CSU_SORTDATA_DATA0 (JS_CSU_BASE+0x3C0*4) +#define JS_CSU_SORTDATA_DATA1 (JS_CSU_BASE+0x3C1*4) +#define JS_CSU_SORTDATA_DATA2 (JS_CSU_BASE+0x3C2*4) +#define JS_CSU_SORTDATA_DATA3 (JS_CSU_BASE+0x3C3*4) +#define JS_CSU_SORTDATA_DATA4 (JS_CSU_BASE+0x3C4*4) +#define JS_CSU_SORTDATA_DATA5 (JS_CSU_BASE+0x3C5*4) +#define JS_CSU_SORTDATA_DATA6 (JS_CSU_BASE+0x3C6*4) +#define JS_CSU_SORTDATA_DATA7 (JS_CSU_BASE+0x3C7*4) +#define JS_CSU_SORTDATA_DATA8 (JS_CSU_BASE+0x3C8*4) +#define JS_CSU_SORTDATA_DATA9 (JS_CSU_BASE+0x3C9*4) +#define JS_CSU_SORTDATA_DATA10 (JS_CSU_BASE+0x3CA*4) +#define JS_CSU_SORTDATA_DATA11 (JS_CSU_BASE+0x3CB*4) +#define JS_CSU_SORTDATA_DATA12 (JS_CSU_BASE+0x3CC*4) +#define JS_CSU_SORTDATA_DATA13 (JS_CSU_BASE+0x3CD*4) +#define JS_CSU_SORTDATA_DATA14 (JS_CSU_BASE+0x3CE*4) +#define JS_CSU_SORTDATA_DATA15 (JS_CSU_BASE+0x3CF*4) +#define JS_CSU_SORTDATA_DATA16 (JS_CSU_BASE+0x3D0*4) +#define JS_CSU_SORTDATA_DATA17 (JS_CSU_BASE+0x3D1*4) +#define JS_CSU_SORTDATA_DATA18 (JS_CSU_BASE+0x3D2*4) +#define JS_CSU_SORTDATA_DATA19 (JS_CSU_BASE+0x3D3*4) +#define JS_CSU_SORTDATA_DATA20 (JS_CSU_BASE+0x3D4*4) +#define JS_CSU_SORTDATA_DATA21 (JS_CSU_BASE+0x3D5*4) +#define JS_CSU_SORTDATA_DATA22 (JS_CSU_BASE+0x3D6*4) +#define JS_CSU_SORTDATA_DATA23 (JS_CSU_BASE+0x3D7*4) +#define JS_CSU_SORTDATA_DATA24 (JS_CSU_BASE+0x3D8*4) +#define JS_CSU_SORTDATA_DATA25 (JS_CSU_BASE+0x3D9*4) +#define JS_CSU_SORTDATA_DATA26 (JS_CSU_BASE+0x3DA*4) +#define JS_CSU_SORTDATA_DATA27 (JS_CSU_BASE+0x3DB*4) +#define JS_CSU_SORTDATA_DATA28 (JS_CSU_BASE+0x3DC*4) +#define JS_CSU_SORTDATA_DATA29 (JS_CSU_BASE+0x3DD*4) +#define JS_CSU_SORTDATA_DATA30 (JS_CSU_BASE+0x3DE*4) +#define JS_CSU_SORTDATA_DATA31 (JS_CSU_BASE+0x3DF*4) +#define JS_CSU_SORTDATA_ID0 (JS_CSU_BASE+0x3E0*4) +#define JS_CSU_SORTDATA_ID1 (JS_CSU_BASE+0x3E1*4) +#define JS_CSU_SORTDATA_ID2 (JS_CSU_BASE+0x3E2*4) +#define JS_CSU_SORTDATA_ID3 (JS_CSU_BASE+0x3E3*4) +#define JS_CSU_SORTDATA_ID4 (JS_CSU_BASE+0x3E4*4) +#define JS_CSU_SORTDATA_ID5 (JS_CSU_BASE+0x3E5*4) +#define JS_CSU_SORTDATA_ID6 (JS_CSU_BASE+0x3E6*4) +#define JS_CSU_SORTDATA_ID7 (JS_CSU_BASE+0x3E7*4) +#define JS_CSU_SORTDATA_ID8 (JS_CSU_BASE+0x3E8*4) +#define JS_CSU_SORTDATA_ID9 (JS_CSU_BASE+0x3E9*4) +#define JS_CSU_SORTDATA_ID10 (JS_CSU_BASE+0x3EA*4) +#define JS_CSU_SORTDATA_ID11 (JS_CSU_BASE+0x3EB*4) +#define JS_CSU_SORTDATA_ID12 (JS_CSU_BASE+0x3EC*4) +#define JS_CSU_SORTDATA_ID13 (JS_CSU_BASE+0x3ED*4) +#define JS_CSU_SORTDATA_ID14 (JS_CSU_BASE+0x3EE*4) +#define JS_CSU_SORTDATA_ID15 (JS_CSU_BASE+0x3EF*4) +#define JS_CSU_SORTDATA_ID16 (JS_CSU_BASE+0x3F0*4) +#define JS_CSU_SORTDATA_ID17 (JS_CSU_BASE+0x3F1*4) +#define JS_CSU_SORTDATA_ID18 (JS_CSU_BASE+0x3F2*4) +#define JS_CSU_SORTDATA_ID19 (JS_CSU_BASE+0x3F3*4) +#define JS_CSU_SORTDATA_ID20 (JS_CSU_BASE+0x3F4*4) +#define JS_CSU_SORTDATA_ID21 (JS_CSU_BASE+0x3F5*4) +#define JS_CSU_SORTDATA_ID22 (JS_CSU_BASE+0x3F6*4) +#define JS_CSU_SORTDATA_ID23 (JS_CSU_BASE+0x3F7*4) +#define JS_CSU_SORTDATA_ID24 (JS_CSU_BASE+0x3F8*4) +#define JS_CSU_SORTDATA_ID25 (JS_CSU_BASE+0x3F9*4) +#define JS_CSU_SORTDATA_ID26 (JS_CSU_BASE+0x3FA*4) +#define JS_CSU_SORTDATA_ID27 (JS_CSU_BASE+0x3FB*4) +#define JS_CSU_SORTDATA_ID28 (JS_CSU_BASE+0x3FC*4) +#define JS_CSU_SORTDATA_ID29 (JS_CSU_BASE+0x3FD*4) +#define JS_CSU_SORTDATA_ID30 (JS_CSU_BASE+0x3FE*4) +#define JS_CSU_SORTDATA_ID31 (JS_CSU_BASE+0x3FF*4) + + +#define JECS_CSU_ALLPENDEVENTMASK (JECS_CSU_BASE+0x000*4) +#define JECS_CSU_EVENTMASK (JECS_CSU_BASE+0x002*4) +#define JECS_CSU_LATCHALFULL (JECS_CSU_BASE+0x003*4) +#define JECS_CSU_INTMASK (JECS_CSU_BASE+0x004*4) +#define JECS_CSU_ELEVELMASK (JECS_CSU_BASE+0x005*4) +#define JECS_CSU_TAGMASK0 (JECS_CSU_BASE+0x006*4) +#define JECS_CSU_TAGMASK1 (JECS_CSU_BASE+0x007*4) +#define JECS_CSU_TAGMASK2 (JECS_CSU_BASE+0x008*4) +#define JECS_CSU_TAGMASK3 (JECS_CSU_BASE+0x009*4) +#define JECS_CSU_ARMCMDRECV (JECS_CSU_BASE+0x00A*4) +#define JECS_CSU_ALLPENDEVENT0 (JECS_CSU_BASE+0x00C*4) +#define JECS_CSU_ALLPENDEVENT1 (JECS_CSU_BASE+0x00D*4) +#define JECS_CSU_AXCSTAMPL32BIT (JECS_CSU_BASE+0x00E*4) +#define JECS_CSU_CTRLSTAMPL32BIT (JECS_CSU_BASE+0x00F*4) +#define JECS_CSU_EM_BS_SMSEL_PREDATANUM (JECS_CSU_BASE+0x010*4) +#define JECS_CSU_ALMOSTFULLSENDTHRED (JECS_CSU_BASE+0x011*4) +#define JECS_CSU_FINDDMATAG (JECS_CSU_BASE+0x014*4) +#define JECS_CSU_AXCSTAMPH32BIT (JECS_CSU_BASE+0x016*4) +#define JECS_CSU_CTRLSTAMPH32BIT (JECS_CSU_BASE+0x017*4) +#define JECS_CSU_CMDFIFO0_CMD (JECS_CSU_BASE+0x018*4) +#define JECS_CSU_CMDFIFO1_CMD (JECS_CSU_BASE+0x019*4) +#define JECS_CSU_CMDFIFO2_CMD (JECS_CSU_BASE+0x01A*4) +#define JECS_CSU_CMDFIFO3_CMD (JECS_CSU_BASE+0x01B*4) +#define JECS_CSU_CMDFIFO0_NUM (JECS_CSU_BASE+0x01C*4) +#define JECS_CSU_CMDFIFO1_NUM (JECS_CSU_BASE+0x01D*4) +#define JECS_CSU_CMDFIFO2_NUM (JECS_CSU_BASE+0x01E*4) +#define JECS_CSU_CMDFIFO3_NUM (JECS_CSU_BASE+0x01F*4) +#define JECS_CSU_PRICMDVALID0 (JECS_CSU_BASE+0x020*4) +#define JECS_CSU_PRICMDVALID1 (JECS_CSU_BASE+0x021*4) +#define JECS_CSU_PRICMDVALID2 (JECS_CSU_BASE+0x022*4) +#define JECS_CSU_PRICMDVALID3 (JECS_CSU_BASE+0x023*4) +#define JECS_CSU_CMDECODATAL32BIT0 (JECS_CSU_BASE+0x024*4) +#define JECS_CSU_CMDECODATAL32BIT1 (JECS_CSU_BASE+0x025*4) +#define JECS_CSU_CMDECODATAL32BIT2 (JECS_CSU_BASE+0x026*4) +#define JECS_CSU_CMDECODATAL32BIT3 (JECS_CSU_BASE+0x027*4) +#define JECS_CSU_CMDHIGHDATA (JECS_CSU_BASE+0x028*4) +#define JECS_CSU_CMDFIFO0 (JECS_CSU_BASE+0x02C*4) +#define JECS_CSU_CMDFIFO1 (JECS_CSU_BASE+0x02D*4) +#define JECS_CSU_CMDFIFO2 (JECS_CSU_BASE+0x02E*4) +#define JECS_CSU_CMDFIFO3 (JECS_CSU_BASE+0x02F*4) +#define JECS_CSU_READYLISTNUM (JECS_CSU_BASE+0x030*4) +#define JECS_CSU_CMDFIFO0_TAGNUM (JECS_CSU_BASE+0x034*4) +#define JECS_CSU_CMDFIFO1_TAGNUM (JECS_CSU_BASE+0x035*4) +#define JECS_CSU_CMDFIFO2_TAGNUM (JECS_CSU_BASE+0x036*4) +#define JECS_CSU_CMDFIFO3_TAGNUM (JECS_CSU_BASE+0x037*4) +#define JECS_CSU_DMASTATUS (JECS_CSU_BASE+0x038*4) +#define JECS_CSU_CMDSTALL_LISTSTALL (JECS_CSU_BASE+0x039*4) +#define JECS_CSU_QOUSTATUS (JECS_CSU_BASE+0x03A*4) +#define JECS_CSU_EVENTINTCLEAR (JECS_CSU_BASE+0x03C*4) +#define JECS_CSU_XSTEPL0 (JECS_CSU_BASE+0x140*4) +#define JECS_CSU_XSTEPH0 (JECS_CSU_BASE+0x141*4) +#define JECS_CSU_XSTEPL1 (JECS_CSU_BASE+0x142*4) +#define JECS_CSU_XSTEPH1 (JECS_CSU_BASE+0x143*4) +#define JECS_CSU_XSTEPL2 (JECS_CSU_BASE+0x144*4) +#define JECS_CSU_XSTEPH2 (JECS_CSU_BASE+0x145*4) +#define JECS_CSU_XSTEPL3 (JECS_CSU_BASE+0x146*4) +#define JECS_CSU_XSTEPH3 (JECS_CSU_BASE+0x147*4) +#define JECS_CSU_XSTEPL4 (JECS_CSU_BASE+0x148*4) +#define JECS_CSU_XSTEPH4 (JECS_CSU_BASE+0x149*4) +#define JECS_CSU_XSTEPL5 (JECS_CSU_BASE+0x150*4) +#define JECS_CSU_XSTEPH5 (JECS_CSU_BASE+0x151*4) +#define JECS_CSU_XSTEPL6 (JECS_CSU_BASE+0x152*4) +#define JECS_CSU_XSTEPH6 (JECS_CSU_BASE+0x153*4) +#define JECS_CSU_XSTEPL7 (JECS_CSU_BASE+0x154*4) +#define JECS_CSU_XSTEPH7 (JECS_CSU_BASE+0x155*4) +#define JECS_CSU_XSTEPL8 (JECS_CSU_BASE+0x156*4) +#define JECS_CSU_XSTEPH8 (JECS_CSU_BASE+0x157*4) +#define JECS_CSU_XSTEPL9 (JECS_CSU_BASE+0x158*4) +#define JECS_CSU_XSTEPH9 (JECS_CSU_BASE+0x159*4) +#define JECS_CSU_XSTEPL10 (JECS_CSU_BASE+0x160*4) +#define JECS_CSU_XSTEPH10 (JECS_CSU_BASE+0x161*4) +#define JECS_CSU_XSTEPL11 (JECS_CSU_BASE+0x162*4) +#define JECS_CSU_XSTEPH11 (JECS_CSU_BASE+0x163*4) +#define JECS_CSU_XSTEPL12 (JECS_CSU_BASE+0x164*4) +#define JECS_CSU_XSTEPH12 (JECS_CSU_BASE+0x165*4) +#define JECS_CSU_XSTEPL13 (JECS_CSU_BASE+0x166*4) +#define JECS_CSU_XSTEPH13 (JECS_CSU_BASE+0x167*4) +#define JECS_CSU_XSTEPL14 (JECS_CSU_BASE+0x168*4) +#define JECS_CSU_XSTEPH14 (JECS_CSU_BASE+0x169*4) +#define JECS_CSU_XSTEPL15 (JECS_CSU_BASE+0x170*4) +#define JECS_CSU_XSTEPH15 (JECS_CSU_BASE+0x171*4) +#define JECS_CSU_XSTEPL16 (JECS_CSU_BASE+0x172*4) +#define JECS_CSU_XSTEPH16 (JECS_CSU_BASE+0x173*4) +#define JECS_CSU_XSTEPL17 (JECS_CSU_BASE+0x174*4) +#define JECS_CSU_XSTEPH17 (JECS_CSU_BASE+0x175*4) +#define JECS_CSU_XSTEPL18 (JECS_CSU_BASE+0x176*4) +#define JECS_CSU_XSTEPH18 (JECS_CSU_BASE+0x177*4) +#define JECS_CSU_XSTEPL19 (JECS_CSU_BASE+0x178*4) +#define JECS_CSU_XSTEPH19 (JECS_CSU_BASE+0x179*4) +#define JECS_CSU_XSTEPL20 (JECS_CSU_BASE+0x180*4) +#define JECS_CSU_XSTEPH20 (JECS_CSU_BASE+0x181*4) +#define JECS_CSU_XSTEPL21 (JECS_CSU_BASE+0x182*4) +#define JECS_CSU_XSTEPH21 (JECS_CSU_BASE+0x183*4) +#define JECS_CSU_XSTEPL22 (JECS_CSU_BASE+0x184*4) +#define JECS_CSU_XSTEPH22 (JECS_CSU_BASE+0x185*4) +#define JECS_CSU_XSTEPL23 (JECS_CSU_BASE+0x186*4) +#define JECS_CSU_XSTEPH23 (JECS_CSU_BASE+0x187*4) +#define JECS_CSU_XSTEPL24 (JECS_CSU_BASE+0x188*4) +#define JECS_CSU_XSTEPH24 (JECS_CSU_BASE+0x189*4) +#define JECS_CSU_XSTEPL25 (JECS_CSU_BASE+0x190*4) +#define JECS_CSU_XSTEPH25 (JECS_CSU_BASE+0x191*4) +#define JECS_CSU_XSTEPL26 (JECS_CSU_BASE+0x192*4) +#define JECS_CSU_XSTEPH26 (JECS_CSU_BASE+0x193*4) +#define JECS_CSU_XSTEPL27 (JECS_CSU_BASE+0x194*4) +#define JECS_CSU_XSTEPH27 (JECS_CSU_BASE+0x195*4) +#define JECS_CSU_XSTEPL28 (JECS_CSU_BASE+0x196*4) +#define JECS_CSU_XSTEPH28 (JECS_CSU_BASE+0x197*4) +#define JECS_CSU_XSTEPL29 (JECS_CSU_BASE+0x198*4) +#define JECS_CSU_XSTEPH29 (JECS_CSU_BASE+0x199*4) +#define JECS_CSU_XSTEPL30 (JECS_CSU_BASE+0x1A0*4) +#define JECS_CSU_XSTEPH30 (JECS_CSU_BASE+0x1A1*4) +#define JECS_CSU_XSTEPL31 (JECS_CSU_BASE+0x1A2*4) +#define JECS_CSU_XSTEPH31 (JECS_CSU_BASE+0x1A3*4) +#define JECS_CSU_DMAADDRL0 (JECS_CSU_BASE+0x200*4) +#define JECS_CSU_DMAADDRH0 (JECS_CSU_BASE+0x201*4) +#define JECS_CSU_DMAYSTEPL0 (JECS_CSU_BASE+0x202*4) +#define JECS_CSU_DMAYSTEPH0 (JECS_CSU_BASE+0x203*4) +#define JECS_CSU_DMAZSTEPL0 (JECS_CSU_BASE+0x204*4) +#define JECS_CSU_DMAZSTEPH0 (JECS_CSU_BASE+0x205*4) +#define JECS_CSU_DMAYNUMXNUM0 (JECS_CSU_BASE+0x206*4) +#define JECS_CSU_DMASIZEGRANALLNUM0 (JECS_CSU_BASE+0x207*4) +#define JECS_CSU_DMAADDRL1 (JECS_CSU_BASE+0x208*4) +#define JECS_CSU_DMAADDRH1 (JECS_CSU_BASE+0x209*4) +#define JECS_CSU_DMAYSTEPL1 (JECS_CSU_BASE+0x20A*4) +#define JECS_CSU_DMAYSTEPH1 (JECS_CSU_BASE+0x20B*4) +#define JECS_CSU_DMAZSTEPL1 (JECS_CSU_BASE+0x20C*4) +#define JECS_CSU_DMAZSTEPH1 (JECS_CSU_BASE+0x20D*4) +#define JECS_CSU_DMAYNUMXNUM1 (JECS_CSU_BASE+0x20E*4) +#define JECS_CSU_DMASIZEGRANALLNUM1 (JECS_CSU_BASE+0x20F*4) +#define JECS_CSU_DMAADDRL2 (JECS_CSU_BASE+0x210*4) +#define JECS_CSU_DMAADDRH2 (JECS_CSU_BASE+0x211*4) +#define JECS_CSU_DMAYSTEPL2 (JECS_CSU_BASE+0x212*4) +#define JECS_CSU_DMAYSTEPH2 (JECS_CSU_BASE+0x213*4) +#define JECS_CSU_DMAZSTEPL2 (JECS_CSU_BASE+0x214*4) +#define JECS_CSU_DMAZSTEPH2 (JECS_CSU_BASE+0x215*4) +#define JECS_CSU_DMAYNUMXNUM2 (JECS_CSU_BASE+0x216*4) +#define JECS_CSU_DMASIZEGRANALLNUM2 (JECS_CSU_BASE+0x217*4) +#define JECS_CSU_DMAADDRL3 (JECS_CSU_BASE+0x218*4) +#define JECS_CSU_DMAADDRH3 (JECS_CSU_BASE+0x219*4) +#define JECS_CSU_DMAYSTEPL3 (JECS_CSU_BASE+0x21A*4) +#define JECS_CSU_DMAYSTEPH3 (JECS_CSU_BASE+0x21B*4) +#define JECS_CSU_DMAZSTEPL3 (JECS_CSU_BASE+0x21C*4) +#define JECS_CSU_DMAZSTEPH3 (JECS_CSU_BASE+0x21D*4) +#define JECS_CSU_DMAYNUMXNUM3 (JECS_CSU_BASE+0x21E*4) +#define JECS_CSU_DMASIZEGRANALLNUM3 (JECS_CSU_BASE+0x21F*4) +#define JECS_CSU_DMAADDRL4 (JECS_CSU_BASE+0x220*4) +#define JECS_CSU_DMAADDRH4 (JECS_CSU_BASE+0x221*4) +#define JECS_CSU_DMAYSTEPL4 (JECS_CSU_BASE+0x222*4) +#define JECS_CSU_DMAYSTEPH4 (JECS_CSU_BASE+0x223*4) +#define JECS_CSU_DMAZSTEPL4 (JECS_CSU_BASE+0x224*4) +#define JECS_CSU_DMAZSTEPH4 (JECS_CSU_BASE+0x225*4) +#define JECS_CSU_DMAYNUMXNUM4 (JECS_CSU_BASE+0x226*4) +#define JECS_CSU_DMASIZEGRANALLNUM4 (JECS_CSU_BASE+0x227*4) +#define JECS_CSU_DMAADDRL5 (JECS_CSU_BASE+0x228*4) +#define JECS_CSU_DMAADDRH5 (JECS_CSU_BASE+0x229*4) +#define JECS_CSU_DMAYSTEPL5 (JECS_CSU_BASE+0x22A*4) +#define JECS_CSU_DMAYSTEPH5 (JECS_CSU_BASE+0x22B*4) +#define JECS_CSU_DMAZSTEPL5 (JECS_CSU_BASE+0x22C*4) +#define JECS_CSU_DMAZSTEPH5 (JECS_CSU_BASE+0x22D*4) +#define JECS_CSU_DMAYNUMXNUM5 (JECS_CSU_BASE+0x22E*4) +#define JECS_CSU_DMASIZEGRANALLNUM5 (JECS_CSU_BASE+0x22F*4) +#define JECS_CSU_DMAADDRL6 (JECS_CSU_BASE+0x230*4) +#define JECS_CSU_DMAADDRH6 (JECS_CSU_BASE+0x231*4) +#define JECS_CSU_DMAYSTEPL6 (JECS_CSU_BASE+0x232*4) +#define JECS_CSU_DMAYSTEPH6 (JECS_CSU_BASE+0x233*4) +#define JECS_CSU_DMAZSTEPL6 (JECS_CSU_BASE+0x234*4) +#define JECS_CSU_DMAZSTEPH6 (JECS_CSU_BASE+0x235*4) +#define JECS_CSU_DMAYNUMXNUM6 (JECS_CSU_BASE+0x236*4) +#define JECS_CSU_DMASIZEGRANALLNUM6 (JECS_CSU_BASE+0x237*4) +#define JECS_CSU_DMAADDRL7 (JECS_CSU_BASE+0x238*4) +#define JECS_CSU_DMAADDRH7 (JECS_CSU_BASE+0x239*4) +#define JECS_CSU_DMAYSTEPL7 (JECS_CSU_BASE+0x23A*4) +#define JECS_CSU_DMAYSTEPH7 (JECS_CSU_BASE+0x23B*4) +#define JECS_CSU_DMAZSTEPL7 (JECS_CSU_BASE+0x23C*4) +#define JECS_CSU_DMAZSTEPH7 (JECS_CSU_BASE+0x23D*4) +#define JECS_CSU_DMAYNUMXNUM7 (JECS_CSU_BASE+0x23E*4) +#define JECS_CSU_DMASIZEGRANALLNUM7 (JECS_CSU_BASE+0x23F*4) +#define JECS_CSU_DMAADDRL8 (JECS_CSU_BASE+0x240*4) +#define JECS_CSU_DMAADDRH8 (JECS_CSU_BASE+0x241*4) +#define JECS_CSU_DMAYSTEPL8 (JECS_CSU_BASE+0x242*4) +#define JECS_CSU_DMAYSTEPH8 (JECS_CSU_BASE+0x243*4) +#define JECS_CSU_DMAZSTEPL8 (JECS_CSU_BASE+0x244*4) +#define JECS_CSU_DMAZSTEPH8 (JECS_CSU_BASE+0x245*4) +#define JECS_CSU_DMAYNUMXNUM8 (JECS_CSU_BASE+0x246*4) +#define JECS_CSU_DMASIZEGRANALLNUM8 (JECS_CSU_BASE+0x247*4) +#define JECS_CSU_DMAADDRL9 (JECS_CSU_BASE+0x248*4) +#define JECS_CSU_DMAADDRH9 (JECS_CSU_BASE+0x249*4) +#define JECS_CSU_DMAYSTEPL9 (JECS_CSU_BASE+0x24A*4) +#define JECS_CSU_DMAYSTEPH9 (JECS_CSU_BASE+0x24B*4) +#define JECS_CSU_DMAZSTEPL9 (JECS_CSU_BASE+0x24C*4) +#define JECS_CSU_DMAZSTEPH9 (JECS_CSU_BASE+0x24D*4) +#define JECS_CSU_DMAYNUMXNUM9 (JECS_CSU_BASE+0x24E*4) +#define JECS_CSU_DMASIZEGRANALLNUM9 (JECS_CSU_BASE+0x24F*4) +#define JECS_CSU_DMAADDRL10 (JECS_CSU_BASE+0x250*4) +#define JECS_CSU_DMAADDRH10 (JECS_CSU_BASE+0x251*4) +#define JECS_CSU_DMAYSTEPL10 (JECS_CSU_BASE+0x252*4) +#define JECS_CSU_DMAYSTEPH10 (JECS_CSU_BASE+0x253*4) +#define JECS_CSU_DMAZSTEPL10 (JECS_CSU_BASE+0x254*4) +#define JECS_CSU_DMAZSTEPH10 (JECS_CSU_BASE+0x255*4) +#define JECS_CSU_DMAYNUMXNUM10 (JECS_CSU_BASE+0x256*4) +#define JECS_CSU_DMASIZEGRANALLNUM10 (JECS_CSU_BASE+0x257*4) +#define JECS_CSU_DMAADDRL11 (JECS_CSU_BASE+0x258*4) +#define JECS_CSU_DMAADDRH11 (JECS_CSU_BASE+0x259*4) +#define JECS_CSU_DMAYSTEPL11 (JECS_CSU_BASE+0x25A*4) +#define JECS_CSU_DMAYSTEPH11 (JECS_CSU_BASE+0x25B*4) +#define JECS_CSU_DMAZSTEPL11 (JECS_CSU_BASE+0x25C*4) +#define JECS_CSU_DMAZSTEPH11 (JECS_CSU_BASE+0x25D*4) +#define JECS_CSU_DMAYNUMXNUM11 (JECS_CSU_BASE+0x25E*4) +#define JECS_CSU_DMASIZEGRANALLNUM11 (JECS_CSU_BASE+0x25F*4) +#define JECS_CSU_DMAADDRL12 (JECS_CSU_BASE+0x260*4) +#define JECS_CSU_DMAADDRH12 (JECS_CSU_BASE+0x261*4) +#define JECS_CSU_DMAYSTEPL12 (JECS_CSU_BASE+0x262*4) +#define JECS_CSU_DMAYSTEPH12 (JECS_CSU_BASE+0x263*4) +#define JECS_CSU_DMAZSTEPL12 (JECS_CSU_BASE+0x264*4) +#define JECS_CSU_DMAZSTEPH12 (JECS_CSU_BASE+0x265*4) +#define JECS_CSU_DMAYNUMXNUM12 (JECS_CSU_BASE+0x266*4) +#define JECS_CSU_DMASIZEGRANALLNUM12 (JECS_CSU_BASE+0x267*4) +#define JECS_CSU_DMAADDRL13 (JECS_CSU_BASE+0x268*4) +#define JECS_CSU_DMAADDRH13 (JECS_CSU_BASE+0x269*4) +#define JECS_CSU_DMAYSTEPL13 (JECS_CSU_BASE+0x26A*4) +#define JECS_CSU_DMAYSTEPH13 (JECS_CSU_BASE+0x26B*4) +#define JECS_CSU_DMAZSTEPL13 (JECS_CSU_BASE+0x26C*4) +#define JECS_CSU_DMAZSTEPH13 (JECS_CSU_BASE+0x26D*4) +#define JECS_CSU_DMAYNUMXNUM13 (JECS_CSU_BASE+0x26E*4) +#define JECS_CSU_DMASIZEGRANALLNUM13 (JECS_CSU_BASE+0x26F*4) +#define JECS_CSU_DMAADDRL14 (JECS_CSU_BASE+0x270*4) +#define JECS_CSU_DMAADDRH14 (JECS_CSU_BASE+0x271*4) +#define JECS_CSU_DMAYSTEPL14 (JECS_CSU_BASE+0x272*4) +#define JECS_CSU_DMAYSTEPH14 (JECS_CSU_BASE+0x273*4) +#define JECS_CSU_DMAZSTEPL14 (JECS_CSU_BASE+0x274*4) +#define JECS_CSU_DMAZSTEPH14 (JECS_CSU_BASE+0x275*4) +#define JECS_CSU_DMAYNUMXNUM14 (JECS_CSU_BASE+0x276*4) +#define JECS_CSU_DMASIZEGRANALLNUM14 (JECS_CSU_BASE+0x277*4) +#define JECS_CSU_DMAADDRL15 (JECS_CSU_BASE+0x278*4) +#define JECS_CSU_DMAADDRH15 (JECS_CSU_BASE+0x279*4) +#define JECS_CSU_DMAYSTEPL15 (JECS_CSU_BASE+0x27A*4) +#define JECS_CSU_DMAYSTEPH15 (JECS_CSU_BASE+0x27B*4) +#define JECS_CSU_DMAZSTEPL15 (JECS_CSU_BASE+0x27C*4) +#define JECS_CSU_DMAZSTEPH15 (JECS_CSU_BASE+0x27D*4) +#define JECS_CSU_DMAYNUMXNUM15 (JECS_CSU_BASE+0x27E*4) +#define JECS_CSU_DMASIZEGRANALLNUM15 (JECS_CSU_BASE+0x27F*4) +#define JECS_CSU_DMAADDRL16 (JECS_CSU_BASE+0x280*4) +#define JECS_CSU_DMAADDRH16 (JECS_CSU_BASE+0x281*4) +#define JECS_CSU_DMAYSTEPL16 (JECS_CSU_BASE+0x282*4) +#define JECS_CSU_DMAYSTEPH16 (JECS_CSU_BASE+0x283*4) +#define JECS_CSU_DMAZSTEPL16 (JECS_CSU_BASE+0x284*4) +#define JECS_CSU_DMAZSTEPH16 (JECS_CSU_BASE+0x285*4) +#define JECS_CSU_DMAYNUMXNUM16 (JECS_CSU_BASE+0x286*4) +#define JECS_CSU_DMASIZEGRANALLNUM16 (JECS_CSU_BASE+0x287*4) +#define JECS_CSU_DMAADDRL17 (JECS_CSU_BASE+0x288*4) +#define JECS_CSU_DMAADDRH17 (JECS_CSU_BASE+0x289*4) +#define JECS_CSU_DMAYSTEPL17 (JECS_CSU_BASE+0x28A*4) +#define JECS_CSU_DMAYSTEPH17 (JECS_CSU_BASE+0x28B*4) +#define JECS_CSU_DMAZSTEPL17 (JECS_CSU_BASE+0x28C*4) +#define JECS_CSU_DMAZSTEPH17 (JECS_CSU_BASE+0x28D*4) +#define JECS_CSU_DMAYNUMXNUM17 (JECS_CSU_BASE+0x28E*4) +#define JECS_CSU_DMASIZEGRANALLNUM17 (JECS_CSU_BASE+0x28F*4) +#define JECS_CSU_DMAADDRL18 (JECS_CSU_BASE+0x290*4) +#define JECS_CSU_DMAADDRH18 (JECS_CSU_BASE+0x291*4) +#define JECS_CSU_DMAYSTEPL18 (JECS_CSU_BASE+0x292*4) +#define JECS_CSU_DMAYSTEPH18 (JECS_CSU_BASE+0x293*4) +#define JECS_CSU_DMAZSTEPL18 (JECS_CSU_BASE+0x294*4) +#define JECS_CSU_DMAZSTEPH18 (JECS_CSU_BASE+0x295*4) +#define JECS_CSU_DMAYNUMXNUM18 (JECS_CSU_BASE+0x296*4) +#define JECS_CSU_DMASIZEGRANALLNUM18 (JECS_CSU_BASE+0x297*4) +#define JECS_CSU_DMAADDRL19 (JECS_CSU_BASE+0x298*4) +#define JECS_CSU_DMAADDRH19 (JECS_CSU_BASE+0x299*4) +#define JECS_CSU_DMAYSTEPL19 (JECS_CSU_BASE+0x29A*4) +#define JECS_CSU_DMAYSTEPH19 (JECS_CSU_BASE+0x29B*4) +#define JECS_CSU_DMAZSTEPL19 (JECS_CSU_BASE+0x29C*4) +#define JECS_CSU_DMAZSTEPH19 (JECS_CSU_BASE+0x29D*4) +#define JECS_CSU_DMAYNUMXNUM19 (JECS_CSU_BASE+0x29E*4) +#define JECS_CSU_DMASIZEGRANALLNUM19 (JECS_CSU_BASE+0x29F*4) +#define JECS_CSU_DMAADDRL20 (JECS_CSU_BASE+0x2A0*4) +#define JECS_CSU_DMAADDRH20 (JECS_CSU_BASE+0x2A1*4) +#define JECS_CSU_DMAYSTEPL20 (JECS_CSU_BASE+0x2A2*4) +#define JECS_CSU_DMAYSTEPH20 (JECS_CSU_BASE+0x2A3*4) +#define JECS_CSU_DMAZSTEPL20 (JECS_CSU_BASE+0x2A4*4) +#define JECS_CSU_DMAZSTEPH20 (JECS_CSU_BASE+0x2A5*4) +#define JECS_CSU_DMAYNUMXNUM20 (JECS_CSU_BASE+0x2A6*4) +#define JECS_CSU_DMASIZEGRANALLNUM20 (JECS_CSU_BASE+0x2A7*4) +#define JECS_CSU_DMAADDRL21 (JECS_CSU_BASE+0x2A8*4) +#define JECS_CSU_DMAADDRH21 (JECS_CSU_BASE+0x2A9*4) +#define JECS_CSU_DMAYSTEPL21 (JECS_CSU_BASE+0x2AA*4) +#define JECS_CSU_DMAYSTEPH21 (JECS_CSU_BASE+0x2AB*4) +#define JECS_CSU_DMAZSTEPL21 (JECS_CSU_BASE+0x2AC*4) +#define JECS_CSU_DMAZSTEPH21 (JECS_CSU_BASE+0x2AD*4) +#define JECS_CSU_DMAYNUMXNUM21 (JECS_CSU_BASE+0x2AE*4) +#define JECS_CSU_DMASIZEGRANALLNUM21 (JECS_CSU_BASE+0x2AF*4) +#define JECS_CSU_DMAADDRL22 (JECS_CSU_BASE+0x2B0*4) +#define JECS_CSU_DMAADDRH22 (JECS_CSU_BASE+0x2B1*4) +#define JECS_CSU_DMAYSTEPL22 (JECS_CSU_BASE+0x2B2*4) +#define JECS_CSU_DMAYSTEPH22 (JECS_CSU_BASE+0x2B3*4) +#define JECS_CSU_DMAZSTEPL22 (JECS_CSU_BASE+0x2B4*4) +#define JECS_CSU_DMAZSTEPH22 (JECS_CSU_BASE+0x2B5*4) +#define JECS_CSU_DMAYNUMXNUM22 (JECS_CSU_BASE+0x2B6*4) +#define JECS_CSU_DMASIZEGRANALLNUM22 (JECS_CSU_BASE+0x2B7*4) +#define JECS_CSU_DMAADDRL23 (JECS_CSU_BASE+0x2B8*4) +#define JECS_CSU_DMAADDRH23 (JECS_CSU_BASE+0x2B9*4) +#define JECS_CSU_DMAYSTEPL23 (JECS_CSU_BASE+0x2BA*4) +#define JECS_CSU_DMAYSTEPH23 (JECS_CSU_BASE+0x2BB*4) +#define JECS_CSU_DMAZSTEPL23 (JECS_CSU_BASE+0x2BC*4) +#define JECS_CSU_DMAZSTEPH23 (JECS_CSU_BASE+0x2BD*4) +#define JECS_CSU_DMAYNUMXNUM23 (JECS_CSU_BASE+0x2BE*4) +#define JECS_CSU_DMASIZEGRANALLNUM23 (JECS_CSU_BASE+0x2BF*4) +#define JECS_CSU_DMAADDRL24 (JECS_CSU_BASE+0x2C0*4) +#define JECS_CSU_DMAADDRH24 (JECS_CSU_BASE+0x2C1*4) +#define JECS_CSU_DMAYSTEPL24 (JECS_CSU_BASE+0x2C2*4) +#define JECS_CSU_DMAYSTEPH24 (JECS_CSU_BASE+0x2C3*4) +#define JECS_CSU_DMAZSTEPL24 (JECS_CSU_BASE+0x2C4*4) +#define JECS_CSU_DMAZSTEPH24 (JECS_CSU_BASE+0x2C5*4) +#define JECS_CSU_DMAYNUMXNUM24 (JECS_CSU_BASE+0x2C6*4) +#define JECS_CSU_DMASIZEGRANALLNUM24 (JECS_CSU_BASE+0x2C7*4) +#define JECS_CSU_DMAADDRL25 (JECS_CSU_BASE+0x2C8*4) +#define JECS_CSU_DMAADDRH25 (JECS_CSU_BASE+0x2C9*4) +#define JECS_CSU_DMAYSTEPL25 (JECS_CSU_BASE+0x2CA*4) +#define JECS_CSU_DMAYSTEPH25 (JECS_CSU_BASE+0x2CB*4) +#define JECS_CSU_DMAZSTEPL25 (JECS_CSU_BASE+0x2CC*4) +#define JECS_CSU_DMAZSTEPH25 (JECS_CSU_BASE+0x2CD*4) +#define JECS_CSU_DMAYNUMXNUM25 (JECS_CSU_BASE+0x2CE*4) +#define JECS_CSU_DMASIZEGRANALLNUM25 (JECS_CSU_BASE+0x2CF*4) +#define JECS_CSU_DMAADDRL26 (JECS_CSU_BASE+0x2D0*4) +#define JECS_CSU_DMAADDRH26 (JECS_CSU_BASE+0x2D1*4) +#define JECS_CSU_DMAYSTEPL26 (JECS_CSU_BASE+0x2D2*4) +#define JECS_CSU_DMAYSTEPH26 (JECS_CSU_BASE+0x2D3*4) +#define JECS_CSU_DMAZSTEPL26 (JECS_CSU_BASE+0x2D4*4) +#define JECS_CSU_DMAZSTEPH26 (JECS_CSU_BASE+0x2D5*4) +#define JECS_CSU_DMAYNUMXNUM26 (JECS_CSU_BASE+0x2D6*4) +#define JECS_CSU_DMASIZEGRANALLNUM26 (JECS_CSU_BASE+0x2D7*4) +#define JECS_CSU_DMAADDRL27 (JECS_CSU_BASE+0x2D8*4) +#define JECS_CSU_DMAADDRH27 (JECS_CSU_BASE+0x2D9*4) +#define JECS_CSU_DMAYSTEPL27 (JECS_CSU_BASE+0x2DA*4) +#define JECS_CSU_DMAYSTEPH27 (JECS_CSU_BASE+0x2DB*4) +#define JECS_CSU_DMAZSTEPL27 (JECS_CSU_BASE+0x2DC*4) +#define JECS_CSU_DMAZSTEPH27 (JECS_CSU_BASE+0x2DD*4) +#define JECS_CSU_DMAYNUMXNUM27 (JECS_CSU_BASE+0x2DE*4) +#define JECS_CSU_DMASIZEGRANALLNUM27 (JECS_CSU_BASE+0x2DF*4) +#define JECS_CSU_DMAADDRL28 (JECS_CSU_BASE+0x2E0*4) +#define JECS_CSU_DMAADDRH28 (JECS_CSU_BASE+0x2E1*4) +#define JECS_CSU_DMAYSTEPL28 (JECS_CSU_BASE+0x2E2*4) +#define JECS_CSU_DMAYSTEPH28 (JECS_CSU_BASE+0x2E3*4) +#define JECS_CSU_DMAZSTEPL28 (JECS_CSU_BASE+0x2E4*4) +#define JECS_CSU_DMAZSTEPH28 (JECS_CSU_BASE+0x2E5*4) +#define JECS_CSU_DMAYNUMXNUM28 (JECS_CSU_BASE+0x2E6*4) +#define JECS_CSU_DMASIZEGRANALLNUM28 (JECS_CSU_BASE+0x2E7*4) +#define JECS_CSU_DMAADDRL29 (JECS_CSU_BASE+0x2E8*4) +#define JECS_CSU_DMAADDRH29 (JECS_CSU_BASE+0x2E9*4) +#define JECS_CSU_DMAYSTEPL29 (JECS_CSU_BASE+0x2EA*4) +#define JECS_CSU_DMAYSTEPH29 (JECS_CSU_BASE+0x2EB*4) +#define JECS_CSU_DMAZSTEPL29 (JECS_CSU_BASE+0x2EC*4) +#define JECS_CSU_DMAZSTEPH29 (JECS_CSU_BASE+0x2ED*4) +#define JECS_CSU_DMAYNUMXNUM29 (JECS_CSU_BASE+0x2EE*4) +#define JECS_CSU_DMASIZEGRANALLNUM29 (JECS_CSU_BASE+0x2EF*4) +#define JECS_CSU_DMAADDRL30 (JECS_CSU_BASE+0x2F0*4) +#define JECS_CSU_DMAADDRH30 (JECS_CSU_BASE+0x2F1*4) +#define JECS_CSU_DMAYSTEPL30 (JECS_CSU_BASE+0x2F2*4) +#define JECS_CSU_DMAYSTEPH30 (JECS_CSU_BASE+0x2F3*4) +#define JECS_CSU_DMAZSTEPL30 (JECS_CSU_BASE+0x2F4*4) +#define JECS_CSU_DMAZSTEPH30 (JECS_CSU_BASE+0x2F5*4) +#define JECS_CSU_DMAYNUMXNUM30 (JECS_CSU_BASE+0x2F6*4) +#define JECS_CSU_DMASIZEGRANALLNUM30 (JECS_CSU_BASE+0x2F7*4) +#define JECS_CSU_DMAADDRL31 (JECS_CSU_BASE+0x2F8*4) +#define JECS_CSU_DMAADDRH31 (JECS_CSU_BASE+0x2F9*4) +#define JECS_CSU_DMAYSTEPL31 (JECS_CSU_BASE+0x2FA*4) +#define JECS_CSU_DMAYSTEPH31 (JECS_CSU_BASE+0x2FB*4) +#define JECS_CSU_DMAZSTEPL31 (JECS_CSU_BASE+0x2FC*4) +#define JECS_CSU_DMAZSTEPH31 (JECS_CSU_BASE+0x2FD*4) +#define JECS_CSU_DMAYNUMXNUM31 (JECS_CSU_BASE+0x2FE*4) +#define JECS_CSU_DMASIZEGRANALLNUM31 (JECS_CSU_BASE+0x2FF*4) +#define JECS_CSU_SORTDATA_NUM (JECS_CSU_BASE+0x380*4) +#define JECS_CSU_SORTDATA_DATA0 (JECS_CSU_BASE+0x3C0*4) +#define JECS_CSU_SORTDATA_DATA1 (JECS_CSU_BASE+0x3C1*4) +#define JECS_CSU_SORTDATA_DATA2 (JECS_CSU_BASE+0x3C2*4) +#define JECS_CSU_SORTDATA_DATA3 (JECS_CSU_BASE+0x3C3*4) +#define JECS_CSU_SORTDATA_DATA4 (JECS_CSU_BASE+0x3C4*4) +#define JECS_CSU_SORTDATA_DATA5 (JECS_CSU_BASE+0x3C5*4) +#define JECS_CSU_SORTDATA_DATA6 (JECS_CSU_BASE+0x3C6*4) +#define JECS_CSU_SORTDATA_DATA7 (JECS_CSU_BASE+0x3C7*4) +#define JECS_CSU_SORTDATA_DATA8 (JECS_CSU_BASE+0x3C8*4) +#define JECS_CSU_SORTDATA_DATA9 (JECS_CSU_BASE+0x3C9*4) +#define JECS_CSU_SORTDATA_DATA10 (JECS_CSU_BASE+0x3CA*4) +#define JECS_CSU_SORTDATA_DATA11 (JECS_CSU_BASE+0x3CB*4) +#define JECS_CSU_SORTDATA_DATA12 (JECS_CSU_BASE+0x3CC*4) +#define JECS_CSU_SORTDATA_DATA13 (JECS_CSU_BASE+0x3CD*4) +#define JECS_CSU_SORTDATA_DATA14 (JECS_CSU_BASE+0x3CE*4) +#define JECS_CSU_SORTDATA_DATA15 (JECS_CSU_BASE+0x3CF*4) +#define JECS_CSU_SORTDATA_DATA16 (JECS_CSU_BASE+0x3D0*4) +#define JECS_CSU_SORTDATA_DATA17 (JECS_CSU_BASE+0x3D1*4) +#define JECS_CSU_SORTDATA_DATA18 (JECS_CSU_BASE+0x3D2*4) +#define JECS_CSU_SORTDATA_DATA19 (JECS_CSU_BASE+0x3D3*4) +#define JECS_CSU_SORTDATA_DATA20 (JECS_CSU_BASE+0x3D4*4) +#define JECS_CSU_SORTDATA_DATA21 (JECS_CSU_BASE+0x3D5*4) +#define JECS_CSU_SORTDATA_DATA22 (JECS_CSU_BASE+0x3D6*4) +#define JECS_CSU_SORTDATA_DATA23 (JECS_CSU_BASE+0x3D7*4) +#define JECS_CSU_SORTDATA_DATA24 (JECS_CSU_BASE+0x3D8*4) +#define JECS_CSU_SORTDATA_DATA25 (JECS_CSU_BASE+0x3D9*4) +#define JECS_CSU_SORTDATA_DATA26 (JECS_CSU_BASE+0x3DA*4) +#define JECS_CSU_SORTDATA_DATA27 (JECS_CSU_BASE+0x3DB*4) +#define JECS_CSU_SORTDATA_DATA28 (JECS_CSU_BASE+0x3DC*4) +#define JECS_CSU_SORTDATA_DATA29 (JECS_CSU_BASE+0x3DD*4) +#define JECS_CSU_SORTDATA_DATA30 (JECS_CSU_BASE+0x3DE*4) +#define JECS_CSU_SORTDATA_DATA31 (JECS_CSU_BASE+0x3DF*4) +#define JECS_CSU_SORTDATA_ID0 (JECS_CSU_BASE+0x3E0*4) +#define JECS_CSU_SORTDATA_ID1 (JECS_CSU_BASE+0x3E1*4) +#define JECS_CSU_SORTDATA_ID2 (JECS_CSU_BASE+0x3E2*4) +#define JECS_CSU_SORTDATA_ID3 (JECS_CSU_BASE+0x3E3*4) +#define JECS_CSU_SORTDATA_ID4 (JECS_CSU_BASE+0x3E4*4) +#define JECS_CSU_SORTDATA_ID5 (JECS_CSU_BASE+0x3E5*4) +#define JECS_CSU_SORTDATA_ID6 (JECS_CSU_BASE+0x3E6*4) +#define JECS_CSU_SORTDATA_ID7 (JECS_CSU_BASE+0x3E7*4) +#define JECS_CSU_SORTDATA_ID8 (JECS_CSU_BASE+0x3E8*4) +#define JECS_CSU_SORTDATA_ID9 (JECS_CSU_BASE+0x3E9*4) +#define JECS_CSU_SORTDATA_ID10 (JECS_CSU_BASE+0x3EA*4) +#define JECS_CSU_SORTDATA_ID11 (JECS_CSU_BASE+0x3EB*4) +#define JECS_CSU_SORTDATA_ID12 (JECS_CSU_BASE+0x3EC*4) +#define JECS_CSU_SORTDATA_ID13 (JECS_CSU_BASE+0x3ED*4) +#define JECS_CSU_SORTDATA_ID14 (JECS_CSU_BASE+0x3EE*4) +#define JECS_CSU_SORTDATA_ID15 (JECS_CSU_BASE+0x3EF*4) +#define JECS_CSU_SORTDATA_ID16 (JECS_CSU_BASE+0x3F0*4) +#define JECS_CSU_SORTDATA_ID17 (JECS_CSU_BASE+0x3F1*4) +#define JECS_CSU_SORTDATA_ID18 (JECS_CSU_BASE+0x3F2*4) +#define JECS_CSU_SORTDATA_ID19 (JECS_CSU_BASE+0x3F3*4) +#define JECS_CSU_SORTDATA_ID20 (JECS_CSU_BASE+0x3F4*4) +#define JECS_CSU_SORTDATA_ID21 (JECS_CSU_BASE+0x3F5*4) +#define JECS_CSU_SORTDATA_ID22 (JECS_CSU_BASE+0x3F6*4) +#define JECS_CSU_SORTDATA_ID23 (JECS_CSU_BASE+0x3F7*4) +#define JECS_CSU_SORTDATA_ID24 (JECS_CSU_BASE+0x3F8*4) +#define JECS_CSU_SORTDATA_ID25 (JECS_CSU_BASE+0x3F9*4) +#define JECS_CSU_SORTDATA_ID26 (JECS_CSU_BASE+0x3FA*4) +#define JECS_CSU_SORTDATA_ID27 (JECS_CSU_BASE+0x3FB*4) +#define JECS_CSU_SORTDATA_ID28 (JECS_CSU_BASE+0x3FC*4) +#define JECS_CSU_SORTDATA_ID29 (JECS_CSU_BASE+0x3FD*4) +#define JECS_CSU_SORTDATA_ID30 (JECS_CSU_BASE+0x3FE*4) +#define JECS_CSU_SORTDATA_ID31 (JECS_CSU_BASE+0x3FF*4) +#define JECS_CSU_CPRITX0RFPSET (JECS_CSU_BASE+0x47E*4) +#define JECS_CSU_CPRITX0PORTINFO0 (JECS_CSU_BASE+0x400*4) +#define JECS_CSU_CPRITX0PORTINFO1 (JECS_CSU_BASE+0x401*4) +#define JECS_CSU_CPRITX0PORTINFO2 (JECS_CSU_BASE+0x402*4) +#define JECS_CSU_CPRITX0PORTINFO3 (JECS_CSU_BASE+0x403*4) +#define JECS_CSU_CPRITX0PORTINFO4 (JECS_CSU_BASE+0x404*4) +#define JECS_CSU_CPRITX0PORTINFO5 (JECS_CSU_BASE+0x405*4) +#define JECS_CSU_CPRITX0PORTINFO6 (JECS_CSU_BASE+0x406*4) +#define JECS_CSU_CPRITX0PORTINFO7 (JECS_CSU_BASE+0x407*4) +#define JECS_CSU_CPRITX0PORTINFO8 (JECS_CSU_BASE+0x408*4) +#define JECS_CSU_CPRITX0PORTINFO9 (JECS_CSU_BASE+0x409*4) +#define JECS_CSU_CPRITX0PORTINFO10 (JECS_CSU_BASE+0x40A*4) +#define JECS_CSU_CPRITX0PORTINFO11 (JECS_CSU_BASE+0x40B*4) +#define JECS_CSU_CPRITX0PORTINFO12 (JECS_CSU_BASE+0x40C*4) +#define JECS_CSU_CPRITX0PORTINFO13 (JECS_CSU_BASE+0x40D*4) +#define JECS_CSU_CPRITX0PORTINFO14 (JECS_CSU_BASE+0x40E*4) +#define JECS_CSU_CPRITX0PORTINFO15 (JECS_CSU_BASE+0x40F*4) +#define JECS_CSU_CPRITX0PORTINFO16 (JECS_CSU_BASE+0x410*4) +#define JECS_CSU_CPRITX0PORTINFO17 (JECS_CSU_BASE+0x411*4) +#define JECS_CSU_CPRITX0PORTINFO18 (JECS_CSU_BASE+0x412*4) +#define JECS_CSU_CPRITX0PORTINFO19 (JECS_CSU_BASE+0x413*4) +#define JECS_CSU_CPRITX0PORTINFO20 (JECS_CSU_BASE+0x414*4) +#define JECS_CSU_CPRITX0PORTINFO21 (JECS_CSU_BASE+0x415*4) +#define JECS_CSU_CPRITX0PORTINFO22 (JECS_CSU_BASE+0x416*4) +#define JECS_CSU_CPRITX0PORTINFO23 (JECS_CSU_BASE+0x417*4) +#define JECS_CSU_CPRITX0PORTINFO24 (JECS_CSU_BASE+0x418*4) +#define JECS_CSU_CPRITX0PORTINFO25 (JECS_CSU_BASE+0x419*4) +#define JECS_CSU_CPRITX0PORTINFO26 (JECS_CSU_BASE+0x41A*4) +#define JECS_CSU_CPRITX0PORTINFO27 (JECS_CSU_BASE+0x41B*4) +#define JECS_CSU_CPRITX0PORTINFO28 (JECS_CSU_BASE+0x41C*4) +#define JECS_CSU_CPRITX0PORTINFO29 (JECS_CSU_BASE+0x41D*4) +#define JECS_CSU_CPRITX0PORTINFO30 (JECS_CSU_BASE+0x41E*4) +#define JECS_CSU_CPRITX0PORTINFO31 (JECS_CSU_BASE+0x41F*4) +#define JECS_CSU_CPRITX0PORTINFO32 (JECS_CSU_BASE+0x420*4) +#define JECS_CSU_CPRITX0PORTINFO33 (JECS_CSU_BASE+0x421*4) +#define JECS_CSU_CPRITX0PORTINFO34 (JECS_CSU_BASE+0x422*4) +#define JECS_CSU_CPRITX0PORTINFO35 (JECS_CSU_BASE+0x423*4) +#define JECS_CSU_CPRITX0PORTINFO36 (JECS_CSU_BASE+0x424*4) +#define JECS_CSU_CPRITX0PORTINFO37 (JECS_CSU_BASE+0x425*4) +#define JECS_CSU_CPRITX0PORTINFO38 (JECS_CSU_BASE+0x426*4) +#define JECS_CSU_CPRITX0PORTINFO39 (JECS_CSU_BASE+0x427*4) +#define JECS_CSU_CPRITX0PORTINFO40 (JECS_CSU_BASE+0x428*4) +#define JECS_CSU_CPRITX0PORTINFO41 (JECS_CSU_BASE+0x429*4) +#define JECS_CSU_CPRITX0PORTINFO42 (JECS_CSU_BASE+0x42A*4) +#define JECS_CSU_CPRITX0PORTINFO43 (JECS_CSU_BASE+0x42B*4) +#define JECS_CSU_CPRITX0PORTINFO44 (JECS_CSU_BASE+0x42C*4) +#define JECS_CSU_CPRITX0PORTINFO45 (JECS_CSU_BASE+0x42D*4) +#define JECS_CSU_CPRITX0PORTINFO46 (JECS_CSU_BASE+0x42E*4) +#define JECS_CSU_CPRITX0PORTINFO47 (JECS_CSU_BASE+0x42F*4) +#define JECS_CSU_CPRITX0PORTINFO48 (JECS_CSU_BASE+0x430*4) +#define JECS_CSU_CPRITX0PORTINFO49 (JECS_CSU_BASE+0x431*4) +#define JECS_CSU_CPRITX0PORTINFO50 (JECS_CSU_BASE+0x432*4) +#define JECS_CSU_CPRITX0PORTINFO51 (JECS_CSU_BASE+0x433*4) +#define JECS_CSU_CPRITX0PORTINFO52 (JECS_CSU_BASE+0x434*4) +#define JECS_CSU_CPRITX0PORTINFO53 (JECS_CSU_BASE+0x435*4) +#define JECS_CSU_CPRITX0PORTINFO54 (JECS_CSU_BASE+0x436*4) +#define JECS_CSU_CPRITX0PORTINFO55 (JECS_CSU_BASE+0x437*4) +#define JECS_CSU_CPRITX0PORTINFO56 (JECS_CSU_BASE+0x438*4) +#define JECS_CSU_CPRITX0PORTINFO57 (JECS_CSU_BASE+0x439*4) +#define JECS_CSU_CPRITX0PORTINFO58 (JECS_CSU_BASE+0x43A*4) +#define JECS_CSU_CPRITX0PORTINFO59 (JECS_CSU_BASE+0x43B*4) +#define JECS_CSU_CPRITX0PORTINFO60 (JECS_CSU_BASE+0x43C*4) +#define JECS_CSU_CPRITX0PORTINFO61 (JECS_CSU_BASE+0x43D*4) +#define JECS_CSU_CPRITX0PORTINFO62 (JECS_CSU_BASE+0x43E*4) +#define JECS_CSU_CPRITX0PORTINFO63 (JECS_CSU_BASE+0x43F*4) +#define JECS_CSU_CPRITX0LATCHINFOL0 (JECS_CSU_BASE+0x450*4) +#define JECS_CSU_CPRITX0LATCHINFOL1 (JECS_CSU_BASE+0x451*4) +#define JECS_CSU_CPRITX0LATCHINFOL2 (JECS_CSU_BASE+0x452*4) +#define JECS_CSU_CPRITX0LATCHINFOL3 (JECS_CSU_BASE+0x453*4) +#define JECS_CSU_CPRITX0LATCHINFOL4 (JECS_CSU_BASE+0x454*4) +#define JECS_CSU_CPRITX0LATCHINFOL5 (JECS_CSU_BASE+0x455*4) +#define JECS_CSU_CPRITX0LATCHINFOL6 (JECS_CSU_BASE+0x456*4) +#define JECS_CSU_CPRITX0LATCHINFOL7 (JECS_CSU_BASE+0x457*4) +#define JECS_CSU_CPRITX0LATCHINFOM0 (JECS_CSU_BASE+0x440*4) +#define JECS_CSU_CPRITX0LATCHINFOM1 (JECS_CSU_BASE+0x441*4) +#define JECS_CSU_CPRITX0LATCHINFOM2 (JECS_CSU_BASE+0x442*4) +#define JECS_CSU_CPRITX0LATCHINFOM3 (JECS_CSU_BASE+0x443*4) +#define JECS_CSU_CPRITX0LATCHINFOM4 (JECS_CSU_BASE+0x444*4) +#define JECS_CSU_CPRITX0LATCHINFOM5 (JECS_CSU_BASE+0x445*4) +#define JECS_CSU_CPRITX0LATCHINFOM6 (JECS_CSU_BASE+0x446*4) +#define JECS_CSU_CPRITX0LATCHINFOM7 (JECS_CSU_BASE+0x447*4) +#define JECS_CSU_CPRITX0LATCHINFOH0 (JECS_CSU_BASE+0x448*4) +#define JECS_CSU_CPRITX0LATCHINFOH1 (JECS_CSU_BASE+0x449*4) +#define JECS_CSU_CPRITX0LATCHINFOH2 (JECS_CSU_BASE+0x44A*4) +#define JECS_CSU_CPRITX0LATCHINFOH3 (JECS_CSU_BASE+0x44B*4) +#define JECS_CSU_CPRITX0LATCHINFOH4 (JECS_CSU_BASE+0x44C*4) +#define JECS_CSU_CPRITX0LATCHINFOH5 (JECS_CSU_BASE+0x44D*4) +#define JECS_CSU_CPRITX0LATCHINFOH6 (JECS_CSU_BASE+0x44E*4) +#define JECS_CSU_CPRITX0LATCHINFOH7 (JECS_CSU_BASE+0x44F*4) +#define JECS_CSU_CPRITX0ONWORK (JECS_CSU_BASE+0x47F*4) +#define JECS_CSU_CPRIRX0RFPSET (JECS_CSU_BASE+0x4FE*4) +#define JECS_CSU_CPRIRX0PORTINFO0 (JECS_CSU_BASE+0x480*4) +#define JECS_CSU_CPRIRX0PORTINFO1 (JECS_CSU_BASE+0x481*4) +#define JECS_CSU_CPRIRX0PORTINFO2 (JECS_CSU_BASE+0x482*4) +#define JECS_CSU_CPRIRX0PORTINFO3 (JECS_CSU_BASE+0x483*4) +#define JECS_CSU_CPRIRX0PORTINFO4 (JECS_CSU_BASE+0x484*4) +#define JECS_CSU_CPRIRX0PORTINFO5 (JECS_CSU_BASE+0x485*4) +#define JECS_CSU_CPRIRX0PORTINFO6 (JECS_CSU_BASE+0x486*4) +#define JECS_CSU_CPRIRX0PORTINFO7 (JECS_CSU_BASE+0x487*4) +#define JECS_CSU_CPRIRX0PORTINFO8 (JECS_CSU_BASE+0x488*4) +#define JECS_CSU_CPRIRX0PORTINFO9 (JECS_CSU_BASE+0x489*4) +#define JECS_CSU_CPRIRX0PORTINFO10 (JECS_CSU_BASE+0x48A*4) +#define JECS_CSU_CPRIRX0PORTINFO11 (JECS_CSU_BASE+0x48B*4) +#define JECS_CSU_CPRIRX0PORTINFO12 (JECS_CSU_BASE+0x48C*4) +#define JECS_CSU_CPRIRX0PORTINFO13 (JECS_CSU_BASE+0x48D*4) +#define JECS_CSU_CPRIRX0PORTINFO14 (JECS_CSU_BASE+0x48E*4) +#define JECS_CSU_CPRIRX0PORTINFO15 (JECS_CSU_BASE+0x48F*4) +#define JECS_CSU_CPRIRX0PORTINFO16 (JECS_CSU_BASE+0x490*4) +#define JECS_CSU_CPRIRX0PORTINFO17 (JECS_CSU_BASE+0x491*4) +#define JECS_CSU_CPRIRX0PORTINFO18 (JECS_CSU_BASE+0x492*4) +#define JECS_CSU_CPRIRX0PORTINFO19 (JECS_CSU_BASE+0x493*4) +#define JECS_CSU_CPRIRX0PORTINFO20 (JECS_CSU_BASE+0x494*4) +#define JECS_CSU_CPRIRX0PORTINFO21 (JECS_CSU_BASE+0x495*4) +#define JECS_CSU_CPRIRX0PORTINFO22 (JECS_CSU_BASE+0x496*4) +#define JECS_CSU_CPRIRX0PORTINFO23 (JECS_CSU_BASE+0x497*4) +#define JECS_CSU_CPRIRX0PORTINFO24 (JECS_CSU_BASE+0x498*4) +#define JECS_CSU_CPRIRX0PORTINFO25 (JECS_CSU_BASE+0x499*4) +#define JECS_CSU_CPRIRX0PORTINFO26 (JECS_CSU_BASE+0x49A*4) +#define JECS_CSU_CPRIRX0PORTINFO27 (JECS_CSU_BASE+0x49B*4) +#define JECS_CSU_CPRIRX0PORTINFO28 (JECS_CSU_BASE+0x49C*4) +#define JECS_CSU_CPRIRX0PORTINFO29 (JECS_CSU_BASE+0x49D*4) +#define JECS_CSU_CPRIRX0PORTINFO30 (JECS_CSU_BASE+0x49E*4) +#define JECS_CSU_CPRIRX0PORTINFO31 (JECS_CSU_BASE+0x49F*4) +#define JECS_CSU_CPRIRX0PORTINFO32 (JECS_CSU_BASE+0x4A0*4) +#define JECS_CSU_CPRIRX0PORTINFO33 (JECS_CSU_BASE+0x4A1*4) +#define JECS_CSU_CPRIRX0PORTINFO34 (JECS_CSU_BASE+0x4A2*4) +#define JECS_CSU_CPRIRX0PORTINFO35 (JECS_CSU_BASE+0x4A3*4) +#define JECS_CSU_CPRIRX0PORTINFO36 (JECS_CSU_BASE+0x4A4*4) +#define JECS_CSU_CPRIRX0PORTINFO37 (JECS_CSU_BASE+0x4A5*4) +#define JECS_CSU_CPRIRX0PORTINFO38 (JECS_CSU_BASE+0x4A6*4) +#define JECS_CSU_CPRIRX0PORTINFO39 (JECS_CSU_BASE+0x4A7*4) +#define JECS_CSU_CPRIRX0PORTINFO40 (JECS_CSU_BASE+0x4A8*4) +#define JECS_CSU_CPRIRX0PORTINFO41 (JECS_CSU_BASE+0x4A9*4) +#define JECS_CSU_CPRIRX0PORTINFO42 (JECS_CSU_BASE+0x4AA*4) +#define JECS_CSU_CPRIRX0PORTINFO43 (JECS_CSU_BASE+0x4AB*4) +#define JECS_CSU_CPRIRX0PORTINFO44 (JECS_CSU_BASE+0x4AC*4) +#define JECS_CSU_CPRIRX0PORTINFO45 (JECS_CSU_BASE+0x4AD*4) +#define JECS_CSU_CPRIRX0PORTINFO46 (JECS_CSU_BASE+0x4AE*4) +#define JECS_CSU_CPRIRX0PORTINFO47 (JECS_CSU_BASE+0x4AF*4) +#define JECS_CSU_CPRIRX0PORTINFO48 (JECS_CSU_BASE+0x4B0*4) +#define JECS_CSU_CPRIRX0PORTINFO49 (JECS_CSU_BASE+0x4B1*4) +#define JECS_CSU_CPRIRX0PORTINFO50 (JECS_CSU_BASE+0x4B2*4) +#define JECS_CSU_CPRIRX0PORTINFO51 (JECS_CSU_BASE+0x4B3*4) +#define JECS_CSU_CPRIRX0PORTINFO52 (JECS_CSU_BASE+0x4B4*4) +#define JECS_CSU_CPRIRX0PORTINFO53 (JECS_CSU_BASE+0x4B5*4) +#define JECS_CSU_CPRIRX0PORTINFO54 (JECS_CSU_BASE+0x4B6*4) +#define JECS_CSU_CPRIRX0PORTINFO55 (JECS_CSU_BASE+0x4B7*4) +#define JECS_CSU_CPRIRX0PORTINFO56 (JECS_CSU_BASE+0x4B8*4) +#define JECS_CSU_CPRIRX0PORTINFO57 (JECS_CSU_BASE+0x4B9*4) +#define JECS_CSU_CPRIRX0PORTINFO58 (JECS_CSU_BASE+0x4BA*4) +#define JECS_CSU_CPRIRX0PORTINFO59 (JECS_CSU_BASE+0x4BB*4) +#define JECS_CSU_CPRIRX0PORTINFO60 (JECS_CSU_BASE+0x4BC*4) +#define JECS_CSU_CPRIRX0PORTINFO61 (JECS_CSU_BASE+0x4BD*4) +#define JECS_CSU_CPRIRX0PORTINFO62 (JECS_CSU_BASE+0x4BE*4) +#define JECS_CSU_CPRIRX0PORTINFO63 (JECS_CSU_BASE+0x4BF*4) +#define JECS_CSU_CPRIRX0LATCHINFOL0 (JECS_CSU_BASE+0x4D0*4) +#define JECS_CSU_CPRIRX0LATCHINFOL1 (JECS_CSU_BASE+0x4D1*4) +#define JECS_CSU_CPRIRX0LATCHINFOL2 (JECS_CSU_BASE+0x4D2*4) +#define JECS_CSU_CPRIRX0LATCHINFOL3 (JECS_CSU_BASE+0x4D3*4) +#define JECS_CSU_CPRIRX0LATCHINFOL4 (JECS_CSU_BASE+0x4D4*4) +#define JECS_CSU_CPRIRX0LATCHINFOL5 (JECS_CSU_BASE+0x4D5*4) +#define JECS_CSU_CPRIRX0LATCHINFOL6 (JECS_CSU_BASE+0x4D6*4) +#define JECS_CSU_CPRIRX0LATCHINFOL7 (JECS_CSU_BASE+0x4D7*4) +#define JECS_CSU_CPRIRX0LATCHINFOH0 (JECS_CSU_BASE+0x4C0*4) +#define JECS_CSU_CPRIRX0LATCHINFOH1 (JECS_CSU_BASE+0x4C1*4) +#define JECS_CSU_CPRIRX0LATCHINFOH2 (JECS_CSU_BASE+0x4C2*4) +#define JECS_CSU_CPRIRX0LATCHINFOH3 (JECS_CSU_BASE+0x4C3*4) +#define JECS_CSU_CPRIRX0LATCHINFOH4 (JECS_CSU_BASE+0x4C4*4) +#define JECS_CSU_CPRIRX0LATCHINFOH5 (JECS_CSU_BASE+0x4C5*4) +#define JECS_CSU_CPRIRX0LATCHINFOH6 (JECS_CSU_BASE+0x4C6*4) +#define JECS_CSU_CPRIRX0LATCHINFOH7 (JECS_CSU_BASE+0x4C7*4) +#define JECS_CSU_CPRIRX0CYCLENUM0 (JECS_CSU_BASE+0x4C8*4) +#define JECS_CSU_CPRIRX0CYCLENUM1 (JECS_CSU_BASE+0x4C9*4) +#define JECS_CSU_CPRIRX0CYCLENUM2 (JECS_CSU_BASE+0x4CA*4) +#define JECS_CSU_CPRIRX0CYCLENUM3 (JECS_CSU_BASE+0x4CB*4) +#define JECS_CSU_CPRIRX0CYCLENUM4 (JECS_CSU_BASE+0x4CC*4) +#define JECS_CSU_CPRIRX0CYCLENUM5 (JECS_CSU_BASE+0x4CD*4) +#define JECS_CSU_CPRIRX0CYCLENUM6 (JECS_CSU_BASE+0x4CE*4) +#define JECS_CSU_CPRIRX0CYCLENUM7 (JECS_CSU_BASE+0x4CF*4) +#define JECS_CSU_CPRIRX0ONWORK (JECS_CSU_BASE+0x4FF*4) +#define JECS_CSU_CPRITX1ONWORK (JECS_CSU_BASE+0x57F*4) +#define JECS_CSU_CPRIRX1ONWORK (JECS_CSU_BASE+0x5FF*4) +#define JECS_CSU_ECPRIPARA0_0 (JECS_CSU_BASE+0x600*4) +#define JECS_CSU_ECPRIPARA0_1 (JECS_CSU_BASE+0x601*4) +#define JECS_CSU_ECPRIPARA0_2 (JECS_CSU_BASE+0x602*4) +#define JECS_CSU_ECPRIPARA0_3 (JECS_CSU_BASE+0x603*4) +#define JECS_CSU_ECPRIPARA0_4 (JECS_CSU_BASE+0x604*4) +#define JECS_CSU_ECPRIPARA0_5 (JECS_CSU_BASE+0x605*4) +#define JECS_CSU_ECPRIPARA0_6 (JECS_CSU_BASE+0x606*4) +#define JECS_CSU_ECPRIPARA0_7 (JECS_CSU_BASE+0x607*4) +#define JECS_CSU_ECPRIPARA1_0 (JECS_CSU_BASE+0x608*4) +#define JECS_CSU_ECPRIPARA1_1 (JECS_CSU_BASE+0x609*4) +#define JECS_CSU_ECPRIPARA1_2 (JECS_CSU_BASE+0x60A*4) +#define JECS_CSU_ECPRIPARA1_3 (JECS_CSU_BASE+0x60B*4) +#define JECS_CSU_ECPRIPARA1_4 (JECS_CSU_BASE+0x60C*4) +#define JECS_CSU_ECPRIPARA1_5 (JECS_CSU_BASE+0x60D*4) +#define JECS_CSU_ECPRIPARA1_6 (JECS_CSU_BASE+0x60E*4) +#define JECS_CSU_ECPRIPARA1_7 (JECS_CSU_BASE+0x60F*4) +#define JECS_CSU_ECPRIPARA2_0 (JECS_CSU_BASE+0x610*4) +#define JECS_CSU_ECPRIPARA2_1 (JECS_CSU_BASE+0x611*4) +#define JECS_CSU_ECPRIPARA2_2 (JECS_CSU_BASE+0x612*4) +#define JECS_CSU_ECPRIPARA2_3 (JECS_CSU_BASE+0x613*4) +#define JECS_CSU_ECPRIPARA2_4 (JECS_CSU_BASE+0x614*4) +#define JECS_CSU_ECPRIPARA2_5 (JECS_CSU_BASE+0x615*4) +#define JECS_CSU_ECPRIPARA2_6 (JECS_CSU_BASE+0x616*4) +#define JECS_CSU_ECPRIPARA2_7 (JECS_CSU_BASE+0x617*4) +#define JECS_CSU_ECPRIPARA3_0 (JECS_CSU_BASE+0x618*4) +#define JECS_CSU_ECPRIPARA3_1 (JECS_CSU_BASE+0x619*4) +#define JECS_CSU_ECPRIPARA3_2 (JECS_CSU_BASE+0x61A*4) +#define JECS_CSU_ECPRIPARA3_3 (JECS_CSU_BASE+0x61B*4) +#define JECS_CSU_ECPRIPARA3_4 (JECS_CSU_BASE+0x61C*4) +#define JECS_CSU_ECPRIPARA3_5 (JECS_CSU_BASE+0x61D*4) +#define JECS_CSU_ECPRIPARA3_6 (JECS_CSU_BASE+0x61E*4) +#define JECS_CSU_ECPRIPARA3_7 (JECS_CSU_BASE+0x61F*4) +#define JECS_CSU_ECPRIPARA4_0 (JECS_CSU_BASE+0x620*4) +#define JECS_CSU_ECPRIPARA4_1 (JECS_CSU_BASE+0x621*4) +#define JECS_CSU_ECPRIPARA4_2 (JECS_CSU_BASE+0x622*4) +#define JECS_CSU_ECPRIPARA4_3 (JECS_CSU_BASE+0x623*4) +#define JECS_CSU_ECPRIPARA4_4 (JECS_CSU_BASE+0x624*4) +#define JECS_CSU_ECPRIPARA4_5 (JECS_CSU_BASE+0x625*4) +#define JECS_CSU_ECPRIPARA4_6 (JECS_CSU_BASE+0x626*4) +#define JECS_CSU_ECPRIPARA4_7 (JECS_CSU_BASE+0x627*4) +#define JECS_CSU_ECPRIPARA5_0 (JECS_CSU_BASE+0x628*4) +#define JECS_CSU_ECPRIPARA5_1 (JECS_CSU_BASE+0x629*4) +#define JECS_CSU_ECPRIPARA5_2 (JECS_CSU_BASE+0x62A*4) +#define JECS_CSU_ECPRIPARA5_3 (JECS_CSU_BASE+0x62B*4) +#define JECS_CSU_ECPRIPARA5_4 (JECS_CSU_BASE+0x62C*4) +#define JECS_CSU_ECPRIPARA5_5 (JECS_CSU_BASE+0x62D*4) +#define JECS_CSU_ECPRIPARA5_6 (JECS_CSU_BASE+0x62E*4) +#define JECS_CSU_ECPRIPARA5_7 (JECS_CSU_BASE+0x62F*4) +#define JECS_CSU_ECPRIPARA6_0 (JECS_CSU_BASE+0x630*4) +#define JECS_CSU_ECPRIPARA6_1 (JECS_CSU_BASE+0x631*4) +#define JECS_CSU_ECPRIPARA6_2 (JECS_CSU_BASE+0x632*4) +#define JECS_CSU_ECPRIPARA6_3 (JECS_CSU_BASE+0x633*4) +#define JECS_CSU_ECPRIPARA6_4 (JECS_CSU_BASE+0x634*4) +#define JECS_CSU_ECPRIPARA6_5 (JECS_CSU_BASE+0x635*4) +#define JECS_CSU_ECPRIPARA6_6 (JECS_CSU_BASE+0x636*4) +#define JECS_CSU_ECPRIPARA6_7 (JECS_CSU_BASE+0x637*4) +#define JECS_CSU_ECPRIPARA7_0 (JECS_CSU_BASE+0x638*4) +#define JECS_CSU_ECPRIPARA7_1 (JECS_CSU_BASE+0x639*4) +#define JECS_CSU_ECPRIPARA7_2 (JECS_CSU_BASE+0x63A*4) +#define JECS_CSU_ECPRIPARA7_3 (JECS_CSU_BASE+0x63B*4) +#define JECS_CSU_ECPRIPARA7_4 (JECS_CSU_BASE+0x63C*4) +#define JECS_CSU_ECPRIPARA7_5 (JECS_CSU_BASE+0x63D*4) +#define JECS_CSU_ECPRIPARA7_6 (JECS_CSU_BASE+0x63E*4) +#define JECS_CSU_ECPRIPARA7_7 (JECS_CSU_BASE+0x63F*4) +#define JECS_CSU_ECPRIPARA8_0 (JECS_CSU_BASE+0x640*4) +#define JECS_CSU_ECPRIPARA8_1 (JECS_CSU_BASE+0x641*4) +#define JECS_CSU_ECPRIPARA8_2 (JECS_CSU_BASE+0x642*4) +#define JECS_CSU_ECPRIPARA8_3 (JECS_CSU_BASE+0x643*4) +#define JECS_CSU_ECPRIPARA8_4 (JECS_CSU_BASE+0x644*4) +#define JECS_CSU_ECPRIPARA8_5 (JECS_CSU_BASE+0x645*4) +#define JECS_CSU_ECPRIPARA8_6 (JECS_CSU_BASE+0x646*4) +#define JECS_CSU_ECPRIPARA8_7 (JECS_CSU_BASE+0x647*4) +#define JECS_CSU_ECPRIPARA9_0 (JECS_CSU_BASE+0x648*4) +#define JECS_CSU_ECPRIPARA9_1 (JECS_CSU_BASE+0x649*4) +#define JECS_CSU_ECPRIPARA9_2 (JECS_CSU_BASE+0x64A*4) +#define JECS_CSU_ECPRIPARA9_3 (JECS_CSU_BASE+0x64B*4) +#define JECS_CSU_ECPRIPARA9_4 (JECS_CSU_BASE+0x64C*4) +#define JECS_CSU_ECPRIPARA9_5 (JECS_CSU_BASE+0x64D*4) +#define JECS_CSU_ECPRIPARA9_6 (JECS_CSU_BASE+0x64E*4) +#define JECS_CSU_ECPRIPARA9_7 (JECS_CSU_BASE+0x64F*4) +#define JECS_CSU_ECPRIPARA10_0 (JECS_CSU_BASE+0x650*4) +#define JECS_CSU_ECPRIPARA10_1 (JECS_CSU_BASE+0x651*4) +#define JECS_CSU_ECPRIPARA10_2 (JECS_CSU_BASE+0x652*4) +#define JECS_CSU_ECPRIPARA10_3 (JECS_CSU_BASE+0x653*4) +#define JECS_CSU_ECPRIPARA10_4 (JECS_CSU_BASE+0x654*4) +#define JECS_CSU_ECPRIPARA10_5 (JECS_CSU_BASE+0x655*4) +#define JECS_CSU_ECPRIPARA10_6 (JECS_CSU_BASE+0x656*4) +#define JECS_CSU_ECPRIPARA10_7 (JECS_CSU_BASE+0x657*4) +#define JECS_CSU_ECPRIPARA11_0 (JECS_CSU_BASE+0x658*4) +#define JECS_CSU_ECPRIPARA11_1 (JECS_CSU_BASE+0x659*4) +#define JECS_CSU_ECPRIPARA11_2 (JECS_CSU_BASE+0x65A*4) +#define JECS_CSU_ECPRIPARA11_3 (JECS_CSU_BASE+0x65B*4) +#define JECS_CSU_ECPRIPARA11_4 (JECS_CSU_BASE+0x65C*4) +#define JECS_CSU_ECPRIPARA11_5 (JECS_CSU_BASE+0x65D*4) +#define JECS_CSU_ECPRIPARA11_6 (JECS_CSU_BASE+0x65E*4) +#define JECS_CSU_ECPRIPARA11_7 (JECS_CSU_BASE+0x65F*4) +#define JECS_CSU_ECPRIPARA12_0 (JECS_CSU_BASE+0x660*4) +#define JECS_CSU_ECPRIPARA12_1 (JECS_CSU_BASE+0x661*4) +#define JECS_CSU_ECPRIPARA12_2 (JECS_CSU_BASE+0x662*4) +#define JECS_CSU_ECPRIPARA12_3 (JECS_CSU_BASE+0x663*4) +#define JECS_CSU_ECPRIPARA12_4 (JECS_CSU_BASE+0x664*4) +#define JECS_CSU_ECPRIPARA12_5 (JECS_CSU_BASE+0x665*4) +#define JECS_CSU_ECPRIPARA12_6 (JECS_CSU_BASE+0x666*4) +#define JECS_CSU_ECPRIPARA12_7 (JECS_CSU_BASE+0x667*4) +#define JECS_CSU_ECPRIPARA13_0 (JECS_CSU_BASE+0x668*4) +#define JECS_CSU_ECPRIPARA13_1 (JECS_CSU_BASE+0x669*4) +#define JECS_CSU_ECPRIPARA13_2 (JECS_CSU_BASE+0x66A*4) +#define JECS_CSU_ECPRIPARA13_3 (JECS_CSU_BASE+0x66B*4) +#define JECS_CSU_ECPRIPARA13_4 (JECS_CSU_BASE+0x66C*4) +#define JECS_CSU_ECPRIPARA13_5 (JECS_CSU_BASE+0x66D*4) +#define JECS_CSU_ECPRIPARA13_6 (JECS_CSU_BASE+0x66E*4) +#define JECS_CSU_ECPRIPARA13_7 (JECS_CSU_BASE+0x66F*4) +#define JECS_CSU_ECPRIPARA14_0 (JECS_CSU_BASE+0x670*4) +#define JECS_CSU_ECPRIPARA14_1 (JECS_CSU_BASE+0x671*4) +#define JECS_CSU_ECPRIPARA14_2 (JECS_CSU_BASE+0x672*4) +#define JECS_CSU_ECPRIPARA14_3 (JECS_CSU_BASE+0x673*4) +#define JECS_CSU_ECPRIPARA14_4 (JECS_CSU_BASE+0x674*4) +#define JECS_CSU_ECPRIPARA14_5 (JECS_CSU_BASE+0x675*4) +#define JECS_CSU_ECPRIPARA14_6 (JECS_CSU_BASE+0x676*4) +#define JECS_CSU_ECPRIPARA14_7 (JECS_CSU_BASE+0x677*4) +#define JECS_CSU_ECPRIPARA15_0 (JECS_CSU_BASE+0x678*4) +#define JECS_CSU_ECPRIPARA15_1 (JECS_CSU_BASE+0x679*4) +#define JECS_CSU_ECPRIPARA15_2 (JECS_CSU_BASE+0x67A*4) +#define JECS_CSU_ECPRIPARA15_3 (JECS_CSU_BASE+0x67B*4) +#define JECS_CSU_ECPRIPARA15_4 (JECS_CSU_BASE+0x67C*4) +#define JECS_CSU_ECPRIPARA15_5 (JECS_CSU_BASE+0x67D*4) +#define JECS_CSU_ECPRIPARA15_6 (JECS_CSU_BASE+0x67E*4) +#define JECS_CSU_ECPRIPARA15_7 (JECS_CSU_BASE+0x67F*4) +#define JECS_CSU_ECPRIPARA16_0 (JECS_CSU_BASE+0x680*4) +#define JECS_CSU_ECPRIPARA16_1 (JECS_CSU_BASE+0x681*4) +#define JECS_CSU_ECPRIPARA16_2 (JECS_CSU_BASE+0x682*4) +#define JECS_CSU_ECPRIPARA16_3 (JECS_CSU_BASE+0x683*4) +#define JECS_CSU_ECPRIPARA16_4 (JECS_CSU_BASE+0x684*4) +#define JECS_CSU_ECPRIPARA16_5 (JECS_CSU_BASE+0x685*4) +#define JECS_CSU_ECPRIPARA16_6 (JECS_CSU_BASE+0x686*4) +#define JECS_CSU_ECPRIPARA16_7 (JECS_CSU_BASE+0x687*4) +#define JECS_CSU_ECPRIPARA17_0 (JECS_CSU_BASE+0x688*4) +#define JECS_CSU_ECPRIPARA17_1 (JECS_CSU_BASE+0x689*4) +#define JECS_CSU_ECPRIPARA17_2 (JECS_CSU_BASE+0x68A*4) +#define JECS_CSU_ECPRIPARA17_3 (JECS_CSU_BASE+0x68B*4) +#define JECS_CSU_ECPRIPARA17_4 (JECS_CSU_BASE+0x68C*4) +#define JECS_CSU_ECPRIPARA17_5 (JECS_CSU_BASE+0x68D*4) +#define JECS_CSU_ECPRIPARA17_6 (JECS_CSU_BASE+0x68E*4) +#define JECS_CSU_ECPRIPARA17_7 (JECS_CSU_BASE+0x68F*4) +#define JECS_CSU_ECPRIPARA18_0 (JECS_CSU_BASE+0x690*4) +#define JECS_CSU_ECPRIPARA18_1 (JECS_CSU_BASE+0x691*4) +#define JECS_CSU_ECPRIPARA18_2 (JECS_CSU_BASE+0x692*4) +#define JECS_CSU_ECPRIPARA18_3 (JECS_CSU_BASE+0x693*4) +#define JECS_CSU_ECPRIPARA18_4 (JECS_CSU_BASE+0x694*4) +#define JECS_CSU_ECPRIPARA18_5 (JECS_CSU_BASE+0x695*4) +#define JECS_CSU_ECPRIPARA18_6 (JECS_CSU_BASE+0x696*4) +#define JECS_CSU_ECPRIPARA18_7 (JECS_CSU_BASE+0x697*4) +#define JECS_CSU_ECPRIPARA19_0 (JECS_CSU_BASE+0x698*4) +#define JECS_CSU_ECPRIPARA19_1 (JECS_CSU_BASE+0x699*4) +#define JECS_CSU_ECPRIPARA19_2 (JECS_CSU_BASE+0x69A*4) +#define JECS_CSU_ECPRIPARA19_3 (JECS_CSU_BASE+0x69B*4) +#define JECS_CSU_ECPRIPARA19_4 (JECS_CSU_BASE+0x69C*4) +#define JECS_CSU_ECPRIPARA19_5 (JECS_CSU_BASE+0x69D*4) +#define JECS_CSU_ECPRIPARA19_6 (JECS_CSU_BASE+0x69E*4) +#define JECS_CSU_ECPRIPARA19_7 (JECS_CSU_BASE+0x69F*4) +#define JECS_CSU_ECPRIPARA20_0 (JECS_CSU_BASE+0x6A0*4) +#define JECS_CSU_ECPRIPARA20_1 (JECS_CSU_BASE+0x6A1*4) +#define JECS_CSU_ECPRIPARA20_2 (JECS_CSU_BASE+0x6A2*4) +#define JECS_CSU_ECPRIPARA20_3 (JECS_CSU_BASE+0x6A3*4) +#define JECS_CSU_ECPRIPARA20_4 (JECS_CSU_BASE+0x6A4*4) +#define JECS_CSU_ECPRIPARA20_5 (JECS_CSU_BASE+0x6A5*4) +#define JECS_CSU_ECPRIPARA20_6 (JECS_CSU_BASE+0x6A6*4) +#define JECS_CSU_ECPRIPARA20_7 (JECS_CSU_BASE+0x6A7*4) +#define JECS_CSU_ECPRIPARA21_0 (JECS_CSU_BASE+0x6A8*4) +#define JECS_CSU_ECPRIPARA21_1 (JECS_CSU_BASE+0x6A9*4) +#define JECS_CSU_ECPRIPARA21_2 (JECS_CSU_BASE+0x6AA*4) +#define JECS_CSU_ECPRIPARA21_3 (JECS_CSU_BASE+0x6AB*4) +#define JECS_CSU_ECPRIPARA21_4 (JECS_CSU_BASE+0x6AC*4) +#define JECS_CSU_ECPRIPARA21_5 (JECS_CSU_BASE+0x6AD*4) +#define JECS_CSU_ECPRIPARA21_6 (JECS_CSU_BASE+0x6AE*4) +#define JECS_CSU_ECPRIPARA21_7 (JECS_CSU_BASE+0x6AF*4) +#define JECS_CSU_ECPRIPARA22_0 (JECS_CSU_BASE+0x6B0*4) +#define JECS_CSU_ECPRIPARA22_1 (JECS_CSU_BASE+0x6B1*4) +#define JECS_CSU_ECPRIPARA22_2 (JECS_CSU_BASE+0x6B2*4) +#define JECS_CSU_ECPRIPARA22_3 (JECS_CSU_BASE+0x6B3*4) +#define JECS_CSU_ECPRIPARA22_4 (JECS_CSU_BASE+0x6B4*4) +#define JECS_CSU_ECPRIPARA22_5 (JECS_CSU_BASE+0x6B5*4) +#define JECS_CSU_ECPRIPARA22_6 (JECS_CSU_BASE+0x6B6*4) +#define JECS_CSU_ECPRIPARA22_7 (JECS_CSU_BASE+0x6B7*4) +#define JECS_CSU_ECPRIPARA23_0 (JECS_CSU_BASE+0x6B8*4) +#define JECS_CSU_ECPRIPARA23_1 (JECS_CSU_BASE+0x6B9*4) +#define JECS_CSU_ECPRIPARA23_2 (JECS_CSU_BASE+0x6BA*4) +#define JECS_CSU_ECPRIPARA23_3 (JECS_CSU_BASE+0x6BB*4) +#define JECS_CSU_ECPRIPARA23_4 (JECS_CSU_BASE+0x6BC*4) +#define JECS_CSU_ECPRIPARA23_5 (JECS_CSU_BASE+0x6BD*4) +#define JECS_CSU_ECPRIPARA23_6 (JECS_CSU_BASE+0x6BE*4) +#define JECS_CSU_ECPRIPARA23_7 (JECS_CSU_BASE+0x6BF*4) +#define JECS_CSU_ECPRIPARA24_0 (JECS_CSU_BASE+0x6C0*4) +#define JECS_CSU_ECPRIPARA24_1 (JECS_CSU_BASE+0x6C1*4) +#define JECS_CSU_ECPRIPARA24_2 (JECS_CSU_BASE+0x6C2*4) +#define JECS_CSU_ECPRIPARA24_3 (JECS_CSU_BASE+0x6C3*4) +#define JECS_CSU_ECPRIPARA24_4 (JECS_CSU_BASE+0x6C4*4) +#define JECS_CSU_ECPRIPARA24_5 (JECS_CSU_BASE+0x6C5*4) +#define JECS_CSU_ECPRIPARA24_6 (JECS_CSU_BASE+0x6C6*4) +#define JECS_CSU_ECPRIPARA24_7 (JECS_CSU_BASE+0x6C7*4) +#define JECS_CSU_ECPRIPARA25_0 (JECS_CSU_BASE+0x6C8*4) +#define JECS_CSU_ECPRIPARA25_1 (JECS_CSU_BASE+0x6C9*4) +#define JECS_CSU_ECPRIPARA25_2 (JECS_CSU_BASE+0x6CA*4) +#define JECS_CSU_ECPRIPARA25_3 (JECS_CSU_BASE+0x6CB*4) +#define JECS_CSU_ECPRIPARA25_4 (JECS_CSU_BASE+0x6CC*4) +#define JECS_CSU_ECPRIPARA25_5 (JECS_CSU_BASE+0x6CD*4) +#define JECS_CSU_ECPRIPARA25_6 (JECS_CSU_BASE+0x6CE*4) +#define JECS_CSU_ECPRIPARA25_7 (JECS_CSU_BASE+0x6CF*4) +#define JECS_CSU_ECPRIPARA26_0 (JECS_CSU_BASE+0x6D0*4) +#define JECS_CSU_ECPRIPARA26_1 (JECS_CSU_BASE+0x6D1*4) +#define JECS_CSU_ECPRIPARA26_2 (JECS_CSU_BASE+0x6D2*4) +#define JECS_CSU_ECPRIPARA26_3 (JECS_CSU_BASE+0x6D3*4) +#define JECS_CSU_ECPRIPARA26_4 (JECS_CSU_BASE+0x6D4*4) +#define JECS_CSU_ECPRIPARA26_5 (JECS_CSU_BASE+0x6D5*4) +#define JECS_CSU_ECPRIPARA26_6 (JECS_CSU_BASE+0x6D6*4) +#define JECS_CSU_ECPRIPARA26_7 (JECS_CSU_BASE+0x6D7*4) +#define JECS_CSU_ECPRIPARA27_0 (JECS_CSU_BASE+0x6D8*4) +#define JECS_CSU_ECPRIPARA27_1 (JECS_CSU_BASE+0x6D9*4) +#define JECS_CSU_ECPRIPARA27_2 (JECS_CSU_BASE+0x6DA*4) +#define JECS_CSU_ECPRIPARA27_3 (JECS_CSU_BASE+0x6DB*4) +#define JECS_CSU_ECPRIPARA27_4 (JECS_CSU_BASE+0x6DC*4) +#define JECS_CSU_ECPRIPARA27_5 (JECS_CSU_BASE+0x6DD*4) +#define JECS_CSU_ECPRIPARA27_6 (JECS_CSU_BASE+0x6DE*4) +#define JECS_CSU_ECPRIPARA27_7 (JECS_CSU_BASE+0x6DF*4) +#define JECS_CSU_ECPRIPARA28_0 (JECS_CSU_BASE+0x6E0*4) +#define JECS_CSU_ECPRIPARA28_1 (JECS_CSU_BASE+0x6E1*4) +#define JECS_CSU_ECPRIPARA28_2 (JECS_CSU_BASE+0x6E2*4) +#define JECS_CSU_ECPRIPARA28_3 (JECS_CSU_BASE+0x6E3*4) +#define JECS_CSU_ECPRIPARA28_4 (JECS_CSU_BASE+0x6E4*4) +#define JECS_CSU_ECPRIPARA28_5 (JECS_CSU_BASE+0x6E5*4) +#define JECS_CSU_ECPRIPARA28_6 (JECS_CSU_BASE+0x6E6*4) +#define JECS_CSU_ECPRIPARA28_7 (JECS_CSU_BASE+0x6E7*4) +#define JECS_CSU_ECPRIPARA29_0 (JECS_CSU_BASE+0x6E8*4) +#define JECS_CSU_ECPRIPARA29_1 (JECS_CSU_BASE+0x6E9*4) +#define JECS_CSU_ECPRIPARA29_2 (JECS_CSU_BASE+0x6EA*4) +#define JECS_CSU_ECPRIPARA29_3 (JECS_CSU_BASE+0x6EB*4) +#define JECS_CSU_ECPRIPARA29_4 (JECS_CSU_BASE+0x6EC*4) +#define JECS_CSU_ECPRIPARA29_5 (JECS_CSU_BASE+0x6ED*4) +#define JECS_CSU_ECPRIPARA29_6 (JECS_CSU_BASE+0x6EE*4) +#define JECS_CSU_ECPRIPARA29_7 (JECS_CSU_BASE+0x6EF*4) +#define JECS_CSU_ECPRIPARA30_0 (JECS_CSU_BASE+0x6F0*4) +#define JECS_CSU_ECPRIPARA30_1 (JECS_CSU_BASE+0x6F1*4) +#define JECS_CSU_ECPRIPARA30_2 (JECS_CSU_BASE+0x6F2*4) +#define JECS_CSU_ECPRIPARA30_3 (JECS_CSU_BASE+0x6F3*4) +#define JECS_CSU_ECPRIPARA30_4 (JECS_CSU_BASE+0x6F4*4) +#define JECS_CSU_ECPRIPARA30_5 (JECS_CSU_BASE+0x6F5*4) +#define JECS_CSU_ECPRIPARA30_6 (JECS_CSU_BASE+0x6F6*4) +#define JECS_CSU_ECPRIPARA30_7 (JECS_CSU_BASE+0x6F7*4) +#define JECS_CSU_ECPRIPARA31_0 (JECS_CSU_BASE+0x6F8*4) +#define JECS_CSU_ECPRIPARA31_1 (JECS_CSU_BASE+0x6F9*4) +#define JECS_CSU_ECPRIPARA31_2 (JECS_CSU_BASE+0x6FA*4) +#define JECS_CSU_ECPRIPARA31_3 (JECS_CSU_BASE+0x6FB*4) +#define JECS_CSU_ECPRIPARA31_4 (JECS_CSU_BASE+0x6FC*4) +#define JECS_CSU_ECPRIPARA31_5 (JECS_CSU_BASE+0x6FD*4) +#define JECS_CSU_ECPRIPARA31_6 (JECS_CSU_BASE+0x6FE*4) +#define JECS_CSU_ECPRIPARA31_7 (JECS_CSU_BASE+0x6FF*4) +#define JECS_CSU_ECPRIPARA32_0 (JECS_CSU_BASE+0x700*4) +#define JECS_CSU_ECPRIPARA32_1 (JECS_CSU_BASE+0x701*4) +#define JECS_CSU_ECPRIPARA32_2 (JECS_CSU_BASE+0x702*4) +#define JECS_CSU_ECPRIPARA32_3 (JECS_CSU_BASE+0x703*4) +#define JECS_CSU_ECPRIPARA32_4 (JECS_CSU_BASE+0x704*4) +#define JECS_CSU_ECPRIPARA32_5 (JECS_CSU_BASE+0x705*4) +#define JECS_CSU_ECPRIPARA32_6 (JECS_CSU_BASE+0x706*4) +#define JECS_CSU_ECPRIPARA32_7 (JECS_CSU_BASE+0x707*4) +#define JECS_CSU_ECPRIPARA33_0 (JECS_CSU_BASE+0x708*4) +#define JECS_CSU_ECPRIPARA33_1 (JECS_CSU_BASE+0x709*4) +#define JECS_CSU_ECPRIPARA33_2 (JECS_CSU_BASE+0x70A*4) +#define JECS_CSU_ECPRIPARA33_3 (JECS_CSU_BASE+0x70B*4) +#define JECS_CSU_ECPRIPARA33_4 (JECS_CSU_BASE+0x70C*4) +#define JECS_CSU_ECPRIPARA33_5 (JECS_CSU_BASE+0x70D*4) +#define JECS_CSU_ECPRIPARA33_6 (JECS_CSU_BASE+0x70E*4) +#define JECS_CSU_ECPRIPARA33_7 (JECS_CSU_BASE+0x70F*4) +#define JECS_CSU_ECPRIPARA34_0 (JECS_CSU_BASE+0x710*4) +#define JECS_CSU_ECPRIPARA34_1 (JECS_CSU_BASE+0x711*4) +#define JECS_CSU_ECPRIPARA34_2 (JECS_CSU_BASE+0x712*4) +#define JECS_CSU_ECPRIPARA34_3 (JECS_CSU_BASE+0x713*4) +#define JECS_CSU_ECPRIPARA34_4 (JECS_CSU_BASE+0x714*4) +#define JECS_CSU_ECPRIPARA34_5 (JECS_CSU_BASE+0x715*4) +#define JECS_CSU_ECPRIPARA34_6 (JECS_CSU_BASE+0x716*4) +#define JECS_CSU_ECPRIPARA34_7 (JECS_CSU_BASE+0x717*4) +#define JECS_CSU_ECPRIPARA35_0 (JECS_CSU_BASE+0x718*4) +#define JECS_CSU_ECPRIPARA35_1 (JECS_CSU_BASE+0x719*4) +#define JECS_CSU_ECPRIPARA35_2 (JECS_CSU_BASE+0x71A*4) +#define JECS_CSU_ECPRIPARA35_3 (JECS_CSU_BASE+0x71B*4) +#define JECS_CSU_ECPRIPARA35_4 (JECS_CSU_BASE+0x71C*4) +#define JECS_CSU_ECPRIPARA35_5 (JECS_CSU_BASE+0x71D*4) +#define JECS_CSU_ECPRIPARA35_6 (JECS_CSU_BASE+0x71E*4) +#define JECS_CSU_ECPRIPARA35_7 (JECS_CSU_BASE+0x71F*4) +#define JECS_CSU_ECPRIPARA36_0 (JECS_CSU_BASE+0x720*4) +#define JECS_CSU_ECPRIPARA36_1 (JECS_CSU_BASE+0x721*4) +#define JECS_CSU_ECPRIPARA36_2 (JECS_CSU_BASE+0x722*4) +#define JECS_CSU_ECPRIPARA36_3 (JECS_CSU_BASE+0x723*4) +#define JECS_CSU_ECPRIPARA36_4 (JECS_CSU_BASE+0x724*4) +#define JECS_CSU_ECPRIPARA36_5 (JECS_CSU_BASE+0x725*4) +#define JECS_CSU_ECPRIPARA36_6 (JECS_CSU_BASE+0x726*4) +#define JECS_CSU_ECPRIPARA36_7 (JECS_CSU_BASE+0x727*4) +#define JECS_CSU_ECPRIPARA37_0 (JECS_CSU_BASE+0x728*4) +#define JECS_CSU_ECPRIPARA37_1 (JECS_CSU_BASE+0x729*4) +#define JECS_CSU_ECPRIPARA37_2 (JECS_CSU_BASE+0x72A*4) +#define JECS_CSU_ECPRIPARA37_3 (JECS_CSU_BASE+0x72B*4) +#define JECS_CSU_ECPRIPARA37_4 (JECS_CSU_BASE+0x72C*4) +#define JECS_CSU_ECPRIPARA37_5 (JECS_CSU_BASE+0x72D*4) +#define JECS_CSU_ECPRIPARA37_6 (JECS_CSU_BASE+0x72E*4) +#define JECS_CSU_ECPRIPARA37_7 (JECS_CSU_BASE+0x72F*4) +#define JECS_CSU_ECPRIPARA38_0 (JECS_CSU_BASE+0x730*4) +#define JECS_CSU_ECPRIPARA38_1 (JECS_CSU_BASE+0x731*4) +#define JECS_CSU_ECPRIPARA38_2 (JECS_CSU_BASE+0x732*4) +#define JECS_CSU_ECPRIPARA38_3 (JECS_CSU_BASE+0x733*4) +#define JECS_CSU_ECPRIPARA38_4 (JECS_CSU_BASE+0x734*4) +#define JECS_CSU_ECPRIPARA38_5 (JECS_CSU_BASE+0x735*4) +#define JECS_CSU_ECPRIPARA38_6 (JECS_CSU_BASE+0x736*4) +#define JECS_CSU_ECPRIPARA38_7 (JECS_CSU_BASE+0x737*4) +#define JECS_CSU_ECPRIPARA39_0 (JECS_CSU_BASE+0x738*4) +#define JECS_CSU_ECPRIPARA39_1 (JECS_CSU_BASE+0x739*4) +#define JECS_CSU_ECPRIPARA39_2 (JECS_CSU_BASE+0x73A*4) +#define JECS_CSU_ECPRIPARA39_3 (JECS_CSU_BASE+0x73B*4) +#define JECS_CSU_ECPRIPARA39_4 (JECS_CSU_BASE+0x73C*4) +#define JECS_CSU_ECPRIPARA39_5 (JECS_CSU_BASE+0x73D*4) +#define JECS_CSU_ECPRIPARA39_6 (JECS_CSU_BASE+0x73E*4) +#define JECS_CSU_ECPRIPARA39_7 (JECS_CSU_BASE+0x73F*4) +#define JECS_CSU_ECPRIPARA40_0 (JECS_CSU_BASE+0x740*4) +#define JECS_CSU_ECPRIPARA40_1 (JECS_CSU_BASE+0x741*4) +#define JECS_CSU_ECPRIPARA40_2 (JECS_CSU_BASE+0x742*4) +#define JECS_CSU_ECPRIPARA40_3 (JECS_CSU_BASE+0x743*4) +#define JECS_CSU_ECPRIPARA40_4 (JECS_CSU_BASE+0x744*4) +#define JECS_CSU_ECPRIPARA40_5 (JECS_CSU_BASE+0x745*4) +#define JECS_CSU_ECPRIPARA40_6 (JECS_CSU_BASE+0x746*4) +#define JECS_CSU_ECPRIPARA40_7 (JECS_CSU_BASE+0x747*4) +#define JECS_CSU_ECPRIPARA41_0 (JECS_CSU_BASE+0x748*4) +#define JECS_CSU_ECPRIPARA41_1 (JECS_CSU_BASE+0x749*4) +#define JECS_CSU_ECPRIPARA41_2 (JECS_CSU_BASE+0x74A*4) +#define JECS_CSU_ECPRIPARA41_3 (JECS_CSU_BASE+0x74B*4) +#define JECS_CSU_ECPRIPARA41_4 (JECS_CSU_BASE+0x74C*4) +#define JECS_CSU_ECPRIPARA41_5 (JECS_CSU_BASE+0x74D*4) +#define JECS_CSU_ECPRIPARA41_6 (JECS_CSU_BASE+0x74E*4) +#define JECS_CSU_ECPRIPARA41_7 (JECS_CSU_BASE+0x74F*4) +#define JECS_CSU_ECPRIPARA42_0 (JECS_CSU_BASE+0x750*4) +#define JECS_CSU_ECPRIPARA42_1 (JECS_CSU_BASE+0x751*4) +#define JECS_CSU_ECPRIPARA42_2 (JECS_CSU_BASE+0x752*4) +#define JECS_CSU_ECPRIPARA42_3 (JECS_CSU_BASE+0x753*4) +#define JECS_CSU_ECPRIPARA42_4 (JECS_CSU_BASE+0x754*4) +#define JECS_CSU_ECPRIPARA42_5 (JECS_CSU_BASE+0x755*4) +#define JECS_CSU_ECPRIPARA42_6 (JECS_CSU_BASE+0x756*4) +#define JECS_CSU_ECPRIPARA42_7 (JECS_CSU_BASE+0x757*4) +#define JECS_CSU_ECPRIPARA43_0 (JECS_CSU_BASE+0x758*4) +#define JECS_CSU_ECPRIPARA43_1 (JECS_CSU_BASE+0x759*4) +#define JECS_CSU_ECPRIPARA43_2 (JECS_CSU_BASE+0x75A*4) +#define JECS_CSU_ECPRIPARA43_3 (JECS_CSU_BASE+0x75B*4) +#define JECS_CSU_ECPRIPARA43_4 (JECS_CSU_BASE+0x75C*4) +#define JECS_CSU_ECPRIPARA43_5 (JECS_CSU_BASE+0x75D*4) +#define JECS_CSU_ECPRIPARA43_6 (JECS_CSU_BASE+0x75E*4) +#define JECS_CSU_ECPRIPARA43_7 (JECS_CSU_BASE+0x75F*4) +#define JECS_CSU_ECPRIPARA44_0 (JECS_CSU_BASE+0x760*4) +#define JECS_CSU_ECPRIPARA44_1 (JECS_CSU_BASE+0x761*4) +#define JECS_CSU_ECPRIPARA44_2 (JECS_CSU_BASE+0x762*4) +#define JECS_CSU_ECPRIPARA44_3 (JECS_CSU_BASE+0x763*4) +#define JECS_CSU_ECPRIPARA44_4 (JECS_CSU_BASE+0x764*4) +#define JECS_CSU_ECPRIPARA44_5 (JECS_CSU_BASE+0x765*4) +#define JECS_CSU_ECPRIPARA44_6 (JECS_CSU_BASE+0x766*4) +#define JECS_CSU_ECPRIPARA44_7 (JECS_CSU_BASE+0x767*4) +#define JECS_CSU_ECPRIPARA45_0 (JECS_CSU_BASE+0x768*4) +#define JECS_CSU_ECPRIPARA45_1 (JECS_CSU_BASE+0x769*4) +#define JECS_CSU_ECPRIPARA45_2 (JECS_CSU_BASE+0x76A*4) +#define JECS_CSU_ECPRIPARA45_3 (JECS_CSU_BASE+0x76B*4) +#define JECS_CSU_ECPRIPARA45_4 (JECS_CSU_BASE+0x76C*4) +#define JECS_CSU_ECPRIPARA45_5 (JECS_CSU_BASE+0x76D*4) +#define JECS_CSU_ECPRIPARA45_6 (JECS_CSU_BASE+0x76E*4) +#define JECS_CSU_ECPRIPARA45_7 (JECS_CSU_BASE+0x76F*4) +#define JECS_CSU_ECPRIPARA46_0 (JECS_CSU_BASE+0x770*4) +#define JECS_CSU_ECPRIPARA46_1 (JECS_CSU_BASE+0x771*4) +#define JECS_CSU_ECPRIPARA46_2 (JECS_CSU_BASE+0x772*4) +#define JECS_CSU_ECPRIPARA46_3 (JECS_CSU_BASE+0x773*4) +#define JECS_CSU_ECPRIPARA46_4 (JECS_CSU_BASE+0x774*4) +#define JECS_CSU_ECPRIPARA46_5 (JECS_CSU_BASE+0x775*4) +#define JECS_CSU_ECPRIPARA46_6 (JECS_CSU_BASE+0x776*4) +#define JECS_CSU_ECPRIPARA46_7 (JECS_CSU_BASE+0x777*4) +#define JECS_CSU_ECPRIPARA47_0 (JECS_CSU_BASE+0x778*4) +#define JECS_CSU_ECPRIPARA47_1 (JECS_CSU_BASE+0x779*4) +#define JECS_CSU_ECPRIPARA47_2 (JECS_CSU_BASE+0x77A*4) +#define JECS_CSU_ECPRIPARA47_3 (JECS_CSU_BASE+0x77B*4) +#define JECS_CSU_ECPRIPARA47_4 (JECS_CSU_BASE+0x77C*4) +#define JECS_CSU_ECPRIPARA47_5 (JECS_CSU_BASE+0x77D*4) +#define JECS_CSU_ECPRIPARA47_6 (JECS_CSU_BASE+0x77E*4) +#define JECS_CSU_ECPRIPARA47_7 (JECS_CSU_BASE+0x77F*4) +#define JECS_CSU_ECPRIPARA48_0 (JECS_CSU_BASE+0x780*4) +#define JECS_CSU_ECPRIPARA48_1 (JECS_CSU_BASE+0x781*4) +#define JECS_CSU_ECPRIPARA48_2 (JECS_CSU_BASE+0x782*4) +#define JECS_CSU_ECPRIPARA48_3 (JECS_CSU_BASE+0x783*4) +#define JECS_CSU_ECPRIPARA48_4 (JECS_CSU_BASE+0x784*4) +#define JECS_CSU_ECPRIPARA48_5 (JECS_CSU_BASE+0x785*4) +#define JECS_CSU_ECPRIPARA48_6 (JECS_CSU_BASE+0x786*4) +#define JECS_CSU_ECPRIPARA48_7 (JECS_CSU_BASE+0x787*4) +#define JECS_CSU_ECPRIPARA49_0 (JECS_CSU_BASE+0x788*4) +#define JECS_CSU_ECPRIPARA49_1 (JECS_CSU_BASE+0x789*4) +#define JECS_CSU_ECPRIPARA49_2 (JECS_CSU_BASE+0x78A*4) +#define JECS_CSU_ECPRIPARA49_3 (JECS_CSU_BASE+0x78B*4) +#define JECS_CSU_ECPRIPARA49_4 (JECS_CSU_BASE+0x78C*4) +#define JECS_CSU_ECPRIPARA49_5 (JECS_CSU_BASE+0x78D*4) +#define JECS_CSU_ECPRIPARA49_6 (JECS_CSU_BASE+0x78E*4) +#define JECS_CSU_ECPRIPARA49_7 (JECS_CSU_BASE+0x78F*4) +#define JECS_CSU_ECPRIPARA50_0 (JECS_CSU_BASE+0x790*4) +#define JECS_CSU_ECPRIPARA50_1 (JECS_CSU_BASE+0x791*4) +#define JECS_CSU_ECPRIPARA50_2 (JECS_CSU_BASE+0x792*4) +#define JECS_CSU_ECPRIPARA50_3 (JECS_CSU_BASE+0x793*4) +#define JECS_CSU_ECPRIPARA50_4 (JECS_CSU_BASE+0x794*4) +#define JECS_CSU_ECPRIPARA50_5 (JECS_CSU_BASE+0x795*4) +#define JECS_CSU_ECPRIPARA50_6 (JECS_CSU_BASE+0x796*4) +#define JECS_CSU_ECPRIPARA50_7 (JECS_CSU_BASE+0x797*4) +#define JECS_CSU_ECPRIPARA51_0 (JECS_CSU_BASE+0x798*4) +#define JECS_CSU_ECPRIPARA51_1 (JECS_CSU_BASE+0x799*4) +#define JECS_CSU_ECPRIPARA51_2 (JECS_CSU_BASE+0x79A*4) +#define JECS_CSU_ECPRIPARA51_3 (JECS_CSU_BASE+0x79B*4) +#define JECS_CSU_ECPRIPARA51_4 (JECS_CSU_BASE+0x79C*4) +#define JECS_CSU_ECPRIPARA51_5 (JECS_CSU_BASE+0x79D*4) +#define JECS_CSU_ECPRIPARA51_6 (JECS_CSU_BASE+0x79E*4) +#define JECS_CSU_ECPRIPARA51_7 (JECS_CSU_BASE+0x79F*4) +#define JECS_CSU_ECPRIPARA52_0 (JECS_CSU_BASE+0x7A0*4) +#define JECS_CSU_ECPRIPARA52_1 (JECS_CSU_BASE+0x7A1*4) +#define JECS_CSU_ECPRIPARA52_2 (JECS_CSU_BASE+0x7A2*4) +#define JECS_CSU_ECPRIPARA52_3 (JECS_CSU_BASE+0x7A3*4) +#define JECS_CSU_ECPRIPARA52_4 (JECS_CSU_BASE+0x7A4*4) +#define JECS_CSU_ECPRIPARA52_5 (JECS_CSU_BASE+0x7A5*4) +#define JECS_CSU_ECPRIPARA52_6 (JECS_CSU_BASE+0x7A6*4) +#define JECS_CSU_ECPRIPARA52_7 (JECS_CSU_BASE+0x7A7*4) +#define JECS_CSU_ECPRIPARA53_0 (JECS_CSU_BASE+0x7A8*4) +#define JECS_CSU_ECPRIPARA53_1 (JECS_CSU_BASE+0x7A9*4) +#define JECS_CSU_ECPRIPARA53_2 (JECS_CSU_BASE+0x7AA*4) +#define JECS_CSU_ECPRIPARA53_3 (JECS_CSU_BASE+0x7AB*4) +#define JECS_CSU_ECPRIPARA53_4 (JECS_CSU_BASE+0x7AC*4) +#define JECS_CSU_ECPRIPARA53_5 (JECS_CSU_BASE+0x7AD*4) +#define JECS_CSU_ECPRIPARA53_6 (JECS_CSU_BASE+0x7AE*4) +#define JECS_CSU_ECPRIPARA53_7 (JECS_CSU_BASE+0x7AF*4) +#define JECS_CSU_ECPRIPARA54_0 (JECS_CSU_BASE+0x7B0*4) +#define JECS_CSU_ECPRIPARA54_1 (JECS_CSU_BASE+0x7B1*4) +#define JECS_CSU_ECPRIPARA54_2 (JECS_CSU_BASE+0x7B2*4) +#define JECS_CSU_ECPRIPARA54_3 (JECS_CSU_BASE+0x7B3*4) +#define JECS_CSU_ECPRIPARA54_4 (JECS_CSU_BASE+0x7B4*4) +#define JECS_CSU_ECPRIPARA54_5 (JECS_CSU_BASE+0x7B5*4) +#define JECS_CSU_ECPRIPARA54_6 (JECS_CSU_BASE+0x7B6*4) +#define JECS_CSU_ECPRIPARA54_7 (JECS_CSU_BASE+0x7B7*4) +#define JECS_CSU_ECPRIPARA55_0 (JECS_CSU_BASE+0x7B8*4) +#define JECS_CSU_ECPRIPARA55_1 (JECS_CSU_BASE+0x7B9*4) +#define JECS_CSU_ECPRIPARA55_2 (JECS_CSU_BASE+0x7BA*4) +#define JECS_CSU_ECPRIPARA55_3 (JECS_CSU_BASE+0x7BB*4) +#define JECS_CSU_ECPRIPARA55_4 (JECS_CSU_BASE+0x7BC*4) +#define JECS_CSU_ECPRIPARA55_5 (JECS_CSU_BASE+0x7BD*4) +#define JECS_CSU_ECPRIPARA55_6 (JECS_CSU_BASE+0x7BE*4) +#define JECS_CSU_ECPRIPARA55_7 (JECS_CSU_BASE+0x7BF*4) +#define JECS_CSU_ECPRIPARA56_0 (JECS_CSU_BASE+0x7C0*4) +#define JECS_CSU_ECPRIPARA56_1 (JECS_CSU_BASE+0x7C1*4) +#define JECS_CSU_ECPRIPARA56_2 (JECS_CSU_BASE+0x7C2*4) +#define JECS_CSU_ECPRIPARA56_3 (JECS_CSU_BASE+0x7C3*4) +#define JECS_CSU_ECPRIPARA56_4 (JECS_CSU_BASE+0x7C4*4) +#define JECS_CSU_ECPRIPARA56_5 (JECS_CSU_BASE+0x7C5*4) +#define JECS_CSU_ECPRIPARA56_6 (JECS_CSU_BASE+0x7C6*4) +#define JECS_CSU_ECPRIPARA56_7 (JECS_CSU_BASE+0x7C7*4) +#define JECS_CSU_ECPRIPARA57_0 (JECS_CSU_BASE+0x7C8*4) +#define JECS_CSU_ECPRIPARA57_1 (JECS_CSU_BASE+0x7C9*4) +#define JECS_CSU_ECPRIPARA57_2 (JECS_CSU_BASE+0x7CA*4) +#define JECS_CSU_ECPRIPARA57_3 (JECS_CSU_BASE+0x7CB*4) +#define JECS_CSU_ECPRIPARA57_4 (JECS_CSU_BASE+0x7CC*4) +#define JECS_CSU_ECPRIPARA57_5 (JECS_CSU_BASE+0x7CD*4) +#define JECS_CSU_ECPRIPARA57_6 (JECS_CSU_BASE+0x7CE*4) +#define JECS_CSU_ECPRIPARA57_7 (JECS_CSU_BASE+0x7CF*4) +#define JECS_CSU_ECPRIPARA58_0 (JECS_CSU_BASE+0x7D0*4) +#define JECS_CSU_ECPRIPARA58_1 (JECS_CSU_BASE+0x7D1*4) +#define JECS_CSU_ECPRIPARA58_2 (JECS_CSU_BASE+0x7D2*4) +#define JECS_CSU_ECPRIPARA58_3 (JECS_CSU_BASE+0x7D3*4) +#define JECS_CSU_ECPRIPARA58_4 (JECS_CSU_BASE+0x7D4*4) +#define JECS_CSU_ECPRIPARA58_5 (JECS_CSU_BASE+0x7D5*4) +#define JECS_CSU_ECPRIPARA58_6 (JECS_CSU_BASE+0x7D6*4) +#define JECS_CSU_ECPRIPARA58_7 (JECS_CSU_BASE+0x7D7*4) +#define JECS_CSU_ECPRIPARA59_0 (JECS_CSU_BASE+0x7D8*4) +#define JECS_CSU_ECPRIPARA59_1 (JECS_CSU_BASE+0x7D9*4) +#define JECS_CSU_ECPRIPARA59_2 (JECS_CSU_BASE+0x7DA*4) +#define JECS_CSU_ECPRIPARA59_3 (JECS_CSU_BASE+0x7DB*4) +#define JECS_CSU_ECPRIPARA59_4 (JECS_CSU_BASE+0x7DC*4) +#define JECS_CSU_ECPRIPARA59_5 (JECS_CSU_BASE+0x7DD*4) +#define JECS_CSU_ECPRIPARA59_6 (JECS_CSU_BASE+0x7DE*4) +#define JECS_CSU_ECPRIPARA59_7 (JECS_CSU_BASE+0x7DF*4) +#define JECS_CSU_ECPRIPARA60_0 (JECS_CSU_BASE+0x7E0*4) +#define JECS_CSU_ECPRIPARA60_1 (JECS_CSU_BASE+0x7E1*4) +#define JECS_CSU_ECPRIPARA60_2 (JECS_CSU_BASE+0x7E2*4) +#define JECS_CSU_ECPRIPARA60_3 (JECS_CSU_BASE+0x7E3*4) +#define JECS_CSU_ECPRIPARA60_4 (JECS_CSU_BASE+0x7E4*4) +#define JECS_CSU_ECPRIPARA60_5 (JECS_CSU_BASE+0x7E5*4) +#define JECS_CSU_ECPRIPARA60_6 (JECS_CSU_BASE+0x7E6*4) +#define JECS_CSU_ECPRIPARA60_7 (JECS_CSU_BASE+0x7E7*4) +#define JECS_CSU_ECPRIPARA61_0 (JECS_CSU_BASE+0x7E8*4) +#define JECS_CSU_ECPRIPARA61_1 (JECS_CSU_BASE+0x7E9*4) +#define JECS_CSU_ECPRIPARA61_2 (JECS_CSU_BASE+0x7EA*4) +#define JECS_CSU_ECPRIPARA61_3 (JECS_CSU_BASE+0x7EB*4) +#define JECS_CSU_ECPRIPARA61_4 (JECS_CSU_BASE+0x7EC*4) +#define JECS_CSU_ECPRIPARA61_5 (JECS_CSU_BASE+0x7ED*4) +#define JECS_CSU_ECPRIPARA61_6 (JECS_CSU_BASE+0x7EE*4) +#define JECS_CSU_ECPRIPARA61_7 (JECS_CSU_BASE+0x7EF*4) +#define JECS_CSU_ECPRIPARA62_0 (JECS_CSU_BASE+0x7F0*4) +#define JECS_CSU_ECPRIPARA62_1 (JECS_CSU_BASE+0x7F1*4) +#define JECS_CSU_ECPRIPARA62_2 (JECS_CSU_BASE+0x7F2*4) +#define JECS_CSU_ECPRIPARA62_3 (JECS_CSU_BASE+0x7F3*4) +#define JECS_CSU_ECPRIPARA62_4 (JECS_CSU_BASE+0x7F4*4) +#define JECS_CSU_ECPRIPARA62_5 (JECS_CSU_BASE+0x7F5*4) +#define JECS_CSU_ECPRIPARA62_6 (JECS_CSU_BASE+0x7F6*4) +#define JECS_CSU_ECPRIPARA62_7 (JECS_CSU_BASE+0x7F7*4) +#define JECS_CSU_ECPRIPARA63_0 (JECS_CSU_BASE+0x7F8*4) +#define JECS_CSU_ECPRIPARA63_1 (JECS_CSU_BASE+0x7F9*4) +#define JECS_CSU_ECPRIPARA63_2 (JECS_CSU_BASE+0x7FA*4) +#define JECS_CSU_ECPRIPARA63_3 (JECS_CSU_BASE+0x7FB*4) +#define JECS_CSU_ECPRIPARA63_4 (JECS_CSU_BASE+0x7FC*4) +#define JECS_CSU_ECPRIPARA63_5 (JECS_CSU_BASE+0x7FD*4) +#define JECS_CSU_ECPRIPARA63_6 (JECS_CSU_BASE+0x7FE*4) +#define JECS_CSU_ECPRIPARA63_7 (JECS_CSU_BASE+0x7FF*4) + + +#endif diff --git a/driver/rfic/ucp/base/inc/dw_apb_gpio.h b/driver/rfic/ucp/base/inc/dw_apb_gpio.h new file mode 100644 index 0000000..c5ea668 --- /dev/null +++ b/driver/rfic/ucp/base/inc/dw_apb_gpio.h @@ -0,0 +1,154 @@ +//******************** (C) COPYRIGHT 2019 SmartLogic******************************* +// FileName : dw_apb_gpio.h +// Author : lijian, jian.li@smartlogictech.com +// Date First Issued : 2019-03-29 03:39:50 PM +// Last Modified : 2020-05-13 10:20:01 AM +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** +#ifndef __GPIO_H__ +#define __GPIO_H__ + + +#define DW_APB_GPIO0_BASE 0x04450000 +#define DW_APB_GPIO1_BASE 0x04d10000 +#define GPIO_SWPORTA_DR_OFFSET 0x00 +#define GPIO_SWPORTA_DDR_OFFSET 0x04 +#define GPIO_SWPORTA_CTL_OFFSET 0x08 +#define GPIO_SWPORTB_DR_OFFSET 0x0C +#define GPIO_SWPORTB_DDR_OFFSET 0x10 +#define GPIO_SWPORTB_CTL_OFFSET 0x14 +#define GPIO_SWPORTC_DR_OFFSET 0x18 +#define GPIO_SWPORTC_DDR_OFFSET 0x1C +#define GPIO_SWPORTC_CTL_OFFSET 0x20 +#define GPIO_SWPORTD_DR_OFFSET 0x24 +#define GPIO_SWPORTD_DDR_OFFSET 0x28 +#define GPIO_SWPORTD_CTL_OFFSET 0x2C +#define GPIO_INTEN_OFFSET 0x30 +#define GPIO_INTMASK_OFFSET 0x34 +#define GPIO_INTTYPE_LEVEL_OFFSET 0x38 +#define GPIO_INT_POLARITY_OFFSET 0x3C +#define GPIO_INTSTATUS_OFFSET 0x40 +#define GPIO_RAW_INTSTATUS_OFFSET 0x44 +#define GPIO_DEBOUNCE_OFFSET 0x48 +#define GPIO_PORTA_EOI_OFFSET 0x4C +#define GPIO_EXT_PORTA_OFFSET 0x50 +#define GPIO_EXT_PORTB_OFFSET 0x54 +#define GPIO_EXT_PORTC_OFFSET 0x58 +#define GPIO_EXT_PORTD_OFFSET 0x5C +#define GPIO_LS_SYNC_OFFSET 0x60 +#define GPIO_ID_CODE_OFFSET 0x64 +#define GPIO_VER_ID_CODE_OFFSET 0x6C +#define GPIO_CONFIGID_REG2_OFFSET 0x70 +#define GPIO_CONFIGID_REG1_OFFSET 0x74 + +#define GPIO0_SWPORTA_DR (DW_APB_GPIO0_BASE + GPIO_SWPORTA_DR_OFFSET) +#define GPIO0_SWPORTA_DDR (DW_APB_GPIO0_BASE + GPIO_SWPORTA_DDR_OFFSET) +#define GPIO0_SWPORTA_CTL (DW_APB_GPIO0_BASE + GPIO_SWPORTA_CTL_OFFSET) +#define GPIO0_SWPORTB_DR (DW_APB_GPIO0_BASE + GPIO_SWPORTB_DR_OFFSET) +#define GPIO0_SWPORTB_DDR (DW_APB_GPIO0_BASE + GPIO_SWPORTB_DDR_OFFSET) +#define GPIO0_SWPORTB_CTL (DW_APB_GPIO0_BASE + GPIO_SWPORTB_CTL_OFFSET) +#define GPIO0_SWPORTC_DR (DW_APB_GPIO0_BASE + GPIO_SWPORTC_DR_OFFSET) +#define GPIO0_SWPORTC_DDR (DW_APB_GPIO0_BASE + GPIO_SWPORTC_DDR_OFFSET) +#define GPIO0_SWPORTC_CTL (DW_APB_GPIO0_BASE + GPIO_SWPORTC_CTL_OFFSET) +#define GPIO0_SWPORTD_DR (DW_APB_GPIO0_BASE + GPIO_SWPORTD_DR_OFFSET) +#define GPIO0_SWPORTD_DDR (DW_APB_GPIO0_BASE + GPIO_SWPORTD_DDR_OFFSET) +#define GPIO0_SWPORTD_CTL (DW_APB_GPIO0_BASE + GPIO_SWPORTD_CTL_OFFSET) +#define GPIO0_INTEN (DW_APB_GPIO0_BASE + GPIO_INTEN_OFFSET) +#define GPIO0_INTMASK (DW_APB_GPIO0_BASE + GPIO_INTMASK_OFFSET) +#define GPIO0_INTTYPE_LEVEL (DW_APB_GPIO0_BASE + GPIO_INTTYPE_LEVEL_OFFSET) +#define GPIO0_INT_POLARITY (DW_APB_GPIO0_BASE + GPIO_INT_POLARITY_OFFSET) +#define GPIO0_INTSTATUS (DW_APB_GPIO0_BASE + GPIO_INTSTATUS_OFFSET) +#define GPIO0_RAW_INTSTATUS (DW_APB_GPIO0_BASE + GPIO_RAW_INTSTATUS_OFFSET) +#define GPIO0_DEBOUNCE (DW_APB_GPIO0_BASE + GPIO_DEBOUNCE_OFFSET) +#define GPIO0_PORTA_EOI (DW_APB_GPIO0_BASE + GPIO_PORTA_EOI_OFFSET) +#define GPIO0_EXT_PORTA (DW_APB_GPIO0_BASE + GPIO_EXT_PORTA_OFFSET) +#define GPIO0_EXT_PORTB (DW_APB_GPIO0_BASE + GPIO_EXT_PORTB_OFFSET) +#define GPIO0_EXT_PORTC (DW_APB_GPIO0_BASE + GPIO_EXT_PORTC_OFFSET) +#define GPIO0_EXT_PORTD (DW_APB_GPIO0_BASE + GPIO_EXT_PORTD_OFFSET) +#define GPIO0_LS_SYNC (DW_APB_GPIO0_BASE + GPIO_LS_SYNC_OFFSET) +#define GPIO0_ID_CODE (DW_APB_GPIO0_BASE + GPIO_ID_CODE_OFFSET) +#define GPIO0_VER_ID_CODE (DW_APB_GPIO0_BASE + GPIO_VER_ID_CODE_OFFSET) +#define GPIO0_CONFIGID_REG2 (DW_APB_GPIO0_BASE + GPIO_CONFIGID_REG2_OFFSET) +#define GPIO0_CONFIGID_REG1 (DW_APB_GPIO0_BASE + GPIO_CONFIGID_REG1_OFFSET) +#define GPIO0PING_1BIT_WR (GPIO0_SWPORTA_DR) +#define GPIO1_SWPORTA_DR (DW_APB_GPIO1_BASE + GPIO_SWPORTA_DR_OFFSET) +#define GPIO1_SWPORTA_DDR (DW_APB_GPIO1_BASE + GPIO_SWPORTA_DDR_OFFSET) +#define GPIO1_SWPORTA_CTL (DW_APB_GPIO1_BASE + GPIO_SWPORTA_CTL_OFFSET) +#define GPIO1_SWPORTB_DR (DW_APB_GPIO1_BASE + GPIO_SWPORTB_DR_OFFSET) +#define GPIO1_SWPORTB_DDR (DW_APB_GPIO1_BASE + GPIO_SWPORTB_DDR_OFFSET) +#define GPIO1_SWPORTB_CTL (DW_APB_GPIO1_BASE + GPIO_SWPORTB_CTL_OFFSET) +#define GPIO1_SWPORTC_DR (DW_APB_GPIO1_BASE + GPIO_SWPORTC_DR_OFFSET) +#define GPIO1_SWPORTC_DDR (DW_APB_GPIO1_BASE + GPIO_SWPORTC_DDR_OFFSET) +#define GPIO1_SWPORTC_CTL (DW_APB_GPIO1_BASE + GPIO_SWPORTC_CTL_OFFSET) +#define GPIO1_SWPORTD_DR (DW_APB_GPIO1_BASE + GPIO_SWPORTD_DR_OFFSET) +#define GPIO1_SWPORTD_DDR (DW_APB_GPIO1_BASE + GPIO_SWPORTD_DDR_OFFSET) +#define GPIO1_SWPORTD_CTL (DW_APB_GPIO1_BASE + GPIO_SWPORTD_CTL_OFFSET) +#define GPIO1_INTEN (DW_APB_GPIO1_BASE + GPIO_INTEN_OFFSET) +#define GPIO1_INTMASK (DW_APB_GPIO1_BASE + GPIO_INTMASK_OFFSET) +#define GPIO1_INTTYPE_LEVEL (DW_APB_GPIO1_BASE + GPIO_INTTYPE_LEVEL_OFFSET) +#define GPIO1_INT_POLARITY (DW_APB_GPIO1_BASE + GPIO_INT_POLARITY_OFFSET) +#define GPIO1_INTSTATUS (DW_APB_GPIO1_BASE + GPIO_INTSTATUS_OFFSET) +#define GPIO1_RAW_INTSTATUS (DW_APB_GPIO1_BASE + GPIO_RAW_INTSTATUS_OFFSET) +#define GPIO1_DEBOUNCE (DW_APB_GPIO1_BASE + GPIO_DEBOUNCE_OFFSET) +#define GPIO1_PORTA_EOI (DW_APB_GPIO1_BASE + GPIO_PORTA_EOI_OFFSET) +#define GPIO1_EXT_PORTA (DW_APB_GPIO1_BASE + GPIO_EXT_PORTA_OFFSET) +#define GPIO1_EXT_PORTB (DW_APB_GPIO1_BASE + GPIO_EXT_PORTB_OFFSET) +#define GPIO1_EXT_PORTC (DW_APB_GPIO1_BASE + GPIO_EXT_PORTC_OFFSET) +#define GPIO1_EXT_PORTD (DW_APB_GPIO1_BASE + GPIO_EXT_PORTD_OFFSET) +#define GPIO1_LS_SYNC (DW_APB_GPIO1_BASE + GPIO_LS_SYNC_OFFSET) +#define GPIO1_ID_CODE (DW_APB_GPIO1_BASE + GPIO_ID_CODE_OFFSET) +#define GPIO1_VER_ID_CODE (DW_APB_GPIO1_BASE + GPIO_VER_ID_CODE_OFFSET) +#define GPIO1_CONFIGID_REG2 (DW_APB_GPIO1_BASE + GPIO_CONFIGID_REG2_OFFSET) +#define GPIO1_CONFIGID_REG1 (DW_APB_GPIO1_BASE + GPIO_CONFIGID_REG1_OFFSET) +#define GPIO1PING_1BIT_WR (GPIO1_SWPORTA_DR) + + +#define CC_GPIO_ADD_ENCODED_PARAM 0x1 +#define CC_GPIO_APB_DATA_WIDTH 32 +#define CC_GPIO_NUM_PORTS 4 +#define CC_GPIO_ID 0 +#define CC_GPIO_DEBOUNCE 0 +#define CC_GPIO_ID_WIDTH 32 +#define CC_GPIO_ID_NUM 0x0 +#define CC_GPIO_REV_ID 0 +#define CC_GPIO_REV_ID_WIDTH 32 +#define CC_GPIO_REV_ID_NUM 0x0 +#define CC_GPIO_PWIDTH_A 8 +#define CC_GPIO_PORTA_SINGLE_CTL 1 +#define CC_GPIO_SWPORTA_RESET 0x0 +#define CC_GPIO_HW_PORTA 1 +#define CC_GPIO_DFLT_DIR_A 0 +#define CC_GPIO_DFLT_SRC_A 0 +#define CC_GPIO_PORTA_INTR 1 +#define CC_GPIO_INT_POL 0 +#define CC_GPIO_INTR_IO 0 +#define CC_GPIO_PA_SYNC_EXT_DATA 1 +#define CC_GPIO_PA_SYNC_INTERRUPTS 1 +#define CC_GPIO_PWIDTH_B 32 +#define CC_GPIO_PORTB_SINGLE_CTL 1 +#define CC_GPIO_SWPORTB_RESET 0x0 +#define CC_GPIO_HW_PORTB 0 +#define CC_GPIO_DFLT_DIR_B 0 +#define CC_GPIO_DFLT_SRC_B 0 +#define CC_GPIO_PB_SYNC_EXT_DATA 1 +#define CC_GPIO_PWIDTH_C 32 +#define CC_GPIO_PORTC_SINGLE_CTL 1 +#define CC_GPIO_SWPORTC_RESET 0x0 +#define CC_GPIO_HW_PORTC 0 +#define CC_GPIO_DFLT_DIR_C 1 +#define CC_GPIO_DFLT_SRC_C 0 +#define CC_GPIO_PC_SYNC_EXT_DATA 0 +#define CC_GPIO_PWIDTH_D 8 +#define CC_GPIO_PORTD_SINGLE_CTL 1 +#define CC_GPIO_SWPORTD_RESET 0x0 +#define CC_GPIO_HW_PORTD 1 +#define CC_GPIO_DFLT_DIR_D 1 +#define CC_GPIO_DFLT_SRC_D 1 +#define CC_GPIO_PD_SYNC_EXT_DATA 1 + + +#endif diff --git a/driver/rfic/ucp/base/inc/dw_tmac.h b/driver/rfic/ucp/base/inc/dw_tmac.h new file mode 100644 index 0000000..f35fb71 --- /dev/null +++ b/driver/rfic/ucp/base/inc/dw_tmac.h @@ -0,0 +1,645 @@ + +#ifndef __TMAC_H__ +#define __TMAC_H__ + +#define TMAC_DWCXL_CORE_BaseAddress 0x09090000 +#define TMAC_DWCXL_MTL_BaseAddress 0x09091000 +#define TMAC_DWCXL_MTL_TCQ0_BaseAddress 0x09091100 +#define TMAC_DWCXL_MTL_TCQ1_BaseAddress 0x09091180 +#define TMAC_DWCXL_MTL_TCQ2_BaseAddress 0x09091200 +#define TMAC_DWCXL_MTL_TCQ3_BaseAddress 0x09091280 +#define TMAC_DWCXL_MTL_TCQ4_BaseAddress 0x09091300 +#define TMAC_DWCXL_MTL_TCQ5_BaseAddress 0x09091380 + +#define TMAC_DWCXL_DMA_BaseAddress 0x09093000 +#define TMAC_DWCXL_DMA_CH0_BaseAddress 0x09093100 +#define TMAC_DWCXL_DMA_CH1_BaseAddress 0x09093180 +#define TMAC_DWCXL_DMA_CH2_BaseAddress 0x09093200 +#define TMAC_DWCXL_DMA_CH3_BaseAddress 0x09093280 +#define TMAC_DWCXL_DMA_CH4_BaseAddress 0x09093300 +#define TMAC_DWCXL_DMA_CH5_BaseAddress 0x09093380 +#define TMAC_DWCXL_DMA_DUMMY_BaseAddress 0x09093ff8 + +#define TMAC_CTRL_BASE 0x09098000 + +#define TMAC_RST_CTRL_REG (TMAC_CTRL_BASE + 0x0 ) +#define TMAC_RST_TIMING_REG (TMAC_CTRL_BASE + 0x4 ) +#define TMAC_STATUS_REG (TMAC_CTRL_BASE + 0x8 ) +#define TMAC_SDB_CTRL_REG (TMAC_CTRL_BASE + 0xc ) +#define TMAC_SPEED_REG (TMAC_CTRL_BASE + 0x10) +#define TMAC_PCS_LANE_ENABLE_REG (TMAC_CTRL_BASE + 0x14) +#define TMAC_SNAP_CTRL_REG (TMAC_CTRL_BASE + 0x18) +#define TMAC_SNAP_TRI_REG (TMAC_CTRL_BASE + 0x1c) +#define TMAC_TS_REG0 (TMAC_CTRL_BASE + 0x20) +#define TMAC_TS_REG1 (TMAC_CTRL_BASE + 0x24) +#define TMAC_INT_FLAG_REG (TMAC_CTRL_BASE + 0x28) +#define TMAC_INT_EN_REG (TMAC_CTRL_BASE + 0x2c) + +#define TMAC_MAC_Tx_Configuration (TMAC_DWCXL_CORE_BaseAddress + 0x0 ) +#define TMAC_MAC_Rx_Configuration (TMAC_DWCXL_CORE_BaseAddress + 0x4 ) +#define TMAC_MAC_Packet_Filter (TMAC_DWCXL_CORE_BaseAddress + 0x8 ) +#define TMAC_MAC_Watchdog_Timeout (TMAC_DWCXL_CORE_BaseAddress + 0xc ) +#define TMAC_MAC_Hash_Table_Reg0 (TMAC_DWCXL_CORE_BaseAddress + 0x10 ) +#define TMAC_MAC_Hash_Table_Reg1 (TMAC_DWCXL_CORE_BaseAddress + 0x14 ) +#define TMAC_MAC_Hash_Table_Reg2 (TMAC_DWCXL_CORE_BaseAddress + 0x18 ) +#define TMAC_MAC_Hash_Table_Reg3 (TMAC_DWCXL_CORE_BaseAddress + 0x1c ) +#define TMAC_MAC_Hash_Table_Reg4 (TMAC_DWCXL_CORE_BaseAddress + 0x20 ) +#define TMAC_MAC_Hash_Table_Reg5 (TMAC_DWCXL_CORE_BaseAddress + 0x24 ) +#define TMAC_MAC_Hash_Table_Reg6 (TMAC_DWCXL_CORE_BaseAddress + 0x28 ) +#define TMAC_MAC_Hash_Table_Reg7 (TMAC_DWCXL_CORE_BaseAddress + 0x2c ) +#define TMAC_MAC_VLAN_Tag_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x50 ) +#define TMAC_MAC_VLAN_Tag_Data (TMAC_DWCXL_CORE_BaseAddress + 0x54 ) +#define TMAC_MAC_VLAN_Tag_Filter0 (TMAC_DWCXL_CORE_BaseAddress + 0x54 ) +#define TMAC_MAC_VLAN_Tag_Filter1 (TMAC_DWCXL_CORE_BaseAddress + 0x54 ) +#define TMAC_MAC_VLAN_Tag_Filter2 (TMAC_DWCXL_CORE_BaseAddress + 0x54 ) +#define TMAC_MAC_VLAN_Tag_Filter3 (TMAC_DWCXL_CORE_BaseAddress + 0x54 ) +#define TMAC_MAC_VLAN_Hash_Table (TMAC_DWCXL_CORE_BaseAddress + 0x58 ) +#define TMAC_MAC_VLAN_Incl (TMAC_DWCXL_CORE_BaseAddress + 0x60 ) +#define TMAC_MAC_Inner_VLAN_Incl (TMAC_DWCXL_CORE_BaseAddress + 0x64 ) +#define TMAC_MAC_Rx_Eth_Type_Match (TMAC_DWCXL_CORE_BaseAddress + 0x6c ) +#define TMAC_MAC_PRI0_Tx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x70 ) +#define TMAC_MAC_PRI1_Tx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x74 ) +#define TMAC_MAC_PRI2_Tx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x78 ) +#define TMAC_MAC_PRI3_Tx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x7c ) +#define TMAC_MAC_PRI4_Tx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x80 ) +#define TMAC_MAC_PRI5_Tx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x84 ) +#define TMAC_MAC_PRI6_Tx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x88 ) +#define TMAC_MAC_PRI7_Tx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x8c ) +#define TMAC_MAC_Rx_Flow_Ctrl (TMAC_DWCXL_CORE_BaseAddress + 0x90 ) +#define TMAC_MAC_Interrupt_Status (TMAC_DWCXL_CORE_BaseAddress + 0xb0 ) +#define TMAC_MAC_Interrupt_Enable (TMAC_DWCXL_CORE_BaseAddress + 0xb4 ) +#define TMAC_MAC_Rx_Tx_Status (TMAC_DWCXL_CORE_BaseAddress + 0xb8 ) +#define TMAC_MAC_PMT_Control_Status (TMAC_DWCXL_CORE_BaseAddress + 0xc0 ) +#define TMAC_MAC_RWK_Packet_Filter (TMAC_DWCXL_CORE_BaseAddress + 0xc4 ) +#define TMAC_RWK_Filter0123_Command (TMAC_DWCXL_CORE_BaseAddress + 0xc4 ) +#define TMAC_RWK_Filter0123_Offset (TMAC_DWCXL_CORE_BaseAddress + 0xc4 ) +#define TMAC_RWK_Filter01_CRC (TMAC_DWCXL_CORE_BaseAddress + 0xc4 ) +#define TMAC_RWK_Filter0_Byte_Mask (TMAC_DWCXL_CORE_BaseAddress + 0xc4 ) +#define TMAC_RWK_Filter1_Byte_Mask (TMAC_DWCXL_CORE_BaseAddress + 0xc4 ) +#define TMAC_RWK_Filter23_CRC (TMAC_DWCXL_CORE_BaseAddress + 0xc4 ) +#define TMAC_RWK_Filter2_Byte_Mask (TMAC_DWCXL_CORE_BaseAddress + 0xc4 ) +#define TMAC_RWK_Filter3_Byte_Mask (TMAC_DWCXL_CORE_BaseAddress + 0xc4 ) +#define TMAC_MAC_LPI_Control_Status (TMAC_DWCXL_CORE_BaseAddress + 0xd0 ) +#define TMAC_MAC_LPI_Timers_Control (TMAC_DWCXL_CORE_BaseAddress + 0xd4 ) +#define TMAC_MAC_LPI_Auto_Entry_Timer (TMAC_DWCXL_CORE_BaseAddress + 0xd8 ) +#define TMAC_MAC_1US_Tic_Counter (TMAC_DWCXL_CORE_BaseAddress + 0xdc ) +#define TMAC_MAC_Version (TMAC_DWCXL_CORE_BaseAddress + 0x110) +#define TMAC_MAC_Debug (TMAC_DWCXL_CORE_BaseAddress + 0x114) +#define TMAC_MAC_HW_Feature0 (TMAC_DWCXL_CORE_BaseAddress + 0x11c) +#define TMAC_MAC_HW_Feature1 (TMAC_DWCXL_CORE_BaseAddress + 0x120) +#define TMAC_MAC_HW_Feature2 (TMAC_DWCXL_CORE_BaseAddress + 0x124) +#define TMAC_MAC_RxQ_Enable_Ctrl0 (TMAC_DWCXL_CORE_BaseAddress + 0x140) +#define TMAC_MAC_RxQ_Mapping_Ctrl0 (TMAC_DWCXL_CORE_BaseAddress + 0x150) +#define TMAC_MAC_RxQ_Mapping_Ctrl1 (TMAC_DWCXL_CORE_BaseAddress + 0x154) +#define TMAC_MAC_RxQ_Priority_Mapping_Ctrl0 (TMAC_DWCXL_CORE_BaseAddress + 0x160) +#define TMAC_MAC_RxQ_Priority_Mapping_Ctrl1 (TMAC_DWCXL_CORE_BaseAddress + 0x164) +#define TMAC_MDIO_Single_Command_Address (TMAC_DWCXL_CORE_BaseAddress + 0x200) +#define TMAC_MDIO_Single_Command_Control_Data (TMAC_DWCXL_CORE_BaseAddress + 0x204) +#define TMAC_MDIO_Continuous_Write_Address (TMAC_DWCXL_CORE_BaseAddress + 0x208) +#define TMAC_MDIO_Continuous_Write_Data (TMAC_DWCXL_CORE_BaseAddress + 0x20c) +#define TMAC_MDIO_Continuous_Scan_Port_Enable (TMAC_DWCXL_CORE_BaseAddress + 0x210) +#define TMAC_MDIO_Interrupt_Status (TMAC_DWCXL_CORE_BaseAddress + 0x214) +#define TMAC_MDIO_Interrupt_Enable (TMAC_DWCXL_CORE_BaseAddress + 0x218) +#define TMAC_MDIO_Port_Connect_Disconnect_Status (TMAC_DWCXL_CORE_BaseAddress + 0x21c) +#define TMAC_MDIO_Clause_22_Port (TMAC_DWCXL_CORE_BaseAddress + 0x220) +#define TMAC_MDIO_Port0_Device_In_Use (TMAC_DWCXL_CORE_BaseAddress + 0x230) +#define TMAC_MDIO_Port0_Link_Status (TMAC_DWCXL_CORE_BaseAddress + 0x234) +#define TMAC_MDIO_Port0_Alive_Status (TMAC_DWCXL_CORE_BaseAddress + 0x238) +#define TMAC_MDIO_Port1_Device_In_Use (TMAC_DWCXL_CORE_BaseAddress + 0x240) +#define TMAC_MDIO_Port1_Link_Status (TMAC_DWCXL_CORE_BaseAddress + 0x244) +#define TMAC_MDIO_Port1_Alive_Status (TMAC_DWCXL_CORE_BaseAddress + 0x248) +#define TMAC_MDIO_Port2_Device_In_Use (TMAC_DWCXL_CORE_BaseAddress + 0x250) +#define TMAC_MDIO_Port2_Link_Status (TMAC_DWCXL_CORE_BaseAddress + 0x254) +#define TMAC_MDIO_Port2_Alive_Status (TMAC_DWCXL_CORE_BaseAddress + 0x258) +#define TMAC_MDIO_Port3_Device_In_Use (TMAC_DWCXL_CORE_BaseAddress + 0x260) +#define TMAC_MDIO_Port3_Link_Status (TMAC_DWCXL_CORE_BaseAddress + 0x264) +#define TMAC_MDIO_Port3_Alive_Status (TMAC_DWCXL_CORE_BaseAddress + 0x268) +#define TMAC_MAC_Address0_High (TMAC_DWCXL_CORE_BaseAddress + 0x300) +#define TMAC_MAC_Address0_Low (TMAC_DWCXL_CORE_BaseAddress + 0x304) +#define TMAC_MAC_Address1_High (TMAC_DWCXL_CORE_BaseAddress + 0x308) +#define TMAC_MAC_Address1_Low (TMAC_DWCXL_CORE_BaseAddress + 0x30c) +#define TMAC_MAC_Address2_High (TMAC_DWCXL_CORE_BaseAddress + 0x310) +#define TMAC_MAC_Address2_Low (TMAC_DWCXL_CORE_BaseAddress + 0x314) +#define TMAC_MAC_Address3_High (TMAC_DWCXL_CORE_BaseAddress + 0x318) +#define TMAC_MAC_Address3_Low (TMAC_DWCXL_CORE_BaseAddress + 0x31c) +#define TMAC_MAC_Address4_High (TMAC_DWCXL_CORE_BaseAddress + 0x320) +#define TMAC_MAC_Address4_Low (TMAC_DWCXL_CORE_BaseAddress + 0x324) +#define TMAC_MAC_Address5_High (TMAC_DWCXL_CORE_BaseAddress + 0x328) +#define TMAC_MAC_Address5_Low (TMAC_DWCXL_CORE_BaseAddress + 0x32c) +#define TMAC_MAC_Address6_High (TMAC_DWCXL_CORE_BaseAddress + 0x330) +#define TMAC_MAC_Address6_Low (TMAC_DWCXL_CORE_BaseAddress + 0x334) +#define TMAC_MAC_Address7_High (TMAC_DWCXL_CORE_BaseAddress + 0x338) +#define TMAC_MAC_Address7_Low (TMAC_DWCXL_CORE_BaseAddress + 0x33c) +#define TMAC_MAC_Address8_High (TMAC_DWCXL_CORE_BaseAddress + 0x340) +#define TMAC_MAC_Address8_Low (TMAC_DWCXL_CORE_BaseAddress + 0x344) +#define TMAC_MMC_Control (TMAC_DWCXL_CORE_BaseAddress + 0x800) +#define TMAC_MMC_Receive_Interrupt (TMAC_DWCXL_CORE_BaseAddress + 0x804) +#define TMAC_MMC_Transmit_Interrupt (TMAC_DWCXL_CORE_BaseAddress + 0x808) +#define TMAC_MMC_Receive_Interrupt_Enable (TMAC_DWCXL_CORE_BaseAddress + 0x80c) +#define TMAC_MMC_Transmit_Interrupt_Enable (TMAC_DWCXL_CORE_BaseAddress + 0x810) +#define TMAC_Tx_Octet_Count_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x814) +#define TMAC_Tx_Octet_Count_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x818) +#define TMAC_Tx_Frame_Count_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x81c) +#define TMAC_Tx_Frame_Count_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x820) +#define TMAC_Tx_Broadcast_Frames_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x824) +#define TMAC_Tx_Broadcast_Frames_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x828) +#define TMAC_Tx_Multicast_Frames_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x82c) +#define TMAC_Tx_Multicast_Frames_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x830) +#define TMAC_Tx_64Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x834) +#define TMAC_Tx_64Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x838) +#define TMAC_Tx_65To127Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x83c) +#define TMAC_Tx_65To127Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x840) +#define TMAC_Tx_128To255Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x844) +#define TMAC_Tx_128To255Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x848) +#define TMAC_Tx_256To511Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x84c) +#define TMAC_Tx_256To511Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x850) +#define TMAC_Tx_512To1023Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x854) +#define TMAC_Tx_512To1023Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x858) +#define TMAC_Tx_1024ToMaxOctets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x85c) +#define TMAC_Tx_1024ToMaxOctets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x860) +#define TMAC_Tx_Unicast_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x864) +#define TMAC_Tx_Unicast_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x868) +#define TMAC_Tx_Multicast_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x86c) +#define TMAC_Tx_Multicast_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x870) +#define TMAC_Tx_Broadcast_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x874) +#define TMAC_Tx_Broadcast_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x878) +#define TMAC_Tx_Underflow_Error_Frames_Low (TMAC_DWCXL_CORE_BaseAddress + 0x87c) +#define TMAC_Tx_Underflow_Error_Frames_High (TMAC_DWCXL_CORE_BaseAddress + 0x880) +#define TMAC_Tx_Octet_Count_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x884) +#define TMAC_Tx_Octet_Count_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x888) +#define TMAC_Tx_Frame_Count_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x88c) +#define TMAC_Tx_Frame_Count_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x890) +#define TMAC_Tx_Pause_Frames_Low (TMAC_DWCXL_CORE_BaseAddress + 0x894) +#define TMAC_Tx_Pause_Frames_High (TMAC_DWCXL_CORE_BaseAddress + 0x898) +#define TMAC_Tx_VLAN_Frames_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x89c) +#define TMAC_Tx_VLAN_Frames_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x8a0) +#define TMAC_Rx_Frame_Count_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x900) +#define TMAC_Rx_Frame_Count_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x904) +#define TMAC_Rx_Octet_Count_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x908) +#define TMAC_Rx_Octet_Count_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x90c) +#define TMAC_Rx_Octet_Count_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x910) +#define TMAC_Rx_Octet_Count_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x914) +#define TMAC_Rx_Broadcast_Frames_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x918) +#define TMAC_Rx_Broadcast_Frames_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x91c) +#define TMAC_Rx_Multicast_Frames_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x920) +#define TMAC_Rx_Multicast_Frames_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x924) +#define TMAC_Rx_CRC_Error_Frames_Low (TMAC_DWCXL_CORE_BaseAddress + 0x928) +#define TMAC_Rx_CRC_Error_Frames_High (TMAC_DWCXL_CORE_BaseAddress + 0x92c) +#define TMAC_Rx_Runt_Error_Frames (TMAC_DWCXL_CORE_BaseAddress + 0x930) +#define TMAC_Rx_Jabber_Error_Frames (TMAC_DWCXL_CORE_BaseAddress + 0x934) +#define TMAC_Rx_Undersize_Frames_Good (TMAC_DWCXL_CORE_BaseAddress + 0x938) +#define TMAC_Rx_Oversize_Frames_Good (TMAC_DWCXL_CORE_BaseAddress + 0x93c) +#define TMAC_Rx_64Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x940) +#define TMAC_Rx_64Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x944) +#define TMAC_Rx_65To127Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x948) +#define TMAC_Rx_65To127Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x94c) +#define TMAC_Rx_128To255Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x950) +#define TMAC_Rx_128To255Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x954) +#define TMAC_Rx_256To511Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x958) +#define TMAC_Rx_256To511Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x95c) +#define TMAC_Rx_512To1023Octets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x960) +#define TMAC_Rx_512To1023Octets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x964) +#define TMAC_Rx_1024ToMaxOctets_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x968) +#define TMAC_Rx_1024ToMaxOctets_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x96c) +#define TMAC_Rx_Unicast_Frames_Good_Low (TMAC_DWCXL_CORE_BaseAddress + 0x970) +#define TMAC_Rx_Unicast_Frames_Good_High (TMAC_DWCXL_CORE_BaseAddress + 0x974) +#define TMAC_Rx_Length_Error_Frames_Low (TMAC_DWCXL_CORE_BaseAddress + 0x978) +#define TMAC_Rx_Length_Error_Frames_High (TMAC_DWCXL_CORE_BaseAddress + 0x97c) +#define TMAC_Rx_OutofRange_Frames_Low (TMAC_DWCXL_CORE_BaseAddress + 0x980) +#define TMAC_Rx_OutofRange_Frames_High (TMAC_DWCXL_CORE_BaseAddress + 0x984) +#define TMAC_Rx_Pause_Frames_Low (TMAC_DWCXL_CORE_BaseAddress + 0x988) +#define TMAC_Rx_Pause_Frames_High (TMAC_DWCXL_CORE_BaseAddress + 0x98c) +#define TMAC_Rx_VLAN_Frames_Good_Bad_Low (TMAC_DWCXL_CORE_BaseAddress + 0x998) +#define TMAC_Rx_VLAN_Frames_Good_Bad_High (TMAC_DWCXL_CORE_BaseAddress + 0x99c) +#define TMAC_Rx_Watchdog_Error_Frames (TMAC_DWCXL_CORE_BaseAddress + 0x9a0) +#define TMAC_MAC_L3_L4_Address_Control (TMAC_DWCXL_CORE_BaseAddress + 0xc00) +#define TMAC_MAC_L3_L4_Control0 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_L3_L4_Control1 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_L3_L4_Control2 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_L3_L4_Control3 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_L3_L4_Data (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer3_Addr0_Reg0 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer3_Addr0_Reg1 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer3_Addr0_Reg2 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer3_Addr0_Reg3 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer3_Addr1_Reg0 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer3_Addr1_Reg1 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer3_Addr1_Reg2 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer3_Addr1_Reg3 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer3_Addr2_Reg0 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer3_Addr2_Reg1 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer3_Addr2_Reg2 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer3_Addr2_Reg3 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer3_Addr3_Reg0 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer3_Addr3_Reg1 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer3_Addr3_Reg2 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer3_Addr3_Reg3 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer4_Address0 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer4_Address1 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer4_Address2 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_Layer4_Address3 (TMAC_DWCXL_CORE_BaseAddress + 0xc04) +#define TMAC_MAC_RSS_Control (TMAC_DWCXL_CORE_BaseAddress + 0xc80) +#define TMAC_MAC_RSS_Address (TMAC_DWCXL_CORE_BaseAddress + 0xc88) +#define TMAC_MAC_RSS_Data (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Hash_Key11_8 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Hash_Key15_12 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Hash_Key19_16 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Hash_Key23_20 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Hash_Key27_24 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Hash_Key31_28 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Hash_Key35_32 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Hash_Key39_36 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Hash_Key3_0 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Hash_Key7_4 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data0 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data1 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data10 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data11 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data12 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data13 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data14 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data15 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data16 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data17 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data18 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data19 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data2 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data20 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data21 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data22 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data23 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data24 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data25 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data26 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data27 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data28 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data29 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data3 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data30 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data31 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data32 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data33 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data34 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data35 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data36 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data37 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data38 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data39 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data4 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data40 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data41 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data42 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data43 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data44 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data45 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data46 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data47 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data48 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data49 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data5 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data50 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data51 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data52 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data53 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data54 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data55 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data56 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data57 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data58 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data59 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data6 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data60 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data61 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data62 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data63 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data7 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data8 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_RSS_Lookup_Data9 (TMAC_DWCXL_CORE_BaseAddress + 0xc8c) +#define TMAC_MAC_Timestamp_Control (TMAC_DWCXL_CORE_BaseAddress + 0xd00) +#define TMAC_MAC_Sub_Second_Increment (TMAC_DWCXL_CORE_BaseAddress + 0xd04) +#define TMAC_MAC_System_Time_Seconds (TMAC_DWCXL_CORE_BaseAddress + 0xd08) +#define TMAC_MAC_System_Time_Nanoseconds (TMAC_DWCXL_CORE_BaseAddress + 0xd0c) +#define TMAC_MAC_System_Time_Seconds_Update (TMAC_DWCXL_CORE_BaseAddress + 0xd10) +#define TMAC_MAC_System_Time_Nanoseconds_Update (TMAC_DWCXL_CORE_BaseAddress + 0xd14) +#define TMAC_MAC_Timestamp_Addend (TMAC_DWCXL_CORE_BaseAddress + 0xd18) +#define TMAC_MAC_System_Time_Higher_Word_Seconds (TMAC_DWCXL_CORE_BaseAddress + 0xd1c) +#define TMAC_MAC_Timestamp_Status (TMAC_DWCXL_CORE_BaseAddress + 0xd20) +#define TMAC_MAC_Tx_Timestamp_Status_Nanoseconds (TMAC_DWCXL_CORE_BaseAddress + 0xd30) +#define TMAC_MAC_Tx_Timestamp_Status_Seconds (TMAC_DWCXL_CORE_BaseAddress + 0xd34) +#define TMAC_MAC_Auxiliary_Control (TMAC_DWCXL_CORE_BaseAddress + 0xd40) +#define TMAC_MAC_Auxiliary_Timestamp_Nanoseconds (TMAC_DWCXL_CORE_BaseAddress + 0xd48) +#define TMAC_MAC_Auxiliary_Timestamp_Seconds (TMAC_DWCXL_CORE_BaseAddress + 0xd4c) +#define TMAC_MAC_Timestamp_Ingress_Asym_Corr (TMAC_DWCXL_CORE_BaseAddress + 0xd50) +#define TMAC_MAC_Timestamp_Egress_Asym_Corr (TMAC_DWCXL_CORE_BaseAddress + 0xd54) +#define TMAC_MAC_Timestamp_Ingress_Corr_Nanosecond (TMAC_DWCXL_CORE_BaseAddress + 0xd58) +#define TMAC_MAC_Timestamp_Ingress_Corr_Subnanosecond (TMAC_DWCXL_CORE_BaseAddress + 0xd5c) +#define TMAC_MAC_Timestamp_Egress_Corr_Nanosecond (TMAC_DWCXL_CORE_BaseAddress + 0xd60) +#define TMAC_MAC_Timestamp_Egress_Corr_Subnanosecond (TMAC_DWCXL_CORE_BaseAddress + 0xd64) +#define TMAC_MAC_PPS_Control (TMAC_DWCXL_CORE_BaseAddress + 0xd70) +#define TMAC_MAC_PPS0_Target_Time_Seconds (TMAC_DWCXL_CORE_BaseAddress + 0xd80) +#define TMAC_MAC_PPS0_Target_Time_Nanoseconds (TMAC_DWCXL_CORE_BaseAddress + 0xd84) +#define TMAC_MAC_PPS0_Interval (TMAC_DWCXL_CORE_BaseAddress + 0xd88) +#define TMAC_MAC_PPS0_Width (TMAC_DWCXL_CORE_BaseAddress + 0xd8c) + + + + +#define TMAC_MTL_Operation_Mode (TMAC_DWCXL_MTL_BaseAddress + 0x0 ) +#define TMAC_MTL_Debug_Control (TMAC_DWCXL_MTL_BaseAddress + 0x8 ) +#define TMAC_MTL_Debug_Status (TMAC_DWCXL_MTL_BaseAddress + 0xc ) +#define TMAC_MTL_FIFO_Debug_Data (TMAC_DWCXL_MTL_BaseAddress + 0x10) +#define TMAC_MTL_Interrupt_Status (TMAC_DWCXL_MTL_BaseAddress + 0x20) +#define TMAC_MTL_RxQ_DMA_Map0 (TMAC_DWCXL_MTL_BaseAddress + 0x30) +#define TMAC_MTL_RxQ_DMA_Map1 (TMAC_DWCXL_MTL_BaseAddress + 0x34) +#define TMAC_MTL_TC_Prty_Map0 (TMAC_DWCXL_MTL_BaseAddress + 0x40) +#define TMAC_MTL_TC_Prty_Map1 (TMAC_DWCXL_MTL_BaseAddress + 0x44) + +#define TMAC_MTL_TxQ0_Operation_Mode (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x0 ) +#define TMAC_MTL_TxQ0_Underflow (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x4 ) +#define TMAC_MTL_TxQ0_Debug (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x8 ) +#define TMAC_MTL_TC0_ETS_Control (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x10) +#define TMAC_MTL_TC0_ETS_Status (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x14) +#define TMAC_MTL_TC0_Quantum_Weight (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x18) +#define TMAC_MTL_RxQ0_Operation_Mode (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x40) +#define TMAC_MTL_RxQ0_Missed_Pkt_Overflow_Cnt (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x44) +#define TMAC_MTL_RxQ0_Debug (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x48) +#define TMAC_MTL_RxQ0_Control (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x4c) +#define TMAC_MTL_RxQ0_Flow_Control (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x50) +#define TMAC_MTL_Q0_Interrupt_Enable (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x70) +#define TMAC_MTL_Q0_Interrupt_Status (TMAC_DWCXL_MTL_TCQ0_BaseAddress + 0x74) + +#define TMAC_MTL_TxQ1_Operation_Mode (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x0 ) +#define TMAC_MTL_TxQ1_Underflow (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x4 ) +#define TMAC_MTL_TxQ1_Debug (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x8 ) +#define TMAC_MTL_TC1_ETS_Control (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x10) +#define TMAC_MTL_TC1_ETS_Status (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x14) +#define TMAC_MTL_TC1_Quantum_Weight (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x18) +#define TMAC_MTL_RxQ1_Operation_Mode (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x40) +#define TMAC_MTL_RxQ1_Missed_Pkt_Overflow_Cnt (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x44) +#define TMAC_MTL_RxQ1_Debug (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x48) +#define TMAC_MTL_RxQ1_Control (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x4c) +#define TMAC_MTL_RxQ1_Flow_Control (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x50) +#define TMAC_MTL_Q1_Interrupt_Enable (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x70) +#define TMAC_MTL_Q1_Interrupt_Status (TMAC_DWCXL_MTL_TCQ1_BaseAddress + 0x74) + +#define TMAC_MTL_TxQ2_Operation_Mode (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x0 ) +#define TMAC_MTL_TxQ2_Underflow (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x4 ) +#define TMAC_MTL_TxQ2_Debug (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x8 ) +#define TMAC_MTL_TC2_ETS_Control (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x10) +#define TMAC_MTL_TC2_ETS_Status (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x14) +#define TMAC_MTL_TC2_Quantum_Weight (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x18) +#define TMAC_MTL_RxQ2_Operation_Mode (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x40) +#define TMAC_MTL_RxQ2_Missed_Pkt_Overflow_Cnt (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x44) +#define TMAC_MTL_RxQ2_Debug (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x48) +#define TMAC_MTL_RxQ2_Control (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x4c) +#define TMAC_MTL_RxQ2_Flow_Control (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x50) +#define TMAC_MTL_Q2_Interrupt_Enable (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x70) +#define TMAC_MTL_Q2_Interrupt_Status (TMAC_DWCXL_MTL_TCQ2_BaseAddress + 0x74) + +#define TMAC_MTL_TxQ3_Operation_Mode (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x0 ) +#define TMAC_MTL_TxQ3_Underflow (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x4 ) +#define TMAC_MTL_TxQ3_Debug (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x8 ) +#define TMAC_MTL_TC3_ETS_Control (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x10) +#define TMAC_MTL_TC3_ETS_Status (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x14) +#define TMAC_MTL_TC3_Quantum_Weight (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x18) +#define TMAC_MTL_TC3_SendSlopeCredit (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x1c) +#define TMAC_MTL_RxQ3_Operation_Mode (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x40) +#define TMAC_MTL_RxQ3_Missed_Pkt_Overflow_Cnt (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x44) +#define TMAC_MTL_RxQ3_Debug (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x48) +#define TMAC_MTL_RxQ3_Control (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x4c) +#define TMAC_MTL_RxQ3_Flow_Control (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x50) +#define TMAC_MTL_Q3_Interrupt_Enable (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x70) +#define TMAC_MTL_Q3_Interrupt_Status (TMAC_DWCXL_MTL_TCQ3_BaseAddress + 0x74) + +#define TMAC_MTL_TxQ4_Operation_Mode (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x0 ) +#define TMAC_MTL_TxQ4_Underflow (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x4 ) +#define TMAC_MTL_TxQ4_Debug (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x8 ) +#define TMAC_MTL_TC4_ETS_Control (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x10) +#define TMAC_MTL_TC4_ETS_Status (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x14) +#define TMAC_MTL_TC4_Quantum_Weight (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x18) +#define TMAC_MTL_TC4_SendSlopeCredit (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x1c) +#define TMAC_MTL_TC4_HiCredit (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x20) +#define TMAC_MTL_TC4_LoCredit (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x24) +#define TMAC_MTL_RxQ4_Operation_Mode (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x40) +#define TMAC_MTL_RxQ4_Missed_Pkt_Overflow_Cnt (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x44) +#define TMAC_MTL_RxQ4_Debug (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x48) +#define TMAC_MTL_RxQ4_Control (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x4c) +#define TMAC_MTL_RxQ4_Flow_Control (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x50) +#define TMAC_MTL_Q4_Interrupt_Enable (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x70) +#define TMAC_MTL_Q4_Interrupt_Status (TMAC_DWCXL_MTL_TCQ4_BaseAddress + 0x74) + +#define TMAC_MTL_TxQ5_Operation_Mode (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x0 ) +#define TMAC_MTL_TxQ5_Underflow (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x4 ) +#define TMAC_MTL_TxQ5_Debug (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x8 ) +#define TMAC_MTL_TC5_ETS_Control (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x10) +#define TMAC_MTL_TC5_ETS_Status (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x14) +#define TMAC_MTL_TC5_Quantum_Weight (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x18) +#define TMAC_MTL_TC5_SendSlopeCredit (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x1c) +#define TMAC_MTL_TC5_HiCredit (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x20) +#define TMAC_MTL_TC5_LoCredit (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x24) +#define TMAC_MTL_RxQ5_Operation_Mode (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x40) +#define TMAC_MTL_RxQ5_Missed_Pkt_Overflow_Cnt (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x44) +#define TMAC_MTL_RxQ5_Debug (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x48) +#define TMAC_MTL_RxQ5_Control (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x4c) +#define TMAC_MTL_RxQ5_Flow_Control (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x50) +#define TMAC_MTL_Q5_Interrupt_Enable (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x70) +#define TMAC_MTL_Q5_Interrupt_Status (TMAC_DWCXL_MTL_TCQ5_BaseAddress + 0x74) + + + +#define TMAC_DMA_Mode (TMAC_DWCXL_DMA_BaseAddress + 0x0 ) +#define TMAC_DMA_SysBus_Mode (TMAC_DWCXL_DMA_BaseAddress + 0x4 ) +#define TMAC_DMA_Interrupt_Status (TMAC_DWCXL_DMA_BaseAddress + 0x8 ) +#define TMAC_AXI_Tx_AR_ACE_Control (TMAC_DWCXL_DMA_BaseAddress + 0x10) +#define TMAC_AXI_Rx_AW_ACE_Control (TMAC_DWCXL_DMA_BaseAddress + 0x18) +#define TMAC_AXI_TxRx_AWAR_ACE_Control (TMAC_DWCXL_DMA_BaseAddress + 0x1c) +#define TMAC_DMA_Debug_Status0 (TMAC_DWCXL_DMA_BaseAddress + 0x20) +#define TMAC_DMA_Debug_Status1 (TMAC_DWCXL_DMA_BaseAddress + 0x24) +#define TMAC_DMA_Debug_Status3 (TMAC_DWCXL_DMA_BaseAddress + 0x2c) +#define TMAC_DMA_Tx_EDMA_Control (TMAC_DWCXL_DMA_BaseAddress + 0x40) +#define TMAC_DMA_Rx_EDMA_Control (TMAC_DWCXL_DMA_BaseAddress + 0x44) +#define TMAC_AXI_LPI_Entry_Interval (TMAC_DWCXL_DMA_BaseAddress + 0x50) + +#define TMAC_DMA_CH0_Control (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x0 ) +#define TMAC_DMA_CH0_Tx_Control (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x4 ) +#define TMAC_DMA_CH0_Rx_Control (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x8 ) +#define TMAC_DMA_CH0_TxDesc_List_HAddress (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x10) +#define TMAC_DMA_CH0_TxDesc_List_LAddress (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x14) +#define TMAC_DMA_CH0_RxDesc_List_HAddress (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x18) +#define TMAC_DMA_CH0_RxDesc_List_LAddress (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x1c) +#define TMAC_DMA_CH0_TxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x20) +#define TMAC_DMA_CH0_TxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x24) +#define TMAC_DMA_CH0_RxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x28) +#define TMAC_DMA_CH0_RxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x2c) +#define TMAC_DMA_CH0_TxDesc_Ring_Length (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x30) +#define TMAC_DMA_CH0_RxDesc_Ring_Length (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x34) +#define TMAC_DMA_CH0_Interrupt_Enable (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x38) +#define TMAC_DMA_CH0_Rx_Interrupt_Watchdog_Timer (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x3c) +#define TMAC_DMA_CH0_Current_App_TxDesc_L (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x44) +#define TMAC_DMA_CH0_Current_App_RxDesc_L (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x4c) +#define TMAC_DMA_CH0_Current_App_TxBuffer_H (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x50) +#define TMAC_DMA_CH0_Current_App_TxBuffer_L (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x54) +#define TMAC_DMA_CH0_Current_App_RxBuffer_H (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x58) +#define TMAC_DMA_CH0_Current_App_RxBuffer_L (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x5c) +#define TMAC_DMA_CH0_Status (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x60) +#define TMAC_DMA_CH0_Debug_Status (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x64) +#define TMAC_DMA_CH0_Desc_Mem_Cache_Fill_Level (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x68) +#define TMAC_DMA_CH0_Miss_Frame_Cnt (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x6c) +#define TMAC_DMA_CH0_Tx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x70) +#define TMAC_DMA_CH0_Rx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x74) +#define TMAC_DMA_CH0_Tx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x78) +#define TMAC_DMA_CH0_Rx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH0_BaseAddress + 0x7c) + +#define TMAC_DMA_CH1_Control (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x0 ) +#define TMAC_DMA_CH1_Tx_Control (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x4 ) +#define TMAC_DMA_CH1_Rx_Control (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x8 ) +#define TMAC_DMA_CH1_TxDesc_List_HAddress (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x10) +#define TMAC_DMA_CH1_TxDesc_List_LAddress (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x14) +#define TMAC_DMA_CH1_RxDesc_List_HAddress (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x18) +#define TMAC_DMA_CH1_RxDesc_List_LAddress (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x1c) +#define TMAC_DMA_CH1_TxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x20) +#define TMAC_DMA_CH1_TxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x24) +#define TMAC_DMA_CH1_RxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x28) +#define TMAC_DMA_CH1_RxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x2c) +#define TMAC_DMA_CH1_TxDesc_Ring_Length (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x30) +#define TMAC_DMA_CH1_RxDesc_Ring_Length (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x34) +#define TMAC_DMA_CH1_Interrupt_Enable (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x38) +#define TMAC_DMA_CH1_Rx_Interrupt_Watchdog_Timer (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x3c) +#define TMAC_DMA_CH1_Current_App_TxDesc_L (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x44) +#define TMAC_DMA_CH1_Current_App_RxDesc_L (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x4c) +#define TMAC_DMA_CH1_Current_App_TxBuffer_H (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x50) +#define TMAC_DMA_CH1_Current_App_TxBuffer_L (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x54) +#define TMAC_DMA_CH1_Current_App_RxBuffer_H (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x58) +#define TMAC_DMA_CH1_Current_App_RxBuffer_L (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x5c) +#define TMAC_DMA_CH1_Status (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x60) +#define TMAC_DMA_CH1_Debug_Status (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x64) +#define TMAC_DMA_CH1_Desc_Mem_Cache_Fill_Level (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x68) +#define TMAC_DMA_CH1_Miss_Frame_Cnt (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x6c) +#define TMAC_DMA_CH1_Tx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x70) +#define TMAC_DMA_CH1_Rx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x74) +#define TMAC_DMA_CH1_Tx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x78) +#define TMAC_DMA_CH1_Rx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH1_BaseAddress + 0x7c) + +#define TMAC_DMA_CH2_Control (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x0 ) +#define TMAC_DMA_CH2_Tx_Control (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x4 ) +#define TMAC_DMA_CH2_Rx_Control (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x8 ) +#define TMAC_DMA_CH2_TxDesc_List_HAddress (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x10) +#define TMAC_DMA_CH2_TxDesc_List_LAddress (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x14) +#define TMAC_DMA_CH2_RxDesc_List_HAddress (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x18) +#define TMAC_DMA_CH2_RxDesc_List_LAddress (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x1c) +#define TMAC_DMA_CH2_TxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x20) +#define TMAC_DMA_CH2_TxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x24) +#define TMAC_DMA_CH2_RxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x28) +#define TMAC_DMA_CH2_RxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x2c) +#define TMAC_DMA_CH2_TxDesc_Ring_Length (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x30) +#define TMAC_DMA_CH2_RxDesc_Ring_Length (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x34) +#define TMAC_DMA_CH2_Interrupt_Enable (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x38) +#define TMAC_DMA_CH2_Rx_Interrupt_Watchdog_Timer (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x3c) +#define TMAC_DMA_CH2_Current_App_TxDesc_L (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x44) +#define TMAC_DMA_CH2_Current_App_RxDesc_L (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x4c) +#define TMAC_DMA_CH2_Current_App_TxBuffer_H (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x50) +#define TMAC_DMA_CH2_Current_App_TxBuffer_L (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x54) +#define TMAC_DMA_CH2_Current_App_RxBuffer_H (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x58) +#define TMAC_DMA_CH2_Current_App_RxBuffer_L (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x5c) +#define TMAC_DMA_CH2_Status (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x60) +#define TMAC_DMA_CH2_Debug_Status (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x64) +#define TMAC_DMA_CH2_Desc_Mem_Cache_Fill_Level (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x68) +#define TMAC_DMA_CH2_Miss_Frame_Cnt (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x6c) +#define TMAC_DMA_CH2_Tx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x70) +#define TMAC_DMA_CH2_Rx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x74) +#define TMAC_DMA_CH2_Tx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x78) +#define TMAC_DMA_CH2_Rx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH2_BaseAddress + 0x7c) + +#define TMAC_DMA_CH3_Control (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x0 ) +#define TMAC_DMA_CH3_Tx_Control (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x4 ) +#define TMAC_DMA_CH3_Rx_Control (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x8 ) +#define TMAC_DMA_CH3_TxDesc_List_HAddress (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x10) +#define TMAC_DMA_CH3_TxDesc_List_LAddress (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x14) +#define TMAC_DMA_CH3_RxDesc_List_HAddress (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x18) +#define TMAC_DMA_CH3_RxDesc_List_LAddress (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x1c) +#define TMAC_DMA_CH3_TxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x20) +#define TMAC_DMA_CH3_TxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x24) +#define TMAC_DMA_CH3_RxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x28) +#define TMAC_DMA_CH3_RxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x2c) +#define TMAC_DMA_CH3_TxDesc_Ring_Length (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x30) +#define TMAC_DMA_CH3_RxDesc_Ring_Length (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x34) +#define TMAC_DMA_CH3_Interrupt_Enable (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x38) +#define TMAC_DMA_CH3_Rx_Interrupt_Watchdog_Timer (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x3c) +#define TMAC_DMA_CH3_Current_App_TxDesc_L (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x44) +#define TMAC_DMA_CH3_Current_App_RxDesc_L (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x4c) +#define TMAC_DMA_CH3_Current_App_TxBuffer_H (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x50) +#define TMAC_DMA_CH3_Current_App_TxBuffer_L (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x54) +#define TMAC_DMA_CH3_Current_App_RxBuffer_H (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x58) +#define TMAC_DMA_CH3_Current_App_RxBuffer_L (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x5c) +#define TMAC_DMA_CH3_Status (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x60) +#define TMAC_DMA_CH3_Debug_Status (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x64) +#define TMAC_DMA_CH3_Desc_Mem_Cache_Fill_Level (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x68) +#define TMAC_DMA_CH3_Miss_Frame_Cnt (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x6c) +#define TMAC_DMA_CH3_Tx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x70) +#define TMAC_DMA_CH3_Rx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x74) +#define TMAC_DMA_CH3_Tx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x78) +#define TMAC_DMA_CH3_Rx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH3_BaseAddress + 0x7c) + +#define TMAC_DMA_CH4_Control (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x0 ) +#define TMAC_DMA_CH4_Tx_Control (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x4 ) +#define TMAC_DMA_CH4_Rx_Control (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x8 ) +#define TMAC_DMA_CH4_TxDesc_List_HAddress (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x10) +#define TMAC_DMA_CH4_TxDesc_List_LAddress (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x14) +#define TMAC_DMA_CH4_RxDesc_List_HAddress (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x18) +#define TMAC_DMA_CH4_RxDesc_List_LAddress (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x1c) +#define TMAC_DMA_CH4_TxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x20) +#define TMAC_DMA_CH4_TxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x24) +#define TMAC_DMA_CH4_RxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x28) +#define TMAC_DMA_CH4_RxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x2c) +#define TMAC_DMA_CH4_TxDesc_Ring_Length (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x30) +#define TMAC_DMA_CH4_RxDesc_Ring_Length (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x34) +#define TMAC_DMA_CH4_Interrupt_Enable (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x38) +#define TMAC_DMA_CH4_Rx_Interrupt_Watchdog_Timer (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x3c) +#define TMAC_DMA_CH4_Current_App_TxDesc_L (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x44) +#define TMAC_DMA_CH4_Current_App_RxDesc_L (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x4c) +#define TMAC_DMA_CH4_Current_App_TxBuffer_H (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x50) +#define TMAC_DMA_CH4_Current_App_TxBuffer_L (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x54) +#define TMAC_DMA_CH4_Current_App_RxBuffer_H (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x58) +#define TMAC_DMA_CH4_Current_App_RxBuffer_L (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x5c) +#define TMAC_DMA_CH4_Status (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x60) +#define TMAC_DMA_CH4_Debug_Status (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x64) +#define TMAC_DMA_CH4_Desc_Mem_Cache_Fill_Level (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x68) +#define TMAC_DMA_CH4_Miss_Frame_Cnt (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x6c) +#define TMAC_DMA_CH4_Tx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x70) +#define TMAC_DMA_CH4_Rx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x74) +#define TMAC_DMA_CH4_Tx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x78) +#define TMAC_DMA_CH4_Rx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH4_BaseAddress + 0x7c) + +#define TMAC_DMA_CH5_Control (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x0 ) +#define TMAC_DMA_CH5_Tx_Control (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x4 ) +#define TMAC_DMA_CH5_Rx_Control (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x8 ) +#define TMAC_DMA_CH5_TxDesc_List_HAddress (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x10) +#define TMAC_DMA_CH5_TxDesc_List_LAddress (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x14) +#define TMAC_DMA_CH5_RxDesc_List_HAddress (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x18) +#define TMAC_DMA_CH5_RxDesc_List_LAddress (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x1c) +#define TMAC_DMA_CH5_TxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x20) +#define TMAC_DMA_CH5_TxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x24) +#define TMAC_DMA_CH5_RxDesc_Tail_HPointer (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x28) +#define TMAC_DMA_CH5_RxDesc_Tail_LPointer (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x2c) +#define TMAC_DMA_CH5_TxDesc_Ring_Length (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x30) +#define TMAC_DMA_CH5_RxDesc_Ring_Length (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x34) +#define TMAC_DMA_CH5_Interrupt_Enable (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x38) +#define TMAC_DMA_CH5_Rx_Interrupt_Watchdog_Timer (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x3c) +#define TMAC_DMA_CH5_Current_App_TxDesc_L (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x44) +#define TMAC_DMA_CH5_Current_App_RxDesc_L (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x4c) +#define TMAC_DMA_CH5_Current_App_TxBuffer_H (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x50) +#define TMAC_DMA_CH5_Current_App_TxBuffer_L (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x54) +#define TMAC_DMA_CH5_Current_App_RxBuffer_H (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x58) +#define TMAC_DMA_CH5_Current_App_RxBuffer_L (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x5c) +#define TMAC_DMA_CH5_Status (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x60) +#define TMAC_DMA_CH5_Debug_Status (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x64) +#define TMAC_DMA_CH5_Desc_Mem_Cache_Fill_Level (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x68) +#define TMAC_DMA_CH5_Miss_Frame_Cnt (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x6c) +#define TMAC_DMA_CH5_Tx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x70) +#define TMAC_DMA_CH5_Rx_Data_Xfer_Ring_Offset (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x74) +#define TMAC_DMA_CH5_Tx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x78) +#define TMAC_DMA_CH5_Rx_Desc_Write_Ring_Offset (TMAC_DWCXL_DMA_CH5_BaseAddress + 0x7c) + +#define TMAC_DMA_Dummy (TMAC_DWCXL_DMA_DUMMY_BaseAddress + 0x4) + +#endif diff --git a/driver/rfic/ucp/base/inc/dw_tpcs.h b/driver/rfic/ucp/base/inc/dw_tpcs.h new file mode 100644 index 0000000..48d64c1 --- /dev/null +++ b/driver/rfic/ucp/base/inc/dw_tpcs.h @@ -0,0 +1,278 @@ +#ifndef __TPCS_H__ +#define __TPCS_H__ + + +#define TPCS_PMA_MMD_BaseAddress 0x090a0000 +#define TPCS_PCS_MMD_BaseAddress 0x090d0000 +#define TPCS_AN_MMD_BaseAddress 0x09100000 +#define TPCS_VS_MMD1_BaseAddress 0x09130000 + +//#define TPCS_PMA_MMD_BaseAddress 0x10000 +//#define TPCS_PCS_MMD_BaseAddress 0x30000 +//#define TPCS_AN_MMD_BaseAddress 0x70000 +//#define TPCS_VS_MMD1_BaseAddress 0x1e0000 + + +#define TPCS_SR_PMA_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x0 ) +#define TPCS_SR_PMA_STATUS1 (TPCS_PMA_MMD_BaseAddress + 4*0x1 ) +#define TPCS_SR_PMA_DEV_ID_1 (TPCS_PMA_MMD_BaseAddress + 4*0x2 ) +#define TPCS_SR_PMA_DEV_ID_2 (TPCS_PMA_MMD_BaseAddress + 4*0x3 ) +#define TPCS_SR_PMA_SPD_ABL (TPCS_PMA_MMD_BaseAddress + 4*0x4 ) +#define TPCS_SR_PMA_DEV_PKG1 (TPCS_PMA_MMD_BaseAddress + 4*0x5 ) +#define TPCS_SR_PMA_DEV_PKG2 (TPCS_PMA_MMD_BaseAddress + 4*0x6 ) +#define TPCS_SR_PMA_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x7 ) +#define TPCS_SR_PMA_STATUS2 (TPCS_PMA_MMD_BaseAddress + 4*0x8 ) +#define TPCS_SR_PMA_TX_DIS (TPCS_PMA_MMD_BaseAddress + 4*0x9 ) +#define TPCS_SR_PMA_RX_SIG_DET (TPCS_PMA_MMD_BaseAddress + 4*0xa ) +#define TPCS_SR_PMA_EXT_ABL (TPCS_PMA_MMD_BaseAddress + 4*0xb ) +#define TPCS_SR_PMA_EXT_ABL1 (TPCS_PMA_MMD_BaseAddress + 4*0xd ) +#define TPCS_SR_PMA_PKG1 (TPCS_PMA_MMD_BaseAddress + 4*0xe ) +#define TPCS_SR_PMA_PKG2 (TPCS_PMA_MMD_BaseAddress + 4*0xf ) +#define TPCS_SR_EEE_ABL (TPCS_PMA_MMD_BaseAddress + 4*0x10 ) +#define TPCS_SR_PMA_EXT_ABL2 (TPCS_PMA_MMD_BaseAddress + 4*0x13 ) +#define TPCS_SR_PMA_KR_PMD_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0x96 ) +#define TPCS_SR_PMA_KR_PMD_STS (TPCS_PMA_MMD_BaseAddress + 4*0x97 ) +#define TPCS_SR_PMA_KR_LP_CEU (TPCS_PMA_MMD_BaseAddress + 4*0x98 ) +#define TPCS_SR_PMA_KR_LP_CESTS (TPCS_PMA_MMD_BaseAddress + 4*0x99 ) +#define TPCS_SR_PMA_KR_LD_CEU (TPCS_PMA_MMD_BaseAddress + 4*0x9a ) +#define TPCS_SR_PMA_KR_LD_CESTS (TPCS_PMA_MMD_BaseAddress + 4*0x9b ) +#define TPCS_SR_PMA_KX_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0xa0 ) +#define TPCS_SR_PMA_KX_STS (TPCS_PMA_MMD_BaseAddress + 4*0xa1 ) +#define TPCS_SR_PMA_KR_FEC_ABL (TPCS_PMA_MMD_BaseAddress + 4*0xaa ) +#define TPCS_SR_PMA_KR_FEC_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0xab ) +#define TPCS_SR_PMA_KR_FEC_CORR_BLK1 (TPCS_PMA_MMD_BaseAddress + 4*0xac ) +#define TPCS_SR_PMA_KR_FEC_CORR_BLK2 (TPCS_PMA_MMD_BaseAddress + 4*0xad ) +#define TPCS_SR_PMA_KR_FEC_UCORR_BLK1 (TPCS_PMA_MMD_BaseAddress + 4*0xae ) +#define TPCS_SR_PMA_KR_FEC_UCORR_BLK2 (TPCS_PMA_MMD_BaseAddress + 4*0xaf ) +#define TPCS_SR_PMA_RS_FEC_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0xc8 ) +#define TPCS_SR_PMA_RS_FEC_STATUS (TPCS_PMA_MMD_BaseAddress + 4*0xc9 ) +#define TPCS_SR_PMA_RS_FEC_CORR_CW_CNTL (TPCS_PMA_MMD_BaseAddress + 4*0xca ) +#define TPCS_SR_PMA_RS_FEC_CORR_CW_CNTH (TPCS_PMA_MMD_BaseAddress + 4*0xcb ) +#define TPCS_SR_PMA_RS_FEC_UCOR_CW_CNTL (TPCS_PMA_MMD_BaseAddress + 4*0xcc ) +#define TPCS_SR_PMA_RS_FEC_UCOR_CW_CNTH (TPCS_PMA_MMD_BaseAddress + 4*0xcd ) +#define TPCS_SR_PMA_RS_FEC_LANE_MAP (TPCS_PMA_MMD_BaseAddress + 4*0xce ) +#define TPCS_SR_PMA_RS_FEC_ERR_CNTL_L0 (TPCS_PMA_MMD_BaseAddress + 4*0xd2 ) +#define TPCS_SR_PMA_RS_FEC_ERR_CNTH_L0 (TPCS_PMA_MMD_BaseAddress + 4*0xd3 ) +#define TPCS_SR_PMA_RS_FEC_ERR_CNTL_L1 (TPCS_PMA_MMD_BaseAddress + 4*0xd4 ) +#define TPCS_SR_PMA_RS_FEC_ERR_CNTH_L1 (TPCS_PMA_MMD_BaseAddress + 4*0xd5 ) +#define TPCS_SR_PMA_RS_FEC_ERR_CNTL_L2 (TPCS_PMA_MMD_BaseAddress + 4*0xd6 ) +#define TPCS_SR_PMA_RS_FEC_ERR_CNTH_L2 (TPCS_PMA_MMD_BaseAddress + 4*0xd7 ) +#define TPCS_SR_PMA_RS_FEC_ERR_CNTL_L3 (TPCS_PMA_MMD_BaseAddress + 4*0xd8 ) +#define TPCS_SR_PMA_RS_FEC_ERR_CNTH_L3 (TPCS_PMA_MMD_BaseAddress + 4*0xd9 ) +#define TPCS_SR_PMA_KR_FEC_CORR_BLK1_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x12c ) +#define TPCS_SR_PMA_KR_FEC_CORR_BLK2_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x12d ) +#define TPCS_SR_PMA_KR_FEC_CORR_BLK1_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x12e ) +#define TPCS_SR_PMA_KR_FEC_CORR_BLK2_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x12f ) +#define TPCS_SR_PMA_KR_FEC_CORR_BLK1_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x130 ) +#define TPCS_SR_PMA_KR_FEC_CORR_BLK2_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x131 ) +#define TPCS_SR_PMA_KR_FEC_CORR_BLK1_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x132 ) +#define TPCS_SR_PMA_KR_FEC_CORR_BLK2_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x133 ) +#define TPCS_SR_PMA_KR_FEC_UCORR_BLK1_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x2bc ) +#define TPCS_SR_PMA_KR_FEC_UCORR_BLK2_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x2bd ) +#define TPCS_SR_PMA_KR_FEC_UCORR_BLK1_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x2be ) +#define TPCS_SR_PMA_KR_FEC_UCORR_BLK2_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x2bf ) +#define TPCS_SR_PMA_KR_FEC_UCORR_BLK1_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x2c0 ) +#define TPCS_SR_PMA_KR_FEC_UCORR_BLK2_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x2c1 ) +#define TPCS_SR_PMA_KR_FEC_UCORR_BLK1_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x2c2 ) +#define TPCS_SR_PMA_KR_FEC_UCORR_BLK2_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x2c3 ) +#define TPCS_SR_PMA_MLN_KR_LP_CEU_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x44c ) +#define TPCS_SR_PMA_MLN_KR_LP_CEU_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x44d ) +#define TPCS_SR_PMA_MLN_KR_LP_CEU_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x44e ) +#define TPCS_SR_PMA_MLN_KR_LP_CEU_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x44f ) +#define TPCS_SR_PMA_MLN_KR_LP_CESTS_LANE_0 (TPCS_PMA_MMD_BaseAddress + 4*0x4b0 ) +#define TPCS_SR_PMA_MLN_KR_LP_CESTS_LANE_1 (TPCS_PMA_MMD_BaseAddress + 4*0x4b1 ) +#define TPCS_SR_PMA_MLN_KR_LP_CESTS_LANE_2 (TPCS_PMA_MMD_BaseAddress + 4*0x4b2 ) +#define TPCS_SR_PMA_MLN_KR_LP_CESTS_LANE_3 (TPCS_PMA_MMD_BaseAddress + 4*0x4b3 ) +#define TPCS_SR_PMA_MLN_KR_LD_CEU_LANE0 (TPCS_PMA_MMD_BaseAddress + 4*0x514 ) +#define TPCS_SR_PMA_MLN_KR_LD_CEU_LANE1 (TPCS_PMA_MMD_BaseAddress + 4*0x515 ) +#define TPCS_SR_PMA_MLN_KR_LD_CEU_LANE2 (TPCS_PMA_MMD_BaseAddress + 4*0x516 ) +#define TPCS_SR_PMA_MLN_KR_LD_CEU_LANE3 (TPCS_PMA_MMD_BaseAddress + 4*0x517 ) +#define TPCS_SR_PMA_MLN_KR_LD_CESTS_LANE0 (TPCS_PMA_MMD_BaseAddress + 4*0x578 ) +#define TPCS_SR_PMA_MLN_KR_LD_CESTS_LANE1 (TPCS_PMA_MMD_BaseAddress + 4*0x579 ) +#define TPCS_SR_PMA_MLN_KR_LD_CESTS_LANE2 (TPCS_PMA_MMD_BaseAddress + 4*0x57a ) +#define TPCS_SR_PMA_MLN_KR_LD_CESTS_LANE3 (TPCS_PMA_MMD_BaseAddress + 4*0x57b ) +#define TPCS_SR_PMA_LNK_TRN_PAT (TPCS_PMA_MMD_BaseAddress + 4*0x5aa ) +#define TPCS_SR_PMA_LNK_TRN_PAT_LN1 (TPCS_PMA_MMD_BaseAddress + 4*0x5ab ) +#define TPCS_SR_PMA_LNK_TRN_PAT_LN2 (TPCS_PMA_MMD_BaseAddress + 4*0x5ac ) +#define TPCS_SR_PMA_LNK_TRN_PAT_LN3 (TPCS_PMA_MMD_BaseAddress + 4*0x5ad ) +#define TPCS_SR_PMA_KR_TST_PAT_ABL (TPCS_PMA_MMD_BaseAddress + 4*0x5dc ) +#define TPCS_SR_PMA_KR_TST_PAT_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0x5dd ) +#define TPCS_SR_PMA_KR_SQUARE_WAVE_CTRL (TPCS_PMA_MMD_BaseAddress + 4*0x5e6 ) +#define TPCS_SR_PMA_KR_PRBS_TX_ERR_CNTR_LANE0 (TPCS_PMA_MMD_BaseAddress + 4*0x640 ) +#define TPCS_SR_PMA_KR_PRBS_TX_ERR_CNTR_LANE1 (TPCS_PMA_MMD_BaseAddress + 4*0x641 ) +#define TPCS_SR_PMA_KR_PRBS_TX_ERR_CNTR_LANE2 (TPCS_PMA_MMD_BaseAddress + 4*0x642 ) +#define TPCS_SR_PMA_KR_PRBS_TX_ERR_CNTR_LANE3 (TPCS_PMA_MMD_BaseAddress + 4*0x643 ) +#define TPCS_SR_PMA_KR_PRBS_RX_ERR_CNTR_LANE0 (TPCS_PMA_MMD_BaseAddress + 4*0x6a4 ) +#define TPCS_SR_PMA_KR_PRBS_RX_ERR_CNTR_LANE1 (TPCS_PMA_MMD_BaseAddress + 4*0x6a5 ) +#define TPCS_SR_PMA_KR_PRBS_RX_ERR_CNTR_LANE2 (TPCS_PMA_MMD_BaseAddress + 4*0x6a6 ) +#define TPCS_SR_PMA_KR_PRBS_RX_ERR_CNTR_LANE3 (TPCS_PMA_MMD_BaseAddress + 4*0x6a7 ) +#define TPCS_VR_PMA_DIG_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x8000) +#define TPCS_VR_PMA_KRTR_PRBS_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x8003) +#define TPCS_VR_PMA_KRTR_PRBS_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x8004) +#define TPCS_VR_PMA_KRTR_PRBS_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x8005) +#define TPCS_VR_PMA_KRTR_TIMER_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x8006) +#define TPCS_VR_PMA_KRTR_TIMER_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x8007) +#define TPCS_VR_PMA_DIG_STS (TPCS_PMA_MMD_BaseAddress + 4*0x8010) +#define TPCS_VR_PMA_RX_LSTS (TPCS_PMA_MMD_BaseAddress + 4*0x8020) +#define TPCS_VR_PMA_CWM00 (TPCS_PMA_MMD_BaseAddress + 4*0x80a3) +#define TPCS_VR_PMA_CWM01 (TPCS_PMA_MMD_BaseAddress + 4*0x80a4) +#define TPCS_VR_PMA_CWM02 (TPCS_PMA_MMD_BaseAddress + 4*0x80a5) +#define TPCS_VR_PMA_CWM03 (TPCS_PMA_MMD_BaseAddress + 4*0x80a6) +#define TPCS_VR_PMA_KRTR_TX_EQ_CFF_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x80b0) +#define TPCS_VR_PMA_KRTR_TX_EQ_CFF_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x80b1) +#define TPCS_VR_PMA_KRTR_TX_EQ_CFF_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x80b2) +#define TPCS_VR_PMA_KRTR_TX_EQ_CFF_CTRL3 (TPCS_PMA_MMD_BaseAddress + 4*0x80b3) +#define TPCS_VR_PMA_KRTR_TX_EQ_STS_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x80b4) +#define TPCS_VR_PMA_KRTR_TX_EQ_STS_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x80b5) +#define TPCS_VR_PMA_KRTR_TX_EQ_STS_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x80b6) +#define TPCS_VR_PMA_KRTR_TX_EQ_STS_CTRL3 (TPCS_PMA_MMD_BaseAddress + 4*0x80b7) +#define TPCS_VR_PMA_PHY_TX_EQ_STS0 (TPCS_PMA_MMD_BaseAddress + 4*0x80b8) +#define TPCS_VR_PMA_PHY_TX_EQ_STS1 (TPCS_PMA_MMD_BaseAddress + 4*0x80b9) +#define TPCS_VR_PMA_PHY_TX_EQ_STS2 (TPCS_PMA_MMD_BaseAddress + 4*0x80ba) +#define TPCS_VR_PMA_PHY_TX_EQ_STS3 (TPCS_PMA_MMD_BaseAddress + 4*0x80bb) +#define TPCS_VR_PMA_KRTR_RX_EQ_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x80bc) +#define TPCS_VR_PMA_KRTR_RX_EQ_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x80bd) +#define TPCS_VR_PMA_KRTR_RX_EQ_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x80be) +#define TPCS_VR_PMA_KRTR_RX_EQ_CTRL3 (TPCS_PMA_MMD_BaseAddress + 4*0x80bf) +#define TPCS_VR_PMA_KRTR_RX_EQ_STS_CTRL0 (TPCS_PMA_MMD_BaseAddress + 4*0x80c0) +#define TPCS_VR_PMA_KRTR_RX_EQ_STS_CTRL1 (TPCS_PMA_MMD_BaseAddress + 4*0x80c1) +#define TPCS_VR_PMA_KRTR_RX_EQ_STS_CTRL2 (TPCS_PMA_MMD_BaseAddress + 4*0x80c2) +#define TPCS_VR_PMA_KRTR_RX_EQ_STS_CTRL3 (TPCS_PMA_MMD_BaseAddress + 4*0x80c3) +#define TPCS_VR_PMA_PHY_RX_EQ_CEU0 (TPCS_PMA_MMD_BaseAddress + 4*0x80c4) +#define TPCS_VR_PMA_PHY_RX_EQ_CEU1 (TPCS_PMA_MMD_BaseAddress + 4*0x80c5) +#define TPCS_VR_PMA_PHY_RX_EQ_CEU2 (TPCS_PMA_MMD_BaseAddress + 4*0x80c6) +#define TPCS_VR_PMA_PHY_RX_EQ_CEU3 (TPCS_PMA_MMD_BaseAddress + 4*0x80c7) + + +#define TPCS_SR_PCS_CTRL1 (TPCS_PCS_MMD_BaseAddress + 4*0x0 ) +#define TPCS_SR_PCS_STS1 (TPCS_PCS_MMD_BaseAddress + 4*0x1 ) +#define TPCS_SR_PCS_DEV_ID1 (TPCS_PCS_MMD_BaseAddress + 4*0x2 ) +#define TPCS_SR_PCS_DEV_ID2 (TPCS_PCS_MMD_BaseAddress + 4*0x3 ) +#define TPCS_SR_PCS_SPD_ABL (TPCS_PCS_MMD_BaseAddress + 4*0x4 ) +#define TPCS_SR_PCS_DEV_PKG1 (TPCS_PCS_MMD_BaseAddress + 4*0x5 ) +#define TPCS_SR_PCS_DEV_PKG2 (TPCS_PCS_MMD_BaseAddress + 4*0x6 ) +#define TPCS_SR_PCS_CTRL2 (TPCS_PCS_MMD_BaseAddress + 4*0x7 ) +#define TPCS_SR_PCS_STS2 (TPCS_PCS_MMD_BaseAddress + 4*0x8 ) +#define TPCS_SR_PCS_PKG1 (TPCS_PCS_MMD_BaseAddress + 4*0xe ) +#define TPCS_SR_PCS_PKG2 (TPCS_PCS_MMD_BaseAddress + 4*0xf ) +#define TPCS_SR_PCS_EEE_ABL (TPCS_PCS_MMD_BaseAddress + 4*0x14 ) +#define TPCS_SR_PCS_EEE_WKERR (TPCS_PCS_MMD_BaseAddress + 4*0x16 ) +#define TPCS_SR_PCS_LSTS (TPCS_PCS_MMD_BaseAddress + 4*0x18 ) +#define TPCS_SR_PCS_BASER_STS1 (TPCS_PCS_MMD_BaseAddress + 4*0x20 ) +#define TPCS_SR_PCS_BASER_STS2 (TPCS_PCS_MMD_BaseAddress + 4*0x21 ) +#define TPCS_SR_PCS_TP_A0 (TPCS_PCS_MMD_BaseAddress + 4*0x22 ) +#define TPCS_SR_PCS_TP_A1 (TPCS_PCS_MMD_BaseAddress + 4*0x23 ) +#define TPCS_SR_PCS_TP_A2 (TPCS_PCS_MMD_BaseAddress + 4*0x24 ) +#define TPCS_SR_PCS_TP_A3 (TPCS_PCS_MMD_BaseAddress + 4*0x25 ) +#define TPCS_SR_PCS_TP_B0 (TPCS_PCS_MMD_BaseAddress + 4*0x26 ) +#define TPCS_SR_PCS_TP_B1 (TPCS_PCS_MMD_BaseAddress + 4*0x27 ) +#define TPCS_SR_PCS_TP_B2 (TPCS_PCS_MMD_BaseAddress + 4*0x28 ) +#define TPCS_SR_PCS_TP_B3 (TPCS_PCS_MMD_BaseAddress + 4*0x29 ) +#define TPCS_SR_PCS_TP_CTRL (TPCS_PCS_MMD_BaseAddress + 4*0x2a ) +#define TPCS_SR_PCS_TP_ERRCTR (TPCS_PCS_MMD_BaseAddress + 4*0x2b ) +#define TPCS_SR_PCS_BER_HI_ORDER_CNT (TPCS_PCS_MMD_BaseAddress + 4*0x2c ) +#define TPCS_SR_PCS_ERR_BLK_HI_ORDER_CNT (TPCS_PCS_MMD_BaseAddress + 4*0x2d ) +#define TPCS_SR_PCS_MLN_ALIGN_STS1 (TPCS_PCS_MMD_BaseAddress + 4*0x32 ) +#define TPCS_SR_PCS_MLN_ALIGN_STS2 (TPCS_PCS_MMD_BaseAddress + 4*0x33 ) +#define TPCS_SR_PCS_MLN_ALIGN_STS3 (TPCS_PCS_MMD_BaseAddress + 4*0x34 ) +#define TPCS_SR_PCS_MLN_ALIGN_STS4 (TPCS_PCS_MMD_BaseAddress + 4*0x35 ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE0 (TPCS_PCS_MMD_BaseAddress + 4*0xc8 ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE1 (TPCS_PCS_MMD_BaseAddress + 4*0xc9 ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE2 (TPCS_PCS_MMD_BaseAddress + 4*0xca ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE3 (TPCS_PCS_MMD_BaseAddress + 4*0xcb ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE4 (TPCS_PCS_MMD_BaseAddress + 4*0xcc ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE5 (TPCS_PCS_MMD_BaseAddress + 4*0xcd ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE6 (TPCS_PCS_MMD_BaseAddress + 4*0xce ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE7 (TPCS_PCS_MMD_BaseAddress + 4*0xcf ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE8 (TPCS_PCS_MMD_BaseAddress + 4*0xd0 ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE9 (TPCS_PCS_MMD_BaseAddress + 4*0xd1 ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE10 (TPCS_PCS_MMD_BaseAddress + 4*0xd2 ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE11 (TPCS_PCS_MMD_BaseAddress + 4*0xd3 ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE12 (TPCS_PCS_MMD_BaseAddress + 4*0xd4 ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE13 (TPCS_PCS_MMD_BaseAddress + 4*0xd5 ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE14 (TPCS_PCS_MMD_BaseAddress + 4*0xd6 ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE15 (TPCS_PCS_MMD_BaseAddress + 4*0xd7 ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE16 (TPCS_PCS_MMD_BaseAddress + 4*0xd8 ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE17 (TPCS_PCS_MMD_BaseAddress + 4*0xd9 ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE18 (TPCS_PCS_MMD_BaseAddress + 4*0xda ) +#define TPCS_SR_PCS_BIP_ERR_CNTR_LANE19 (TPCS_PCS_MMD_BaseAddress + 4*0xdb ) +#define TPCS_SR_PCS_LANE0_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x190 ) +#define TPCS_SR_PCS_LANE1_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x191 ) +#define TPCS_SR_PCS_LANE2_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x192 ) +#define TPCS_SR_PCS_LANE3_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x193 ) +#define TPCS_SR_PCS_LANE4_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x194 ) +#define TPCS_SR_PCS_LANE5_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x195 ) +#define TPCS_SR_PCS_LANE6_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x196 ) +#define TPCS_SR_PCS_LANE7_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x197 ) +#define TPCS_SR_PCS_LANE8_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x198 ) +#define TPCS_SR_PCS_LANE9_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x199 ) +#define TPCS_SR_PCS_LANE10_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19a ) +#define TPCS_SR_PCS_LANE11_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19b ) +#define TPCS_SR_PCS_LANE12_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19c ) +#define TPCS_SR_PCS_LANE13_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19d ) +#define TPCS_SR_PCS_LANE14_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19e ) +#define TPCS_SR_PCS_LANE15_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x19f ) +#define TPCS_SR_PCS_LANE16_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x1a0 ) +#define TPCS_SR_PCS_LANE17_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x1a1 ) +#define TPCS_SR_PCS_LANE18_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x1a2 ) +#define TPCS_SR_PCS_LANE19_MAPPING (TPCS_PCS_MMD_BaseAddress + 4*0x1a3 ) +#define TPCS_VR_PCS_DIG_CTRL1 (TPCS_PCS_MMD_BaseAddress + 4*0x8000) +#define TPCS_VR_PCS_DIG_CTRL2 (TPCS_PCS_MMD_BaseAddress + 4*0x8001) +#define TPCS_VR_PCS_DIG_CTRL3 (TPCS_PCS_MMD_BaseAddress + 4*0x8003) +#define TPCS_VR_PCS_DEBUG_CTRL (TPCS_PCS_MMD_BaseAddress + 4*0x8005) +#define TPCS_VR_PCS_EEE_MCTRL (TPCS_PCS_MMD_BaseAddress + 4*0x8006) +#define TPCS_VR_PCS_KR_CTRL (TPCS_PCS_MMD_BaseAddress + 4*0x8007) +#define TPCS_VR_PCS_EEE_TXTIMER (TPCS_PCS_MMD_BaseAddress + 4*0x8008) +#define TPCS_VR_PCS_EEE_RXTIMER (TPCS_PCS_MMD_BaseAddress + 4*0x8009) +#define TPCS_VR_PCS_EEE_MISC_TIMER (TPCS_PCS_MMD_BaseAddress + 4*0x800a) +#define TPCS_VR_PCS_DIG_STS (TPCS_PCS_MMD_BaseAddress + 4*0x8010) +#define TPCS_VR_PCS_AM_CNT (TPCS_PCS_MMD_BaseAddress + 4*0x8018) +#define TPCS_VR_PCS_SKW_OUT_OF_RANGE (TPCS_PCS_MMD_BaseAddress + 4*0x8019) +#define TPCS_VR_PCS_ALT_AM_CNT (TPCS_PCS_MMD_BaseAddress + 4*0x801a) +#define TPCS_VR_PCS_MISC_STS (TPCS_PCS_MMD_BaseAddress + 4*0x8020) + + +#define TPCS_SR_AN_CTRL (TPCS_AN_MMD_BaseAddress + 4*0x0 ) +#define TPCS_SR_AN_STS (TPCS_AN_MMD_BaseAddress + 4*0x1 ) +#define TPCS_SR_AN_DEV_ID1 (TPCS_AN_MMD_BaseAddress + 4*0x2 ) +#define TPCS_SR_AN_DEV_ID2 (TPCS_AN_MMD_BaseAddress + 4*0x3 ) +#define TPCS_SR_AN_DEV_PKG1 (TPCS_AN_MMD_BaseAddress + 4*0x5 ) +#define TPCS_SR_AN_DEV_PKG2 (TPCS_AN_MMD_BaseAddress + 4*0x6 ) +#define TPCS_SR_AN_PKG1 (TPCS_AN_MMD_BaseAddress + 4*0xe ) +#define TPCS_SR_AN_PKG2 (TPCS_AN_MMD_BaseAddress + 4*0xf ) +#define TPCS_SR_AN_ADV1 (TPCS_AN_MMD_BaseAddress + 4*0x10 ) +#define TPCS_SR_AN_ADV2 (TPCS_AN_MMD_BaseAddress + 4*0x11 ) +#define TPCS_SR_AN_ADV3 (TPCS_AN_MMD_BaseAddress + 4*0x12 ) +#define TPCS_SR_AN_LP_ABL1 (TPCS_AN_MMD_BaseAddress + 4*0x13 ) +#define TPCS_SR_AN_LP_ABL2 (TPCS_AN_MMD_BaseAddress + 4*0x14 ) +#define TPCS_SR_AN_LP_ABL3 (TPCS_AN_MMD_BaseAddress + 4*0x15 ) +#define TPCS_SR_AN_XNP_TX1 (TPCS_AN_MMD_BaseAddress + 4*0x16 ) +#define TPCS_SR_AN_XNP_TX2 (TPCS_AN_MMD_BaseAddress + 4*0x17 ) +#define TPCS_SR_AN_XNP_TX3 (TPCS_AN_MMD_BaseAddress + 4*0x18 ) +#define TPCS_SR_AN_LP_XNP_ABL1 (TPCS_AN_MMD_BaseAddress + 4*0x19 ) +#define TPCS_SR_AN_LP_XNP_ABL2 (TPCS_AN_MMD_BaseAddress + 4*0x1a ) +#define TPCS_SR_AN_LP_XNP_ABL3 (TPCS_AN_MMD_BaseAddress + 4*0x1b ) +#define TPCS_SR_AN_COMP_STS (TPCS_AN_MMD_BaseAddress + 4*0x30 ) +#define TPCS_SR_AN_EEE_ABL (TPCS_AN_MMD_BaseAddress + 4*0x3c ) +#define TPCS_SR_AN_EEE_LP_ABL (TPCS_AN_MMD_BaseAddress + 4*0x3d ) +#define TPCS_VR_AN_VR_DIG_CTRL (TPCS_AN_MMD_BaseAddress + 4*0x8000 ) +#define TPCS_VR_AN_INTR_MSK (TPCS_AN_MMD_BaseAddress + 4*0x8001 ) +#define TPCS_VR_AN_INTR (TPCS_AN_MMD_BaseAddress + 4*0x8002 ) +#define TPCS_VR_AN_MODE_CTRL (TPCS_AN_MMD_BaseAddress + 4*0x8003 ) +#define TPCS_VR_AN_TIMER_CTRL0 (TPCS_AN_MMD_BaseAddress + 4*0x8004 ) +#define TPCS_VR_AN_TIMER_CTRL1 (TPCS_AN_MMD_BaseAddress + 4*0x8005 ) + +#define TPCS_SR_VSMMD_PMA_ID1 (TPCS_VS_MMD1_BaseAddress + 4*0x0 ) +#define TPCS_SR_VSMMD_PMA_ID2 (TPCS_VS_MMD1_BaseAddress + 4*0x1 ) +#define TPCS_SR_VSMMD_DEV_ID1 (TPCS_VS_MMD1_BaseAddress + 4*0x2 ) +#define TPCS_SR_VSMMD_DEV_ID2 (TPCS_VS_MMD1_BaseAddress + 4*0x3 ) +#define TPCS_SR_VSMMD_PCS_ID1 (TPCS_VS_MMD1_BaseAddress + 4*0x4 ) +#define TPCS_SR_VSMMD_PCS_ID2 (TPCS_VS_MMD1_BaseAddress + 4*0x5 ) +#define TPCS_SR_VSMMD_AN_ID1 (TPCS_VS_MMD1_BaseAddress + 4*0x6 ) +#define TPCS_SR_VSMMD_AN_ID2 (TPCS_VS_MMD1_BaseAddress + 4*0x7 ) +#define TPCS_SR_VSMMD_STS (TPCS_VS_MMD1_BaseAddress + 4*0x8 ) +#define TPCS_SR_VSMMD_CTRL (TPCS_VS_MMD1_BaseAddress + 4*0x9 ) +#define TPCS_SR_VSMMD_PKGID1 (TPCS_VS_MMD1_BaseAddress + 4*0xe ) +#define TPCS_SR_VSMMD_PKGID2 (TPCS_VS_MMD1_BaseAddress + 4*0xf ) + +#endif diff --git a/driver/rfic/ucp/base/inc/jesd204.h b/driver/rfic/ucp/base/inc/jesd204.h new file mode 100644 index 0000000..506a8bc --- /dev/null +++ b/driver/rfic/ucp/base/inc/jesd204.h @@ -0,0 +1,2758 @@ +//******************** (C) COPYRIGHT 2020 SmartLogic******************************* +// FileName : jesd204.h +// Author : liugeng, geng.liu@smartlogictech.com +// Date First Issued : 2022-06-01 06:16:38 PM +// Last Modified : 2022-06-02 10:12:03 AM +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + + +//******************** (C) COPYRIGHT 2020 SmartLogic******************************* +#ifndef __JESD204_H__ +#define __JESD204_H__ + +#define JS_CSU_BASE 0x05F60000 +#define JS_COMC_BASE 0x06000000 +#define JS_COMC_204B_RX0_BASE JS_COMC_BASE + 0x0000 +#define JS_COMC_204B_RX1_BASE JS_COMC_BASE + 0x1000 +#define JS_COMC_204B_TX_BASE JS_COMC_BASE + 0x2000 +#define JS_COMC_204C_RX0_BASE JS_COMC_BASE + 0x3000 +#define JS_COMC_204C_RX1_BASE JS_COMC_BASE + 0x4000 +#define JS_COMC_204C_TX_BASE JS_COMC_BASE + 0x5000 +#define JS_RX0_TMR_BASE JS_COMC_BASE + 0x6000 +#define JS_RX1_TMR_BASE JS_COMC_BASE + 0x7000 +#define JS_TX0_TMR_BASE JS_COMC_BASE + 0x8000 +#define JS_TX1_TMR_BASE JS_COMC_BASE + 0x9000 +#define JS_204B_RX0_SUBCTRL_BASE 0x06080000 +#define JS_204C_RX0_SUBCTRL_BASE 0x06090000 +#define JS_204B_RX1_SUBCTRL_BASE 0x060A0000 +#define JS_204C_RX1_SUBCTRL_BASE 0x060B0000 +#define JS_204B_TX_SUBCTRL_BASE 0x060C0000 +#define JS_204C_TX_SUBCTRL_BASE 0x060D0000 + +#define JS_COMC_204B_RX0_BANK_ID (JS_COMC_204B_RX0_BASE + 0x000) +#define JS_COMC_204B_RX0_DID (JS_COMC_204B_RX0_BASE + 0x004) +#define JS_COMC_204B_RX0_LID (JS_COMC_204B_RX0_BASE + 0x008) +#define JS_COMC_204B_RX0_LID2 (JS_COMC_204B_RX0_BASE + 0x00C) +#define JS_COMC_204B_RX0_LID3 (JS_COMC_204B_RX0_BASE + 0x010) +#define JS_COMC_204B_RX0_LID4 (JS_COMC_204B_RX0_BASE + 0x014) +#define JS_COMC_204B_RX0_DATAPATH_INTERCONNECT (JS_COMC_204B_RX0_BASE + 0x018) +#define JS_COMC_204B_RX0_SUBCLASS (JS_COMC_204B_RX0_BASE + 0x01C) +#define JS_COMC_204B_RX0_CF (JS_COMC_204B_RX0_BASE + 0x020) +#define JS_COMC_204B_RX0_CS (JS_COMC_204B_RX0_BASE + 0x024) +#define JS_COMC_204B_RX0_F (JS_COMC_204B_RX0_BASE + 0x028) +#define JS_COMC_204B_RX0_K (JS_COMC_204B_RX0_BASE + 0x02C) +#define JS_COMC_204B_RX0_L (JS_COMC_204B_RX0_BASE + 0x030) +#define JS_COMC_204B_RX0_N (JS_COMC_204B_RX0_BASE + 0x034) +#define JS_COMC_204B_RX0_M (JS_COMC_204B_RX0_BASE + 0x038) +#define JS_COMC_204B_RX0_NTOTAL (JS_COMC_204B_RX0_BASE + 0x03C) +#define JS_COMC_204B_RX0_S (JS_COMC_204B_RX0_BASE + 0x040) +#define JS_COMC_204B_RX0_HD (JS_COMC_204B_RX0_BASE + 0x044) +#define JS_COMC_204B_RX0_SCR (JS_COMC_204B_RX0_BASE + 0x048) +#define JS_COMC_204B_RX0_ENABLEMODULE (JS_COMC_204B_RX0_BASE + 0x050) +#define JS_COMC_204B_RX0_ENABLELINKTEST (JS_COMC_204B_RX0_BASE + 0x054) +#define JS_COMC_204B_RX0_GEN_SYSREF (JS_COMC_204B_RX0_BASE + 0x3E4) +#define JS_COMC_204B_RX0_FEC_EN (JS_COMC_204B_RX0_BASE + 0x2C4) +#define JS_COMC_204B_RX0_CRC3_EN (JS_COMC_204B_RX0_BASE + 0x2C8) +#define JS_COMC_204B_RX0_CRC12_EN (JS_COMC_204B_RX0_BASE + 0x2CC) +#define JS_COMC_204B_RX0_SOFT_SYNC (JS_COMC_204B_RX0_BASE + 0x2D0) +#define JS_COMC_204B_RX0_E (JS_COMC_204B_RX0_BASE + 0x2D4) +#define JS_COMC_204B_RX0_BIT_ORDER (JS_COMC_204B_RX0_BASE + 0x2D8) +#define JS_COMC_204B_RX0_TL_TEST_MODE (JS_COMC_204B_RX0_BASE + 0x2DC) +#define JS_COMC_204B_RX0_RESYNC_COUNT_STATUS (JS_COMC_204B_RX0_BASE + 0x2FC) +#define JS_COMC_204B_RX0_S_ON_IF_REG (JS_COMC_204B_RX0_BASE + 0x368) +//#define JS_COMC_204B_RX0_MERGE_CF_GROUP (JS_COMC_204B_RX0_BASE + 0x36C) +#define JS_COMC_204B_RX0_CMD_EN (JS_COMC_204B_RX0_BASE + 0x370) +#define JS_COMC_204B_RX0_SYSREF_COUNTER_STATUS (JS_COMC_204B_RX0_BASE + 0x374) +#define JS_COMC_204B_RX0_LINKCONFIGURATIONERROR (JS_COMC_204B_RX0_BASE + 0x04C) +#define JS_COMC_204B_RX0_LINKTEST_0_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x058) +#define JS_COMC_204B_RX0_LINKTEST_1_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x05C) +#define JS_COMC_204B_RX0_LINKTEST_2_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x060) +#define JS_COMC_204B_RX0_LINKTEST_3_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x064) +#define JS_COMC_204B_RX0_LINKTEST_4_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x068) +#define JS_COMC_204B_RX0_LINKTEST_5_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x06C) +#define JS_COMC_204B_RX0_LINKTEST_6_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x070) +#define JS_COMC_204B_RX0_LINKTEST_7_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x074) +#define JS_COMC_204B_RX0_LINKTEST_8_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x078) +#define JS_COMC_204B_RX0_LINKTEST_9_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x07C) +#define JS_COMC_204B_RX0_LINKTEST_10_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x080) +#define JS_COMC_204B_RX0_LINKTEST_11_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x084) +#define JS_COMC_204B_RX0_LINKTEST_12_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x088) +#define JS_COMC_204B_RX0_LINKTEST_13_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x08C) +#define JS_COMC_204B_RX0_LINKTEST_14_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x090) +#define JS_COMC_204B_RX0_LINKTEST_15_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x094) +#define JS_COMC_204B_RX0_LINKTEST_16_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x098) +#define JS_COMC_204B_RX0_LINKTEST_17_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x09C) +#define JS_COMC_204B_RX0_LINKTEST_18_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x0A0) +#define JS_COMC_204B_RX0_LINKTEST_19_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x0A4) +#define JS_COMC_204B_RX0_LINKTEST_20_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x0A8) +#define JS_COMC_204B_RX0_LINKTEST_21_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x0AC) +#define JS_COMC_204B_RX0_LINKTEST_22_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x0B0) +#define JS_COMC_204B_RX0_LINKTEST_23_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x0B4) +#define JS_COMC_204B_RX0_LINKTEST_0_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x0C0) +#define JS_COMC_204B_RX0_LINKTEST_1_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x0C4) +#define JS_COMC_204B_RX0_LINKTEST_2_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x0C8) +#define JS_COMC_204B_RX0_LINKTEST_3_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x0CC) +#define JS_COMC_204B_RX0_LINKTEST_4_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x0D0) +#define JS_COMC_204B_RX0_LINKTEST_5_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x0D4) +#define JS_COMC_204B_RX0_LINKTEST_6_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x0D8) +#define JS_COMC_204B_RX0_LINKTEST_7_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x0DC) +#define JS_COMC_204B_RX0_LINKTEST_8_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x0E0) +#define JS_COMC_204B_RX0_LINKTEST_9_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x0E4) +#define JS_COMC_204B_RX0_LINKTEST_10_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x0E8) +#define JS_COMC_204B_RX0_LINKTEST_11_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x0EC) +#define JS_COMC_204B_RX0_LINKTEST_12_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x0F0) +#define JS_COMC_204B_RX0_LINKTEST_13_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x0F4) +#define JS_COMC_204B_RX0_LINKTEST_14_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x0F8) +#define JS_COMC_204B_RX0_LINKTEST_15_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x0FC) +#define JS_COMC_204B_RX0_LINKTEST_16_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x100) +#define JS_COMC_204B_RX0_LINKTEST_17_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x104) +#define JS_COMC_204B_RX0_LINKTEST_18_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x108) +#define JS_COMC_204B_RX0_LINKTEST_19_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x10C) +#define JS_COMC_204B_RX0_LINKTEST_20_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x110) +#define JS_COMC_204B_RX0_LINKTEST_21_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x114) +#define JS_COMC_204B_RX0_LINKTEST_22_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x118) +#define JS_COMC_204B_RX0_LINKTEST_23_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x11C) +#define JS_COMC_204B_RX0_FEATURE_DISABLE (JS_COMC_204B_RX0_BASE + 0x120) +#define JS_COMC_204B_RX0_CORE_INTERRUPT_MASK (JS_COMC_204B_RX0_BASE + 0x124) +#define JS_COMC_204B_RX0_CORE_INTERRUPT_STATUS (JS_COMC_204B_RX0_BASE + 0x128) +#define JS_COMC_204B_RX0_ILAS_DETAILS (JS_COMC_204B_RX0_BASE + 0x12C) +#define JS_COMC_204B_RX0_ERR_INJ_REQ (JS_COMC_204B_RX0_BASE + 0x130) +#define JS_COMC_204B_RX0_CLK_RATIO (JS_COMC_204B_RX0_BASE + 0x13C) +#define JS_COMC_204B_RX0_PRBS_TEST_0_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x140) +#define JS_COMC_204B_RX0_PRBS_TEST_1_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x144) +#define JS_COMC_204B_RX0_PRBS_TEST_2_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x148) +#define JS_COMC_204B_RX0_PRBS_TEST_3_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x14C) +#define JS_COMC_204B_RX0_PRBS_TEST_4_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x150) +#define JS_COMC_204B_RX0_PRBS_TEST_5_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x154) +#define JS_COMC_204B_RX0_PRBS_TEST_6_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x158) +#define JS_COMC_204B_RX0_PRBS_TEST_7_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x15C) +#define JS_COMC_204B_RX0_PRBS_TEST_8_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x160) +#define JS_COMC_204B_RX0_PRBS_TEST_9_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x164) +#define JS_COMC_204B_RX0_PRBS_TEST_10_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x168) +#define JS_COMC_204B_RX0_PRBS_TEST_11_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x16C) +#define JS_COMC_204B_RX0_PRBS_TEST_12_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x170) +#define JS_COMC_204B_RX0_PRBS_TEST_13_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x174) +#define JS_COMC_204B_RX0_PRBS_TEST_14_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x178) +#define JS_COMC_204B_RX0_PRBS_TEST_15_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x17C) +#define JS_COMC_204B_RX0_PRBS_TEST_16_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x180) +#define JS_COMC_204B_RX0_PRBS_TEST_17_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x184) +#define JS_COMC_204B_RX0_PRBS_TEST_18_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x188) +#define JS_COMC_204B_RX0_PRBS_TEST_19_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x18C) +#define JS_COMC_204B_RX0_PRBS_TEST_20_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x190) +#define JS_COMC_204B_RX0_PRBS_TEST_21_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x194) +#define JS_COMC_204B_RX0_PRBS_TEST_22_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x198) +#define JS_COMC_204B_RX0_PRBS_TEST_23_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x19C) +#define JS_COMC_204B_RX0_JTSPAT_TEST_0_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1A0) +#define JS_COMC_204B_RX0_JTSPAT_TEST_1_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1A4) +#define JS_COMC_204B_RX0_JTSPAT_TEST_2_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1A8) +#define JS_COMC_204B_RX0_JTSPAT_TEST_3_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1AC) +#define JS_COMC_204B_RX0_JTSPAT_TEST_4_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1B0) +#define JS_COMC_204B_RX0_JTSPAT_TEST_5_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1B4) +#define JS_COMC_204B_RX0_JTSPAT_TEST_6_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1B8) +#define JS_COMC_204B_RX0_JTSPAT_TEST_7_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1BC) +#define JS_COMC_204B_RX0_JTSPAT_TEST_8_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1C0) +#define JS_COMC_204B_RX0_JTSPAT_TEST_9_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1C4) +#define JS_COMC_204B_RX0_JTSPAT_TEST_10_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1C8) +#define JS_COMC_204B_RX0_JTSPAT_TEST_11_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1CC) +#define JS_COMC_204B_RX0_JTSPAT_TEST_12_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1D0) +#define JS_COMC_204B_RX0_JTSPAT_TEST_13_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1D4) +#define JS_COMC_204B_RX0_JTSPAT_TEST_14_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1D8) +#define JS_COMC_204B_RX0_JTSPAT_TEST_15_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1DC) +#define JS_COMC_204B_RX0_JTSPAT_TEST_16_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1E0) +#define JS_COMC_204B_RX0_JTSPAT_TEST_17_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1E4) +#define JS_COMC_204B_RX0_JTSPAT_TEST_18_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1E8) +#define JS_COMC_204B_RX0_JTSPAT_TEST_19_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1EC) +#define JS_COMC_204B_RX0_JTSPAT_TEST_20_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1F0) +#define JS_COMC_204B_RX0_JTSPAT_TEST_21_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1F4) +#define JS_COMC_204B_RX0_JTSPAT_TEST_22_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1F8) +#define JS_COMC_204B_RX0_JTSPAT_TEST_23_ERRORCOUNTER (JS_COMC_204B_RX0_BASE + 0x1FC) +#define JS_COMC_204B_RX0_PRBS_TEST_0_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x200) +#define JS_COMC_204B_RX0_PRBS_TEST_1_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x204) +#define JS_COMC_204B_RX0_PRBS_TEST_2_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x208) +#define JS_COMC_204B_RX0_PRBS_TEST_3_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x20C) +#define JS_COMC_204B_RX0_PRBS_TEST_4_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x210) +#define JS_COMC_204B_RX0_PRBS_TEST_5_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x214) +#define JS_COMC_204B_RX0_PRBS_TEST_6_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x218) +#define JS_COMC_204B_RX0_PRBS_TEST_7_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x21C) +#define JS_COMC_204B_RX0_PRBS_TEST_8_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x220) +#define JS_COMC_204B_RX0_PRBS_TEST_9_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x224) +#define JS_COMC_204B_RX0_PRBS_TEST_10_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x228) +#define JS_COMC_204B_RX0_PRBS_TEST_11_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x22C) +#define JS_COMC_204B_RX0_PRBS_TEST_12_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x230) +#define JS_COMC_204B_RX0_PRBS_TEST_13_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x234) +#define JS_COMC_204B_RX0_PRBS_TEST_14_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x238) +#define JS_COMC_204B_RX0_PRBS_TEST_15_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x23C) +#define JS_COMC_204B_RX0_PRBS_TEST_16_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x240) +#define JS_COMC_204B_RX0_PRBS_TEST_17_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x244) +#define JS_COMC_204B_RX0_PRBS_TEST_18_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x248) +#define JS_COMC_204B_RX0_PRBS_TEST_19_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x24C) +#define JS_COMC_204B_RX0_PRBS_TEST_20_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x250) +#define JS_COMC_204B_RX0_PRBS_TEST_21_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x254) +#define JS_COMC_204B_RX0_PRBS_TEST_22_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x258) +#define JS_COMC_204B_RX0_PRBS_TEST_23_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x25C) +#define JS_COMC_204B_RX0_JTSPAT_TEST_0_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x260) +#define JS_COMC_204B_RX0_JTSPAT_TEST_1_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x264) +#define JS_COMC_204B_RX0_JTSPAT_TEST_2_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x268) +#define JS_COMC_204B_RX0_JTSPAT_TEST_3_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x26C) +#define JS_COMC_204B_RX0_JTSPAT_TEST_4_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x270) +#define JS_COMC_204B_RX0_JTSPAT_TEST_5_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x274) +#define JS_COMC_204B_RX0_JTSPAT_TEST_6_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x278) +#define JS_COMC_204B_RX0_JTSPAT_TEST_7_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x27C) +#define JS_COMC_204B_RX0_JTSPAT_TEST_8_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x280) +#define JS_COMC_204B_RX0_JTSPAT_TEST_9_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x284) +#define JS_COMC_204B_RX0_JTSPAT_TEST_10_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x288) +#define JS_COMC_204B_RX0_JTSPAT_TEST_11_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x28C) +#define JS_COMC_204B_RX0_JTSPAT_TEST_12_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x290) +#define JS_COMC_204B_RX0_JTSPAT_TEST_13_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x294) +#define JS_COMC_204B_RX0_JTSPAT_TEST_14_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x298) +#define JS_COMC_204B_RX0_JTSPAT_TEST_15_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x29C) +#define JS_COMC_204B_RX0_JTSPAT_TEST_16_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x2A0) +#define JS_COMC_204B_RX0_JTSPAT_TEST_17_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x2A4) +#define JS_COMC_204B_RX0_JTSPAT_TEST_18_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x2A8) +#define JS_COMC_204B_RX0_JTSPAT_TEST_19_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x2AC) +#define JS_COMC_204B_RX0_JTSPAT_TEST_20_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x2B0) +#define JS_COMC_204B_RX0_JTSPAT_TEST_21_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x2B4) +#define JS_COMC_204B_RX0_JTSPAT_TEST_22_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x2B8) +#define JS_COMC_204B_RX0_JTSPAT_TEST_23_RECEIVECOUNTER (JS_COMC_204B_RX0_BASE + 0x2BC) +#define JS_COMC_204B_RX0_LMFC_LEMC_DELAY (JS_COMC_204B_RX0_BASE + 0x2E0) +#define JS_COMC_204B_RX0_SYSREF_CONFIG (JS_COMC_204B_RX0_BASE + 0x2E4) +#define JS_COMC_204B_RX0_MAST_INST (JS_COMC_204B_RX0_BASE + 0x2E8) +#define JS_COMC_204B_RX0_SH_LOCK_STATUS (JS_COMC_204B_RX0_BASE + 0x2EC) +#define JS_COMC_204B_RX0_SH_LOCK_LOSS_STATUS (JS_COMC_204B_RX0_BASE + 0x2F0) +#define JS_COMC_204B_RX0_EMB_LOCK_STATUS (JS_COMC_204B_RX0_BASE + 0x2F4) +#define JS_COMC_204B_RX0_EMB_LOCK_LOSS_STATUS (JS_COMC_204B_RX0_BASE + 0x2F8) +#define JS_COMC_204B_RX0_LEMC_BOUNDARY_PHASE (JS_COMC_204B_RX0_BASE + 0x3D8) +#define JS_COMC_204B_RX0_RBD_LENGTH_OCTETS (JS_COMC_204B_RX0_BASE + 0x3DC) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE0 (JS_COMC_204B_RX0_BASE + 0x300) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE1 (JS_COMC_204B_RX0_BASE + 0x304) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE2 (JS_COMC_204B_RX0_BASE + 0x308) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE3 (JS_COMC_204B_RX0_BASE + 0x30C) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE4 (JS_COMC_204B_RX0_BASE + 0x310) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE5 (JS_COMC_204B_RX0_BASE + 0x314) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE6 (JS_COMC_204B_RX0_BASE + 0x318) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE7 (JS_COMC_204B_RX0_BASE + 0x31C) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE8 (JS_COMC_204B_RX0_BASE + 0x320) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE9 (JS_COMC_204B_RX0_BASE + 0x324) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE10 (JS_COMC_204B_RX0_BASE + 0x328) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE11 (JS_COMC_204B_RX0_BASE + 0x32C) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE12 (JS_COMC_204B_RX0_BASE + 0x330) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE13 (JS_COMC_204B_RX0_BASE + 0x334) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE14 (JS_COMC_204B_RX0_BASE + 0x338) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE15 (JS_COMC_204B_RX0_BASE + 0x33C) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE16 (JS_COMC_204B_RX0_BASE + 0x340) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE17 (JS_COMC_204B_RX0_BASE + 0x344) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE18 (JS_COMC_204B_RX0_BASE + 0x348) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE19 (JS_COMC_204B_RX0_BASE + 0x34C) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE20 (JS_COMC_204B_RX0_BASE + 0x350) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE21 (JS_COMC_204B_RX0_BASE + 0x354) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE22 (JS_COMC_204B_RX0_BASE + 0x358) +#define JS_COMC_204B_RX0_ERROR_REPORT_LANE23 (JS_COMC_204B_RX0_BASE + 0x35C) +#define JS_COMC_204B_RX0_TRESH_EMB_ERR (JS_COMC_204B_RX0_BASE + 0x360) +#define JS_COMC_204B_RX0_TRESH_SH_ERR (JS_COMC_204B_RX0_BASE + 0x364) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE0 (JS_COMC_204B_RX0_BASE + 0x378) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE1 (JS_COMC_204B_RX0_BASE + 0x37C) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE2 (JS_COMC_204B_RX0_BASE + 0x380) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE3 (JS_COMC_204B_RX0_BASE + 0x384) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE4 (JS_COMC_204B_RX0_BASE + 0x388) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE5 (JS_COMC_204B_RX0_BASE + 0x38C) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE6 (JS_COMC_204B_RX0_BASE + 0x390) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE7 (JS_COMC_204B_RX0_BASE + 0x394) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE8 (JS_COMC_204B_RX0_BASE + 0x398) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE9 (JS_COMC_204B_RX0_BASE + 0x39C) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE10 (JS_COMC_204B_RX0_BASE + 0x3A0) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE11 (JS_COMC_204B_RX0_BASE + 0x3A4) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE12 (JS_COMC_204B_RX0_BASE + 0x3A8) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE13 (JS_COMC_204B_RX0_BASE + 0x3AC) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE14 (JS_COMC_204B_RX0_BASE + 0x3B0) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE15 (JS_COMC_204B_RX0_BASE + 0x3B4) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE16 (JS_COMC_204B_RX0_BASE + 0x3B8) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE17 (JS_COMC_204B_RX0_BASE + 0x3BC) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE18 (JS_COMC_204B_RX0_BASE + 0x3C0) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE19 (JS_COMC_204B_RX0_BASE + 0x3C4) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE20 (JS_COMC_204B_RX0_BASE + 0x3C8) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE21 (JS_COMC_204B_RX0_BASE + 0x3CC) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE22 (JS_COMC_204B_RX0_BASE + 0x3D0) +#define JS_COMC_204B_RX0_ICOUNTER_REPORT_LANE23 (JS_COMC_204B_RX0_BASE + 0x3D4) + +#define JS_COMC_204B_RX1_BANK_ID (JS_COMC_204B_RX1_BASE + 0x000) +#define JS_COMC_204B_RX1_DID (JS_COMC_204B_RX1_BASE + 0x004) +#define JS_COMC_204B_RX1_LID (JS_COMC_204B_RX1_BASE + 0x008) +#define JS_COMC_204B_RX1_LID2 (JS_COMC_204B_RX1_BASE + 0x00C) +#define JS_COMC_204B_RX1_LID3 (JS_COMC_204B_RX1_BASE + 0x010) +#define JS_COMC_204B_RX1_LID4 (JS_COMC_204B_RX1_BASE + 0x014) +#define JS_COMC_204B_RX1_DATAPATH_INTERCONNECT (JS_COMC_204B_RX1_BASE + 0x018) +#define JS_COMC_204B_RX1_SUBCLASS (JS_COMC_204B_RX1_BASE + 0x01C) +#define JS_COMC_204B_RX1_CF (JS_COMC_204B_RX1_BASE + 0x020) +#define JS_COMC_204B_RX1_CS (JS_COMC_204B_RX1_BASE + 0x024) +#define JS_COMC_204B_RX1_F (JS_COMC_204B_RX1_BASE + 0x028) +#define JS_COMC_204B_RX1_K (JS_COMC_204B_RX1_BASE + 0x02C) +#define JS_COMC_204B_RX1_L (JS_COMC_204B_RX1_BASE + 0x030) +#define JS_COMC_204B_RX1_N (JS_COMC_204B_RX1_BASE + 0x034) +#define JS_COMC_204B_RX1_M (JS_COMC_204B_RX1_BASE + 0x038) +#define JS_COMC_204B_RX1_NTOTAL (JS_COMC_204B_RX1_BASE + 0x03C) +#define JS_COMC_204B_RX1_S (JS_COMC_204B_RX1_BASE + 0x040) +#define JS_COMC_204B_RX1_HD (JS_COMC_204B_RX1_BASE + 0x044) +#define JS_COMC_204B_RX1_SCR (JS_COMC_204B_RX1_BASE + 0x048) +#define JS_COMC_204B_RX1_ENABLEMODULE (JS_COMC_204B_RX1_BASE + 0x050) +#define JS_COMC_204B_RX1_ENABLELINKTEST (JS_COMC_204B_RX1_BASE + 0x054) +#define JS_COMC_204B_RX1_GEN_SYSREF (JS_COMC_204B_RX1_BASE + 0x3E4) +#define JS_COMC_204B_RX1_FEC_EN (JS_COMC_204B_RX1_BASE + 0x2C4) +#define JS_COMC_204B_RX1_CRC3_EN (JS_COMC_204B_RX1_BASE + 0x2C8) +#define JS_COMC_204B_RX1_CRC12_EN (JS_COMC_204B_RX1_BASE + 0x2CC) +#define JS_COMC_204B_RX1_SOFT_SYNC (JS_COMC_204B_RX1_BASE + 0x2D0) +#define JS_COMC_204B_RX1_E (JS_COMC_204B_RX1_BASE + 0x2D4) +#define JS_COMC_204B_RX1_BIT_ORDER (JS_COMC_204B_RX1_BASE + 0x2D8) +#define JS_COMC_204B_RX1_TL_TEST_MODE (JS_COMC_204B_RX1_BASE + 0x2DC) +#define JS_COMC_204B_RX1_RESYNC_COUNT_STATUS (JS_COMC_204B_RX1_BASE + 0x2FC) +#define JS_COMC_204B_RX1_S_ON_IF_REG (JS_COMC_204B_RX1_BASE + 0x368) +//#define JS_COMC_204B_RX1_MERGE_CF_GROUP (JS_COMC_204B_RX1_BASE + 0x36C) +#define JS_COMC_204B_RX1_CMD_EN (JS_COMC_204B_RX1_BASE + 0x370) +#define JS_COMC_204B_RX1_SYSREF_COUNTER_STATUS (JS_COMC_204B_RX1_BASE + 0x374) +#define JS_COMC_204B_RX1_LINKCONFIGURATIONERROR (JS_COMC_204B_RX1_BASE + 0x04C) +#define JS_COMC_204B_RX1_LINKTEST_0_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x058) +#define JS_COMC_204B_RX1_LINKTEST_1_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x05C) +#define JS_COMC_204B_RX1_LINKTEST_2_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x060) +#define JS_COMC_204B_RX1_LINKTEST_3_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x064) +#define JS_COMC_204B_RX1_LINKTEST_4_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x068) +#define JS_COMC_204B_RX1_LINKTEST_5_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x06C) +#define JS_COMC_204B_RX1_LINKTEST_6_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x070) +#define JS_COMC_204B_RX1_LINKTEST_7_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x074) +#define JS_COMC_204B_RX1_LINKTEST_8_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x078) +#define JS_COMC_204B_RX1_LINKTEST_9_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x07C) +#define JS_COMC_204B_RX1_LINKTEST_10_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x080) +#define JS_COMC_204B_RX1_LINKTEST_11_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x084) +#define JS_COMC_204B_RX1_LINKTEST_12_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x088) +#define JS_COMC_204B_RX1_LINKTEST_13_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x08C) +#define JS_COMC_204B_RX1_LINKTEST_14_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x090) +#define JS_COMC_204B_RX1_LINKTEST_15_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x094) +#define JS_COMC_204B_RX1_LINKTEST_16_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x098) +#define JS_COMC_204B_RX1_LINKTEST_17_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x09C) +#define JS_COMC_204B_RX1_LINKTEST_18_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x0A0) +#define JS_COMC_204B_RX1_LINKTEST_19_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x0A4) +#define JS_COMC_204B_RX1_LINKTEST_20_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x0A8) +#define JS_COMC_204B_RX1_LINKTEST_21_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x0AC) +#define JS_COMC_204B_RX1_LINKTEST_22_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x0B0) +#define JS_COMC_204B_RX1_LINKTEST_23_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x0B4) +#define JS_COMC_204B_RX1_LINKTEST_0_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x0C0) +#define JS_COMC_204B_RX1_LINKTEST_1_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x0C4) +#define JS_COMC_204B_RX1_LINKTEST_2_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x0C8) +#define JS_COMC_204B_RX1_LINKTEST_3_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x0CC) +#define JS_COMC_204B_RX1_LINKTEST_4_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x0D0) +#define JS_COMC_204B_RX1_LINKTEST_5_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x0D4) +#define JS_COMC_204B_RX1_LINKTEST_6_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x0D8) +#define JS_COMC_204B_RX1_LINKTEST_7_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x0DC) +#define JS_COMC_204B_RX1_LINKTEST_8_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x0E0) +#define JS_COMC_204B_RX1_LINKTEST_9_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x0E4) +#define JS_COMC_204B_RX1_LINKTEST_10_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x0E8) +#define JS_COMC_204B_RX1_LINKTEST_11_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x0EC) +#define JS_COMC_204B_RX1_LINKTEST_12_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x0F0) +#define JS_COMC_204B_RX1_LINKTEST_13_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x0F4) +#define JS_COMC_204B_RX1_LINKTEST_14_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x0F8) +#define JS_COMC_204B_RX1_LINKTEST_15_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x0FC) +#define JS_COMC_204B_RX1_LINKTEST_16_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x100) +#define JS_COMC_204B_RX1_LINKTEST_17_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x104) +#define JS_COMC_204B_RX1_LINKTEST_18_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x108) +#define JS_COMC_204B_RX1_LINKTEST_19_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x10C) +#define JS_COMC_204B_RX1_LINKTEST_20_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x110) +#define JS_COMC_204B_RX1_LINKTEST_21_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x114) +#define JS_COMC_204B_RX1_LINKTEST_22_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x118) +#define JS_COMC_204B_RX1_LINKTEST_23_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x11C) +#define JS_COMC_204B_RX1_FEATURE_DISABLE (JS_COMC_204B_RX1_BASE + 0x120) +#define JS_COMC_204B_RX1_CORE_INTERRUPT_MASK (JS_COMC_204B_RX1_BASE + 0x124) +#define JS_COMC_204B_RX1_CORE_INTERRUPT_STATUS (JS_COMC_204B_RX1_BASE + 0x128) +#define JS_COMC_204B_RX1_ILAS_DETAILS (JS_COMC_204B_RX1_BASE + 0x12C) +#define JS_COMC_204B_RX1_ERR_INJ_REQ (JS_COMC_204B_RX1_BASE + 0x130) +#define JS_COMC_204B_RX1_CLK_RATIO (JS_COMC_204B_RX1_BASE + 0x13C) +#define JS_COMC_204B_RX1_PRBS_TEST_0_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x140) +#define JS_COMC_204B_RX1_PRBS_TEST_1_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x144) +#define JS_COMC_204B_RX1_PRBS_TEST_2_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x148) +#define JS_COMC_204B_RX1_PRBS_TEST_3_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x14C) +#define JS_COMC_204B_RX1_PRBS_TEST_4_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x150) +#define JS_COMC_204B_RX1_PRBS_TEST_5_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x154) +#define JS_COMC_204B_RX1_PRBS_TEST_6_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x158) +#define JS_COMC_204B_RX1_PRBS_TEST_7_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x15C) +#define JS_COMC_204B_RX1_PRBS_TEST_8_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x160) +#define JS_COMC_204B_RX1_PRBS_TEST_9_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x164) +#define JS_COMC_204B_RX1_PRBS_TEST_10_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x168) +#define JS_COMC_204B_RX1_PRBS_TEST_11_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x16C) +#define JS_COMC_204B_RX1_PRBS_TEST_12_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x170) +#define JS_COMC_204B_RX1_PRBS_TEST_13_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x174) +#define JS_COMC_204B_RX1_PRBS_TEST_14_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x178) +#define JS_COMC_204B_RX1_PRBS_TEST_15_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x17C) +#define JS_COMC_204B_RX1_PRBS_TEST_16_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x180) +#define JS_COMC_204B_RX1_PRBS_TEST_17_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x184) +#define JS_COMC_204B_RX1_PRBS_TEST_18_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x188) +#define JS_COMC_204B_RX1_PRBS_TEST_19_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x18C) +#define JS_COMC_204B_RX1_PRBS_TEST_20_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x190) +#define JS_COMC_204B_RX1_PRBS_TEST_21_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x194) +#define JS_COMC_204B_RX1_PRBS_TEST_22_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x198) +#define JS_COMC_204B_RX1_PRBS_TEST_23_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x19C) +#define JS_COMC_204B_RX1_JTSPAT_TEST_0_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1A0) +#define JS_COMC_204B_RX1_JTSPAT_TEST_1_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1A4) +#define JS_COMC_204B_RX1_JTSPAT_TEST_2_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1A8) +#define JS_COMC_204B_RX1_JTSPAT_TEST_3_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1AC) +#define JS_COMC_204B_RX1_JTSPAT_TEST_4_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1B0) +#define JS_COMC_204B_RX1_JTSPAT_TEST_5_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1B4) +#define JS_COMC_204B_RX1_JTSPAT_TEST_6_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1B8) +#define JS_COMC_204B_RX1_JTSPAT_TEST_7_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1BC) +#define JS_COMC_204B_RX1_JTSPAT_TEST_8_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1C0) +#define JS_COMC_204B_RX1_JTSPAT_TEST_9_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1C4) +#define JS_COMC_204B_RX1_JTSPAT_TEST_10_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1C8) +#define JS_COMC_204B_RX1_JTSPAT_TEST_11_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1CC) +#define JS_COMC_204B_RX1_JTSPAT_TEST_12_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1D0) +#define JS_COMC_204B_RX1_JTSPAT_TEST_13_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1D4) +#define JS_COMC_204B_RX1_JTSPAT_TEST_14_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1D8) +#define JS_COMC_204B_RX1_JTSPAT_TEST_15_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1DC) +#define JS_COMC_204B_RX1_JTSPAT_TEST_16_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1E0) +#define JS_COMC_204B_RX1_JTSPAT_TEST_17_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1E4) +#define JS_COMC_204B_RX1_JTSPAT_TEST_18_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1E8) +#define JS_COMC_204B_RX1_JTSPAT_TEST_19_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1EC) +#define JS_COMC_204B_RX1_JTSPAT_TEST_20_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1F0) +#define JS_COMC_204B_RX1_JTSPAT_TEST_21_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1F4) +#define JS_COMC_204B_RX1_JTSPAT_TEST_22_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1F8) +#define JS_COMC_204B_RX1_JTSPAT_TEST_23_ERRORCOUNTER (JS_COMC_204B_RX1_BASE + 0x1FC) +#define JS_COMC_204B_RX1_PRBS_TEST_0_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x200) +#define JS_COMC_204B_RX1_PRBS_TEST_1_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x204) +#define JS_COMC_204B_RX1_PRBS_TEST_2_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x208) +#define JS_COMC_204B_RX1_PRBS_TEST_3_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x20C) +#define JS_COMC_204B_RX1_PRBS_TEST_4_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x210) +#define JS_COMC_204B_RX1_PRBS_TEST_5_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x214) +#define JS_COMC_204B_RX1_PRBS_TEST_6_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x218) +#define JS_COMC_204B_RX1_PRBS_TEST_7_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x21C) +#define JS_COMC_204B_RX1_PRBS_TEST_8_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x220) +#define JS_COMC_204B_RX1_PRBS_TEST_9_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x224) +#define JS_COMC_204B_RX1_PRBS_TEST_10_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x228) +#define JS_COMC_204B_RX1_PRBS_TEST_11_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x22C) +#define JS_COMC_204B_RX1_PRBS_TEST_12_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x230) +#define JS_COMC_204B_RX1_PRBS_TEST_13_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x234) +#define JS_COMC_204B_RX1_PRBS_TEST_14_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x238) +#define JS_COMC_204B_RX1_PRBS_TEST_15_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x23C) +#define JS_COMC_204B_RX1_PRBS_TEST_16_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x240) +#define JS_COMC_204B_RX1_PRBS_TEST_17_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x244) +#define JS_COMC_204B_RX1_PRBS_TEST_18_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x248) +#define JS_COMC_204B_RX1_PRBS_TEST_19_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x24C) +#define JS_COMC_204B_RX1_PRBS_TEST_20_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x250) +#define JS_COMC_204B_RX1_PRBS_TEST_21_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x254) +#define JS_COMC_204B_RX1_PRBS_TEST_22_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x258) +#define JS_COMC_204B_RX1_PRBS_TEST_23_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x25C) +#define JS_COMC_204B_RX1_JTSPAT_TEST_0_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x260) +#define JS_COMC_204B_RX1_JTSPAT_TEST_1_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x264) +#define JS_COMC_204B_RX1_JTSPAT_TEST_2_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x268) +#define JS_COMC_204B_RX1_JTSPAT_TEST_3_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x26C) +#define JS_COMC_204B_RX1_JTSPAT_TEST_4_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x270) +#define JS_COMC_204B_RX1_JTSPAT_TEST_5_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x274) +#define JS_COMC_204B_RX1_JTSPAT_TEST_6_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x278) +#define JS_COMC_204B_RX1_JTSPAT_TEST_7_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x27C) +#define JS_COMC_204B_RX1_JTSPAT_TEST_8_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x280) +#define JS_COMC_204B_RX1_JTSPAT_TEST_9_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x284) +#define JS_COMC_204B_RX1_JTSPAT_TEST_10_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x288) +#define JS_COMC_204B_RX1_JTSPAT_TEST_11_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x28C) +#define JS_COMC_204B_RX1_JTSPAT_TEST_12_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x290) +#define JS_COMC_204B_RX1_JTSPAT_TEST_13_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x294) +#define JS_COMC_204B_RX1_JTSPAT_TEST_14_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x298) +#define JS_COMC_204B_RX1_JTSPAT_TEST_15_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x29C) +#define JS_COMC_204B_RX1_JTSPAT_TEST_16_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x2A0) +#define JS_COMC_204B_RX1_JTSPAT_TEST_17_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x2A4) +#define JS_COMC_204B_RX1_JTSPAT_TEST_18_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x2A8) +#define JS_COMC_204B_RX1_JTSPAT_TEST_19_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x2AC) +#define JS_COMC_204B_RX1_JTSPAT_TEST_20_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x2B0) +#define JS_COMC_204B_RX1_JTSPAT_TEST_21_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x2B4) +#define JS_COMC_204B_RX1_JTSPAT_TEST_22_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x2B8) +#define JS_COMC_204B_RX1_JTSPAT_TEST_23_RECEIVECOUNTER (JS_COMC_204B_RX1_BASE + 0x2BC) +#define JS_COMC_204B_RX1_LMFC_LEMC_DELAY (JS_COMC_204B_RX1_BASE + 0x2E0) +#define JS_COMC_204B_RX1_SYSREF_CONFIG (JS_COMC_204B_RX1_BASE + 0x2E4) +#define JS_COMC_204B_RX1_MAST_INST (JS_COMC_204B_RX1_BASE + 0x2E8) +#define JS_COMC_204B_RX1_SH_LOCK_STATUS (JS_COMC_204B_RX1_BASE + 0x2EC) +#define JS_COMC_204B_RX1_SH_LOCK_LOSS_STATUS (JS_COMC_204B_RX1_BASE + 0x2F0) +#define JS_COMC_204B_RX1_EMB_LOCK_STATUS (JS_COMC_204B_RX1_BASE + 0x2F4) +#define JS_COMC_204B_RX1_EMB_LOCK_LOSS_STATUS (JS_COMC_204B_RX1_BASE + 0x2F8) +#define JS_COMC_204B_RX1_LEMC_BOUNDARY_PHASE (JS_COMC_204B_RX1_BASE + 0x3D8) +#define JS_COMC_204B_RX1_RBD_LENGTH_OCTETS (JS_COMC_204B_RX1_BASE + 0x3DC) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE0 (JS_COMC_204B_RX1_BASE + 0x300) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE1 (JS_COMC_204B_RX1_BASE + 0x304) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE2 (JS_COMC_204B_RX1_BASE + 0x308) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE3 (JS_COMC_204B_RX1_BASE + 0x30C) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE4 (JS_COMC_204B_RX1_BASE + 0x310) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE5 (JS_COMC_204B_RX1_BASE + 0x314) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE6 (JS_COMC_204B_RX1_BASE + 0x318) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE7 (JS_COMC_204B_RX1_BASE + 0x31C) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE8 (JS_COMC_204B_RX1_BASE + 0x320) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE9 (JS_COMC_204B_RX1_BASE + 0x324) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE10 (JS_COMC_204B_RX1_BASE + 0x328) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE11 (JS_COMC_204B_RX1_BASE + 0x32C) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE12 (JS_COMC_204B_RX1_BASE + 0x330) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE13 (JS_COMC_204B_RX1_BASE + 0x334) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE14 (JS_COMC_204B_RX1_BASE + 0x338) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE15 (JS_COMC_204B_RX1_BASE + 0x33C) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE16 (JS_COMC_204B_RX1_BASE + 0x340) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE17 (JS_COMC_204B_RX1_BASE + 0x344) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE18 (JS_COMC_204B_RX1_BASE + 0x348) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE19 (JS_COMC_204B_RX1_BASE + 0x34C) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE20 (JS_COMC_204B_RX1_BASE + 0x350) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE21 (JS_COMC_204B_RX1_BASE + 0x354) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE22 (JS_COMC_204B_RX1_BASE + 0x358) +#define JS_COMC_204B_RX1_ERROR_REPORT_LANE23 (JS_COMC_204B_RX1_BASE + 0x35C) +#define JS_COMC_204B_RX1_TRESH_EMB_ERR (JS_COMC_204B_RX1_BASE + 0x360) +#define JS_COMC_204B_RX1_TRESH_SH_ERR (JS_COMC_204B_RX1_BASE + 0x364) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE0 (JS_COMC_204B_RX1_BASE + 0x378) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE1 (JS_COMC_204B_RX1_BASE + 0x37C) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE2 (JS_COMC_204B_RX1_BASE + 0x380) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE3 (JS_COMC_204B_RX1_BASE + 0x384) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE4 (JS_COMC_204B_RX1_BASE + 0x388) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE5 (JS_COMC_204B_RX1_BASE + 0x38C) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE6 (JS_COMC_204B_RX1_BASE + 0x390) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE7 (JS_COMC_204B_RX1_BASE + 0x394) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE8 (JS_COMC_204B_RX1_BASE + 0x398) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE9 (JS_COMC_204B_RX1_BASE + 0x39C) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE10 (JS_COMC_204B_RX1_BASE + 0x3A0) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE11 (JS_COMC_204B_RX1_BASE + 0x3A4) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE12 (JS_COMC_204B_RX1_BASE + 0x3A8) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE13 (JS_COMC_204B_RX1_BASE + 0x3AC) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE14 (JS_COMC_204B_RX1_BASE + 0x3B0) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE15 (JS_COMC_204B_RX1_BASE + 0x3B4) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE16 (JS_COMC_204B_RX1_BASE + 0x3B8) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE17 (JS_COMC_204B_RX1_BASE + 0x3BC) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE18 (JS_COMC_204B_RX1_BASE + 0x3C0) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE19 (JS_COMC_204B_RX1_BASE + 0x3C4) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE20 (JS_COMC_204B_RX1_BASE + 0x3C8) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE21 (JS_COMC_204B_RX1_BASE + 0x3CC) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE22 (JS_COMC_204B_RX1_BASE + 0x3D0) +#define JS_COMC_204B_RX1_ICOUNTER_REPORT_LANE23 (JS_COMC_204B_RX1_BASE + 0x3D4) + +#define JS_COMC_204B_TX_BANK_ID (JS_COMC_204B_TX_BASE + 0x000) +#define JS_COMC_204B_TX_DID (JS_COMC_204B_TX_BASE + 0x004) +#define JS_COMC_204B_TX_LID (JS_COMC_204B_TX_BASE + 0x008) +#define JS_COMC_204B_TX_LID2 (JS_COMC_204B_TX_BASE + 0x00C) +#define JS_COMC_204B_TX_LID3 (JS_COMC_204B_TX_BASE + 0x010) +#define JS_COMC_204B_TX_LID4 (JS_COMC_204B_TX_BASE + 0x014) +#define JS_COMC_204B_TX_DATAPATH_INTERCONNECT (JS_COMC_204B_TX_BASE + 0x018) +#define JS_COMC_204B_TX_SUBCLASS (JS_COMC_204B_TX_BASE + 0x01C) +#define JS_COMC_204B_TX_CF (JS_COMC_204B_TX_BASE + 0x020) +#define JS_COMC_204B_TX_CS (JS_COMC_204B_TX_BASE + 0x024) +#define JS_COMC_204B_TX_F (JS_COMC_204B_TX_BASE + 0x028) +#define JS_COMC_204B_TX_K (JS_COMC_204B_TX_BASE + 0x02C) +#define JS_COMC_204B_TX_L (JS_COMC_204B_TX_BASE + 0x030) +#define JS_COMC_204B_TX_N (JS_COMC_204B_TX_BASE + 0x034) +#define JS_COMC_204B_TX_M (JS_COMC_204B_TX_BASE + 0x038) +#define JS_COMC_204B_TX_NTOTAL (JS_COMC_204B_TX_BASE + 0x03C) +#define JS_COMC_204B_TX_S (JS_COMC_204B_TX_BASE + 0x040) +#define JS_COMC_204B_TX_HD (JS_COMC_204B_TX_BASE + 0x044) +#define JS_COMC_204B_TX_SCR (JS_COMC_204B_TX_BASE + 0x048) +#define JS_COMC_204B_TX_ENABLEMODULE (JS_COMC_204B_TX_BASE + 0x050) +#define JS_COMC_204B_TX_ENABLELINKTEST (JS_COMC_204B_TX_BASE + 0x054) +#define JS_COMC_204B_TX_GEN_SYSREF (JS_COMC_204B_TX_BASE + 0x3E4) +#define JS_COMC_204B_TX_FEC_EN (JS_COMC_204B_TX_BASE + 0x2C4) +#define JS_COMC_204B_TX_CRC3_EN (JS_COMC_204B_TX_BASE + 0x2C8) +#define JS_COMC_204B_TX_CRC12_EN (JS_COMC_204B_TX_BASE + 0x2CC) +#define JS_COMC_204B_TX_SOFT_SYNC (JS_COMC_204B_TX_BASE + 0x2D0) +#define JS_COMC_204B_TX_E (JS_COMC_204B_TX_BASE + 0x2D4) +#define JS_COMC_204B_TX_BIT_ORDER (JS_COMC_204B_TX_BASE + 0x2D8) +#define JS_COMC_204B_TX_TL_TEST_MODE (JS_COMC_204B_TX_BASE + 0x2DC) +#define JS_COMC_204B_TX_RESYNC_COUNT_STATUS (JS_COMC_204B_TX_BASE + 0x2FC) +#define JS_COMC_204B_TX_S_ON_IF_REG (JS_COMC_204B_TX_BASE + 0x368) +//#define JS_COMC_204B_TX_MERGE_CF_GROUP (JS_COMC_204B_TX_BASE + 0x36C) +#define JS_COMC_204B_TX_CMD_EN (JS_COMC_204B_TX_BASE + 0x370) +#define JS_COMC_204B_TX_SYSREF_COUNTER_STATUS (JS_COMC_204B_TX_BASE + 0x374) +//#define JS_COMC_204B_TX_TAILBITS (JS_COMC_204B_TX_BASE + 0x058) +#define JS_COMC_204B_TX_LINKTEST_CUSTOM_DATA (JS_COMC_204B_TX_BASE + 0x05C) +#define JS_COMC_204B_TX_LINKTEST_CUSTOM_ENABLE (JS_COMC_204B_TX_BASE + 0x060) +#define JS_COMC_204B_TX_FEATURE_DISABLE (JS_COMC_204B_TX_BASE + 0x120) +#define JS_COMC_204B_TX_CORE_INTERRUPT_MASK (JS_COMC_204B_TX_BASE + 0x124) +#define JS_COMC_204B_TX_CORE_INTERRUPT_STATUS (JS_COMC_204B_TX_BASE + 0x128) +#define JS_COMC_204B_TX_ILAS_DETAILS (JS_COMC_204B_TX_BASE + 0x12C) +#define JS_COMC_204B_TX_CLK_RATIO (JS_COMC_204B_TX_BASE + 0x13C) +#define JS_COMC_204B_TX_FIRST_SYMBOL_DISP (JS_COMC_204B_TX_BASE + 0x140) +#define JS_COMC_204B_TX_TL_LATENCY (JS_COMC_204B_TX_BASE + 0x2C0) +#define JS_COMC_204B_TX_LMFC_LEMC_DELAY (JS_COMC_204B_TX_BASE + 0x2E0) +#define JS_COMC_204B_TX_SYSREF_CONFIG (JS_COMC_204B_TX_BASE + 0x2E4) +#define JS_COMC_204B_TX_SAMPLE_REQ (JS_COMC_204B_TX_BASE + 0x3E0) + +#define JS_COMC_204C_RX0_BANK_ID (JS_COMC_204C_RX0_BASE + 0x000) +#define JS_COMC_204C_RX0_DID (JS_COMC_204C_RX0_BASE + 0x004) +#define JS_COMC_204C_RX0_LID (JS_COMC_204C_RX0_BASE + 0x008) +#define JS_COMC_204C_RX0_LID2 (JS_COMC_204C_RX0_BASE + 0x00C) +#define JS_COMC_204C_RX0_LID3 (JS_COMC_204C_RX0_BASE + 0x010) +#define JS_COMC_204C_RX0_LID4 (JS_COMC_204C_RX0_BASE + 0x014) +#define JS_COMC_204C_RX0_DATAPATH_INTERCONNECT (JS_COMC_204C_RX0_BASE + 0x018) +#define JS_COMC_204C_RX0_SUBCLASS (JS_COMC_204C_RX0_BASE + 0x01C) +#define JS_COMC_204C_RX0_CF (JS_COMC_204C_RX0_BASE + 0x020) +#define JS_COMC_204C_RX0_CS (JS_COMC_204C_RX0_BASE + 0x024) +#define JS_COMC_204C_RX0_F (JS_COMC_204C_RX0_BASE + 0x028) +#define JS_COMC_204C_RX0_K (JS_COMC_204C_RX0_BASE + 0x02C) +#define JS_COMC_204C_RX0_L (JS_COMC_204C_RX0_BASE + 0x030) +#define JS_COMC_204C_RX0_N (JS_COMC_204C_RX0_BASE + 0x034) +#define JS_COMC_204C_RX0_M (JS_COMC_204C_RX0_BASE + 0x038) +#define JS_COMC_204C_RX0_NTOTAL (JS_COMC_204C_RX0_BASE + 0x03C) +#define JS_COMC_204C_RX0_S (JS_COMC_204C_RX0_BASE + 0x040) +#define JS_COMC_204C_RX0_HD (JS_COMC_204C_RX0_BASE + 0x044) +#define JS_COMC_204C_RX0_SCR (JS_COMC_204C_RX0_BASE + 0x048) +#define JS_COMC_204C_RX0_ENABLEMODULE (JS_COMC_204C_RX0_BASE + 0x050) +#define JS_COMC_204C_RX0_ENABLELINKTEST (JS_COMC_204C_RX0_BASE + 0x054) +#define JS_COMC_204C_RX0_GEN_SYSREF (JS_COMC_204C_RX0_BASE + 0x3E4) +#define JS_COMC_204C_RX0_FEC_EN (JS_COMC_204C_RX0_BASE + 0x2C4) +#define JS_COMC_204C_RX0_CRC3_EN (JS_COMC_204C_RX0_BASE + 0x2C8) +#define JS_COMC_204C_RX0_CRC12_EN (JS_COMC_204C_RX0_BASE + 0x2CC) +#define JS_COMC_204C_RX0_SOFT_SYNC (JS_COMC_204C_RX0_BASE + 0x2D0) +#define JS_COMC_204C_RX0_E (JS_COMC_204C_RX0_BASE + 0x2D4) +#define JS_COMC_204C_RX0_BIT_ORDER (JS_COMC_204C_RX0_BASE + 0x2D8) +#define JS_COMC_204C_RX0_TL_TEST_MODE (JS_COMC_204C_RX0_BASE + 0x2DC) +#define JS_COMC_204C_RX0_RESYNC_COUNT_STATUS (JS_COMC_204C_RX0_BASE + 0x2FC) +#define JS_COMC_204C_RX0_S_ON_IF_REG (JS_COMC_204C_RX0_BASE + 0x368) +//#define JS_COMC_204C_RX0_MERGE_CF_GROUP (JS_COMC_204C_RX0_BASE + 0x36C) +#define JS_COMC_204C_RX0_CMD_EN (JS_COMC_204C_RX0_BASE + 0x370) +#define JS_COMC_204C_RX0_SYSREF_COUNTER_STATUS (JS_COMC_204C_RX0_BASE + 0x374) +#define JS_COMC_204C_RX0_LINKCONFIGURATIONERROR (JS_COMC_204C_RX0_BASE + 0x04C) +#define JS_COMC_204C_RX0_LINKTEST_0_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x058) +#define JS_COMC_204C_RX0_LINKTEST_1_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x05C) +#define JS_COMC_204C_RX0_LINKTEST_2_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x060) +#define JS_COMC_204C_RX0_LINKTEST_3_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x064) +#define JS_COMC_204C_RX0_LINKTEST_4_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x068) +#define JS_COMC_204C_RX0_LINKTEST_5_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x06C) +#define JS_COMC_204C_RX0_LINKTEST_6_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x070) +#define JS_COMC_204C_RX0_LINKTEST_7_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x074) +#define JS_COMC_204C_RX0_LINKTEST_8_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x078) +#define JS_COMC_204C_RX0_LINKTEST_9_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x07C) +#define JS_COMC_204C_RX0_LINKTEST_10_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x080) +#define JS_COMC_204C_RX0_LINKTEST_11_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x084) +#define JS_COMC_204C_RX0_LINKTEST_12_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x088) +#define JS_COMC_204C_RX0_LINKTEST_13_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x08C) +#define JS_COMC_204C_RX0_LINKTEST_14_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x090) +#define JS_COMC_204C_RX0_LINKTEST_15_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x094) +#define JS_COMC_204C_RX0_LINKTEST_16_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x098) +#define JS_COMC_204C_RX0_LINKTEST_17_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x09C) +#define JS_COMC_204C_RX0_LINKTEST_18_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x0A0) +#define JS_COMC_204C_RX0_LINKTEST_19_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x0A4) +#define JS_COMC_204C_RX0_LINKTEST_20_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x0A8) +#define JS_COMC_204C_RX0_LINKTEST_21_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x0AC) +#define JS_COMC_204C_RX0_LINKTEST_22_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x0B0) +#define JS_COMC_204C_RX0_LINKTEST_23_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x0B4) +#define JS_COMC_204C_RX0_LINKTEST_0_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x0C0) +#define JS_COMC_204C_RX0_LINKTEST_1_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x0C4) +#define JS_COMC_204C_RX0_LINKTEST_2_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x0C8) +#define JS_COMC_204C_RX0_LINKTEST_3_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x0CC) +#define JS_COMC_204C_RX0_LINKTEST_4_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x0D0) +#define JS_COMC_204C_RX0_LINKTEST_5_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x0D4) +#define JS_COMC_204C_RX0_LINKTEST_6_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x0D8) +#define JS_COMC_204C_RX0_LINKTEST_7_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x0DC) +#define JS_COMC_204C_RX0_LINKTEST_8_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x0E0) +#define JS_COMC_204C_RX0_LINKTEST_9_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x0E4) +#define JS_COMC_204C_RX0_LINKTEST_10_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x0E8) +#define JS_COMC_204C_RX0_LINKTEST_11_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x0EC) +#define JS_COMC_204C_RX0_LINKTEST_12_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x0F0) +#define JS_COMC_204C_RX0_LINKTEST_13_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x0F4) +#define JS_COMC_204C_RX0_LINKTEST_14_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x0F8) +#define JS_COMC_204C_RX0_LINKTEST_15_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x0FC) +#define JS_COMC_204C_RX0_LINKTEST_16_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x100) +#define JS_COMC_204C_RX0_LINKTEST_17_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x104) +#define JS_COMC_204C_RX0_LINKTEST_18_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x108) +#define JS_COMC_204C_RX0_LINKTEST_19_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x10C) +#define JS_COMC_204C_RX0_LINKTEST_20_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x110) +#define JS_COMC_204C_RX0_LINKTEST_21_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x114) +#define JS_COMC_204C_RX0_LINKTEST_22_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x118) +#define JS_COMC_204C_RX0_LINKTEST_23_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x11C) +#define JS_COMC_204C_RX0_FEATURE_DISABLE (JS_COMC_204C_RX0_BASE + 0x120) +#define JS_COMC_204C_RX0_CORE_INTERRUPT_MASK (JS_COMC_204C_RX0_BASE + 0x124) +#define JS_COMC_204C_RX0_CORE_INTERRUPT_STATUS (JS_COMC_204C_RX0_BASE + 0x128) +#define JS_COMC_204C_RX0_ILAS_DETAILS (JS_COMC_204C_RX0_BASE + 0x12C) +#define JS_COMC_204C_RX0_ERR_INJ_REQ (JS_COMC_204C_RX0_BASE + 0x130) +#define JS_COMC_204C_RX0_CLK_RATIO (JS_COMC_204C_RX0_BASE + 0x13C) +#define JS_COMC_204C_RX0_PRBS_TEST_0_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x140) +#define JS_COMC_204C_RX0_PRBS_TEST_1_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x144) +#define JS_COMC_204C_RX0_PRBS_TEST_2_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x148) +#define JS_COMC_204C_RX0_PRBS_TEST_3_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x14C) +#define JS_COMC_204C_RX0_PRBS_TEST_4_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x150) +#define JS_COMC_204C_RX0_PRBS_TEST_5_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x154) +#define JS_COMC_204C_RX0_PRBS_TEST_6_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x158) +#define JS_COMC_204C_RX0_PRBS_TEST_7_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x15C) +#define JS_COMC_204C_RX0_PRBS_TEST_8_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x160) +#define JS_COMC_204C_RX0_PRBS_TEST_9_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x164) +#define JS_COMC_204C_RX0_PRBS_TEST_10_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x168) +#define JS_COMC_204C_RX0_PRBS_TEST_11_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x16C) +#define JS_COMC_204C_RX0_PRBS_TEST_12_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x170) +#define JS_COMC_204C_RX0_PRBS_TEST_13_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x174) +#define JS_COMC_204C_RX0_PRBS_TEST_14_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x178) +#define JS_COMC_204C_RX0_PRBS_TEST_15_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x17C) +#define JS_COMC_204C_RX0_PRBS_TEST_16_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x180) +#define JS_COMC_204C_RX0_PRBS_TEST_17_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x184) +#define JS_COMC_204C_RX0_PRBS_TEST_18_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x188) +#define JS_COMC_204C_RX0_PRBS_TEST_19_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x18C) +#define JS_COMC_204C_RX0_PRBS_TEST_20_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x190) +#define JS_COMC_204C_RX0_PRBS_TEST_21_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x194) +#define JS_COMC_204C_RX0_PRBS_TEST_22_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x198) +#define JS_COMC_204C_RX0_PRBS_TEST_23_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x19C) +#define JS_COMC_204C_RX0_JTSPAT_TEST_0_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1A0) +#define JS_COMC_204C_RX0_JTSPAT_TEST_1_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1A4) +#define JS_COMC_204C_RX0_JTSPAT_TEST_2_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1A8) +#define JS_COMC_204C_RX0_JTSPAT_TEST_3_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1AC) +#define JS_COMC_204C_RX0_JTSPAT_TEST_4_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1B0) +#define JS_COMC_204C_RX0_JTSPAT_TEST_5_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1B4) +#define JS_COMC_204C_RX0_JTSPAT_TEST_6_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1B8) +#define JS_COMC_204C_RX0_JTSPAT_TEST_7_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1BC) +#define JS_COMC_204C_RX0_JTSPAT_TEST_8_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1C0) +#define JS_COMC_204C_RX0_JTSPAT_TEST_9_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1C4) +#define JS_COMC_204C_RX0_JTSPAT_TEST_10_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1C8) +#define JS_COMC_204C_RX0_JTSPAT_TEST_11_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1CC) +#define JS_COMC_204C_RX0_JTSPAT_TEST_12_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1D0) +#define JS_COMC_204C_RX0_JTSPAT_TEST_13_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1D4) +#define JS_COMC_204C_RX0_JTSPAT_TEST_14_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1D8) +#define JS_COMC_204C_RX0_JTSPAT_TEST_15_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1DC) +#define JS_COMC_204C_RX0_JTSPAT_TEST_16_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1E0) +#define JS_COMC_204C_RX0_JTSPAT_TEST_17_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1E4) +#define JS_COMC_204C_RX0_JTSPAT_TEST_18_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1E8) +#define JS_COMC_204C_RX0_JTSPAT_TEST_19_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1EC) +#define JS_COMC_204C_RX0_JTSPAT_TEST_20_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1F0) +#define JS_COMC_204C_RX0_JTSPAT_TEST_21_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1F4) +#define JS_COMC_204C_RX0_JTSPAT_TEST_22_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1F8) +#define JS_COMC_204C_RX0_JTSPAT_TEST_23_ERRORCOUNTER (JS_COMC_204C_RX0_BASE + 0x1FC) +#define JS_COMC_204C_RX0_PRBS_TEST_0_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x200) +#define JS_COMC_204C_RX0_PRBS_TEST_1_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x204) +#define JS_COMC_204C_RX0_PRBS_TEST_2_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x208) +#define JS_COMC_204C_RX0_PRBS_TEST_3_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x20C) +#define JS_COMC_204C_RX0_PRBS_TEST_4_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x210) +#define JS_COMC_204C_RX0_PRBS_TEST_5_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x214) +#define JS_COMC_204C_RX0_PRBS_TEST_6_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x218) +#define JS_COMC_204C_RX0_PRBS_TEST_7_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x21C) +#define JS_COMC_204C_RX0_PRBS_TEST_8_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x220) +#define JS_COMC_204C_RX0_PRBS_TEST_9_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x224) +#define JS_COMC_204C_RX0_PRBS_TEST_10_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x228) +#define JS_COMC_204C_RX0_PRBS_TEST_11_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x22C) +#define JS_COMC_204C_RX0_PRBS_TEST_12_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x230) +#define JS_COMC_204C_RX0_PRBS_TEST_13_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x234) +#define JS_COMC_204C_RX0_PRBS_TEST_14_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x238) +#define JS_COMC_204C_RX0_PRBS_TEST_15_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x23C) +#define JS_COMC_204C_RX0_PRBS_TEST_16_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x240) +#define JS_COMC_204C_RX0_PRBS_TEST_17_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x244) +#define JS_COMC_204C_RX0_PRBS_TEST_18_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x248) +#define JS_COMC_204C_RX0_PRBS_TEST_19_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x24C) +#define JS_COMC_204C_RX0_PRBS_TEST_20_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x250) +#define JS_COMC_204C_RX0_PRBS_TEST_21_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x254) +#define JS_COMC_204C_RX0_PRBS_TEST_22_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x258) +#define JS_COMC_204C_RX0_PRBS_TEST_23_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x25C) +#define JS_COMC_204C_RX0_JTSPAT_TEST_0_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x260) +#define JS_COMC_204C_RX0_JTSPAT_TEST_1_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x264) +#define JS_COMC_204C_RX0_JTSPAT_TEST_2_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x268) +#define JS_COMC_204C_RX0_JTSPAT_TEST_3_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x26C) +#define JS_COMC_204C_RX0_JTSPAT_TEST_4_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x270) +#define JS_COMC_204C_RX0_JTSPAT_TEST_5_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x274) +#define JS_COMC_204C_RX0_JTSPAT_TEST_6_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x278) +#define JS_COMC_204C_RX0_JTSPAT_TEST_7_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x27C) +#define JS_COMC_204C_RX0_JTSPAT_TEST_8_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x280) +#define JS_COMC_204C_RX0_JTSPAT_TEST_9_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x284) +#define JS_COMC_204C_RX0_JTSPAT_TEST_10_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x288) +#define JS_COMC_204C_RX0_JTSPAT_TEST_11_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x28C) +#define JS_COMC_204C_RX0_JTSPAT_TEST_12_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x290) +#define JS_COMC_204C_RX0_JTSPAT_TEST_13_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x294) +#define JS_COMC_204C_RX0_JTSPAT_TEST_14_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x298) +#define JS_COMC_204C_RX0_JTSPAT_TEST_15_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x29C) +#define JS_COMC_204C_RX0_JTSPAT_TEST_16_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x2A0) +#define JS_COMC_204C_RX0_JTSPAT_TEST_17_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x2A4) +#define JS_COMC_204C_RX0_JTSPAT_TEST_18_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x2A8) +#define JS_COMC_204C_RX0_JTSPAT_TEST_19_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x2AC) +#define JS_COMC_204C_RX0_JTSPAT_TEST_20_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x2B0) +#define JS_COMC_204C_RX0_JTSPAT_TEST_21_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x2B4) +#define JS_COMC_204C_RX0_JTSPAT_TEST_22_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x2B8) +#define JS_COMC_204C_RX0_JTSPAT_TEST_23_RECEIVECOUNTER (JS_COMC_204C_RX0_BASE + 0x2BC) +#define JS_COMC_204C_RX0_LMFC_LEMC_DELAY (JS_COMC_204C_RX0_BASE + 0x2E0) +#define JS_COMC_204C_RX0_SYSREF_CONFIG (JS_COMC_204C_RX0_BASE + 0x2E4) +#define JS_COMC_204C_RX0_MAST_INST (JS_COMC_204C_RX0_BASE + 0x2E8) +#define JS_COMC_204C_RX0_SH_LOCK_STATUS (JS_COMC_204C_RX0_BASE + 0x2EC) +#define JS_COMC_204C_RX0_SH_LOCK_LOSS_STATUS (JS_COMC_204C_RX0_BASE + 0x2F0) +#define JS_COMC_204C_RX0_EMB_LOCK_STATUS (JS_COMC_204C_RX0_BASE + 0x2F4) +#define JS_COMC_204C_RX0_EMB_LOCK_LOSS_STATUS (JS_COMC_204C_RX0_BASE + 0x2F8) +#define JS_COMC_204C_RX0_LEMC_BOUNDARY_PHASE (JS_COMC_204C_RX0_BASE + 0x3D8) +#define JS_COMC_204C_RX0_RBD_LENGTH_OCTETS (JS_COMC_204C_RX0_BASE + 0x3DC) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE0 (JS_COMC_204C_RX0_BASE + 0x300) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE1 (JS_COMC_204C_RX0_BASE + 0x304) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE2 (JS_COMC_204C_RX0_BASE + 0x308) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE3 (JS_COMC_204C_RX0_BASE + 0x30C) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE4 (JS_COMC_204C_RX0_BASE + 0x310) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE5 (JS_COMC_204C_RX0_BASE + 0x314) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE6 (JS_COMC_204C_RX0_BASE + 0x318) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE7 (JS_COMC_204C_RX0_BASE + 0x31C) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE8 (JS_COMC_204C_RX0_BASE + 0x320) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE9 (JS_COMC_204C_RX0_BASE + 0x324) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE10 (JS_COMC_204C_RX0_BASE + 0x328) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE11 (JS_COMC_204C_RX0_BASE + 0x32C) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE12 (JS_COMC_204C_RX0_BASE + 0x330) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE13 (JS_COMC_204C_RX0_BASE + 0x334) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE14 (JS_COMC_204C_RX0_BASE + 0x338) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE15 (JS_COMC_204C_RX0_BASE + 0x33C) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE16 (JS_COMC_204C_RX0_BASE + 0x340) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE17 (JS_COMC_204C_RX0_BASE + 0x344) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE18 (JS_COMC_204C_RX0_BASE + 0x348) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE19 (JS_COMC_204C_RX0_BASE + 0x34C) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE20 (JS_COMC_204C_RX0_BASE + 0x350) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE21 (JS_COMC_204C_RX0_BASE + 0x354) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE22 (JS_COMC_204C_RX0_BASE + 0x358) +#define JS_COMC_204C_RX0_ERROR_REPORT_LANE23 (JS_COMC_204C_RX0_BASE + 0x35C) +#define JS_COMC_204C_RX0_TRESH_EMB_ERR (JS_COMC_204C_RX0_BASE + 0x360) +#define JS_COMC_204C_RX0_TRESH_SH_ERR (JS_COMC_204C_RX0_BASE + 0x364) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE0 (JS_COMC_204C_RX0_BASE + 0x378) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE1 (JS_COMC_204C_RX0_BASE + 0x37C) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE2 (JS_COMC_204C_RX0_BASE + 0x380) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE3 (JS_COMC_204C_RX0_BASE + 0x384) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE4 (JS_COMC_204C_RX0_BASE + 0x388) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE5 (JS_COMC_204C_RX0_BASE + 0x38C) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE6 (JS_COMC_204C_RX0_BASE + 0x390) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE7 (JS_COMC_204C_RX0_BASE + 0x394) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE8 (JS_COMC_204C_RX0_BASE + 0x398) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE9 (JS_COMC_204C_RX0_BASE + 0x39C) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE10 (JS_COMC_204C_RX0_BASE + 0x3A0) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE11 (JS_COMC_204C_RX0_BASE + 0x3A4) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE12 (JS_COMC_204C_RX0_BASE + 0x3A8) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE13 (JS_COMC_204C_RX0_BASE + 0x3AC) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE14 (JS_COMC_204C_RX0_BASE + 0x3B0) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE15 (JS_COMC_204C_RX0_BASE + 0x3B4) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE16 (JS_COMC_204C_RX0_BASE + 0x3B8) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE17 (JS_COMC_204C_RX0_BASE + 0x3BC) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE18 (JS_COMC_204C_RX0_BASE + 0x3C0) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE19 (JS_COMC_204C_RX0_BASE + 0x3C4) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE20 (JS_COMC_204C_RX0_BASE + 0x3C8) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE21 (JS_COMC_204C_RX0_BASE + 0x3CC) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE22 (JS_COMC_204C_RX0_BASE + 0x3D0) +#define JS_COMC_204C_RX0_ICOUNTER_REPORT_LANE23 (JS_COMC_204C_RX0_BASE + 0x3D4) + +#define JS_COMC_204C_RX1_BANK_ID (JS_COMC_204C_RX1_BASE + 0x000) +#define JS_COMC_204C_RX1_DID (JS_COMC_204C_RX1_BASE + 0x004) +#define JS_COMC_204C_RX1_LID (JS_COMC_204C_RX1_BASE + 0x008) +#define JS_COMC_204C_RX1_LID2 (JS_COMC_204C_RX1_BASE + 0x00C) +#define JS_COMC_204C_RX1_LID3 (JS_COMC_204C_RX1_BASE + 0x010) +#define JS_COMC_204C_RX1_LID4 (JS_COMC_204C_RX1_BASE + 0x014) +#define JS_COMC_204C_RX1_DATAPATH_INTERCONNECT (JS_COMC_204C_RX1_BASE + 0x018) +#define JS_COMC_204C_RX1_SUBCLASS (JS_COMC_204C_RX1_BASE + 0x01C) +#define JS_COMC_204C_RX1_CF (JS_COMC_204C_RX1_BASE + 0x020) +#define JS_COMC_204C_RX1_CS (JS_COMC_204C_RX1_BASE + 0x024) +#define JS_COMC_204C_RX1_F (JS_COMC_204C_RX1_BASE + 0x028) +#define JS_COMC_204C_RX1_K (JS_COMC_204C_RX1_BASE + 0x02C) +#define JS_COMC_204C_RX1_L (JS_COMC_204C_RX1_BASE + 0x030) +#define JS_COMC_204C_RX1_N (JS_COMC_204C_RX1_BASE + 0x034) +#define JS_COMC_204C_RX1_M (JS_COMC_204C_RX1_BASE + 0x038) +#define JS_COMC_204C_RX1_NTOTAL (JS_COMC_204C_RX1_BASE + 0x03C) +#define JS_COMC_204C_RX1_S (JS_COMC_204C_RX1_BASE + 0x040) +#define JS_COMC_204C_RX1_HD (JS_COMC_204C_RX1_BASE + 0x044) +#define JS_COMC_204C_RX1_SCR (JS_COMC_204C_RX1_BASE + 0x048) +#define JS_COMC_204C_RX1_ENABLEMODULE (JS_COMC_204C_RX1_BASE + 0x050) +#define JS_COMC_204C_RX1_ENABLELINKTEST (JS_COMC_204C_RX1_BASE + 0x054) +#define JS_COMC_204C_RX1_GEN_SYSREF (JS_COMC_204C_RX1_BASE + 0x3E4) +#define JS_COMC_204C_RX1_FEC_EN (JS_COMC_204C_RX1_BASE + 0x2C4) +#define JS_COMC_204C_RX1_CRC3_EN (JS_COMC_204C_RX1_BASE + 0x2C8) +#define JS_COMC_204C_RX1_CRC12_EN (JS_COMC_204C_RX1_BASE + 0x2CC) +#define JS_COMC_204C_RX1_SOFT_SYNC (JS_COMC_204C_RX1_BASE + 0x2D0) +#define JS_COMC_204C_RX1_E (JS_COMC_204C_RX1_BASE + 0x2D4) +#define JS_COMC_204C_RX1_BIT_ORDER (JS_COMC_204C_RX1_BASE + 0x2D8) +#define JS_COMC_204C_RX1_TL_TEST_MODE (JS_COMC_204C_RX1_BASE + 0x2DC) +#define JS_COMC_204C_RX1_RESYNC_COUNT_STATUS (JS_COMC_204C_RX1_BASE + 0x2FC) +#define JS_COMC_204C_RX1_S_ON_IF_REG (JS_COMC_204C_RX1_BASE + 0x368) +//#define JS_COMC_204C_RX1_MERGE_CF_GROUP (JS_COMC_204C_RX1_BASE + 0x36C) +#define JS_COMC_204C_RX1_CMD_EN (JS_COMC_204C_RX1_BASE + 0x370) +#define JS_COMC_204C_RX1_SYSREF_COUNTER_STATUS (JS_COMC_204C_RX1_BASE + 0x374) +#define JS_COMC_204C_RX1_LINKCONFIGURATIONERROR (JS_COMC_204C_RX1_BASE + 0x04C) +#define JS_COMC_204C_RX1_LINKTEST_0_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x058) +#define JS_COMC_204C_RX1_LINKTEST_1_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x05C) +#define JS_COMC_204C_RX1_LINKTEST_2_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x060) +#define JS_COMC_204C_RX1_LINKTEST_3_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x064) +#define JS_COMC_204C_RX1_LINKTEST_4_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x068) +#define JS_COMC_204C_RX1_LINKTEST_5_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x06C) +#define JS_COMC_204C_RX1_LINKTEST_6_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x070) +#define JS_COMC_204C_RX1_LINKTEST_7_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x074) +#define JS_COMC_204C_RX1_LINKTEST_8_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x078) +#define JS_COMC_204C_RX1_LINKTEST_9_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x07C) +#define JS_COMC_204C_RX1_LINKTEST_10_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x080) +#define JS_COMC_204C_RX1_LINKTEST_11_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x084) +#define JS_COMC_204C_RX1_LINKTEST_12_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x088) +#define JS_COMC_204C_RX1_LINKTEST_13_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x08C) +#define JS_COMC_204C_RX1_LINKTEST_14_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x090) +#define JS_COMC_204C_RX1_LINKTEST_15_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x094) +#define JS_COMC_204C_RX1_LINKTEST_16_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x098) +#define JS_COMC_204C_RX1_LINKTEST_17_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x09C) +#define JS_COMC_204C_RX1_LINKTEST_18_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x0A0) +#define JS_COMC_204C_RX1_LINKTEST_19_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x0A4) +#define JS_COMC_204C_RX1_LINKTEST_20_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x0A8) +#define JS_COMC_204C_RX1_LINKTEST_21_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x0AC) +#define JS_COMC_204C_RX1_LINKTEST_22_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x0B0) +#define JS_COMC_204C_RX1_LINKTEST_23_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x0B4) +#define JS_COMC_204C_RX1_LINKTEST_0_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x0C0) +#define JS_COMC_204C_RX1_LINKTEST_1_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x0C4) +#define JS_COMC_204C_RX1_LINKTEST_2_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x0C8) +#define JS_COMC_204C_RX1_LINKTEST_3_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x0CC) +#define JS_COMC_204C_RX1_LINKTEST_4_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x0D0) +#define JS_COMC_204C_RX1_LINKTEST_5_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x0D4) +#define JS_COMC_204C_RX1_LINKTEST_6_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x0D8) +#define JS_COMC_204C_RX1_LINKTEST_7_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x0DC) +#define JS_COMC_204C_RX1_LINKTEST_8_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x0E0) +#define JS_COMC_204C_RX1_LINKTEST_9_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x0E4) +#define JS_COMC_204C_RX1_LINKTEST_10_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x0E8) +#define JS_COMC_204C_RX1_LINKTEST_11_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x0EC) +#define JS_COMC_204C_RX1_LINKTEST_12_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x0F0) +#define JS_COMC_204C_RX1_LINKTEST_13_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x0F4) +#define JS_COMC_204C_RX1_LINKTEST_14_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x0F8) +#define JS_COMC_204C_RX1_LINKTEST_15_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x0FC) +#define JS_COMC_204C_RX1_LINKTEST_16_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x100) +#define JS_COMC_204C_RX1_LINKTEST_17_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x104) +#define JS_COMC_204C_RX1_LINKTEST_18_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x108) +#define JS_COMC_204C_RX1_LINKTEST_19_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x10C) +#define JS_COMC_204C_RX1_LINKTEST_20_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x110) +#define JS_COMC_204C_RX1_LINKTEST_21_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x114) +#define JS_COMC_204C_RX1_LINKTEST_22_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x118) +#define JS_COMC_204C_RX1_LINKTEST_23_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x11C) +#define JS_COMC_204C_RX1_FEATURE_DISABLE (JS_COMC_204C_RX1_BASE + 0x120) +#define JS_COMC_204C_RX1_CORE_INTERRUPT_MASK (JS_COMC_204C_RX1_BASE + 0x124) +#define JS_COMC_204C_RX1_CORE_INTERRUPT_STATUS (JS_COMC_204C_RX1_BASE + 0x128) +#define JS_COMC_204C_RX1_ILAS_DETAILS (JS_COMC_204C_RX1_BASE + 0x12C) +#define JS_COMC_204C_RX1_ERR_INJ_REQ (JS_COMC_204C_RX1_BASE + 0x130) +#define JS_COMC_204C_RX1_CLK_RATIO (JS_COMC_204C_RX1_BASE + 0x13C) +#define JS_COMC_204C_RX1_PRBS_TEST_0_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x140) +#define JS_COMC_204C_RX1_PRBS_TEST_1_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x144) +#define JS_COMC_204C_RX1_PRBS_TEST_2_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x148) +#define JS_COMC_204C_RX1_PRBS_TEST_3_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x14C) +#define JS_COMC_204C_RX1_PRBS_TEST_4_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x150) +#define JS_COMC_204C_RX1_PRBS_TEST_5_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x154) +#define JS_COMC_204C_RX1_PRBS_TEST_6_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x158) +#define JS_COMC_204C_RX1_PRBS_TEST_7_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x15C) +#define JS_COMC_204C_RX1_PRBS_TEST_8_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x160) +#define JS_COMC_204C_RX1_PRBS_TEST_9_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x164) +#define JS_COMC_204C_RX1_PRBS_TEST_10_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x168) +#define JS_COMC_204C_RX1_PRBS_TEST_11_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x16C) +#define JS_COMC_204C_RX1_PRBS_TEST_12_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x170) +#define JS_COMC_204C_RX1_PRBS_TEST_13_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x174) +#define JS_COMC_204C_RX1_PRBS_TEST_14_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x178) +#define JS_COMC_204C_RX1_PRBS_TEST_15_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x17C) +#define JS_COMC_204C_RX1_PRBS_TEST_16_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x180) +#define JS_COMC_204C_RX1_PRBS_TEST_17_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x184) +#define JS_COMC_204C_RX1_PRBS_TEST_18_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x188) +#define JS_COMC_204C_RX1_PRBS_TEST_19_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x18C) +#define JS_COMC_204C_RX1_PRBS_TEST_20_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x190) +#define JS_COMC_204C_RX1_PRBS_TEST_21_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x194) +#define JS_COMC_204C_RX1_PRBS_TEST_22_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x198) +#define JS_COMC_204C_RX1_PRBS_TEST_23_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x19C) +#define JS_COMC_204C_RX1_JTSPAT_TEST_0_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1A0) +#define JS_COMC_204C_RX1_JTSPAT_TEST_1_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1A4) +#define JS_COMC_204C_RX1_JTSPAT_TEST_2_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1A8) +#define JS_COMC_204C_RX1_JTSPAT_TEST_3_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1AC) +#define JS_COMC_204C_RX1_JTSPAT_TEST_4_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1B0) +#define JS_COMC_204C_RX1_JTSPAT_TEST_5_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1B4) +#define JS_COMC_204C_RX1_JTSPAT_TEST_6_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1B8) +#define JS_COMC_204C_RX1_JTSPAT_TEST_7_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1BC) +#define JS_COMC_204C_RX1_JTSPAT_TEST_8_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1C0) +#define JS_COMC_204C_RX1_JTSPAT_TEST_9_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1C4) +#define JS_COMC_204C_RX1_JTSPAT_TEST_10_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1C8) +#define JS_COMC_204C_RX1_JTSPAT_TEST_11_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1CC) +#define JS_COMC_204C_RX1_JTSPAT_TEST_12_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1D0) +#define JS_COMC_204C_RX1_JTSPAT_TEST_13_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1D4) +#define JS_COMC_204C_RX1_JTSPAT_TEST_14_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1D8) +#define JS_COMC_204C_RX1_JTSPAT_TEST_15_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1DC) +#define JS_COMC_204C_RX1_JTSPAT_TEST_16_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1E0) +#define JS_COMC_204C_RX1_JTSPAT_TEST_17_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1E4) +#define JS_COMC_204C_RX1_JTSPAT_TEST_18_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1E8) +#define JS_COMC_204C_RX1_JTSPAT_TEST_19_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1EC) +#define JS_COMC_204C_RX1_JTSPAT_TEST_20_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1F0) +#define JS_COMC_204C_RX1_JTSPAT_TEST_21_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1F4) +#define JS_COMC_204C_RX1_JTSPAT_TEST_22_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1F8) +#define JS_COMC_204C_RX1_JTSPAT_TEST_23_ERRORCOUNTER (JS_COMC_204C_RX1_BASE + 0x1FC) +#define JS_COMC_204C_RX1_PRBS_TEST_0_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x200) +#define JS_COMC_204C_RX1_PRBS_TEST_1_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x204) +#define JS_COMC_204C_RX1_PRBS_TEST_2_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x208) +#define JS_COMC_204C_RX1_PRBS_TEST_3_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x20C) +#define JS_COMC_204C_RX1_PRBS_TEST_4_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x210) +#define JS_COMC_204C_RX1_PRBS_TEST_5_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x214) +#define JS_COMC_204C_RX1_PRBS_TEST_6_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x218) +#define JS_COMC_204C_RX1_PRBS_TEST_7_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x21C) +#define JS_COMC_204C_RX1_PRBS_TEST_8_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x220) +#define JS_COMC_204C_RX1_PRBS_TEST_9_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x224) +#define JS_COMC_204C_RX1_PRBS_TEST_10_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x228) +#define JS_COMC_204C_RX1_PRBS_TEST_11_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x22C) +#define JS_COMC_204C_RX1_PRBS_TEST_12_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x230) +#define JS_COMC_204C_RX1_PRBS_TEST_13_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x234) +#define JS_COMC_204C_RX1_PRBS_TEST_14_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x238) +#define JS_COMC_204C_RX1_PRBS_TEST_15_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x23C) +#define JS_COMC_204C_RX1_PRBS_TEST_16_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x240) +#define JS_COMC_204C_RX1_PRBS_TEST_17_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x244) +#define JS_COMC_204C_RX1_PRBS_TEST_18_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x248) +#define JS_COMC_204C_RX1_PRBS_TEST_19_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x24C) +#define JS_COMC_204C_RX1_PRBS_TEST_20_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x250) +#define JS_COMC_204C_RX1_PRBS_TEST_21_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x254) +#define JS_COMC_204C_RX1_PRBS_TEST_22_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x258) +#define JS_COMC_204C_RX1_PRBS_TEST_23_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x25C) +#define JS_COMC_204C_RX1_JTSPAT_TEST_0_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x260) +#define JS_COMC_204C_RX1_JTSPAT_TEST_1_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x264) +#define JS_COMC_204C_RX1_JTSPAT_TEST_2_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x268) +#define JS_COMC_204C_RX1_JTSPAT_TEST_3_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x26C) +#define JS_COMC_204C_RX1_JTSPAT_TEST_4_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x270) +#define JS_COMC_204C_RX1_JTSPAT_TEST_5_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x274) +#define JS_COMC_204C_RX1_JTSPAT_TEST_6_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x278) +#define JS_COMC_204C_RX1_JTSPAT_TEST_7_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x27C) +#define JS_COMC_204C_RX1_JTSPAT_TEST_8_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x280) +#define JS_COMC_204C_RX1_JTSPAT_TEST_9_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x284) +#define JS_COMC_204C_RX1_JTSPAT_TEST_10_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x288) +#define JS_COMC_204C_RX1_JTSPAT_TEST_11_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x28C) +#define JS_COMC_204C_RX1_JTSPAT_TEST_12_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x290) +#define JS_COMC_204C_RX1_JTSPAT_TEST_13_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x294) +#define JS_COMC_204C_RX1_JTSPAT_TEST_14_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x298) +#define JS_COMC_204C_RX1_JTSPAT_TEST_15_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x29C) +#define JS_COMC_204C_RX1_JTSPAT_TEST_16_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x2A0) +#define JS_COMC_204C_RX1_JTSPAT_TEST_17_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x2A4) +#define JS_COMC_204C_RX1_JTSPAT_TEST_18_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x2A8) +#define JS_COMC_204C_RX1_JTSPAT_TEST_19_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x2AC) +#define JS_COMC_204C_RX1_JTSPAT_TEST_20_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x2B0) +#define JS_COMC_204C_RX1_JTSPAT_TEST_21_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x2B4) +#define JS_COMC_204C_RX1_JTSPAT_TEST_22_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x2B8) +#define JS_COMC_204C_RX1_JTSPAT_TEST_23_RECEIVECOUNTER (JS_COMC_204C_RX1_BASE + 0x2BC) +#define JS_COMC_204C_RX1_LMFC_LEMC_DELAY (JS_COMC_204C_RX1_BASE + 0x2E0) +#define JS_COMC_204C_RX1_SYSREF_CONFIG (JS_COMC_204C_RX1_BASE + 0x2E4) +#define JS_COMC_204C_RX1_MAST_INST (JS_COMC_204C_RX1_BASE + 0x2E8) +#define JS_COMC_204C_RX1_SH_LOCK_STATUS (JS_COMC_204C_RX1_BASE + 0x2EC) +#define JS_COMC_204C_RX1_SH_LOCK_LOSS_STATUS (JS_COMC_204C_RX1_BASE + 0x2F0) +#define JS_COMC_204C_RX1_EMB_LOCK_STATUS (JS_COMC_204C_RX1_BASE + 0x2F4) +#define JS_COMC_204C_RX1_EMB_LOCK_LOSS_STATUS (JS_COMC_204C_RX1_BASE + 0x2F8) +#define JS_COMC_204C_RX1_LEMC_BOUNDARY_PHASE (JS_COMC_204C_RX1_BASE + 0x3D8) +#define JS_COMC_204C_RX1_RBD_LENGTH_OCTETS (JS_COMC_204C_RX1_BASE + 0x3DC) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE0 (JS_COMC_204C_RX1_BASE + 0x300) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE1 (JS_COMC_204C_RX1_BASE + 0x304) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE2 (JS_COMC_204C_RX1_BASE + 0x308) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE3 (JS_COMC_204C_RX1_BASE + 0x30C) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE4 (JS_COMC_204C_RX1_BASE + 0x310) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE5 (JS_COMC_204C_RX1_BASE + 0x314) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE6 (JS_COMC_204C_RX1_BASE + 0x318) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE7 (JS_COMC_204C_RX1_BASE + 0x31C) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE8 (JS_COMC_204C_RX1_BASE + 0x320) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE9 (JS_COMC_204C_RX1_BASE + 0x324) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE10 (JS_COMC_204C_RX1_BASE + 0x328) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE11 (JS_COMC_204C_RX1_BASE + 0x32C) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE12 (JS_COMC_204C_RX1_BASE + 0x330) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE13 (JS_COMC_204C_RX1_BASE + 0x334) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE14 (JS_COMC_204C_RX1_BASE + 0x338) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE15 (JS_COMC_204C_RX1_BASE + 0x33C) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE16 (JS_COMC_204C_RX1_BASE + 0x340) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE17 (JS_COMC_204C_RX1_BASE + 0x344) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE18 (JS_COMC_204C_RX1_BASE + 0x348) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE19 (JS_COMC_204C_RX1_BASE + 0x34C) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE20 (JS_COMC_204C_RX1_BASE + 0x350) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE21 (JS_COMC_204C_RX1_BASE + 0x354) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE22 (JS_COMC_204C_RX1_BASE + 0x358) +#define JS_COMC_204C_RX1_ERROR_REPORT_LANE23 (JS_COMC_204C_RX1_BASE + 0x35C) +#define JS_COMC_204C_RX1_TRESH_EMB_ERR (JS_COMC_204C_RX1_BASE + 0x360) +#define JS_COMC_204C_RX1_TRESH_SH_ERR (JS_COMC_204C_RX1_BASE + 0x364) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE0 (JS_COMC_204C_RX1_BASE + 0x378) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE1 (JS_COMC_204C_RX1_BASE + 0x37C) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE2 (JS_COMC_204C_RX1_BASE + 0x380) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE3 (JS_COMC_204C_RX1_BASE + 0x384) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE4 (JS_COMC_204C_RX1_BASE + 0x388) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE5 (JS_COMC_204C_RX1_BASE + 0x38C) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE6 (JS_COMC_204C_RX1_BASE + 0x390) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE7 (JS_COMC_204C_RX1_BASE + 0x394) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE8 (JS_COMC_204C_RX1_BASE + 0x398) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE9 (JS_COMC_204C_RX1_BASE + 0x39C) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE10 (JS_COMC_204C_RX1_BASE + 0x3A0) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE11 (JS_COMC_204C_RX1_BASE + 0x3A4) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE12 (JS_COMC_204C_RX1_BASE + 0x3A8) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE13 (JS_COMC_204C_RX1_BASE + 0x3AC) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE14 (JS_COMC_204C_RX1_BASE + 0x3B0) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE15 (JS_COMC_204C_RX1_BASE + 0x3B4) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE16 (JS_COMC_204C_RX1_BASE + 0x3B8) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE17 (JS_COMC_204C_RX1_BASE + 0x3BC) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE18 (JS_COMC_204C_RX1_BASE + 0x3C0) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE19 (JS_COMC_204C_RX1_BASE + 0x3C4) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE20 (JS_COMC_204C_RX1_BASE + 0x3C8) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE21 (JS_COMC_204C_RX1_BASE + 0x3CC) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE22 (JS_COMC_204C_RX1_BASE + 0x3D0) +#define JS_COMC_204C_RX1_ICOUNTER_REPORT_LANE23 (JS_COMC_204C_RX1_BASE + 0x3D4) + +#define JS_COMC_204C_TX_BANK_ID (JS_COMC_204C_TX_BASE + 0x000) +#define JS_COMC_204C_TX_DID (JS_COMC_204C_TX_BASE + 0x004) +#define JS_COMC_204C_TX_LID (JS_COMC_204C_TX_BASE + 0x008) +#define JS_COMC_204C_TX_LID2 (JS_COMC_204C_TX_BASE + 0x00C) +#define JS_COMC_204C_TX_LID3 (JS_COMC_204C_TX_BASE + 0x010) +#define JS_COMC_204C_TX_LID4 (JS_COMC_204C_TX_BASE + 0x014) +#define JS_COMC_204C_TX_DATAPATH_INTERCONNECT (JS_COMC_204C_TX_BASE + 0x018) +#define JS_COMC_204C_TX_SUBCLASS (JS_COMC_204C_TX_BASE + 0x01C) +#define JS_COMC_204C_TX_CF (JS_COMC_204C_TX_BASE + 0x020) +#define JS_COMC_204C_TX_CS (JS_COMC_204C_TX_BASE + 0x024) +#define JS_COMC_204C_TX_F (JS_COMC_204C_TX_BASE + 0x028) +#define JS_COMC_204C_TX_K (JS_COMC_204C_TX_BASE + 0x02C) +#define JS_COMC_204C_TX_L (JS_COMC_204C_TX_BASE + 0x030) +#define JS_COMC_204C_TX_N (JS_COMC_204C_TX_BASE + 0x034) +#define JS_COMC_204C_TX_M (JS_COMC_204C_TX_BASE + 0x038) +#define JS_COMC_204C_TX_NTOTAL (JS_COMC_204C_TX_BASE + 0x03C) +#define JS_COMC_204C_TX_S (JS_COMC_204C_TX_BASE + 0x040) +#define JS_COMC_204C_TX_HD (JS_COMC_204C_TX_BASE + 0x044) +#define JS_COMC_204C_TX_SCR (JS_COMC_204C_TX_BASE + 0x048) +#define JS_COMC_204C_TX_ENABLEMODULE (JS_COMC_204C_TX_BASE + 0x050) +#define JS_COMC_204C_TX_ENABLELINKTEST (JS_COMC_204C_TX_BASE + 0x054) +#define JS_COMC_204C_TX_GEN_SYSREF (JS_COMC_204C_TX_BASE + 0x3E4) +#define JS_COMC_204C_TX_FEC_EN (JS_COMC_204C_TX_BASE + 0x2C4) +#define JS_COMC_204C_TX_CRC3_EN (JS_COMC_204C_TX_BASE + 0x2C8) +#define JS_COMC_204C_TX_CRC12_EN (JS_COMC_204C_TX_BASE + 0x2CC) +#define JS_COMC_204C_TX_SOFT_SYNC (JS_COMC_204C_TX_BASE + 0x2D0) +#define JS_COMC_204C_TX_E (JS_COMC_204C_TX_BASE + 0x2D4) +#define JS_COMC_204C_TX_BIT_ORDER (JS_COMC_204C_TX_BASE + 0x2D8) +#define JS_COMC_204C_TX_TL_TEST_MODE (JS_COMC_204C_TX_BASE + 0x2DC) +#define JS_COMC_204C_TX_RESYNC_COUNT_STATUS (JS_COMC_204C_TX_BASE + 0x2FC) +#define JS_COMC_204C_TX_S_ON_IF_REG (JS_COMC_204C_TX_BASE + 0x368) +//#define JS_COMC_204C_TX_MERGE_CF_GROUP (JS_COMC_204C_TX_BASE + 0x36C) +#define JS_COMC_204C_TX_CMD_EN (JS_COMC_204C_TX_BASE + 0x370) +#define JS_COMC_204C_TX_SYSREF_COUNTER_STATUS (JS_COMC_204C_TX_BASE + 0x374) +//#define JS_COMC_204C_TX_TAILBITS (JS_COMC_204C_TX_BASE + 0x058) +#define JS_COMC_204C_TX_LINKTEST_CUSTOM_DATA (JS_COMC_204C_TX_BASE + 0x05C) +#define JS_COMC_204C_TX_LINKTEST_CUSTOM_ENABLE (JS_COMC_204C_TX_BASE + 0x060) +#define JS_COMC_204C_TX_FEATURE_DISABLE (JS_COMC_204C_TX_BASE + 0x120) +#define JS_COMC_204C_TX_CORE_INTERRUPT_MASK (JS_COMC_204C_TX_BASE + 0x124) +#define JS_COMC_204C_TX_CORE_INTERRUPT_STATUS (JS_COMC_204C_TX_BASE + 0x128) +#define JS_COMC_204C_TX_ILAS_DETAILS (JS_COMC_204C_TX_BASE + 0x12C) +#define JS_COMC_204C_TX_CLK_RATIO (JS_COMC_204C_TX_BASE + 0x13C) +#define JS_COMC_204C_TX_FIRST_SYMBOL_DISP (JS_COMC_204C_TX_BASE + 0x140) +#define JS_COMC_204C_TX_TL_LATENCY (JS_COMC_204C_TX_BASE + 0x2C0) +#define JS_COMC_204C_TX_LMFC_LEMC_DELAY (JS_COMC_204C_TX_BASE + 0x2E0) +#define JS_COMC_204C_TX_SYSREF_CONFIG (JS_COMC_204C_TX_BASE + 0x2E4) +#define JS_COMC_204C_TX_SAMPLE_REQ (JS_COMC_204C_TX_BASE + 0x3E0) + +#define JS_RX0_PIN_CTRL_REG (JS_RX0_TMR_BASE + 4*0x00) +#define JS_RX0_IO_CTRL_REG (JS_RX0_TMR_BASE + 4*0x01) +#define JS_RX0_TMR_INTC_REG (JS_RX0_TMR_BASE + 4*0x02) +#define JS_RX0_TMR_SCR_CTRL_REG (JS_RX0_TMR_BASE + 4*0x03) +#define JS_RX0_TMR_CTRL_REG (JS_RX0_TMR_BASE + 4*0x04) +#define JS_RX0_TMR_RX_SCRL_0_REG (JS_RX0_TMR_BASE + 4*0x05) +#define JS_RX0_TMR_RX_SCRH_0_REG (JS_RX0_TMR_BASE + 4*0x06) +#define JS_RX0_TMR_TX_SCRL_0_REG (JS_RX0_TMR_BASE + 4*0x07) +#define JS_RX0_TMR_TX_SCRH_0_REG (JS_RX0_TMR_BASE + 4*0x08) +#define JS_RX0_TMR_RX_SCRL_1_REG (JS_RX0_TMR_BASE + 4*0x09) +#define JS_RX0_TMR_RX_SCRH_1_REG (JS_RX0_TMR_BASE + 4*0x0A) +#define JS_RX0_TMR_TX_SCRL_1_REG (JS_RX0_TMR_BASE + 4*0x0B) +#define JS_RX0_TMR_TX_SCRH_1_REG (JS_RX0_TMR_BASE + 4*0x0C) +#define JS_RX0_TMR_TEVENT0_REG (JS_RX0_TMR_BASE + 4*0x10) +#define JS_RX0_TMR_TEVENT1_REG (JS_RX0_TMR_BASE + 4*0x11) +#define JS_RX0_TMR_TEVENT2_REG (JS_RX0_TMR_BASE + 4*0x12) +#define JS_RX0_TMR_TSCR_TRG_REG (JS_RX0_TMR_BASE + 4*0x13) +#define JS_RX0_TMR_TWREQ0_REG (JS_RX0_TMR_BASE + 4*0x14) +#define JS_RX0_TMR_TWREQ1_REG (JS_RX0_TMR_BASE + 4*0x15) +#define JS_RX0_TMR_TWREQ2_REG (JS_RX0_TMR_BASE + 4*0x16) +#define JS_RX0_TMR_TINTE00_REG (JS_RX0_TMR_BASE + 4*0x17) +#define JS_RX0_TMR_TINTF00_REG (JS_RX0_TMR_BASE + 4*0x18) +#define JS_RX0_TMR_TINTE01_REG (JS_RX0_TMR_BASE + 4*0x19) +#define JS_RX0_TMR_TINTF01_REG (JS_RX0_TMR_BASE + 4*0x1A) +#define JS_RX0_TMR_TINTE02_REG (JS_RX0_TMR_BASE + 4*0x1B) +#define JS_RX0_TMR_TINTF02_REG (JS_RX0_TMR_BASE + 4*0x1C) +#define JS_RX0_TMR_TINTE10_REG (JS_RX0_TMR_BASE + 4*0x1D) +#define JS_RX0_TMR_TINTF10_REG (JS_RX0_TMR_BASE + 4*0x1E) +#define JS_RX0_TMR_TINTE11_REG (JS_RX0_TMR_BASE + 4*0x1F) +#define JS_RX0_TMR_TINTF11_REG (JS_RX0_TMR_BASE + 4*0x20) +#define JS_RX0_TMR_TINTE12_REG (JS_RX0_TMR_BASE + 4*0x21) +#define JS_RX0_TMR_TINTF12_REG (JS_RX0_TMR_BASE + 4*0x22) +#define JS_RX0_TMR_TINTE20_REG (JS_RX0_TMR_BASE + 4*0x23) +#define JS_RX0_TMR_TINTF20_REG (JS_RX0_TMR_BASE + 4*0x24) +#define JS_RX0_TMR_TINTE21_REG (JS_RX0_TMR_BASE + 4*0x25) +#define JS_RX0_TMR_TINTF21_REG (JS_RX0_TMR_BASE + 4*0x26) +#define JS_RX0_TMR_TINTE22_REG (JS_RX0_TMR_BASE + 4*0x27) +#define JS_RX0_TMR_TINTF22_REG (JS_RX0_TMR_BASE + 4*0x28) +#define JS_RX0_TMR_TINTE30_REG (JS_RX0_TMR_BASE + 4*0x29) +#define JS_RX0_TMR_TINTF30_REG (JS_RX0_TMR_BASE + 4*0x2A) +#define JS_RX0_TMR_TINTE31_REG (JS_RX0_TMR_BASE + 4*0x2B) +#define JS_RX0_TMR_TINTF31_REG (JS_RX0_TMR_BASE + 4*0x2C) +#define JS_RX0_TMR_TINTE32_REG (JS_RX0_TMR_BASE + 4*0x2D) +#define JS_RX0_TMR_TINTF32_REG (JS_RX0_TMR_BASE + 4*0x2E) +#define JS_RX0_TMR_TINTE40_REG (JS_RX0_TMR_BASE + 4*0x2F) +#define JS_RX0_TMR_TINTF40_REG (JS_RX0_TMR_BASE + 4*0x30) +#define JS_RX0_TMR_TINTE41_REG (JS_RX0_TMR_BASE + 4*0x31) +#define JS_RX0_TMR_TINTF41_REG (JS_RX0_TMR_BASE + 4*0x32) +#define JS_RX0_TMR_TINTE42_REG (JS_RX0_TMR_BASE + 4*0x33) +#define JS_RX0_TMR_TINTF42_REG (JS_RX0_TMR_BASE + 4*0x34) +#define JS_RX0_TMR_TINTE50_REG (JS_RX0_TMR_BASE + 4*0x35) +#define JS_RX0_TMR_TINTF50_REG (JS_RX0_TMR_BASE + 4*0x36) +#define JS_RX0_TMR_TINTE51_REG (JS_RX0_TMR_BASE + 4*0x37) +#define JS_RX0_TMR_TINTF51_REG (JS_RX0_TMR_BASE + 4*0x38) +#define JS_RX0_TMR_TINTE52_REG (JS_RX0_TMR_BASE + 4*0x39) +#define JS_RX0_TMR_TINTF52_REG (JS_RX0_TMR_BASE + 4*0x3A) +#define JS_RX0_TMR_TINTE60_REG (JS_RX0_TMR_BASE + 4*0x3B) +#define JS_RX0_TMR_TINTF60_REG (JS_RX0_TMR_BASE + 4*0x3C) +#define JS_RX0_TMR_TINTE61_REG (JS_RX0_TMR_BASE + 4*0x3D) +#define JS_RX0_TMR_TINTF61_REG (JS_RX0_TMR_BASE + 4*0x3E) +#define JS_RX0_TMR_TINTE62_REG (JS_RX0_TMR_BASE + 4*0x3F) +#define JS_RX0_TMR_TINTF62_REG (JS_RX0_TMR_BASE + 4*0x40) +#define JS_RX0_TMR_TINTE70_REG (JS_RX0_TMR_BASE + 4*0x41) +#define JS_RX0_TMR_TINTF70_REG (JS_RX0_TMR_BASE + 4*0x42) +#define JS_RX0_TMR_TINTE71_REG (JS_RX0_TMR_BASE + 4*0x43) +#define JS_RX0_TMR_TINTF71_REG (JS_RX0_TMR_BASE + 4*0x44) +#define JS_RX0_TMR_TINTE72_REG (JS_RX0_TMR_BASE + 4*0x45) +#define JS_RX0_TMR_TINTF72_REG (JS_RX0_TMR_BASE + 4*0x46) +#define JS_RX0_TMR_TINTE80_REG (JS_RX0_TMR_BASE + 4*0x47) +#define JS_RX0_TMR_TINTF80_REG (JS_RX0_TMR_BASE + 4*0x48) +#define JS_RX0_TMR_TINTE81_REG (JS_RX0_TMR_BASE + 4*0x49) +#define JS_RX0_TMR_TINTF81_REG (JS_RX0_TMR_BASE + 4*0x4A) +#define JS_RX0_TMR_TINTE82_REG (JS_RX0_TMR_BASE + 4*0x4B) +#define JS_RX0_TMR_TINTF82_REG (JS_RX0_TMR_BASE + 4*0x4C) +#define JS_RX0_TMR_TINTE90_REG (JS_RX0_TMR_BASE + 4*0x4D) +#define JS_RX0_TMR_TINTF90_REG (JS_RX0_TMR_BASE + 4*0x4E) +#define JS_RX0_TMR_TINTE91_REG (JS_RX0_TMR_BASE + 4*0x4F) +#define JS_RX0_TMR_TINTF91_REG (JS_RX0_TMR_BASE + 4*0x50) +#define JS_RX0_TMR_TINTE92_REG (JS_RX0_TMR_BASE + 4*0x51) +#define JS_RX0_TMR_TINTF92_REG (JS_RX0_TMR_BASE + 4*0x52) +#define JS_RX0_TMR_TINTEA0_REG (JS_RX0_TMR_BASE + 4*0x53) +#define JS_RX0_TMR_TINTFA0_REG (JS_RX0_TMR_BASE + 4*0x54) +#define JS_RX0_TMR_TINTEA1_REG (JS_RX0_TMR_BASE + 4*0x55) +#define JS_RX0_TMR_TINTFA1_REG (JS_RX0_TMR_BASE + 4*0x56) +#define JS_RX0_TMR_TINTEA2_REG (JS_RX0_TMR_BASE + 4*0x57) +#define JS_RX0_TMR_TINTFA2_REG (JS_RX0_TMR_BASE + 4*0x58) +#define JS_RX0_TMR_TINTEB0_REG (JS_RX0_TMR_BASE + 4*0x59) +#define JS_RX0_TMR_TINTFB0_REG (JS_RX0_TMR_BASE + 4*0x5A) +#define JS_RX0_TMR_TINTEB1_REG (JS_RX0_TMR_BASE + 4*0x5B) +#define JS_RX0_TMR_TINTFB1_REG (JS_RX0_TMR_BASE + 4*0x5C) +#define JS_RX0_TMR_TINTEB2_REG (JS_RX0_TMR_BASE + 4*0x5D) +#define JS_RX0_TMR_TINTFB2_REG (JS_RX0_TMR_BASE + 4*0x5E) +#define JS_RX0_TMR_CEVENT_REG (JS_RX0_TMR_BASE + 4*0x5F) +#define JS_RX0_TMR_CMSK_REG (JS_RX0_TMR_BASE + 4*0x60) +#define JS_RX0_TMR_CINTE0_REG (JS_RX0_TMR_BASE + 4*0x61) +#define JS_RX0_TMR_CINTF0_REG (JS_RX0_TMR_BASE + 4*0x62) +#define JS_RX0_TMR_CINTE1_REG (JS_RX0_TMR_BASE + 4*0x63) +#define JS_RX0_TMR_CINTF1_REG (JS_RX0_TMR_BASE + 4*0x64) +#define JS_RX0_TMR_CINTE2_REG (JS_RX0_TMR_BASE + 4*0x65) +#define JS_RX0_TMR_CINTF2_REG (JS_RX0_TMR_BASE + 4*0x66) +#define JS_RX0_TMR_CINTE3_REG (JS_RX0_TMR_BASE + 4*0x67) +#define JS_RX0_TMR_CINTF3_REG (JS_RX0_TMR_BASE + 4*0x68) +#define JS_RX0_TMR_CINTE4_REG (JS_RX0_TMR_BASE + 4*0x69) +#define JS_RX0_TMR_CINTF4_REG (JS_RX0_TMR_BASE + 4*0x6A) +#define JS_RX0_TMR_CINTE5_REG (JS_RX0_TMR_BASE + 4*0x6B) +#define JS_RX0_TMR_CINTF5_REG (JS_RX0_TMR_BASE + 4*0x6C) +#define JS_RX0_TMR_CINTE6_REG (JS_RX0_TMR_BASE + 4*0x6D) +#define JS_RX0_TMR_CINTF6_REG (JS_RX0_TMR_BASE + 4*0x6E) +#define JS_RX0_TMR_CINTE7_REG (JS_RX0_TMR_BASE + 4*0x6F) +#define JS_RX0_TMR_CINTF7_REG (JS_RX0_TMR_BASE + 4*0x70) +#define JS_RX0_TMR_CINTE8_REG (JS_RX0_TMR_BASE + 4*0x71) +#define JS_RX0_TMR_CINTF8_REG (JS_RX0_TMR_BASE + 4*0x72) +#define JS_RX0_TMR_CINTE9_REG (JS_RX0_TMR_BASE + 4*0x73) +#define JS_RX0_TMR_CINTF9_REG (JS_RX0_TMR_BASE + 4*0x74) +#define JS_RX0_TMR_CINTEA_REG (JS_RX0_TMR_BASE + 4*0x75) +#define JS_RX0_TMR_CINTFA_REG (JS_RX0_TMR_BASE + 4*0x76) +#define JS_RX0_TMR_CINTEB_REG (JS_RX0_TMR_BASE + 4*0x77) +#define JS_RX0_TMR_CINTFB_REG (JS_RX0_TMR_BASE + 4*0x78) +#define JS_RX0_TMR_OVFL_REG (JS_RX0_TMR_BASE + 4*0x79) +#define JS_RX0_TMR_OVFH_REG (JS_RX0_TMR_BASE + 4*0x7A) +#define JS_RX0_TMR_RXEN0_0L_REG (JS_RX0_TMR_BASE + 4*0x7B) +#define JS_RX0_TMR_RXEN0_0H_REG (JS_RX0_TMR_BASE + 4*0x7C) +#define JS_RX0_TMR_RXEN0_1L_REG (JS_RX0_TMR_BASE + 4*0x7D) +#define JS_RX0_TMR_RXEN0_1H_REG (JS_RX0_TMR_BASE + 4*0x7E) +#define JS_RX0_TMR_TXEN0_0L_REG (JS_RX0_TMR_BASE + 4*0x7F) +#define JS_RX0_TMR_TXEN0_0H_REG (JS_RX0_TMR_BASE + 4*0x80) +#define JS_RX0_TMR_TXEN0_1L_REG (JS_RX0_TMR_BASE + 4*0x81) +#define JS_RX0_TMR_TXEN0_1H_REG (JS_RX0_TMR_BASE + 4*0x82) +#define JS_RX0_TMR_RXEN1_0L_REG (JS_RX0_TMR_BASE + 4*0x83) +#define JS_RX0_TMR_RXEN1_0H_REG (JS_RX0_TMR_BASE + 4*0x84) +#define JS_RX0_TMR_RXEN1_1L_REG (JS_RX0_TMR_BASE + 4*0x85) +#define JS_RX0_TMR_RXEN1_1H_REG (JS_RX0_TMR_BASE + 4*0x86) +#define JS_RX0_TMR_TXEN1_0L_REG (JS_RX0_TMR_BASE + 4*0x87) +#define JS_RX0_TMR_TXEN1_0H_REG (JS_RX0_TMR_BASE + 4*0x88) +#define JS_RX0_TMR_TXEN1_1L_REG (JS_RX0_TMR_BASE + 4*0x89) +#define JS_RX0_TMR_TXEN1_1H_REG (JS_RX0_TMR_BASE + 4*0x8A) +#define JS_RX0_TMR_RXEN2CSU0L_REG (JS_RX0_TMR_BASE + 4*0x8B) +#define JS_RX0_TMR_RXEN2CSU0H_REG (JS_RX0_TMR_BASE + 4*0x8C) +#define JS_RX0_TMR_RXEN2CSU1L_REG (JS_RX0_TMR_BASE + 4*0x8D) +#define JS_RX0_TMR_RXEN2CSU1H_REG (JS_RX0_TMR_BASE + 4*0x8E) +#define JS_RX0_TMR_TXEN2CSU0L_REG (JS_RX0_TMR_BASE + 4*0x8F) +#define JS_RX0_TMR_TXEN2CSU0H_REG (JS_RX0_TMR_BASE + 4*0x90) +#define JS_RX0_TMR_TXEN2CSU1L_REG (JS_RX0_TMR_BASE + 4*0x91) +#define JS_RX0_TMR_TXEN2CSU1H_REG (JS_RX0_TMR_BASE + 4*0x92) +#define JS_RX0_TMR_SCRATH0L_REG (JS_RX0_TMR_BASE + 4*0x93) +#define JS_RX0_TMR_SCRATH0H_REG (JS_RX0_TMR_BASE + 4*0x94) +#define JS_RX0_TMR_SCRATH1L_REG (JS_RX0_TMR_BASE + 4*0x95) +#define JS_RX0_TMR_SCRATH1H_REG (JS_RX0_TMR_BASE + 4*0x96) +#define JS_RX0_TMR_RX_SCRL_REG (JS_RX0_TMR_BASE + 4*0x97) +#define JS_RX0_TMR_RX_SCRH_REG (JS_RX0_TMR_BASE + 4*0x98) +#define JS_RX0_TMR_TX_SCRL_REG (JS_RX0_TMR_BASE + 4*0x99) +#define JS_RX0_TMR_TX_SCRH_REG (JS_RX0_TMR_BASE + 4*0x9A) +#define JS_RX0_TMR_1PPSL_REG (JS_RX0_TMR_BASE + 4*0x9B) +#define JS_RX0_TMR_1PPSH_REG (JS_RX0_TMR_BASE + 4*0x9C) +#define JS_RX0_TMR_CPRI_10MS_CTRL (JS_RX0_TMR_BASE + 4*0x9D) +#define JS_RX0_TMR_CPRI_ADJ_L (JS_RX0_TMR_BASE + 4*0x9E) +#define JS_RX0_TMR_CPRI_ADJ_H (JS_RX0_TMR_BASE + 4*0x9F) +#define JS_RX0_TMR_CPRI_10MS_CLR (JS_RX0_TMR_BASE + 4*0xA0) + +#define JS_RX0_TMR_RX_SOF0_SCR_L_REG (JS_RX0_TMR_BASE + 4*0xA1) +#define JS_RX0_TMR_RX_SOF0_SCR_H_REG (JS_RX0_TMR_BASE + 4*0xA2) +#define JS_RX0_TMR_RX_SOF1_SCR_L_REG (JS_RX0_TMR_BASE + 4*0xA3) +#define JS_RX0_TMR_RX_SOF1_SCR_H_REG (JS_RX0_TMR_BASE + 4*0xA4) +#define JS_RX0_TMR_RX_SOF2_SCR_L_REG (JS_RX0_TMR_BASE + 4*0xA5) +#define JS_RX0_TMR_RX_SOF2_SCR_H_REG (JS_RX0_TMR_BASE + 4*0xA6) +#define JS_RX0_TMR_RX_SOF3_SCR_L_REG (JS_RX0_TMR_BASE + 4*0xA7) +#define JS_RX0_TMR_RX_SOF3_SCR_H_REG (JS_RX0_TMR_BASE + 4*0xA8) +#define JS_RX0_TMR_RX_EOF0_SCR_L_REG (JS_RX0_TMR_BASE + 4*0xA9) +#define JS_RX0_TMR_RX_EOF0_SCR_H_REG (JS_RX0_TMR_BASE + 4*0xAA) +#define JS_RX0_TMR_RX_EOF1_SCR_L_REG (JS_RX0_TMR_BASE + 4*0xAB) +#define JS_RX0_TMR_RX_EOF1_SCR_H_REG (JS_RX0_TMR_BASE + 4*0xAC) +#define JS_RX0_TMR_RX_EOF2_SCR_L_REG (JS_RX0_TMR_BASE + 4*0xAD) +#define JS_RX0_TMR_RX_EOF2_SCR_H_REG (JS_RX0_TMR_BASE + 4*0xAE) +#define JS_RX0_TMR_RX_EOF3_SCR_L_REG (JS_RX0_TMR_BASE + 4*0xAF) +#define JS_RX0_TMR_RX_EOF3_SCR_H_REG (JS_RX0_TMR_BASE + 4*0xB0) +#define JS_RX0_TMR_RX_SOF_EOF_SCR_EN (JS_RX0_TMR_BASE + 4*0xB1) + + + + +#define JS_RX0_TMR_TnL_REG0 (JS_RX0_TMR_BASE + 4*0x100+8*0x0) +#define JS_RX0_TMR_TnL_REG1 (JS_RX0_TMR_BASE + 4*0x100+8*0x1) +#define JS_RX0_TMR_TnL_REG2 (JS_RX0_TMR_BASE + 4*0x100+8*0x2) +#define JS_RX0_TMR_TnL_REG3 (JS_RX0_TMR_BASE + 4*0x100+8*0x3) +#define JS_RX0_TMR_TnL_REG4 (JS_RX0_TMR_BASE + 4*0x100+8*0x4) +#define JS_RX0_TMR_TnL_REG5 (JS_RX0_TMR_BASE + 4*0x100+8*0x5) +#define JS_RX0_TMR_TnL_REG6 (JS_RX0_TMR_BASE + 4*0x100+8*0x6) +#define JS_RX0_TMR_TnL_REG7 (JS_RX0_TMR_BASE + 4*0x100+8*0x7) +#define JS_RX0_TMR_TnL_REG8 (JS_RX0_TMR_BASE + 4*0x100+8*0x8) +#define JS_RX0_TMR_TnL_REG9 (JS_RX0_TMR_BASE + 4*0x100+8*0x9) +#define JS_RX0_TMR_TnL_REG10 (JS_RX0_TMR_BASE + 4*0x100+8*0xa) +#define JS_RX0_TMR_TnL_REG11 (JS_RX0_TMR_BASE + 4*0x100+8*0xb) +#define JS_RX0_TMR_TnL_REG12 (JS_RX0_TMR_BASE + 4*0x100+8*0xc) +#define JS_RX0_TMR_TnL_REG13 (JS_RX0_TMR_BASE + 4*0x100+8*0xd) +#define JS_RX0_TMR_TnL_REG14 (JS_RX0_TMR_BASE + 4*0x100+8*0xe) +#define JS_RX0_TMR_TnL_REG15 (JS_RX0_TMR_BASE + 4*0x100+8*0xf) +#define JS_RX0_TMR_TnL_REG16 (JS_RX0_TMR_BASE + 4*0x100+8*0x10) +#define JS_RX0_TMR_TnL_REG17 (JS_RX0_TMR_BASE + 4*0x100+8*0x11) +#define JS_RX0_TMR_TnL_REG18 (JS_RX0_TMR_BASE + 4*0x100+8*0x12) +#define JS_RX0_TMR_TnL_REG19 (JS_RX0_TMR_BASE + 4*0x100+8*0x13) +#define JS_RX0_TMR_TnL_REG20 (JS_RX0_TMR_BASE + 4*0x100+8*0x14) +#define JS_RX0_TMR_TnL_REG21 (JS_RX0_TMR_BASE + 4*0x100+8*0x15) +#define JS_RX0_TMR_TnL_REG22 (JS_RX0_TMR_BASE + 4*0x100+8*0x16) +#define JS_RX0_TMR_TnL_REG23 (JS_RX0_TMR_BASE + 4*0x100+8*0x17) +#define JS_RX0_TMR_TnL_REG24 (JS_RX0_TMR_BASE + 4*0x100+8*0x18) +#define JS_RX0_TMR_TnL_REG25 (JS_RX0_TMR_BASE + 4*0x100+8*0x19) +#define JS_RX0_TMR_TnL_REG26 (JS_RX0_TMR_BASE + 4*0x100+8*0x1a) +#define JS_RX0_TMR_TnL_REG27 (JS_RX0_TMR_BASE + 4*0x100+8*0x1b) +#define JS_RX0_TMR_TnL_REG28 (JS_RX0_TMR_BASE + 4*0x100+8*0x1c) +#define JS_RX0_TMR_TnL_REG29 (JS_RX0_TMR_BASE + 4*0x100+8*0x1d) +#define JS_RX0_TMR_TnL_REG30 (JS_RX0_TMR_BASE + 4*0x100+8*0x1e) +#define JS_RX0_TMR_TnL_REG31 (JS_RX0_TMR_BASE + 4*0x100+8*0x1f) +#define JS_RX0_TMR_TnL_REG32 (JS_RX0_TMR_BASE + 4*0x100+8*0x20) +#define JS_RX0_TMR_TnL_REG33 (JS_RX0_TMR_BASE + 4*0x100+8*0x21) +#define JS_RX0_TMR_TnL_REG34 (JS_RX0_TMR_BASE + 4*0x100+8*0x22) +#define JS_RX0_TMR_TnL_REG35 (JS_RX0_TMR_BASE + 4*0x100+8*0x23) +#define JS_RX0_TMR_TnL_REG36 (JS_RX0_TMR_BASE + 4*0x100+8*0x24) +#define JS_RX0_TMR_TnL_REG37 (JS_RX0_TMR_BASE + 4*0x100+8*0x25) +#define JS_RX0_TMR_TnL_REG38 (JS_RX0_TMR_BASE + 4*0x100+8*0x26) +#define JS_RX0_TMR_TnL_REG39 (JS_RX0_TMR_BASE + 4*0x100+8*0x27) +#define JS_RX0_TMR_TnL_REG40 (JS_RX0_TMR_BASE + 4*0x100+8*0x28) +#define JS_RX0_TMR_TnL_REG41 (JS_RX0_TMR_BASE + 4*0x100+8*0x29) +#define JS_RX0_TMR_TnL_REG42 (JS_RX0_TMR_BASE + 4*0x100+8*0x2a) +#define JS_RX0_TMR_TnL_REG43 (JS_RX0_TMR_BASE + 4*0x100+8*0x2b) +#define JS_RX0_TMR_TnL_REG44 (JS_RX0_TMR_BASE + 4*0x100+8*0x2c) +#define JS_RX0_TMR_TnL_REG45 (JS_RX0_TMR_BASE + 4*0x100+8*0x2d) +#define JS_RX0_TMR_TnL_REG46 (JS_RX0_TMR_BASE + 4*0x100+8*0x2e) +#define JS_RX0_TMR_TnL_REG47 (JS_RX0_TMR_BASE + 4*0x100+8*0x2f) +#define JS_RX0_TMR_TnL_REG48 (JS_RX0_TMR_BASE + 4*0x100+8*0x30) +#define JS_RX0_TMR_TnL_REG49 (JS_RX0_TMR_BASE + 4*0x100+8*0x31) +#define JS_RX0_TMR_TnL_REG50 (JS_RX0_TMR_BASE + 4*0x100+8*0x32) +#define JS_RX0_TMR_TnL_REG51 (JS_RX0_TMR_BASE + 4*0x100+8*0x33) +#define JS_RX0_TMR_TnL_REG52 (JS_RX0_TMR_BASE + 4*0x100+8*0x34) +#define JS_RX0_TMR_TnL_REG53 (JS_RX0_TMR_BASE + 4*0x100+8*0x35) +#define JS_RX0_TMR_TnL_REG54 (JS_RX0_TMR_BASE + 4*0x100+8*0x36) +#define JS_RX0_TMR_TnL_REG55 (JS_RX0_TMR_BASE + 4*0x100+8*0x37) +#define JS_RX0_TMR_TnL_REG56 (JS_RX0_TMR_BASE + 4*0x100+8*0x38) +#define JS_RX0_TMR_TnL_REG57 (JS_RX0_TMR_BASE + 4*0x100+8*0x39) +#define JS_RX0_TMR_TnL_REG58 (JS_RX0_TMR_BASE + 4*0x100+8*0x3a) +#define JS_RX0_TMR_TnL_REG59 (JS_RX0_TMR_BASE + 4*0x100+8*0x3b) +#define JS_RX0_TMR_TnL_REG60 (JS_RX0_TMR_BASE + 4*0x100+8*0x3c) +#define JS_RX0_TMR_TnL_REG61 (JS_RX0_TMR_BASE + 4*0x100+8*0x3d) +#define JS_RX0_TMR_TnL_REG62 (JS_RX0_TMR_BASE + 4*0x100+8*0x3e) +#define JS_RX0_TMR_TnL_REG63 (JS_RX0_TMR_BASE + 4*0x100+8*0x3f) +#define JS_RX0_TMR_TnL_REG64 (JS_RX0_TMR_BASE + 4*0x100+8*0x40) +#define JS_RX0_TMR_TnL_REG65 (JS_RX0_TMR_BASE + 4*0x100+8*0x41) +#define JS_RX0_TMR_TnL_REG66 (JS_RX0_TMR_BASE + 4*0x100+8*0x42) +#define JS_RX0_TMR_TnL_REG67 (JS_RX0_TMR_BASE + 4*0x100+8*0x43) +#define JS_RX0_TMR_TnL_REG68 (JS_RX0_TMR_BASE + 4*0x100+8*0x44) +#define JS_RX0_TMR_TnL_REG69 (JS_RX0_TMR_BASE + 4*0x100+8*0x45) +#define JS_RX0_TMR_TnL_REG70 (JS_RX0_TMR_BASE + 4*0x100+8*0x46) +#define JS_RX0_TMR_TnL_REG71 (JS_RX0_TMR_BASE + 4*0x100+8*0x47) +#define JS_RX0_TMR_TnL_REG72 (JS_RX0_TMR_BASE + 4*0x100+8*0x48) +#define JS_RX0_TMR_TnL_REG73 (JS_RX0_TMR_BASE + 4*0x100+8*0x49) +#define JS_RX0_TMR_TnL_REG74 (JS_RX0_TMR_BASE + 4*0x100+8*0x4a) +#define JS_RX0_TMR_TnL_REG75 (JS_RX0_TMR_BASE + 4*0x100+8*0x4b) +#define JS_RX0_TMR_TnL_REG76 (JS_RX0_TMR_BASE + 4*0x100+8*0x4c) +#define JS_RX0_TMR_TnL_REG77 (JS_RX0_TMR_BASE + 4*0x100+8*0x4d) +#define JS_RX0_TMR_TnL_REG78 (JS_RX0_TMR_BASE + 4*0x100+8*0x4e) +#define JS_RX0_TMR_TnL_REG79 (JS_RX0_TMR_BASE + 4*0x100+8*0x4f) +#define JS_RX0_TMR_TnL_REG80 (JS_RX0_TMR_BASE + 4*0x100+8*0x50) +#define JS_RX0_TMR_TnL_REG81 (JS_RX0_TMR_BASE + 4*0x100+8*0x51) +#define JS_RX0_TMR_TnL_REG82 (JS_RX0_TMR_BASE + 4*0x100+8*0x52) +#define JS_RX0_TMR_TnL_REG83 (JS_RX0_TMR_BASE + 4*0x100+8*0x53) +#define JS_RX0_TMR_TnL_REG84 (JS_RX0_TMR_BASE + 4*0x100+8*0x54) +#define JS_RX0_TMR_TnL_REG85 (JS_RX0_TMR_BASE + 4*0x100+8*0x55) +#define JS_RX0_TMR_TnL_REG86 (JS_RX0_TMR_BASE + 4*0x100+8*0x56) +#define JS_RX0_TMR_TnL_REG87 (JS_RX0_TMR_BASE + 4*0x100+8*0x57) +#define JS_RX0_TMR_TnL_REG88 (JS_RX0_TMR_BASE + 4*0x100+8*0x58) +#define JS_RX0_TMR_TnL_REG89 (JS_RX0_TMR_BASE + 4*0x100+8*0x59) +#define JS_RX0_TMR_TnL_REG90 (JS_RX0_TMR_BASE + 4*0x100+8*0x5a) +#define JS_RX0_TMR_TnL_REG91 (JS_RX0_TMR_BASE + 4*0x100+8*0x5b) +#define JS_RX0_TMR_TnL_REG92 (JS_RX0_TMR_BASE + 4*0x100+8*0x5c) +#define JS_RX0_TMR_TnL_REG93 (JS_RX0_TMR_BASE + 4*0x100+8*0x5d) +#define JS_RX0_TMR_TnL_REG94 (JS_RX0_TMR_BASE + 4*0x100+8*0x5e) +#define JS_RX0_TMR_TnL_REG95 (JS_RX0_TMR_BASE + 4*0x100+8*0x5f) + + + +#define JS_RX0_TMR_TnH_REG0 (JS_RX0_TMR_BASE + 4*0x100+8*0x0 + 0x4) +#define JS_RX0_TMR_TnH_REG1 (JS_RX0_TMR_BASE + 4*0x100+8*0x1 + 0x4) +#define JS_RX0_TMR_TnH_REG2 (JS_RX0_TMR_BASE + 4*0x100+8*0x2 + 0x4) +#define JS_RX0_TMR_TnH_REG3 (JS_RX0_TMR_BASE + 4*0x100+8*0x3 + 0x4) +#define JS_RX0_TMR_TnH_REG4 (JS_RX0_TMR_BASE + 4*0x100+8*0x4 + 0x4) +#define JS_RX0_TMR_TnH_REG5 (JS_RX0_TMR_BASE + 4*0x100+8*0x5 + 0x4) +#define JS_RX0_TMR_TnH_REG6 (JS_RX0_TMR_BASE + 4*0x100+8*0x6 + 0x4) +#define JS_RX0_TMR_TnH_REG7 (JS_RX0_TMR_BASE + 4*0x100+8*0x7 + 0x4) +#define JS_RX0_TMR_TnH_REG8 (JS_RX0_TMR_BASE + 4*0x100+8*0x8 + 0x4) +#define JS_RX0_TMR_TnH_REG9 (JS_RX0_TMR_BASE + 4*0x100+8*0x9 + 0x4) +#define JS_RX0_TMR_TnH_REG10 (JS_RX0_TMR_BASE + 4*0x100+8*0xa + 0x4) +#define JS_RX0_TMR_TnH_REG11 (JS_RX0_TMR_BASE + 4*0x100+8*0xb + 0x4) +#define JS_RX0_TMR_TnH_REG12 (JS_RX0_TMR_BASE + 4*0x100+8*0xc + 0x4) +#define JS_RX0_TMR_TnH_REG13 (JS_RX0_TMR_BASE + 4*0x100+8*0xd + 0x4) +#define JS_RX0_TMR_TnH_REG14 (JS_RX0_TMR_BASE + 4*0x100+8*0xe + 0x4) +#define JS_RX0_TMR_TnH_REG15 (JS_RX0_TMR_BASE + 4*0x100+8*0xf + 0x4) +#define JS_RX0_TMR_TnH_REG16 (JS_RX0_TMR_BASE + 4*0x100+8*0x10 + 0x4) +#define JS_RX0_TMR_TnH_REG17 (JS_RX0_TMR_BASE + 4*0x100+8*0x11 + 0x4) +#define JS_RX0_TMR_TnH_REG18 (JS_RX0_TMR_BASE + 4*0x100+8*0x12 + 0x4) +#define JS_RX0_TMR_TnH_REG19 (JS_RX0_TMR_BASE + 4*0x100+8*0x13 + 0x4) +#define JS_RX0_TMR_TnH_REG20 (JS_RX0_TMR_BASE + 4*0x100+8*0x14 + 0x4) +#define JS_RX0_TMR_TnH_REG21 (JS_RX0_TMR_BASE + 4*0x100+8*0x15 + 0x4) +#define JS_RX0_TMR_TnH_REG22 (JS_RX0_TMR_BASE + 4*0x100+8*0x16 + 0x4) +#define JS_RX0_TMR_TnH_REG23 (JS_RX0_TMR_BASE + 4*0x100+8*0x17 + 0x4) +#define JS_RX0_TMR_TnH_REG24 (JS_RX0_TMR_BASE + 4*0x100+8*0x18 + 0x4) +#define JS_RX0_TMR_TnH_REG25 (JS_RX0_TMR_BASE + 4*0x100+8*0x19 + 0x4) +#define JS_RX0_TMR_TnH_REG26 (JS_RX0_TMR_BASE + 4*0x100+8*0x1a + 0x4) +#define JS_RX0_TMR_TnH_REG27 (JS_RX0_TMR_BASE + 4*0x100+8*0x1b + 0x4) +#define JS_RX0_TMR_TnH_REG28 (JS_RX0_TMR_BASE + 4*0x100+8*0x1c + 0x4) +#define JS_RX0_TMR_TnH_REG29 (JS_RX0_TMR_BASE + 4*0x100+8*0x1d + 0x4) +#define JS_RX0_TMR_TnH_REG30 (JS_RX0_TMR_BASE + 4*0x100+8*0x1e + 0x4) +#define JS_RX0_TMR_TnH_REG31 (JS_RX0_TMR_BASE + 4*0x100+8*0x1f + 0x4) +#define JS_RX0_TMR_TnH_REG32 (JS_RX0_TMR_BASE + 4*0x100+8*0x20 + 0x4) +#define JS_RX0_TMR_TnH_REG33 (JS_RX0_TMR_BASE + 4*0x100+8*0x21 + 0x4) +#define JS_RX0_TMR_TnH_REG34 (JS_RX0_TMR_BASE + 4*0x100+8*0x22 + 0x4) +#define JS_RX0_TMR_TnH_REG35 (JS_RX0_TMR_BASE + 4*0x100+8*0x23 + 0x4) +#define JS_RX0_TMR_TnH_REG36 (JS_RX0_TMR_BASE + 4*0x100+8*0x24 + 0x4) +#define JS_RX0_TMR_TnH_REG37 (JS_RX0_TMR_BASE + 4*0x100+8*0x25 + 0x4) +#define JS_RX0_TMR_TnH_REG38 (JS_RX0_TMR_BASE + 4*0x100+8*0x26 + 0x4) +#define JS_RX0_TMR_TnH_REG39 (JS_RX0_TMR_BASE + 4*0x100+8*0x27 + 0x4) +#define JS_RX0_TMR_TnH_REG40 (JS_RX0_TMR_BASE + 4*0x100+8*0x28 + 0x4) +#define JS_RX0_TMR_TnH_REG41 (JS_RX0_TMR_BASE + 4*0x100+8*0x29 + 0x4) +#define JS_RX0_TMR_TnH_REG42 (JS_RX0_TMR_BASE + 4*0x100+8*0x2a + 0x4) +#define JS_RX0_TMR_TnH_REG43 (JS_RX0_TMR_BASE + 4*0x100+8*0x2b + 0x4) +#define JS_RX0_TMR_TnH_REG44 (JS_RX0_TMR_BASE + 4*0x100+8*0x2c + 0x4) +#define JS_RX0_TMR_TnH_REG45 (JS_RX0_TMR_BASE + 4*0x100+8*0x2d + 0x4) +#define JS_RX0_TMR_TnH_REG46 (JS_RX0_TMR_BASE + 4*0x100+8*0x2e + 0x4) +#define JS_RX0_TMR_TnH_REG47 (JS_RX0_TMR_BASE + 4*0x100+8*0x2f + 0x4) +#define JS_RX0_TMR_TnH_REG48 (JS_RX0_TMR_BASE + 4*0x100+8*0x30 + 0x4) +#define JS_RX0_TMR_TnH_REG49 (JS_RX0_TMR_BASE + 4*0x100+8*0x31 + 0x4) +#define JS_RX0_TMR_TnH_REG50 (JS_RX0_TMR_BASE + 4*0x100+8*0x32 + 0x4) +#define JS_RX0_TMR_TnH_REG51 (JS_RX0_TMR_BASE + 4*0x100+8*0x33 + 0x4) +#define JS_RX0_TMR_TnH_REG52 (JS_RX0_TMR_BASE + 4*0x100+8*0x34 + 0x4) +#define JS_RX0_TMR_TnH_REG53 (JS_RX0_TMR_BASE + 4*0x100+8*0x35 + 0x4) +#define JS_RX0_TMR_TnH_REG54 (JS_RX0_TMR_BASE + 4*0x100+8*0x36 + 0x4) +#define JS_RX0_TMR_TnH_REG55 (JS_RX0_TMR_BASE + 4*0x100+8*0x37 + 0x4) +#define JS_RX0_TMR_TnH_REG56 (JS_RX0_TMR_BASE + 4*0x100+8*0x38 + 0x4) +#define JS_RX0_TMR_TnH_REG57 (JS_RX0_TMR_BASE + 4*0x100+8*0x39 + 0x4) +#define JS_RX0_TMR_TnH_REG58 (JS_RX0_TMR_BASE + 4*0x100+8*0x3a + 0x4) +#define JS_RX0_TMR_TnH_REG59 (JS_RX0_TMR_BASE + 4*0x100+8*0x3b + 0x4) +#define JS_RX0_TMR_TnH_REG60 (JS_RX0_TMR_BASE + 4*0x100+8*0x3c + 0x4) +#define JS_RX0_TMR_TnH_REG61 (JS_RX0_TMR_BASE + 4*0x100+8*0x3d + 0x4) +#define JS_RX0_TMR_TnH_REG62 (JS_RX0_TMR_BASE + 4*0x100+8*0x3e + 0x4) +#define JS_RX0_TMR_TnH_REG63 (JS_RX0_TMR_BASE + 4*0x100+8*0x3f + 0x4) +#define JS_RX0_TMR_TnH_REG64 (JS_RX0_TMR_BASE + 4*0x100+8*0x40 + 0x4) +#define JS_RX0_TMR_TnH_REG65 (JS_RX0_TMR_BASE + 4*0x100+8*0x41 + 0x4) +#define JS_RX0_TMR_TnH_REG66 (JS_RX0_TMR_BASE + 4*0x100+8*0x42 + 0x4) +#define JS_RX0_TMR_TnH_REG67 (JS_RX0_TMR_BASE + 4*0x100+8*0x43 + 0x4) +#define JS_RX0_TMR_TnH_REG68 (JS_RX0_TMR_BASE + 4*0x100+8*0x44 + 0x4) +#define JS_RX0_TMR_TnH_REG69 (JS_RX0_TMR_BASE + 4*0x100+8*0x45 + 0x4) +#define JS_RX0_TMR_TnH_REG70 (JS_RX0_TMR_BASE + 4*0x100+8*0x46 + 0x4) +#define JS_RX0_TMR_TnH_REG71 (JS_RX0_TMR_BASE + 4*0x100+8*0x47 + 0x4) +#define JS_RX0_TMR_TnH_REG72 (JS_RX0_TMR_BASE + 4*0x100+8*0x48 + 0x4) +#define JS_RX0_TMR_TnH_REG73 (JS_RX0_TMR_BASE + 4*0x100+8*0x49 + 0x4) +#define JS_RX0_TMR_TnH_REG74 (JS_RX0_TMR_BASE + 4*0x100+8*0x4a + 0x4) +#define JS_RX0_TMR_TnH_REG75 (JS_RX0_TMR_BASE + 4*0x100+8*0x4b + 0x4) +#define JS_RX0_TMR_TnH_REG76 (JS_RX0_TMR_BASE + 4*0x100+8*0x4c + 0x4) +#define JS_RX0_TMR_TnH_REG77 (JS_RX0_TMR_BASE + 4*0x100+8*0x4d + 0x4) +#define JS_RX0_TMR_TnH_REG78 (JS_RX0_TMR_BASE + 4*0x100+8*0x4e + 0x4) +#define JS_RX0_TMR_TnH_REG79 (JS_RX0_TMR_BASE + 4*0x100+8*0x4f + 0x4) +#define JS_RX0_TMR_TnH_REG80 (JS_RX0_TMR_BASE + 4*0x100+8*0x50 + 0x4) +#define JS_RX0_TMR_TnH_REG81 (JS_RX0_TMR_BASE + 4*0x100+8*0x51 + 0x4) +#define JS_RX0_TMR_TnH_REG82 (JS_RX0_TMR_BASE + 4*0x100+8*0x52 + 0x4) +#define JS_RX0_TMR_TnH_REG83 (JS_RX0_TMR_BASE + 4*0x100+8*0x53 + 0x4) +#define JS_RX0_TMR_TnH_REG84 (JS_RX0_TMR_BASE + 4*0x100+8*0x54 + 0x4) +#define JS_RX0_TMR_TnH_REG85 (JS_RX0_TMR_BASE + 4*0x100+8*0x55 + 0x4) +#define JS_RX0_TMR_TnH_REG86 (JS_RX0_TMR_BASE + 4*0x100+8*0x56 + 0x4) +#define JS_RX0_TMR_TnH_REG87 (JS_RX0_TMR_BASE + 4*0x100+8*0x57 + 0x4) +#define JS_RX0_TMR_TnH_REG88 (JS_RX0_TMR_BASE + 4*0x100+8*0x58 + 0x4) +#define JS_RX0_TMR_TnH_REG89 (JS_RX0_TMR_BASE + 4*0x100+8*0x59 + 0x4) +#define JS_RX0_TMR_TnH_REG90 (JS_RX0_TMR_BASE + 4*0x100+8*0x5a + 0x4) +#define JS_RX0_TMR_TnH_REG91 (JS_RX0_TMR_BASE + 4*0x100+8*0x5b + 0x4) +#define JS_RX0_TMR_TnH_REG92 (JS_RX0_TMR_BASE + 4*0x100+8*0x5c + 0x4) +#define JS_RX0_TMR_TnH_REG93 (JS_RX0_TMR_BASE + 4*0x100+8*0x5d + 0x4) +#define JS_RX0_TMR_TnH_REG94 (JS_RX0_TMR_BASE + 4*0x100+8*0x5e + 0x4) +#define JS_RX0_TMR_TnH_REG95 (JS_RX0_TMR_BASE + 4*0x100+8*0x5f + 0x4) + +#define JS_RX1_PIN_CTRL_REG (JS_RX1_TMR_BASE + 4*0x00) +#define JS_RX1_IO_CTRL_REG (JS_RX1_TMR_BASE + 4*0x01) +#define JS_RX1_TMR_INTC_REG (JS_RX1_TMR_BASE + 4*0x02) +#define JS_RX1_TMR_SCR_CTRL_REG (JS_RX1_TMR_BASE + 4*0x03) +#define JS_RX1_TMR_CTRL_REG (JS_RX1_TMR_BASE + 4*0x04) +#define JS_RX1_TMR_RX_SCRL_0_REG (JS_RX1_TMR_BASE + 4*0x05) +#define JS_RX1_TMR_RX_SCRH_0_REG (JS_RX1_TMR_BASE + 4*0x06) +#define JS_RX1_TMR_TX_SCRL_0_REG (JS_RX1_TMR_BASE + 4*0x07) +#define JS_RX1_TMR_TX_SCRH_0_REG (JS_RX1_TMR_BASE + 4*0x08) +#define JS_RX1_TMR_RX_SCRL_1_REG (JS_RX1_TMR_BASE + 4*0x09) +#define JS_RX1_TMR_RX_SCRH_1_REG (JS_RX1_TMR_BASE + 4*0x0A) +#define JS_RX1_TMR_TX_SCRL_1_REG (JS_RX1_TMR_BASE + 4*0x0B) +#define JS_RX1_TMR_TX_SCRH_1_REG (JS_RX1_TMR_BASE + 4*0x0C) +#define JS_RX1_TMR_TEVENT0_REG (JS_RX1_TMR_BASE + 4*0x10) +#define JS_RX1_TMR_TEVENT1_REG (JS_RX1_TMR_BASE + 4*0x11) +#define JS_RX1_TMR_TEVENT2_REG (JS_RX1_TMR_BASE + 4*0x12) +#define JS_RX1_TMR_TSCR_TRG_REG (JS_RX1_TMR_BASE + 4*0x13) +#define JS_RX1_TMR_TWREQ0_REG (JS_RX1_TMR_BASE + 4*0x14) +#define JS_RX1_TMR_TWREQ1_REG (JS_RX1_TMR_BASE + 4*0x15) +#define JS_RX1_TMR_TWREQ2_REG (JS_RX1_TMR_BASE + 4*0x16) +#define JS_RX1_TMR_TINTE00_REG (JS_RX1_TMR_BASE + 4*0x17) +#define JS_RX1_TMR_TINTF00_REG (JS_RX1_TMR_BASE + 4*0x18) +#define JS_RX1_TMR_TINTE01_REG (JS_RX1_TMR_BASE + 4*0x19) +#define JS_RX1_TMR_TINTF01_REG (JS_RX1_TMR_BASE + 4*0x1A) +#define JS_RX1_TMR_TINTE02_REG (JS_RX1_TMR_BASE + 4*0x1B) +#define JS_RX1_TMR_TINTF02_REG (JS_RX1_TMR_BASE + 4*0x1C) +#define JS_RX1_TMR_TINTE10_REG (JS_RX1_TMR_BASE + 4*0x1D) +#define JS_RX1_TMR_TINTF10_REG (JS_RX1_TMR_BASE + 4*0x1E) +#define JS_RX1_TMR_TINTE11_REG (JS_RX1_TMR_BASE + 4*0x1F) +#define JS_RX1_TMR_TINTF11_REG (JS_RX1_TMR_BASE + 4*0x20) +#define JS_RX1_TMR_TINTE12_REG (JS_RX1_TMR_BASE + 4*0x21) +#define JS_RX1_TMR_TINTF12_REG (JS_RX1_TMR_BASE + 4*0x22) +#define JS_RX1_TMR_TINTE20_REG (JS_RX1_TMR_BASE + 4*0x23) +#define JS_RX1_TMR_TINTF20_REG (JS_RX1_TMR_BASE + 4*0x24) +#define JS_RX1_TMR_TINTE21_REG (JS_RX1_TMR_BASE + 4*0x25) +#define JS_RX1_TMR_TINTF21_REG (JS_RX1_TMR_BASE + 4*0x26) +#define JS_RX1_TMR_TINTE22_REG (JS_RX1_TMR_BASE + 4*0x27) +#define JS_RX1_TMR_TINTF22_REG (JS_RX1_TMR_BASE + 4*0x28) +#define JS_RX1_TMR_TINTE30_REG (JS_RX1_TMR_BASE + 4*0x29) +#define JS_RX1_TMR_TINTF30_REG (JS_RX1_TMR_BASE + 4*0x2A) +#define JS_RX1_TMR_TINTE31_REG (JS_RX1_TMR_BASE + 4*0x2B) +#define JS_RX1_TMR_TINTF31_REG (JS_RX1_TMR_BASE + 4*0x2C) +#define JS_RX1_TMR_TINTE32_REG (JS_RX1_TMR_BASE + 4*0x2D) +#define JS_RX1_TMR_TINTF32_REG (JS_RX1_TMR_BASE + 4*0x2E) +#define JS_RX1_TMR_TINTE40_REG (JS_RX1_TMR_BASE + 4*0x2F) +#define JS_RX1_TMR_TINTF40_REG (JS_RX1_TMR_BASE + 4*0x30) +#define JS_RX1_TMR_TINTE41_REG (JS_RX1_TMR_BASE + 4*0x31) +#define JS_RX1_TMR_TINTF41_REG (JS_RX1_TMR_BASE + 4*0x32) +#define JS_RX1_TMR_TINTE42_REG (JS_RX1_TMR_BASE + 4*0x33) +#define JS_RX1_TMR_TINTF42_REG (JS_RX1_TMR_BASE + 4*0x34) +#define JS_RX1_TMR_TINTE50_REG (JS_RX1_TMR_BASE + 4*0x35) +#define JS_RX1_TMR_TINTF50_REG (JS_RX1_TMR_BASE + 4*0x36) +#define JS_RX1_TMR_TINTE51_REG (JS_RX1_TMR_BASE + 4*0x37) +#define JS_RX1_TMR_TINTF51_REG (JS_RX1_TMR_BASE + 4*0x38) +#define JS_RX1_TMR_TINTE52_REG (JS_RX1_TMR_BASE + 4*0x39) +#define JS_RX1_TMR_TINTF52_REG (JS_RX1_TMR_BASE + 4*0x3A) +#define JS_RX1_TMR_TINTE60_REG (JS_RX1_TMR_BASE + 4*0x3B) +#define JS_RX1_TMR_TINTF60_REG (JS_RX1_TMR_BASE + 4*0x3C) +#define JS_RX1_TMR_TINTE61_REG (JS_RX1_TMR_BASE + 4*0x3D) +#define JS_RX1_TMR_TINTF61_REG (JS_RX1_TMR_BASE + 4*0x3E) +#define JS_RX1_TMR_TINTE62_REG (JS_RX1_TMR_BASE + 4*0x3F) +#define JS_RX1_TMR_TINTF62_REG (JS_RX1_TMR_BASE + 4*0x40) +#define JS_RX1_TMR_TINTE70_REG (JS_RX1_TMR_BASE + 4*0x41) +#define JS_RX1_TMR_TINTF70_REG (JS_RX1_TMR_BASE + 4*0x42) +#define JS_RX1_TMR_TINTE71_REG (JS_RX1_TMR_BASE + 4*0x43) +#define JS_RX1_TMR_TINTF71_REG (JS_RX1_TMR_BASE + 4*0x44) +#define JS_RX1_TMR_TINTE72_REG (JS_RX1_TMR_BASE + 4*0x45) +#define JS_RX1_TMR_TINTF72_REG (JS_RX1_TMR_BASE + 4*0x46) +#define JS_RX1_TMR_TINTE80_REG (JS_RX1_TMR_BASE + 4*0x47) +#define JS_RX1_TMR_TINTF80_REG (JS_RX1_TMR_BASE + 4*0x48) +#define JS_RX1_TMR_TINTE81_REG (JS_RX1_TMR_BASE + 4*0x49) +#define JS_RX1_TMR_TINTF81_REG (JS_RX1_TMR_BASE + 4*0x4A) +#define JS_RX1_TMR_TINTE82_REG (JS_RX1_TMR_BASE + 4*0x4B) +#define JS_RX1_TMR_TINTF82_REG (JS_RX1_TMR_BASE + 4*0x4C) +#define JS_RX1_TMR_TINTE90_REG (JS_RX1_TMR_BASE + 4*0x4D) +#define JS_RX1_TMR_TINTF90_REG (JS_RX1_TMR_BASE + 4*0x4E) +#define JS_RX1_TMR_TINTE91_REG (JS_RX1_TMR_BASE + 4*0x4F) +#define JS_RX1_TMR_TINTF91_REG (JS_RX1_TMR_BASE + 4*0x50) +#define JS_RX1_TMR_TINTE92_REG (JS_RX1_TMR_BASE + 4*0x51) +#define JS_RX1_TMR_TINTF92_REG (JS_RX1_TMR_BASE + 4*0x52) +#define JS_RX1_TMR_TINTEA0_REG (JS_RX1_TMR_BASE + 4*0x53) +#define JS_RX1_TMR_TINTFA0_REG (JS_RX1_TMR_BASE + 4*0x54) +#define JS_RX1_TMR_TINTEA1_REG (JS_RX1_TMR_BASE + 4*0x55) +#define JS_RX1_TMR_TINTFA1_REG (JS_RX1_TMR_BASE + 4*0x56) +#define JS_RX1_TMR_TINTEA2_REG (JS_RX1_TMR_BASE + 4*0x57) +#define JS_RX1_TMR_TINTFA2_REG (JS_RX1_TMR_BASE + 4*0x58) +#define JS_RX1_TMR_TINTEB0_REG (JS_RX1_TMR_BASE + 4*0x59) +#define JS_RX1_TMR_TINTFB0_REG (JS_RX1_TMR_BASE + 4*0x5A) +#define JS_RX1_TMR_TINTEB1_REG (JS_RX1_TMR_BASE + 4*0x5B) +#define JS_RX1_TMR_TINTFB1_REG (JS_RX1_TMR_BASE + 4*0x5C) +#define JS_RX1_TMR_TINTEB2_REG (JS_RX1_TMR_BASE + 4*0x5D) +#define JS_RX1_TMR_TINTFB2_REG (JS_RX1_TMR_BASE + 4*0x5E) +#define JS_RX1_TMR_CEVENT_REG (JS_RX1_TMR_BASE + 4*0x5F) +#define JS_RX1_TMR_CMSK_REG (JS_RX1_TMR_BASE + 4*0x60) +#define JS_RX1_TMR_CINTE0_REG (JS_RX1_TMR_BASE + 4*0x61) +#define JS_RX1_TMR_CINTF0_REG (JS_RX1_TMR_BASE + 4*0x62) +#define JS_RX1_TMR_CINTE1_REG (JS_RX1_TMR_BASE + 4*0x63) +#define JS_RX1_TMR_CINTF1_REG (JS_RX1_TMR_BASE + 4*0x64) +#define JS_RX1_TMR_CINTE2_REG (JS_RX1_TMR_BASE + 4*0x65) +#define JS_RX1_TMR_CINTF2_REG (JS_RX1_TMR_BASE + 4*0x66) +#define JS_RX1_TMR_CINTE3_REG (JS_RX1_TMR_BASE + 4*0x67) +#define JS_RX1_TMR_CINTF3_REG (JS_RX1_TMR_BASE + 4*0x68) +#define JS_RX1_TMR_CINTE4_REG (JS_RX1_TMR_BASE + 4*0x69) +#define JS_RX1_TMR_CINTF4_REG (JS_RX1_TMR_BASE + 4*0x6A) +#define JS_RX1_TMR_CINTE5_REG (JS_RX1_TMR_BASE + 4*0x6B) +#define JS_RX1_TMR_CINTF5_REG (JS_RX1_TMR_BASE + 4*0x6C) +#define JS_RX1_TMR_CINTE6_REG (JS_RX1_TMR_BASE + 4*0x6D) +#define JS_RX1_TMR_CINTF6_REG (JS_RX1_TMR_BASE + 4*0x6E) +#define JS_RX1_TMR_CINTE7_REG (JS_RX1_TMR_BASE + 4*0x6F) +#define JS_RX1_TMR_CINTF7_REG (JS_RX1_TMR_BASE + 4*0x70) +#define JS_RX1_TMR_CINTE8_REG (JS_RX1_TMR_BASE + 4*0x71) +#define JS_RX1_TMR_CINTF8_REG (JS_RX1_TMR_BASE + 4*0x72) +#define JS_RX1_TMR_CINTE9_REG (JS_RX1_TMR_BASE + 4*0x73) +#define JS_RX1_TMR_CINTF9_REG (JS_RX1_TMR_BASE + 4*0x74) +#define JS_RX1_TMR_CINTEA_REG (JS_RX1_TMR_BASE + 4*0x75) +#define JS_RX1_TMR_CINTFA_REG (JS_RX1_TMR_BASE + 4*0x76) +#define JS_RX1_TMR_CINTEB_REG (JS_RX1_TMR_BASE + 4*0x77) +#define JS_RX1_TMR_CINTFB_REG (JS_RX1_TMR_BASE + 4*0x78) +#define JS_RX1_TMR_OVFL_REG (JS_RX1_TMR_BASE + 4*0x79) +#define JS_RX1_TMR_OVFH_REG (JS_RX1_TMR_BASE + 4*0x7A) +#define JS_RX1_TMR_RXEN0_0L_REG (JS_RX1_TMR_BASE + 4*0x7B) +#define JS_RX1_TMR_RXEN0_0H_REG (JS_RX1_TMR_BASE + 4*0x7C) +#define JS_RX1_TMR_RXEN0_1L_REG (JS_RX1_TMR_BASE + 4*0x7D) +#define JS_RX1_TMR_RXEN0_1H_REG (JS_RX1_TMR_BASE + 4*0x7E) +#define JS_RX1_TMR_TXEN0_0L_REG (JS_RX1_TMR_BASE + 4*0x7F) +#define JS_RX1_TMR_TXEN0_0H_REG (JS_RX1_TMR_BASE + 4*0x80) +#define JS_RX1_TMR_TXEN0_1L_REG (JS_RX1_TMR_BASE + 4*0x81) +#define JS_RX1_TMR_TXEN0_1H_REG (JS_RX1_TMR_BASE + 4*0x82) +#define JS_RX1_TMR_RXEN1_0L_REG (JS_RX1_TMR_BASE + 4*0x83) +#define JS_RX1_TMR_RXEN1_0H_REG (JS_RX1_TMR_BASE + 4*0x84) +#define JS_RX1_TMR_RXEN1_1L_REG (JS_RX1_TMR_BASE + 4*0x85) +#define JS_RX1_TMR_RXEN1_1H_REG (JS_RX1_TMR_BASE + 4*0x86) +#define JS_RX1_TMR_TXEN1_0L_REG (JS_RX1_TMR_BASE + 4*0x87) +#define JS_RX1_TMR_TXEN1_0H_REG (JS_RX1_TMR_BASE + 4*0x88) +#define JS_RX1_TMR_TXEN1_1L_REG (JS_RX1_TMR_BASE + 4*0x89) +#define JS_RX1_TMR_TXEN1_1H_REG (JS_RX1_TMR_BASE + 4*0x8A) +#define JS_RX1_TMR_RXEN2CSU0L_REG (JS_RX1_TMR_BASE + 4*0x8B) +#define JS_RX1_TMR_RXEN2CSU0H_REG (JS_RX1_TMR_BASE + 4*0x8C) +#define JS_RX1_TMR_RXEN2CSU1L_REG (JS_RX1_TMR_BASE + 4*0x8D) +#define JS_RX1_TMR_RXEN2CSU1H_REG (JS_RX1_TMR_BASE + 4*0x8E) +#define JS_RX1_TMR_TXEN2CSU0L_REG (JS_RX1_TMR_BASE + 4*0x8F) +#define JS_RX1_TMR_TXEN2CSU0H_REG (JS_RX1_TMR_BASE + 4*0x90) +#define JS_RX1_TMR_TXEN2CSU1L_REG (JS_RX1_TMR_BASE + 4*0x91) +#define JS_RX1_TMR_TXEN2CSU1H_REG (JS_RX1_TMR_BASE + 4*0x92) +#define JS_RX1_TMR_SCRATH0L_REG (JS_RX1_TMR_BASE + 4*0x93) +#define JS_RX1_TMR_SCRATH0H_REG (JS_RX1_TMR_BASE + 4*0x94) +#define JS_RX1_TMR_SCRATH1L_REG (JS_RX1_TMR_BASE + 4*0x95) +#define JS_RX1_TMR_SCRATH1H_REG (JS_RX1_TMR_BASE + 4*0x96) +#define JS_RX1_TMR_RX_SCRL_REG (JS_RX1_TMR_BASE + 4*0x97) +#define JS_RX1_TMR_RX_SCRH_REG (JS_RX1_TMR_BASE + 4*0x98) +#define JS_RX1_TMR_TX_SCRL_REG (JS_RX1_TMR_BASE + 4*0x99) +#define JS_RX1_TMR_TX_SCRH_REG (JS_RX1_TMR_BASE + 4*0x9A) +#define JS_RX1_TMR_1PPSL_REG (JS_RX1_TMR_BASE + 4*0x9B) +#define JS_RX1_TMR_1PPSH_REG (JS_RX1_TMR_BASE + 4*0x9C) +#define JS_RX1_TMR_CPRI_10MS_CTRL (JS_RX1_TMR_BASE + 4*0x9D) +#define JS_RX1_TMR_CPRI_ADJ_L (JS_RX1_TMR_BASE + 4*0x9E) +#define JS_RX1_TMR_CPRI_ADJ_H (JS_RX1_TMR_BASE + 4*0x9F) +#define JS_RX1_TMR_CPRI_10MS_CLR (JS_RX1_TMR_BASE + 4*0xA0) + +#define JS_RX1_TMR_RX_SOF0_SCR_L_REG (JS_RX1_TMR_BASE + 4*0xA1) +#define JS_RX1_TMR_RX_SOF0_SCR_H_REG (JS_RX1_TMR_BASE + 4*0xA2) +#define JS_RX1_TMR_RX_SOF1_SCR_L_REG (JS_RX1_TMR_BASE + 4*0xA3) +#define JS_RX1_TMR_RX_SOF1_SCR_H_REG (JS_RX1_TMR_BASE + 4*0xA4) +#define JS_RX1_TMR_RX_SOF2_SCR_L_REG (JS_RX1_TMR_BASE + 4*0xA5) +#define JS_RX1_TMR_RX_SOF2_SCR_H_REG (JS_RX1_TMR_BASE + 4*0xA6) +#define JS_RX1_TMR_RX_SOF3_SCR_L_REG (JS_RX1_TMR_BASE + 4*0xA7) +#define JS_RX1_TMR_RX_SOF3_SCR_H_REG (JS_RX1_TMR_BASE + 4*0xA8) +#define JS_RX1_TMR_RX_EOF0_SCR_L_REG (JS_RX1_TMR_BASE + 4*0xA9) +#define JS_RX1_TMR_RX_EOF0_SCR_H_REG (JS_RX1_TMR_BASE + 4*0xAA) +#define JS_RX1_TMR_RX_EOF1_SCR_L_REG (JS_RX1_TMR_BASE + 4*0xAB) +#define JS_RX1_TMR_RX_EOF1_SCR_H_REG (JS_RX1_TMR_BASE + 4*0xAC) +#define JS_RX1_TMR_RX_EOF2_SCR_L_REG (JS_RX1_TMR_BASE + 4*0xAD) +#define JS_RX1_TMR_RX_EOF2_SCR_H_REG (JS_RX1_TMR_BASE + 4*0xAE) +#define JS_RX1_TMR_RX_EOF3_SCR_L_REG (JS_RX1_TMR_BASE + 4*0xAF) +#define JS_RX1_TMR_RX_EOF3_SCR_H_REG (JS_RX1_TMR_BASE + 4*0xB0) +#define JS_RX1_TMR_RX_SOF_EOF_SCR_EN (JS_RX1_TMR_BASE + 4*0xB1) + + +#define JS_RX1_TMR_TnL_REG0 (JS_RX1_TMR_BASE + 4*0x100+8*0x0) +#define JS_RX1_TMR_TnL_REG1 (JS_RX1_TMR_BASE + 4*0x100+8*0x1) +#define JS_RX1_TMR_TnL_REG2 (JS_RX1_TMR_BASE + 4*0x100+8*0x2) +#define JS_RX1_TMR_TnL_REG3 (JS_RX1_TMR_BASE + 4*0x100+8*0x3) +#define JS_RX1_TMR_TnL_REG4 (JS_RX1_TMR_BASE + 4*0x100+8*0x4) +#define JS_RX1_TMR_TnL_REG5 (JS_RX1_TMR_BASE + 4*0x100+8*0x5) +#define JS_RX1_TMR_TnL_REG6 (JS_RX1_TMR_BASE + 4*0x100+8*0x6) +#define JS_RX1_TMR_TnL_REG7 (JS_RX1_TMR_BASE + 4*0x100+8*0x7) +#define JS_RX1_TMR_TnL_REG8 (JS_RX1_TMR_BASE + 4*0x100+8*0x8) +#define JS_RX1_TMR_TnL_REG9 (JS_RX1_TMR_BASE + 4*0x100+8*0x9) +#define JS_RX1_TMR_TnL_REG10 (JS_RX1_TMR_BASE + 4*0x100+8*0xa) +#define JS_RX1_TMR_TnL_REG11 (JS_RX1_TMR_BASE + 4*0x100+8*0xb) +#define JS_RX1_TMR_TnL_REG12 (JS_RX1_TMR_BASE + 4*0x100+8*0xc) +#define JS_RX1_TMR_TnL_REG13 (JS_RX1_TMR_BASE + 4*0x100+8*0xd) +#define JS_RX1_TMR_TnL_REG14 (JS_RX1_TMR_BASE + 4*0x100+8*0xe) +#define JS_RX1_TMR_TnL_REG15 (JS_RX1_TMR_BASE + 4*0x100+8*0xf) +#define JS_RX1_TMR_TnL_REG16 (JS_RX1_TMR_BASE + 4*0x100+8*0x10) +#define JS_RX1_TMR_TnL_REG17 (JS_RX1_TMR_BASE + 4*0x100+8*0x11) +#define JS_RX1_TMR_TnL_REG18 (JS_RX1_TMR_BASE + 4*0x100+8*0x12) +#define JS_RX1_TMR_TnL_REG19 (JS_RX1_TMR_BASE + 4*0x100+8*0x13) +#define JS_RX1_TMR_TnL_REG20 (JS_RX1_TMR_BASE + 4*0x100+8*0x14) +#define JS_RX1_TMR_TnL_REG21 (JS_RX1_TMR_BASE + 4*0x100+8*0x15) +#define JS_RX1_TMR_TnL_REG22 (JS_RX1_TMR_BASE + 4*0x100+8*0x16) +#define JS_RX1_TMR_TnL_REG23 (JS_RX1_TMR_BASE + 4*0x100+8*0x17) +#define JS_RX1_TMR_TnL_REG24 (JS_RX1_TMR_BASE + 4*0x100+8*0x18) +#define JS_RX1_TMR_TnL_REG25 (JS_RX1_TMR_BASE + 4*0x100+8*0x19) +#define JS_RX1_TMR_TnL_REG26 (JS_RX1_TMR_BASE + 4*0x100+8*0x1a) +#define JS_RX1_TMR_TnL_REG27 (JS_RX1_TMR_BASE + 4*0x100+8*0x1b) +#define JS_RX1_TMR_TnL_REG28 (JS_RX1_TMR_BASE + 4*0x100+8*0x1c) +#define JS_RX1_TMR_TnL_REG29 (JS_RX1_TMR_BASE + 4*0x100+8*0x1d) +#define JS_RX1_TMR_TnL_REG30 (JS_RX1_TMR_BASE + 4*0x100+8*0x1e) +#define JS_RX1_TMR_TnL_REG31 (JS_RX1_TMR_BASE + 4*0x100+8*0x1f) +#define JS_RX1_TMR_TnL_REG32 (JS_RX1_TMR_BASE + 4*0x100+8*0x20) +#define JS_RX1_TMR_TnL_REG33 (JS_RX1_TMR_BASE + 4*0x100+8*0x21) +#define JS_RX1_TMR_TnL_REG34 (JS_RX1_TMR_BASE + 4*0x100+8*0x22) +#define JS_RX1_TMR_TnL_REG35 (JS_RX1_TMR_BASE + 4*0x100+8*0x23) +#define JS_RX1_TMR_TnL_REG36 (JS_RX1_TMR_BASE + 4*0x100+8*0x24) +#define JS_RX1_TMR_TnL_REG37 (JS_RX1_TMR_BASE + 4*0x100+8*0x25) +#define JS_RX1_TMR_TnL_REG38 (JS_RX1_TMR_BASE + 4*0x100+8*0x26) +#define JS_RX1_TMR_TnL_REG39 (JS_RX1_TMR_BASE + 4*0x100+8*0x27) +#define JS_RX1_TMR_TnL_REG40 (JS_RX1_TMR_BASE + 4*0x100+8*0x28) +#define JS_RX1_TMR_TnL_REG41 (JS_RX1_TMR_BASE + 4*0x100+8*0x29) +#define JS_RX1_TMR_TnL_REG42 (JS_RX1_TMR_BASE + 4*0x100+8*0x2a) +#define JS_RX1_TMR_TnL_REG43 (JS_RX1_TMR_BASE + 4*0x100+8*0x2b) +#define JS_RX1_TMR_TnL_REG44 (JS_RX1_TMR_BASE + 4*0x100+8*0x2c) +#define JS_RX1_TMR_TnL_REG45 (JS_RX1_TMR_BASE + 4*0x100+8*0x2d) +#define JS_RX1_TMR_TnL_REG46 (JS_RX1_TMR_BASE + 4*0x100+8*0x2e) +#define JS_RX1_TMR_TnL_REG47 (JS_RX1_TMR_BASE + 4*0x100+8*0x2f) +#define JS_RX1_TMR_TnL_REG48 (JS_RX1_TMR_BASE + 4*0x100+8*0x30) +#define JS_RX1_TMR_TnL_REG49 (JS_RX1_TMR_BASE + 4*0x100+8*0x31) +#define JS_RX1_TMR_TnL_REG50 (JS_RX1_TMR_BASE + 4*0x100+8*0x32) +#define JS_RX1_TMR_TnL_REG51 (JS_RX1_TMR_BASE + 4*0x100+8*0x33) +#define JS_RX1_TMR_TnL_REG52 (JS_RX1_TMR_BASE + 4*0x100+8*0x34) +#define JS_RX1_TMR_TnL_REG53 (JS_RX1_TMR_BASE + 4*0x100+8*0x35) +#define JS_RX1_TMR_TnL_REG54 (JS_RX1_TMR_BASE + 4*0x100+8*0x36) +#define JS_RX1_TMR_TnL_REG55 (JS_RX1_TMR_BASE + 4*0x100+8*0x37) +#define JS_RX1_TMR_TnL_REG56 (JS_RX1_TMR_BASE + 4*0x100+8*0x38) +#define JS_RX1_TMR_TnL_REG57 (JS_RX1_TMR_BASE + 4*0x100+8*0x39) +#define JS_RX1_TMR_TnL_REG58 (JS_RX1_TMR_BASE + 4*0x100+8*0x3a) +#define JS_RX1_TMR_TnL_REG59 (JS_RX1_TMR_BASE + 4*0x100+8*0x3b) +#define JS_RX1_TMR_TnL_REG60 (JS_RX1_TMR_BASE + 4*0x100+8*0x3c) +#define JS_RX1_TMR_TnL_REG61 (JS_RX1_TMR_BASE + 4*0x100+8*0x3d) +#define JS_RX1_TMR_TnL_REG62 (JS_RX1_TMR_BASE + 4*0x100+8*0x3e) +#define JS_RX1_TMR_TnL_REG63 (JS_RX1_TMR_BASE + 4*0x100+8*0x3f) +#define JS_RX1_TMR_TnL_REG64 (JS_RX1_TMR_BASE + 4*0x100+8*0x40) +#define JS_RX1_TMR_TnL_REG65 (JS_RX1_TMR_BASE + 4*0x100+8*0x41) +#define JS_RX1_TMR_TnL_REG66 (JS_RX1_TMR_BASE + 4*0x100+8*0x42) +#define JS_RX1_TMR_TnL_REG67 (JS_RX1_TMR_BASE + 4*0x100+8*0x43) +#define JS_RX1_TMR_TnL_REG68 (JS_RX1_TMR_BASE + 4*0x100+8*0x44) +#define JS_RX1_TMR_TnL_REG69 (JS_RX1_TMR_BASE + 4*0x100+8*0x45) +#define JS_RX1_TMR_TnL_REG70 (JS_RX1_TMR_BASE + 4*0x100+8*0x46) +#define JS_RX1_TMR_TnL_REG71 (JS_RX1_TMR_BASE + 4*0x100+8*0x47) +#define JS_RX1_TMR_TnL_REG72 (JS_RX1_TMR_BASE + 4*0x100+8*0x48) +#define JS_RX1_TMR_TnL_REG73 (JS_RX1_TMR_BASE + 4*0x100+8*0x49) +#define JS_RX1_TMR_TnL_REG74 (JS_RX1_TMR_BASE + 4*0x100+8*0x4a) +#define JS_RX1_TMR_TnL_REG75 (JS_RX1_TMR_BASE + 4*0x100+8*0x4b) +#define JS_RX1_TMR_TnL_REG76 (JS_RX1_TMR_BASE + 4*0x100+8*0x4c) +#define JS_RX1_TMR_TnL_REG77 (JS_RX1_TMR_BASE + 4*0x100+8*0x4d) +#define JS_RX1_TMR_TnL_REG78 (JS_RX1_TMR_BASE + 4*0x100+8*0x4e) +#define JS_RX1_TMR_TnL_REG79 (JS_RX1_TMR_BASE + 4*0x100+8*0x4f) +#define JS_RX1_TMR_TnL_REG80 (JS_RX1_TMR_BASE + 4*0x100+8*0x50) +#define JS_RX1_TMR_TnL_REG81 (JS_RX1_TMR_BASE + 4*0x100+8*0x51) +#define JS_RX1_TMR_TnL_REG82 (JS_RX1_TMR_BASE + 4*0x100+8*0x52) +#define JS_RX1_TMR_TnL_REG83 (JS_RX1_TMR_BASE + 4*0x100+8*0x53) +#define JS_RX1_TMR_TnL_REG84 (JS_RX1_TMR_BASE + 4*0x100+8*0x54) +#define JS_RX1_TMR_TnL_REG85 (JS_RX1_TMR_BASE + 4*0x100+8*0x55) +#define JS_RX1_TMR_TnL_REG86 (JS_RX1_TMR_BASE + 4*0x100+8*0x56) +#define JS_RX1_TMR_TnL_REG87 (JS_RX1_TMR_BASE + 4*0x100+8*0x57) +#define JS_RX1_TMR_TnL_REG88 (JS_RX1_TMR_BASE + 4*0x100+8*0x58) +#define JS_RX1_TMR_TnL_REG89 (JS_RX1_TMR_BASE + 4*0x100+8*0x59) +#define JS_RX1_TMR_TnL_REG90 (JS_RX1_TMR_BASE + 4*0x100+8*0x5a) +#define JS_RX1_TMR_TnL_REG91 (JS_RX1_TMR_BASE + 4*0x100+8*0x5b) +#define JS_RX1_TMR_TnL_REG92 (JS_RX1_TMR_BASE + 4*0x100+8*0x5c) +#define JS_RX1_TMR_TnL_REG93 (JS_RX1_TMR_BASE + 4*0x100+8*0x5d) +#define JS_RX1_TMR_TnL_REG94 (JS_RX1_TMR_BASE + 4*0x100+8*0x5e) +#define JS_RX1_TMR_TnL_REG95 (JS_RX1_TMR_BASE + 4*0x100+8*0x5f) + + + +#define JS_RX1_TMR_TnH_REG0 (JS_RX1_TMR_BASE + 4*0x100+8*0x0 + 0x4) +#define JS_RX1_TMR_TnH_REG1 (JS_RX1_TMR_BASE + 4*0x100+8*0x1 + 0x4) +#define JS_RX1_TMR_TnH_REG2 (JS_RX1_TMR_BASE + 4*0x100+8*0x2 + 0x4) +#define JS_RX1_TMR_TnH_REG3 (JS_RX1_TMR_BASE + 4*0x100+8*0x3 + 0x4) +#define JS_RX1_TMR_TnH_REG4 (JS_RX1_TMR_BASE + 4*0x100+8*0x4 + 0x4) +#define JS_RX1_TMR_TnH_REG5 (JS_RX1_TMR_BASE + 4*0x100+8*0x5 + 0x4) +#define JS_RX1_TMR_TnH_REG6 (JS_RX1_TMR_BASE + 4*0x100+8*0x6 + 0x4) +#define JS_RX1_TMR_TnH_REG7 (JS_RX1_TMR_BASE + 4*0x100+8*0x7 + 0x4) +#define JS_RX1_TMR_TnH_REG8 (JS_RX1_TMR_BASE + 4*0x100+8*0x8 + 0x4) +#define JS_RX1_TMR_TnH_REG9 (JS_RX1_TMR_BASE + 4*0x100+8*0x9 + 0x4) +#define JS_RX1_TMR_TnH_REG10 (JS_RX1_TMR_BASE + 4*0x100+8*0xa + 0x4) +#define JS_RX1_TMR_TnH_REG11 (JS_RX1_TMR_BASE + 4*0x100+8*0xb + 0x4) +#define JS_RX1_TMR_TnH_REG12 (JS_RX1_TMR_BASE + 4*0x100+8*0xc + 0x4) +#define JS_RX1_TMR_TnH_REG13 (JS_RX1_TMR_BASE + 4*0x100+8*0xd + 0x4) +#define JS_RX1_TMR_TnH_REG14 (JS_RX1_TMR_BASE + 4*0x100+8*0xe + 0x4) +#define JS_RX1_TMR_TnH_REG15 (JS_RX1_TMR_BASE + 4*0x100+8*0xf + 0x4) +#define JS_RX1_TMR_TnH_REG16 (JS_RX1_TMR_BASE + 4*0x100+8*0x10 + 0x4) +#define JS_RX1_TMR_TnH_REG17 (JS_RX1_TMR_BASE + 4*0x100+8*0x11 + 0x4) +#define JS_RX1_TMR_TnH_REG18 (JS_RX1_TMR_BASE + 4*0x100+8*0x12 + 0x4) +#define JS_RX1_TMR_TnH_REG19 (JS_RX1_TMR_BASE + 4*0x100+8*0x13 + 0x4) +#define JS_RX1_TMR_TnH_REG20 (JS_RX1_TMR_BASE + 4*0x100+8*0x14 + 0x4) +#define JS_RX1_TMR_TnH_REG21 (JS_RX1_TMR_BASE + 4*0x100+8*0x15 + 0x4) +#define JS_RX1_TMR_TnH_REG22 (JS_RX1_TMR_BASE + 4*0x100+8*0x16 + 0x4) +#define JS_RX1_TMR_TnH_REG23 (JS_RX1_TMR_BASE + 4*0x100+8*0x17 + 0x4) +#define JS_RX1_TMR_TnH_REG24 (JS_RX1_TMR_BASE + 4*0x100+8*0x18 + 0x4) +#define JS_RX1_TMR_TnH_REG25 (JS_RX1_TMR_BASE + 4*0x100+8*0x19 + 0x4) +#define JS_RX1_TMR_TnH_REG26 (JS_RX1_TMR_BASE + 4*0x100+8*0x1a + 0x4) +#define JS_RX1_TMR_TnH_REG27 (JS_RX1_TMR_BASE + 4*0x100+8*0x1b + 0x4) +#define JS_RX1_TMR_TnH_REG28 (JS_RX1_TMR_BASE + 4*0x100+8*0x1c + 0x4) +#define JS_RX1_TMR_TnH_REG29 (JS_RX1_TMR_BASE + 4*0x100+8*0x1d + 0x4) +#define JS_RX1_TMR_TnH_REG30 (JS_RX1_TMR_BASE + 4*0x100+8*0x1e + 0x4) +#define JS_RX1_TMR_TnH_REG31 (JS_RX1_TMR_BASE + 4*0x100+8*0x1f + 0x4) +#define JS_RX1_TMR_TnH_REG32 (JS_RX1_TMR_BASE + 4*0x100+8*0x20 + 0x4) +#define JS_RX1_TMR_TnH_REG33 (JS_RX1_TMR_BASE + 4*0x100+8*0x21 + 0x4) +#define JS_RX1_TMR_TnH_REG34 (JS_RX1_TMR_BASE + 4*0x100+8*0x22 + 0x4) +#define JS_RX1_TMR_TnH_REG35 (JS_RX1_TMR_BASE + 4*0x100+8*0x23 + 0x4) +#define JS_RX1_TMR_TnH_REG36 (JS_RX1_TMR_BASE + 4*0x100+8*0x24 + 0x4) +#define JS_RX1_TMR_TnH_REG37 (JS_RX1_TMR_BASE + 4*0x100+8*0x25 + 0x4) +#define JS_RX1_TMR_TnH_REG38 (JS_RX1_TMR_BASE + 4*0x100+8*0x26 + 0x4) +#define JS_RX1_TMR_TnH_REG39 (JS_RX1_TMR_BASE + 4*0x100+8*0x27 + 0x4) +#define JS_RX1_TMR_TnH_REG40 (JS_RX1_TMR_BASE + 4*0x100+8*0x28 + 0x4) +#define JS_RX1_TMR_TnH_REG41 (JS_RX1_TMR_BASE + 4*0x100+8*0x29 + 0x4) +#define JS_RX1_TMR_TnH_REG42 (JS_RX1_TMR_BASE + 4*0x100+8*0x2a + 0x4) +#define JS_RX1_TMR_TnH_REG43 (JS_RX1_TMR_BASE + 4*0x100+8*0x2b + 0x4) +#define JS_RX1_TMR_TnH_REG44 (JS_RX1_TMR_BASE + 4*0x100+8*0x2c + 0x4) +#define JS_RX1_TMR_TnH_REG45 (JS_RX1_TMR_BASE + 4*0x100+8*0x2d + 0x4) +#define JS_RX1_TMR_TnH_REG46 (JS_RX1_TMR_BASE + 4*0x100+8*0x2e + 0x4) +#define JS_RX1_TMR_TnH_REG47 (JS_RX1_TMR_BASE + 4*0x100+8*0x2f + 0x4) +#define JS_RX1_TMR_TnH_REG48 (JS_RX1_TMR_BASE + 4*0x100+8*0x30 + 0x4) +#define JS_RX1_TMR_TnH_REG49 (JS_RX1_TMR_BASE + 4*0x100+8*0x31 + 0x4) +#define JS_RX1_TMR_TnH_REG50 (JS_RX1_TMR_BASE + 4*0x100+8*0x32 + 0x4) +#define JS_RX1_TMR_TnH_REG51 (JS_RX1_TMR_BASE + 4*0x100+8*0x33 + 0x4) +#define JS_RX1_TMR_TnH_REG52 (JS_RX1_TMR_BASE + 4*0x100+8*0x34 + 0x4) +#define JS_RX1_TMR_TnH_REG53 (JS_RX1_TMR_BASE + 4*0x100+8*0x35 + 0x4) +#define JS_RX1_TMR_TnH_REG54 (JS_RX1_TMR_BASE + 4*0x100+8*0x36 + 0x4) +#define JS_RX1_TMR_TnH_REG55 (JS_RX1_TMR_BASE + 4*0x100+8*0x37 + 0x4) +#define JS_RX1_TMR_TnH_REG56 (JS_RX1_TMR_BASE + 4*0x100+8*0x38 + 0x4) +#define JS_RX1_TMR_TnH_REG57 (JS_RX1_TMR_BASE + 4*0x100+8*0x39 + 0x4) +#define JS_RX1_TMR_TnH_REG58 (JS_RX1_TMR_BASE + 4*0x100+8*0x3a + 0x4) +#define JS_RX1_TMR_TnH_REG59 (JS_RX1_TMR_BASE + 4*0x100+8*0x3b + 0x4) +#define JS_RX1_TMR_TnH_REG60 (JS_RX1_TMR_BASE + 4*0x100+8*0x3c + 0x4) +#define JS_RX1_TMR_TnH_REG61 (JS_RX1_TMR_BASE + 4*0x100+8*0x3d + 0x4) +#define JS_RX1_TMR_TnH_REG62 (JS_RX1_TMR_BASE + 4*0x100+8*0x3e + 0x4) +#define JS_RX1_TMR_TnH_REG63 (JS_RX1_TMR_BASE + 4*0x100+8*0x3f + 0x4) +#define JS_RX1_TMR_TnH_REG64 (JS_RX1_TMR_BASE + 4*0x100+8*0x40 + 0x4) +#define JS_RX1_TMR_TnH_REG65 (JS_RX1_TMR_BASE + 4*0x100+8*0x41 + 0x4) +#define JS_RX1_TMR_TnH_REG66 (JS_RX1_TMR_BASE + 4*0x100+8*0x42 + 0x4) +#define JS_RX1_TMR_TnH_REG67 (JS_RX1_TMR_BASE + 4*0x100+8*0x43 + 0x4) +#define JS_RX1_TMR_TnH_REG68 (JS_RX1_TMR_BASE + 4*0x100+8*0x44 + 0x4) +#define JS_RX1_TMR_TnH_REG69 (JS_RX1_TMR_BASE + 4*0x100+8*0x45 + 0x4) +#define JS_RX1_TMR_TnH_REG70 (JS_RX1_TMR_BASE + 4*0x100+8*0x46 + 0x4) +#define JS_RX1_TMR_TnH_REG71 (JS_RX1_TMR_BASE + 4*0x100+8*0x47 + 0x4) +#define JS_RX1_TMR_TnH_REG72 (JS_RX1_TMR_BASE + 4*0x100+8*0x48 + 0x4) +#define JS_RX1_TMR_TnH_REG73 (JS_RX1_TMR_BASE + 4*0x100+8*0x49 + 0x4) +#define JS_RX1_TMR_TnH_REG74 (JS_RX1_TMR_BASE + 4*0x100+8*0x4a + 0x4) +#define JS_RX1_TMR_TnH_REG75 (JS_RX1_TMR_BASE + 4*0x100+8*0x4b + 0x4) +#define JS_RX1_TMR_TnH_REG76 (JS_RX1_TMR_BASE + 4*0x100+8*0x4c + 0x4) +#define JS_RX1_TMR_TnH_REG77 (JS_RX1_TMR_BASE + 4*0x100+8*0x4d + 0x4) +#define JS_RX1_TMR_TnH_REG78 (JS_RX1_TMR_BASE + 4*0x100+8*0x4e + 0x4) +#define JS_RX1_TMR_TnH_REG79 (JS_RX1_TMR_BASE + 4*0x100+8*0x4f + 0x4) +#define JS_RX1_TMR_TnH_REG80 (JS_RX1_TMR_BASE + 4*0x100+8*0x50 + 0x4) +#define JS_RX1_TMR_TnH_REG81 (JS_RX1_TMR_BASE + 4*0x100+8*0x51 + 0x4) +#define JS_RX1_TMR_TnH_REG82 (JS_RX1_TMR_BASE + 4*0x100+8*0x52 + 0x4) +#define JS_RX1_TMR_TnH_REG83 (JS_RX1_TMR_BASE + 4*0x100+8*0x53 + 0x4) +#define JS_RX1_TMR_TnH_REG84 (JS_RX1_TMR_BASE + 4*0x100+8*0x54 + 0x4) +#define JS_RX1_TMR_TnH_REG85 (JS_RX1_TMR_BASE + 4*0x100+8*0x55 + 0x4) +#define JS_RX1_TMR_TnH_REG86 (JS_RX1_TMR_BASE + 4*0x100+8*0x56 + 0x4) +#define JS_RX1_TMR_TnH_REG87 (JS_RX1_TMR_BASE + 4*0x100+8*0x57 + 0x4) +#define JS_RX1_TMR_TnH_REG88 (JS_RX1_TMR_BASE + 4*0x100+8*0x58 + 0x4) +#define JS_RX1_TMR_TnH_REG89 (JS_RX1_TMR_BASE + 4*0x100+8*0x59 + 0x4) +#define JS_RX1_TMR_TnH_REG90 (JS_RX1_TMR_BASE + 4*0x100+8*0x5a + 0x4) +#define JS_RX1_TMR_TnH_REG91 (JS_RX1_TMR_BASE + 4*0x100+8*0x5b + 0x4) +#define JS_RX1_TMR_TnH_REG92 (JS_RX1_TMR_BASE + 4*0x100+8*0x5c + 0x4) +#define JS_RX1_TMR_TnH_REG93 (JS_RX1_TMR_BASE + 4*0x100+8*0x5d + 0x4) +#define JS_RX1_TMR_TnH_REG94 (JS_RX1_TMR_BASE + 4*0x100+8*0x5e + 0x4) +#define JS_RX1_TMR_TnH_REG95 (JS_RX1_TMR_BASE + 4*0x100+8*0x5f + 0x4) + +#define JS_TX0_PIN_CTRL_REG (JS_TX0_TMR_BASE + 4*0x00) +#define JS_TX0_IO_CTRL_REG (JS_TX0_TMR_BASE + 4*0x01) +#define JS_TX0_TMR_INTC_REG (JS_TX0_TMR_BASE + 4*0x02) +#define JS_TX0_TMR_SCR_CTRL_REG (JS_TX0_TMR_BASE + 4*0x03) +#define JS_TX0_TMR_CTRL_REG (JS_TX0_TMR_BASE + 4*0x04) +#define JS_TX0_TMR_RX_SCRL_0_REG (JS_TX0_TMR_BASE + 4*0x05) +#define JS_TX0_TMR_RX_SCRH_0_REG (JS_TX0_TMR_BASE + 4*0x06) +#define JS_TX0_TMR_TX_SCRL_0_REG (JS_TX0_TMR_BASE + 4*0x07) +#define JS_TX0_TMR_TX_SCRH_0_REG (JS_TX0_TMR_BASE + 4*0x08) +#define JS_TX0_TMR_RX_SCRL_1_REG (JS_TX0_TMR_BASE + 4*0x09) +#define JS_TX0_TMR_RX_SCRH_1_REG (JS_TX0_TMR_BASE + 4*0x0A) +#define JS_TX0_TMR_TX_SCRL_1_REG (JS_TX0_TMR_BASE + 4*0x0B) +#define JS_TX0_TMR_TX_SCRH_1_REG (JS_TX0_TMR_BASE + 4*0x0C) +#define JS_TX0_TMR_TEVENT0_REG (JS_TX0_TMR_BASE + 4*0x10) +#define JS_TX0_TMR_TEVENT1_REG (JS_TX0_TMR_BASE + 4*0x11) +#define JS_TX0_TMR_TEVENT2_REG (JS_TX0_TMR_BASE + 4*0x12) +#define JS_TX0_TMR_TSCR_TRG_REG (JS_TX0_TMR_BASE + 4*0x13) +#define JS_TX0_TMR_TWREQ0_REG (JS_TX0_TMR_BASE + 4*0x14) +#define JS_TX0_TMR_TWREQ1_REG (JS_TX0_TMR_BASE + 4*0x15) +#define JS_TX0_TMR_TWREQ2_REG (JS_TX0_TMR_BASE + 4*0x16) +#define JS_TX0_TMR_TINTE00_REG (JS_TX0_TMR_BASE + 4*0x17) +#define JS_TX0_TMR_TINTF00_REG (JS_TX0_TMR_BASE + 4*0x18) +#define JS_TX0_TMR_TINTE01_REG (JS_TX0_TMR_BASE + 4*0x19) +#define JS_TX0_TMR_TINTF01_REG (JS_TX0_TMR_BASE + 4*0x1A) +#define JS_TX0_TMR_TINTE02_REG (JS_TX0_TMR_BASE + 4*0x1B) +#define JS_TX0_TMR_TINTF02_REG (JS_TX0_TMR_BASE + 4*0x1C) +#define JS_TX0_TMR_TINTE10_REG (JS_TX0_TMR_BASE + 4*0x1D) +#define JS_TX0_TMR_TINTF10_REG (JS_TX0_TMR_BASE + 4*0x1E) +#define JS_TX0_TMR_TINTE11_REG (JS_TX0_TMR_BASE + 4*0x1F) +#define JS_TX0_TMR_TINTF11_REG (JS_TX0_TMR_BASE + 4*0x20) +#define JS_TX0_TMR_TINTE12_REG (JS_TX0_TMR_BASE + 4*0x21) +#define JS_TX0_TMR_TINTF12_REG (JS_TX0_TMR_BASE + 4*0x22) +#define JS_TX0_TMR_TINTE20_REG (JS_TX0_TMR_BASE + 4*0x23) +#define JS_TX0_TMR_TINTF20_REG (JS_TX0_TMR_BASE + 4*0x24) +#define JS_TX0_TMR_TINTE21_REG (JS_TX0_TMR_BASE + 4*0x25) +#define JS_TX0_TMR_TINTF21_REG (JS_TX0_TMR_BASE + 4*0x26) +#define JS_TX0_TMR_TINTE22_REG (JS_TX0_TMR_BASE + 4*0x27) +#define JS_TX0_TMR_TINTF22_REG (JS_TX0_TMR_BASE + 4*0x28) +#define JS_TX0_TMR_TINTE30_REG (JS_TX0_TMR_BASE + 4*0x29) +#define JS_TX0_TMR_TINTF30_REG (JS_TX0_TMR_BASE + 4*0x2A) +#define JS_TX0_TMR_TINTE31_REG (JS_TX0_TMR_BASE + 4*0x2B) +#define JS_TX0_TMR_TINTF31_REG (JS_TX0_TMR_BASE + 4*0x2C) +#define JS_TX0_TMR_TINTE32_REG (JS_TX0_TMR_BASE + 4*0x2D) +#define JS_TX0_TMR_TINTF32_REG (JS_TX0_TMR_BASE + 4*0x2E) +#define JS_TX0_TMR_TINTE40_REG (JS_TX0_TMR_BASE + 4*0x2F) +#define JS_TX0_TMR_TINTF40_REG (JS_TX0_TMR_BASE + 4*0x30) +#define JS_TX0_TMR_TINTE41_REG (JS_TX0_TMR_BASE + 4*0x31) +#define JS_TX0_TMR_TINTF41_REG (JS_TX0_TMR_BASE + 4*0x32) +#define JS_TX0_TMR_TINTE42_REG (JS_TX0_TMR_BASE + 4*0x33) +#define JS_TX0_TMR_TINTF42_REG (JS_TX0_TMR_BASE + 4*0x34) +#define JS_TX0_TMR_TINTE50_REG (JS_TX0_TMR_BASE + 4*0x35) +#define JS_TX0_TMR_TINTF50_REG (JS_TX0_TMR_BASE + 4*0x36) +#define JS_TX0_TMR_TINTE51_REG (JS_TX0_TMR_BASE + 4*0x37) +#define JS_TX0_TMR_TINTF51_REG (JS_TX0_TMR_BASE + 4*0x38) +#define JS_TX0_TMR_TINTE52_REG (JS_TX0_TMR_BASE + 4*0x39) +#define JS_TX0_TMR_TINTF52_REG (JS_TX0_TMR_BASE + 4*0x3A) +#define JS_TX0_TMR_TINTE60_REG (JS_TX0_TMR_BASE + 4*0x3B) +#define JS_TX0_TMR_TINTF60_REG (JS_TX0_TMR_BASE + 4*0x3C) +#define JS_TX0_TMR_TINTE61_REG (JS_TX0_TMR_BASE + 4*0x3D) +#define JS_TX0_TMR_TINTF61_REG (JS_TX0_TMR_BASE + 4*0x3E) +#define JS_TX0_TMR_TINTE62_REG (JS_TX0_TMR_BASE + 4*0x3F) +#define JS_TX0_TMR_TINTF62_REG (JS_TX0_TMR_BASE + 4*0x40) +#define JS_TX0_TMR_TINTE70_REG (JS_TX0_TMR_BASE + 4*0x41) +#define JS_TX0_TMR_TINTF70_REG (JS_TX0_TMR_BASE + 4*0x42) +#define JS_TX0_TMR_TINTE71_REG (JS_TX0_TMR_BASE + 4*0x43) +#define JS_TX0_TMR_TINTF71_REG (JS_TX0_TMR_BASE + 4*0x44) +#define JS_TX0_TMR_TINTE72_REG (JS_TX0_TMR_BASE + 4*0x45) +#define JS_TX0_TMR_TINTF72_REG (JS_TX0_TMR_BASE + 4*0x46) +#define JS_TX0_TMR_TINTE80_REG (JS_TX0_TMR_BASE + 4*0x47) +#define JS_TX0_TMR_TINTF80_REG (JS_TX0_TMR_BASE + 4*0x48) +#define JS_TX0_TMR_TINTE81_REG (JS_TX0_TMR_BASE + 4*0x49) +#define JS_TX0_TMR_TINTF81_REG (JS_TX0_TMR_BASE + 4*0x4A) +#define JS_TX0_TMR_TINTE82_REG (JS_TX0_TMR_BASE + 4*0x4B) +#define JS_TX0_TMR_TINTF82_REG (JS_TX0_TMR_BASE + 4*0x4C) +#define JS_TX0_TMR_TINTE90_REG (JS_TX0_TMR_BASE + 4*0x4D) +#define JS_TX0_TMR_TINTF90_REG (JS_TX0_TMR_BASE + 4*0x4E) +#define JS_TX0_TMR_TINTE91_REG (JS_TX0_TMR_BASE + 4*0x4F) +#define JS_TX0_TMR_TINTF91_REG (JS_TX0_TMR_BASE + 4*0x50) +#define JS_TX0_TMR_TINTE92_REG (JS_TX0_TMR_BASE + 4*0x51) +#define JS_TX0_TMR_TINTF92_REG (JS_TX0_TMR_BASE + 4*0x52) +#define JS_TX0_TMR_TINTEA0_REG (JS_TX0_TMR_BASE + 4*0x53) +#define JS_TX0_TMR_TINTFA0_REG (JS_TX0_TMR_BASE + 4*0x54) +#define JS_TX0_TMR_TINTEA1_REG (JS_TX0_TMR_BASE + 4*0x55) +#define JS_TX0_TMR_TINTFA1_REG (JS_TX0_TMR_BASE + 4*0x56) +#define JS_TX0_TMR_TINTEA2_REG (JS_TX0_TMR_BASE + 4*0x57) +#define JS_TX0_TMR_TINTFA2_REG (JS_TX0_TMR_BASE + 4*0x58) +#define JS_TX0_TMR_TINTEB0_REG (JS_TX0_TMR_BASE + 4*0x59) +#define JS_TX0_TMR_TINTFB0_REG (JS_TX0_TMR_BASE + 4*0x5A) +#define JS_TX0_TMR_TINTEB1_REG (JS_TX0_TMR_BASE + 4*0x5B) +#define JS_TX0_TMR_TINTFB1_REG (JS_TX0_TMR_BASE + 4*0x5C) +#define JS_TX0_TMR_TINTEB2_REG (JS_TX0_TMR_BASE + 4*0x5D) +#define JS_TX0_TMR_TINTFB2_REG (JS_TX0_TMR_BASE + 4*0x5E) +#define JS_TX0_TMR_CEVENT_REG (JS_TX0_TMR_BASE + 4*0x5F) +#define JS_TX0_TMR_CMSK_REG (JS_TX0_TMR_BASE + 4*0x60) +#define JS_TX0_TMR_CINTE0_REG (JS_TX0_TMR_BASE + 4*0x61) +#define JS_TX0_TMR_CINTF0_REG (JS_TX0_TMR_BASE + 4*0x62) +#define JS_TX0_TMR_CINTE1_REG (JS_TX0_TMR_BASE + 4*0x63) +#define JS_TX0_TMR_CINTF1_REG (JS_TX0_TMR_BASE + 4*0x64) +#define JS_TX0_TMR_CINTE2_REG (JS_TX0_TMR_BASE + 4*0x65) +#define JS_TX0_TMR_CINTF2_REG (JS_TX0_TMR_BASE + 4*0x66) +#define JS_TX0_TMR_CINTE3_REG (JS_TX0_TMR_BASE + 4*0x67) +#define JS_TX0_TMR_CINTF3_REG (JS_TX0_TMR_BASE + 4*0x68) +#define JS_TX0_TMR_CINTE4_REG (JS_TX0_TMR_BASE + 4*0x69) +#define JS_TX0_TMR_CINTF4_REG (JS_TX0_TMR_BASE + 4*0x6A) +#define JS_TX0_TMR_CINTE5_REG (JS_TX0_TMR_BASE + 4*0x6B) +#define JS_TX0_TMR_CINTF5_REG (JS_TX0_TMR_BASE + 4*0x6C) +#define JS_TX0_TMR_CINTE6_REG (JS_TX0_TMR_BASE + 4*0x6D) +#define JS_TX0_TMR_CINTF6_REG (JS_TX0_TMR_BASE + 4*0x6E) +#define JS_TX0_TMR_CINTE7_REG (JS_TX0_TMR_BASE + 4*0x6F) +#define JS_TX0_TMR_CINTF7_REG (JS_TX0_TMR_BASE + 4*0x70) +#define JS_TX0_TMR_CINTE8_REG (JS_TX0_TMR_BASE + 4*0x71) +#define JS_TX0_TMR_CINTF8_REG (JS_TX0_TMR_BASE + 4*0x72) +#define JS_TX0_TMR_CINTE9_REG (JS_TX0_TMR_BASE + 4*0x73) +#define JS_TX0_TMR_CINTF9_REG (JS_TX0_TMR_BASE + 4*0x74) +#define JS_TX0_TMR_CINTEA_REG (JS_TX0_TMR_BASE + 4*0x75) +#define JS_TX0_TMR_CINTFA_REG (JS_TX0_TMR_BASE + 4*0x76) +#define JS_TX0_TMR_CINTEB_REG (JS_TX0_TMR_BASE + 4*0x77) +#define JS_TX0_TMR_CINTFB_REG (JS_TX0_TMR_BASE + 4*0x78) +#define JS_TX0_TMR_OVFL_REG (JS_TX0_TMR_BASE + 4*0x79) +#define JS_TX0_TMR_OVFH_REG (JS_TX0_TMR_BASE + 4*0x7A) +#define JS_TX0_TMR_RXEN0_0L_REG (JS_TX0_TMR_BASE + 4*0x7B) +#define JS_TX0_TMR_RXEN0_0H_REG (JS_TX0_TMR_BASE + 4*0x7C) +#define JS_TX0_TMR_RXEN0_1L_REG (JS_TX0_TMR_BASE + 4*0x7D) +#define JS_TX0_TMR_RXEN0_1H_REG (JS_TX0_TMR_BASE + 4*0x7E) +#define JS_TX0_TMR_TXEN0_0L_REG (JS_TX0_TMR_BASE + 4*0x7F) +#define JS_TX0_TMR_TXEN0_0H_REG (JS_TX0_TMR_BASE + 4*0x80) +#define JS_TX0_TMR_TXEN0_1L_REG (JS_TX0_TMR_BASE + 4*0x81) +#define JS_TX0_TMR_TXEN0_1H_REG (JS_TX0_TMR_BASE + 4*0x82) +#define JS_TX0_TMR_RXEN1_0L_REG (JS_TX0_TMR_BASE + 4*0x83) +#define JS_TX0_TMR_RXEN1_0H_REG (JS_TX0_TMR_BASE + 4*0x84) +#define JS_TX0_TMR_RXEN1_1L_REG (JS_TX0_TMR_BASE + 4*0x85) +#define JS_TX0_TMR_RXEN1_1H_REG (JS_TX0_TMR_BASE + 4*0x86) +#define JS_TX0_TMR_TXEN1_0L_REG (JS_TX0_TMR_BASE + 4*0x87) +#define JS_TX0_TMR_TXEN1_0H_REG (JS_TX0_TMR_BASE + 4*0x88) +#define JS_TX0_TMR_TXEN1_1L_REG (JS_TX0_TMR_BASE + 4*0x89) +#define JS_TX0_TMR_TXEN1_1H_REG (JS_TX0_TMR_BASE + 4*0x8A) +#define JS_TX0_TMR_RXEN2CSU0L_REG (JS_TX0_TMR_BASE + 4*0x8B) +#define JS_TX0_TMR_RXEN2CSU0H_REG (JS_TX0_TMR_BASE + 4*0x8C) +#define JS_TX0_TMR_RXEN2CSU1L_REG (JS_TX0_TMR_BASE + 4*0x8D) +#define JS_TX0_TMR_RXEN2CSU1H_REG (JS_TX0_TMR_BASE + 4*0x8E) +#define JS_TX0_TMR_TXEN2CSU0L_REG (JS_TX0_TMR_BASE + 4*0x8F) +#define JS_TX0_TMR_TXEN2CSU0H_REG (JS_TX0_TMR_BASE + 4*0x90) +#define JS_TX0_TMR_TXEN2CSU1L_REG (JS_TX0_TMR_BASE + 4*0x91) +#define JS_TX0_TMR_TXEN2CSU1H_REG (JS_TX0_TMR_BASE + 4*0x92) +#define JS_TX0_TMR_SCRATH0L_REG (JS_TX0_TMR_BASE + 4*0x93) +#define JS_TX0_TMR_SCRATH0H_REG (JS_TX0_TMR_BASE + 4*0x94) +#define JS_TX0_TMR_SCRATH1L_REG (JS_TX0_TMR_BASE + 4*0x95) +#define JS_TX0_TMR_SCRATH1H_REG (JS_TX0_TMR_BASE + 4*0x96) +#define JS_TX0_TMR_RX_SCRL_REG (JS_TX0_TMR_BASE + 4*0x97) +#define JS_TX0_TMR_RX_SCRH_REG (JS_TX0_TMR_BASE + 4*0x98) +#define JS_TX0_TMR_TX_SCRL_REG (JS_TX0_TMR_BASE + 4*0x99) +#define JS_TX0_TMR_TX_SCRH_REG (JS_TX0_TMR_BASE + 4*0x9A) +#define JS_TX0_TMR_1PPSL_REG (JS_TX0_TMR_BASE + 4*0x9B) +#define JS_TX0_TMR_1PPSH_REG (JS_TX0_TMR_BASE + 4*0x9C) +#define JS_TX0_TMR_CPRI_10MS_CTRL (JS_TX0_TMR_BASE + 4*0x9D) +#define JS_TX0_TMR_CPRI_ADJ_L (JS_TX0_TMR_BASE + 4*0x9E) +#define JS_TX0_TMR_CPRI_ADJ_H (JS_TX0_TMR_BASE + 4*0x9F) +#define JS_TX0_TMR_CPRI_10MS_CLR (JS_TX0_TMR_BASE + 4*0xA0) + +#define JS_TX0_TMR_RX_SOF0_SCR_L_REG (JS_TX0_TMR_BASE + 4*0xA1) +#define JS_TX0_TMR_RX_SOF0_SCR_H_REG (JS_TX0_TMR_BASE + 4*0xA2) +#define JS_TX0_TMR_RX_SOF1_SCR_L_REG (JS_TX0_TMR_BASE + 4*0xA3) +#define JS_TX0_TMR_RX_SOF1_SCR_H_REG (JS_TX0_TMR_BASE + 4*0xA4) +#define JS_TX0_TMR_RX_SOF2_SCR_L_REG (JS_TX0_TMR_BASE + 4*0xA5) +#define JS_TX0_TMR_RX_SOF2_SCR_H_REG (JS_TX0_TMR_BASE + 4*0xA6) +#define JS_TX0_TMR_RX_SOF3_SCR_L_REG (JS_TX0_TMR_BASE + 4*0xA7) +#define JS_TX0_TMR_RX_SOF3_SCR_H_REG (JS_TX0_TMR_BASE + 4*0xA8) +#define JS_TX0_TMR_RX_EOF0_SCR_L_REG (JS_TX0_TMR_BASE + 4*0xA9) +#define JS_TX0_TMR_RX_EOF0_SCR_H_REG (JS_TX0_TMR_BASE + 4*0xAA) +#define JS_TX0_TMR_RX_EOF1_SCR_L_REG (JS_TX0_TMR_BASE + 4*0xAB) +#define JS_TX0_TMR_RX_EOF1_SCR_H_REG (JS_TX0_TMR_BASE + 4*0xAC) +#define JS_TX0_TMR_RX_EOF2_SCR_L_REG (JS_TX0_TMR_BASE + 4*0xAD) +#define JS_TX0_TMR_RX_EOF2_SCR_H_REG (JS_TX0_TMR_BASE + 4*0xAE) +#define JS_TX0_TMR_RX_EOF3_SCR_L_REG (JS_TX0_TMR_BASE + 4*0xAF) +#define JS_TX0_TMR_RX_EOF3_SCR_H_REG (JS_TX0_TMR_BASE + 4*0xB0) +#define JS_TX0_TMR_RX_SOF_EOF_SCR_EN (JS_TX0_TMR_BASE + 4*0xB1) + + +#define JS_TX0_TMR_TnL_REG0 (JS_TX0_TMR_BASE + 4*0x100+8*0x0) +#define JS_TX0_TMR_TnL_REG1 (JS_TX0_TMR_BASE + 4*0x100+8*0x1) +#define JS_TX0_TMR_TnL_REG2 (JS_TX0_TMR_BASE + 4*0x100+8*0x2) +#define JS_TX0_TMR_TnL_REG3 (JS_TX0_TMR_BASE + 4*0x100+8*0x3) +#define JS_TX0_TMR_TnL_REG4 (JS_TX0_TMR_BASE + 4*0x100+8*0x4) +#define JS_TX0_TMR_TnL_REG5 (JS_TX0_TMR_BASE + 4*0x100+8*0x5) +#define JS_TX0_TMR_TnL_REG6 (JS_TX0_TMR_BASE + 4*0x100+8*0x6) +#define JS_TX0_TMR_TnL_REG7 (JS_TX0_TMR_BASE + 4*0x100+8*0x7) +#define JS_TX0_TMR_TnL_REG8 (JS_TX0_TMR_BASE + 4*0x100+8*0x8) +#define JS_TX0_TMR_TnL_REG9 (JS_TX0_TMR_BASE + 4*0x100+8*0x9) +#define JS_TX0_TMR_TnL_REG10 (JS_TX0_TMR_BASE + 4*0x100+8*0xa) +#define JS_TX0_TMR_TnL_REG11 (JS_TX0_TMR_BASE + 4*0x100+8*0xb) +#define JS_TX0_TMR_TnL_REG12 (JS_TX0_TMR_BASE + 4*0x100+8*0xc) +#define JS_TX0_TMR_TnL_REG13 (JS_TX0_TMR_BASE + 4*0x100+8*0xd) +#define JS_TX0_TMR_TnL_REG14 (JS_TX0_TMR_BASE + 4*0x100+8*0xe) +#define JS_TX0_TMR_TnL_REG15 (JS_TX0_TMR_BASE + 4*0x100+8*0xf) +#define JS_TX0_TMR_TnL_REG16 (JS_TX0_TMR_BASE + 4*0x100+8*0x10) +#define JS_TX0_TMR_TnL_REG17 (JS_TX0_TMR_BASE + 4*0x100+8*0x11) +#define JS_TX0_TMR_TnL_REG18 (JS_TX0_TMR_BASE + 4*0x100+8*0x12) +#define JS_TX0_TMR_TnL_REG19 (JS_TX0_TMR_BASE + 4*0x100+8*0x13) +#define JS_TX0_TMR_TnL_REG20 (JS_TX0_TMR_BASE + 4*0x100+8*0x14) +#define JS_TX0_TMR_TnL_REG21 (JS_TX0_TMR_BASE + 4*0x100+8*0x15) +#define JS_TX0_TMR_TnL_REG22 (JS_TX0_TMR_BASE + 4*0x100+8*0x16) +#define JS_TX0_TMR_TnL_REG23 (JS_TX0_TMR_BASE + 4*0x100+8*0x17) +#define JS_TX0_TMR_TnL_REG24 (JS_TX0_TMR_BASE + 4*0x100+8*0x18) +#define JS_TX0_TMR_TnL_REG25 (JS_TX0_TMR_BASE + 4*0x100+8*0x19) +#define JS_TX0_TMR_TnL_REG26 (JS_TX0_TMR_BASE + 4*0x100+8*0x1a) +#define JS_TX0_TMR_TnL_REG27 (JS_TX0_TMR_BASE + 4*0x100+8*0x1b) +#define JS_TX0_TMR_TnL_REG28 (JS_TX0_TMR_BASE + 4*0x100+8*0x1c) +#define JS_TX0_TMR_TnL_REG29 (JS_TX0_TMR_BASE + 4*0x100+8*0x1d) +#define JS_TX0_TMR_TnL_REG30 (JS_TX0_TMR_BASE + 4*0x100+8*0x1e) +#define JS_TX0_TMR_TnL_REG31 (JS_TX0_TMR_BASE + 4*0x100+8*0x1f) +#define JS_TX0_TMR_TnL_REG32 (JS_TX0_TMR_BASE + 4*0x100+8*0x20) +#define JS_TX0_TMR_TnL_REG33 (JS_TX0_TMR_BASE + 4*0x100+8*0x21) +#define JS_TX0_TMR_TnL_REG34 (JS_TX0_TMR_BASE + 4*0x100+8*0x22) +#define JS_TX0_TMR_TnL_REG35 (JS_TX0_TMR_BASE + 4*0x100+8*0x23) +#define JS_TX0_TMR_TnL_REG36 (JS_TX0_TMR_BASE + 4*0x100+8*0x24) +#define JS_TX0_TMR_TnL_REG37 (JS_TX0_TMR_BASE + 4*0x100+8*0x25) +#define JS_TX0_TMR_TnL_REG38 (JS_TX0_TMR_BASE + 4*0x100+8*0x26) +#define JS_TX0_TMR_TnL_REG39 (JS_TX0_TMR_BASE + 4*0x100+8*0x27) +#define JS_TX0_TMR_TnL_REG40 (JS_TX0_TMR_BASE + 4*0x100+8*0x28) +#define JS_TX0_TMR_TnL_REG41 (JS_TX0_TMR_BASE + 4*0x100+8*0x29) +#define JS_TX0_TMR_TnL_REG42 (JS_TX0_TMR_BASE + 4*0x100+8*0x2a) +#define JS_TX0_TMR_TnL_REG43 (JS_TX0_TMR_BASE + 4*0x100+8*0x2b) +#define JS_TX0_TMR_TnL_REG44 (JS_TX0_TMR_BASE + 4*0x100+8*0x2c) +#define JS_TX0_TMR_TnL_REG45 (JS_TX0_TMR_BASE + 4*0x100+8*0x2d) +#define JS_TX0_TMR_TnL_REG46 (JS_TX0_TMR_BASE + 4*0x100+8*0x2e) +#define JS_TX0_TMR_TnL_REG47 (JS_TX0_TMR_BASE + 4*0x100+8*0x2f) +#define JS_TX0_TMR_TnL_REG48 (JS_TX0_TMR_BASE + 4*0x100+8*0x30) +#define JS_TX0_TMR_TnL_REG49 (JS_TX0_TMR_BASE + 4*0x100+8*0x31) +#define JS_TX0_TMR_TnL_REG50 (JS_TX0_TMR_BASE + 4*0x100+8*0x32) +#define JS_TX0_TMR_TnL_REG51 (JS_TX0_TMR_BASE + 4*0x100+8*0x33) +#define JS_TX0_TMR_TnL_REG52 (JS_TX0_TMR_BASE + 4*0x100+8*0x34) +#define JS_TX0_TMR_TnL_REG53 (JS_TX0_TMR_BASE + 4*0x100+8*0x35) +#define JS_TX0_TMR_TnL_REG54 (JS_TX0_TMR_BASE + 4*0x100+8*0x36) +#define JS_TX0_TMR_TnL_REG55 (JS_TX0_TMR_BASE + 4*0x100+8*0x37) +#define JS_TX0_TMR_TnL_REG56 (JS_TX0_TMR_BASE + 4*0x100+8*0x38) +#define JS_TX0_TMR_TnL_REG57 (JS_TX0_TMR_BASE + 4*0x100+8*0x39) +#define JS_TX0_TMR_TnL_REG58 (JS_TX0_TMR_BASE + 4*0x100+8*0x3a) +#define JS_TX0_TMR_TnL_REG59 (JS_TX0_TMR_BASE + 4*0x100+8*0x3b) +#define JS_TX0_TMR_TnL_REG60 (JS_TX0_TMR_BASE + 4*0x100+8*0x3c) +#define JS_TX0_TMR_TnL_REG61 (JS_TX0_TMR_BASE + 4*0x100+8*0x3d) +#define JS_TX0_TMR_TnL_REG62 (JS_TX0_TMR_BASE + 4*0x100+8*0x3e) +#define JS_TX0_TMR_TnL_REG63 (JS_TX0_TMR_BASE + 4*0x100+8*0x3f) +#define JS_TX0_TMR_TnL_REG64 (JS_TX0_TMR_BASE + 4*0x100+8*0x40) +#define JS_TX0_TMR_TnL_REG65 (JS_TX0_TMR_BASE + 4*0x100+8*0x41) +#define JS_TX0_TMR_TnL_REG66 (JS_TX0_TMR_BASE + 4*0x100+8*0x42) +#define JS_TX0_TMR_TnL_REG67 (JS_TX0_TMR_BASE + 4*0x100+8*0x43) +#define JS_TX0_TMR_TnL_REG68 (JS_TX0_TMR_BASE + 4*0x100+8*0x44) +#define JS_TX0_TMR_TnL_REG69 (JS_TX0_TMR_BASE + 4*0x100+8*0x45) +#define JS_TX0_TMR_TnL_REG70 (JS_TX0_TMR_BASE + 4*0x100+8*0x46) +#define JS_TX0_TMR_TnL_REG71 (JS_TX0_TMR_BASE + 4*0x100+8*0x47) +#define JS_TX0_TMR_TnL_REG72 (JS_TX0_TMR_BASE + 4*0x100+8*0x48) +#define JS_TX0_TMR_TnL_REG73 (JS_TX0_TMR_BASE + 4*0x100+8*0x49) +#define JS_TX0_TMR_TnL_REG74 (JS_TX0_TMR_BASE + 4*0x100+8*0x4a) +#define JS_TX0_TMR_TnL_REG75 (JS_TX0_TMR_BASE + 4*0x100+8*0x4b) +#define JS_TX0_TMR_TnL_REG76 (JS_TX0_TMR_BASE + 4*0x100+8*0x4c) +#define JS_TX0_TMR_TnL_REG77 (JS_TX0_TMR_BASE + 4*0x100+8*0x4d) +#define JS_TX0_TMR_TnL_REG78 (JS_TX0_TMR_BASE + 4*0x100+8*0x4e) +#define JS_TX0_TMR_TnL_REG79 (JS_TX0_TMR_BASE + 4*0x100+8*0x4f) +#define JS_TX0_TMR_TnL_REG80 (JS_TX0_TMR_BASE + 4*0x100+8*0x50) +#define JS_TX0_TMR_TnL_REG81 (JS_TX0_TMR_BASE + 4*0x100+8*0x51) +#define JS_TX0_TMR_TnL_REG82 (JS_TX0_TMR_BASE + 4*0x100+8*0x52) +#define JS_TX0_TMR_TnL_REG83 (JS_TX0_TMR_BASE + 4*0x100+8*0x53) +#define JS_TX0_TMR_TnL_REG84 (JS_TX0_TMR_BASE + 4*0x100+8*0x54) +#define JS_TX0_TMR_TnL_REG85 (JS_TX0_TMR_BASE + 4*0x100+8*0x55) +#define JS_TX0_TMR_TnL_REG86 (JS_TX0_TMR_BASE + 4*0x100+8*0x56) +#define JS_TX0_TMR_TnL_REG87 (JS_TX0_TMR_BASE + 4*0x100+8*0x57) +#define JS_TX0_TMR_TnL_REG88 (JS_TX0_TMR_BASE + 4*0x100+8*0x58) +#define JS_TX0_TMR_TnL_REG89 (JS_TX0_TMR_BASE + 4*0x100+8*0x59) +#define JS_TX0_TMR_TnL_REG90 (JS_TX0_TMR_BASE + 4*0x100+8*0x5a) +#define JS_TX0_TMR_TnL_REG91 (JS_TX0_TMR_BASE + 4*0x100+8*0x5b) +#define JS_TX0_TMR_TnL_REG92 (JS_TX0_TMR_BASE + 4*0x100+8*0x5c) +#define JS_TX0_TMR_TnL_REG93 (JS_TX0_TMR_BASE + 4*0x100+8*0x5d) +#define JS_TX0_TMR_TnL_REG94 (JS_TX0_TMR_BASE + 4*0x100+8*0x5e) +#define JS_TX0_TMR_TnL_REG95 (JS_TX0_TMR_BASE + 4*0x100+8*0x5f) + + + +#define JS_TX0_TMR_TnH_REG0 (JS_TX0_TMR_BASE + 4*0x100+8*0x0 + 0x4) +#define JS_TX0_TMR_TnH_REG1 (JS_TX0_TMR_BASE + 4*0x100+8*0x1 + 0x4) +#define JS_TX0_TMR_TnH_REG2 (JS_TX0_TMR_BASE + 4*0x100+8*0x2 + 0x4) +#define JS_TX0_TMR_TnH_REG3 (JS_TX0_TMR_BASE + 4*0x100+8*0x3 + 0x4) +#define JS_TX0_TMR_TnH_REG4 (JS_TX0_TMR_BASE + 4*0x100+8*0x4 + 0x4) +#define JS_TX0_TMR_TnH_REG5 (JS_TX0_TMR_BASE + 4*0x100+8*0x5 + 0x4) +#define JS_TX0_TMR_TnH_REG6 (JS_TX0_TMR_BASE + 4*0x100+8*0x6 + 0x4) +#define JS_TX0_TMR_TnH_REG7 (JS_TX0_TMR_BASE + 4*0x100+8*0x7 + 0x4) +#define JS_TX0_TMR_TnH_REG8 (JS_TX0_TMR_BASE + 4*0x100+8*0x8 + 0x4) +#define JS_TX0_TMR_TnH_REG9 (JS_TX0_TMR_BASE + 4*0x100+8*0x9 + 0x4) +#define JS_TX0_TMR_TnH_REG10 (JS_TX0_TMR_BASE + 4*0x100+8*0xa + 0x4) +#define JS_TX0_TMR_TnH_REG11 (JS_TX0_TMR_BASE + 4*0x100+8*0xb + 0x4) +#define JS_TX0_TMR_TnH_REG12 (JS_TX0_TMR_BASE + 4*0x100+8*0xc + 0x4) +#define JS_TX0_TMR_TnH_REG13 (JS_TX0_TMR_BASE + 4*0x100+8*0xd + 0x4) +#define JS_TX0_TMR_TnH_REG14 (JS_TX0_TMR_BASE + 4*0x100+8*0xe + 0x4) +#define JS_TX0_TMR_TnH_REG15 (JS_TX0_TMR_BASE + 4*0x100+8*0xf + 0x4) +#define JS_TX0_TMR_TnH_REG16 (JS_TX0_TMR_BASE + 4*0x100+8*0x10 + 0x4) +#define JS_TX0_TMR_TnH_REG17 (JS_TX0_TMR_BASE + 4*0x100+8*0x11 + 0x4) +#define JS_TX0_TMR_TnH_REG18 (JS_TX0_TMR_BASE + 4*0x100+8*0x12 + 0x4) +#define JS_TX0_TMR_TnH_REG19 (JS_TX0_TMR_BASE + 4*0x100+8*0x13 + 0x4) +#define JS_TX0_TMR_TnH_REG20 (JS_TX0_TMR_BASE + 4*0x100+8*0x14 + 0x4) +#define JS_TX0_TMR_TnH_REG21 (JS_TX0_TMR_BASE + 4*0x100+8*0x15 + 0x4) +#define JS_TX0_TMR_TnH_REG22 (JS_TX0_TMR_BASE + 4*0x100+8*0x16 + 0x4) +#define JS_TX0_TMR_TnH_REG23 (JS_TX0_TMR_BASE + 4*0x100+8*0x17 + 0x4) +#define JS_TX0_TMR_TnH_REG24 (JS_TX0_TMR_BASE + 4*0x100+8*0x18 + 0x4) +#define JS_TX0_TMR_TnH_REG25 (JS_TX0_TMR_BASE + 4*0x100+8*0x19 + 0x4) +#define JS_TX0_TMR_TnH_REG26 (JS_TX0_TMR_BASE + 4*0x100+8*0x1a + 0x4) +#define JS_TX0_TMR_TnH_REG27 (JS_TX0_TMR_BASE + 4*0x100+8*0x1b + 0x4) +#define JS_TX0_TMR_TnH_REG28 (JS_TX0_TMR_BASE + 4*0x100+8*0x1c + 0x4) +#define JS_TX0_TMR_TnH_REG29 (JS_TX0_TMR_BASE + 4*0x100+8*0x1d + 0x4) +#define JS_TX0_TMR_TnH_REG30 (JS_TX0_TMR_BASE + 4*0x100+8*0x1e + 0x4) +#define JS_TX0_TMR_TnH_REG31 (JS_TX0_TMR_BASE + 4*0x100+8*0x1f + 0x4) +#define JS_TX0_TMR_TnH_REG32 (JS_TX0_TMR_BASE + 4*0x100+8*0x20 + 0x4) +#define JS_TX0_TMR_TnH_REG33 (JS_TX0_TMR_BASE + 4*0x100+8*0x21 + 0x4) +#define JS_TX0_TMR_TnH_REG34 (JS_TX0_TMR_BASE + 4*0x100+8*0x22 + 0x4) +#define JS_TX0_TMR_TnH_REG35 (JS_TX0_TMR_BASE + 4*0x100+8*0x23 + 0x4) +#define JS_TX0_TMR_TnH_REG36 (JS_TX0_TMR_BASE + 4*0x100+8*0x24 + 0x4) +#define JS_TX0_TMR_TnH_REG37 (JS_TX0_TMR_BASE + 4*0x100+8*0x25 + 0x4) +#define JS_TX0_TMR_TnH_REG38 (JS_TX0_TMR_BASE + 4*0x100+8*0x26 + 0x4) +#define JS_TX0_TMR_TnH_REG39 (JS_TX0_TMR_BASE + 4*0x100+8*0x27 + 0x4) +#define JS_TX0_TMR_TnH_REG40 (JS_TX0_TMR_BASE + 4*0x100+8*0x28 + 0x4) +#define JS_TX0_TMR_TnH_REG41 (JS_TX0_TMR_BASE + 4*0x100+8*0x29 + 0x4) +#define JS_TX0_TMR_TnH_REG42 (JS_TX0_TMR_BASE + 4*0x100+8*0x2a + 0x4) +#define JS_TX0_TMR_TnH_REG43 (JS_TX0_TMR_BASE + 4*0x100+8*0x2b + 0x4) +#define JS_TX0_TMR_TnH_REG44 (JS_TX0_TMR_BASE + 4*0x100+8*0x2c + 0x4) +#define JS_TX0_TMR_TnH_REG45 (JS_TX0_TMR_BASE + 4*0x100+8*0x2d + 0x4) +#define JS_TX0_TMR_TnH_REG46 (JS_TX0_TMR_BASE + 4*0x100+8*0x2e + 0x4) +#define JS_TX0_TMR_TnH_REG47 (JS_TX0_TMR_BASE + 4*0x100+8*0x2f + 0x4) +#define JS_TX0_TMR_TnH_REG48 (JS_TX0_TMR_BASE + 4*0x100+8*0x30 + 0x4) +#define JS_TX0_TMR_TnH_REG49 (JS_TX0_TMR_BASE + 4*0x100+8*0x31 + 0x4) +#define JS_TX0_TMR_TnH_REG50 (JS_TX0_TMR_BASE + 4*0x100+8*0x32 + 0x4) +#define JS_TX0_TMR_TnH_REG51 (JS_TX0_TMR_BASE + 4*0x100+8*0x33 + 0x4) +#define JS_TX0_TMR_TnH_REG52 (JS_TX0_TMR_BASE + 4*0x100+8*0x34 + 0x4) +#define JS_TX0_TMR_TnH_REG53 (JS_TX0_TMR_BASE + 4*0x100+8*0x35 + 0x4) +#define JS_TX0_TMR_TnH_REG54 (JS_TX0_TMR_BASE + 4*0x100+8*0x36 + 0x4) +#define JS_TX0_TMR_TnH_REG55 (JS_TX0_TMR_BASE + 4*0x100+8*0x37 + 0x4) +#define JS_TX0_TMR_TnH_REG56 (JS_TX0_TMR_BASE + 4*0x100+8*0x38 + 0x4) +#define JS_TX0_TMR_TnH_REG57 (JS_TX0_TMR_BASE + 4*0x100+8*0x39 + 0x4) +#define JS_TX0_TMR_TnH_REG58 (JS_TX0_TMR_BASE + 4*0x100+8*0x3a + 0x4) +#define JS_TX0_TMR_TnH_REG59 (JS_TX0_TMR_BASE + 4*0x100+8*0x3b + 0x4) +#define JS_TX0_TMR_TnH_REG60 (JS_TX0_TMR_BASE + 4*0x100+8*0x3c + 0x4) +#define JS_TX0_TMR_TnH_REG61 (JS_TX0_TMR_BASE + 4*0x100+8*0x3d + 0x4) +#define JS_TX0_TMR_TnH_REG62 (JS_TX0_TMR_BASE + 4*0x100+8*0x3e + 0x4) +#define JS_TX0_TMR_TnH_REG63 (JS_TX0_TMR_BASE + 4*0x100+8*0x3f + 0x4) +#define JS_TX0_TMR_TnH_REG64 (JS_TX0_TMR_BASE + 4*0x100+8*0x40 + 0x4) +#define JS_TX0_TMR_TnH_REG65 (JS_TX0_TMR_BASE + 4*0x100+8*0x41 + 0x4) +#define JS_TX0_TMR_TnH_REG66 (JS_TX0_TMR_BASE + 4*0x100+8*0x42 + 0x4) +#define JS_TX0_TMR_TnH_REG67 (JS_TX0_TMR_BASE + 4*0x100+8*0x43 + 0x4) +#define JS_TX0_TMR_TnH_REG68 (JS_TX0_TMR_BASE + 4*0x100+8*0x44 + 0x4) +#define JS_TX0_TMR_TnH_REG69 (JS_TX0_TMR_BASE + 4*0x100+8*0x45 + 0x4) +#define JS_TX0_TMR_TnH_REG70 (JS_TX0_TMR_BASE + 4*0x100+8*0x46 + 0x4) +#define JS_TX0_TMR_TnH_REG71 (JS_TX0_TMR_BASE + 4*0x100+8*0x47 + 0x4) +#define JS_TX0_TMR_TnH_REG72 (JS_TX0_TMR_BASE + 4*0x100+8*0x48 + 0x4) +#define JS_TX0_TMR_TnH_REG73 (JS_TX0_TMR_BASE + 4*0x100+8*0x49 + 0x4) +#define JS_TX0_TMR_TnH_REG74 (JS_TX0_TMR_BASE + 4*0x100+8*0x4a + 0x4) +#define JS_TX0_TMR_TnH_REG75 (JS_TX0_TMR_BASE + 4*0x100+8*0x4b + 0x4) +#define JS_TX0_TMR_TnH_REG76 (JS_TX0_TMR_BASE + 4*0x100+8*0x4c + 0x4) +#define JS_TX0_TMR_TnH_REG77 (JS_TX0_TMR_BASE + 4*0x100+8*0x4d + 0x4) +#define JS_TX0_TMR_TnH_REG78 (JS_TX0_TMR_BASE + 4*0x100+8*0x4e + 0x4) +#define JS_TX0_TMR_TnH_REG79 (JS_TX0_TMR_BASE + 4*0x100+8*0x4f + 0x4) +#define JS_TX0_TMR_TnH_REG80 (JS_TX0_TMR_BASE + 4*0x100+8*0x50 + 0x4) +#define JS_TX0_TMR_TnH_REG81 (JS_TX0_TMR_BASE + 4*0x100+8*0x51 + 0x4) +#define JS_TX0_TMR_TnH_REG82 (JS_TX0_TMR_BASE + 4*0x100+8*0x52 + 0x4) +#define JS_TX0_TMR_TnH_REG83 (JS_TX0_TMR_BASE + 4*0x100+8*0x53 + 0x4) +#define JS_TX0_TMR_TnH_REG84 (JS_TX0_TMR_BASE + 4*0x100+8*0x54 + 0x4) +#define JS_TX0_TMR_TnH_REG85 (JS_TX0_TMR_BASE + 4*0x100+8*0x55 + 0x4) +#define JS_TX0_TMR_TnH_REG86 (JS_TX0_TMR_BASE + 4*0x100+8*0x56 + 0x4) +#define JS_TX0_TMR_TnH_REG87 (JS_TX0_TMR_BASE + 4*0x100+8*0x57 + 0x4) +#define JS_TX0_TMR_TnH_REG88 (JS_TX0_TMR_BASE + 4*0x100+8*0x58 + 0x4) +#define JS_TX0_TMR_TnH_REG89 (JS_TX0_TMR_BASE + 4*0x100+8*0x59 + 0x4) +#define JS_TX0_TMR_TnH_REG90 (JS_TX0_TMR_BASE + 4*0x100+8*0x5a + 0x4) +#define JS_TX0_TMR_TnH_REG91 (JS_TX0_TMR_BASE + 4*0x100+8*0x5b + 0x4) +#define JS_TX0_TMR_TnH_REG92 (JS_TX0_TMR_BASE + 4*0x100+8*0x5c + 0x4) +#define JS_TX0_TMR_TnH_REG93 (JS_TX0_TMR_BASE + 4*0x100+8*0x5d + 0x4) +#define JS_TX0_TMR_TnH_REG94 (JS_TX0_TMR_BASE + 4*0x100+8*0x5e + 0x4) +#define JS_TX0_TMR_TnH_REG95 (JS_TX0_TMR_BASE + 4*0x100+8*0x5f + 0x4) + +#define JS_TX1_PIN_CTRL_REG (JS_TX1_TMR_BASE + 4*0x00) +#define JS_TX1_IO_CTRL_REG (JS_TX1_TMR_BASE + 4*0x01) +#define JS_TX1_TMR_INTC_REG (JS_TX1_TMR_BASE + 4*0x02) +#define JS_TX1_TMR_SCR_CTRL_REG (JS_TX1_TMR_BASE + 4*0x03) +#define JS_TX1_TMR_CTRL_REG (JS_TX1_TMR_BASE + 4*0x04) +#define JS_TX1_TMR_RX_SCRL_0_REG (JS_TX1_TMR_BASE + 4*0x05) +#define JS_TX1_TMR_RX_SCRH_0_REG (JS_TX1_TMR_BASE + 4*0x06) +#define JS_TX1_TMR_TX_SCRL_0_REG (JS_TX1_TMR_BASE + 4*0x07) +#define JS_TX1_TMR_TX_SCRH_0_REG (JS_TX1_TMR_BASE + 4*0x08) +#define JS_TX1_TMR_RX_SCRL_1_REG (JS_TX1_TMR_BASE + 4*0x09) +#define JS_TX1_TMR_RX_SCRH_1_REG (JS_TX1_TMR_BASE + 4*0x0A) +#define JS_TX1_TMR_TX_SCRL_1_REG (JS_TX1_TMR_BASE + 4*0x0B) +#define JS_TX1_TMR_TX_SCRH_1_REG (JS_TX1_TMR_BASE + 4*0x0C) +#define JS_TX1_TMR_TEVENT0_REG (JS_TX1_TMR_BASE + 4*0x10) +#define JS_TX1_TMR_TEVENT1_REG (JS_TX1_TMR_BASE + 4*0x11) +#define JS_TX1_TMR_TEVENT2_REG (JS_TX1_TMR_BASE + 4*0x12) +#define JS_TX1_TMR_TSCR_TRG_REG (JS_TX1_TMR_BASE + 4*0x13) +#define JS_TX1_TMR_TWREQ0_REG (JS_TX1_TMR_BASE + 4*0x14) +#define JS_TX1_TMR_TWREQ1_REG (JS_TX1_TMR_BASE + 4*0x15) +#define JS_TX1_TMR_TWREQ2_REG (JS_TX1_TMR_BASE + 4*0x16) +#define JS_TX1_TMR_TINTE00_REG (JS_TX1_TMR_BASE + 4*0x17) +#define JS_TX1_TMR_TINTF00_REG (JS_TX1_TMR_BASE + 4*0x18) +#define JS_TX1_TMR_TINTE01_REG (JS_TX1_TMR_BASE + 4*0x19) +#define JS_TX1_TMR_TINTF01_REG (JS_TX1_TMR_BASE + 4*0x1A) +#define JS_TX1_TMR_TINTE02_REG (JS_TX1_TMR_BASE + 4*0x1B) +#define JS_TX1_TMR_TINTF02_REG (JS_TX1_TMR_BASE + 4*0x1C) +#define JS_TX1_TMR_TINTE10_REG (JS_TX1_TMR_BASE + 4*0x1D) +#define JS_TX1_TMR_TINTF10_REG (JS_TX1_TMR_BASE + 4*0x1E) +#define JS_TX1_TMR_TINTE11_REG (JS_TX1_TMR_BASE + 4*0x1F) +#define JS_TX1_TMR_TINTF11_REG (JS_TX1_TMR_BASE + 4*0x20) +#define JS_TX1_TMR_TINTE12_REG (JS_TX1_TMR_BASE + 4*0x21) +#define JS_TX1_TMR_TINTF12_REG (JS_TX1_TMR_BASE + 4*0x22) +#define JS_TX1_TMR_TINTE20_REG (JS_TX1_TMR_BASE + 4*0x23) +#define JS_TX1_TMR_TINTF20_REG (JS_TX1_TMR_BASE + 4*0x24) +#define JS_TX1_TMR_TINTE21_REG (JS_TX1_TMR_BASE + 4*0x25) +#define JS_TX1_TMR_TINTF21_REG (JS_TX1_TMR_BASE + 4*0x26) +#define JS_TX1_TMR_TINTE22_REG (JS_TX1_TMR_BASE + 4*0x27) +#define JS_TX1_TMR_TINTF22_REG (JS_TX1_TMR_BASE + 4*0x28) +#define JS_TX1_TMR_TINTE30_REG (JS_TX1_TMR_BASE + 4*0x29) +#define JS_TX1_TMR_TINTF30_REG (JS_TX1_TMR_BASE + 4*0x2A) +#define JS_TX1_TMR_TINTE31_REG (JS_TX1_TMR_BASE + 4*0x2B) +#define JS_TX1_TMR_TINTF31_REG (JS_TX1_TMR_BASE + 4*0x2C) +#define JS_TX1_TMR_TINTE32_REG (JS_TX1_TMR_BASE + 4*0x2D) +#define JS_TX1_TMR_TINTF32_REG (JS_TX1_TMR_BASE + 4*0x2E) +#define JS_TX1_TMR_TINTE40_REG (JS_TX1_TMR_BASE + 4*0x2F) +#define JS_TX1_TMR_TINTF40_REG (JS_TX1_TMR_BASE + 4*0x30) +#define JS_TX1_TMR_TINTE41_REG (JS_TX1_TMR_BASE + 4*0x31) +#define JS_TX1_TMR_TINTF41_REG (JS_TX1_TMR_BASE + 4*0x32) +#define JS_TX1_TMR_TINTE42_REG (JS_TX1_TMR_BASE + 4*0x33) +#define JS_TX1_TMR_TINTF42_REG (JS_TX1_TMR_BASE + 4*0x34) +#define JS_TX1_TMR_TINTE50_REG (JS_TX1_TMR_BASE + 4*0x35) +#define JS_TX1_TMR_TINTF50_REG (JS_TX1_TMR_BASE + 4*0x36) +#define JS_TX1_TMR_TINTE51_REG (JS_TX1_TMR_BASE + 4*0x37) +#define JS_TX1_TMR_TINTF51_REG (JS_TX1_TMR_BASE + 4*0x38) +#define JS_TX1_TMR_TINTE52_REG (JS_TX1_TMR_BASE + 4*0x39) +#define JS_TX1_TMR_TINTF52_REG (JS_TX1_TMR_BASE + 4*0x3A) +#define JS_TX1_TMR_TINTE60_REG (JS_TX1_TMR_BASE + 4*0x3B) +#define JS_TX1_TMR_TINTF60_REG (JS_TX1_TMR_BASE + 4*0x3C) +#define JS_TX1_TMR_TINTE61_REG (JS_TX1_TMR_BASE + 4*0x3D) +#define JS_TX1_TMR_TINTF61_REG (JS_TX1_TMR_BASE + 4*0x3E) +#define JS_TX1_TMR_TINTE62_REG (JS_TX1_TMR_BASE + 4*0x3F) +#define JS_TX1_TMR_TINTF62_REG (JS_TX1_TMR_BASE + 4*0x40) +#define JS_TX1_TMR_TINTE70_REG (JS_TX1_TMR_BASE + 4*0x41) +#define JS_TX1_TMR_TINTF70_REG (JS_TX1_TMR_BASE + 4*0x42) +#define JS_TX1_TMR_TINTE71_REG (JS_TX1_TMR_BASE + 4*0x43) +#define JS_TX1_TMR_TINTF71_REG (JS_TX1_TMR_BASE + 4*0x44) +#define JS_TX1_TMR_TINTE72_REG (JS_TX1_TMR_BASE + 4*0x45) +#define JS_TX1_TMR_TINTF72_REG (JS_TX1_TMR_BASE + 4*0x46) +#define JS_TX1_TMR_TINTE80_REG (JS_TX1_TMR_BASE + 4*0x47) +#define JS_TX1_TMR_TINTF80_REG (JS_TX1_TMR_BASE + 4*0x48) +#define JS_TX1_TMR_TINTE81_REG (JS_TX1_TMR_BASE + 4*0x49) +#define JS_TX1_TMR_TINTF81_REG (JS_TX1_TMR_BASE + 4*0x4A) +#define JS_TX1_TMR_TINTE82_REG (JS_TX1_TMR_BASE + 4*0x4B) +#define JS_TX1_TMR_TINTF82_REG (JS_TX1_TMR_BASE + 4*0x4C) +#define JS_TX1_TMR_TINTE90_REG (JS_TX1_TMR_BASE + 4*0x4D) +#define JS_TX1_TMR_TINTF90_REG (JS_TX1_TMR_BASE + 4*0x4E) +#define JS_TX1_TMR_TINTE91_REG (JS_TX1_TMR_BASE + 4*0x4F) +#define JS_TX1_TMR_TINTF91_REG (JS_TX1_TMR_BASE + 4*0x50) +#define JS_TX1_TMR_TINTE92_REG (JS_TX1_TMR_BASE + 4*0x51) +#define JS_TX1_TMR_TINTF92_REG (JS_TX1_TMR_BASE + 4*0x52) +#define JS_TX1_TMR_TINTEA0_REG (JS_TX1_TMR_BASE + 4*0x53) +#define JS_TX1_TMR_TINTFA0_REG (JS_TX1_TMR_BASE + 4*0x54) +#define JS_TX1_TMR_TINTEA1_REG (JS_TX1_TMR_BASE + 4*0x55) +#define JS_TX1_TMR_TINTFA1_REG (JS_TX1_TMR_BASE + 4*0x56) +#define JS_TX1_TMR_TINTEA2_REG (JS_TX1_TMR_BASE + 4*0x57) +#define JS_TX1_TMR_TINTFA2_REG (JS_TX1_TMR_BASE + 4*0x58) +#define JS_TX1_TMR_TINTEB0_REG (JS_TX1_TMR_BASE + 4*0x59) +#define JS_TX1_TMR_TINTFB0_REG (JS_TX1_TMR_BASE + 4*0x5A) +#define JS_TX1_TMR_TINTEB1_REG (JS_TX1_TMR_BASE + 4*0x5B) +#define JS_TX1_TMR_TINTFB1_REG (JS_TX1_TMR_BASE + 4*0x5C) +#define JS_TX1_TMR_TINTEB2_REG (JS_TX1_TMR_BASE + 4*0x5D) +#define JS_TX1_TMR_TINTFB2_REG (JS_TX1_TMR_BASE + 4*0x5E) +#define JS_TX1_TMR_CEVENT_REG (JS_TX1_TMR_BASE + 4*0x5F) +#define JS_TX1_TMR_CMSK_REG (JS_TX1_TMR_BASE + 4*0x60) +#define JS_TX1_TMR_CINTE0_REG (JS_TX1_TMR_BASE + 4*0x61) +#define JS_TX1_TMR_CINTF0_REG (JS_TX1_TMR_BASE + 4*0x62) +#define JS_TX1_TMR_CINTE1_REG (JS_TX1_TMR_BASE + 4*0x63) +#define JS_TX1_TMR_CINTF1_REG (JS_TX1_TMR_BASE + 4*0x64) +#define JS_TX1_TMR_CINTE2_REG (JS_TX1_TMR_BASE + 4*0x65) +#define JS_TX1_TMR_CINTF2_REG (JS_TX1_TMR_BASE + 4*0x66) +#define JS_TX1_TMR_CINTE3_REG (JS_TX1_TMR_BASE + 4*0x67) +#define JS_TX1_TMR_CINTF3_REG (JS_TX1_TMR_BASE + 4*0x68) +#define JS_TX1_TMR_CINTE4_REG (JS_TX1_TMR_BASE + 4*0x69) +#define JS_TX1_TMR_CINTF4_REG (JS_TX1_TMR_BASE + 4*0x6A) +#define JS_TX1_TMR_CINTE5_REG (JS_TX1_TMR_BASE + 4*0x6B) +#define JS_TX1_TMR_CINTF5_REG (JS_TX1_TMR_BASE + 4*0x6C) +#define JS_TX1_TMR_CINTE6_REG (JS_TX1_TMR_BASE + 4*0x6D) +#define JS_TX1_TMR_CINTF6_REG (JS_TX1_TMR_BASE + 4*0x6E) +#define JS_TX1_TMR_CINTE7_REG (JS_TX1_TMR_BASE + 4*0x6F) +#define JS_TX1_TMR_CINTF7_REG (JS_TX1_TMR_BASE + 4*0x70) +#define JS_TX1_TMR_CINTE8_REG (JS_TX1_TMR_BASE + 4*0x71) +#define JS_TX1_TMR_CINTF8_REG (JS_TX1_TMR_BASE + 4*0x72) +#define JS_TX1_TMR_CINTE9_REG (JS_TX1_TMR_BASE + 4*0x73) +#define JS_TX1_TMR_CINTF9_REG (JS_TX1_TMR_BASE + 4*0x74) +#define JS_TX1_TMR_CINTEA_REG (JS_TX1_TMR_BASE + 4*0x75) +#define JS_TX1_TMR_CINTFA_REG (JS_TX1_TMR_BASE + 4*0x76) +#define JS_TX1_TMR_CINTEB_REG (JS_TX1_TMR_BASE + 4*0x77) +#define JS_TX1_TMR_CINTFB_REG (JS_TX1_TMR_BASE + 4*0x78) +#define JS_TX1_TMR_OVFL_REG (JS_TX1_TMR_BASE + 4*0x79) +#define JS_TX1_TMR_OVFH_REG (JS_TX1_TMR_BASE + 4*0x7A) +#define JS_TX1_TMR_RXEN0_0L_REG (JS_TX1_TMR_BASE + 4*0x7B) +#define JS_TX1_TMR_RXEN0_0H_REG (JS_TX1_TMR_BASE + 4*0x7C) +#define JS_TX1_TMR_RXEN0_1L_REG (JS_TX1_TMR_BASE + 4*0x7D) +#define JS_TX1_TMR_RXEN0_1H_REG (JS_TX1_TMR_BASE + 4*0x7E) +#define JS_TX1_TMR_TXEN0_0L_REG (JS_TX1_TMR_BASE + 4*0x7F) +#define JS_TX1_TMR_TXEN0_0H_REG (JS_TX1_TMR_BASE + 4*0x80) +#define JS_TX1_TMR_TXEN0_1L_REG (JS_TX1_TMR_BASE + 4*0x81) +#define JS_TX1_TMR_TXEN0_1H_REG (JS_TX1_TMR_BASE + 4*0x82) +#define JS_TX1_TMR_RXEN1_0L_REG (JS_TX1_TMR_BASE + 4*0x83) +#define JS_TX1_TMR_RXEN1_0H_REG (JS_TX1_TMR_BASE + 4*0x84) +#define JS_TX1_TMR_RXEN1_1L_REG (JS_TX1_TMR_BASE + 4*0x85) +#define JS_TX1_TMR_RXEN1_1H_REG (JS_TX1_TMR_BASE + 4*0x86) +#define JS_TX1_TMR_TXEN1_0L_REG (JS_TX1_TMR_BASE + 4*0x87) +#define JS_TX1_TMR_TXEN1_0H_REG (JS_TX1_TMR_BASE + 4*0x88) +#define JS_TX1_TMR_TXEN1_1L_REG (JS_TX1_TMR_BASE + 4*0x89) +#define JS_TX1_TMR_TXEN1_1H_REG (JS_TX1_TMR_BASE + 4*0x8A) +#define JS_TX1_TMR_RXEN2CSU0L_REG (JS_TX1_TMR_BASE + 4*0x8B) +#define JS_TX1_TMR_RXEN2CSU0H_REG (JS_TX1_TMR_BASE + 4*0x8C) +#define JS_TX1_TMR_RXEN2CSU1L_REG (JS_TX1_TMR_BASE + 4*0x8D) +#define JS_TX1_TMR_RXEN2CSU1H_REG (JS_TX1_TMR_BASE + 4*0x8E) +#define JS_TX1_TMR_TXEN2CSU0L_REG (JS_TX1_TMR_BASE + 4*0x8F) +#define JS_TX1_TMR_TXEN2CSU0H_REG (JS_TX1_TMR_BASE + 4*0x90) +#define JS_TX1_TMR_TXEN2CSU1L_REG (JS_TX1_TMR_BASE + 4*0x91) +#define JS_TX1_TMR_TXEN2CSU1H_REG (JS_TX1_TMR_BASE + 4*0x92) +#define JS_TX1_TMR_SCRATH0L_REG (JS_TX1_TMR_BASE + 4*0x93) +#define JS_TX1_TMR_SCRATH0H_REG (JS_TX1_TMR_BASE + 4*0x94) +#define JS_TX1_TMR_SCRATH1L_REG (JS_TX1_TMR_BASE + 4*0x95) +#define JS_TX1_TMR_SCRATH1H_REG (JS_TX1_TMR_BASE + 4*0x96) +#define JS_TX1_TMR_RX_SCRL_REG (JS_TX1_TMR_BASE + 4*0x97) +#define JS_TX1_TMR_RX_SCRH_REG (JS_TX1_TMR_BASE + 4*0x98) +#define JS_TX1_TMR_TX_SCRL_REG (JS_TX1_TMR_BASE + 4*0x99) +#define JS_TX1_TMR_TX_SCRH_REG (JS_TX1_TMR_BASE + 4*0x9A) +#define JS_TX1_TMR_1PPSL_REG (JS_TX1_TMR_BASE + 4*0x9B) +#define JS_TX1_TMR_1PPSH_REG (JS_TX1_TMR_BASE + 4*0x9C) +#define JS_TX1_TMR_CPRI_10MS_CTRL (JS_TX1_TMR_BASE + 4*0x9D) +#define JS_TX1_TMR_CPRI_ADJ_L (JS_TX1_TMR_BASE + 4*0x9E) +#define JS_TX1_TMR_CPRI_ADJ_H (JS_TX1_TMR_BASE + 4*0x9F) +#define JS_TX1_TMR_CPRI_10MS_CLR (JS_TX1_TMR_BASE + 4*0xA0) + +#define JS_TX1_TMR_RX_SOF0_SCR_L_REG (JS_TX1_TMR_BASE + 4*0xA1) +#define JS_TX1_TMR_RX_SOF0_SCR_H_REG (JS_TX1_TMR_BASE + 4*0xA2) +#define JS_TX1_TMR_RX_SOF1_SCR_L_REG (JS_TX1_TMR_BASE + 4*0xA3) +#define JS_TX1_TMR_RX_SOF1_SCR_H_REG (JS_TX1_TMR_BASE + 4*0xA4) +#define JS_TX1_TMR_RX_SOF2_SCR_L_REG (JS_TX1_TMR_BASE + 4*0xA5) +#define JS_TX1_TMR_RX_SOF2_SCR_H_REG (JS_TX1_TMR_BASE + 4*0xA6) +#define JS_TX1_TMR_RX_SOF3_SCR_L_REG (JS_TX1_TMR_BASE + 4*0xA7) +#define JS_TX1_TMR_RX_SOF3_SCR_H_REG (JS_TX1_TMR_BASE + 4*0xA8) +#define JS_TX1_TMR_RX_EOF0_SCR_L_REG (JS_TX1_TMR_BASE + 4*0xA9) +#define JS_TX1_TMR_RX_EOF0_SCR_H_REG (JS_TX1_TMR_BASE + 4*0xAA) +#define JS_TX1_TMR_RX_EOF1_SCR_L_REG (JS_TX1_TMR_BASE + 4*0xAB) +#define JS_TX1_TMR_RX_EOF1_SCR_H_REG (JS_TX1_TMR_BASE + 4*0xAC) +#define JS_TX1_TMR_RX_EOF2_SCR_L_REG (JS_TX1_TMR_BASE + 4*0xAD) +#define JS_TX1_TMR_RX_EOF2_SCR_H_REG (JS_TX1_TMR_BASE + 4*0xAE) +#define JS_TX1_TMR_RX_EOF3_SCR_L_REG (JS_TX1_TMR_BASE + 4*0xAF) +#define JS_TX1_TMR_RX_EOF3_SCR_H_REG (JS_TX1_TMR_BASE + 4*0xB0) +#define JS_TX1_TMR_RX_SOF_EOF_SCR_EN (JS_TX1_TMR_BASE + 4*0xB1) + + +#define JS_TX1_TMR_TnL_REG0 (JS_TX1_TMR_BASE + 4*0x100+8*0x0) +#define JS_TX1_TMR_TnL_REG1 (JS_TX1_TMR_BASE + 4*0x100+8*0x1) +#define JS_TX1_TMR_TnL_REG2 (JS_TX1_TMR_BASE + 4*0x100+8*0x2) +#define JS_TX1_TMR_TnL_REG3 (JS_TX1_TMR_BASE + 4*0x100+8*0x3) +#define JS_TX1_TMR_TnL_REG4 (JS_TX1_TMR_BASE + 4*0x100+8*0x4) +#define JS_TX1_TMR_TnL_REG5 (JS_TX1_TMR_BASE + 4*0x100+8*0x5) +#define JS_TX1_TMR_TnL_REG6 (JS_TX1_TMR_BASE + 4*0x100+8*0x6) +#define JS_TX1_TMR_TnL_REG7 (JS_TX1_TMR_BASE + 4*0x100+8*0x7) +#define JS_TX1_TMR_TnL_REG8 (JS_TX1_TMR_BASE + 4*0x100+8*0x8) +#define JS_TX1_TMR_TnL_REG9 (JS_TX1_TMR_BASE + 4*0x100+8*0x9) +#define JS_TX1_TMR_TnL_REG10 (JS_TX1_TMR_BASE + 4*0x100+8*0xa) +#define JS_TX1_TMR_TnL_REG11 (JS_TX1_TMR_BASE + 4*0x100+8*0xb) +#define JS_TX1_TMR_TnL_REG12 (JS_TX1_TMR_BASE + 4*0x100+8*0xc) +#define JS_TX1_TMR_TnL_REG13 (JS_TX1_TMR_BASE + 4*0x100+8*0xd) +#define JS_TX1_TMR_TnL_REG14 (JS_TX1_TMR_BASE + 4*0x100+8*0xe) +#define JS_TX1_TMR_TnL_REG15 (JS_TX1_TMR_BASE + 4*0x100+8*0xf) +#define JS_TX1_TMR_TnL_REG16 (JS_TX1_TMR_BASE + 4*0x100+8*0x10) +#define JS_TX1_TMR_TnL_REG17 (JS_TX1_TMR_BASE + 4*0x100+8*0x11) +#define JS_TX1_TMR_TnL_REG18 (JS_TX1_TMR_BASE + 4*0x100+8*0x12) +#define JS_TX1_TMR_TnL_REG19 (JS_TX1_TMR_BASE + 4*0x100+8*0x13) +#define JS_TX1_TMR_TnL_REG20 (JS_TX1_TMR_BASE + 4*0x100+8*0x14) +#define JS_TX1_TMR_TnL_REG21 (JS_TX1_TMR_BASE + 4*0x100+8*0x15) +#define JS_TX1_TMR_TnL_REG22 (JS_TX1_TMR_BASE + 4*0x100+8*0x16) +#define JS_TX1_TMR_TnL_REG23 (JS_TX1_TMR_BASE + 4*0x100+8*0x17) +#define JS_TX1_TMR_TnL_REG24 (JS_TX1_TMR_BASE + 4*0x100+8*0x18) +#define JS_TX1_TMR_TnL_REG25 (JS_TX1_TMR_BASE + 4*0x100+8*0x19) +#define JS_TX1_TMR_TnL_REG26 (JS_TX1_TMR_BASE + 4*0x100+8*0x1a) +#define JS_TX1_TMR_TnL_REG27 (JS_TX1_TMR_BASE + 4*0x100+8*0x1b) +#define JS_TX1_TMR_TnL_REG28 (JS_TX1_TMR_BASE + 4*0x100+8*0x1c) +#define JS_TX1_TMR_TnL_REG29 (JS_TX1_TMR_BASE + 4*0x100+8*0x1d) +#define JS_TX1_TMR_TnL_REG30 (JS_TX1_TMR_BASE + 4*0x100+8*0x1e) +#define JS_TX1_TMR_TnL_REG31 (JS_TX1_TMR_BASE + 4*0x100+8*0x1f) +#define JS_TX1_TMR_TnL_REG32 (JS_TX1_TMR_BASE + 4*0x100+8*0x20) +#define JS_TX1_TMR_TnL_REG33 (JS_TX1_TMR_BASE + 4*0x100+8*0x21) +#define JS_TX1_TMR_TnL_REG34 (JS_TX1_TMR_BASE + 4*0x100+8*0x22) +#define JS_TX1_TMR_TnL_REG35 (JS_TX1_TMR_BASE + 4*0x100+8*0x23) +#define JS_TX1_TMR_TnL_REG36 (JS_TX1_TMR_BASE + 4*0x100+8*0x24) +#define JS_TX1_TMR_TnL_REG37 (JS_TX1_TMR_BASE + 4*0x100+8*0x25) +#define JS_TX1_TMR_TnL_REG38 (JS_TX1_TMR_BASE + 4*0x100+8*0x26) +#define JS_TX1_TMR_TnL_REG39 (JS_TX1_TMR_BASE + 4*0x100+8*0x27) +#define JS_TX1_TMR_TnL_REG40 (JS_TX1_TMR_BASE + 4*0x100+8*0x28) +#define JS_TX1_TMR_TnL_REG41 (JS_TX1_TMR_BASE + 4*0x100+8*0x29) +#define JS_TX1_TMR_TnL_REG42 (JS_TX1_TMR_BASE + 4*0x100+8*0x2a) +#define JS_TX1_TMR_TnL_REG43 (JS_TX1_TMR_BASE + 4*0x100+8*0x2b) +#define JS_TX1_TMR_TnL_REG44 (JS_TX1_TMR_BASE + 4*0x100+8*0x2c) +#define JS_TX1_TMR_TnL_REG45 (JS_TX1_TMR_BASE + 4*0x100+8*0x2d) +#define JS_TX1_TMR_TnL_REG46 (JS_TX1_TMR_BASE + 4*0x100+8*0x2e) +#define JS_TX1_TMR_TnL_REG47 (JS_TX1_TMR_BASE + 4*0x100+8*0x2f) +#define JS_TX1_TMR_TnL_REG48 (JS_TX1_TMR_BASE + 4*0x100+8*0x30) +#define JS_TX1_TMR_TnL_REG49 (JS_TX1_TMR_BASE + 4*0x100+8*0x31) +#define JS_TX1_TMR_TnL_REG50 (JS_TX1_TMR_BASE + 4*0x100+8*0x32) +#define JS_TX1_TMR_TnL_REG51 (JS_TX1_TMR_BASE + 4*0x100+8*0x33) +#define JS_TX1_TMR_TnL_REG52 (JS_TX1_TMR_BASE + 4*0x100+8*0x34) +#define JS_TX1_TMR_TnL_REG53 (JS_TX1_TMR_BASE + 4*0x100+8*0x35) +#define JS_TX1_TMR_TnL_REG54 (JS_TX1_TMR_BASE + 4*0x100+8*0x36) +#define JS_TX1_TMR_TnL_REG55 (JS_TX1_TMR_BASE + 4*0x100+8*0x37) +#define JS_TX1_TMR_TnL_REG56 (JS_TX1_TMR_BASE + 4*0x100+8*0x38) +#define JS_TX1_TMR_TnL_REG57 (JS_TX1_TMR_BASE + 4*0x100+8*0x39) +#define JS_TX1_TMR_TnL_REG58 (JS_TX1_TMR_BASE + 4*0x100+8*0x3a) +#define JS_TX1_TMR_TnL_REG59 (JS_TX1_TMR_BASE + 4*0x100+8*0x3b) +#define JS_TX1_TMR_TnL_REG60 (JS_TX1_TMR_BASE + 4*0x100+8*0x3c) +#define JS_TX1_TMR_TnL_REG61 (JS_TX1_TMR_BASE + 4*0x100+8*0x3d) +#define JS_TX1_TMR_TnL_REG62 (JS_TX1_TMR_BASE + 4*0x100+8*0x3e) +#define JS_TX1_TMR_TnL_REG63 (JS_TX1_TMR_BASE + 4*0x100+8*0x3f) +#define JS_TX1_TMR_TnL_REG64 (JS_TX1_TMR_BASE + 4*0x100+8*0x40) +#define JS_TX1_TMR_TnL_REG65 (JS_TX1_TMR_BASE + 4*0x100+8*0x41) +#define JS_TX1_TMR_TnL_REG66 (JS_TX1_TMR_BASE + 4*0x100+8*0x42) +#define JS_TX1_TMR_TnL_REG67 (JS_TX1_TMR_BASE + 4*0x100+8*0x43) +#define JS_TX1_TMR_TnL_REG68 (JS_TX1_TMR_BASE + 4*0x100+8*0x44) +#define JS_TX1_TMR_TnL_REG69 (JS_TX1_TMR_BASE + 4*0x100+8*0x45) +#define JS_TX1_TMR_TnL_REG70 (JS_TX1_TMR_BASE + 4*0x100+8*0x46) +#define JS_TX1_TMR_TnL_REG71 (JS_TX1_TMR_BASE + 4*0x100+8*0x47) +#define JS_TX1_TMR_TnL_REG72 (JS_TX1_TMR_BASE + 4*0x100+8*0x48) +#define JS_TX1_TMR_TnL_REG73 (JS_TX1_TMR_BASE + 4*0x100+8*0x49) +#define JS_TX1_TMR_TnL_REG74 (JS_TX1_TMR_BASE + 4*0x100+8*0x4a) +#define JS_TX1_TMR_TnL_REG75 (JS_TX1_TMR_BASE + 4*0x100+8*0x4b) +#define JS_TX1_TMR_TnL_REG76 (JS_TX1_TMR_BASE + 4*0x100+8*0x4c) +#define JS_TX1_TMR_TnL_REG77 (JS_TX1_TMR_BASE + 4*0x100+8*0x4d) +#define JS_TX1_TMR_TnL_REG78 (JS_TX1_TMR_BASE + 4*0x100+8*0x4e) +#define JS_TX1_TMR_TnL_REG79 (JS_TX1_TMR_BASE + 4*0x100+8*0x4f) +#define JS_TX1_TMR_TnL_REG80 (JS_TX1_TMR_BASE + 4*0x100+8*0x50) +#define JS_TX1_TMR_TnL_REG81 (JS_TX1_TMR_BASE + 4*0x100+8*0x51) +#define JS_TX1_TMR_TnL_REG82 (JS_TX1_TMR_BASE + 4*0x100+8*0x52) +#define JS_TX1_TMR_TnL_REG83 (JS_TX1_TMR_BASE + 4*0x100+8*0x53) +#define JS_TX1_TMR_TnL_REG84 (JS_TX1_TMR_BASE + 4*0x100+8*0x54) +#define JS_TX1_TMR_TnL_REG85 (JS_TX1_TMR_BASE + 4*0x100+8*0x55) +#define JS_TX1_TMR_TnL_REG86 (JS_TX1_TMR_BASE + 4*0x100+8*0x56) +#define JS_TX1_TMR_TnL_REG87 (JS_TX1_TMR_BASE + 4*0x100+8*0x57) +#define JS_TX1_TMR_TnL_REG88 (JS_TX1_TMR_BASE + 4*0x100+8*0x58) +#define JS_TX1_TMR_TnL_REG89 (JS_TX1_TMR_BASE + 4*0x100+8*0x59) +#define JS_TX1_TMR_TnL_REG90 (JS_TX1_TMR_BASE + 4*0x100+8*0x5a) +#define JS_TX1_TMR_TnL_REG91 (JS_TX1_TMR_BASE + 4*0x100+8*0x5b) +#define JS_TX1_TMR_TnL_REG92 (JS_TX1_TMR_BASE + 4*0x100+8*0x5c) +#define JS_TX1_TMR_TnL_REG93 (JS_TX1_TMR_BASE + 4*0x100+8*0x5d) +#define JS_TX1_TMR_TnL_REG94 (JS_TX1_TMR_BASE + 4*0x100+8*0x5e) +#define JS_TX1_TMR_TnL_REG95 (JS_TX1_TMR_BASE + 4*0x100+8*0x5f) + + + +#define JS_TX1_TMR_TnH_REG0 (JS_TX1_TMR_BASE + 4*0x100+8*0x0 + 0x4) +#define JS_TX1_TMR_TnH_REG1 (JS_TX1_TMR_BASE + 4*0x100+8*0x1 + 0x4) +#define JS_TX1_TMR_TnH_REG2 (JS_TX1_TMR_BASE + 4*0x100+8*0x2 + 0x4) +#define JS_TX1_TMR_TnH_REG3 (JS_TX1_TMR_BASE + 4*0x100+8*0x3 + 0x4) +#define JS_TX1_TMR_TnH_REG4 (JS_TX1_TMR_BASE + 4*0x100+8*0x4 + 0x4) +#define JS_TX1_TMR_TnH_REG5 (JS_TX1_TMR_BASE + 4*0x100+8*0x5 + 0x4) +#define JS_TX1_TMR_TnH_REG6 (JS_TX1_TMR_BASE + 4*0x100+8*0x6 + 0x4) +#define JS_TX1_TMR_TnH_REG7 (JS_TX1_TMR_BASE + 4*0x100+8*0x7 + 0x4) +#define JS_TX1_TMR_TnH_REG8 (JS_TX1_TMR_BASE + 4*0x100+8*0x8 + 0x4) +#define JS_TX1_TMR_TnH_REG9 (JS_TX1_TMR_BASE + 4*0x100+8*0x9 + 0x4) +#define JS_TX1_TMR_TnH_REG10 (JS_TX1_TMR_BASE + 4*0x100+8*0xa + 0x4) +#define JS_TX1_TMR_TnH_REG11 (JS_TX1_TMR_BASE + 4*0x100+8*0xb + 0x4) +#define JS_TX1_TMR_TnH_REG12 (JS_TX1_TMR_BASE + 4*0x100+8*0xc + 0x4) +#define JS_TX1_TMR_TnH_REG13 (JS_TX1_TMR_BASE + 4*0x100+8*0xd + 0x4) +#define JS_TX1_TMR_TnH_REG14 (JS_TX1_TMR_BASE + 4*0x100+8*0xe + 0x4) +#define JS_TX1_TMR_TnH_REG15 (JS_TX1_TMR_BASE + 4*0x100+8*0xf + 0x4) +#define JS_TX1_TMR_TnH_REG16 (JS_TX1_TMR_BASE + 4*0x100+8*0x10 + 0x4) +#define JS_TX1_TMR_TnH_REG17 (JS_TX1_TMR_BASE + 4*0x100+8*0x11 + 0x4) +#define JS_TX1_TMR_TnH_REG18 (JS_TX1_TMR_BASE + 4*0x100+8*0x12 + 0x4) +#define JS_TX1_TMR_TnH_REG19 (JS_TX1_TMR_BASE + 4*0x100+8*0x13 + 0x4) +#define JS_TX1_TMR_TnH_REG20 (JS_TX1_TMR_BASE + 4*0x100+8*0x14 + 0x4) +#define JS_TX1_TMR_TnH_REG21 (JS_TX1_TMR_BASE + 4*0x100+8*0x15 + 0x4) +#define JS_TX1_TMR_TnH_REG22 (JS_TX1_TMR_BASE + 4*0x100+8*0x16 + 0x4) +#define JS_TX1_TMR_TnH_REG23 (JS_TX1_TMR_BASE + 4*0x100+8*0x17 + 0x4) +#define JS_TX1_TMR_TnH_REG24 (JS_TX1_TMR_BASE + 4*0x100+8*0x18 + 0x4) +#define JS_TX1_TMR_TnH_REG25 (JS_TX1_TMR_BASE + 4*0x100+8*0x19 + 0x4) +#define JS_TX1_TMR_TnH_REG26 (JS_TX1_TMR_BASE + 4*0x100+8*0x1a + 0x4) +#define JS_TX1_TMR_TnH_REG27 (JS_TX1_TMR_BASE + 4*0x100+8*0x1b + 0x4) +#define JS_TX1_TMR_TnH_REG28 (JS_TX1_TMR_BASE + 4*0x100+8*0x1c + 0x4) +#define JS_TX1_TMR_TnH_REG29 (JS_TX1_TMR_BASE + 4*0x100+8*0x1d + 0x4) +#define JS_TX1_TMR_TnH_REG30 (JS_TX1_TMR_BASE + 4*0x100+8*0x1e + 0x4) +#define JS_TX1_TMR_TnH_REG31 (JS_TX1_TMR_BASE + 4*0x100+8*0x1f + 0x4) +#define JS_TX1_TMR_TnH_REG32 (JS_TX1_TMR_BASE + 4*0x100+8*0x20 + 0x4) +#define JS_TX1_TMR_TnH_REG33 (JS_TX1_TMR_BASE + 4*0x100+8*0x21 + 0x4) +#define JS_TX1_TMR_TnH_REG34 (JS_TX1_TMR_BASE + 4*0x100+8*0x22 + 0x4) +#define JS_TX1_TMR_TnH_REG35 (JS_TX1_TMR_BASE + 4*0x100+8*0x23 + 0x4) +#define JS_TX1_TMR_TnH_REG36 (JS_TX1_TMR_BASE + 4*0x100+8*0x24 + 0x4) +#define JS_TX1_TMR_TnH_REG37 (JS_TX1_TMR_BASE + 4*0x100+8*0x25 + 0x4) +#define JS_TX1_TMR_TnH_REG38 (JS_TX1_TMR_BASE + 4*0x100+8*0x26 + 0x4) +#define JS_TX1_TMR_TnH_REG39 (JS_TX1_TMR_BASE + 4*0x100+8*0x27 + 0x4) +#define JS_TX1_TMR_TnH_REG40 (JS_TX1_TMR_BASE + 4*0x100+8*0x28 + 0x4) +#define JS_TX1_TMR_TnH_REG41 (JS_TX1_TMR_BASE + 4*0x100+8*0x29 + 0x4) +#define JS_TX1_TMR_TnH_REG42 (JS_TX1_TMR_BASE + 4*0x100+8*0x2a + 0x4) +#define JS_TX1_TMR_TnH_REG43 (JS_TX1_TMR_BASE + 4*0x100+8*0x2b + 0x4) +#define JS_TX1_TMR_TnH_REG44 (JS_TX1_TMR_BASE + 4*0x100+8*0x2c + 0x4) +#define JS_TX1_TMR_TnH_REG45 (JS_TX1_TMR_BASE + 4*0x100+8*0x2d + 0x4) +#define JS_TX1_TMR_TnH_REG46 (JS_TX1_TMR_BASE + 4*0x100+8*0x2e + 0x4) +#define JS_TX1_TMR_TnH_REG47 (JS_TX1_TMR_BASE + 4*0x100+8*0x2f + 0x4) +#define JS_TX1_TMR_TnH_REG48 (JS_TX1_TMR_BASE + 4*0x100+8*0x30 + 0x4) +#define JS_TX1_TMR_TnH_REG49 (JS_TX1_TMR_BASE + 4*0x100+8*0x31 + 0x4) +#define JS_TX1_TMR_TnH_REG50 (JS_TX1_TMR_BASE + 4*0x100+8*0x32 + 0x4) +#define JS_TX1_TMR_TnH_REG51 (JS_TX1_TMR_BASE + 4*0x100+8*0x33 + 0x4) +#define JS_TX1_TMR_TnH_REG52 (JS_TX1_TMR_BASE + 4*0x100+8*0x34 + 0x4) +#define JS_TX1_TMR_TnH_REG53 (JS_TX1_TMR_BASE + 4*0x100+8*0x35 + 0x4) +#define JS_TX1_TMR_TnH_REG54 (JS_TX1_TMR_BASE + 4*0x100+8*0x36 + 0x4) +#define JS_TX1_TMR_TnH_REG55 (JS_TX1_TMR_BASE + 4*0x100+8*0x37 + 0x4) +#define JS_TX1_TMR_TnH_REG56 (JS_TX1_TMR_BASE + 4*0x100+8*0x38 + 0x4) +#define JS_TX1_TMR_TnH_REG57 (JS_TX1_TMR_BASE + 4*0x100+8*0x39 + 0x4) +#define JS_TX1_TMR_TnH_REG58 (JS_TX1_TMR_BASE + 4*0x100+8*0x3a + 0x4) +#define JS_TX1_TMR_TnH_REG59 (JS_TX1_TMR_BASE + 4*0x100+8*0x3b + 0x4) +#define JS_TX1_TMR_TnH_REG60 (JS_TX1_TMR_BASE + 4*0x100+8*0x3c + 0x4) +#define JS_TX1_TMR_TnH_REG61 (JS_TX1_TMR_BASE + 4*0x100+8*0x3d + 0x4) +#define JS_TX1_TMR_TnH_REG62 (JS_TX1_TMR_BASE + 4*0x100+8*0x3e + 0x4) +#define JS_TX1_TMR_TnH_REG63 (JS_TX1_TMR_BASE + 4*0x100+8*0x3f + 0x4) +#define JS_TX1_TMR_TnH_REG64 (JS_TX1_TMR_BASE + 4*0x100+8*0x40 + 0x4) +#define JS_TX1_TMR_TnH_REG65 (JS_TX1_TMR_BASE + 4*0x100+8*0x41 + 0x4) +#define JS_TX1_TMR_TnH_REG66 (JS_TX1_TMR_BASE + 4*0x100+8*0x42 + 0x4) +#define JS_TX1_TMR_TnH_REG67 (JS_TX1_TMR_BASE + 4*0x100+8*0x43 + 0x4) +#define JS_TX1_TMR_TnH_REG68 (JS_TX1_TMR_BASE + 4*0x100+8*0x44 + 0x4) +#define JS_TX1_TMR_TnH_REG69 (JS_TX1_TMR_BASE + 4*0x100+8*0x45 + 0x4) +#define JS_TX1_TMR_TnH_REG70 (JS_TX1_TMR_BASE + 4*0x100+8*0x46 + 0x4) +#define JS_TX1_TMR_TnH_REG71 (JS_TX1_TMR_BASE + 4*0x100+8*0x47 + 0x4) +#define JS_TX1_TMR_TnH_REG72 (JS_TX1_TMR_BASE + 4*0x100+8*0x48 + 0x4) +#define JS_TX1_TMR_TnH_REG73 (JS_TX1_TMR_BASE + 4*0x100+8*0x49 + 0x4) +#define JS_TX1_TMR_TnH_REG74 (JS_TX1_TMR_BASE + 4*0x100+8*0x4a + 0x4) +#define JS_TX1_TMR_TnH_REG75 (JS_TX1_TMR_BASE + 4*0x100+8*0x4b + 0x4) +#define JS_TX1_TMR_TnH_REG76 (JS_TX1_TMR_BASE + 4*0x100+8*0x4c + 0x4) +#define JS_TX1_TMR_TnH_REG77 (JS_TX1_TMR_BASE + 4*0x100+8*0x4d + 0x4) +#define JS_TX1_TMR_TnH_REG78 (JS_TX1_TMR_BASE + 4*0x100+8*0x4e + 0x4) +#define JS_TX1_TMR_TnH_REG79 (JS_TX1_TMR_BASE + 4*0x100+8*0x4f + 0x4) +#define JS_TX1_TMR_TnH_REG80 (JS_TX1_TMR_BASE + 4*0x100+8*0x50 + 0x4) +#define JS_TX1_TMR_TnH_REG81 (JS_TX1_TMR_BASE + 4*0x100+8*0x51 + 0x4) +#define JS_TX1_TMR_TnH_REG82 (JS_TX1_TMR_BASE + 4*0x100+8*0x52 + 0x4) +#define JS_TX1_TMR_TnH_REG83 (JS_TX1_TMR_BASE + 4*0x100+8*0x53 + 0x4) +#define JS_TX1_TMR_TnH_REG84 (JS_TX1_TMR_BASE + 4*0x100+8*0x54 + 0x4) +#define JS_TX1_TMR_TnH_REG85 (JS_TX1_TMR_BASE + 4*0x100+8*0x55 + 0x4) +#define JS_TX1_TMR_TnH_REG86 (JS_TX1_TMR_BASE + 4*0x100+8*0x56 + 0x4) +#define JS_TX1_TMR_TnH_REG87 (JS_TX1_TMR_BASE + 4*0x100+8*0x57 + 0x4) +#define JS_TX1_TMR_TnH_REG88 (JS_TX1_TMR_BASE + 4*0x100+8*0x58 + 0x4) +#define JS_TX1_TMR_TnH_REG89 (JS_TX1_TMR_BASE + 4*0x100+8*0x59 + 0x4) +#define JS_TX1_TMR_TnH_REG90 (JS_TX1_TMR_BASE + 4*0x100+8*0x5a + 0x4) +#define JS_TX1_TMR_TnH_REG91 (JS_TX1_TMR_BASE + 4*0x100+8*0x5b + 0x4) +#define JS_TX1_TMR_TnH_REG92 (JS_TX1_TMR_BASE + 4*0x100+8*0x5c + 0x4) +#define JS_TX1_TMR_TnH_REG93 (JS_TX1_TMR_BASE + 4*0x100+8*0x5d + 0x4) +#define JS_TX1_TMR_TnH_REG94 (JS_TX1_TMR_BASE + 4*0x100+8*0x5e + 0x4) +#define JS_TX1_TMR_TnH_REG95 (JS_TX1_TMR_BASE + 4*0x100+8*0x5f + 0x4) + + +#define JS_204B_RX0_SUBCTRL_SH_LOCK (JS_204B_RX0_SUBCTRL_BASE + 0x014) +#define JS_204B_RX0_SUBCTRL_EMB_LOCK (JS_204B_RX0_SUBCTRL_BASE + 0x018) +#define JS_204B_RX0_SUBCTRL_RX_CMD (JS_204B_RX0_SUBCTRL_BASE + 0x020) +#define JS_204B_RX0_SUBCTRL_CMD_ERR_CNT_0 (JS_204B_RX0_SUBCTRL_BASE + 0x024) +#define JS_204B_RX0_SUBCTRL_CMD_ERR_CNT_1 (JS_204B_RX0_SUBCTRL_BASE + 0x028) +#define JS_204B_RX0_SUBCTRL_CMD_VALID_APB_CNT (JS_204B_RX0_SUBCTRL_BASE + 0x02C) +#define JS_204B_RX0_SUBCTRL_SYSREF_CNT (JS_204B_RX0_SUBCTRL_BASE + 0x030) +#define JS_204B_RX0_SUBCTRL_SAM_IF_RECORD (JS_204B_RX0_SUBCTRL_BASE + 0x034) +#define JS_204B_RX0_SUBCTRL_MAP_IF_RECORD (JS_204B_RX0_SUBCTRL_BASE + 0x038) +#define JS_204B_RX0_SUBCTRL_SERDES_IF_RECORD (JS_204B_RX0_SUBCTRL_BASE + 0x03C) +#define JS_204B_RX0_SUBCTRL_SYSREF_RX_SEL (JS_204B_RX0_SUBCTRL_BASE + 0x040) +#define JS_204B_RX0_SUBCTRL_SYNC_B_SEL (JS_204B_RX0_SUBCTRL_BASE + 0x044) +#define JS_204B_RX0_SUBCTRL_INTR_MASK (JS_204B_RX0_SUBCTRL_BASE + 0x048) +#define JS_204B_RX0_SUBCTRL_INTR_TH_0 (JS_204B_RX0_SUBCTRL_BASE + 0x04C) +#define JS_204B_RX0_SUBCTRL_INTR_TH_1 (JS_204B_RX0_SUBCTRL_BASE + 0x050) +#define JS_204B_RX0_SUBCTRL_INTR_TH_2 (JS_204B_RX0_SUBCTRL_BASE + 0x054) +#define JS_204B_RX0_SUBCTRL_INTR_TH_3 (JS_204B_RX0_SUBCTRL_BASE + 0x058) +#define JS_204B_RX0_SUBCTRL_SYSREF (JS_204B_RX0_SUBCTRL_BASE + 0x05C) +#define JS_204B_RX0_SUBCTRL_INTR_FLAG (JS_204B_RX0_SUBCTRL_BASE + 0x060) +#define JS_204B_RX0_SUBCTRL_SAM_ERR_CNT (JS_204B_RX0_SUBCTRL_BASE + 0x064) +#define JS_204B_RX0_SUBCTRL_TL_TEST_MODE_CNT (JS_204B_RX0_SUBCTRL_BASE + 0x068) +#define JS_204B_RX0_SUBCTRL_SAM_IF_RECORD_DATA (JS_204B_RX0_SUBCTRL_BASE + 0x0800) +#define JS_204B_RX0_SUBCTRL_MAP_IF_RECORD_DATA (JS_204B_RX0_SUBCTRL_BASE + 0x1000) +#define JS_204B_RX0_SUBCTRL_SERDES_IF_RECORD_DATA (JS_204B_RX0_SUBCTRL_BASE + 0x1400) + +#define JS_204B_RX1_SUBCTRL_SH_LOCK (JS_204B_RX1_SUBCTRL_BASE + 0x014) +#define JS_204B_RX1_SUBCTRL_EMB_LOCK (JS_204B_RX1_SUBCTRL_BASE + 0x018) +#define JS_204B_RX1_SUBCTRL_RX_CMD (JS_204B_RX1_SUBCTRL_BASE + 0x020) +#define JS_204B_RX1_SUBCTRL_CMD_ERR_CNT_0 (JS_204B_RX1_SUBCTRL_BASE + 0x024) +#define JS_204B_RX1_SUBCTRL_CMD_ERR_CNT_1 (JS_204B_RX1_SUBCTRL_BASE + 0x028) +#define JS_204B_RX1_SUBCTRL_CMD_VALID_APB_CNT (JS_204B_RX1_SUBCTRL_BASE + 0x02C) +#define JS_204B_RX1_SUBCTRL_SYSREF_CNT (JS_204B_RX1_SUBCTRL_BASE + 0x030) +#define JS_204B_RX1_SUBCTRL_SAM_IF_RECORD (JS_204B_RX1_SUBCTRL_BASE + 0x034) +#define JS_204B_RX1_SUBCTRL_MAP_IF_RECORD (JS_204B_RX1_SUBCTRL_BASE + 0x038) +#define JS_204B_RX1_SUBCTRL_SERDES_IF_RECORD (JS_204B_RX1_SUBCTRL_BASE + 0x03C) +#define JS_204B_RX1_SUBCTRL_SYSREF_RX_SEL (JS_204B_RX1_SUBCTRL_BASE + 0x040) +#define JS_204B_RX1_SUBCTRL_SYNC_B_SEL (JS_204B_RX1_SUBCTRL_BASE + 0x044) +#define JS_204B_RX1_SUBCTRL_INTR_MASK (JS_204B_RX1_SUBCTRL_BASE + 0x048) +#define JS_204B_RX1_SUBCTRL_INTR_TH_0 (JS_204B_RX1_SUBCTRL_BASE + 0x04C) +#define JS_204B_RX1_SUBCTRL_INTR_TH_1 (JS_204B_RX1_SUBCTRL_BASE + 0x050) +#define JS_204B_RX1_SUBCTRL_INTR_TH_2 (JS_204B_RX1_SUBCTRL_BASE + 0x054) +#define JS_204B_RX1_SUBCTRL_INTR_TH_3 (JS_204B_RX1_SUBCTRL_BASE + 0x058) +#define JS_204B_RX1_SUBCTRL_SYSREF (JS_204B_RX1_SUBCTRL_BASE + 0x05C) +#define JS_204B_RX1_SUBCTRL_INTR_FLAG (JS_204B_RX1_SUBCTRL_BASE + 0x060) +#define JS_204B_RX1_SUBCTRL_SAM_ERR_CNT (JS_204B_RX1_SUBCTRL_BASE + 0x064) +#define JS_204B_RX1_SUBCTRL_TL_TEST_MODE_CNT (JS_204B_RX1_SUBCTRL_BASE + 0x068) +#define JS_204B_RX1_SUBCTRL_SAM_IF_RECORD_DATA (JS_204B_RX1_SUBCTRL_BASE + 0x0800) +#define JS_204B_RX1_SUBCTRL_MAP_IF_RECORD_DATA (JS_204B_RX1_SUBCTRL_BASE + 0x1000) +#define JS_204B_RX1_SUBCTRL_SERDES_IF_RECORD_DATA (JS_204B_RX1_SUBCTRL_BASE + 0x1800) + +#define JS_204B_TX_SUBCTRL_SAM_IF_RECORD_EN (JS_204B_TX_SUBCTRL_BASE + 0x014) +#define JS_204B_TX_SUBCTRL_SERDES_IF_RECORD_EN (JS_204B_TX_SUBCTRL_BASE + 0x018) +#define JS_204B_TX_SUBCTRL_TRANS_TH (JS_204B_TX_SUBCTRL_BASE + 0x01C) +#define JS_204B_TX_SUBCTRL_SYSREF_TX_SEL (JS_204B_TX_SUBCTRL_BASE + 0x020) +#define JS_204B_TX_SUBCTRL_SYNC_B_SEL (JS_204B_TX_SUBCTRL_BASE + 0x024) +#define JS_204B_TX_SUBCTRL_TX_CMD (JS_204B_TX_SUBCTRL_BASE + 0x028) +#define JS_204B_TX_SUBCTRL_CMD_APB_VALID_CNT (JS_204B_TX_SUBCTRL_BASE + 0x02C) +#define JS_204B_TX_SUBCTRL_CMD_SENT_CNT (JS_204B_TX_SUBCTRL_BASE + 0x030) +#define JS_204B_TX_SUBCTRL_SAM_DATA_IDLE_ARRAY0 (JS_204B_TX_SUBCTRL_BASE + 0x038) +#define JS_204B_TX_SUBCTRL_SAM_DATA_IDLE_ARRAY1 (JS_204B_TX_SUBCTRL_BASE + 0x03C) +#define JS_204B_TX_SUBCTRL_SAM_DATA_IDLE_ARRAY2 (JS_204B_TX_SUBCTRL_BASE + 0x040) +#define JS_204B_TX_SUBCTRL_SAM_DATA_IDLE_ARRAY3 (JS_204B_TX_SUBCTRL_BASE + 0x044) +#define JS_204B_TX_SUBCTRL_SAM_DATA_IDLE_ARRAY4 (JS_204B_TX_SUBCTRL_BASE + 0x048) +#define JS_204B_TX_SUBCTRL_SAM_DATA_IDLE_ARRAY5 (JS_204B_TX_SUBCTRL_BASE + 0x04C) +#define JS_204B_TX_SUBCTRL_SAM_DATA_IDLE_ARRAY6 (JS_204B_TX_SUBCTRL_BASE + 0x050) +#define JS_204B_TX_SUBCTRL_SAM_DATA_IDLE_ARRAY7 (JS_204B_TX_SUBCTRL_BASE + 0x054) +#define JS_204B_TX_SUBCTRL_SAM_DATA_IDLE_CNT (JS_204B_TX_SUBCTRL_BASE + 0x058) +#define JS_204B_TX_SUBCTRL_SAM_IF_RECORD_DONE (JS_204B_TX_SUBCTRL_BASE + 0x05C) +#define JS_204B_TX_SUBCTRL_SERDES_IF_RECORD_DONE (JS_204B_TX_SUBCTRL_BASE + 0x060) +#define JS_204B_TX_SUBCTRL_SAM_IF_RECORD_DATA (JS_204B_TX_SUBCTRL_BASE + 0x800) +#define JS_204B_TX_SUBCTRL_SERDES_IF_RECORD_DATA (JS_204B_TX_SUBCTRL_BASE + 0x1000) + +#define JS_204C_RX0_SUBCTRL_SH_LOCK (JS_204C_RX0_SUBCTRL_BASE + 0x014) +#define JS_204C_RX0_SUBCTRL_EMB_LOCK (JS_204C_RX0_SUBCTRL_BASE + 0x018) +#define JS_204C_RX0_SUBCTRL_RX_CMD (JS_204C_RX0_SUBCTRL_BASE + 0x020) +#define JS_204C_RX0_SUBCTRL_CMD_ERR_CNT_0 (JS_204C_RX0_SUBCTRL_BASE + 0x024) +#define JS_204C_RX0_SUBCTRL_CMD_ERR_CNT_1 (JS_204C_RX0_SUBCTRL_BASE + 0x028) +#define JS_204C_RX0_SUBCTRL_CMD_VALID_APB_CNT (JS_204C_RX0_SUBCTRL_BASE + 0x02C) +#define JS_204C_RX0_SUBCTRL_SYSREF_CNT (JS_204C_RX0_SUBCTRL_BASE + 0x030) +#define JS_204C_RX0_SUBCTRL_SAM_IF_RECORD (JS_204C_RX0_SUBCTRL_BASE + 0x034) +#define JS_204C_RX0_SUBCTRL_MAP_IF_RECORD (JS_204C_RX0_SUBCTRL_BASE + 0x038) +#define JS_204C_RX0_SUBCTRL_SERDES_IF_RECORD (JS_204C_RX0_SUBCTRL_BASE + 0x03C) +#define JS_204C_RX0_SUBCTRL_SYSREF_RX_SEL (JS_204C_RX0_SUBCTRL_BASE + 0x040) +#define JS_204C_RX0_SUBCTRL_SYNC_B_SEL (JS_204C_RX0_SUBCTRL_BASE + 0x044) +#define JS_204C_RX0_SUBCTRL_INTR_MASK (JS_204C_RX0_SUBCTRL_BASE + 0x048) +#define JS_204C_RX0_SUBCTRL_INTR_TH_0 (JS_204C_RX0_SUBCTRL_BASE + 0x04C) +#define JS_204C_RX0_SUBCTRL_INTR_TH_1 (JS_204C_RX0_SUBCTRL_BASE + 0x050) +#define JS_204C_RX0_SUBCTRL_INTR_TH_2 (JS_204C_RX0_SUBCTRL_BASE + 0x054) +#define JS_204C_RX0_SUBCTRL_INTR_TH_3 (JS_204C_RX0_SUBCTRL_BASE + 0x058) +#define JS_204C_RX0_SUBCTRL_SYSREF (JS_204C_RX0_SUBCTRL_BASE + 0x05C) +#define JS_204C_RX0_SUBCTRL_INTR_FLAG (JS_204C_RX0_SUBCTRL_BASE + 0x060) +#define JS_204C_RX0_SUBCTRL_SAM_ERR_CNT (JS_204C_RX0_SUBCTRL_BASE + 0x064) +#define JS_204C_RX0_SUBCTRL_TL_TEST_MODE_CNT (JS_204C_RX0_SUBCTRL_BASE + 0x068) +#define JS_204C_RX0_SUBCTRL_SAM_IF_RECORD_DATA (JS_204C_RX0_SUBCTRL_BASE + 0x0800) +#define JS_204C_RX0_SUBCTRL_MAP_IF_RECORD_DATA (JS_204C_RX0_SUBCTRL_BASE + 0x1000) +#define JS_204C_RX0_SUBCTRL_SERDES_IF_RECORD_DATA (JS_204C_RX0_SUBCTRL_BASE + 0x1400) + +#define JS_204C_RX1_SUBCTRL_SH_LOCK (JS_204C_RX1_SUBCTRL_BASE + 0x014) +#define JS_204C_RX1_SUBCTRL_EMB_LOCK (JS_204C_RX1_SUBCTRL_BASE + 0x018) +#define JS_204C_RX1_SUBCTRL_RX_CMD (JS_204C_RX1_SUBCTRL_BASE + 0x020) +#define JS_204C_RX1_SUBCTRL_CMD_ERR_CNT_0 (JS_204C_RX1_SUBCTRL_BASE + 0x024) +#define JS_204C_RX1_SUBCTRL_CMD_ERR_CNT_1 (JS_204C_RX1_SUBCTRL_BASE + 0x028) +#define JS_204C_RX1_SUBCTRL_CMD_VALID_APB_CNT (JS_204C_RX1_SUBCTRL_BASE + 0x02C) +#define JS_204C_RX1_SUBCTRL_SYSREF_CNT (JS_204C_RX1_SUBCTRL_BASE + 0x030) +#define JS_204C_RX1_SUBCTRL_SAM_IF_RECORD (JS_204C_RX1_SUBCTRL_BASE + 0x034) +#define JS_204C_RX1_SUBCTRL_MAP_IF_RECORD (JS_204C_RX1_SUBCTRL_BASE + 0x038) +#define JS_204C_RX1_SUBCTRL_SERDES_IF_RECORD (JS_204C_RX1_SUBCTRL_BASE + 0x03C) +#define JS_204C_RX1_SUBCTRL_SYSREF_RX_SEL (JS_204C_RX1_SUBCTRL_BASE + 0x040) +#define JS_204C_RX1_SUBCTRL_SYNC_B_SEL (JS_204C_RX1_SUBCTRL_BASE + 0x044) +#define JS_204C_RX1_SUBCTRL_INTR_MASK (JS_204C_RX1_SUBCTRL_BASE + 0x048) +#define JS_204C_RX1_SUBCTRL_INTR_TH_0 (JS_204C_RX1_SUBCTRL_BASE + 0x04C) +#define JS_204C_RX1_SUBCTRL_INTR_TH_1 (JS_204C_RX1_SUBCTRL_BASE + 0x050) +#define JS_204C_RX1_SUBCTRL_INTR_TH_2 (JS_204C_RX1_SUBCTRL_BASE + 0x054) +#define JS_204C_RX1_SUBCTRL_INTR_TH_3 (JS_204C_RX1_SUBCTRL_BASE + 0x058) +#define JS_204C_RX1_SUBCTRL_SYSREF (JS_204C_RX1_SUBCTRL_BASE + 0x05C) +#define JS_204C_RX1_SUBCTRL_INTR_FLAG (JS_204C_RX1_SUBCTRL_BASE + 0x060) +#define JS_204C_RX1_SUBCTRL_SAM_ERR_CNT (JS_204C_RX1_SUBCTRL_BASE + 0x064) +#define JS_204C_RX1_SUBCTRL_TL_TEST_MODE_CNT (JS_204C_RX1_SUBCTRL_BASE + 0x068) +#define JS_204C_RX1_SUBCTRL_SAM_IF_RECORD_DATA (JS_204C_RX1_SUBCTRL_BASE + 0x0800) +#define JS_204C_RX1_SUBCTRL_MAP_IF_RECORD_DATA (JS_204C_RX1_SUBCTRL_BASE + 0x1000) +#define JS_204C_RX1_SUBCTRL_SERDES_IF_RECORD_DATA (JS_204C_RX1_SUBCTRL_BASE + 0x1800) + +#define JS_204C_TX_SUBCTRL_SAM_IF_RECORD_EN (JS_204C_TX_SUBCTRL_BASE + 0x014) +#define JS_204C_TX_SUBCTRL_SERDES_IF_RECORD_EN (JS_204C_TX_SUBCTRL_BASE + 0x018) +#define JS_204C_TX_SUBCTRL_TRANS_TH (JS_204C_TX_SUBCTRL_BASE + 0x01C) +#define JS_204C_TX_SUBCTRL_SYSREF_TX_SEL (JS_204C_TX_SUBCTRL_BASE + 0x020) +#define JS_204C_TX_SUBCTRL_SYNC_B_SEL (JS_204C_TX_SUBCTRL_BASE + 0x024) +#define JS_204C_TX_SUBCTRL_TX_CMD (JS_204C_TX_SUBCTRL_BASE + 0x028) +#define JS_204C_TX_SUBCTRL_CMD_APB_VALID_CNT (JS_204C_TX_SUBCTRL_BASE + 0x02C) +#define JS_204C_TX_SUBCTRL_CMD_SENT_CNT (JS_204C_TX_SUBCTRL_BASE + 0x030) +#define JS_204C_TX_SUBCTRL_SAM_DATA_IDLE_ARRAY0 (JS_204C_TX_SUBCTRL_BASE + 0x038) +#define JS_204C_TX_SUBCTRL_SAM_DATA_IDLE_ARRAY1 (JS_204C_TX_SUBCTRL_BASE + 0x03C) +#define JS_204C_TX_SUBCTRL_SAM_DATA_IDLE_ARRAY2 (JS_204C_TX_SUBCTRL_BASE + 0x040) +#define JS_204C_TX_SUBCTRL_SAM_DATA_IDLE_ARRAY3 (JS_204C_TX_SUBCTRL_BASE + 0x044) +#define JS_204C_TX_SUBCTRL_SAM_DATA_IDLE_ARRAY4 (JS_204C_TX_SUBCTRL_BASE + 0x048) +#define JS_204C_TX_SUBCTRL_SAM_DATA_IDLE_ARRAY5 (JS_204C_TX_SUBCTRL_BASE + 0x04C) +#define JS_204C_TX_SUBCTRL_SAM_DATA_IDLE_ARRAY6 (JS_204C_TX_SUBCTRL_BASE + 0x050) +#define JS_204C_TX_SUBCTRL_SAM_DATA_IDLE_ARRAY7 (JS_204C_TX_SUBCTRL_BASE + 0x054) +#define JS_204C_TX_SUBCTRL_SAM_DATA_IDLE_CNT (JS_204C_TX_SUBCTRL_BASE + 0x058) +#define JS_204C_TX_SUBCTRL_SAM_IF_RECORD_DONE (JS_204C_TX_SUBCTRL_BASE + 0x05C) +#define JS_204C_TX_SUBCTRL_SERDES_IF_RECORD_DONE (JS_204C_TX_SUBCTRL_BASE + 0x060) +#define JS_204C_TX_SUBCTRL_SAM_IF_RECORD_DATA (JS_204C_TX_SUBCTRL_BASE + 0x800) +#define JS_204C_TX_SUBCTRL_SERDES_IF_RECORD_DATA (JS_204C_TX_SUBCTRL_BASE + 0x1000) + + +#endif // __JESD204_H__ + diff --git a/driver/rfic/ucp/base/inc/ucp_hardware.h b/driver/rfic/ucp/base/inc/ucp_hardware.h new file mode 100644 index 0000000..e6aec56 --- /dev/null +++ b/driver/rfic/ucp/base/inc/ucp_hardware.h @@ -0,0 +1,64 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_api_hardware.h +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-03-04 14:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef UCP_API_HARDWARE_H_ +#define UCP_API_HARDWARE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +// ARM & UCP share memery addr +#define UCP_SHAREPARA_BASE (0x0a4F2000) + +#define SERDES_INIT_FLAG_ADDR (UCP_SHAREPARA_BASE + 0x0240) // work step + +#define GPIO_ULDELAY2UCP_ADDR (UCP_SHAREPARA_BASE + 0x0238) // uldelay +#define GPIO_DLDELAY2UCP_ADDR (UCP_SHAREPARA_BASE + 0x023C) // dldelay + +#define GPIO_VERSION2UCP_ADDR (UCP_SHAREPARA_BASE + 0x1000) // version + +#define UCP_JESDPARA_RX0 (UCP_SHAREPARA_BASE + 0x1010) // rx0 para +#define UCP_CLKPARA0_RX0 (UCP_SHAREPARA_BASE + 0x1020) +#define UCP_CLKPARA1_RX0 (UCP_SHAREPARA_BASE + 0x1024) +#define UCP_JESDPARA_RX1 (UCP_SHAREPARA_BASE + 0x1030) // rx1 para +#define UCP_CLKPARA0_RX1 (UCP_SHAREPARA_BASE + 0x1040) +#define UCP_CLKPARA1_RX1 (UCP_SHAREPARA_BASE + 0x1044) +#define UCP_JESDPARA_TX0 (UCP_SHAREPARA_BASE + 0x1050) // tx0 para +#define UCP_CLKPARA0_TX0 (UCP_SHAREPARA_BASE + 0x1060) +#define UCP_CLKPARA1_TX0 (UCP_SHAREPARA_BASE + 0x1064) +#define UCP_JESDPARA_TX1 (UCP_SHAREPARA_BASE + 0x1070) // tx1 para +#define UCP_CLKPARA0_TX1 (UCP_SHAREPARA_BASE + 0x1080) +#define UCP_CLKPARA1_TX1 (UCP_SHAREPARA_BASE + 0x1084) + +#define GPIO_TRIGBIT2UCP_ADDR (UCP_SHAREPARA_BASE + 0x1100) // TRIG + +#define GPIO_TXTRXBIT2UCP_ADDR (UCP_SHAREPARA_BASE + 0x1120) // TX trx +#define GPIO_TXRFBIT2UCP_ADDR (UCP_SHAREPARA_BASE + 0x1140) // TX rf +#define GPIO_TXSWBIT2UCP_ADDR (UCP_SHAREPARA_BASE + 0x1160) // TX SW + +#define GPIO_RXTRXBIT2UCP_ADDR (UCP_SHAREPARA_BASE + 0x1180) // RX trx +#define GPIO_RXRFBIT2UCP_ADDR (UCP_SHAREPARA_BASE + 0x11A0) // RX rf +#define GPIO_RXSWBIT2UCP_ADDR (UCP_SHAREPARA_BASE + 0x11C0) // RX sw + + +#define GPIO_ORXTRXBIT2UCP_ADDR (UCP_SHAREPARA_BASE + 0x11E0) // ORX trx +#define GPIO_ORXRFBIT2UCP_ADDR (UCP_SHAREPARA_BASE + 0x1200) // ORX rf +#define GPIO_ORXSWBIT2UCP_ADDR (UCP_SHAREPARA_BASE + 0x1220) // ORX sw + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef UCP_API_HARDWARE_H_ */ + diff --git a/driver/rfic/ucp/base/inc/ucp_jesd_gpio.h b/driver/rfic/ucp/base/inc/ucp_jesd_gpio.h new file mode 100644 index 0000000..a285af4 --- /dev/null +++ b/driver/rfic/ucp/base/inc/ucp_jesd_gpio.h @@ -0,0 +1,121 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_jesd_gpio.h (ap side) +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2022-09-08 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef __UCP_JESD_GPIO__ +#define __UCP_JESD_GPIO__ + +#include "ucp_api_jesd.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define GPIO_INDEX_MAX (64) +#define UCP_GPIO(port, pin) ((tUcpGpioRegTable_t *)&pUcpGpioTable[port][pin]) + +typedef struct tUcpGpioRegTable_tag { + uint32_t pinMuxReg; + uint32_t muxValue; + uint32_t muxMask; + uint32_t dirReg; + uint32_t valueReg; + uint32_t bitMask; +} tUcpGpioRegTable_t; + +typedef struct tGpioInfRegTable_tag { + uint8_t index; + uint8_t enable; + uint8_t dir; + uint8_t value; + tUcpGpioRegTable_t *gpio; +} tGpioInfRegTable; + +enum { + GPIO_PORT0A = 0, + GPIO_PORT0B, + GPIO_PORT1A, + GPIO_PORT1B +}; + +typedef enum eGpioDir_tag { + GPIO_DIR_IN = 0, + GPIO_DIR_OUT +} eGpioDir; + +enum { + GPIO_INDEX_TRX_TX1 = 0, + GPIO_INDEX_TRX_TX2, + GPIO_INDEX_TRX_TX3, + GPIO_INDEX_TRX_TX4, + GPIO_INDEX_RF_TX1, + GPIO_INDEX_RF_TX2, + GPIO_INDEX_RF_TX3, + GPIO_INDEX_RF_TX4, + GPIO_INDEX_SW_TX1, + GPIO_INDEX_SW_TX2, + GPIO_INDEX_SW_TX3, + GPIO_INDEX_SW_TX4, + + GPIO_INDEX_TRX_RX1, + GPIO_INDEX_TRX_RX2, + GPIO_INDEX_TRX_RX3, + GPIO_INDEX_TRX_RX4, + GPIO_INDEX_RF_RX1, + GPIO_INDEX_RF_RX2, + GPIO_INDEX_RF_RX3, + GPIO_INDEX_RF_RX4, + GPIO_INDEX_SW_RX1, + GPIO_INDEX_SW_RX2, + GPIO_INDEX_SW_RX3, + GPIO_INDEX_SW_RX4, + + GPIO_INDEX_TRX_ORX1, + GPIO_INDEX_TRX_ORX2, + GPIO_INDEX_TRX_ORX3, + GPIO_INDEX_TRX_ORX4, + GPIO_INDEX_RF_ORX1, + GPIO_INDEX_RF_ORX2, + GPIO_INDEX_RF_ORX3, + GPIO_INDEX_RF_ORX4, + GPIO_INDEX_SW_ORX1, + GPIO_INDEX_SW_ORX2, + GPIO_INDEX_SW_ORX3, + GPIO_INDEX_SW_ORX4, + + GPIO_INDEX_TRIGER, + + GPIO_INDEX_TR_MAX +}; + +extern const tUcpGpioRegTable_t *pUcpGpioTable[]; +extern ucp_jesd_TrxGpioCfg_t ucp_jesd_gpioInit (const char *trxGpioConfigFile, uint16_t enLog); +extern int ucp_jesd_gpioConfig (const int pinIdex, uint8_t dir, uint8_t enable, tUcpGpioRegTable_t *gpio); +extern int ucp_jesd_gpioSetDir(const int pinIdex, eGpioDir dir); +extern eGpioDir ucp_jesd_gpioGetDir(const int pinIdex); +extern int ucp_jesd_gpioSet(const int pinIdex, int value); +extern int ucp_jesd_gpioGet(const int pinIdex); +extern void ucp_jesd_gpio_tx (void); +extern void ucp_jesd_gpio_rx (void); +extern void ucp_jesd_gpio_on (void); +extern void ucp_jesd_gpio_off (void); +extern void ucp_jesd_gpio_orxOn (void); +extern void ucp_jesd_gpio_orxOff (void); +extern void ucp_jesd_gpio_trigOn (void); +extern void ucp_jesd_gpio_trigOff (void); + +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/driver/rfic/ucp/base/inc/ucp_js_ctrl.h b/driver/rfic/ucp/base/inc/ucp_js_ctrl.h new file mode 100644 index 0000000..b8bf1c9 --- /dev/null +++ b/driver/rfic/ucp/base/inc/ucp_js_ctrl.h @@ -0,0 +1,89 @@ +/********************************************************************* + * + * Filename: ucp_js_ctrl.h + * + * Created: 2021-11-08 10:54:34 AM + * Last Modified: 2022-06-08 05:32:38 PM + * Author: LiPin , lip2014@ia.ac.cn + * Organization: Beijing Smart Logic Technology Co., Ltd. + * + * Description: + * + * + ********************************************************************/ + +#ifndef __JS_CTRL__ +#define __JS_CTRL__ + +//The JESD And SRIO SubCtrl Base Addr +#define JS_CTRL_BASE 0x05f50000 +//The JESD ECPRI CPRI SRIO SubCtrl Base Addr +#define JECS_CTRL_BASE 0x08460000 + +//------------------------------------JS SYSTEM--------------------------------// +//JESD And SRIO SubCtrl Reg Addr +#define JS_CTRL_CLK_SEL (JS_CTRL_BASE + 4*18) //RW +#define JS_CTRL_TX_TMR_EN_CTRL (JS_CTRL_BASE + 4*19) //RW +#define JS_PHY_BS_CTRL (JS_CTRL_BASE + 4*20) +#define JS_CTRL_PHY_MISC_SEL_0 (JS_CTRL_BASE + 4*22) //RW +#define JS_CTRL_PHY_INT_CLK_SEL_SUB0 (JS_CTRL_BASE + 4*23) //RW +#define JS_CTRL_PHY_OUT_TEST_CLK_SEL_SUB0 (JS_CTRL_BASE + 4*24) //RW +#define JS_CTRL_PHY_MISC_SEL_1 (JS_CTRL_BASE + 4*53) //RW +#define JS_CTRL_SRIO0_AWADDR_H (JS_CTRL_BASE + 4*54) //RW +#define JS_CTRL_SRIO0_ARADDR_H (JS_CTRL_BASE + 4*55) //RW +#define JS_CTRL_JESD204_QOS (JS_CTRL_BASE + 4*56) //RW +#define JS_CTRL_RFC_QOS (JS_CTRL_BASE + 4*57) //RW +#define JS_CTRL_JESD204_MODE_SEL (JS_CTRL_BASE + 4*58) //RW +#define JS_SERDES_CLK_EN (JS_CTRL_BASE + 4*59) //RW + +//------------------------------------ES SYSTEM--------------------------------// +//JESD ECPRI CPRI SRIO SubCtrl Reg Addr +#define JECS_CTRL_RFM_USER0 (JECS_CTRL_BASE + 4*0) //RW +#define JECS_CTRL_RFM_USER1 (JECS_CTRL_BASE + 4*1) //RW +#define JECS_CTRL_RFM_USER2 (JECS_CTRL_BASE + 4*2) //RW +#define JECS_CTRL_RFM_USER3 (JECS_CTRL_BASE + 4*3) //RW +#define JECS_CTRL_RFM_USER4 (JECS_CTRL_BASE + 4*4) //RW +#define JECS_CTRL_RFM_USER5 (JECS_CTRL_BASE + 4*5) //RW +#define JECS_CTRL_RFM_ADDR_CTRL (JECS_CTRL_BASE + 4*6) //RW +#define JECS_CTRL_QOS_M3_SRIO_AXIM (JECS_CTRL_BASE + 4*7) //RW +#define JECS_CTRL_PHY_CLK_SEL (JECS_CTRL_BASE + 4*8) //RW +#define JECS_CTRL_PROTOCOL_SEL (JECS_CTRL_BASE + 4*9) //RW +#define JECS_CTRL_RFM_INT_MASK0 (JECS_CTRL_BASE + 10*4) +#define JECS_CTRL_RFM_INT_MASK1 (JECS_CTRL_BASE + 11*4) +#define JECS_CTRL_RFM_INT_MASK2 (JECS_CTRL_BASE + 12*4) +#define JECS_CTRL_RFM_INT_MASK3 (JECS_CTRL_BASE + 13*4) +#define JECS_CTRL_RFM_INT_MASK4 (JECS_CTRL_BASE + 14*4) +#define JECS_CTRL_RFM_INT_MASK5 (JECS_CTRL_BASE + 15*4) +#define JECS_CTRL_RFM_INT_MASK6 (JECS_CTRL_BASE + 16*4) +#define JECS_CTRL_RFM_INT_MASK7 (JECS_CTRL_BASE + 17*4) +#define JECS_CTRL_RFM_INT_MASK8 (JECS_CTRL_BASE + 18*4) +#define JECS_CTRL_RFM_INT_MASK9 (JECS_CTRL_BASE + 19*4) +#define JECS_CTRL_RFM_INT_MASK10 (JECS_CTRL_BASE + 20*4) +#define JECS_CTRL_RFM_INT_MASK11 (JECS_CTRL_BASE + 21*4) +#define JECS_CTRL_RFM_INT_MASK12 (JECS_CTRL_BASE + 22*4) +#define JECS_CTRL_RFM_INT_MASK13 (JECS_CTRL_BASE + 23*4) +#define JECS_CTRL_RFM_INT_MASK14 (JECS_CTRL_BASE + 24*4) +#define JECS_CTRL_RFM_INT_MASK15 (JECS_CTRL_BASE + 25*4) +#define JECS_CTRL_CTC_INT0 (JECS_CTRL_BASE + 26*4) +#define JECS_CTRL_CTC_INT1 (JECS_CTRL_BASE + 27*4) +#define JECS_CTRL_CTC_INT2 (JECS_CTRL_BASE + 28*4) +#define JECS_CTRL_CTC_INT3 (JECS_CTRL_BASE + 29*4) +#define JECS_CTRL_CTC_INT4 (JECS_CTRL_BASE + 30*4) +#define JECS_CTRL_CTC_INT5 (JECS_CTRL_BASE + 31*4) +#define JECS_CTRL_CTC_INT6 (JECS_CTRL_BASE + 32*4) +#define JECS_CTRL_CPRI_GMAC_PHY_INT (JECS_CTRL_BASE + 33*4) +#define JECS_PHY_BS_CTRL (JECS_CTRL_BASE + 34*4) +#define JECS_CTRL_ECPRI_QOSH (JECS_CTRL_BASE + 35*4) +#define JECS_CTRL_ECPRI_QOSL (JECS_CTRL_BASE + 36*4) +#define JECS_CTRL_CSU_BUS_CTRL (JECS_CTRL_BASE + 37*4) +#define JECS_CTRL_CPRI_PAD_CTRL (JECS_CTRL_BASE + 38*4) +#define JECS_CLK_GATE_CTRL (JECS_CTRL_BASE + 39*4) + + +#define JECS_PMA_TIMER_CTRL (JECS_CTRL_BASE + 41*4) + + + + + +#endif diff --git a/driver/rfic/ucp/base/inc/ucp_js_subcrg.h b/driver/rfic/ucp/base/inc/ucp_js_subcrg.h new file mode 100644 index 0000000..da37030 --- /dev/null +++ b/driver/rfic/ucp/base/inc/ucp_js_subcrg.h @@ -0,0 +1,192 @@ +/********************************************************************* + * + * Filename: ucp_js_subcrg.h + * + * Created: 2021-11-11 09:34:35 AM + * Last Modified: 2022-06-21 02:57:28 PM + * Author: LiPin , lip2014@ia.ac.cn + * Organization: Beijing Smart Logic Technology Co., Ltd. + * + * Description: + * + * + ********************************************************************/ + +#ifndef __JS_JECS_SUBCRG__ +#define __JS_JECS_SUBCRG__ + +//The JESD And SRIO SUBCRG Base Addr +#define JS_CRG_BASE 0x05F10000 +//The ECPRI And SRIO SUBCRG Base Addr +#define JECS_CRG_BASE 0x08430000 +//The JESD LVDS Base Addr +#define JESD_LVDS_BASE 0x05F20000 + +//--------------------------------------JS SYSTEM-------------------------------// +//JESD And SRIO SubCtrl Reg Addr +#define JS_CRG_CLK_SEL (JS_CRG_BASE + 4*0) //RW +#define JS_CRG_DPLL0_CTRL_0 (JS_CRG_BASE + 4*1) //RW +#define JS_CRG_DPLL0_CTRL_1 (JS_CRG_BASE + 4*2) //RW +#define JS_CRG_DPLL1_CTRL_0 (JS_CRG_BASE + 4*3) //RW +#define JS_CRG_DPLL1_CTRL_1 (JS_CRG_BASE + 4*4) //RW +#define JS_CRG_SAM0_CLK_CTRL (JS_CRG_BASE + 4*5) //RW +#define JS_CRG_SAM1_CLK_CTRL (JS_CRG_BASE + 4*6) //RW +#define JS_CRG_SAM2_CLK_CTRL (JS_CRG_BASE + 4*7) //RW +#define JS_CRG_CHA0_CLK_CTRL (JS_CRG_BASE + 4*8) //RW +#define JS_CRG_CHA1_CLK_CTRL (JS_CRG_BASE + 4*9) //RW +#define JS_CRG_CHA2_CLK_CTRL (JS_CRG_BASE + 4*10) //RW +#define JS_CRG_SAM3_CLK_CTRL (JS_CRG_BASE + 4*11) //RW +#define JS_CRG_DPLL_PMA_CTRL (JS_CRG_BASE + 4*12) //RW +#define JS_CRG_DPLL_CLK_CTRL (JS_CRG_BASE + 4*13) //RW +#define JS_CRG_JESD0_TIME_CTRL (JS_CRG_BASE + 4*14) //RW +#define JS_CRG_JESD1_TIME_CTRL (JS_CRG_BASE + 4*15) //RW +#define JS_CRG_JESD2_TIME_CTRL (JS_CRG_BASE + 4*16) //RW +#define JS_CRG_JESD3_TIME_CTRL (JS_CRG_BASE + 4*17) //RW +#define JS_CRG_JESD4_TIME_CTRL (JS_CRG_BASE + 4*18) //RW +#define JS_CRG_JESD5_TIME_CTRL (JS_CRG_BASE + 4*19) //RW +#define JS_CRG_JESD6_TIME_CTRL (JS_CRG_BASE + 4*20) //RW +#define JS_CRG_JESD7_TIME_CTRL (JS_CRG_BASE + 4*21) //RW +#define JS_CRG_JESD8_TIME_CTRL (JS_CRG_BASE + 4*22) //RW +#define JS_CRG_JESD9_TIME_CTRL (JS_CRG_BASE + 4*23) //RW +#define JS_CRG_JESD10_TIME_CTRL (JS_CRG_BASE + 4*24) //RW +#define JS_CRG_JESD11_TIME_CTRL (JS_CRG_BASE + 4*25) //RW +#define JS_CRG_DPLL0_DSKEW_CTRL (JS_CRG_BASE + 4*26) //RO +#define JS_CRG_DPLL1_DSKEW_CTRL (JS_CRG_BASE + 4*27) //RO +#define JS_CRG_PHY_TX_RSTN_JS_CTRL_0 (JS_CRG_BASE + 4*28) //RW +#define JS_CRG_PHY_TX_RSTN_JS_CTRL_1 (JS_CRG_BASE + 4*29) //RW +#define JS_CRG_PHY_TX_RSTN_JS_CTRL_2 (JS_CRG_BASE + 4*30) //RW +#define JS_CRG_PHY_TX_RSTN_JS_CTRL_3 (JS_CRG_BASE + 4*31) //RW +#define JS_CRG_PHY_RX_RSTN_JS_CTRL_0 (JS_CRG_BASE + 4*32) //RW +#define JS_CRG_PHY_RX_RSTN_JS_CTRL_1 (JS_CRG_BASE + 4*33) //RW +#define JS_CRG_PHY_RX_RSTN_JS_CTRL_2 (JS_CRG_BASE + 4*34) //RW +#define JS_CRG_PHY_RX_RSTN_JS_CTRL_3 (JS_CRG_BASE + 4*35) //RW +#define JS_CRG_CHA3_CLK_CTRL (JS_CRG_BASE + 4*36) //RW +#define JS_CRG_SAM_CHA6_RST_CTRL (JS_CRG_BASE + 4*37) //RW +#define JS_CRG_SAM_CHA7_RST_CTRL (JS_CRG_BASE + 4*38) //RW +#define JS_CRG_PHY_TX_RSTN_JECS_CTRL_3 (JS_CRG_BASE + 4*39) //RW +#define JS_CRG_RFC_TMR_CLK_CTRL (JS_CRG_BASE + 4*40) //RW +#define JS_CRG_RFC_TMR_RST_CTRL (JS_CRG_BASE + 4*41) //RW +#define JS_CRG_PHY_RX_RSTN_JECS_CTRL_2 (JS_CRG_BASE + 4*42) //RW +#define JS_CRG_PHY_RX_RSTN_JECS_CTRL_3 (JS_CRG_BASE + 4*43) //RW +#define JS_CRG_PHY_RX_RST_JS_CTRL_0 (JS_CRG_BASE + 4*46) //RW +#define JS_CRG_PHY_RX_RST_JS_CTRL_1 (JS_CRG_BASE + 4*47) //RW +#define JS_CRG_PHY_RX_RST_JS_CTRL_2 (JS_CRG_BASE + 4*48) //RW +#define JS_CRG_PHY_RX_RST_JS_CTRL_3 (JS_CRG_BASE + 4*49) //RW +#define JS_CRG_PHY_RX_RST_JECS_CTRL_0 (JS_CRG_BASE + 4*50) //RW +#define JS_CRG_PHY_RX_RST_JECS_CTRL_1 (JS_CRG_BASE + 4*51) //RW +#define JS_CRG_PHY_RX_RST_JECS_CTRL_2 (JS_CRG_BASE + 4*52) //RW +#define JS_CRG_PHY_RX_RST_JECS_CTRL_3 (JS_CRG_BASE + 4*53) //RW +#define JS_CRG_PHY_EQ_RSTN_JS_CTRL_0 (JS_CRG_BASE + 4*54) //RW +#define JS_CRG_PHY_EQ_RSTN_JS_CTRL_1 (JS_CRG_BASE + 4*55) //RW +#define JS_CRG_PHY_EQ_RSTN_JS_CTRL_2 (JS_CRG_BASE + 4*56) //RW +#define JS_CRG_PHY_EQ_RSTN_JS_CTRL_3 (JS_CRG_BASE + 4*57) //RW +#define JS_CRG_PHY_EQ_RSTN_JECS_CTRL_0 (JS_CRG_BASE + 4*58) //RW +#define JS_CRG_PHY_EQ_RSTN_JECS_CTRL_1 (JS_CRG_BASE + 4*59) //RW +#define JS_CRG_PHY_EQ_RSTN_JECS_CTRL_2 (JS_CRG_BASE + 4*60) //RW +#define JS_CRG_PHY_EQ_RSTN_JECS_CTRL_3 (JS_CRG_BASE + 4*61) //RW +#define JS_CRG_PHY_PWR_ON_RST_JS_CTRL (JS_CRG_BASE + 4*62) //RW +#define JS_CRG_PHY_PWR_ON_RST_JECS_CTRL (JS_CRG_BASE + 4*63) //RW +#define JS_CRG_SRIO_PWR_ON_RST_JS_CTRL (JS_CRG_BASE + 4*64) //RW +#define JS_CRG_SRIO_PWR_ON_RST_JECS_CTRL (JS_CRG_BASE + 4*65) //RW +#define JS_CRG_SAM_CHA0_RST_CTRL (JS_CRG_BASE + 4*66) //RW +#define JS_CRG_SAM_CHA1_RST_CTRL (JS_CRG_BASE + 4*67) //RW +#define JS_CRG_SAM_CHA2_RST_CTRL (JS_CRG_BASE + 4*68) //RW +#define JS_CRG_SAM_CHA3_RST_CTRL (JS_CRG_BASE + 4*69) //RW +#define JS_CRG_SAM_CHA4_RST_CTRL (JS_CRG_BASE + 4*70) //RW +#define JS_CRG_SAM_CHA5_RST_CTRL (JS_CRG_BASE + 4*71) //RW +#define JS_CRG_TMR_EN_SAM_CLK_SEL (JS_CRG_BASE + 4*72) //RW +#define JS_CRG_JESD_CLK_CFG (JS_CRG_BASE + 4*73) //RW +#define JS_CRG_SYSREF_CFG (JS_CRG_BASE + 4*74) //RW + +//--------------------------------------JECS SYSTEM-------------------------------// +//JESD ECPRI CPRI SRIO Subcrg Reg Addr +#define JECS_CRG_PLL_CTL_REG0 (JECS_CRG_BASE + 4*0) +#define JECS_CRG_PLL_CTL_REG1 (JECS_CRG_BASE + 4*1) +#define JECS_CRG_PLL_CTL_REG2 (JECS_CRG_BASE + 4*2) +#define JECS_CRG_PLL_CTL_REG3 (JECS_CRG_BASE + 4*3) +#define JECS_CRG_PLL_CTL_REG4 (JECS_CRG_BASE + 4*4) +#define JECS_CRG_PLLSEL (JECS_CRG_BASE + 4*5) +#define JECS_CRG_CLK_CTRL0 (JECS_CRG_BASE + 4*6) +#define JECS_CRG_CLK_CTRL1 (JECS_CRG_BASE + 4*7) +#define JECS_CRG_CLK_CTRL2 (JECS_CRG_BASE + 4*8) +#define JECS_CRG_CLK_CTRL3 (JECS_CRG_BASE + 4*9) +#define JECS_CRG_CLK_CTRL4 (JECS_CRG_BASE + 4*10) +#define JECS_CRG_CLK_CTRL5 (JECS_CRG_BASE + 4*11) +#define ECPRI_ACLK_CFG_REG (JECS_CRG_BASE + 4*11) +#define JECS_CRG_CLK_CTRL6 (JECS_CRG_BASE + 4*12) +#define JECS_CRG_CLK_CTRL7 (JECS_CRG_BASE + 4*13) +#define JECS_CRG_CLK_CTRL8 (JECS_CRG_BASE + 4*14) +#define JECS_CRG_CLK_CTRL9 (JECS_CRG_BASE + 4*15) +#define JECS_CRG_CLK_CTRL10 (JECS_CRG_BASE + 4*16) +#define JECS_CRG_CLK_CTRL11 (JECS_CRG_BASE + 4*17) +#define JECS_CRG_PLL0_LOCK_CTRL (JECS_CRG_BASE + 4*18) +#define JECS_CRG_MANTICORE0_RST_CTRL (JECS_CRG_BASE + 4*19) +#define JECS_CRG_MANTICORE1_RST_CTRL (JECS_CRG_BASE + 4*20) +#define JECS_CRG_MANTICORE2_RST_CTRL (JECS_CRG_BASE + 4*21) +#define JECS_CRG_MANTICORE3_RST_CTRL (JECS_CRG_BASE + 4*22) +#define JECS_CRG_MANTICORE4_RST_CTRL (JECS_CRG_BASE + 4*23) +#define JECS_CRG_MANTICORE5_RST_CTRL (JECS_CRG_BASE + 4*59) +#define JECS_CRG_MANTICORE6_RST_CTRL (JECS_CRG_BASE + 4*60) +#define JECS_CRG_MANTICORE7_RST_CTRL (JECS_CRG_BASE + 4*63) +#define JECS_CRG_MANTICORE8_RST_CTRL (JECS_CRG_BASE + 4*64) +#define JECS_CRG_PMA0_RST_CTRL (JECS_CRG_BASE + 4*24) +#define JECS_CRG_PMA1_RST_CTRL (JECS_CRG_BASE + 4*25) +#define JECS_CRG_PMA2_RST_CTRL (JECS_CRG_BASE + 4*26) +#define JECS_CRG_PMA3_RST_CTRL (JECS_CRG_BASE + 4*27) +#define JECS_CRG_PMA4_RST_CTRL (JECS_CRG_BASE + 4*28) +#define JECS_CRG_PMA5_RST_CTRL (JECS_CRG_BASE + 4*29) +#define JECS_CRG_PMA6_RST_CTRL (JECS_CRG_BASE + 4*30) +#define JECS_CRG_PMA7_RST_CTRL (JECS_CRG_BASE + 4*31) +#define JECS_CRG_PMA8_RST_CTRL (JECS_CRG_BASE + 4*32) +#define JECS_CRG_PMA9_RST_CTRL (JECS_CRG_BASE + 4*33) +#define JECS_CRG_PMA10_RST_CTRL (JECS_CRG_BASE + 4*34) +#define JECS_CRG_PMA11_RST_CTRL (JECS_CRG_BASE + 4*35) +#define JECS_CRG_PMA12_RST_CTRL (JECS_CRG_BASE + 4*36) +#define JECS_CRG_PMA13_RST_CTRL (JECS_CRG_BASE + 4*37) +#define JECS_CRG_PMA14_RST_CTRL (JECS_CRG_BASE + 4*38) +#define JECS_CRG_PMA15_RST_CTRL (JECS_CRG_BASE + 4*39) +#define JECS_CRG_PMA16_RST_CTRL (JECS_CRG_BASE + 4*40) +#define JECS_CRG_PMA17_RST_CTRL (JECS_CRG_BASE + 4*41) +#define ECPRI_RST_CFG_REG (JECS_CRG_BASE + 4*41) +#define JECS_CRG_SRIO_ULI_RST_CTRL (JECS_CRG_BASE + 4*43) +#define JECS_CRG_STC_RST_CTRL (JECS_CRG_BASE + 4*43) +#define JECS_CRG_SRIO_PWR_ON_RST_CTRL (JECS_CRG_BASE + 4*44) +#define JECS_CRG_CPRI0_RST_CTRL (JECS_CRG_BASE + 4*45) +#define JECS_CRG_CPRI1_RST_CTRL (JECS_CRG_BASE + 4*46) +#define JECS_CRG_CPRI2_RST_CTRL (JECS_CRG_BASE + 4*47) +#define JECS_CRG_CPRI3_RST_CTRL (JECS_CRG_BASE + 4*48) +#define JECS_CRG_CPRI4_RST_CTRL (JECS_CRG_BASE + 4*49) +#define JECS_CRG_CPRI5_RST_CTRL (JECS_CRG_BASE + 4*50) +#define JECS_CRG_CPRI6_RST_CTRL (JECS_CRG_BASE + 4*51) +#define JECS_CRG_CPRI_CDR_CLK_CTRL (JECS_CRG_BASE + 4*52) +#define JECS_CRG_CPRI_ALT_CLK_CTRL (JECS_CRG_BASE + 4*53) +#define JECS_CRG_CPRI_CORE_CLK_CTRL (JECS_CRG_BASE + 4*54) +#define JECS_CRG_CPRI_PCS_CORE_CLK_CTRL (JECS_CRG_BASE + 4*55) +#define JECS_CRG_CPRI0_CLK_CTRL (JECS_CRG_BASE + 4*56) +#define JECS_CRG_CPRI1_CLK_CTRL (JECS_CRG_BASE + 4*57) +#define JECS_CRG_CPRI2_CLK_CTRL (JECS_CRG_BASE + 4*58) +#define SYNCE_OUT_CLK_SEL (JECS_CRG_BASE + 4*61) +#define JECS_CRG_ECPRI_CPRI_RST (JECS_CRG_BASE + 4*62) + +//------------------------------------JESD LVDS--------------------------------// +//JESD LVDS Reg Addr +#define JS_CTRL_LVDS_BIAS_EN (JESD_LVDS_BASE + 4*1) //RW +#define JS_CTRL_LVDS_VBIAS_SEL (JESD_LVDS_BASE + 4*2) //RW +#define JS_CTRL_LVDS_PULLDN (JESD_LVDS_BASE + 4*3) //RW +#define JS_CTRL_LVDS_SCHMITT_EN (JESD_LVDS_BASE + 4*4) //RW +#define JS_CTRL_LVDS_RTERM_EN (JESD_LVDS_BASE + 4*5) //RW +#define JS_CTRL_LVDS_RTERM_VAL_0 (JESD_LVDS_BASE + 4*6) //RW +#define JS_CTRL_LVDS_RTERM_VAL_1 (JESD_LVDS_BASE + 4*7) //RW +#define JS_CTRL_LVDS_RTERM_VAL_2 (JESD_LVDS_BASE + 4*8) //RW +#define JS_CTRL_LVDS_RTERM_VAL_3 (JESD_LVDS_BASE + 4*9) //RW +#define JS_CTRL_LVDS_RXCM_EN (JESD_LVDS_BASE + 4*10) //RW +#define JS_CTRL_LVDS_RXEN (JESD_LVDS_BASE + 4*11) //RW +#define JS_CTRL_LVDS_TXDRV_0 (JESD_LVDS_BASE + 4*12) //RW +#define JS_CTRL_LVDS_TXDRV_1 (JESD_LVDS_BASE + 4*13) //RW +#define JS_CTRL_LVDS_TXDRV_2 (JESD_LVDS_BASE + 4*14) //RW +#define JS_CTRL_LVDS_TXDRV_3 (JESD_LVDS_BASE + 4*15) //RW +#define JS_CTRL_LVDS_TXEN (JESD_LVDS_BASE + 4*16) //RW +#define JS_CTRL_LVDS_TX_CM (JESD_LVDS_BASE + 4*17) //RW +#define JS_CTRL_LVDS_PMUX_MODE (JESD_LVDS_BASE + 4*18) //RW + +#endif diff --git a/driver/rfic/ucp/base/inc/ucp_jsonTools.h b/driver/rfic/ucp/base/inc/ucp_jsonTools.h new file mode 100644 index 0000000..9e2eff6 --- /dev/null +++ b/driver/rfic/ucp/base/inc/ucp_jsonTools.h @@ -0,0 +1,31 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_jsonTools.h (ap side) +// Author : boheng.lin@smartlogictech.com +// Date First Issued : 2023-08-16 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef __UCP_JSONTOOLS__ +#define __UCP_JSONTOOLS__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ucp_api_jesd.h" + +extern ucp_jesd_TrxGpioCfg_t ucp_GetGpioConfig (const char *fileName); +extern void ucp_printGpioConfigStruct (ucp_jesd_TrxGpioCfg_t trxGpioCfg); + +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/driver/rfic/ucp/base/inc/ucp_param.h b/driver/rfic/ucp/base/inc/ucp_param.h new file mode 100644 index 0000000..62a820d --- /dev/null +++ b/driver/rfic/ucp/base/inc/ucp_param.h @@ -0,0 +1,1353 @@ +//******************** (C) COPYRIGHT 2019 SmartLogic******************************* +// FileName : ucp_param.h +// Author : lijian, jian.li@smartlogictech.com +// Date First Issued : 2019-03-29 02:37:50 PM +// Last Modified : 2022-06-29 10:05:40 PM +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef __PARAM_UCP_H__ +#define __PARAM_UCP_H__ + +#include + +typedef uint8_t UINT8; +typedef uint16_t UINT16; +typedef uint32_t UINT32; +typedef uint64_t UINT64; + +#define BIT0 (0x1<<0ul) +#define BIT1 (0x1<<1ul) +#define BIT2 (0x1<<2ul) +#define BIT3 (0x1<<3ul) +#define BIT4 (0x1<<4ul) +#define BIT5 (0x1<<5ul) +#define BIT6 (0x1<<6ul) +#define BIT7 (0x1<<7ul) +#define BIT8 (0x1<<8ul) +#define BIT9 (0x1<<9ul) +#define BIT10 (0x1<<10ul) +#define BIT11 (0x1<<11ul) +#define BIT12 (0x1<<12ul) +#define BIT13 (0x1<<13ul) +#define BIT14 (0x1<<14ul) +#define BIT15 (0x1<<15ul) +#define BIT16 (0x1<<16ul) +#define BIT17 (0x1<<17ul) +#define BIT18 (0x1<<18ul) +#define BIT19 (0x1<<19ul) +#define BIT20 (0x1<<20ul) +#define BIT21 (0x1<<21ul) +#define BIT22 (0x1<<22ul) +#define BIT23 (0x1<<23ul) +#define BIT24 (0x1<<24ul) +#define BIT25 (0x1<<25ul) +#define BIT26 (0x1<<26ul) +#define BIT27 (0x1<<27ul) +#define BIT28 (0x1<<28ul) +#define BIT29 (0x1<<29ul) +#define BIT30 (0x1<<30ul) +#define BIT31 (0x1<<31ul) + +#define S64B 0x00000040ul +#define S128B 0x00000080ul +#define S256B 0x00000100ul +#define S512B 0x00000200ul +#define S1KB 0x00000400ul +#define S2KB 0x00000800ul +#define S4KB 0x00001000ul +#define S8KB 0x00002000ul +#define S16KB 0x00004000ul +#define S32KB 0x00008000ul +#define S64KB 0x00010000ul +#define S128KB 0x00020000ul +#define S256KB 0x00040000ul +#define S512KB 0x00080000ul +#define S1MB 0x00100000ul +#define S15MB 0x00180000ul +#define S2MB 0x00200000ul +#define S4MB 0x00400000ul + +//m3 -> apsm0 apsm -> apsm1 +#define M3_SRAM_BASE 0x043c8000ul +#define APSM0_BASE 0x04768000ul +#define APSM1_BASE 0x04778000ul +#define CPSM_BASE 0x09300000ul +#define DDR_BASE 0x10000000ul +#define APSM0_SIZE S64KB +#define APSM1_SIZE S64KB +#define CPSM_SIZE S128KB +#define M3_SRAM_SIZE S32KB + + +#define JS_SM_BASE 0x04d80000ul +#define JECS_SM_BASE 0x07200000ul +#define PET_SM_BASE 0x08700000ul +#define JS_SM_SIZE S128KB +#define JECS_SM_SIZE S128KB +#define PET_SM_SIZE S128KB + + + +#define SM0_BASE 0x09d00000ul +#define SM1_BASE 0x09e00000ul +#define SM2_BASE 0x09f00000ul +#define SM3_BASE 0x0a080000ul +#define SM4_BASE 0x0a200000ul +#define SM5_BASE 0x0a380000ul +#define SM0_SIZE S1MB +#define SM1_SIZE S1MB +#define SM2_SIZE S15MB +#define SM3_SIZE S15MB +#define SM4_SIZE S15MB +#define SM5_SIZE S15MB + +#define PET_PET_CTC_INTER 0 +#define JECS_JECS_CTC_INTER 0 + +#define APC_CPSPACC0_INTR 0 +#define APC_TMAC_INTR 1 +#define APC_JESD204A_WRAPPER_INTR 2 +#define APC_JESD204B_WRAPPER_INTR 3 +#define APC_JS_SM_EMPTY_INTR0 4 +#define APC_JS_SM_EMPTY_INTR1 5 +#define APC_JS_SM_EMPTY_INTR2 6 +#define APC_JS_SM_EMPTY_INTR3 7 +#define APC_JS_SM_EMPTY_INTR4 8 +#define APC_JS_SM_EMPTY_INTR5 9 +#define APC_JS_SM_EMPTY_INTR6 10 +#define APC_JS_SM_EMPTY_INTR7 11 +#define APC_JS_SM_FULL_INTR0 12 +#define APC_JS_SM_FULL_INTR1 13 +#define APC_JS_SM_FULL_INTR2 14 +#define APC_JS_SM_FULL_INTR3 15 +#define APC_JS_SM_FULL_INTR4 16 +#define APC_JS_SM_FULL_INTR5 17 +#define APC_JS_SM_FULL_INTR6 18 +#define APC_JS_SM_FULL_INTR7 19 +#define APC_SRIO_SUB0_INTR 20 +#define APC_SRIO_SUB1_INTR 21 +#define APC_PPS_OUT_INTR 22 +#define APC_PET_SM_EMPTY_INTR0 23 +#define APC_PET_SM_EMPTY_INTR1 24 +#define APC_PET_SM_EMPTY_INTR2 25 +#define APC_PET_SM_EMPTY_INTR3 26 +#define APC_PET_SM_EMPTY_INTR4 27 +#define APC_PET_SM_EMPTY_INTR5 28 +#define APC_PET_SM_EMPTY_INTR6 29 +#define APC_PET_SM_EMPTY_INTR7 30 +#define APC_PET_SM_FULL_INTR0 31 +#define APC_PET_SM_FULL_INTR1 32 +#define APC_PET_SM_FULL_INTR2 33 +#define APC_PET_SM_FULL_INTR3 34 +#define APC_PET_SM_FULL_INTR4 35 +#define APC_PET_SM_FULL_INTR5 36 +#define APC_PET_SM_FULL_INTR6 37 +#define APC_PET_SM_FULL_INTR7 38 +#define APC_JECS_SM_EMPTY_INTR0 39 +#define APC_JECS_SM_EMPTY_INTR1 40 +#define APC_JECS_SM_EMPTY_INTR2 41 +#define APC_JECS_SM_EMPTY_INTR3 42 +#define APC_JECS_SM_EMPTY_INTR4 43 +#define APC_JECS_SM_EMPTY_INTR5 44 +#define APC_JECS_SM_EMPTY_INTR6 45 +#define APC_JECS_SM_EMPTY_INTR7 46 +#define APC_JECS_SM_FULL_INTR0 47 +#define APC_JECS_SM_FULL_INTR1 48 +#define APC_JECS_SM_FULL_INTR2 49 +#define APC_JECS_SM_FULL_INTR3 50 +#define APC_JECS_SM_FULL_INTR4 51 +#define APC_JECS_SM_FULL_INTR5 52 +#define APC_JECS_SM_FULL_INTR6 53 +#define APC_JECS_SM_FULL_INTR7 54 +#define APC_MBX0_HPRI_INTR0 55 +#define APC_MBX0_HPRI_INTR1 56 +#define APC_MBX0_HPRI_INTR2 57 +#define APC_MBX0_HPRI_INTR3 58 +#define APC_MBX0_LPRI_INTR0 59 +#define APC_MBX0_LPRI_INTR1 60 +#define APC_MBX0_LPRI_INTR2 61 +#define APC_MBX0_LPRI_INTR3 62 +#define APC_MBX1_HPRI_INTR0 63 +#define APC_MBX1_HPRI_INTR1 64 +#define APC_MBX1_HPRI_INTR2 65 +#define APC_MBX1_HPRI_INTR3 66 +#define APC_MBX1_LPRI_INTR0 67 +#define APC_MBX1_LPRI_INTR1 68 +#define APC_MBX1_LPRI_INTR2 69 +#define APC_MBX1_LPRI_INTR3 70 +#define APC_SSI2_INTR 71 +#define APC_SSI3_INTR 72 +#define APC_TIMER10_INTR 73 +#define APC_TIMER11_INTR 74 +#define APC_TIMER12_INTR 75 +#define APC_TIMER13_INTR 76 +#define APC_TIMER14_INTR 77 +#define APC_TIMER15_INTR 78 +#define APC_TIMER16_INTR 79 +#define APC_TIMER17_INTR 80 +#define APC_TIMER20_INTR 81 +#define APC_TIMER21_INTR 82 +#define APC_TIMER22_INTR 83 +#define APC_TIMER23_INTR 84 +#define APC_TIMER24_INTR 85 +#define APC_TIMER25_INTR 86 +#define APC_TIMER26_INTR 87 +#define APC_TIMER27_INTR 88 +#define APC_JS_CRG_INTR 89 +#define APC_RFC_INTR0 90 +#define APC_RFC_INTR1 91 +#define APC_RFC_INTR2 92 +#define APC_PETSPACC0_INTR 93 +#define APC_RFCSU_RX_INTR 94 +#define APC_RFCSU_TX_INTR 95 +#define APC_JESD_RX0_SBU0_TMR_INTR0 96 +#define APC_JESD_RX0_SBU0_TMR_INTR1 97 +#define APC_JESD_RX0_SBU0_TMR_INTR2 98 +#define APC_JESD_RX0_SBU0_TMR_INTR3 99 +#define APC_JESD_RX0_SBU0_TMR_INTR4 100 +#define APC_JESD_RX0_SBU0_TMR_INTR5 101 +#define APC_JESD_RX0_SBU0_TMR_INTR6 102 +#define APC_JESD_RX0_SBU0_TMR_INTR7 103 +#define APC_JESD_RX0_SBU0_TMR_INTR8 104 +#define APC_JESD_RX0_SBU0_TMR_INTR9 105 +#define APC_JESD_RX0_SBU0_TMR_INTR10 106 +#define APC_JESD_RX0_SBU0_TMR_INTR11 107 +#define APC_SLAVE_INTERRUPT_204B_RX0 108 +#define APC_SLAVE_INTERRUPT_204B_RX1 109 +#define APC_SLAVE_INTERRUPT_204B_TX0 110 +#define APC_SLAVE_INTERRUPT_204C_RX0 111 +#define APC_SLAVE_INTERRUPT_204C_RX1 112 +#define APC_SLAVE_INTERRUPT_204C_TX0 113 +#define APC_JECS_CTC_INTER 114 +#define APC_PET_CTC_INTER 115 +#define APC_SPACC0_INTR 116 +#define APC_CPSM_EMPTY_INTR0 120 +#define APC_CPSM_EMPTY_INTR1 121 +#define APC_CPSM_EMPTY_INTR2 122 +#define APC_CPSM_EMPTY_INTR3 123 +#define APC_CPSM_EMPTY_INTR4 124 +#define APC_CPSM_EMPTY_INTR5 125 +#define APC_CPSM_EMPTY_INTR6 126 +#define APC_CPSM_EMPTY_INTR7 127 +#define APC_CPSM_FULL_INTR0 128 +#define APC_CPSM_FULL_INTR1 129 +#define APC_CPSM_FULL_INTR2 130 +#define APC_CPSM_FULL_INTR3 131 +#define APC_CPSM_FULL_INTR4 132 +#define APC_CPSM_FULL_INTR5 133 +#define APC_CPSM_FULL_INTR6 134 +#define APC_CPSM_FULL_INTR7 135 +#define APC_RFC_DMA_INTR 136 +#define APC_JESD_CSU_RX0_INTR 137 +#define APC_JESD_CSU_TX_INTR 138 +#define APC_JESD_CSU_RX1_INTR 139 +#define APC_JESDA_CSU_TX_INTR1 140 +#define APC_JESDB_CSU_RX_INTR0 141 +#define APC_JESDB_CSU_RX_INTR1 142 +#define APC_JESDB_CSU_TX_INTR0 143 +#define APC_JESDB_CSU_TX_INTR1 144 + +#define APC_PETRFM_OUT_INTR0 205 +#define APC_PETRFM_OUT_INTR1 206 +#define APC_PETRFM_OUT_INTR2 207 +#define APC_PETRFM_OUT_INTR3 208 +#define APC_PETRFM_OUT_INTR4 209 +#define APC_PETRFM_OUT_INTR5 210 +#define APC_PETRFM_OUT_INTR6 211 +#define APC_PETRFM_OUT_INTR7 212 +#define APC_PETRFM_OUT_INTR8 213 +#define APC_PETRFM_OUT_INTR9 214 +#define APC_PETRFM_OUT_INTR10 215 +#define APC_PETRFM_OUT_INTR11 216 +#define APC_PETRFM_OUT_INTR12 217 +#define APC_PETRFM_OUT_INTR13 218 +#define APC_PETRFM_OUT_INTR14 219 +#define APC_PETRFM_OUT_INTR15 220 +#define APC_PETRFM_OUT_INTR16 221 +#define APC_PETRFM_OUT_INTR17 222 +#define APC_PETRFM_OUT_INTR18 223 +#define APC_PETRFM_OUT_INTR19 224 +#define APC_JECSRFM_OUT_INTR0 225 +#define APC_JECSRFM_OUT_INTR1 226 +#define APC_JECSRFM_OUT_INTR2 227 +#define APC_JECSRFM_OUT_INTR3 228 +#define APC_JECSRFM_OUT_INTR4 229 +#define APC_JECSRFM_OUT_INTR5 230 +#define APC_JECSRFM_OUT_INTR6 231 +#define APC_JECSRFM_OUT_INTR7 232 +#define APC_JECSRFM_OUT_INTR8 233 +#define APC_JECSRFM_OUT_INTR9 234 +#define APC_JECSRFM_OUT_INTR10 235 +#define APC_JECSRFM_OUT_INTR11 236 +#define APC_JECSRFM_OUT_INTR12 237 +#define APC_JECSRFM_OUT_INTR13 238 +#define APC_JECSRFM_OUT_INTR14 239 +#define APC_JECSRFM_OUT_INTR15 240 +#define APC_JECSRFM_OUT_INTR16 241 +#define APC_JECSRFM_OUT_INTR17 242 +#define APC_JECSRFM_OUT_INTR18 243 +#define APC_JECSRFM_OUT_INTR19 244 +#define APC_ECPRI_SUB_INTR0 245 +#define APC_ECPRI_SUB_INTR1 246 +#define APC_ECPRI_SUB_INTR2 247 +#define APC_ECPRI_SUB_INTR3 248 +#define APC_ECPRI_SUB_INTR4 249 +#define APC_ECPRI_SUB_INTR5 250 +#define APC_ECPRI_SUB_INTR6 251 +#define APC_ECPRI_SUB_INTR7 252 +#define APC_ECPRI_SUB_INTR8 253 +#define APC_ECPRI_SUB_INTR9 254 +#define APC_ECPRI_SUB_INTR10 255 +#define APC_ECPRI_SUB_INTR11 256 +#define APC_ECPRI_SUB_INTR12 257 +#define APC_ECPRI_SUB_INTR13 258 +#define APC_ECPRI_SUB_INTR14 259 +#define APC_ECPRI_SUB_INTR15 260 +#define APC_ECPRI_SUB_INTR16 261 +#define APC_ECPRI_SUB_INTR17 262 +#define APC_ECPRI_SUB_INTR18 263 +#define APC_ECPRI_SUB_INTR19 264 +#define APC_ECPRI_SUB_INTR20 265 +#define APC_ECPRI_SUB_INTR21 266 +#define APC_ECPRI_SUB_INTR22 267 +#define APC_ECPRI_SUB_INTR23 268 +#define APC_ECPRI_SUB_INTR24 269 +#define APC_ECPRI_SUB_INTR25 270 +#define APC_ECPRI_SUB_INTR26 271 +#define APC_ECPRI_SUB_INTR27 272 +#define APC_ECPRI_SUB_INTR28 273 +#define APC_ECPRI_SUB_INTR29 274 +#define APC_ECPRI_SUB_INTR30 275 +#define APC_ECPRI_SUB_INTR31 276 +#define APC_PETSPACC1_INTR 277 +#define APC_CPRI_SUB_INTR0 278 +#define APC_CPRI_SUB_INTR1 279 +#define APC_STC_INTR0 280 +#define APC_STC_INTR1 281 +#define APC_STC_INTR2 282 +#define APC_STC_INTR3 283 +#define APC_STC_INTR4 284 +#define APC_STC_INTR5 285 +#define APC_STC_INTR6 286 +#define APC_STC_INTR7 287 +#define APC_STC_INTR8 288 +#define APC_STC_INTR9 289 +#define APC_STC_INTR10 290 + +#define APC_CPRI_TMR_INTR0 291 +#define APC_CPRI_TMR_INTR1 292 +#define APC_CPRI_TMR_INTR2 293 +#define APC_CPRI_TMR_INTR3 294 +#define APC_CPRI_TMR_INTR4 295 +#define APC_CPRI_TMR_INTR5 296 +#define APC_CPRI_TMR_INTR6 297 +#define APC_CPRI_TMR_INTR7 298 +#define APC_CPRI_TMR_INTR8 299 +#define APC_CPRI_TMR_INTR9 300 +#define APC_CPRI_TMR_INTR10 301 +#define APC_CPRI_TMR_INTR11 302 + +#define APC_SSI0_INTR (310+0) +#define APC_SSI1_INTR (310+1) +#define APC_UART0_INTR (310+2) +#define APC_UART1_INTR (310+3) +#define APC_WDT0_INTR (310+4) +#define APC_WDT1_INTR (310+5) +#define APC_TIMER0_INTR (310+6) +#define APC_GPIO0_INTR (310+7) + +#define APC_GPIO1_INTR (467) +#define APC_PEREST_INTR 466 + +#define APC_APSM1_EMPTY_INTR0 (310+4+4) +#define APC_APSM1_EMPTY_INTR1 (310+4+5) +#define APC_APSM1_EMPTY_INTR2 (310+4+6) +#define APC_APSM1_EMPTY_INTR3 (310+4+7) +#define APC_APSM1_EMPTY_INTR4 (310+4+8) +#define APC_APSM1_EMPTY_INTR5 (310+4+9) +#define APC_APSM1_EMPTY_INTR6 (310+4+10) +#define APC_APSM1_EMPTY_INTR7 (310+4+11) +#define APC_APSM1_FULL_INTR0 (310+4+12) +#define APC_APSM1_FULL_INTR1 (310+4+13) +#define APC_APSM1_FULL_INTR2 (310+4+14) +#define APC_APSM1_FULL_INTR3 (310+4+15) +#define APC_APSM1_FULL_INTR4 (310+4+16) +#define APC_APSM1_FULL_INTR5 (310+4+17) +#define APC_APSM1_FULL_INTR6 (310+4+18) +#define APC_APSM1_FULL_INTR7 (310+4+19) + +#define APC_AP_CSU_INTR0 (310+28) +#define APC_AP_CSU_INTR1 (310+29) +#define APC_AP_CSU_INTR2 (310+30) +#define APC_AP_CSU_INTR3 (310+31) +#define APC_AP_CSU_INTR4 (310+32) +#define APC_AP_CSU_INTR5 (310+33) +#define APC_AP_CSU_INTR6 (310+34) +#define APC_AP_CSU_INTR7 (310+35) +#define APC_SYSC_CTC10_INTR0 (310+36) +#define APC_SYSC_CTC11_INTR0 (310+37) +#define APC_SYSC_CTC12_INTR0 (310+38) +#define APC_SYSC_CTC13_INTR0 (310+39) +#define APC_SYSC_CTC14_INTR0 (310+40) +#define APC_SYSC_CTC15_INTR0 (310+41) +#define APC_SYSC_CTC16_INTR0 (310+42) +#define APC_SYSC_CTC17_INTR0 (310+43) +#define APC_SYSC_CTC18_INTR0 (310+44) +#define APC_SYSC_CTC19_INTR0 (310+45) +#define APC_SYSC_CTC20_INTR0 (310+46) +#define APC_SYSC_CTC21_INTR0 (310+47) +#define APC_SYSC_CTC22_INTR0 (310+48) +#define APC_SYSC_CTC23_INTR0 (310+49) +#define APC_SYSC_CTC24_INTR0 (310+50) +#define APC_SYSC_CTC25_INTR0 (310+51) +#define APC_SYSC_CTC26_INTR0 (310+52) +#define APC_SYSC_CTC27_INTR0 (310+53) +#define APC_SYSC_CTC28_INTR0 (310+54) +#define APC_SYSC_CTC29_INTR0 (310+55) +#define APC_SYSC_CTC30_INTR0 (310+56) +#define APC_SYSC_CTC31_INTR0 (310+57) +#define APC_SYSC_CTC32_INTR0 (310+58) +#define APC_SYSC_CTC33_INTR0 (310+59) +#define APC_SYSC_CTC34_INTR0 (310+60) +#define APC_SYSC_CTC35_INTR0 (310+61) +#define APC_SYSC_CTC36_INTR0 (310+62) +#define APC_SYSC_CTC37_INTR0 (310+63) +#define APC_SYSC_CTC38_INTR0 (310+64) +#define APC_SYSC_CTC39_INTR0 (310+65) +#define APC_SYSC_CTC40_INTR0 (310+66) +#define APC_SYSC_CTC41_INTR0 (310+67) +#define APC_SYSC_CTC42_INTR0 (310+68) +#define APC_SYSC_CTC43_INTR0 (310+69) +#define APC_SYSC_CTC44_INTR0 (310+70) +#define APC_SYSC_CTC45_INTR0 (310+71) +#define APC_SYSC_CTC46_INTR0 (310+72) +#define APC_SYSC_CTC47_INTR0 (310+73) +#define APC_SYSC_CTC48_INTR0 (310+74) +#define APC_SYSC_CTC49_INTR0 (310+75) +#define APC_SYSC_CTC50_INTR0 (310+76) +#define APC_SYSC_CTC51_INTR0 (310+77) +#define APC_SYSC_CTC52_INTR0 (310+78) +#define APC_SYSC_CTC53_INTR0 (310+79) +#define APC_SYSC_CTC54_INTR0 (310+80) +#define APC_SYSC_CTC55_INTR0 (310+81) +#define APC_SYSC_CTC56_INTR0 (310+82) +#define APC_SYSC_CTC57_INTR0 (310+83) +#define APC_SYSC_CTC58_INTR0 (310+84) +#define APC_SYSC_CTC59_INTR0 (310+85) +#define APC_SYSC_CTC60_INTR0 (310+86) +#define APC_SYSC_CTC61_INTR0 (310+87) +#define APC_SYSC_CTC62_INTR0 (310+88) +#define APC_SYSC_CTC63_INTR0 (310+89) +#define APC_SYSC_CTC64_INTR0 (310+90) +#define APC_SYSC_CTC65_INTR0 (310+91) +#define APC_SYSC_CTC66_INTR0 (310+92) +#define APC_SYSC_CTC67_INTR0 (310+93) +#define APC_SYSC_CTC68_INTR0 (310+94) +#define APC_SYSC_CTC69_INTR0 (310+95) +#define APC_SYSC_CTC70_INTR0 (310+96) +#define APC_SYSC_CTC71_INTR0 (310+97) + +#define APC_JESD_TX0_SBU0_TMR_INTR0 408 +#define APC_JESD_TX0_SBU0_TMR_INTR1 409 +#define APC_JESD_TX0_SBU0_TMR_INTR2 410 +#define APC_JESD_TX0_SBU0_TMR_INTR3 411 +#define APC_JESD_TX0_SBU0_TMR_INTR4 412 +#define APC_JESD_TX0_SBU0_TMR_INTR5 413 +#define APC_JESD_TX0_SBU0_TMR_INTR6 414 +#define APC_JESD_TX0_SBU0_TMR_INTR7 415 +#define APC_JESD_TX0_SBU0_TMR_INTR8 416 +#define APC_JESD_TX0_SBU0_TMR_INTR9 417 +#define APC_JESD_TX0_SBU0_TMR_INTR10 418 +#define APC_JESD_TX0_SBU0_TMR_INTR11 419 + +#define APC_JESD_TX_SBU1_TMR_INTR0 420 +#define APC_JESD_TX_SBU1_TMR_INTR1 421 +#define APC_JESD_TX_SBU1_TMR_INTR2 422 +#define APC_JESD_TX_SBU1_TMR_INTR3 423 +#define APC_JESD_TX_SBU1_TMR_INTR4 424 +#define APC_JESD_TX_SBU1_TMR_INTR5 425 +#define APC_JESD_TX_SBU1_TMR_INTR6 426 +#define APC_JESD_TX_SBU1_TMR_INTR7 427 +#define APC_JESD_TX_SBU1_TMR_INTR8 428 +#define APC_JESD_TX_SBU1_TMR_INTR9 429 +#define APC_JESD_TX_SBU1_TMR_INTR10 430 +#define APC_JESD_TX_SBU1_TMR_INTR11 431 + +#define APC_JESD_TX1_SBU0_TMR_INTR0 266 +#define APC_JESD_TX1_SBU0_TMR_INTR1 267 +#define APC_JESD_TX1_SBU0_TMR_INTR2 268 +#define APC_JESD_TX1_SBU0_TMR_INTR3 269 +#define APC_JESD_TX1_SBU0_TMR_INTR4 270 +#define APC_JESD_TX1_SBU0_TMR_INTR5 271 +#define APC_JESD_TX1_SBU0_TMR_INTR6 272 +#define APC_JESD_TX1_SBU0_TMR_INTR7 273 +#define APC_JESD_TX1_SBU0_TMR_INTR8 274 +#define APC_JESD_TX1_SBU0_TMR_INTR9 275 +#define APC_JESD_TX1_SBU0_TMR_INTR10 276 +#define APC_JESD_TX1_SBU0_TMR_INTR11 277 + +#define APC_JS_CSU_TXRX1_INTR0 432 +#define APC_JS_CSU_TXRX1_INTR1 433 +#define APC_JS_CSU_TXRX1_INTR2 434 +#define APC_JS_CSU_TXRX1_INTR3 435 +#define APC_JS_CSU_TXRX1_INTR4 436 +#define APC_JS_CSU_TXRX1_INTR5 437 +#define APC_JS_CSU_TXRX1_INTR6 438 +#define APC_JS_CSU_TXRX1_INTR7 439 + +#define APC_JECS_CSU_INTR0 440 +#define APC_JECS_CSU_INTR1 441 +#define APC_JECS_CSU_INTR2 442 +#define APC_JECS_CSU_INTR3 443 +#define APC_JECS_CSU_INTR4 444 +#define APC_JECS_CSU_INTR5 445 +#define APC_JECS_CSU_INTR6 446 +#define APC_JECS_CSU_INTR7 447 + +#define APC_JECS_CSU_TXRX1_INTR0 448 +#define APC_JECS_CSU_TXRX1_INTR1 449 +#define APC_JECS_CSU_TXRX1_INTR2 450 +#define APC_JECS_CSU_TXRX1_INTR3 451 +#define APC_JECS_CSU_TXRX1_INTR4 452 +#define APC_JECS_CSU_TXRX1_INTR5 453 +#define APC_JECS_CSU_TXRX1_INTR6 454 +#define APC_JECS_CSU_TXRX1_INTR7 455 + + +#define APC_EIP0_GLOBLE_INT 117 +#define APC_EIP0_RING0_INT 118 +#define APC_EIP0_RING1_INT 119 +#define APC_EIP0_RING2_INT 456 +#define APC_EIP0_RING3_INT 457 +#define APC_EIP1_GLOBLE_INT 458 +#define APC_EIP1_RING0_INT 459 +#define APC_EIP1_RING1_INT 460 +#define APC_EIP1_RING2_INT 461 +#define APC_EIP1_RING3_INT 462 + +#define APC_GMAC0SDB_INT 463 +#define APC_GMAC0PMT_INT 464 +#define APC_GMAC0LPI_INT 465 + + + +#define APC_JESD_RX0_SBU1_TMR_INTR0 471 +#define APC_JESD_RX0_SBU1_TMR_INTR1 472 +#define APC_JESD_RX0_SBU1_TMR_INTR2 473 +#define APC_JESD_RX0_SBU1_TMR_INTR3 474 +#define APC_JESD_RX0_SBU1_TMR_INTR4 475 +#define APC_JESD_RX0_SBU1_TMR_INTR5 476 +#define APC_JESD_RX0_SBU1_TMR_INTR6 477 +#define APC_JESD_RX0_SBU1_TMR_INTR7 478 +#define APC_JESD_RX0_SBU1_TMR_INTR8 479 +#define APC_JESD_RX0_SBU1_TMR_INTR9 480 +#define APC_JESD_RX0_SBU1_TMR_INTR10 481 +#define APC_JESD_RX0_SBU1_TMR_INTR11 482 + +#define APC_JESD_RX1_SBU0_TMR_INTR0 483 +#define APC_JESD_RX1_SBU0_TMR_INTR1 484 +#define APC_JESD_RX1_SBU0_TMR_INTR2 485 +#define APC_JESD_RX1_SBU0_TMR_INTR3 486 +#define APC_JESD_RX1_SBU0_TMR_INTR4 487 +#define APC_JESD_RX1_SBU0_TMR_INTR5 488 +#define APC_JESD_RX1_SBU0_TMR_INTR6 489 +#define APC_JESD_RX1_SBU0_TMR_INTR7 490 +#define APC_JESD_RX1_SBU0_TMR_INTR8 491 +#define APC_JESD_RX1_SBU0_TMR_INTR9 492 +#define APC_JESD_RX1_SBU0_TMR_INTR10 493 +#define APC_JESD_RX1_SBU0_TMR_INTR11 494 + +#define APC_JESD_RX1_SBU1_TMR_INTR0 495 +#define APC_JESD_RX1_SBU1_TMR_INTR1 496 +#define APC_JESD_RX1_SBU1_TMR_INTR2 497 +#define APC_JESD_RX1_SBU1_TMR_INTR3 498 +#define APC_JESD_RX1_SBU1_TMR_INTR4 499 +#define APC_JESD_RX1_SBU1_TMR_INTR5 500 +#define APC_JESD_RX1_SBU1_TMR_INTR6 501 +#define APC_JESD_RX1_SBU1_TMR_INTR7 502 +#define APC_JESD_RX1_SBU1_TMR_INTR8 503 +#define APC_JESD_RX1_SBU1_TMR_INTR9 504 +#define APC_JESD_RX1_SBU1_TMR_INTR10 505 +#define APC_JESD_RX1_SBU1_TMR_INTR11 506 + + +#define APC_EIP2_GLOBLE_INT 93 +#define APC_EIP2_RING0_INT 507 +#define APC_EIP2_RING1_INT 508 +#define APC_EIP2_RING2_INT 509 +#define APC_EIP2_RING3_INT 510 + +#define APC_PCIE_INTR 511 + + + +#define APC_INPUT0 145 +#define APC_INPUT1 165 +#define APC_INPUT2 185 +#define APC_INPUT3 205 +#define APC_INPUT4 225 +#define APC_INPUT5 310+8 + +//APC interconnect int +#define APC_INPUT0_INTR0 (0+ APC_INPUT0) +#define APC_INPUT0_INTR1 (1+ APC_INPUT0) +#define APC_INPUT0_INTR2 (2+ APC_INPUT0) +#define APC_INPUT0_INTR3 (3+ APC_INPUT0) +#define APC_INPUT0_INTR4 (4+ APC_INPUT0) +#define APC_INPUT0_INTR5 (5+ APC_INPUT0) +#define APC_INPUT0_INTR6 (6+ APC_INPUT0) +#define APC_INPUT0_INTR7 (7+ APC_INPUT0) +#define APC_INPUT0_INTR8 (8+ APC_INPUT0) +#define APC_INPUT0_INTR9 (9+ APC_INPUT0) +#define APC_INPUT0_INTR10 (10+APC_INPUT0) +#define APC_INPUT0_INTR11 (11+APC_INPUT0) +#define APC_INPUT0_INTR12 (12+APC_INPUT0) +#define APC_INPUT0_INTR13 (13+APC_INPUT0) +#define APC_INPUT0_INTR14 (14+APC_INPUT0) +#define APC_INPUT0_INTR15 (15+APC_INPUT0) +#define APC_INPUT0_INTR16 (16+APC_INPUT0) +#define APC_INPUT0_INTR17 (17+APC_INPUT0) +#define APC_INPUT0_INTR18 (18+APC_INPUT0) +#define APC_INPUT0_INTR19 (19+APC_INPUT0) + +#define APC_INPUT1_INTR0 (0+ APC_INPUT1) +#define APC_INPUT1_INTR1 (1+ APC_INPUT1) +#define APC_INPUT1_INTR2 (2+ APC_INPUT1) +#define APC_INPUT1_INTR3 (3+ APC_INPUT1) +#define APC_INPUT1_INTR4 (4+ APC_INPUT1) +#define APC_INPUT1_INTR5 (5+ APC_INPUT1) +#define APC_INPUT1_INTR6 (6+ APC_INPUT1) +#define APC_INPUT1_INTR7 (7+ APC_INPUT1) +#define APC_INPUT1_INTR8 (8+ APC_INPUT1) +#define APC_INPUT1_INTR9 (9+ APC_INPUT1) +#define APC_INPUT1_INTR10 (10+APC_INPUT1) +#define APC_INPUT1_INTR11 (11+APC_INPUT1) +#define APC_INPUT1_INTR12 (12+APC_INPUT1) +#define APC_INPUT1_INTR13 (13+APC_INPUT1) +#define APC_INPUT1_INTR14 (14+APC_INPUT1) +#define APC_INPUT1_INTR15 (15+APC_INPUT1) +#define APC_INPUT1_INTR16 (16+APC_INPUT1) +#define APC_INPUT1_INTR17 (17+APC_INPUT1) +#define APC_INPUT1_INTR18 (18+APC_INPUT1) +#define APC_INPUT1_INTR19 (19+APC_INPUT1) + +#define APC_INPUT2_INTR0 (0+ APC_INPUT2) +#define APC_INPUT2_INTR1 (1+ APC_INPUT2) +#define APC_INPUT2_INTR2 (2+ APC_INPUT2) +#define APC_INPUT2_INTR3 (3+ APC_INPUT2) +#define APC_INPUT2_INTR4 (4+ APC_INPUT2) +#define APC_INPUT2_INTR5 (5+ APC_INPUT2) +#define APC_INPUT2_INTR6 (6+ APC_INPUT2) +#define APC_INPUT2_INTR7 (7+ APC_INPUT2) +#define APC_INPUT2_INTR8 (8+ APC_INPUT2) +#define APC_INPUT2_INTR9 (9+ APC_INPUT2) +#define APC_INPUT2_INTR10 (10+APC_INPUT2) +#define APC_INPUT2_INTR11 (11+APC_INPUT2) +#define APC_INPUT2_INTR12 (12+APC_INPUT2) +#define APC_INPUT2_INTR13 (13+APC_INPUT2) +#define APC_INPUT2_INTR14 (14+APC_INPUT2) +#define APC_INPUT2_INTR15 (15+APC_INPUT2) +#define APC_INPUT2_INTR16 (16+APC_INPUT2) +#define APC_INPUT2_INTR17 (17+APC_INPUT2) +#define APC_INPUT2_INTR18 (18+APC_INPUT2) +#define APC_INPUT2_INTR19 (19+APC_INPUT2) + +#define APC_INPUT3_INTR0 (0+ APC_INPUT3) +#define APC_INPUT3_INTR1 (1+ APC_INPUT3) +#define APC_INPUT3_INTR2 (2+ APC_INPUT3) +#define APC_INPUT3_INTR3 (3+ APC_INPUT3) +#define APC_INPUT3_INTR4 (4+ APC_INPUT3) +#define APC_INPUT3_INTR5 (5+ APC_INPUT3) +#define APC_INPUT3_INTR6 (6+ APC_INPUT3) +#define APC_INPUT3_INTR7 (7+ APC_INPUT3) +#define APC_INPUT3_INTR8 (8+ APC_INPUT3) +#define APC_INPUT3_INTR9 (9+ APC_INPUT3) +#define APC_INPUT3_INTR10 (10+APC_INPUT3) +#define APC_INPUT3_INTR11 (11+APC_INPUT3) +#define APC_INPUT3_INTR12 (12+APC_INPUT3) +#define APC_INPUT3_INTR13 (13+APC_INPUT3) +#define APC_INPUT3_INTR14 (14+APC_INPUT3) +#define APC_INPUT3_INTR15 (15+APC_INPUT3) +#define APC_INPUT3_INTR16 (16+APC_INPUT3) +#define APC_INPUT3_INTR17 (17+APC_INPUT3) +#define APC_INPUT3_INTR18 (18+APC_INPUT3) +#define APC_INPUT3_INTR19 (19+APC_INPUT3) + +#define APC_INPUT4_INTR0 (0+ APC_INPUT4) +#define APC_INPUT4_INTR1 (1+ APC_INPUT4) +#define APC_INPUT4_INTR2 (2+ APC_INPUT4) +#define APC_INPUT4_INTR3 (3+ APC_INPUT4) +#define APC_INPUT4_INTR4 (4+ APC_INPUT4) +#define APC_INPUT4_INTR5 (5+ APC_INPUT4) +#define APC_INPUT4_INTR6 (6+ APC_INPUT4) +#define APC_INPUT4_INTR7 (7+ APC_INPUT4) +#define APC_INPUT4_INTR8 (8+ APC_INPUT4) +#define APC_INPUT4_INTR9 (9+ APC_INPUT4) +#define APC_INPUT4_INTR10 (10+APC_INPUT4) +#define APC_INPUT4_INTR11 (11+APC_INPUT4) +#define APC_INPUT4_INTR12 (12+APC_INPUT4) +#define APC_INPUT4_INTR13 (13+APC_INPUT4) +#define APC_INPUT4_INTR14 (14+APC_INPUT4) +#define APC_INPUT4_INTR15 (15+APC_INPUT4) +#define APC_INPUT4_INTR16 (16+APC_INPUT4) +#define APC_INPUT4_INTR17 (17+APC_INPUT4) +#define APC_INPUT4_INTR18 (18+APC_INPUT4) +#define APC_INPUT4_INTR19 (19+APC_INPUT4) + +#define APC_INPUT5_INTR0 (0+ APC_INPUT5) +#define APC_INPUT5_INTR1 (1+ APC_INPUT5) +#define APC_INPUT5_INTR2 (2+ APC_INPUT5) +#define APC_INPUT5_INTR3 (3+ APC_INPUT5) +#define APC_INPUT5_INTR4 (4+ APC_INPUT5) +#define APC_INPUT5_INTR5 (5+ APC_INPUT5) +#define APC_INPUT5_INTR6 (6+ APC_INPUT5) +#define APC_INPUT5_INTR7 (7+ APC_INPUT5) +#define APC_INPUT5_INTR8 (8+ APC_INPUT5) +#define APC_INPUT5_INTR9 (9+ APC_INPUT5) +#define APC_INPUT5_INTR10 (10+APC_INPUT5) +#define APC_INPUT5_INTR11 (11+APC_INPUT5) +#define APC_INPUT5_INTR12 (12+APC_INPUT5) +#define APC_INPUT5_INTR13 (13+APC_INPUT5) +#define APC_INPUT5_INTR14 (14+APC_INPUT5) +#define APC_INPUT5_INTR15 (15+APC_INPUT5) +#define APC_INPUT5_INTR16 (16+APC_INPUT5) +#define APC_INPUT5_INTR17 (17+APC_INPUT5) +#define APC_INPUT5_INTR18 (18+APC_INPUT5) +#define APC_INPUT5_INTR19 (19+APC_INPUT5) + + +#define APRFM_SYSC_CTC8_INTR0 570 +#define APRFM_SYSC_CTC9_INTR0 571 +#define APRFM_SYSC_CTC10_INTR0 572 +#define APRFM_SYSC_CTC11_INTR0 573 +#define APRFM_SYSC_CTC12_INTR0 574 +#define APRFM_SYSC_CTC13_INTR0 575 +#define APRFM_SYSC_CTC14_INTR0 576 +#define APRFM_SYSC_CTC15_INTR0 577 + + +#define PPS_OUT_INTR (175+460) +//define ARM INTERRUPT NUM +#define PETRFM2SYS_INTR0 (175+280) +#define PETRFM2SYS_INTR1 (175+281) +#define PETRFM2SYS_INTR2 (175+282) +#define PETRFM2SYS_INTR3 (175+283) +#define PETRFM2SYS_INTR4 (175+284) +#define PETRFM2SYS_INTR5 (175+285) +#define PETRFM2SYS_INTR6 (175+286) +#define PETRFM2SYS_INTR7 (175+287) +#define PETRFM2SYS_INTR8 (175+288) +#define PETRFM2SYS_INTR9 (175+289) +#define PETRFM2SYS_INTR10 (175+290) +#define PETRFM2SYS_INTR11 (175+291) +#define PETRFM2SYS_INTR12 (175+292) +#define PETRFM2SYS_INTR13 (175+293) +#define PETRFM2SYS_INTR14 (175+294) +#define PETRFM2SYS_INTR15 (175+295) +#define PETRFM2SYS_INTR16 (175+296) +#define PETRFM2SYS_INTR17 (175+297) +#define PETRFM2SYS_INTR18 (175+298) +#define PETRFM2SYS_INTR19 (175+299) +#define JECS_RFM_OUT_INTR0 (175+300) +#define JECS_RFM_OUT_INTR1 (175+301) +#define JECS_RFM_OUT_INTR2 (175+302) +#define JECS_RFM_OUT_INTR3 (175+303) +#define JECS_RFM_OUT_INTR4 (175+304) +#define JECS_RFM_OUT_INTR5 (175+305) +#define JECS_RFM_OUT_INTR6 (175+306) +#define JECS_RFM_OUT_INTR7 (175+307) +#define JECS_RFM_OUT_INTR8 (175+308) +#define JECS_RFM_OUT_INTR9 (175+309) +#define JECS_RFM_OUT_INTR10 (175+310) +#define JECS_RFM_OUT_INTR11 (175+311) +#define JECS_RFM_OUT_INTR12 (175+312) +#define JECS_RFM_OUT_INTR13 (175+313) +#define JECS_RFM_OUT_INTR14 (175+314) +#define JECS_RFM_OUT_INTR15 (175+315) +#define JECS_RFM_OUT_INTR16 (175+316) +#define JECS_RFM_OUT_INTR17 (175+317) +#define JECS_RFM_OUT_INTR18 (175+318) +#define JECS_RFM_OUT_INTR19 (175+319) +#define RFC_INTR0 (175+320) +#define RFC_INTR1 (175+321) +#define RFC_INTR2 (175+322) +#define RFCSU_RX_INTR (175+323) +#define RFCSU_TX_INTR (175+324) + +#define JESD_RX0_SBU0_TMR_INTR0 (175+162+325-162) +#define JESD_RX0_SBU0_TMR_INTR1 (175+163+325-162) +#define JESD_RX0_SBU0_TMR_INTR2 (175+164+325-162) +#define JESD_RX0_SBU0_TMR_INTR3 (175+165+325-162) +#define JESD_RX0_SBU0_TMR_INTR4 (175+166+325-162) +#define JESD_RX0_SBU0_TMR_INTR5 (175+167+325-162) +#define JESD_RX0_SBU0_TMR_INTR6 (175+168+325-162) +#define JESD_RX0_SBU0_TMR_INTR7 (175+169+325-162) +#define JESD_RX0_SBU0_TMR_INTR8 (175+170+325-162) +#define JESD_RX0_SBU0_TMR_INTR9 (175+171+325-162) +#define JESD_RX0_SBU0_TMR_INTR10 (175+172+325-162) +#define JESD_RX0_SBU0_TMR_INTR11 (175+173+325-162) +//#define JESD_RX0_SBU1_TMR_INTR0 (175+162+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR1 (175+163+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR2 (175+164+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR3 (175+165+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR4 (175+166+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR5 (175+167+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR6 (175+168+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR7 (175+169+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR8 (175+170+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR9 (175+171+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR10 (175+172+424-162)tie 0 +//#define JESD_RX0_SBU1_TMR_INTR11 (175+173+424-162)tie 0 +#define JESD_RX1_SBU0_TMR_INTR0 (175+162+436-162) +#define JESD_RX1_SBU0_TMR_INTR1 (175+163+436-162) +#define JESD_RX1_SBU0_TMR_INTR2 (175+164+436-162) +#define JESD_RX1_SBU0_TMR_INTR3 (175+165+436-162) +#define JESD_RX1_SBU0_TMR_INTR4 (175+166+436-162) +#define JESD_RX1_SBU0_TMR_INTR5 (175+167+436-162) +#define JESD_RX1_SBU0_TMR_INTR6 (175+168+436-162) +#define JESD_RX1_SBU0_TMR_INTR7 (175+169+436-162) +#define JESD_RX1_SBU0_TMR_INTR8 (175+170+436-162) +#define JESD_RX1_SBU0_TMR_INTR9 (175+171+436-162) +#define JESD_RX1_SBU0_TMR_INTR10 (175+172+436-162) +#define JESD_RX1_SBU0_TMR_INTR11 (175+173+436-162) +//#define JESD_RX1_SBU1_TMR_INTR0 (175+162+448-162) +//#define JESD_RX1_SBU1_TMR_INTR1 (175+163+448-162) +//#define JESD_RX1_SBU1_TMR_INTR2 (175+164+448-162) +//#define JESD_RX1_SBU1_TMR_INTR3 (175+165+448-162) +//#define JESD_RX1_SBU1_TMR_INTR4 (175+166+448-162) +//#define JESD_RX1_SBU1_TMR_INTR5 (175+167+448-162) +//#define JESD_RX1_SBU1_TMR_INTR6 (175+168+448-162) +//#define JESD_RX1_SBU1_TMR_INTR7 (175+169+448-162) +//#define JESD_RX1_SBU1_TMR_INTR8 (175+170+448-162) +//#define JESD_RX1_SBU1_TMR_INTR9 (175+171+448-162) +//#define JESD_RX1_SBU1_TMR_INTR10 (175+172+448-162) +//#define JESD_RX1_SBU1_TMR_INTR11 (175+173+448-162) +#define SLAVE_INTERRUPT_204B_RX0 (175+337) +#define SLAVE_INTERRUPT_204B_RX1 (175+339) +#define SLAVE_INTERRUPT_204B_TX0 (175+341) +#define SLAVE_INTERRUPT_204C_RX0 (175+368) +#define SLAVE_INTERRUPT_204C_RX1 (175+369) +#define SLAVE_INTERRUPT_204C_TX0 (175+370) +#define JECS_CTC_INTR0 (175+343) +#define JECS_CTC_INTR1 (175+344) +#define PET_CTC_INTR0 (175+345) +#define PET_CTC_INTR1 (175+346) +#define EIP2_RING2_INT (175+347) +#define EIP2_RING3_INT (175+348) +#define RFC_DMA_INTR (175+349) +#define JESDA_CSU_INTR (175+350) +#define JESDA_CSU_TX_INTR (175+351) +#define JECS_CSU_INTR (175+352) +#define JESDB_CSU_TX_INTR (175+353) +#define ECPRI_SUB_INTR0 (175+360) +#define ECPRI_SUB_INTR1 (175+361) +#define ECPRI_SUB_INTR2 (175+362) +#define ECPRI_SUB_INTR3 (175+363) +#define ECPRI_SUB_INTR4 (175+364) +#define ECPRI_SUB_INTR5 (175+365) +//#define ECPRI_SUB_INTR6 (175+366) +//#define ECPRI_SUB_INTR7 (175+367) +#define JESD_204B_SUBCTRL_INTR (175+366) +#define JESD_204C_SUBCTRL_INTR (175+367) +//#define ECPRI_SUB_INTR8 (175+368) +//#define ECPRI_SUB_INTR9 (175+369) +//#define ECPRI_SUB_INTR10 (175+370) +#define ECPRI_SUB_INTR11 (175+371) +#define ECPRI_SUB_INTR12 (175+372) +#define ECPRI_SUB_INTR13 (175+373) +#define ECPRI_SUB_INTR14 (175+374) +#define ECPRI_SUB_INTR15 (175+375) +#define ECPRI_SUB_INTR16 (175+376) +#define ECPRI_SUB_INTR17 (175+377) +#define ECPRI_SUB_INTR18 (175+378) +#define ECPRI_SUB_INTR19 (175+379) +#define ECPRI_SUB_INTR20 (175+380) +#define ECPRI_SUB_INTR21 (175+381) +#define ECPRI_SUB_INTR22 (175+382) +#define ECPRI_SUB_INTR23 (175+383) +#define ECPRI_SUB_INTR24 (175+384) +#define ECPRI_SUB_INTR25 (175+385) +#define ECPRI_SUB_INTR26 (175+386) +#define ECPRI_SUB_INTR27 (175+387) +#define ECPRI_SUB_INTR28 (175+388) +#define ECPRI_SUB_INTR29 (175+389) +#define ECPRI_SUB_INTR30 (175+390) +#define ECPRI_SUB_INTR31 (175+391) +#define CPRI_SUB_INTR0 (175+392) +#define CPRI_SUB_INTR1 (175+393) +#define STC_INTR0 (175+394) +#define STC_INTR1 (175+395) +#define STC_INTR2 (175+396) +#define STC_INTR3 (175+397) +#define STC_INTR4 (175+398) +#define STC_INTR5 (175+399) +#define STC_INTR6 (175+400) +#define STC_INTR7 (175+401) +#define STC_INTR8 (175+402) +#define STC_INTR9 (175+403) +#define STC_INTR10 (175+404) + +#define CPRI_TMR_INTR0 (175+405) +#define CPRI_TMR_INTR1 (175+406) +#define CPRI_TMR_INTR2 (175+407) +#define CPRI_TMR_INTR3 (175+408) +#define CPRI_TMR_INTR4 (175+409) +#define CPRI_TMR_INTR5 (175+410) +#define CPRI_TMR_INTR6 (175+411) +#define CPRI_TMR_INTR7 (175+412) +#define CPRI_TMR_INTR8 (175+413) +#define CPRI_TMR_INTR9 (175+414) +#define CPRI_TMR_INTR10 (175+415) +#define CPRI_TMR_INTR11 (175+416) +#define APC3OUT_INTR0 (175+260) +#define APC3OUT_INTR1 (175+261) +#define APC3OUT_INTR2 (175+262) +#define APC3OUT_INTR3 (175+263) +#define APC3OUT_INTR4 (175+264) +#define APC3OUT_INTR5 (175+265) +#define APC3OUT_INTR6 (175+266) +#define APC3OUT_INTR7 (175+267) +#define APC3OUT_INTR8 (175+268) +#define APC3OUT_INTR9 (175+269) +#define APC3OUT_INTR10 (175+270) +#define APC3OUT_INTR11 (175+271) +#define APC3OUT_INTR12 (175+272) +#define APC3OUT_INTR13 (175+273) +#define APC3OUT_INTR14 (175+274) +#define APC3OUT_INTR15 (175+275) +#define APC3OUT_INTR16 (175+276) +#define APC3OUT_INTR17 (175+277) +#define APC3OUT_INTR18 (175+278) +#define APC3OUT_INTR19 (175+279) +#define APC2OUT_INTR0 (175+240) +#define APC2OUT_INTR1 (175+241) +#define APC2OUT_INTR2 (175+242) +#define APC2OUT_INTR3 (175+243) +#define APC2OUT_INTR4 (175+244) +#define APC2OUT_INTR5 (175+245) +#define APC2OUT_INTR6 (175+246) +#define APC2OUT_INTR7 (175+247) +#define APC2OUT_INTR8 (175+248) +#define APC2OUT_INTR9 (175+249) +#define APC2OUT_INTR10 (175+250) +#define APC2OUT_INTR11 (175+251) +#define APC2OUT_INTR12 (175+252) +#define APC2OUT_INTR13 (175+253) +#define APC2OUT_INTR14 (175+254) +#define APC2OUT_INTR15 (175+255) +#define APC2OUT_INTR16 (175+256) +#define APC2OUT_INTR17 (175+257) +#define APC2OUT_INTR18 (175+258) +#define APC2OUT_INTR19 (175+259) +#define APC1OUT_INTR0 (175+220) +#define APC1OUT_INTR1 (175+221) +#define APC1OUT_INTR2 (175+222) +#define APC1OUT_INTR3 (175+223) +#define APC1OUT_INTR4 (175+224) +#define APC1OUT_INTR5 (175+225) +#define APC1OUT_INTR6 (175+226) +#define APC1OUT_INTR7 (175+227) +#define APC1OUT_INTR8 (175+228) +#define APC1OUT_INTR9 (175+229) +#define APC1OUT_INTR10 (175+230) +#define APC1OUT_INTR11 (175+231) +#define APC1OUT_INTR12 (175+232) +#define APC1OUT_INTR13 (175+233) +#define APC1OUT_INTR14 (175+234) +#define APC1OUT_INTR15 (175+235) +#define APC1OUT_INTR16 (175+236) +#define APC1OUT_INTR17 (175+237) +#define APC1OUT_INTR18 (175+238) +#define APC1OUT_INTR19 (175+239) +#define APC0OUT_INTR0 (175+200) +#define APC0OUT_INTR1 (175+201) +#define APC0OUT_INTR2 (175+202) +#define APC0OUT_INTR3 (175+203) +#define APC0OUT_INTR4 (175+204) +#define APC0OUT_INTR5 (175+205) +#define APC0OUT_INTR6 (175+206) +#define APC0OUT_INTR7 (175+207) +#define APC0OUT_INTR8 (175+208) +#define APC0OUT_INTR9 (175+209) +#define APC0OUT_INTR10 (175+210) +#define APC0OUT_INTR11 (175+211) +#define APC0OUT_INTR12 (175+212) +#define APC0OUT_INTR13 (175+213) +#define APC0OUT_INTR14 (175+214) +#define APC0OUT_INTR15 (175+215) +#define APC0OUT_INTR16 (175+216) +#define APC0OUT_INTR17 (175+217) +#define APC0OUT_INTR18 (175+218) +#define APC0OUT_INTR19 (175+219) +#define UART3_INTR (175+197) +#define UART2_INTR (175+196) +#define TIMER27_INTR (175+195) +#define TIMER26_INTR (175+194) +#define TIMER25_INTR (175+193) +#define TIMER24_INTR (175+192) +#define TIMER23_INTR (175+191) +#define TIMER22_INTR (175+190) +#define TIMER21_INTR (175+189) +#define TIMER20_INTR (175+188) +#define TIMER17_INTR (175+187) +#define TIMER16_INTR (175+186) +#define TIMER15_INTR (175+185) +#define TIMER14_INTR (175+184) +#define TIMER13_INTR (175+183) +#define TIMER12_INTR (175+182) +#define TIMER11_INTR (175+181) +#define TIMER10_INTR (175+180) +#define SPI3_INTR (175+179) +#define SPI2_INTR (175+178) +//175+174 175+177 tie 0 +#define JESD_TX0_SBU0_TMR_INTR0 (175+162) +#define JESD_TX0_SBU0_TMR_INTR1 (175+163) +#define JESD_TX0_SBU0_TMR_INTR2 (175+164) +#define JESD_TX0_SBU0_TMR_INTR3 (175+165) +#define JESD_TX0_SBU0_TMR_INTR4 (175+166) +#define JESD_TX0_SBU0_TMR_INTR5 (175+167) +#define JESD_TX0_SBU0_TMR_INTR6 (175+168) +#define JESD_TX0_SBU0_TMR_INTR7 (175+169) +#define JESD_TX0_SBU0_TMR_INTR8 (175+170) +#define JESD_TX0_SBU0_TMR_INTR9 (175+171) +#define JESD_TX0_SBU0_TMR_INTR10 (175+172) +#define JESD_TX0_SBU0_TMR_INTR11 (175+173) +#define JESD_TX_SBU1_TMR_INTR0 (175+174) +#define JESD_TX_SBU1_TMR_INTR1 (175+175) +#define JESD_TX_SBU1_TMR_INTR2 (175+176) +#define JESD_TX_SBU1_TMR_INTR3 (175+177) +#define JESD_TX_SBU1_TMR_INTR4 (175+198) +#define JESD_TX_SBU1_TMR_INTR5 (175+199) +#define JESD_TX_SBU1_TMR_INTR6 (175+354) +#define JESD_TX_SBU1_TMR_INTR7 (175+355) +#define JESD_TX_SBU1_TMR_INTR8 (175+356) +#define JESD_TX_SBU1_TMR_INTR9 (175+357) +#define JESD_TX_SBU1_TMR_INTR10 (175+358) +#define JESD_TX_SBU1_TMR_INTR11 (175+359) + +#define JESD_TX1_SBU0_TMR_INTR0 (175+371) +#define JESD_TX1_SBU0_TMR_INTR1 (175+372) +#define JESD_TX1_SBU0_TMR_INTR2 (175+373) +#define JESD_TX1_SBU0_TMR_INTR3 (175+374) +#define JESD_TX1_SBU0_TMR_INTR4 (175+375) +#define JESD_TX1_SBU0_TMR_INTR5 (175+376) +#define JESD_TX1_SBU0_TMR_INTR6 (175+377) +#define JESD_TX1_SBU0_TMR_INTR7 (175+378) +#define JESD_TX1_SBU0_TMR_INTR8 (175+379) +#define JESD_TX1_SBU0_TMR_INTR9 (175+380) +#define JESD_TX1_SBU0_TMR_INTR10 (175+381) +#define JESD_TX1_SBU0_TMR_INTR11 (175+382) + + +#define MBX1_LPRI_INTR24 (175+164-16) +#define MBX1_LPRI_INTR25 (175+165-16) +#define MBX1_LPRI_INTR26 (175+166-16) +#define MBX1_LPRI_INTR27 (175+167-16) +#define MBX1_LPRI_INTR28 (175+168-16) +#define MBX1_LPRI_INTR29 (175+169-16) +#define MBX1_LPRI_INTR30 (175+170-16) +#define MBX1_LPRI_INTR31 (175+171-16) +#define MBX1_LPRI_INTR32 (175+172-16) +#define MBX1_LPRI_INTR33 (175+173-16) +#define MBX1_LPRI_INTR34 (175+174-16) +#define MBX1_LPRI_INTR35 (175+175-16) +#define MBX1_LPRI_INTR36 (175+176-16) +#define MBX1_LPRI_INTR37 (175+177-16) + + +#define MBX1_HPRI_INTR24 (175+146-12) +#define MBX1_HPRI_INTR25 (175+147-12) +#define MBX1_HPRI_INTR26 (175+148-12) +#define MBX1_HPRI_INTR27 (175+149-12) +#define MBX1_HPRI_INTR28 (175+150-12) +#define MBX1_HPRI_INTR29 (175+151-12) +#define MBX1_HPRI_INTR30 (175+152-12) +#define MBX1_HPRI_INTR31 (175+153-12) +#define MBX1_HPRI_INTR32 (175+154-12) +#define MBX1_HPRI_INTR33 (175+155-12) +#define MBX1_HPRI_INTR34 (175+156-12) +#define MBX1_HPRI_INTR35 (175+157-12) +#define MBX1_HPRI_INTR36 (175+158-12) +#define MBX1_HPRI_INTR37 (175+159-12) + +#define MBX0_LPRI_INTR24 (175+128-8) +#define MBX0_LPRI_INTR25 (175+129-8) +#define MBX0_LPRI_INTR26 (175+130-8) +#define MBX0_LPRI_INTR27 (175+131-8) +#define MBX0_LPRI_INTR28 (175+132-8) +#define MBX0_LPRI_INTR29 (175+133-8) +#define MBX0_LPRI_INTR30 (175+134-8) +#define MBX0_LPRI_INTR31 (175+135-8) +#define MBX0_LPRI_INTR32 (175+136-8) +#define MBX0_LPRI_INTR33 (175+137-8) +#define MBX0_LPRI_INTR34 (175+138-8) +#define MBX0_LPRI_INTR35 (175+139-8) +#define MBX0_LPRI_INTR36 (175+140-8) +#define MBX0_LPRI_INTR37 (175+141-8) + +#define MBX0_HPRI_INTR24 (175+110-4) +#define MBX0_HPRI_INTR25 (175+111-4) +#define MBX0_HPRI_INTR26 (175+112-4) +#define MBX0_HPRI_INTR27 (175+113-4) +#define MBX0_HPRI_INTR28 (175+114-4) +#define MBX0_HPRI_INTR29 (175+115-4) +#define MBX0_HPRI_INTR30 (175+116-4) +#define MBX0_HPRI_INTR31 (175+117-4) +#define MBX0_HPRI_INTR32 (175+118-4) +#define MBX0_HPRI_INTR33 (175+119-4) +#define MBX0_HPRI_INTR34 (175+120-4) +#define MBX0_HPRI_INTR35 (175+121-4) +#define MBX0_HPRI_INTR36 (175+122-4) +#define MBX0_HPRI_INTR37 (175+123-4) +#define GPIO1_INTR0 (175+74) +#define GPIO1_INTR1 (175+75) +#define GPIO1_INTR2 (175+76) +#define GPIO1_INTR3 (175+77) +#define GPIO1_INTR4 (175+78) +#define GPIO1_INTR5 (175+79) +#define GPIO1_INTR6 (175+80) +#define GPIO1_INTR7 (175+81) +#define GPIO1_INTR8 (175+82) +#define GPIO1_INTR9 (175+83) +#define GPIO1_INTR10 (175+84) +#define GPIO1_INTR11 (175+85) +#define GPIO1_INTR12 (175+86) +#define GPIO1_INTR13 (175+87) +#define GPIO1_INTR14 (175+88) +#define GPIO1_INTR15 (175+89) +#define GPIO1_INTR16 (175+90) +#define GPIO1_INTR17 (175+91) +#define GPIO1_INTR18 (175+92) +#define GPIO1_INTR19 (175+93) +#define GPIO1_INTR20 (175+94) +#define GPIO1_INTR21 (175+95) +#define GPIO1_INTR22 (175+96) +#define GPIO1_INTR23 (175+97) +#define GPIO1_INTR24 (175+98) +#define GPIO1_INTR25 (175+99) +#define GPIO1_INTR26 (175+100) +#define GPIO1_INTR27 (175+101) +#define GPIO1_INTR28 (175+102) +#define GPIO1_INTR29 (175+103) +#define GPIO1_INTR30 (175+104) +#define GPIO1_INTR31 (175+105) +#define DMAS1_INTR (175+73) +#define DPLL_LOCK_INTR (175+72) +#define CPSM_FULL7_INTR (175+71) +#define CPSM_FULL6_INTR (175+70) +#define CPSM_FULL5_INTR (175+69) +#define CPSM_FULL4_INTR (175+68) +#define CPSM_FULL3_INTR (175+67) +#define CPSM_FULL2_INTR (175+66) +#define CPSM_FULL1_INTR (175+65) +#define CPSM_FULL0_INTR (175+64) +#define CPSM_EMPTY7_INTR (175+63) +#define CPSM_EMPTY6_INTR (175+62) +#define CPSM_EMPTY5_INTR (175+61) +#define CPSM_EMPTY4_INTR (175+60) +#define CPSM_EMPTY3_INTR (175+59) +#define CPSM_EMPTY2_INTR (175+58) +#define CPSM_EMPTY1_INTR (175+57) +#define CPSM_EMPTY0_INTR (175+56) +#define JECSSM_FULL7_INTR (175+54+1) +#define JECSSM_FULL6_INTR (175+53+1) +#define JECSSM_FULL5_INTR (175+52+1) +#define JECSSM_FULL4_INTR (175+51+1) +#define JECSSM_FULL3_INTR (175+50+1) +#define JECSSM_FULL2_INTR (175+49+1) +#define JECSSM_FULL1_INTR (175+48+1) +#define JECSSM_FULL0_INTR (175+47+1) +#define JECSSM_EMPTY7_INTR (175+46+1) +#define JECSSM_EMPTY6_INTR (175+45+1) +#define JECSSM_EMPTY5_INTR (175+44+1) +#define JECSSM_EMPTY4_INTR (175+43+1) +#define JECSSM_EMPTY3_INTR (175+42+1) +#define JECSSM_EMPTY2_INTR (175+41+1) +#define JECSSM_EMPTY1_INTR (175+40+1) +#define JECSSM_EMPTY0_INTR (175+39+1) +#define PETSM_FULL7_INTR (175+38+1) +#define PETSM_FULL6_INTR (175+37+1) +#define PETSM_FULL5_INTR (175+36+1) +#define PETSM_FULL4_INTR (175+35+1) +#define PETSM_FULL3_INTR (175+34+1) +#define PETSM_FULL2_INTR (175+33+1) +#define PETSM_FULL1_INTR (175+32+1) +#define PETSM_FULL0_INTR (175+31+1) +#define PETSM_EMPTY7_INTR (175+30+1) +#define PETSM_EMPTY6_INTR (175+29+1) +#define PETSM_EMPTY5_INTR (175+28+1) +#define PETSM_EMPTY4_INTR (175+27+1) +#define PETSM_EMPTY3_INTR (175+26+1) +#define PETSM_EMPTY2_INTR (175+25+1) +#define PETSM_EMPTY1_INTR (175+24+1) +#define PETSM_EMPTY0_INTR (175+23+1) +#define ES_ETHPLL_LOCK_INTR (175+23) +#define EIP2_RING0_INT (175+21) +#define EIP2_RING1_INT (175+22) +#define PET_TMAC_INTR (175+20) +#define PET_PCIE_INTR (175+19) +#define PEREST_INTR (175+383) +#define EIP2_GLOBLE_INT (175+18) +#define SRIO1_RAB_INTR (175+17) +#define SRIO0_RAB_INTR (175+16) +#define JSSM_FULL7_INTR (175+15) +#define JSSM_FULL6_INTR (175+14) +#define JSSM_FULL5_INTR (175+13) +#define JSSM_FULL4_INTR (175+12) +#define JSSM_FULL3_INTR (175+11) +#define JSSM_FULL2_INTR (175+10) +#define JSSM_FULL1_INTR (175+9) +#define JSSM_FULL0_INTR (175+8) +#define JSSM_EMPTY7_INTR (175+7) +#define JSSM_EMPTY6_INTR (175+6) +#define JSSM_EMPTY5_INTR (175+5) +#define JSSM_EMPTY4_INTR (175+4) +#define JSSM_EMPTY3_INTR (175+3) +#define JSSM_EMPTY2_INTR (175+2) +#define JSSM_EMPTY1_INTR (175+1) +#define JSSM_EMPTY0_INTR (175+0) +#define TRNG_INTR 174 +#define SPACC0_INTR 173 +#define PKA_INTR 172 +#define SYSC_CTC9_INTR1 171 +#define SYSC_CTC9_INTR0 170 +#define SYSC_CTC8_INTR1 169 +#define SYSC_CTC8_INTR0 168 +#define SYSC_CTC7_INTR1 167 +#define SYSC_CTC7_INTR0 166 +#define SYSC_CTC6_INTR1 165 +#define SYSC_CTC6_INTR0 164 +#define SYSC_CTC5_INTR1 163 +#define SYSC_CTC5_INTR0 162 +#define SYSC_CTC4_INTR1 161 +#define SYSC_CTC4_INTR0 160 +#define SYSC_CTC3_INTR1 159 +#define SYSC_CTC3_INTR0 158 +#define SYSC_CTC2_INTR1 157 +#define SYSC_CTC2_INTR0 156 +#define SYSC_CTC1_INTR1 155 +#define SYSC_CTC1_INTR0 154 +#define SYSC_CTC0_INTR1 153 +#define SYSC_CTC0_INTR0 152 +#define SYSCTRL_INTR 151 +#define SDIOH_INTR 150 +#define PVT_INTR 149 +#define SMMU_S_INTR 148 +#define SMMU_NS_INTR 147 +#define GICECCFATAL_INTR 146 +#define GICAXIERR_INTR 145 +#define CCINERR_INTR 144 +//112-143 tie0 +#define WDT1_INTR 111 +#define WDT0_INTR 110 +#define USB_INTR 109 +#define UART1_INTR 108 +#define UART0_INTR 107 +#define TIMER07_INTR 106 +#define TIMER06_INTR 105 +#define TIMER05_INTR 104 +#define TIMER04_INTR 103 +#define TIMER03_INTR 102 +#define TIMER02_INTR 101 +#define TIMER01_INTR 100 +#define TIMER00_INTR 99 +#define SPI1_INTR 98 +#define SPI0_INTR 97 +#define RTC_INTR 96 +#define I2C1_INTR 95 +#define I2C0_INTR 94 +#define GPIO0_INTR0 62 +#define GPIO0_INTR1 63 +#define GPIO0_INTR2 64 +#define GPIO0_INTR3 65 +#define GPIO0_INTR4 66 +#define GPIO0_INTR5 67 +#define GPIO0_INTR6 68 +#define GPIO0_INTR7 69 +#define GPIO0_INTR8 70 +#define GPIO0_INTR9 71 +#define GPIO0_INTR10 72 +#define GPIO0_INTR11 73 +#define GPIO0_INTR12 74 +#define GPIO0_INTR13 75 +#define GPIO0_INTR14 76 +#define GPIO0_INTR15 77 +#define GPIO0_INTR16 78 +#define GPIO0_INTR17 79 +#define GPIO0_INTR18 80 +#define GPIO0_INTR19 81 +#define GPIO0_INTR20 82 +#define GPIO0_INTR21 83 +#define GPIO0_INTR22 84 +#define GPIO0_INTR23 85 +#define GPIO0_INTR24 86 +#define GPIO0_INTR25 87 +#define GPIO0_INTR26 88 +#define GPIO0_INTR27 89 +#define GPIO0_INTR28 90 +#define GPIO0_INTR29 91 +#define GPIO0_INTR30 92 +#define GPIO0_INTR31 93 +//53 - 61 tie 0 +#define EIP0_GLOBLE_INT 43 +#define EIP0_RING0_INT 44 +#define EIP0_RING1_INT 45 +#define EIP0_RING2_INT 46 +#define EIP0_RING3_INT 47 +#define EIP1_GLOBLE_INT 48 +#define EIP1_RING0_INT 49 +#define EIP1_RING1_INT 50 +#define EIP1_RING2_INT 51 +#define EIP1_RING3_INT 52 +//#define SPACC1_INTR 38 TIE0 +//#define SPACC2_INTR 39 TIE0 +//#define SPACC3_INTR 40 TIE0 +#define A72NEXTERR_INTR_1 42 +#define A72NINTERR_INTR_1 41 +#define APCSU_INTR0 30 +#define APCSU_INTR1 31 +#define APCSU_INTR2 32 +#define APCSU_INTR3 33 +#define APCSU_INTR4 34 +#define APCSU_INTR5 35 +#define APCSU_INTR6 36 +#define APCSU_INTR7 37 +#define GMAC1SDB_INTR 29 +#define GMAC1PMT_INTR 28 +#define GMAC1LPI_INTR 27 +#define GMAC0SDB_INTR 26 +#define GMAC0PMT_INTR 25 +#define GMAC0LPI_INTR 24 +#define EFUSE_INTR 23 +#define DDRPHY_INTR 22 +#define DDRC_INTR 21 +#define DMAS0_INTR 20 +//#define CSUDMA_INTR 19 tie 0 +#define CRG_INTR 18 +#define APSM1_FULL7_INTR 17 +#define APSM1_FULL6_INTR 16 +#define APSM1_FULL5_INTR 15 +#define APSM1_FULL4_INTR 14 +#define APSM1_FULL3_INTR 13 +#define APSM1_FULL2_INTR 12 +#define APSM1_FULL1_INTR 11 +#define APSM1_FULL0_INTR 10 +#define APSM1_EMPTY7_INTR 9 +#define APSM1_EMPTY6_INTR 8 +#define APSM1_EMPTY5_INTR 7 +#define APSM1_EMPTY4_INTR 6 +#define APSM1_EMPTY3_INTR 5 +#define APSM1_EMPTY2_INTR 4 +#define APSM1_EMPTY1_INTR 3 +#define APSM1_EMPTY0_INTR 2 +#define A72NEXTERR_INTR 1 +#define A72NINTERR_INTR 0 + +extern void wno_unused_myheadername(void); + +#endif /* End of __IO_UCP_H */ diff --git a/driver/rfic/ucp/base/inc/ucp_pma.h b/driver/rfic/ucp/base/inc/ucp_pma.h new file mode 100644 index 0000000..e856591 --- /dev/null +++ b/driver/rfic/ucp/base/inc/ucp_pma.h @@ -0,0 +1,2797 @@ +/********************************************************************* + * + * Filename: ucp_pma.h + * + * Created: 2021-11-06 03:30:30 PM + * Last Modified: 2022-01-22 02:50:47 PM + * Author: LiPin , lip2014@ia.ac.cn + * Organization: Beijing Smart Logic Technology Co., Ltd. + * + * Description: + * + * + ********************************************************************/ + +#ifndef __PMA__ +#define __PMA__ + +//The PMA Config Base Addr +#define JS_PMA0_CFG 0x05f74000 +#define JECS_PMA1_CFG 0x08484000 +#define PET_PMA3_CFG 0x09204000 + +//------------------------JS0 SUBSYSTEM -------------------------// +//The PMA Lane Config Base Addr +#define JS_PMA0_LANE0_BASE JS_PMA0_CFG + 0x10000*4 +#define JS_PMA0_LANE1_BASE JS_PMA0_CFG + 0x10800*4 +#define JS_PMA0_LANE2_BASE JS_PMA0_CFG + 0x11000*4 +#define JS_PMA0_LANE3_BASE JS_PMA0_CFG + 0x11800*4 +#define JS_PMA0_BROADCAST_BASE JS_PMA0_CFG + 0x12000*4 +//The PMA COMMON Base Addr +#define JS_PMA0_COMMON_BASE JS_PMA0_CFG + 0x14000*4 + +//The PMA PCS Addr +#define JS_PMA0_PCS_BASE JS_PMA0_CFG + 0x18000*4 + +//The PMA Lane Config Register +#define JS_PMA0_LANE0_PMA_LOOPBACK_CTRL (JS_PMA0_LANE0_BASE + 4*0x00) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_REQ (JS_PMA0_LANE0_BASE + 4*0x01) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_REQ_ACK (JS_PMA0_LANE0_BASE + 4*0x02) //Attributes : RO +#define JS_PMA0_LANE0_RECEIVER_REQ_PARAM2 (JS_PMA0_LANE0_BASE + 4*0x03) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_REQ_PARAM3 (JS_PMA0_LANE0_BASE + 4*0x04) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_REQ_PARAM4 (JS_PMA0_LANE0_BASE + 4*0x05) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_REQ_PARAM5 (JS_PMA0_LANE0_BASE + 4*0x06) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_REQ_PARAM6 (JS_PMA0_LANE0_BASE + 4*0x07) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_REQ_PARAM7 (JS_PMA0_LANE0_BASE + 4*0x08) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_REQ_PARAM8 (JS_PMA0_LANE0_BASE + 4*0x09) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_REQ_PARAM9 (JS_PMA0_LANE0_BASE + 4*0x0A) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_REQ_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x0B) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_ADAPT_REQ (JS_PMA0_LANE0_BASE + 4*0x10) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_ADAPT_REQ_ACK (JS_PMA0_LANE0_BASE + 4*0x11) //Attributes : RO +#define JS_PMA0_LANE0_RECEIVER_ADAPT_DIR (JS_PMA0_LANE0_BASE + 4*0x12) //Attributes : RO +#define JS_PMA0_LANE0_RECEIVER_ADAPT_SETTING (JS_PMA0_LANE0_BASE + 4*0x13) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_ADAPT_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x14) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_DATAPATH_EN (JS_PMA0_LANE0_BASE + 4*0x20) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_DATAPATH_SETTING1 (JS_PMA0_LANE0_BASE + 4*0x21) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_DATAPATH_SETTING2 (JS_PMA0_LANE0_BASE + 4*0x22) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_DATAPATH_SETTING3 (JS_PMA0_LANE0_BASE + 4*0x23) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_DATAPATH_STATUS1 (JS_PMA0_LANE0_BASE + 4*0x24) //Attributes : RO +#define JS_PMA0_LANE0_RECEIVER_DATAPATH_STATUS2 (JS_PMA0_LANE0_BASE + 4*0x25) //Attributes : RO +#define JS_PMA0_LANE0_RECEIVER_DATAPATH_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x26) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_RESET (JS_PMA0_LANE0_BASE + 4*0x30) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_CONTROL (JS_PMA0_LANE0_BASE + 4*0x31) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_CONTROL_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x32) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_RECAL_CTRL (JS_PMA0_LANE0_BASE + 4*0x40) //Attributes : RW +#define JS_PMA0_LANE0_RECEIVER_RECAL_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x41) //Attributes : RW +#define JS_PMA0_LANE0_TRANSMITTER_REQ (JS_PMA0_LANE0_BASE + 4*0x50) //Attributes : RW +#define JS_PMA0_LANE0_TRANSMITTER_REQ_ACK (JS_PMA0_LANE0_BASE + 4*0x51) //Attributes : RO +#define JS_PMA0_LANE0_TRANSMITTER_REQ_PARAM1 (JS_PMA0_LANE0_BASE + 4*0x52) //Attributes : RW +#define JS_PMA0_LANE0_TRANSMITTER_REQ_PARAM2 (JS_PMA0_LANE0_BASE + 4*0x53) //Attributes : RW +#define JS_PMA0_LANE0_TRANSMITTER_REQ_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x55) //Attributes : RW +#define JS_PMA0_LANE0_TRANSMITTER_DATAPATH_EN (JS_PMA0_LANE0_BASE + 4*0x60) //Attributes : RW +#define JS_PMA0_LANE0_TRANSMITTER_DATAPATH_CLKRDY (JS_PMA0_LANE0_BASE + 4*0x61) //Attributes : RW +#define JS_PMA0_LANE0_TRANSMITTER_DATAPATH_SETTING (JS_PMA0_LANE0_BASE + 4*0x62) //Attributes : RW +#define JS_PMA0_LANE0_TRANSMITTER_DATAPATH_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x63) //Attributes : RW +#define JS_PMA0_LANE0_TRANSMITTER_CONTROL1 (JS_PMA0_LANE0_BASE + 4*0x70) //Attributes : RW +#define JS_PMA0_LANE0_TRANSMITTER_CONTROL2 (JS_PMA0_LANE0_BASE + 4*0x71) //Attributes : RW +#define JS_PMA0_LANE0_TRANSMITTER_CONTROL_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x72) //Attributes : RW +#define JS_PMA0_LANE0_TRANSMITTER_EQ1 (JS_PMA0_LANE0_BASE + 4*0x80) //Attributes : RW +#define JS_PMA0_LANE0_TRANSMITTER_EQ2 (JS_PMA0_LANE0_BASE + 4*0x81) //Attributes : RW +#define JS_PMA0_LANE0_TRANSMITTER_EQ3 (JS_PMA0_LANE0_BASE + 4*0x82) //Attributes : RW +#define JS_PMA0_LANE0_TRANSMITTER_EQ_MUX_CTRL (JS_PMA0_LANE0_BASE + 4*0x83) //Attributes : RW +#define JS_PMA0_LANE0_CONTEXT_RESTORE_CTRL1 (JS_PMA0_LANE0_BASE + 4*0x90) //Attributes : RW +#define JS_PMA0_LANE0_CONTEXT_RESTORE_CTRL2 (JS_PMA0_LANE0_BASE + 4*0x91) //Attributes : RW +#define JS_PMA0_LANE0_CONTEXT_RESTORE_CTRL3 (JS_PMA0_LANE0_BASE + 4*0x92) //Attributes : RW +#define JS_PMA0_LANE0_CONTEXT_RESTORE_CTRL4 (JS_PMA0_LANE0_BASE + 4*0x93) //Attributes : RW +#define JS_PMA0_LANE0_CONTEXT_RESTORE_MUX (JS_PMA0_LANE0_BASE + 4*0x94) //Attributes : RW +#define JS_PMA0_LANE0_LANE_REFCLK_SEL (JS_PMA0_LANE0_BASE + 4*0xA0) //Attributes : RW +#define JS_PMA0_LANE0_ETH_CLK_CTRL (JS_PMA0_LANE0_BASE + 4*0xB0) //Attributes : RW +#define JS_PMA0_LANE0_ETH_CLK_CTRL_MUX (JS_PMA0_LANE0_BASE + 4*0xB1) //Attributes : RW +#define JS_PMA0_LANE0_RX_ADAPT_CTRL (JS_PMA0_LANE0_BASE + 4*0xC0) //Attributes : RW +#define JS_PMA0_LANE0_RX_DCC_CTRL (JS_PMA0_LANE0_BASE + 4*0xC1) //Attributes : RW +#define JS_PMA0_LANE0_RX_EQ_CTRL1 (JS_PMA0_LANE0_BASE + 4*0xC2) //Attributes : RW +#define JS_PMA0_LANE0_RX_EQ_CTRL2 (JS_PMA0_LANE0_BASE + 4*0xC3) //Attributes : RW +#define JS_PMA0_LANE0_RX_MARGIN_CTRL (JS_PMA0_LANE0_BASE + 4*0xC4) //Attributes : RW +#define JS_PMA0_LANE0_RX_MARGIN_ERROR (JS_PMA0_LANE0_BASE + 4*0xC5) //Attributes : RO +#define JS_PMA0_LANE0_RECV_REQUEST_CTRL_MUX (JS_PMA0_LANE0_BASE + 4*0xC6) //Attributes : RW +#define JS_PMA0_LANE0_RX_COARSE_ADAPT_CTRL (JS_PMA0_LANE0_BASE + 4*0xC8) //Attributes : RW +#define JS_PMA0_LANE0_RX_COARSE_ADAPT_CTRL_MUX (JS_PMA0_LANE0_BASE + 4*0xC9) //Attributes : RW +#define JS_PMA0_LANE0_RX_DIV_CLK_CTRL (JS_PMA0_LANE0_BASE + 4*0xCA) //Attributes : RW +#define JS_PMA0_LANE0_TX_DIV_CLK_CTRL (JS_PMA0_LANE0_BASE + 4*0xCB) //Attributes : RW +#define JS_PMA0_LANE0_MULTI_CLK_CTRL_MUX (JS_PMA0_LANE0_BASE + 4*0xCC) //Attributes : RW +#define JS_PMA0_LANE0_TRANS_REQ_CTRL1 (JS_PMA0_LANE0_BASE + 4*0xD0) //Attributes : RW +#define JS_PMA0_LANE0_TRANS_REQ_CTRL2 (JS_PMA0_LANE0_BASE + 4*0xD1) //Attributes : RW +#define JS_PMA0_LANE0_TRANS_REQ_CTRL3 (JS_PMA0_LANE0_BASE + 4*0xD2) //Attributes : RW +#define JS_PMA0_LANE0_TRANS_REQ_CTRL4 (JS_PMA0_LANE0_BASE + 4*0xD3) //Attributes : RW +#define JS_PMA0_LANE0_TRANS_REQ_CTRL5 (JS_PMA0_LANE0_BASE + 4*0xD4) //Attributes : RW +#define JS_PMA0_LANE0_TRANS_REQ_MUX (JS_PMA0_LANE0_BASE + 4*0xD5) //Attributes : RW +#define JS_PMA0_LANE0_TRANS_INTERFACE_CTRL (JS_PMA0_LANE0_BASE + 4*0xD6) //Attributes : RW +#define JS_PMA0_LANE0_TRANS_INTERFACE_MUX (JS_PMA0_LANE0_BASE + 4*0xD7) //Attributes : RW +#define JS_PMA0_LANE0_TRANS_MASTER_PLL_STATE (JS_PMA0_LANE0_BASE + 4*0xD8) //Attributes : RW +#define JS_PMA0_LANE0_TRANS_PLL_STATE (JS_PMA0_LANE0_BASE + 4*0xD9) //Attributes : RO +#define JS_PMA0_LANE0_PLL_STATE_MUX (JS_PMA0_LANE0_BASE + 4*0xDA) //Attributes : RW +#define JS_PMA0_LANE0_RX_VALID_PHY (JS_PMA0_LANE0_BASE + 4*0xDF) //Attributes : RO +#define JS_PMA0_LANE0_RX_VALID_MUX (JS_PMA0_LANE0_BASE + 4*0xE0) //Attributes : RW +#define JS_PMA0_LANE0_RX_SRIO_SIGDET_MUX (JS_PMA0_LANE0_BASE + 4*0xE1) //Attributes : RW +#define JS_PMA0_LANE0_SRIO_DEGRADED (JS_PMA0_LANE0_BASE + 4*0xE2) //Attributes : RW +#define JS_PMA0_LANE0_SRIO_RETRAIN (JS_PMA0_LANE0_BASE + 4*0xE3) //Attributes : RW +#define JS_PMA0_LANE0_SRIO_SHORT_RUN (JS_PMA0_LANE0_BASE + 4*0xE4) //Attributes : RW +#define JS_PMA0_LANE0_EQ_INIT_C0 (JS_PMA0_LANE0_BASE + 4*0xE5) //Attributes : RW +#define JS_PMA0_LANE0_EQ_INIT_CN1 (JS_PMA0_LANE0_BASE + 4*0xE6) //Attributes : RW +#define JS_PMA0_LANE0_EQ_INIT_CP1 (JS_PMA0_LANE0_BASE + 4*0xE7) //Attributes : RW +#define JS_PMA0_LANE0_EQ_RULE_CTRL_1 (JS_PMA0_LANE0_BASE + 4*0xE8) //Attributes : RW +#define JS_PMA0_LANE0_EQ_RULE_CTRL_2 (JS_PMA0_LANE0_BASE + 4*0xE9) //Attributes : RW +#define JS_PMA0_LANE0_EQ_RULE_CTRL_3 (JS_PMA0_LANE0_BASE + 4*0xEA) //Attributes : RW +#define JS_PMA0_LANE0_EQ_RULE_CTRL_4 (JS_PMA0_LANE0_BASE + 4*0xEB) //Attributes : RW +#define JS_PMA0_LANE0_EQ_ALGORITHM_CTRL (JS_PMA0_LANE0_BASE + 4*0xEC) //Attributes : RW +#define JS_PMA0_LANE0_EQ_TX_TRAIN_CTRL (JS_PMA0_LANE0_BASE + 4*0xED) //Attributes : RW +#define JS_PMA0_LANE0_EQ_ADJ_INTERVAL (JS_PMA0_LANE0_BASE + 4*0xEE) //Attributes : RW +#define JS_PMA0_LANE0_EQ_RX_REQ_CTRL (JS_PMA0_LANE0_BASE + 4*0xEF) //Attributes : RW +#define JS_PMA0_LANE0_EQ_RX_TRAIN_CTRL (JS_PMA0_LANE0_BASE + 4*0xF0) //Attributes : RW +#define JS_PMA0_LANE0_EQ_RX_RESET_CYCLE (JS_PMA0_LANE0_BASE + 4*0xF1) //Attributes : RW +#define JS_PMA0_LANE0_RPCS_KTR_STATUS (JS_PMA0_LANE0_BASE + 4*0xF2) //Attributes : RO +#define JS_PMA0_LANE0_EQ_FSM (JS_PMA0_LANE0_BASE + 4*0xF3) //Attributes : RO +#define JS_PMA0_LANE0_ETH_RX_LOS (JS_PMA0_LANE0_BASE + 4*0xF4) //Attributes : RW +#define JS_PMA0_LANE0_EQ_PRESET_C0 (JS_PMA0_LANE0_BASE + 4*0xF5) //Attributes : RW +#define JS_PMA0_LANE0_EQ_PRESET_CN1 (JS_PMA0_LANE0_BASE + 4*0xF6) //Attributes : RW +#define JS_PMA0_LANE0_EQ_PRESET_CP1 (JS_PMA0_LANE0_BASE + 4*0xF7) //Attributes : RW +#define JS_PMA0_LANE0_EQ_SUCC_MASK (JS_PMA0_LANE0_BASE + 4*0xF8) //Attributes : RW +#define JS_PMA0_LANE0_PMA_COM_SCRATCH (JS_PMA0_LANE0_BASE + 4*0xff) //Attributes : RW +#define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY0 (JS_PMA0_LANE0_BASE + 4*0x100) //Attributes : RO_EXT_L +#define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY1 (JS_PMA0_LANE0_BASE + 4*0x101) //Attributes : RO_EXT +#define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY2 (JS_PMA0_LANE0_BASE + 4*0x102) //Attributes : RO_EXT +#define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY3 (JS_PMA0_LANE0_BASE + 4*0x103) //Attributes : RO_EXT +#define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY4 (JS_PMA0_LANE0_BASE + 4*0x104) //Attributes : RO_EXT +#define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY5 (JS_PMA0_LANE0_BASE + 4*0x105) //Attributes : RO_EXT +#define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY6 (JS_PMA0_LANE0_BASE + 4*0x106) //Attributes : RO_EXT +#define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY7 (JS_PMA0_LANE0_BASE + 4*0x107) //Attributes : RO_EXT_H +#define JS_PMA0_LANE0_EQ_TX_FSM_HISTORY_CTRL (JS_PMA0_LANE0_BASE + 4*0x108) //Attributes : RW +#define JS_PMA0_LANE0_EQ_RX_FSM_HISTORY0 (JS_PMA0_LANE0_BASE + 4*0x109) //Attributes : RO_EXT_L +#define JS_PMA0_LANE0_EQ_RX_FSM_HISTORY1 (JS_PMA0_LANE0_BASE + 4*0x10A) //Attributes : RO_EXT +#define JS_PMA0_LANE0_EQ_RX_FSM_HISTORY2 (JS_PMA0_LANE0_BASE + 4*0x10B) //Attributes : RO_EXT +#define JS_PMA0_LANE0_EQ_RX_FSM_HISTORY3 (JS_PMA0_LANE0_BASE + 4*0x10C) //Attributes : RO_EXT_H +#define JS_PMA0_LANE0_EQ_RX_FSM_HISTORY_CTRL (JS_PMA0_LANE0_BASE + 4*0x10D) //Attributes : RW +#define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY0 (JS_PMA0_LANE0_BASE + 4*0x110) //Attributes : RO_EXT_L +#define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY1 (JS_PMA0_LANE0_BASE + 4*0x111) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY2 (JS_PMA0_LANE0_BASE + 4*0x112) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY3 (JS_PMA0_LANE0_BASE + 4*0x113) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY4 (JS_PMA0_LANE0_BASE + 4*0x114) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY5 (JS_PMA0_LANE0_BASE + 4*0x115) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY6 (JS_PMA0_LANE0_BASE + 4*0x116) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY7 (JS_PMA0_LANE0_BASE + 4*0x117) //Attributes : RO_EXT_H +#define JS_PMA0_LANE0_TX_EQ_MAIN_HISTORY_CTRL (JS_PMA0_LANE0_BASE + 4*0x118) //Attributes : RW +#define JS_PMA0_LANE0_RX_TXMAIN_DIR_HISTORY0 (JS_PMA0_LANE0_BASE + 4*0x119) //Attributes : RO_EXT_L +#define JS_PMA0_LANE0_RX_TXMAIN_DIR_HISTORY1 (JS_PMA0_LANE0_BASE + 4*0x11A) //Attributes : RO_EXT +#define JS_PMA0_LANE0_RX_TXMAIN_DIR_HISTORY2 (JS_PMA0_LANE0_BASE + 4*0x11B) //Attributes : RO_EXT +#define JS_PMA0_LANE0_RX_TXMAIN_DIR_HISTORY3 (JS_PMA0_LANE0_BASE + 4*0x11C) //Attributes : RO_EXT_H +#define JS_PMA0_LANE0_RX_TXMAIN_DIR_HISTORY_CTRL (JS_PMA0_LANE0_BASE + 4*0x11D) //Attributes : RW +#define JS_PMA0_LANE0_TX_EQ_POST_HISTORY0 (JS_PMA0_LANE0_BASE + 4*0x120) //Attributes : RO_EXT_L +#define JS_PMA0_LANE0_TX_EQ_POST_HISTORY1 (JS_PMA0_LANE0_BASE + 4*0x121) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_POST_HISTORY2 (JS_PMA0_LANE0_BASE + 4*0x122) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_POST_HISTORY3 (JS_PMA0_LANE0_BASE + 4*0x123) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_POST_HISTORY4 (JS_PMA0_LANE0_BASE + 4*0x124) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_POST_HISTORY5 (JS_PMA0_LANE0_BASE + 4*0x125) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_POST_HISTORY6 (JS_PMA0_LANE0_BASE + 4*0x126) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_POST_HISTORY7 (JS_PMA0_LANE0_BASE + 4*0x127) //Attributes : RO_EXT_H +#define JS_PMA0_LANE0_TX_EQ_POST_HISTORY_CTRL (JS_PMA0_LANE0_BASE + 4*0x128) //Attributes : RW +#define JS_PMA0_LANE0_RX_TXPOST_DIR_HISTORY0 (JS_PMA0_LANE0_BASE + 4*0x129) //Attributes : RO_EXT_L +#define JS_PMA0_LANE0_RX_TXPOST_DIR_HISTORY1 (JS_PMA0_LANE0_BASE + 4*0x12A) //Attributes : RO_EXT +#define JS_PMA0_LANE0_RX_TXPOST_DIR_HISTORY2 (JS_PMA0_LANE0_BASE + 4*0x12B) //Attributes : RO_EXT +#define JS_PMA0_LANE0_RX_TXPOST_DIR_HISTORY3 (JS_PMA0_LANE0_BASE + 4*0x12C) //Attributes : RO_EXT_H +#define JS_PMA0_LANE0_RX_TXPOST_DIR_HISTORY_CTRL (JS_PMA0_LANE0_BASE + 4*0x12D) //Attributes : RW +#define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY0 (JS_PMA0_LANE0_BASE + 4*0x130) //Attributes : RO_EXT_L +#define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY1 (JS_PMA0_LANE0_BASE + 4*0x131) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY2 (JS_PMA0_LANE0_BASE + 4*0x132) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY3 (JS_PMA0_LANE0_BASE + 4*0x133) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY4 (JS_PMA0_LANE0_BASE + 4*0x134) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY5 (JS_PMA0_LANE0_BASE + 4*0x135) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY6 (JS_PMA0_LANE0_BASE + 4*0x136) //Attributes : RO_EXT +#define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY7 (JS_PMA0_LANE0_BASE + 4*0x137) //Attributes : RO_EXT_H +#define JS_PMA0_LANE0_TX_EQ_PRE_HISTORY_CTRL (JS_PMA0_LANE0_BASE + 4*0x138) //Attributes : RW +#define JS_PMA0_LANE0_RX_TXPRE_DIR_HISTORY0 (JS_PMA0_LANE0_BASE + 4*0x139) //Attributes : RO_EXT_L +#define JS_PMA0_LANE0_RX_TXPRE_DIR_HISTORY1 (JS_PMA0_LANE0_BASE + 4*0x13A) //Attributes : RO_EXT +#define JS_PMA0_LANE0_RX_TXPRE_DIR_HISTORY2 (JS_PMA0_LANE0_BASE + 4*0x13B) //Attributes : RO_EXT +#define JS_PMA0_LANE0_RX_TXPRE_DIR_HISTORY3 (JS_PMA0_LANE0_BASE + 4*0x13C) //Attributes : RO_EXT_H +#define JS_PMA0_LANE0_RX_TXPRE_DIR_HISTORY_CTRL (JS_PMA0_LANE0_BASE + 4*0x13D) //Attributes : RW + +#define JS_PMA0_LANE1_PMA_LOOPBACK_CTRL (JS_PMA0_LANE1_BASE + 4*0x00) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_REQ (JS_PMA0_LANE1_BASE + 4*0x01) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_REQ_ACK (JS_PMA0_LANE1_BASE + 4*0x02) //Attributes : RO +#define JS_PMA0_LANE1_RECEIVER_REQ_PARAM2 (JS_PMA0_LANE1_BASE + 4*0x03) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_REQ_PARAM3 (JS_PMA0_LANE1_BASE + 4*0x04) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_REQ_PARAM4 (JS_PMA0_LANE1_BASE + 4*0x05) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_REQ_PARAM5 (JS_PMA0_LANE1_BASE + 4*0x06) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_REQ_PARAM6 (JS_PMA0_LANE1_BASE + 4*0x07) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_REQ_PARAM7 (JS_PMA0_LANE1_BASE + 4*0x08) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_REQ_PARAM8 (JS_PMA0_LANE1_BASE + 4*0x09) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_REQ_PARAM9 (JS_PMA0_LANE1_BASE + 4*0x0A) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_REQ_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x0B) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_ADAPT_REQ (JS_PMA0_LANE1_BASE + 4*0x10) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_ADAPT_REQ_ACK (JS_PMA0_LANE1_BASE + 4*0x11) //Attributes : RO +#define JS_PMA0_LANE1_RECEIVER_ADAPT_DIR (JS_PMA0_LANE1_BASE + 4*0x12) //Attributes : RO +#define JS_PMA0_LANE1_RECEIVER_ADAPT_SETTING (JS_PMA0_LANE1_BASE + 4*0x13) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_ADAPT_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x14) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_DATAPATH_EN (JS_PMA0_LANE1_BASE + 4*0x20) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_DATAPATH_SETTING1 (JS_PMA0_LANE1_BASE + 4*0x21) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_DATAPATH_SETTING2 (JS_PMA0_LANE1_BASE + 4*0x22) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_DATAPATH_SETTING3 (JS_PMA0_LANE1_BASE + 4*0x23) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_DATAPATH_STATUS1 (JS_PMA0_LANE1_BASE + 4*0x24) //Attributes : RO +#define JS_PMA0_LANE1_RECEIVER_DATAPATH_STATUS2 (JS_PMA0_LANE1_BASE + 4*0x25) //Attributes : RO +#define JS_PMA0_LANE1_RECEIVER_DATAPATH_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x26) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_RESET (JS_PMA0_LANE1_BASE + 4*0x30) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_CONTROL (JS_PMA0_LANE1_BASE + 4*0x31) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_CONTROL_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x32) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_RECAL_CTRL (JS_PMA0_LANE1_BASE + 4*0x40) //Attributes : RW +#define JS_PMA0_LANE1_RECEIVER_RECAL_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x41) //Attributes : RW +#define JS_PMA0_LANE1_TRANSMITTER_REQ (JS_PMA0_LANE1_BASE + 4*0x50) //Attributes : RW +#define JS_PMA0_LANE1_TRANSMITTER_REQ_ACK (JS_PMA0_LANE1_BASE + 4*0x51) //Attributes : RO +#define JS_PMA0_LANE1_TRANSMITTER_REQ_PARAM1 (JS_PMA0_LANE1_BASE + 4*0x52) //Attributes : RW +#define JS_PMA0_LANE1_TRANSMITTER_REQ_PARAM2 (JS_PMA0_LANE1_BASE + 4*0x53) //Attributes : RW +#define JS_PMA0_LANE1_TRANSMITTER_REQ_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x55) //Attributes : RW +#define JS_PMA0_LANE1_TRANSMITTER_DATAPATH_EN (JS_PMA0_LANE1_BASE + 4*0x60) //Attributes : RW +#define JS_PMA0_LANE1_TRANSMITTER_DATAPATH_CLKRDY (JS_PMA0_LANE1_BASE + 4*0x61) //Attributes : RW +#define JS_PMA0_LANE1_TRANSMITTER_DATAPATH_SETTING (JS_PMA0_LANE1_BASE + 4*0x62) //Attributes : RW +#define JS_PMA0_LANE1_TRANSMITTER_DATAPATH_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x63) //Attributes : RW +#define JS_PMA0_LANE1_TRANSMITTER_CONTROL1 (JS_PMA0_LANE1_BASE + 4*0x70) //Attributes : RW +#define JS_PMA0_LANE1_TRANSMITTER_CONTROL2 (JS_PMA0_LANE1_BASE + 4*0x71) //Attributes : RW +#define JS_PMA0_LANE1_TRANSMITTER_CONTROL_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x72) //Attributes : RW +#define JS_PMA0_LANE1_TRANSMITTER_EQ1 (JS_PMA0_LANE1_BASE + 4*0x80) //Attributes : RW +#define JS_PMA0_LANE1_TRANSMITTER_EQ2 (JS_PMA0_LANE1_BASE + 4*0x81) //Attributes : RW +#define JS_PMA0_LANE1_TRANSMITTER_EQ3 (JS_PMA0_LANE1_BASE + 4*0x82) //Attributes : RW +#define JS_PMA0_LANE1_TRANSMITTER_EQ_MUX_CTRL (JS_PMA0_LANE1_BASE + 4*0x83) //Attributes : RW +#define JS_PMA0_LANE1_CONTEXT_RESTORE_CTRL1 (JS_PMA0_LANE1_BASE + 4*0x90) //Attributes : RW +#define JS_PMA0_LANE1_CONTEXT_RESTORE_CTRL2 (JS_PMA0_LANE1_BASE + 4*0x91) //Attributes : RW +#define JS_PMA0_LANE1_CONTEXT_RESTORE_CTRL3 (JS_PMA0_LANE1_BASE + 4*0x92) //Attributes : RW +#define JS_PMA0_LANE1_CONTEXT_RESTORE_CTRL4 (JS_PMA0_LANE1_BASE + 4*0x93) //Attributes : RW +#define JS_PMA0_LANE1_CONTEXT_RESTORE_MUX (JS_PMA0_LANE1_BASE + 4*0x94) //Attributes : RW +#define JS_PMA0_LANE1_LANE_REFCLK_SEL (JS_PMA0_LANE1_BASE + 4*0xA0) //Attributes : RW +#define JS_PMA0_LANE1_ETH_CLK_CTRL (JS_PMA0_LANE1_BASE + 4*0xB0) //Attributes : RW +#define JS_PMA0_LANE1_ETH_CLK_CTRL_MUX (JS_PMA0_LANE1_BASE + 4*0xB1) //Attributes : RW +#define JS_PMA0_LANE1_RX_ADAPT_CTRL (JS_PMA0_LANE1_BASE + 4*0xC0) //Attributes : RW +#define JS_PMA0_LANE1_RX_DCC_CTRL (JS_PMA0_LANE1_BASE + 4*0xC1) //Attributes : RW +#define JS_PMA0_LANE1_RX_EQ_CTRL1 (JS_PMA0_LANE1_BASE + 4*0xC2) //Attributes : RW +#define JS_PMA0_LANE1_RX_EQ_CTRL2 (JS_PMA0_LANE1_BASE + 4*0xC3) //Attributes : RW +#define JS_PMA0_LANE1_RX_MARGIN_CTRL (JS_PMA0_LANE1_BASE + 4*0xC4) //Attributes : RW +#define JS_PMA0_LANE1_RX_MARGIN_ERROR (JS_PMA0_LANE1_BASE + 4*0xC5) //Attributes : RO +#define JS_PMA0_LANE1_RECV_REQUEST_CTRL_MUX (JS_PMA0_LANE1_BASE + 4*0xC6) //Attributes : RW +#define JS_PMA0_LANE1_RX_COARSE_ADAPT_CTRL (JS_PMA0_LANE1_BASE + 4*0xC8) //Attributes : RW +#define JS_PMA0_LANE1_RX_COARSE_ADAPT_CTRL_MUX (JS_PMA0_LANE1_BASE + 4*0xC9) //Attributes : RW +#define JS_PMA0_LANE1_RX_DIV_CLK_CTRL (JS_PMA0_LANE1_BASE + 4*0xCA) //Attributes : RW +#define JS_PMA0_LANE1_TX_DIV_CLK_CTRL (JS_PMA0_LANE1_BASE + 4*0xCB) //Attributes : RW +#define JS_PMA0_LANE1_MULTI_CLK_CTRL_MUX (JS_PMA0_LANE1_BASE + 4*0xCC) //Attributes : RW +#define JS_PMA0_LANE1_TRANS_REQ_CTRL1 (JS_PMA0_LANE1_BASE + 4*0xD0) //Attributes : RW +#define JS_PMA0_LANE1_TRANS_REQ_CTRL2 (JS_PMA0_LANE1_BASE + 4*0xD1) //Attributes : RW +#define JS_PMA0_LANE1_TRANS_REQ_CTRL3 (JS_PMA0_LANE1_BASE + 4*0xD2) //Attributes : RW +#define JS_PMA0_LANE1_TRANS_REQ_CTRL4 (JS_PMA0_LANE1_BASE + 4*0xD3) //Attributes : RW +#define JS_PMA0_LANE1_TRANS_REQ_CTRL5 (JS_PMA0_LANE1_BASE + 4*0xD4) //Attributes : RW +#define JS_PMA0_LANE1_TRANS_REQ_MUX (JS_PMA0_LANE1_BASE + 4*0xD5) //Attributes : RW +#define JS_PMA0_LANE1_TRANS_INTERFACE_CTRL (JS_PMA0_LANE1_BASE + 4*0xD6) //Attributes : RW +#define JS_PMA0_LANE1_TRANS_INTERFACE_MUX (JS_PMA0_LANE1_BASE + 4*0xD7) //Attributes : RW +#define JS_PMA0_LANE1_TRANS_MASTER_PLL_STATE (JS_PMA0_LANE1_BASE + 4*0xD8) //Attributes : RW +#define JS_PMA0_LANE1_TRANS_PLL_STATE (JS_PMA0_LANE1_BASE + 4*0xD9) //Attributes : RO +#define JS_PMA0_LANE1_PLL_STATE_MUX (JS_PMA0_LANE1_BASE + 4*0xDA) //Attributes : RW +#define JS_PMA0_LANE1_RX_VALID_PHY (JS_PMA0_LANE1_BASE + 4*0xDF) //Attributes : RO +#define JS_PMA0_LANE1_RX_VALID_MUX (JS_PMA0_LANE1_BASE + 4*0xE0) //Attributes : RW +#define JS_PMA0_LANE1_RX_SRIO_SIGDET_MUX (JS_PMA0_LANE1_BASE + 4*0xE1) //Attributes : RW +#define JS_PMA0_LANE1_SRIO_DEGRADED (JS_PMA0_LANE1_BASE + 4*0xE2) //Attributes : RW +#define JS_PMA0_LANE1_SRIO_RETRAIN (JS_PMA0_LANE1_BASE + 4*0xE3) //Attributes : RW +#define JS_PMA0_LANE1_SRIO_SHORT_RUN (JS_PMA0_LANE1_BASE + 4*0xE4) //Attributes : RW +#define JS_PMA0_LANE1_EQ_INIT_C0 (JS_PMA0_LANE1_BASE + 4*0xE5) //Attributes : RW +#define JS_PMA0_LANE1_EQ_INIT_CN1 (JS_PMA0_LANE1_BASE + 4*0xE6) //Attributes : RW +#define JS_PMA0_LANE1_EQ_INIT_CP1 (JS_PMA0_LANE1_BASE + 4*0xE7) //Attributes : RW +#define JS_PMA0_LANE1_EQ_RULE_CTRL_1 (JS_PMA0_LANE1_BASE + 4*0xE8) //Attributes : RW +#define JS_PMA0_LANE1_EQ_RULE_CTRL_2 (JS_PMA0_LANE1_BASE + 4*0xE9) //Attributes : RW +#define JS_PMA0_LANE1_EQ_RULE_CTRL_3 (JS_PMA0_LANE1_BASE + 4*0xEA) //Attributes : RW +#define JS_PMA0_LANE1_EQ_RULE_CTRL_4 (JS_PMA0_LANE1_BASE + 4*0xEB) //Attributes : RW +#define JS_PMA0_LANE1_EQ_ALGORITHM_CTRL (JS_PMA0_LANE1_BASE + 4*0xEC) //Attributes : RW +#define JS_PMA0_LANE1_EQ_TX_TRAIN_CTRL (JS_PMA0_LANE1_BASE + 4*0xED) //Attributes : RW +#define JS_PMA0_LANE1_EQ_ADJ_INTERVAL (JS_PMA0_LANE1_BASE + 4*0xEE) //Attributes : RW +#define JS_PMA0_LANE1_EQ_RX_REQ_CTRL (JS_PMA0_LANE1_BASE + 4*0xEF) //Attributes : RW +#define JS_PMA0_LANE1_EQ_RX_TRAIN_CTRL (JS_PMA0_LANE1_BASE + 4*0xF0) //Attributes : RW +#define JS_PMA0_LANE1_EQ_RX_RESET_CYCLE (JS_PMA0_LANE1_BASE + 4*0xF1) //Attributes : RW +#define JS_PMA0_LANE1_RPCS_KTR_STATUS (JS_PMA0_LANE1_BASE + 4*0xF2) //Attributes : RO +#define JS_PMA0_LANE1_EQ_FSM (JS_PMA0_LANE1_BASE + 4*0xF3) //Attributes : RO +#define JS_PMA0_LANE1_ETH_RX_LOS (JS_PMA0_LANE1_BASE + 4*0xF4) //Attributes : RW +#define JS_PMA0_LANE1_EQ_PRESET_C0 (JS_PMA0_LANE1_BASE + 4*0xF5) //Attributes : RW +#define JS_PMA0_LANE1_EQ_PRESET_CN1 (JS_PMA0_LANE1_BASE + 4*0xF6) //Attributes : RW +#define JS_PMA0_LANE1_EQ_PRESET_CP1 (JS_PMA0_LANE1_BASE + 4*0xF7) //Attributes : RW +#define JS_PMA0_LANE1_EQ_SUCC_MASK (JS_PMA0_LANE1_BASE + 4*0xF8) //Attributes : RW +#define JS_PMA0_LANE1_PMA_COM_SCRATCH (JS_PMA0_LANE1_BASE + 4*0xff) //Attributes : RW +#define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY0 (JS_PMA0_LANE1_BASE + 4*0x100) //Attributes : RO_EXT_L +#define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY1 (JS_PMA0_LANE1_BASE + 4*0x101) //Attributes : RO_EXT +#define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY2 (JS_PMA0_LANE1_BASE + 4*0x102) //Attributes : RO_EXT +#define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY3 (JS_PMA0_LANE1_BASE + 4*0x103) //Attributes : RO_EXT +#define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY4 (JS_PMA0_LANE1_BASE + 4*0x104) //Attributes : RO_EXT +#define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY5 (JS_PMA0_LANE1_BASE + 4*0x105) //Attributes : RO_EXT +#define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY6 (JS_PMA0_LANE1_BASE + 4*0x106) //Attributes : RO_EXT +#define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY7 (JS_PMA0_LANE1_BASE + 4*0x107) //Attributes : RO_EXT_H +#define JS_PMA0_LANE1_EQ_TX_FSM_HISTORY_CTRL (JS_PMA0_LANE1_BASE + 4*0x108) //Attributes : RW +#define JS_PMA0_LANE1_EQ_RX_FSM_HISTORY0 (JS_PMA0_LANE1_BASE + 4*0x109) //Attributes : RO_EXT_L +#define JS_PMA0_LANE1_EQ_RX_FSM_HISTORY1 (JS_PMA0_LANE1_BASE + 4*0x10A) //Attributes : RO_EXT +#define JS_PMA0_LANE1_EQ_RX_FSM_HISTORY2 (JS_PMA0_LANE1_BASE + 4*0x10B) //Attributes : RO_EXT +#define JS_PMA0_LANE1_EQ_RX_FSM_HISTORY3 (JS_PMA0_LANE1_BASE + 4*0x10C) //Attributes : RO_EXT_H +#define JS_PMA0_LANE1_EQ_RX_FSM_HISTORY_CTRL (JS_PMA0_LANE1_BASE + 4*0x10D) //Attributes : RW +#define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY0 (JS_PMA0_LANE1_BASE + 4*0x110) //Attributes : RO_EXT_L +#define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY1 (JS_PMA0_LANE1_BASE + 4*0x111) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY2 (JS_PMA0_LANE1_BASE + 4*0x112) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY3 (JS_PMA0_LANE1_BASE + 4*0x113) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY4 (JS_PMA0_LANE1_BASE + 4*0x114) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY5 (JS_PMA0_LANE1_BASE + 4*0x115) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY6 (JS_PMA0_LANE1_BASE + 4*0x116) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY7 (JS_PMA0_LANE1_BASE + 4*0x117) //Attributes : RO_EXT_H +#define JS_PMA0_LANE1_TX_EQ_MAIN_HISTORY_CTRL (JS_PMA0_LANE1_BASE + 4*0x118) //Attributes : RW +#define JS_PMA0_LANE1_RX_TXMAIN_DIR_HISTORY0 (JS_PMA0_LANE1_BASE + 4*0x119) //Attributes : RO_EXT_L +#define JS_PMA0_LANE1_RX_TXMAIN_DIR_HISTORY1 (JS_PMA0_LANE1_BASE + 4*0x11A) //Attributes : RO_EXT +#define JS_PMA0_LANE1_RX_TXMAIN_DIR_HISTORY2 (JS_PMA0_LANE1_BASE + 4*0x11B) //Attributes : RO_EXT +#define JS_PMA0_LANE1_RX_TXMAIN_DIR_HISTORY3 (JS_PMA0_LANE1_BASE + 4*0x11C) //Attributes : RO_EXT_H +#define JS_PMA0_LANE1_RX_TXMAIN_DIR_HISTORY_CTRL (JS_PMA0_LANE1_BASE + 4*0x11D) //Attributes : RW +#define JS_PMA0_LANE1_TX_EQ_POST_HISTORY0 (JS_PMA0_LANE1_BASE + 4*0x120) //Attributes : RO_EXT_L +#define JS_PMA0_LANE1_TX_EQ_POST_HISTORY1 (JS_PMA0_LANE1_BASE + 4*0x121) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_POST_HISTORY2 (JS_PMA0_LANE1_BASE + 4*0x122) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_POST_HISTORY3 (JS_PMA0_LANE1_BASE + 4*0x123) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_POST_HISTORY4 (JS_PMA0_LANE1_BASE + 4*0x124) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_POST_HISTORY5 (JS_PMA0_LANE1_BASE + 4*0x125) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_POST_HISTORY6 (JS_PMA0_LANE1_BASE + 4*0x126) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_POST_HISTORY7 (JS_PMA0_LANE1_BASE + 4*0x127) //Attributes : RO_EXT_H +#define JS_PMA0_LANE1_TX_EQ_POST_HISTORY_CTRL (JS_PMA0_LANE1_BASE + 4*0x128) //Attributes : RW +#define JS_PMA0_LANE1_RX_TXPOST_DIR_HISTORY0 (JS_PMA0_LANE1_BASE + 4*0x129) //Attributes : RO_EXT_L +#define JS_PMA0_LANE1_RX_TXPOST_DIR_HISTORY1 (JS_PMA0_LANE1_BASE + 4*0x12A) //Attributes : RO_EXT +#define JS_PMA0_LANE1_RX_TXPOST_DIR_HISTORY2 (JS_PMA0_LANE1_BASE + 4*0x12B) //Attributes : RO_EXT +#define JS_PMA0_LANE1_RX_TXPOST_DIR_HISTORY3 (JS_PMA0_LANE1_BASE + 4*0x12C) //Attributes : RO_EXT_H +#define JS_PMA0_LANE1_RX_TXPOST_DIR_HISTORY_CTRL (JS_PMA0_LANE1_BASE + 4*0x12D) //Attributes : RW +#define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY0 (JS_PMA0_LANE1_BASE + 4*0x130) //Attributes : RO_EXT_L +#define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY1 (JS_PMA0_LANE1_BASE + 4*0x131) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY2 (JS_PMA0_LANE1_BASE + 4*0x132) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY3 (JS_PMA0_LANE1_BASE + 4*0x133) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY4 (JS_PMA0_LANE1_BASE + 4*0x134) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY5 (JS_PMA0_LANE1_BASE + 4*0x135) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY6 (JS_PMA0_LANE1_BASE + 4*0x136) //Attributes : RO_EXT +#define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY7 (JS_PMA0_LANE1_BASE + 4*0x137) //Attributes : RO_EXT_H +#define JS_PMA0_LANE1_TX_EQ_PRE_HISTORY_CTRL (JS_PMA0_LANE1_BASE + 4*0x138) //Attributes : RW +#define JS_PMA0_LANE1_RX_TXPRE_DIR_HISTORY0 (JS_PMA0_LANE1_BASE + 4*0x139) //Attributes : RO_EXT_L +#define JS_PMA0_LANE1_RX_TXPRE_DIR_HISTORY1 (JS_PMA0_LANE1_BASE + 4*0x13A) //Attributes : RO_EXT +#define JS_PMA0_LANE1_RX_TXPRE_DIR_HISTORY2 (JS_PMA0_LANE1_BASE + 4*0x13B) //Attributes : RO_EXT +#define JS_PMA0_LANE1_RX_TXPRE_DIR_HISTORY3 (JS_PMA0_LANE1_BASE + 4*0x13C) //Attributes : RO_EXT_H +#define JS_PMA0_LANE1_RX_TXPRE_DIR_HISTORY_CTRL (JS_PMA0_LANE1_BASE + 4*0x13D) //Attributes : RW + +#define JS_PMA0_LANE2_PMA_LOOPBACK_CTRL (JS_PMA0_LANE2_BASE + 4*0x00) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_REQ (JS_PMA0_LANE2_BASE + 4*0x01) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_REQ_ACK (JS_PMA0_LANE2_BASE + 4*0x02) //Attributes : RO +#define JS_PMA0_LANE2_RECEIVER_REQ_PARAM2 (JS_PMA0_LANE2_BASE + 4*0x03) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_REQ_PARAM3 (JS_PMA0_LANE2_BASE + 4*0x04) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_REQ_PARAM4 (JS_PMA0_LANE2_BASE + 4*0x05) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_REQ_PARAM5 (JS_PMA0_LANE2_BASE + 4*0x06) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_REQ_PARAM6 (JS_PMA0_LANE2_BASE + 4*0x07) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_REQ_PARAM7 (JS_PMA0_LANE2_BASE + 4*0x08) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_REQ_PARAM8 (JS_PMA0_LANE2_BASE + 4*0x09) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_REQ_PARAM9 (JS_PMA0_LANE2_BASE + 4*0x0A) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_REQ_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x0B) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_ADAPT_REQ (JS_PMA0_LANE2_BASE + 4*0x10) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_ADAPT_REQ_ACK (JS_PMA0_LANE2_BASE + 4*0x11) //Attributes : RO +#define JS_PMA0_LANE2_RECEIVER_ADAPT_DIR (JS_PMA0_LANE2_BASE + 4*0x12) //Attributes : RO +#define JS_PMA0_LANE2_RECEIVER_ADAPT_SETTING (JS_PMA0_LANE2_BASE + 4*0x13) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_ADAPT_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x14) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_DATAPATH_EN (JS_PMA0_LANE2_BASE + 4*0x20) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_DATAPATH_SETTING1 (JS_PMA0_LANE2_BASE + 4*0x21) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_DATAPATH_SETTING2 (JS_PMA0_LANE2_BASE + 4*0x22) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_DATAPATH_SETTING3 (JS_PMA0_LANE2_BASE + 4*0x23) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_DATAPATH_STATUS1 (JS_PMA0_LANE2_BASE + 4*0x24) //Attributes : RO +#define JS_PMA0_LANE2_RECEIVER_DATAPATH_STATUS2 (JS_PMA0_LANE2_BASE + 4*0x25) //Attributes : RO +#define JS_PMA0_LANE2_RECEIVER_DATAPATH_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x26) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_RESET (JS_PMA0_LANE2_BASE + 4*0x30) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_CONTROL (JS_PMA0_LANE2_BASE + 4*0x31) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_CONTROL_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x32) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_RECAL_CTRL (JS_PMA0_LANE2_BASE + 4*0x40) //Attributes : RW +#define JS_PMA0_LANE2_RECEIVER_RECAL_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x41) //Attributes : RW +#define JS_PMA0_LANE2_TRANSMITTER_REQ (JS_PMA0_LANE2_BASE + 4*0x50) //Attributes : RW +#define JS_PMA0_LANE2_TRANSMITTER_REQ_ACK (JS_PMA0_LANE2_BASE + 4*0x51) //Attributes : RO +#define JS_PMA0_LANE2_TRANSMITTER_REQ_PARAM1 (JS_PMA0_LANE2_BASE + 4*0x52) //Attributes : RW +#define JS_PMA0_LANE2_TRANSMITTER_REQ_PARAM2 (JS_PMA0_LANE2_BASE + 4*0x53) //Attributes : RW +#define JS_PMA0_LANE2_TRANSMITTER_REQ_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x55) //Attributes : RW +#define JS_PMA0_LANE2_TRANSMITTER_DATAPATH_EN (JS_PMA0_LANE2_BASE + 4*0x60) //Attributes : RW +#define JS_PMA0_LANE2_TRANSMITTER_DATAPATH_CLKRDY (JS_PMA0_LANE2_BASE + 4*0x61) //Attributes : RW +#define JS_PMA0_LANE2_TRANSMITTER_DATAPATH_SETTING (JS_PMA0_LANE2_BASE + 4*0x62) //Attributes : RW +#define JS_PMA0_LANE2_TRANSMITTER_DATAPATH_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x63) //Attributes : RW +#define JS_PMA0_LANE2_TRANSMITTER_CONTROL1 (JS_PMA0_LANE2_BASE + 4*0x70) //Attributes : RW +#define JS_PMA0_LANE2_TRANSMITTER_CONTROL2 (JS_PMA0_LANE2_BASE + 4*0x71) //Attributes : RW +#define JS_PMA0_LANE2_TRANSMITTER_CONTROL_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x72) //Attributes : RW +#define JS_PMA0_LANE2_TRANSMITTER_EQ1 (JS_PMA0_LANE2_BASE + 4*0x80) //Attributes : RW +#define JS_PMA0_LANE2_TRANSMITTER_EQ2 (JS_PMA0_LANE2_BASE + 4*0x81) //Attributes : RW +#define JS_PMA0_LANE2_TRANSMITTER_EQ3 (JS_PMA0_LANE2_BASE + 4*0x82) //Attributes : RW +#define JS_PMA0_LANE2_TRANSMITTER_EQ_MUX_CTRL (JS_PMA0_LANE2_BASE + 4*0x83) //Attributes : RW +#define JS_PMA0_LANE2_CONTEXT_RESTORE_CTRL1 (JS_PMA0_LANE2_BASE + 4*0x90) //Attributes : RW +#define JS_PMA0_LANE2_CONTEXT_RESTORE_CTRL2 (JS_PMA0_LANE2_BASE + 4*0x91) //Attributes : RW +#define JS_PMA0_LANE2_CONTEXT_RESTORE_CTRL3 (JS_PMA0_LANE2_BASE + 4*0x92) //Attributes : RW +#define JS_PMA0_LANE2_CONTEXT_RESTORE_CTRL4 (JS_PMA0_LANE2_BASE + 4*0x93) //Attributes : RW +#define JS_PMA0_LANE2_CONTEXT_RESTORE_MUX (JS_PMA0_LANE2_BASE + 4*0x94) //Attributes : RW +#define JS_PMA0_LANE2_LANE_REFCLK_SEL (JS_PMA0_LANE2_BASE + 4*0xA0) //Attributes : RW +#define JS_PMA0_LANE2_ETH_CLK_CTRL (JS_PMA0_LANE2_BASE + 4*0xB0) //Attributes : RW +#define JS_PMA0_LANE2_ETH_CLK_CTRL_MUX (JS_PMA0_LANE2_BASE + 4*0xB1) //Attributes : RW +#define JS_PMA0_LANE2_RX_ADAPT_CTRL (JS_PMA0_LANE2_BASE + 4*0xC0) //Attributes : RW +#define JS_PMA0_LANE2_RX_DCC_CTRL (JS_PMA0_LANE2_BASE + 4*0xC1) //Attributes : RW +#define JS_PMA0_LANE2_RX_EQ_CTRL1 (JS_PMA0_LANE2_BASE + 4*0xC2) //Attributes : RW +#define JS_PMA0_LANE2_RX_EQ_CTRL2 (JS_PMA0_LANE2_BASE + 4*0xC3) //Attributes : RW +#define JS_PMA0_LANE2_RX_MARGIN_CTRL (JS_PMA0_LANE2_BASE + 4*0xC4) //Attributes : RW +#define JS_PMA0_LANE2_RX_MARGIN_ERROR (JS_PMA0_LANE2_BASE + 4*0xC5) //Attributes : RO +#define JS_PMA0_LANE2_RECV_REQUEST_CTRL_MUX (JS_PMA0_LANE2_BASE + 4*0xC6) //Attributes : RW +#define JS_PMA0_LANE2_RX_COARSE_ADAPT_CTRL (JS_PMA0_LANE2_BASE + 4*0xC8) //Attributes : RW +#define JS_PMA0_LANE2_RX_COARSE_ADAPT_CTRL_MUX (JS_PMA0_LANE2_BASE + 4*0xC9) //Attributes : RW +#define JS_PMA0_LANE2_RX_DIV_CLK_CTRL (JS_PMA0_LANE2_BASE + 4*0xCA) //Attributes : RW +#define JS_PMA0_LANE2_TX_DIV_CLK_CTRL (JS_PMA0_LANE2_BASE + 4*0xCB) //Attributes : RW +#define JS_PMA0_LANE2_MULTI_CLK_CTRL_MUX (JS_PMA0_LANE2_BASE + 4*0xCC) //Attributes : RW +#define JS_PMA0_LANE2_TRANS_REQ_CTRL1 (JS_PMA0_LANE2_BASE + 4*0xD0) //Attributes : RW +#define JS_PMA0_LANE2_TRANS_REQ_CTRL2 (JS_PMA0_LANE2_BASE + 4*0xD1) //Attributes : RW +#define JS_PMA0_LANE2_TRANS_REQ_CTRL3 (JS_PMA0_LANE2_BASE + 4*0xD2) //Attributes : RW +#define JS_PMA0_LANE2_TRANS_REQ_CTRL4 (JS_PMA0_LANE2_BASE + 4*0xD3) //Attributes : RW +#define JS_PMA0_LANE2_TRANS_REQ_CTRL5 (JS_PMA0_LANE2_BASE + 4*0xD4) //Attributes : RW +#define JS_PMA0_LANE2_TRANS_REQ_MUX (JS_PMA0_LANE2_BASE + 4*0xD5) //Attributes : RW +#define JS_PMA0_LANE2_TRANS_INTERFACE_CTRL (JS_PMA0_LANE2_BASE + 4*0xD6) //Attributes : RW +#define JS_PMA0_LANE2_TRANS_INTERFACE_MUX (JS_PMA0_LANE2_BASE + 4*0xD7) //Attributes : RW +#define JS_PMA0_LANE2_TRANS_MASTER_PLL_STATE (JS_PMA0_LANE2_BASE + 4*0xD8) //Attributes : RW +#define JS_PMA0_LANE2_TRANS_PLL_STATE (JS_PMA0_LANE2_BASE + 4*0xD9) //Attributes : RO +#define JS_PMA0_LANE2_PLL_STATE_MUX (JS_PMA0_LANE2_BASE + 4*0xDA) //Attributes : RW +#define JS_PMA0_LANE2_RX_VALID_PHY (JS_PMA0_LANE2_BASE + 4*0xDF) //Attributes : RO +#define JS_PMA0_LANE2_RX_VALID_MUX (JS_PMA0_LANE2_BASE + 4*0xE0) //Attributes : RW +#define JS_PMA0_LANE2_RX_SRIO_SIGDET_MUX (JS_PMA0_LANE2_BASE + 4*0xE1) //Attributes : RW +#define JS_PMA0_LANE2_SRIO_DEGRADED (JS_PMA0_LANE2_BASE + 4*0xE2) //Attributes : RW +#define JS_PMA0_LANE2_SRIO_RETRAIN (JS_PMA0_LANE2_BASE + 4*0xE3) //Attributes : RW +#define JS_PMA0_LANE2_SRIO_SHORT_RUN (JS_PMA0_LANE2_BASE + 4*0xE4) //Attributes : RW +#define JS_PMA0_LANE2_EQ_INIT_C0 (JS_PMA0_LANE2_BASE + 4*0xE5) //Attributes : RW +#define JS_PMA0_LANE2_EQ_INIT_CN1 (JS_PMA0_LANE2_BASE + 4*0xE6) //Attributes : RW +#define JS_PMA0_LANE2_EQ_INIT_CP1 (JS_PMA0_LANE2_BASE + 4*0xE7) //Attributes : RW +#define JS_PMA0_LANE2_EQ_RULE_CTRL_1 (JS_PMA0_LANE2_BASE + 4*0xE8) //Attributes : RW +#define JS_PMA0_LANE2_EQ_RULE_CTRL_2 (JS_PMA0_LANE2_BASE + 4*0xE9) //Attributes : RW +#define JS_PMA0_LANE2_EQ_RULE_CTRL_3 (JS_PMA0_LANE2_BASE + 4*0xEA) //Attributes : RW +#define JS_PMA0_LANE2_EQ_RULE_CTRL_4 (JS_PMA0_LANE2_BASE + 4*0xEB) //Attributes : RW +#define JS_PMA0_LANE2_EQ_ALGORITHM_CTRL (JS_PMA0_LANE2_BASE + 4*0xEC) //Attributes : RW +#define JS_PMA0_LANE2_EQ_TX_TRAIN_CTRL (JS_PMA0_LANE2_BASE + 4*0xED) //Attributes : RW +#define JS_PMA0_LANE2_EQ_ADJ_INTERVAL (JS_PMA0_LANE2_BASE + 4*0xEE) //Attributes : RW +#define JS_PMA0_LANE2_EQ_RX_REQ_CTRL (JS_PMA0_LANE2_BASE + 4*0xEF) //Attributes : RW +#define JS_PMA0_LANE2_EQ_RX_TRAIN_CTRL (JS_PMA0_LANE2_BASE + 4*0xF0) //Attributes : RW +#define JS_PMA0_LANE2_EQ_RX_RESET_CYCLE (JS_PMA0_LANE2_BASE + 4*0xF1) //Attributes : RW +#define JS_PMA0_LANE2_RPCS_KTR_STATUS (JS_PMA0_LANE2_BASE + 4*0xF2) //Attributes : RO +#define JS_PMA0_LANE2_EQ_FSM (JS_PMA0_LANE2_BASE + 4*0xF3) //Attributes : RO +#define JS_PMA0_LANE2_ETH_RX_LOS (JS_PMA0_LANE2_BASE + 4*0xF4) //Attributes : RW +#define JS_PMA0_LANE2_EQ_PRESET_C0 (JS_PMA0_LANE2_BASE + 4*0xF5) //Attributes : RW +#define JS_PMA0_LANE2_EQ_PRESET_CN1 (JS_PMA0_LANE2_BASE + 4*0xF6) //Attributes : RW +#define JS_PMA0_LANE2_EQ_PRESET_CP1 (JS_PMA0_LANE2_BASE + 4*0xF7) //Attributes : RW +#define JS_PMA0_LANE2_EQ_SUCC_MASK (JS_PMA0_LANE2_BASE + 4*0xF8) //Attributes : RW +#define JS_PMA0_LANE2_PMA_COM_SCRATCH (JS_PMA0_LANE2_BASE + 4*0xFF) //Attributes : RW +#define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY0 (JS_PMA0_LANE2_BASE + 4*0x100) //Attributes : RO_EXT_L +#define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY1 (JS_PMA0_LANE2_BASE + 4*0x101) //Attributes : RO_EXT +#define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY2 (JS_PMA0_LANE2_BASE + 4*0x102) //Attributes : RO_EXT +#define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY3 (JS_PMA0_LANE2_BASE + 4*0x103) //Attributes : RO_EXT +#define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY4 (JS_PMA0_LANE2_BASE + 4*0x104) //Attributes : RO_EXT +#define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY5 (JS_PMA0_LANE2_BASE + 4*0x105) //Attributes : RO_EXT +#define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY6 (JS_PMA0_LANE2_BASE + 4*0x106) //Attributes : RO_EXT +#define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY7 (JS_PMA0_LANE2_BASE + 4*0x107) //Attributes : RO_EXT_H +#define JS_PMA0_LANE2_EQ_TX_FSM_HISTORY_CTRL (JS_PMA0_LANE2_BASE + 4*0x108) //Attributes : RW +#define JS_PMA0_LANE2_EQ_RX_FSM_HISTORY0 (JS_PMA0_LANE2_BASE + 4*0x109) //Attributes : RO_EXT_L +#define JS_PMA0_LANE2_EQ_RX_FSM_HISTORY1 (JS_PMA0_LANE2_BASE + 4*0x10A) //Attributes : RO_EXT +#define JS_PMA0_LANE2_EQ_RX_FSM_HISTORY2 (JS_PMA0_LANE2_BASE + 4*0x10B) //Attributes : RO_EXT +#define JS_PMA0_LANE2_EQ_RX_FSM_HISTORY3 (JS_PMA0_LANE2_BASE + 4*0x10C) //Attributes : RO_EXT_H +#define JS_PMA0_LANE2_EQ_RX_FSM_HISTORY_CTRL (JS_PMA0_LANE2_BASE + 4*0x10D) //Attributes : RW +#define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY0 (JS_PMA0_LANE2_BASE + 4*0x110) //Attributes : RO_EXT_L +#define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY1 (JS_PMA0_LANE2_BASE + 4*0x111) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY2 (JS_PMA0_LANE2_BASE + 4*0x112) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY3 (JS_PMA0_LANE2_BASE + 4*0x113) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY4 (JS_PMA0_LANE2_BASE + 4*0x114) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY5 (JS_PMA0_LANE2_BASE + 4*0x115) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY6 (JS_PMA0_LANE2_BASE + 4*0x116) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY7 (JS_PMA0_LANE2_BASE + 4*0x117) //Attributes : RO_EXT_H +#define JS_PMA0_LANE2_TX_EQ_MAIN_HISTORY_CTRL (JS_PMA0_LANE2_BASE + 4*0x118) //Attributes : RW +#define JS_PMA0_LANE2_RX_TXMAIN_DIR_HISTORY0 (JS_PMA0_LANE2_BASE + 4*0x119) //Attributes : RO_EXT_L +#define JS_PMA0_LANE2_RX_TXMAIN_DIR_HISTORY1 (JS_PMA0_LANE2_BASE + 4*0x11A) //Attributes : RO_EXT +#define JS_PMA0_LANE2_RX_TXMAIN_DIR_HISTORY2 (JS_PMA0_LANE2_BASE + 4*0x11B) //Attributes : RO_EXT +#define JS_PMA0_LANE2_RX_TXMAIN_DIR_HISTORY3 (JS_PMA0_LANE2_BASE + 4*0x11C) //Attributes : RO_EXT_H +#define JS_PMA0_LANE2_RX_TXMAIN_DIR_HISTORY_CTRL (JS_PMA0_LANE2_BASE + 4*0x11D) //Attributes : RW +#define JS_PMA0_LANE2_TX_EQ_POST_HISTORY0 (JS_PMA0_LANE2_BASE + 4*0x120) //Attributes : RO_EXT_L +#define JS_PMA0_LANE2_TX_EQ_POST_HISTORY1 (JS_PMA0_LANE2_BASE + 4*0x121) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_POST_HISTORY2 (JS_PMA0_LANE2_BASE + 4*0x122) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_POST_HISTORY3 (JS_PMA0_LANE2_BASE + 4*0x123) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_POST_HISTORY4 (JS_PMA0_LANE2_BASE + 4*0x124) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_POST_HISTORY5 (JS_PMA0_LANE2_BASE + 4*0x125) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_POST_HISTORY6 (JS_PMA0_LANE2_BASE + 4*0x126) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_POST_HISTORY7 (JS_PMA0_LANE2_BASE + 4*0x127) //Attributes : RO_EXT_H +#define JS_PMA0_LANE2_TX_EQ_POST_HISTORY_CTRL (JS_PMA0_LANE2_BASE + 4*0x128) //Attributes : RW +#define JS_PMA0_LANE2_RX_TXPOST_DIR_HISTORY0 (JS_PMA0_LANE2_BASE + 4*0x129) //Attributes : RO_EXT_L +#define JS_PMA0_LANE2_RX_TXPOST_DIR_HISTORY1 (JS_PMA0_LANE2_BASE + 4*0x12A) //Attributes : RO_EXT +#define JS_PMA0_LANE2_RX_TXPOST_DIR_HISTORY2 (JS_PMA0_LANE2_BASE + 4*0x12B) //Attributes : RO_EXT +#define JS_PMA0_LANE2_RX_TXPOST_DIR_HISTORY3 (JS_PMA0_LANE2_BASE + 4*0x12C) //Attributes : RO_EXT_H +#define JS_PMA0_LANE2_RX_TXPOST_DIR_HISTORY_CTRL (JS_PMA0_LANE2_BASE + 4*0x12D) //Attributes : RW +#define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY0 (JS_PMA0_LANE2_BASE + 4*0x130) //Attributes : RO_EXT_L +#define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY1 (JS_PMA0_LANE2_BASE + 4*0x131) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY2 (JS_PMA0_LANE2_BASE + 4*0x132) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY3 (JS_PMA0_LANE2_BASE + 4*0x133) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY4 (JS_PMA0_LANE2_BASE + 4*0x134) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY5 (JS_PMA0_LANE2_BASE + 4*0x135) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY6 (JS_PMA0_LANE2_BASE + 4*0x136) //Attributes : RO_EXT +#define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY7 (JS_PMA0_LANE2_BASE + 4*0x137) //Attributes : RO_EXT_H +#define JS_PMA0_LANE2_TX_EQ_PRE_HISTORY_CTRL (JS_PMA0_LANE2_BASE + 4*0x138) //Attributes : RW +#define JS_PMA0_LANE2_RX_TXPRE_DIR_HISTORY0 (JS_PMA0_LANE2_BASE + 4*0x139) //Attributes : RO_EXT_L +#define JS_PMA0_LANE2_RX_TXPRE_DIR_HISTORY1 (JS_PMA0_LANE2_BASE + 4*0x13A) //Attributes : RO_EXT +#define JS_PMA0_LANE2_RX_TXPRE_DIR_HISTORY2 (JS_PMA0_LANE2_BASE + 4*0x13B) //Attributes : RO_EXT +#define JS_PMA0_LANE2_RX_TXPRE_DIR_HISTORY3 (JS_PMA0_LANE2_BASE + 4*0x13C) //Attributes : RO_EXT_H +#define JS_PMA0_LANE2_RX_TXPRE_DIR_HISTORY_CTRL (JS_PMA0_LANE2_BASE + 4*0x13D) //Attributes : RW + +#define JS_PMA0_LANE3_PMA_LOOPBACK_CTRL (JS_PMA0_LANE3_BASE + 4*0x00) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_REQ (JS_PMA0_LANE3_BASE + 4*0x01) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_REQ_ACK (JS_PMA0_LANE3_BASE + 4*0x02) //Attributes : RO +#define JS_PMA0_LANE3_RECEIVER_REQ_PARAM2 (JS_PMA0_LANE3_BASE + 4*0x03) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_REQ_PARAM3 (JS_PMA0_LANE3_BASE + 4*0x04) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_REQ_PARAM4 (JS_PMA0_LANE3_BASE + 4*0x05) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_REQ_PARAM5 (JS_PMA0_LANE3_BASE + 4*0x06) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_REQ_PARAM6 (JS_PMA0_LANE3_BASE + 4*0x07) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_REQ_PARAM7 (JS_PMA0_LANE3_BASE + 4*0x08) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_REQ_PARAM8 (JS_PMA0_LANE3_BASE + 4*0x09) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_REQ_PARAM9 (JS_PMA0_LANE3_BASE + 4*0x0A) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_REQ_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x0B) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_ADAPT_REQ (JS_PMA0_LANE3_BASE + 4*0x10) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_ADAPT_REQ_ACK (JS_PMA0_LANE3_BASE + 4*0x11) //Attributes : RO +#define JS_PMA0_LANE3_RECEIVER_ADAPT_DIR (JS_PMA0_LANE3_BASE + 4*0x12) //Attributes : RO +#define JS_PMA0_LANE3_RECEIVER_ADAPT_SETTING (JS_PMA0_LANE3_BASE + 4*0x13) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_ADAPT_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x14) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_DATAPATH_EN (JS_PMA0_LANE3_BASE + 4*0x20) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_DATAPATH_SETTING1 (JS_PMA0_LANE3_BASE + 4*0x21) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_DATAPATH_SETTING2 (JS_PMA0_LANE3_BASE + 4*0x22) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_DATAPATH_SETTING3 (JS_PMA0_LANE3_BASE + 4*0x23) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_DATAPATH_STATUS1 (JS_PMA0_LANE3_BASE + 4*0x24) //Attributes : RO +#define JS_PMA0_LANE3_RECEIVER_DATAPATH_STATUS2 (JS_PMA0_LANE3_BASE + 4*0x25) //Attributes : RO +#define JS_PMA0_LANE3_RECEIVER_DATAPATH_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x26) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_RESET (JS_PMA0_LANE3_BASE + 4*0x30) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_CONTROL (JS_PMA0_LANE3_BASE + 4*0x31) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_CONTROL_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x32) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_RECAL_CTRL (JS_PMA0_LANE3_BASE + 4*0x40) //Attributes : RW +#define JS_PMA0_LANE3_RECEIVER_RECAL_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x41) //Attributes : RW +#define JS_PMA0_LANE3_TRANSMITTER_REQ (JS_PMA0_LANE3_BASE + 4*0x50) //Attributes : RW +#define JS_PMA0_LANE3_TRANSMITTER_REQ_ACK (JS_PMA0_LANE3_BASE + 4*0x51) //Attributes : RO +#define JS_PMA0_LANE3_TRANSMITTER_REQ_PARAM1 (JS_PMA0_LANE3_BASE + 4*0x52) //Attributes : RW +#define JS_PMA0_LANE3_TRANSMITTER_REQ_PARAM2 (JS_PMA0_LANE3_BASE + 4*0x53) //Attributes : RW +#define JS_PMA0_LANE3_TRANSMITTER_REQ_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x55) //Attributes : RW +#define JS_PMA0_LANE3_TRANSMITTER_DATAPATH_EN (JS_PMA0_LANE3_BASE + 4*0x60) //Attributes : RW +#define JS_PMA0_LANE3_TRANSMITTER_DATAPATH_CLKRDY (JS_PMA0_LANE3_BASE + 4*0x61) //Attributes : RW +#define JS_PMA0_LANE3_TRANSMITTER_DATAPATH_SETTING (JS_PMA0_LANE3_BASE + 4*0x62) //Attributes : RW +#define JS_PMA0_LANE3_TRANSMITTER_DATAPATH_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x63) //Attributes : RW +#define JS_PMA0_LANE3_TRANSMITTER_CONTROL1 (JS_PMA0_LANE3_BASE + 4*0x70) //Attributes : RW +#define JS_PMA0_LANE3_TRANSMITTER_CONTROL2 (JS_PMA0_LANE3_BASE + 4*0x71) //Attributes : RW +#define JS_PMA0_LANE3_TRANSMITTER_CONTROL_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x72) //Attributes : RW +#define JS_PMA0_LANE3_TRANSMITTER_EQ1 (JS_PMA0_LANE3_BASE + 4*0x80) //Attributes : RW +#define JS_PMA0_LANE3_TRANSMITTER_EQ2 (JS_PMA0_LANE3_BASE + 4*0x81) //Attributes : RW +#define JS_PMA0_LANE3_TRANSMITTER_EQ3 (JS_PMA0_LANE3_BASE + 4*0x82) //Attributes : RW +#define JS_PMA0_LANE3_TRANSMITTER_EQ_MUX_CTRL (JS_PMA0_LANE3_BASE + 4*0x83) //Attributes : RW +#define JS_PMA0_LANE3_CONTEXT_RESTORE_CTRL1 (JS_PMA0_LANE3_BASE + 4*0x90) //Attributes : RW +#define JS_PMA0_LANE3_CONTEXT_RESTORE_CTRL2 (JS_PMA0_LANE3_BASE + 4*0x91) //Attributes : RW +#define JS_PMA0_LANE3_CONTEXT_RESTORE_CTRL3 (JS_PMA0_LANE3_BASE + 4*0x92) //Attributes : RW +#define JS_PMA0_LANE3_CONTEXT_RESTORE_CTRL4 (JS_PMA0_LANE3_BASE + 4*0x93) //Attributes : RW +#define JS_PMA0_LANE3_CONTEXT_RESTORE_MUX (JS_PMA0_LANE3_BASE + 4*0x94) //Attributes : RW +#define JS_PMA0_LANE3_LANE_REFCLK_SEL (JS_PMA0_LANE3_BASE + 4*0xA0) //Attributes : RW +#define JS_PMA0_LANE3_ETH_CLK_CTRL (JS_PMA0_LANE3_BASE + 4*0xB0) //Attributes : RW +#define JS_PMA0_LANE3_ETH_CLK_CTRL_MUX (JS_PMA0_LANE3_BASE + 4*0xB1) //Attributes : RW +#define JS_PMA0_LANE3_RX_ADAPT_CTRL (JS_PMA0_LANE3_BASE + 4*0xC0) //Attributes : RW +#define JS_PMA0_LANE3_RX_DCC_CTRL (JS_PMA0_LANE3_BASE + 4*0xC1) //Attributes : RW +#define JS_PMA0_LANE3_RX_EQ_CTRL1 (JS_PMA0_LANE3_BASE + 4*0xC2) //Attributes : RW +#define JS_PMA0_LANE3_RX_EQ_CTRL2 (JS_PMA0_LANE3_BASE + 4*0xC3) //Attributes : RW +#define JS_PMA0_LANE3_RX_MARGIN_CTRL (JS_PMA0_LANE3_BASE + 4*0xC4) //Attributes : RW +#define JS_PMA0_LANE3_RX_MARGIN_ERROR (JS_PMA0_LANE3_BASE + 4*0xC5) //Attributes : RO +#define JS_PMA0_LANE3_RECV_REQUEST_CTRL_MUX (JS_PMA0_LANE3_BASE + 4*0xC6) //Attributes : RW +#define JS_PMA0_LANE3_RX_COARSE_ADAPT_CTRL (JS_PMA0_LANE3_BASE + 4*0xC8) //Attributes : RW +#define JS_PMA0_LANE3_RX_COARSE_ADAPT_CTRL_MUX (JS_PMA0_LANE3_BASE + 4*0xC9) //Attributes : RW +#define JS_PMA0_LANE3_RX_DIV_CLK_CTRL (JS_PMA0_LANE3_BASE + 4*0xCA) //Attributes : RW +#define JS_PMA0_LANE3_TX_DIV_CLK_CTRL (JS_PMA0_LANE3_BASE + 4*0xCB) //Attributes : RW +#define JS_PMA0_LANE3_MULTI_CLK_CTRL_MUX (JS_PMA0_LANE3_BASE + 4*0xCC) //Attributes : RW +#define JS_PMA0_LANE3_TRANS_REQ_CTRL1 (JS_PMA0_LANE3_BASE + 4*0xD0) //Attributes : RW +#define JS_PMA0_LANE3_TRANS_REQ_CTRL2 (JS_PMA0_LANE3_BASE + 4*0xD1) //Attributes : RW +#define JS_PMA0_LANE3_TRANS_REQ_CTRL3 (JS_PMA0_LANE3_BASE + 4*0xD2) //Attributes : RW +#define JS_PMA0_LANE3_TRANS_REQ_CTRL4 (JS_PMA0_LANE3_BASE + 4*0xD3) //Attributes : RW +#define JS_PMA0_LANE3_TRANS_REQ_CTRL5 (JS_PMA0_LANE3_BASE + 4*0xD4) //Attributes : RW +#define JS_PMA0_LANE3_TRANS_REQ_MUX (JS_PMA0_LANE3_BASE + 4*0xD5) //Attributes : RW +#define JS_PMA0_LANE3_TRANS_INTERFACE_CTRL (JS_PMA0_LANE3_BASE + 4*0xD6) //Attributes : RW +#define JS_PMA0_LANE3_TRANS_INTERFACE_MUX (JS_PMA0_LANE3_BASE + 4*0xD7) //Attributes : RW +#define JS_PMA0_LANE3_TRANS_MASTER_PLL_STATE (JS_PMA0_LANE3_BASE + 4*0xD8) //Attributes : RW +#define JS_PMA0_LANE3_TRANS_PLL_STATE (JS_PMA0_LANE3_BASE + 4*0xD9) //Attributes : RO +#define JS_PMA0_LANE3_PLL_STATE_MUX (JS_PMA0_LANE3_BASE + 4*0xDA) //Attributes : RW +#define JS_PMA0_LANE3_RX_VALID_PHY (JS_PMA0_LANE3_BASE + 4*0xDF) //Attributes : RO +#define JS_PMA0_LANE3_RX_VALID_MUX (JS_PMA0_LANE3_BASE + 4*0xE0) //Attributes : RW +#define JS_PMA0_LANE3_RX_SRIO_SIGDET_MUX (JS_PMA0_LANE3_BASE + 4*0xE1) //Attributes : RW +#define JS_PMA0_LANE3_SRIO_DEGRADED (JS_PMA0_LANE3_BASE + 4*0xE2) //Attributes : RW +#define JS_PMA0_LANE3_SRIO_RETRAIN (JS_PMA0_LANE3_BASE + 4*0xE3) //Attributes : RW +#define JS_PMA0_LANE3_SRIO_SHORT_RUN (JS_PMA0_LANE3_BASE + 4*0xE4) //Attributes : RW +#define JS_PMA0_LANE3_EQ_INIT_C0 (JS_PMA0_LANE3_BASE + 4*0xE5) //Attributes : RW +#define JS_PMA0_LANE3_EQ_INIT_CN1 (JS_PMA0_LANE3_BASE + 4*0xE6) //Attributes : RW +#define JS_PMA0_LANE3_EQ_INIT_CP1 (JS_PMA0_LANE3_BASE + 4*0xE7) //Attributes : RW +#define JS_PMA0_LANE3_EQ_RULE_CTRL_1 (JS_PMA0_LANE3_BASE + 4*0xE8) //Attributes : RW +#define JS_PMA0_LANE3_EQ_RULE_CTRL_2 (JS_PMA0_LANE3_BASE + 4*0xE9) //Attributes : RW +#define JS_PMA0_LANE3_EQ_RULE_CTRL_3 (JS_PMA0_LANE3_BASE + 4*0xEA) //Attributes : RW +#define JS_PMA0_LANE3_EQ_RULE_CTRL_4 (JS_PMA0_LANE3_BASE + 4*0xEB) //Attributes : RW +#define JS_PMA0_LANE3_EQ_ALGORITHM_CTRL (JS_PMA0_LANE3_BASE + 4*0xEC) //Attributes : RW +#define JS_PMA0_LANE3_EQ_TX_TRAIN_CTRL (JS_PMA0_LANE3_BASE + 4*0xED) //Attributes : RW +#define JS_PMA0_LANE3_EQ_ADJ_INTERVAL (JS_PMA0_LANE3_BASE + 4*0xEE) //Attributes : RW +#define JS_PMA0_LANE3_EQ_RX_REQ_CTRL (JS_PMA0_LANE3_BASE + 4*0xEF) //Attributes : RW +#define JS_PMA0_LANE3_EQ_RX_TRAIN_CTRL (JS_PMA0_LANE3_BASE + 4*0xF0) //Attributes : RW +#define JS_PMA0_LANE3_EQ_RX_RESET_CYCLE (JS_PMA0_LANE3_BASE + 4*0xF1) //Attributes : RW +#define JS_PMA0_LANE3_RPCS_KTR_STATUS (JS_PMA0_LANE3_BASE + 4*0xF2) //Attributes : RO +#define JS_PMA0_LANE3_EQ_FSM (JS_PMA0_LANE3_BASE + 4*0xF3) //Attributes : RO +#define JS_PMA0_LANE3_ETH_RX_LOS (JS_PMA0_LANE3_BASE + 4*0xF4) //Attributes : RW +#define JS_PMA0_LANE3_EQ_PRESET_C0 (JS_PMA0_LANE3_BASE + 4*0xF5) //Attributes : RW +#define JS_PMA0_LANE3_EQ_PRESET_CN1 (JS_PMA0_LANE3_BASE + 4*0xF6) //Attributes : RW +#define JS_PMA0_LANE3_EQ_PRESET_CP1 (JS_PMA0_LANE3_BASE + 4*0xF7) //Attributes : RW +#define JS_PMA0_LANE3_EQ_SUCC_MASK (JS_PMA0_LANE3_BASE + 4*0xF8) //Attributes : RW +#define JS_PMA0_LANE3_PMA_COM_SCRATCH (JS_PMA0_LANE3_BASE + 4*0xff) //Attributes : RW +#define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY0 (JS_PMA0_LANE3_BASE + 4*0x100) //Attributes : RO_EXT_L +#define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY1 (JS_PMA0_LANE3_BASE + 4*0x101) //Attributes : RO_EXT +#define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY2 (JS_PMA0_LANE3_BASE + 4*0x102) //Attributes : RO_EXT +#define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY3 (JS_PMA0_LANE3_BASE + 4*0x103) //Attributes : RO_EXT +#define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY4 (JS_PMA0_LANE3_BASE + 4*0x104) //Attributes : RO_EXT +#define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY5 (JS_PMA0_LANE3_BASE + 4*0x105) //Attributes : RO_EXT +#define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY6 (JS_PMA0_LANE3_BASE + 4*0x106) //Attributes : RO_EXT +#define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY7 (JS_PMA0_LANE3_BASE + 4*0x107) //Attributes : RO_EXT_H +#define JS_PMA0_LANE3_EQ_TX_FSM_HISTORY_CTRL (JS_PMA0_LANE3_BASE + 4*0x108) //Attributes : RW +#define JS_PMA0_LANE3_EQ_RX_FSM_HISTORY0 (JS_PMA0_LANE3_BASE + 4*0x109) //Attributes : RO_EXT_L +#define JS_PMA0_LANE3_EQ_RX_FSM_HISTORY1 (JS_PMA0_LANE3_BASE + 4*0x10A) //Attributes : RO_EXT +#define JS_PMA0_LANE3_EQ_RX_FSM_HISTORY2 (JS_PMA0_LANE3_BASE + 4*0x10B) //Attributes : RO_EXT +#define JS_PMA0_LANE3_EQ_RX_FSM_HISTORY3 (JS_PMA0_LANE3_BASE + 4*0x10C) //Attributes : RO_EXT_H +#define JS_PMA0_LANE3_EQ_RX_FSM_HISTORY_CTRL (JS_PMA0_LANE3_BASE + 4*0x10D) //Attributes : RW +#define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY0 (JS_PMA0_LANE3_BASE + 4*0x110) //Attributes : RO_EXT_L +#define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY1 (JS_PMA0_LANE3_BASE + 4*0x111) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY2 (JS_PMA0_LANE3_BASE + 4*0x112) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY3 (JS_PMA0_LANE3_BASE + 4*0x113) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY4 (JS_PMA0_LANE3_BASE + 4*0x114) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY5 (JS_PMA0_LANE3_BASE + 4*0x115) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY6 (JS_PMA0_LANE3_BASE + 4*0x116) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY7 (JS_PMA0_LANE3_BASE + 4*0x117) //Attributes : RO_EXT_H +#define JS_PMA0_LANE3_TX_EQ_MAIN_HISTORY_CTRL (JS_PMA0_LANE3_BASE + 4*0x118) //Attributes : RW +#define JS_PMA0_LANE3_RX_TXMAIN_DIR_HISTORY0 (JS_PMA0_LANE3_BASE + 4*0x119) //Attributes : RO_EXT_L +#define JS_PMA0_LANE3_RX_TXMAIN_DIR_HISTORY1 (JS_PMA0_LANE3_BASE + 4*0x11A) //Attributes : RO_EXT +#define JS_PMA0_LANE3_RX_TXMAIN_DIR_HISTORY2 (JS_PMA0_LANE3_BASE + 4*0x11B) //Attributes : RO_EXT +#define JS_PMA0_LANE3_RX_TXMAIN_DIR_HISTORY3 (JS_PMA0_LANE3_BASE + 4*0x11C) //Attributes : RO_EXT_H +#define JS_PMA0_LANE3_RX_TXMAIN_DIR_HISTORY_CTRL (JS_PMA0_LANE3_BASE + 4*0x11D) //Attributes : RW +#define JS_PMA0_LANE3_TX_EQ_POST_HISTORY0 (JS_PMA0_LANE3_BASE + 4*0x120) //Attributes : RO_EXT_L +#define JS_PMA0_LANE3_TX_EQ_POST_HISTORY1 (JS_PMA0_LANE3_BASE + 4*0x121) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_POST_HISTORY2 (JS_PMA0_LANE3_BASE + 4*0x122) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_POST_HISTORY3 (JS_PMA0_LANE3_BASE + 4*0x123) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_POST_HISTORY4 (JS_PMA0_LANE3_BASE + 4*0x124) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_POST_HISTORY5 (JS_PMA0_LANE3_BASE + 4*0x125) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_POST_HISTORY6 (JS_PMA0_LANE3_BASE + 4*0x126) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_POST_HISTORY7 (JS_PMA0_LANE3_BASE + 4*0x127) //Attributes : RO_EXT_H +#define JS_PMA0_LANE3_TX_EQ_POST_HISTORY_CTRL (JS_PMA0_LANE3_BASE + 4*0x128) //Attributes : RW +#define JS_PMA0_LANE3_RX_TXPOST_DIR_HISTORY0 (JS_PMA0_LANE3_BASE + 4*0x129) //Attributes : RO_EXT_L +#define JS_PMA0_LANE3_RX_TXPOST_DIR_HISTORY1 (JS_PMA0_LANE3_BASE + 4*0x12A) //Attributes : RO_EXT +#define JS_PMA0_LANE3_RX_TXPOST_DIR_HISTORY2 (JS_PMA0_LANE3_BASE + 4*0x12B) //Attributes : RO_EXT +#define JS_PMA0_LANE3_RX_TXPOST_DIR_HISTORY3 (JS_PMA0_LANE3_BASE + 4*0x12C) //Attributes : RO_EXT_H +#define JS_PMA0_LANE3_RX_TXPOST_DIR_HISTORY_CTRL (JS_PMA0_LANE3_BASE + 4*0x12D) //Attributes : RW +#define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY0 (JS_PMA0_LANE3_BASE + 4*0x130) //Attributes : RO_EXT_L +#define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY1 (JS_PMA0_LANE3_BASE + 4*0x131) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY2 (JS_PMA0_LANE3_BASE + 4*0x132) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY3 (JS_PMA0_LANE3_BASE + 4*0x133) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY4 (JS_PMA0_LANE3_BASE + 4*0x134) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY5 (JS_PMA0_LANE3_BASE + 4*0x135) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY6 (JS_PMA0_LANE3_BASE + 4*0x136) //Attributes : RO_EXT +#define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY7 (JS_PMA0_LANE3_BASE + 4*0x137) //Attributes : RO_EXT_H +#define JS_PMA0_LANE3_TX_EQ_PRE_HISTORY_CTRL (JS_PMA0_LANE3_BASE + 4*0x138) //Attributes : RW +#define JS_PMA0_LANE3_RX_TXPRE_DIR_HISTORY0 (JS_PMA0_LANE3_BASE + 4*0x139) //Attributes : RO_EXT_L +#define JS_PMA0_LANE3_RX_TXPRE_DIR_HISTORY1 (JS_PMA0_LANE3_BASE + 4*0x13A) //Attributes : RO_EXT +#define JS_PMA0_LANE3_RX_TXPRE_DIR_HISTORY2 (JS_PMA0_LANE3_BASE + 4*0x13B) //Attributes : RO_EXT +#define JS_PMA0_LANE3_RX_TXPRE_DIR_HISTORY3 (JS_PMA0_LANE3_BASE + 4*0x13C) //Attributes : RO_EXT_H +#define JS_PMA0_LANE3_RX_TXPRE_DIR_HISTORY_CTRL (JS_PMA0_LANE3_BASE + 4*0x13D) //Attributes : RW + +#define JS_PMA0_BROADCAST_PMA_LOOPBACK_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x00) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_REQ (JS_PMA0_BROADCAST_BASE + 4*0x01) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_REQ_ACK (JS_PMA0_BROADCAST_BASE + 4*0x02) //Attributes : RO +#define JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM2 (JS_PMA0_BROADCAST_BASE + 4*0x03) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM3 (JS_PMA0_BROADCAST_BASE + 4*0x04) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM4 (JS_PMA0_BROADCAST_BASE + 4*0x05) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM5 (JS_PMA0_BROADCAST_BASE + 4*0x06) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM6 (JS_PMA0_BROADCAST_BASE + 4*0x07) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM7 (JS_PMA0_BROADCAST_BASE + 4*0x08) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM8 (JS_PMA0_BROADCAST_BASE + 4*0x09) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM9 (JS_PMA0_BROADCAST_BASE + 4*0x0A) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_REQ_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x0B) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_ADAPT_REQ (JS_PMA0_BROADCAST_BASE + 4*0x10) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_ADAPT_REQ_ACK (JS_PMA0_BROADCAST_BASE + 4*0x11) //Attributes : RO +#define JS_PMA0_BROADCAST_RECEIVER_ADAPT_DIR (JS_PMA0_BROADCAST_BASE + 4*0x12) //Attributes : RO +#define JS_PMA0_BROADCAST_RECEIVER_ADAPT_SETTING (JS_PMA0_BROADCAST_BASE + 4*0x13) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_ADAPT_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x14) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_DATAPATH_EN (JS_PMA0_BROADCAST_BASE + 4*0x20) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_DATAPATH_SETTING1 (JS_PMA0_BROADCAST_BASE + 4*0x21) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_DATAPATH_SETTING2 (JS_PMA0_BROADCAST_BASE + 4*0x22) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_DATAPATH_SETTING3 (JS_PMA0_BROADCAST_BASE + 4*0x23) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_DATAPATH_STATUS1 (JS_PMA0_BROADCAST_BASE + 4*0x24) //Attributes : RO +#define JS_PMA0_BROADCAST_RECEIVER_DATAPATH_STATUS2 (JS_PMA0_BROADCAST_BASE + 4*0x25) //Attributes : RO +#define JS_PMA0_BROADCAST_RECEIVER_DATAPATH_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x26) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_RESET (JS_PMA0_BROADCAST_BASE + 4*0x30) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_CONTROL (JS_PMA0_BROADCAST_BASE + 4*0x31) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_CONTROL_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x32) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_RECAL_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x40) //Attributes : RW +#define JS_PMA0_BROADCAST_RECEIVER_RECAL_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x41) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANSMITTER_REQ (JS_PMA0_BROADCAST_BASE + 4*0x50) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANSMITTER_REQ_ACK (JS_PMA0_BROADCAST_BASE + 4*0x51) //Attributes : RO +#define JS_PMA0_BROADCAST_TRANSMITTER_REQ_PARAM1 (JS_PMA0_BROADCAST_BASE + 4*0x52) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANSMITTER_REQ_PARAM2 (JS_PMA0_BROADCAST_BASE + 4*0x53) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANSMITTER_REQ_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x55) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANSMITTER_DATAPATH_EN (JS_PMA0_BROADCAST_BASE + 4*0x60) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANSMITTER_DATAPATH_CLKRDY (JS_PMA0_BROADCAST_BASE + 4*0x61) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANSMITTER_DATAPATH_SETTING (JS_PMA0_BROADCAST_BASE + 4*0x62) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANSMITTER_DATAPATH_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x63) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANSMITTER_CONTROL1 (JS_PMA0_BROADCAST_BASE + 4*0x70) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANSMITTER_CONTROL2 (JS_PMA0_BROADCAST_BASE + 4*0x71) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANSMITTER_CONTROL_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x72) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANSMITTER_EQ1 (JS_PMA0_BROADCAST_BASE + 4*0x80) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANSMITTER_EQ2 (JS_PMA0_BROADCAST_BASE + 4*0x81) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANSMITTER_EQ3 (JS_PMA0_BROADCAST_BASE + 4*0x82) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANSMITTER_EQ_MUX_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x83) //Attributes : RW +#define JS_PMA0_BROADCAST_CONTEXT_RESTORE_CTRL1 (JS_PMA0_BROADCAST_BASE + 4*0x90) //Attributes : RW +#define JS_PMA0_BROADCAST_CONTEXT_RESTORE_CTRL2 (JS_PMA0_BROADCAST_BASE + 4*0x91) //Attributes : RW +#define JS_PMA0_BROADCAST_CONTEXT_RESTORE_CTRL3 (JS_PMA0_BROADCAST_BASE + 4*0x92) //Attributes : RW +#define JS_PMA0_BROADCAST_CONTEXT_RESTORE_CTRL4 (JS_PMA0_BROADCAST_BASE + 4*0x93) //Attributes : RW +#define JS_PMA0_BROADCAST_CONTEXT_RESTORE_MUX (JS_PMA0_BROADCAST_BASE + 4*0x94) //Attributes : RW +#define JS_PMA0_BROADCAST_LANE_REFCLK_SEL (JS_PMA0_BROADCAST_BASE + 4*0xA0) //Attributes : RW +#define JS_PMA0_BROADCAST_ETH_CLK_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xB0) //Attributes : RW +#define JS_PMA0_BROADCAST_ETH_CLK_CTRL_MUX (JS_PMA0_BROADCAST_BASE + 4*0xB1) //Attributes : RW +#define JS_PMA0_BROADCAST_RX_ADAPT_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xC0) //Attributes : RW +#define JS_PMA0_BROADCAST_RX_DCC_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xC1) //Attributes : RW +#define JS_PMA0_BROADCAST_RX_EQ_CTRL1 (JS_PMA0_BROADCAST_BASE + 4*0xC2) //Attributes : RW +#define JS_PMA0_BROADCAST_RX_EQ_CTRL2 (JS_PMA0_BROADCAST_BASE + 4*0xC3) //Attributes : RW +#define JS_PMA0_BROADCAST_RX_MARGIN_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xC4) //Attributes : RW +#define JS_PMA0_BROADCAST_RX_MARGIN_ERROR (JS_PMA0_BROADCAST_BASE + 4*0xC5) //Attributes : RO +#define JS_PMA0_BROADCAST_RECV_REQUEST_CTRL_MUX (JS_PMA0_BROADCAST_BASE + 4*0xC6) //Attributes : RW +#define JS_PMA0_BROADCAST_RX_COARSE_ADAPT_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xC8) //Attributes : RW +#define JS_PMA0_BROADCAST_RX_COARSE_ADAPT_CTRL_MUX (JS_PMA0_BROADCAST_BASE + 4*0xC9) //Attributes : RW +#define JS_PMA0_BROADCAST_RX_DIV_CLK_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xCA) //Attributes : RW +#define JS_PMA0_BROADCAST_TX_DIV_CLK_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xCB) //Attributes : RW +#define JS_PMA0_BROADCAST_MULTI_CLK_CTRL_MUX (JS_PMA0_BROADCAST_BASE + 4*0xCC) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANS_REQ_CTRL1 (JS_PMA0_BROADCAST_BASE + 4*0xD0) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANS_REQ_CTRL2 (JS_PMA0_BROADCAST_BASE + 4*0xD1) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANS_REQ_CTRL3 (JS_PMA0_BROADCAST_BASE + 4*0xD2) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANS_REQ_CTRL4 (JS_PMA0_BROADCAST_BASE + 4*0xD3) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANS_REQ_CTRL5 (JS_PMA0_BROADCAST_BASE + 4*0xD4) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANS_REQ_MUX (JS_PMA0_BROADCAST_BASE + 4*0xD5) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANS_INTERFACE_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xD6) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANS_INTERFACE_MUX (JS_PMA0_BROADCAST_BASE + 4*0xD7) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANS_MASTER_PLL_STATE (JS_PMA0_BROADCAST_BASE + 4*0xD8) //Attributes : RW +#define JS_PMA0_BROADCAST_TRANS_PLL_STATE (JS_PMA0_BROADCAST_BASE + 4*0xD9) //Attributes : RO +#define JS_PMA0_BROADCAST_PLL_STATE_MUX (JS_PMA0_BROADCAST_BASE + 4*0xDA) //Attributes : RW +#define JS_PMA0_BROADCAST_RX_VALID_PHY (JS_PMA0_BROADCAST_BASE + 4*0xDF) //Attributes : RO +#define JS_PMA0_BROADCAST_RX_VALID_MUX (JS_PMA0_BROADCAST_BASE + 4*0xE0) //Attributes : RW +#define JS_PMA0_BROADCAST_RX_SRIO_SIGDET_MUX (JS_PMA0_BROADCAST_BASE + 4*0xE1) //Attributes : RW +#define JS_PMA0_BROADCAST_SRIO_DEGRADED (JS_PMA0_BROADCAST_BASE + 4*0xE2) //Attributes : RW +#define JS_PMA0_BROADCAST_SRIO_RETRAIN (JS_PMA0_BROADCAST_BASE + 4*0xE3) //Attributes : RW +#define JS_PMA0_BROADCAST_SRIO_SHORT_RUN (JS_PMA0_BROADCAST_BASE + 4*0xE4) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_INIT_C0 (JS_PMA0_BROADCAST_BASE + 4*0xE5) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_INIT_CN1 (JS_PMA0_BROADCAST_BASE + 4*0xE6) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_INIT_CP1 (JS_PMA0_BROADCAST_BASE + 4*0xE7) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_RULE_CTRL_1 (JS_PMA0_BROADCAST_BASE + 4*0xE8) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_RULE_CTRL_2 (JS_PMA0_BROADCAST_BASE + 4*0xE9) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_RULE_CTRL_3 (JS_PMA0_BROADCAST_BASE + 4*0xEA) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_RULE_CTRL_4 (JS_PMA0_BROADCAST_BASE + 4*0xEB) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_ALGORITHM_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xEC) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_TX_TRAIN_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xED) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_ADJ_INTERVAL (JS_PMA0_BROADCAST_BASE + 4*0xEE) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_RX_REQ_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xEF) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_RX_TRAIN_CTRL (JS_PMA0_BROADCAST_BASE + 4*0xF0) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_RX_RESET_CYCLE (JS_PMA0_BROADCAST_BASE + 4*0xF1) //Attributes : RW +#define JS_PMA0_BROADCAST_RPCS_KTR_STATUS (JS_PMA0_BROADCAST_BASE + 4*0xF2) //Attributes : RO +#define JS_PMA0_BROADCAST_EQ_FSM (JS_PMA0_BROADCAST_BASE + 4*0xF3) //Attributes : RO +#define JS_PMA0_BROADCAST_ETH_RX_LOS (JS_PMA0_BROADCAST_BASE + 4*0xF4) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_PRESET_C0 (JS_PMA0_BROADCAST_BASE + 4*0xF5) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_PRESET_CN1 (JS_PMA0_BROADCAST_BASE + 4*0xF6) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_PRESET_CP1 (JS_PMA0_BROADCAST_BASE + 4*0xF7) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_SUCC_MASK (JS_PMA0_BROADCAST_BASE + 4*0xF8) //Attributes : RW +#define JS_PMA0_BROADCAST_PMA_COM_SCRATCH (JS_PMA0_BROADCAST_BASE + 4*0xff) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY0 (JS_PMA0_BROADCAST_BASE + 4*0x100) //Attributes : RO_EXT_L +#define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY1 (JS_PMA0_BROADCAST_BASE + 4*0x101) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY2 (JS_PMA0_BROADCAST_BASE + 4*0x102) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY3 (JS_PMA0_BROADCAST_BASE + 4*0x103) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY4 (JS_PMA0_BROADCAST_BASE + 4*0x104) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY5 (JS_PMA0_BROADCAST_BASE + 4*0x105) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY6 (JS_PMA0_BROADCAST_BASE + 4*0x106) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY7 (JS_PMA0_BROADCAST_BASE + 4*0x107) //Attributes : RO_EXT_H +#define JS_PMA0_BROADCAST_EQ_TX_FSM_HISTORY_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x108) //Attributes : RW +#define JS_PMA0_BROADCAST_EQ_RX_FSM_HISTORY0 (JS_PMA0_BROADCAST_BASE + 4*0x109) //Attributes : RO_EXT_L +#define JS_PMA0_BROADCAST_EQ_RX_FSM_HISTORY1 (JS_PMA0_BROADCAST_BASE + 4*0x10A) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_EQ_RX_FSM_HISTORY2 (JS_PMA0_BROADCAST_BASE + 4*0x10B) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_EQ_RX_FSM_HISTORY3 (JS_PMA0_BROADCAST_BASE + 4*0x10C) //Attributes : RO_EXT_H +#define JS_PMA0_BROADCAST_EQ_RX_FSM_HISTORY_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x10D) //Attributes : RW +#define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY0 (JS_PMA0_BROADCAST_BASE + 4*0x110) //Attributes : RO_EXT_L +#define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY1 (JS_PMA0_BROADCAST_BASE + 4*0x111) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY2 (JS_PMA0_BROADCAST_BASE + 4*0x112) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY3 (JS_PMA0_BROADCAST_BASE + 4*0x113) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY4 (JS_PMA0_BROADCAST_BASE + 4*0x114) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY5 (JS_PMA0_BROADCAST_BASE + 4*0x115) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY6 (JS_PMA0_BROADCAST_BASE + 4*0x116) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY7 (JS_PMA0_BROADCAST_BASE + 4*0x117) //Attributes : RO_EXT_H +#define JS_PMA0_BROADCAST_TX_EQ_MAIN_HISTORY_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x118) //Attributes : RW +#define JS_PMA0_BROADCAST_RX_TXMAIN_DIR_HISTORY0 (JS_PMA0_BROADCAST_BASE + 4*0x119) //Attributes : RO_EXT_L +#define JS_PMA0_BROADCAST_RX_TXMAIN_DIR_HISTORY1 (JS_PMA0_BROADCAST_BASE + 4*0x11A) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_RX_TXMAIN_DIR_HISTORY2 (JS_PMA0_BROADCAST_BASE + 4*0x11B) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_RX_TXMAIN_DIR_HISTORY3 (JS_PMA0_BROADCAST_BASE + 4*0x11C) //Attributes : RO_EXT_H +#define JS_PMA0_BROADCAST_RX_TXMAIN_DIR_HISTORY_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x11D) //Attributes : RW +#define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY0 (JS_PMA0_BROADCAST_BASE + 4*0x120) //Attributes : RO_EXT_L +#define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY1 (JS_PMA0_BROADCAST_BASE + 4*0x121) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY2 (JS_PMA0_BROADCAST_BASE + 4*0x122) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY3 (JS_PMA0_BROADCAST_BASE + 4*0x123) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY4 (JS_PMA0_BROADCAST_BASE + 4*0x124) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY5 (JS_PMA0_BROADCAST_BASE + 4*0x125) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY6 (JS_PMA0_BROADCAST_BASE + 4*0x126) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY7 (JS_PMA0_BROADCAST_BASE + 4*0x127) //Attributes : RO_EXT_H +#define JS_PMA0_BROADCAST_TX_EQ_POST_HISTORY_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x128) //Attributes : RW +#define JS_PMA0_BROADCAST_RX_TXPOST_DIR_HISTORY0 (JS_PMA0_BROADCAST_BASE + 4*0x129) //Attributes : RO_EXT_L +#define JS_PMA0_BROADCAST_RX_TXPOST_DIR_HISTORY1 (JS_PMA0_BROADCAST_BASE + 4*0x12A) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_RX_TXPOST_DIR_HISTORY2 (JS_PMA0_BROADCAST_BASE + 4*0x12B) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_RX_TXPOST_DIR_HISTORY3 (JS_PMA0_BROADCAST_BASE + 4*0x12C) //Attributes : RO_EXT_H +#define JS_PMA0_BROADCAST_RX_TXPOST_DIR_HISTORY_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x12D) //Attributes : RW +#define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY0 (JS_PMA0_BROADCAST_BASE + 4*0x130) //Attributes : RO_EXT_L +#define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY1 (JS_PMA0_BROADCAST_BASE + 4*0x131) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY2 (JS_PMA0_BROADCAST_BASE + 4*0x132) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY3 (JS_PMA0_BROADCAST_BASE + 4*0x133) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY4 (JS_PMA0_BROADCAST_BASE + 4*0x134) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY5 (JS_PMA0_BROADCAST_BASE + 4*0x135) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY6 (JS_PMA0_BROADCAST_BASE + 4*0x136) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY7 (JS_PMA0_BROADCAST_BASE + 4*0x137) //Attributes : RO_EXT_H +#define JS_PMA0_BROADCAST_TX_EQ_PRE_HISTORY_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x138) //Attributes : RW +#define JS_PMA0_BROADCAST_RX_TXPRE_DIR_HISTORY0 (JS_PMA0_BROADCAST_BASE + 4*0x139) //Attributes : RO_EXT_L +#define JS_PMA0_BROADCAST_RX_TXPRE_DIR_HISTORY1 (JS_PMA0_BROADCAST_BASE + 4*0x13A) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_RX_TXPRE_DIR_HISTORY2 (JS_PMA0_BROADCAST_BASE + 4*0x13B) //Attributes : RO_EXT +#define JS_PMA0_BROADCAST_RX_TXPRE_DIR_HISTORY3 (JS_PMA0_BROADCAST_BASE + 4*0x13C) //Attributes : RO_EXT_H +#define JS_PMA0_BROADCAST_RX_TXPRE_DIR_HISTORY_CTRL (JS_PMA0_BROADCAST_BASE + 4*0x13D) //Attributes : RW + +//The PMA COMMON Register +#define JS_PMA0_MPLLA_PARAM1 (JS_PMA0_COMMON_BASE + 4*0x00) //Attributes : RW +#define JS_PMA0_MPLLA_PARAM2 (JS_PMA0_COMMON_BASE + 4*0x01) //Attributes : RW +#define JS_PMA0_MPLLA_PARAM3 (JS_PMA0_COMMON_BASE + 4*0x02) //Attributes : RW +#define JS_PMA0_MPLLA_PARAM4 (JS_PMA0_COMMON_BASE + 4*0x03) //Attributes : RW +#define JS_PMA0_MPLLA_PARAM5 (JS_PMA0_COMMON_BASE + 4*0x04) //Attributes : RW +#define JS_PMA0_MPLLA_PARAM6 (JS_PMA0_COMMON_BASE + 4*0x05) //Attributes : RW +#define JS_PMA0_MPLLA_FORCE_EN (JS_PMA0_COMMON_BASE + 4*0x06) //Attributes : RW +#define JS_PMA0_MPLLA_FORCE_ACK (JS_PMA0_COMMON_BASE + 4*0x07) //Attributes : RO +#define JS_PMA0_MPLLB_PARAM1 (JS_PMA0_COMMON_BASE + 4*0x08) //Attributes : RW +#define JS_PMA0_MPLLB_PARAM2 (JS_PMA0_COMMON_BASE + 4*0x09) //Attributes : RW +#define JS_PMA0_MPLLB_PARAM3 (JS_PMA0_COMMON_BASE + 4*0x0A) //Attributes : RW +#define JS_PMA0_MPLLB_PARAM4 (JS_PMA0_COMMON_BASE + 4*0x0B) //Attributes : RW +#define JS_PMA0_MPLLB_PARAM5 (JS_PMA0_COMMON_BASE + 4*0x0C) //Attributes : RW +#define JS_PMA0_MPLLB_PARAM6 (JS_PMA0_COMMON_BASE + 4*0x0D) //Attributes : RW +#define JS_PMA0_MPLLB_FORCE_EN (JS_PMA0_COMMON_BASE + 4*0x0E) //Attributes : RW +#define JS_PMA0_MPLLB_FORCE_ACK (JS_PMA0_COMMON_BASE + 4*0x0F) //Attributes : RO +#define JS_PMA0_SUP_MISC (JS_PMA0_COMMON_BASE + 4*0x16) //Attributes : RW +#define JS_PMA0_MPLLA_FRAC_CTRL1 (JS_PMA0_COMMON_BASE + 4*0x17) //Attributes : RW +#define JS_PMA0_MPLLA_FRAC_CTRL2 (JS_PMA0_COMMON_BASE + 4*0x18) //Attributes : RW +#define JS_PMA0_MPLLA_FRAC_CTRL3 (JS_PMA0_COMMON_BASE + 4*0x19) //Attributes : RW +#define JS_PMA0_MPLLA_FRAC_CTRL4 (JS_PMA0_COMMON_BASE + 4*0x1A) //Attributes : RW +#define JS_PMA0_MPLLA_SSC_CTRL1 (JS_PMA0_COMMON_BASE + 4*0x1B) //Attributes : RW +#define JS_PMA0_MPLLA_SSC_CTRL2 (JS_PMA0_COMMON_BASE + 4*0x1C) //Attributes : RW_EXT_L +#define JS_PMA0_MPLLA_SSC_CTRL3 (JS_PMA0_COMMON_BASE + 4*0x1D) //Attributes : RW_EXT_H +#define JS_PMA0_MPLLA_SSC_CTRL4 (JS_PMA0_COMMON_BASE + 4*0x1E) //Attributes : RW +#define JS_PMA0_MPLLA_SSC_CTRL5 (JS_PMA0_COMMON_BASE + 4*0x1F) //Attributes : RW_EXT_L +#define JS_PMA0_MPLLA_SSC_CTRL6 (JS_PMA0_COMMON_BASE + 4*0x20) //Attributes : RW_EXT_H +#define JS_PMA0_MPLLB_FRAC_CTRL1 (JS_PMA0_COMMON_BASE + 4*0x21) //Attributes : RW +#define JS_PMA0_MPLLB_FRAC_CTRL2 (JS_PMA0_COMMON_BASE + 4*0x22) //Attributes : RW +#define JS_PMA0_MPLLB_FRAC_CTRL3 (JS_PMA0_COMMON_BASE + 4*0x23) //Attributes : RW +#define JS_PMA0_MPLLB_FRAC_CTRL4 (JS_PMA0_COMMON_BASE + 4*0x24) //Attributes : RW +#define JS_PMA0_MPLLB_SSC_CTRL1 (JS_PMA0_COMMON_BASE + 4*0x25) //Attributes : RW +#define JS_PMA0_MPLLB_SSC_CTRL2 (JS_PMA0_COMMON_BASE + 4*0x26) //Attributes : RW_EXT_L +#define JS_PMA0_MPLLB_SSC_CTRL3 (JS_PMA0_COMMON_BASE + 4*0x27) //Attributes : RW_EXT_H +#define JS_PMA0_MPLLB_SSC_CTRL4 (JS_PMA0_COMMON_BASE + 4*0x28) //Attributes : RW +#define JS_PMA0_MPLLB_SSC_CTRL5 (JS_PMA0_COMMON_BASE + 4*0x29) //Attributes : RW_EXT_L +#define JS_PMA0_MPLLB_SSC_CTRL6 (JS_PMA0_COMMON_BASE + 4*0x2A) //Attributes : RW_EXT_H +#define JS_PMA0_MPLLA_RECAL_CTRL (JS_PMA0_COMMON_BASE + 4*0x2B) //Attributes : RW +#define JS_PMA0_MPLLB_RECAL_CTRL (JS_PMA0_COMMON_BASE + 4*0x2C) //Attributes : RW +#define JS_PMA0_MPLL_CTRL_MUX (JS_PMA0_COMMON_BASE + 4*0x2D) //Attributes : RW +#define JS_PMA0_POWER_SUPPLY_SEL (JS_PMA0_COMMON_BASE + 4*0x30) //Attributes : RW +#define JS_PMA0_PHY_RESET (JS_PMA0_COMMON_BASE + 4*0x31) //Attributes : RW +#define JS_PMA0_REF_CLK_CTRL (JS_PMA0_COMMON_BASE + 4*0x40) //Attributes : RW +#define JS_PMA0_REFA_CLK_CTRL1 (JS_PMA0_COMMON_BASE + 4*0x41) //Attributes : RW +#define JS_PMA0_REFA_CLK_CTRL2 (JS_PMA0_COMMON_BASE + 4*0x42) //Attributes : RW +#define JS_PMA0_REFA_CLK_STATUS (JS_PMA0_COMMON_BASE + 4*0x43) //Attributes : RO +#define JS_PMA0_REFB_CLK_CTRL1 (JS_PMA0_COMMON_BASE + 4*0x44) //Attributes : RW +#define JS_PMA0_REFB_CLK_CTRL2 (JS_PMA0_COMMON_BASE + 4*0x45) //Attributes : RW +#define JS_PMA0_REFB_CLK_STATUS (JS_PMA0_COMMON_BASE + 4*0x46) //Attributes : RO +#define JS_PMA0_REF_CLK_MUX (JS_PMA0_COMMON_BASE + 4*0x47) //Attributes : RW +#define JS_PMA0_RES_ACK_IN (JS_PMA0_COMMON_BASE + 4*0x50) //Attributes : RW +#define JS_PMA0_RES_ACK_OUT (JS_PMA0_COMMON_BASE + 4*0x51) //Attributes : RO +#define JS_PMA0_RES_REQ_IN (JS_PMA0_COMMON_BASE + 4*0x52) //Attributes : RW +#define JS_PMA0_RES_REQ_OUT (JS_PMA0_COMMON_BASE + 4*0x53) //Attributes : RO +#define JS_PMA0_RTUNE_REQ (JS_PMA0_COMMON_BASE + 4*0x54) //Attributes : RW +#define JS_PMA0_RTUNE_ACK (JS_PMA0_COMMON_BASE + 4*0x55) //Attributes : RO +#define JS_PMA0_RTUNE_CTRL1 (JS_PMA0_COMMON_BASE + 4*0x56) //Attributes : RW +#define JS_PMA0_RTUNE_CTRL2 (JS_PMA0_COMMON_BASE + 4*0x57) //Attributes : RW +#define JS_PMA0_RTUNE_CTRL3 (JS_PMA0_COMMON_BASE + 4*0x58) //Attributes : RW +#define JS_PMA0_RX_BIAS_CURRENT_CTRL (JS_PMA0_COMMON_BASE + 4*0x59) //Attributes : RW +#define JS_PMA0_CR_PARA_SEL (JS_PMA0_COMMON_BASE + 4*0x90) //Attributes : RW +#define JS_PMA0_POWER_GATING_SIGNAL1 (JS_PMA0_COMMON_BASE + 4*0x60) //Attributes : RW +#define JS_PMA0_POWER_GATING_SIGNAL2 (JS_PMA0_COMMON_BASE + 4*0x61) //Attributes : RO +#define JS_PMA0_POWER_GATING_SIGNAL3 (JS_PMA0_COMMON_BASE + 4*0x62) //Attributes : RW +#define JS_PMA0_SRAM_CTRL (JS_PMA0_COMMON_BASE + 4*0x68) //Attributes : RW +#define JS_PMA0_SRAM_STATUS (JS_PMA0_COMMON_BASE + 4*0x69) //Attributes : RO +#define JS_PMA0_SRIO_RST_REQ (JS_PMA0_COMMON_BASE + 4*0x6A) //Attributes : RO +#define JS_PMA0_SRIO_GEN3_EN (JS_PMA0_COMMON_BASE + 4*0x6C) //Attributes : RW +#define JS_PMA0_SRIO_RATE_OUT (JS_PMA0_COMMON_BASE + 4*0x6D) //Attributes : RW +#define JS_PMA0_CPRI_RST_REQ (JS_PMA0_COMMON_BASE + 4*0x70) //Attributes : RW +#define JS_PMA0_CPRI_RX_LOS (JS_PMA0_COMMON_BASE + 4*0x71) //Attributes : RW +#define JS_PMA0_CPRI_SIGNAL_OK (JS_PMA0_COMMON_BASE + 4*0x72) //Attributes : RW +#define JS_PMA0_CPRI_ENERGY_DET (JS_PMA0_COMMON_BASE + 4*0x73) //Attributes : RW +#define JS_PMA0_CPRI_SIGDET (JS_PMA0_COMMON_BASE + 4*0x74) //Attributes : RW +#define JS_PMA0_CPRI_PCS_STATUS (JS_PMA0_COMMON_BASE + 4*0x75) //Attributes : RO +#define JS_PMA0_CPRI_PCS_STATUS_CTRL (JS_PMA0_COMMON_BASE + 4*0x76) //Attributes : RW +#define JS_PMA0_ETH_ENERGY_DET (JS_PMA0_COMMON_BASE + 4*0x80) //Attributes : RW +#define JS_PMA0_ETH_SPEED_CTRL (JS_PMA0_COMMON_BASE + 4*0x81) //Attributes : RO +#define JS_PMA0_TX_CLK_SEL (JS_PMA0_COMMON_BASE + 4*0xF0) //Attributes : RW +#define JS_PMA0_RPCS_TX_CLK_SEL (JS_PMA0_COMMON_BASE + 4*0xF1) //Attributes : RW +#define JS_PMA0_RPCS_RX_CLK_SEL (JS_PMA0_COMMON_BASE + 4*0xF2) //Attributes : RW +#define JS_PMA0_PMA_COM_SCRATCH (JS_PMA0_COMMON_BASE + 4*0xff) //Attributes : RW + +//The PMA PCS Register +#define JS_PMA0_PCS_SOFT_RESET (JS_PMA0_PCS_BASE + 4*0x00) //Attributes : RW +#define JS_PMA0_PCS_LOOPBACK_CTRL (JS_PMA0_PCS_BASE + 4*0x04) //Attributes : RW +#define JS_PMA0_PCS_PRBS_UDP_SEND (JS_PMA0_PCS_BASE + 4*0x05) //Attributes : RW +#define JS_PMA0_PCS_PRBS_SEND_ERRINS (JS_PMA0_PCS_BASE + 4*0x06) //Attributes : RW +#define JS_PMA0_PCS_TXUDP_0 (JS_PMA0_PCS_BASE + 4*0x07) //Attributes : RW_EXT_L +#define JS_PMA0_PCS_TXUDP_1 (JS_PMA0_PCS_BASE + 4*0x08) //Attributes : RW_EXT +#define JS_PMA0_PCS_TXUDP_2 (JS_PMA0_PCS_BASE + 4*0x09) //Attributes : RW_EXT +#define JS_PMA0_PCS_TXUDP_3 (JS_PMA0_PCS_BASE + 4*0x0A) //Attributes : RW_EXT +#define JS_PMA0_PCS_TXUDP_4 (JS_PMA0_PCS_BASE + 4*0x0B) //Attributes : RW_EXT_H +#define JS_PMA0_PCS_PRBS_UDP_CHK (JS_PMA0_PCS_BASE + 4*0x10) //Attributes : RW +#define JS_PMA0_PCS_RXUDP_0 (JS_PMA0_PCS_BASE + 4*0x11) //Attributes : RW_EXT_L +#define JS_PMA0_PCS_RXUDP_1 (JS_PMA0_PCS_BASE + 4*0x12) //Attributes : RW_EXT +#define JS_PMA0_PCS_RXUDP_2 (JS_PMA0_PCS_BASE + 4*0x13) //Attributes : RW_EXT +#define JS_PMA0_PCS_RXUDP_3 (JS_PMA0_PCS_BASE + 4*0x14) //Attributes : RW_EXT +#define JS_PMA0_PCS_RXUDP_4 (JS_PMA0_PCS_BASE + 4*0x15) //Attributes : RW_EXT_H +#define JS_PMA0_PCS_RXPRBS_ERRCNT_L0 (JS_PMA0_PCS_BASE + 4*0x16) //Attributes : RO +#define JS_PMA0_PCS_RXPRBS_ERRCNT_L1 (JS_PMA0_PCS_BASE + 4*0x17) //Attributes : RO +#define JS_PMA0_PCS_RXPRBS_ERRCNT_L2 (JS_PMA0_PCS_BASE + 4*0x18) //Attributes : RO +#define JS_PMA0_PCS_RXPRBS_ERRCNT_L3 (JS_PMA0_PCS_BASE + 4*0x19) //Attributes : RO +#define JS_PMA0_PCS_NELP_FIFO_STATUS (JS_PMA0_PCS_BASE + 4*0x20) //Attributes : RO +#define JS_PMA0_PCS_FELP_FIFO_STATUS (JS_PMA0_PCS_BASE + 4*0x21) //Attributes : RO +#define JS_PMA0_PCS_BIT_REV_CTRL (JS_PMA0_PCS_BASE + 4*0x22) //Attributes : RW +#define JS_PMA0_PCS_SOFT_PON_RST (JS_PMA0_PCS_BASE + 4*0xfe) //Attributes : RW +#define JS_PMA0_PCS_PCS_SCRATCH (JS_PMA0_PCS_BASE + 4*0xff) //Attributes : RW + +//------------------------JS1 SUBSYSTEM -------------------------// +//The PMA Lane Config Base Addr +#define JECS_PMA1_LANE0_BASE JECS_PMA1_CFG + 0x10000*4 +#define JECS_PMA1_LANE1_BASE JECS_PMA1_CFG + 0x10800*4 +#define JECS_PMA1_LANE2_BASE JECS_PMA1_CFG + 0x11000*4 +#define JECS_PMA1_LANE3_BASE JECS_PMA1_CFG + 0x11800*4 +#define JECS_PMA1_BROADCAST_BASE JECS_PMA1_CFG + 0x12000*4 +//The PMA COMMON Base Addr +#define JECS_PMA1_COMMON_BASE JECS_PMA1_CFG + 0x14000*4 + +//The PMA PCS Addr +#define JECS_PMA1_PCS_BASE JECS_PMA1_CFG + 0x18000*4 + + +//The PMA Lane Config Register +#define JECS_PMA1_LANE0_PMA_LOOPBACK_CTRL (JECS_PMA1_LANE0_BASE + 4*0x00) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_REQ (JECS_PMA1_LANE0_BASE + 4*0x01) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_REQ_ACK (JECS_PMA1_LANE0_BASE + 4*0x02) //Attributes : RO +#define JECS_PMA1_LANE0_RECEIVER_REQ_PARAM2 (JECS_PMA1_LANE0_BASE + 4*0x03) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_REQ_PARAM3 (JECS_PMA1_LANE0_BASE + 4*0x04) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_REQ_PARAM4 (JECS_PMA1_LANE0_BASE + 4*0x05) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_REQ_PARAM5 (JECS_PMA1_LANE0_BASE + 4*0x06) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_REQ_PARAM6 (JECS_PMA1_LANE0_BASE + 4*0x07) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_REQ_PARAM7 (JECS_PMA1_LANE0_BASE + 4*0x08) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_REQ_PARAM8 (JECS_PMA1_LANE0_BASE + 4*0x09) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_REQ_PARAM9 (JECS_PMA1_LANE0_BASE + 4*0x0A) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_REQ_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x0B) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ (JECS_PMA1_LANE0_BASE + 4*0x10) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK (JECS_PMA1_LANE0_BASE + 4*0x11) //Attributes : RO +#define JECS_PMA1_LANE0_RECEIVER_ADAPT_DIR (JECS_PMA1_LANE0_BASE + 4*0x12) //Attributes : RO +#define JECS_PMA1_LANE0_RECEIVER_ADAPT_SETTING (JECS_PMA1_LANE0_BASE + 4*0x13) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_ADAPT_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x14) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN (JECS_PMA1_LANE0_BASE + 4*0x20) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_DATAPATH_SETTING1 (JECS_PMA1_LANE0_BASE + 4*0x21) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_DATAPATH_SETTING2 (JECS_PMA1_LANE0_BASE + 4*0x22) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_DATAPATH_SETTING3 (JECS_PMA1_LANE0_BASE + 4*0x23) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_DATAPATH_STATUS1 (JECS_PMA1_LANE0_BASE + 4*0x24) //Attributes : RO +#define JECS_PMA1_LANE0_RECEIVER_DATAPATH_STATUS2 (JECS_PMA1_LANE0_BASE + 4*0x25) //Attributes : RO +#define JECS_PMA1_LANE0_RECEIVER_DATAPATH_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x26) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_RESET (JECS_PMA1_LANE0_BASE + 4*0x30) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_CONTROL (JECS_PMA1_LANE0_BASE + 4*0x31) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_CONTROL_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x32) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_RECAL_CTRL (JECS_PMA1_LANE0_BASE + 4*0x40) //Attributes : RW +#define JECS_PMA1_LANE0_RECEIVER_RECAL_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x41) //Attributes : RW +#define JECS_PMA1_LANE0_TRANSMITTER_REQ (JECS_PMA1_LANE0_BASE + 4*0x50) //Attributes : RW +#define JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK (JECS_PMA1_LANE0_BASE + 4*0x51) //Attributes : RO +#define JECS_PMA1_LANE0_TRANSMITTER_REQ_PARAM1 (JECS_PMA1_LANE0_BASE + 4*0x52) //Attributes : RW +#define JECS_PMA1_LANE0_TRANSMITTER_REQ_PARAM2 (JECS_PMA1_LANE0_BASE + 4*0x53) //Attributes : RW +#define JECS_PMA1_LANE0_TRANSMITTER_REQ_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x55) //Attributes : RW +#define JECS_PMA1_LANE0_TRANSMITTER_DATAPATH_EN (JECS_PMA1_LANE0_BASE + 4*0x60) //Attributes : RW +#define JECS_PMA1_LANE0_TRANSMITTER_DATAPATH_CLKRDY (JECS_PMA1_LANE0_BASE + 4*0x61) //Attributes : RW +#define JECS_PMA1_LANE0_TRANSMITTER_DATAPATH_SETTING (JECS_PMA1_LANE0_BASE + 4*0x62) //Attributes : RW +#define JECS_PMA1_LANE0_TRANSMITTER_DATAPATH_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x63) //Attributes : RW +#define JECS_PMA1_LANE0_TRANSMITTER_CONTROL1 (JECS_PMA1_LANE0_BASE + 4*0x70) //Attributes : RW +#define JECS_PMA1_LANE0_TRANSMITTER_CONTROL2 (JECS_PMA1_LANE0_BASE + 4*0x71) //Attributes : RW +#define JECS_PMA1_LANE0_TRANSMITTER_CONTROL_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x72) //Attributes : RW +#define JECS_PMA1_LANE0_TRANSMITTER_EQ1 (JECS_PMA1_LANE0_BASE + 4*0x80) //Attributes : RW +#define JECS_PMA1_LANE0_TRANSMITTER_EQ2 (JECS_PMA1_LANE0_BASE + 4*0x81) //Attributes : RW +#define JECS_PMA1_LANE0_TRANSMITTER_EQ3 (JECS_PMA1_LANE0_BASE + 4*0x82) //Attributes : RW +#define JECS_PMA1_LANE0_TRANSMITTER_EQ_MUX_CTRL (JECS_PMA1_LANE0_BASE + 4*0x83) //Attributes : RW +#define JECS_PMA1_LANE0_CONTEXT_RESTORE_CTRL1 (JECS_PMA1_LANE0_BASE + 4*0x90) //Attributes : RW +#define JECS_PMA1_LANE0_CONTEXT_RESTORE_CTRL2 (JECS_PMA1_LANE0_BASE + 4*0x91) //Attributes : RW +#define JECS_PMA1_LANE0_CONTEXT_RESTORE_CTRL3 (JECS_PMA1_LANE0_BASE + 4*0x92) //Attributes : RW +#define JECS_PMA1_LANE0_CONTEXT_RESTORE_CTRL4 (JECS_PMA1_LANE0_BASE + 4*0x93) //Attributes : RW +#define JECS_PMA1_LANE0_CONTEXT_RESTORE_MUX (JECS_PMA1_LANE0_BASE + 4*0x94) //Attributes : RW +#define JECS_PMA1_LANE0_LANE_REFCLK_SEL (JECS_PMA1_LANE0_BASE + 4*0xA0) //Attributes : RW +#define JECS_PMA1_LANE0_ETH_CLK_CTRL (JECS_PMA1_LANE0_BASE + 4*0xB0) //Attributes : RW +#define JECS_PMA1_LANE0_ETH_CLK_CTRL_MUX (JECS_PMA1_LANE0_BASE + 4*0xB1) //Attributes : RW +#define JECS_PMA1_LANE0_RX_ADAPT_CTRL (JECS_PMA1_LANE0_BASE + 4*0xC0) //Attributes : RW +#define JECS_PMA1_LANE0_RX_DCC_CTRL (JECS_PMA1_LANE0_BASE + 4*0xC1) //Attributes : RW +#define JECS_PMA1_LANE0_RX_EQ_CTRL1 (JECS_PMA1_LANE0_BASE + 4*0xC2) //Attributes : RW +#define JECS_PMA1_LANE0_RX_EQ_CTRL2 (JECS_PMA1_LANE0_BASE + 4*0xC3) //Attributes : RW +#define JECS_PMA1_LANE0_RX_MARGIN_CTRL (JECS_PMA1_LANE0_BASE + 4*0xC4) //Attributes : RW +#define JECS_PMA1_LANE0_RX_MARGIN_ERROR (JECS_PMA1_LANE0_BASE + 4*0xC5) //Attributes : RO +#define JECS_PMA1_LANE0_RECV_REQUEST_CTRL_MUX (JECS_PMA1_LANE0_BASE + 4*0xC6) //Attributes : RW +#define JECS_PMA1_LANE0_RX_COARSE_ADAPT_CTRL (JECS_PMA1_LANE0_BASE + 4*0xC8) //Attributes : RW +#define JECS_PMA1_LANE0_RX_COARSE_ADAPT_CTRL_MUX (JECS_PMA1_LANE0_BASE + 4*0xC9) //Attributes : RW +#define JECS_PMA1_LANE0_RX_DIV_CLK_CTRL (JECS_PMA1_LANE0_BASE + 4*0xCA) //Attributes : RW +#define JECS_PMA1_LANE0_TX_DIV_CLK_CTRL (JECS_PMA1_LANE0_BASE + 4*0xCB) //Attributes : RW +#define JECS_PMA1_LANE0_MULTI_CLK_CTRL_MUX (JECS_PMA1_LANE0_BASE + 4*0xCC) //Attributes : RW +#define JECS_PMA1_LANE0_TRANS_REQ_CTRL1 (JECS_PMA1_LANE0_BASE + 4*0xD0) //Attributes : RW +#define JECS_PMA1_LANE0_TRANS_REQ_CTRL2 (JECS_PMA1_LANE0_BASE + 4*0xD1) //Attributes : RW +#define JECS_PMA1_LANE0_TRANS_REQ_CTRL3 (JECS_PMA1_LANE0_BASE + 4*0xD2) //Attributes : RW +#define JECS_PMA1_LANE0_TRANS_REQ_CTRL4 (JECS_PMA1_LANE0_BASE + 4*0xD3) //Attributes : RW +#define JECS_PMA1_LANE0_TRANS_REQ_CTRL5 (JECS_PMA1_LANE0_BASE + 4*0xD4) //Attributes : RW +#define JECS_PMA1_LANE0_TRANS_REQ_MUX (JECS_PMA1_LANE0_BASE + 4*0xD5) //Attributes : RW +#define JECS_PMA1_LANE0_TRANS_INTERFACE_CTRL (JECS_PMA1_LANE0_BASE + 4*0xD6) //Attributes : RW +#define JECS_PMA1_LANE0_TRANS_INTERFACE_MUX (JECS_PMA1_LANE0_BASE + 4*0xD7) //Attributes : RW +#define JECS_PMA1_LANE0_TRANS_MASTER_PLL_STATE (JECS_PMA1_LANE0_BASE + 4*0xD8) //Attributes : RW +#define JECS_PMA1_LANE0_TRANS_PLL_STATE (JECS_PMA1_LANE0_BASE + 4*0xD9) //Attributes : RO +#define JECS_PMA1_LANE0_PLL_STATE_MUX (JECS_PMA1_LANE0_BASE + 4*0xDA) //Attributes : RW +#define JECS_PMA1_LANE0_RX_VALID_PHY (JECS_PMA1_LANE0_BASE + 4*0xDF) //Attributes : RO +#define JECS_PMA1_LANE0_RX_VALID_MUX (JECS_PMA1_LANE0_BASE + 4*0xE0) //Attributes : RW +#define JECS_PMA1_LANE0_RX_SRIO_SIGDET_MUX (JECS_PMA1_LANE0_BASE + 4*0xE1) //Attributes : RW +#define JECS_PMA1_LANE0_SRIO_DEGRADED (JECS_PMA1_LANE0_BASE + 4*0xE2) //Attributes : RW +#define JECS_PMA1_LANE0_SRIO_RETRAIN (JECS_PMA1_LANE0_BASE + 4*0xE3) //Attributes : RW +#define JECS_PMA1_LANE0_SRIO_SHORT_RUN (JECS_PMA1_LANE0_BASE + 4*0xE4) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_INIT_C0 (JECS_PMA1_LANE0_BASE + 4*0xE5) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_INIT_CN1 (JECS_PMA1_LANE0_BASE + 4*0xE6) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_INIT_CP1 (JECS_PMA1_LANE0_BASE + 4*0xE7) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_RULE_CTRL_1 (JECS_PMA1_LANE0_BASE + 4*0xE8) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_RULE_CTRL_2 (JECS_PMA1_LANE0_BASE + 4*0xE9) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_RULE_CTRL_3 (JECS_PMA1_LANE0_BASE + 4*0xEA) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_RULE_CTRL_4 (JECS_PMA1_LANE0_BASE + 4*0xEB) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_ALGORITHM_CTRL (JECS_PMA1_LANE0_BASE + 4*0xEC) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_TX_TRAIN_CTRL (JECS_PMA1_LANE0_BASE + 4*0xED) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_ADJ_INTERVAL (JECS_PMA1_LANE0_BASE + 4*0xEE) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_RX_REQ_CTRL (JECS_PMA1_LANE0_BASE + 4*0xEF) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_RX_TRAIN_CTRL (JECS_PMA1_LANE0_BASE + 4*0xF0) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_RX_RESET_CYCLE (JECS_PMA1_LANE0_BASE + 4*0xF1) //Attributes : RW +#define JECS_PMA1_LANE0_RPCS_KTR_STATUS (JECS_PMA1_LANE0_BASE + 4*0xF2) //Attributes : RO +#define JECS_PMA1_LANE0_EQ_FSM (JECS_PMA1_LANE0_BASE + 4*0xF3) //Attributes : RO +#define JECS_PMA1_LANE0_ETH_RX_LOS (JECS_PMA1_LANE0_BASE + 4*0xF4) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_PRESET_C0 (JECS_PMA1_LANE0_BASE + 4*0xF5) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_PRESET_CN1 (JECS_PMA1_LANE0_BASE + 4*0xF6) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_PRESET_CP1 (JECS_PMA1_LANE0_BASE + 4*0xF7) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_SUCC_MASK (JECS_PMA1_LANE0_BASE + 4*0xF8) //Attributes : RW +#define JECS_PMA1_LANE0_PMA_COM_SCRATCH (JECS_PMA1_LANE0_BASE + 4*0xff) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY0 (JECS_PMA1_LANE0_BASE + 4*0x100) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY1 (JECS_PMA1_LANE0_BASE + 4*0x101) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY2 (JECS_PMA1_LANE0_BASE + 4*0x102) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY3 (JECS_PMA1_LANE0_BASE + 4*0x103) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY4 (JECS_PMA1_LANE0_BASE + 4*0x104) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY5 (JECS_PMA1_LANE0_BASE + 4*0x105) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY6 (JECS_PMA1_LANE0_BASE + 4*0x106) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY7 (JECS_PMA1_LANE0_BASE + 4*0x107) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE0_EQ_TX_FSM_HISTORY_CTRL (JECS_PMA1_LANE0_BASE + 4*0x108) //Attributes : RW +#define JECS_PMA1_LANE0_EQ_RX_FSM_HISTORY0 (JECS_PMA1_LANE0_BASE + 4*0x109) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE0_EQ_RX_FSM_HISTORY1 (JECS_PMA1_LANE0_BASE + 4*0x10A) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_EQ_RX_FSM_HISTORY2 (JECS_PMA1_LANE0_BASE + 4*0x10B) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_EQ_RX_FSM_HISTORY3 (JECS_PMA1_LANE0_BASE + 4*0x10C) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE0_EQ_RX_FSM_HISTORY_CTRL (JECS_PMA1_LANE0_BASE + 4*0x10D) //Attributes : RW +#define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY0 (JECS_PMA1_LANE0_BASE + 4*0x110) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY1 (JECS_PMA1_LANE0_BASE + 4*0x111) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY2 (JECS_PMA1_LANE0_BASE + 4*0x112) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY3 (JECS_PMA1_LANE0_BASE + 4*0x113) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY4 (JECS_PMA1_LANE0_BASE + 4*0x114) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY5 (JECS_PMA1_LANE0_BASE + 4*0x115) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY6 (JECS_PMA1_LANE0_BASE + 4*0x116) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY7 (JECS_PMA1_LANE0_BASE + 4*0x117) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE0_TX_EQ_MAIN_HISTORY_CTRL (JECS_PMA1_LANE0_BASE + 4*0x118) //Attributes : RW +#define JECS_PMA1_LANE0_RX_TXMAIN_DIR_HISTORY0 (JECS_PMA1_LANE0_BASE + 4*0x119) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE0_RX_TXMAIN_DIR_HISTORY1 (JECS_PMA1_LANE0_BASE + 4*0x11A) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_RX_TXMAIN_DIR_HISTORY2 (JECS_PMA1_LANE0_BASE + 4*0x11B) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_RX_TXMAIN_DIR_HISTORY3 (JECS_PMA1_LANE0_BASE + 4*0x11C) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE0_RX_TXMAIN_DIR_HISTORY_CTRL (JECS_PMA1_LANE0_BASE + 4*0x11D) //Attributes : RW +#define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY0 (JECS_PMA1_LANE0_BASE + 4*0x120) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY1 (JECS_PMA1_LANE0_BASE + 4*0x121) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY2 (JECS_PMA1_LANE0_BASE + 4*0x122) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY3 (JECS_PMA1_LANE0_BASE + 4*0x123) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY4 (JECS_PMA1_LANE0_BASE + 4*0x124) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY5 (JECS_PMA1_LANE0_BASE + 4*0x125) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY6 (JECS_PMA1_LANE0_BASE + 4*0x126) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY7 (JECS_PMA1_LANE0_BASE + 4*0x127) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE0_TX_EQ_POST_HISTORY_CTRL (JECS_PMA1_LANE0_BASE + 4*0x128) //Attributes : RW +#define JECS_PMA1_LANE0_RX_TXPOST_DIR_HISTORY0 (JECS_PMA1_LANE0_BASE + 4*0x129) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE0_RX_TXPOST_DIR_HISTORY1 (JECS_PMA1_LANE0_BASE + 4*0x12A) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_RX_TXPOST_DIR_HISTORY2 (JECS_PMA1_LANE0_BASE + 4*0x12B) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_RX_TXPOST_DIR_HISTORY3 (JECS_PMA1_LANE0_BASE + 4*0x12C) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE0_RX_TXPOST_DIR_HISTORY_CTRL (JECS_PMA1_LANE0_BASE + 4*0x12D) //Attributes : RW +#define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY0 (JECS_PMA1_LANE0_BASE + 4*0x130) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY1 (JECS_PMA1_LANE0_BASE + 4*0x131) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY2 (JECS_PMA1_LANE0_BASE + 4*0x132) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY3 (JECS_PMA1_LANE0_BASE + 4*0x133) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY4 (JECS_PMA1_LANE0_BASE + 4*0x134) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY5 (JECS_PMA1_LANE0_BASE + 4*0x135) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY6 (JECS_PMA1_LANE0_BASE + 4*0x136) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY7 (JECS_PMA1_LANE0_BASE + 4*0x137) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE0_TX_EQ_PRE_HISTORY_CTRL (JECS_PMA1_LANE0_BASE + 4*0x138) //Attributes : RW +#define JECS_PMA1_LANE0_RX_TXPRE_DIR_HISTORY0 (JECS_PMA1_LANE0_BASE + 4*0x139) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE0_RX_TXPRE_DIR_HISTORY1 (JECS_PMA1_LANE0_BASE + 4*0x13A) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_RX_TXPRE_DIR_HISTORY2 (JECS_PMA1_LANE0_BASE + 4*0x13B) //Attributes : RO_EXT +#define JECS_PMA1_LANE0_RX_TXPRE_DIR_HISTORY3 (JECS_PMA1_LANE0_BASE + 4*0x13C) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE0_RX_TXPRE_DIR_HISTORY_CTRL (JECS_PMA1_LANE0_BASE + 4*0x13D) //Attributes : RW + +#define JECS_PMA1_LANE1_PMA_LOOPBACK_CTRL (JECS_PMA1_LANE1_BASE + 4*0x00) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_REQ (JECS_PMA1_LANE1_BASE + 4*0x01) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_REQ_ACK (JECS_PMA1_LANE1_BASE + 4*0x02) //Attributes : RO +#define JECS_PMA1_LANE1_RECEIVER_REQ_PARAM2 (JECS_PMA1_LANE1_BASE + 4*0x03) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_REQ_PARAM3 (JECS_PMA1_LANE1_BASE + 4*0x04) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_REQ_PARAM4 (JECS_PMA1_LANE1_BASE + 4*0x05) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_REQ_PARAM5 (JECS_PMA1_LANE1_BASE + 4*0x06) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_REQ_PARAM6 (JECS_PMA1_LANE1_BASE + 4*0x07) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_REQ_PARAM7 (JECS_PMA1_LANE1_BASE + 4*0x08) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_REQ_PARAM8 (JECS_PMA1_LANE1_BASE + 4*0x09) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_REQ_PARAM9 (JECS_PMA1_LANE1_BASE + 4*0x0A) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_REQ_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x0B) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_ADAPT_REQ (JECS_PMA1_LANE1_BASE + 4*0x10) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_ADAPT_REQ_ACK (JECS_PMA1_LANE1_BASE + 4*0x11) //Attributes : RO +#define JECS_PMA1_LANE1_RECEIVER_ADAPT_DIR (JECS_PMA1_LANE1_BASE + 4*0x12) //Attributes : RO +#define JECS_PMA1_LANE1_RECEIVER_ADAPT_SETTING (JECS_PMA1_LANE1_BASE + 4*0x13) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_ADAPT_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x14) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_DATAPATH_EN (JECS_PMA1_LANE1_BASE + 4*0x20) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_DATAPATH_SETTING1 (JECS_PMA1_LANE1_BASE + 4*0x21) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_DATAPATH_SETTING2 (JECS_PMA1_LANE1_BASE + 4*0x22) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_DATAPATH_SETTING3 (JECS_PMA1_LANE1_BASE + 4*0x23) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_DATAPATH_STATUS1 (JECS_PMA1_LANE1_BASE + 4*0x24) //Attributes : RO +#define JECS_PMA1_LANE1_RECEIVER_DATAPATH_STATUS2 (JECS_PMA1_LANE1_BASE + 4*0x25) //Attributes : RO +#define JECS_PMA1_LANE1_RECEIVER_DATAPATH_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x26) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_RESET (JECS_PMA1_LANE1_BASE + 4*0x30) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_CONTROL (JECS_PMA1_LANE1_BASE + 4*0x31) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_CONTROL_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x32) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_RECAL_CTRL (JECS_PMA1_LANE1_BASE + 4*0x40) //Attributes : RW +#define JECS_PMA1_LANE1_RECEIVER_RECAL_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x41) //Attributes : RW +#define JECS_PMA1_LANE1_TRANSMITTER_REQ (JECS_PMA1_LANE1_BASE + 4*0x50) //Attributes : RW +#define JECS_PMA1_LANE1_TRANSMITTER_REQ_ACK (JECS_PMA1_LANE1_BASE + 4*0x51) //Attributes : RO +#define JECS_PMA1_LANE1_TRANSMITTER_REQ_PARAM1 (JECS_PMA1_LANE1_BASE + 4*0x52) //Attributes : RW +#define JECS_PMA1_LANE1_TRANSMITTER_REQ_PARAM2 (JECS_PMA1_LANE1_BASE + 4*0x53) //Attributes : RW +#define JECS_PMA1_LANE1_TRANSMITTER_REQ_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x55) //Attributes : RW +#define JECS_PMA1_LANE1_TRANSMITTER_DATAPATH_EN (JECS_PMA1_LANE1_BASE + 4*0x60) //Attributes : RW +#define JECS_PMA1_LANE1_TRANSMITTER_DATAPATH_CLKRDY (JECS_PMA1_LANE1_BASE + 4*0x61) //Attributes : RW +#define JECS_PMA1_LANE1_TRANSMITTER_DATAPATH_SETTING (JECS_PMA1_LANE1_BASE + 4*0x62) //Attributes : RW +#define JECS_PMA1_LANE1_TRANSMITTER_DATAPATH_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x63) //Attributes : RW +#define JECS_PMA1_LANE1_TRANSMITTER_CONTROL1 (JECS_PMA1_LANE1_BASE + 4*0x70) //Attributes : RW +#define JECS_PMA1_LANE1_TRANSMITTER_CONTROL2 (JECS_PMA1_LANE1_BASE + 4*0x71) //Attributes : RW +#define JECS_PMA1_LANE1_TRANSMITTER_CONTROL_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x72) //Attributes : RW +#define JECS_PMA1_LANE1_TRANSMITTER_EQ1 (JECS_PMA1_LANE1_BASE + 4*0x80) //Attributes : RW +#define JECS_PMA1_LANE1_TRANSMITTER_EQ2 (JECS_PMA1_LANE1_BASE + 4*0x81) //Attributes : RW +#define JECS_PMA1_LANE1_TRANSMITTER_EQ3 (JECS_PMA1_LANE1_BASE + 4*0x82) //Attributes : RW +#define JECS_PMA1_LANE1_TRANSMITTER_EQ_MUX_CTRL (JECS_PMA1_LANE1_BASE + 4*0x83) //Attributes : RW +#define JECS_PMA1_LANE1_CONTEXT_RESTORE_CTRL1 (JECS_PMA1_LANE1_BASE + 4*0x90) //Attributes : RW +#define JECS_PMA1_LANE1_CONTEXT_RESTORE_CTRL2 (JECS_PMA1_LANE1_BASE + 4*0x91) //Attributes : RW +#define JECS_PMA1_LANE1_CONTEXT_RESTORE_CTRL3 (JECS_PMA1_LANE1_BASE + 4*0x92) //Attributes : RW +#define JECS_PMA1_LANE1_CONTEXT_RESTORE_CTRL4 (JECS_PMA1_LANE1_BASE + 4*0x93) //Attributes : RW +#define JECS_PMA1_LANE1_CONTEXT_RESTORE_MUX (JECS_PMA1_LANE1_BASE + 4*0x94) //Attributes : RW +#define JECS_PMA1_LANE1_LANE_REFCLK_SEL (JECS_PMA1_LANE1_BASE + 4*0xA0) //Attributes : RW +#define JECS_PMA1_LANE1_ETH_CLK_CTRL (JECS_PMA1_LANE1_BASE + 4*0xB0) //Attributes : RW +#define JECS_PMA1_LANE1_ETH_CLK_CTRL_MUX (JECS_PMA1_LANE1_BASE + 4*0xB1) //Attributes : RW +#define JECS_PMA1_LANE1_RX_ADAPT_CTRL (JECS_PMA1_LANE1_BASE + 4*0xC0) //Attributes : RW +#define JECS_PMA1_LANE1_RX_DCC_CTRL (JECS_PMA1_LANE1_BASE + 4*0xC1) //Attributes : RW +#define JECS_PMA1_LANE1_RX_EQ_CTRL1 (JECS_PMA1_LANE1_BASE + 4*0xC2) //Attributes : RW +#define JECS_PMA1_LANE1_RX_EQ_CTRL2 (JECS_PMA1_LANE1_BASE + 4*0xC3) //Attributes : RW +#define JECS_PMA1_LANE1_RX_MARGIN_CTRL (JECS_PMA1_LANE1_BASE + 4*0xC4) //Attributes : RW +#define JECS_PMA1_LANE1_RX_MARGIN_ERROR (JECS_PMA1_LANE1_BASE + 4*0xC5) //Attributes : RO +#define JECS_PMA1_LANE1_RECV_REQUEST_CTRL_MUX (JECS_PMA1_LANE1_BASE + 4*0xC6) //Attributes : RW +#define JECS_PMA1_LANE1_RX_COARSE_ADAPT_CTRL (JECS_PMA1_LANE1_BASE + 4*0xC8) //Attributes : RW +#define JECS_PMA1_LANE1_RX_COARSE_ADAPT_CTRL_MUX (JECS_PMA1_LANE1_BASE + 4*0xC9) //Attributes : RW +#define JECS_PMA1_LANE1_RX_DIV_CLK_CTRL (JECS_PMA1_LANE1_BASE + 4*0xCA) //Attributes : RW +#define JECS_PMA1_LANE1_TX_DIV_CLK_CTRL (JECS_PMA1_LANE1_BASE + 4*0xCB) //Attributes : RW +#define JECS_PMA1_LANE1_MULTI_CLK_CTRL_MUX (JECS_PMA1_LANE1_BASE + 4*0xCC) //Attributes : RW +#define JECS_PMA1_LANE1_TRANS_REQ_CTRL1 (JECS_PMA1_LANE1_BASE + 4*0xD0) //Attributes : RW +#define JECS_PMA1_LANE1_TRANS_REQ_CTRL2 (JECS_PMA1_LANE1_BASE + 4*0xD1) //Attributes : RW +#define JECS_PMA1_LANE1_TRANS_REQ_CTRL3 (JECS_PMA1_LANE1_BASE + 4*0xD2) //Attributes : RW +#define JECS_PMA1_LANE1_TRANS_REQ_CTRL4 (JECS_PMA1_LANE1_BASE + 4*0xD3) //Attributes : RW +#define JECS_PMA1_LANE1_TRANS_REQ_CTRL5 (JECS_PMA1_LANE1_BASE + 4*0xD4) //Attributes : RW +#define JECS_PMA1_LANE1_TRANS_REQ_MUX (JECS_PMA1_LANE1_BASE + 4*0xD5) //Attributes : RW +#define JECS_PMA1_LANE1_TRANS_INTERFACE_CTRL (JECS_PMA1_LANE1_BASE + 4*0xD6) //Attributes : RW +#define JECS_PMA1_LANE1_TRANS_INTERFACE_MUX (JECS_PMA1_LANE1_BASE + 4*0xD7) //Attributes : RW +#define JECS_PMA1_LANE1_TRANS_MASTER_PLL_STATE (JECS_PMA1_LANE1_BASE + 4*0xD8) //Attributes : RW +#define JECS_PMA1_LANE1_TRANS_PLL_STATE (JECS_PMA1_LANE1_BASE + 4*0xD9) //Attributes : RO +#define JECS_PMA1_LANE1_PLL_STATE_MUX (JECS_PMA1_LANE1_BASE + 4*0xDA) //Attributes : RW +#define JECS_PMA1_LANE1_RX_VALID_PHY (JECS_PMA1_LANE1_BASE + 4*0xDF) //Attributes : RO +#define JECS_PMA1_LANE1_RX_VALID_MUX (JECS_PMA1_LANE1_BASE + 4*0xE0) //Attributes : RW +#define JECS_PMA1_LANE1_RX_SRIO_SIGDET_MUX (JECS_PMA1_LANE1_BASE + 4*0xE1) //Attributes : RW +#define JECS_PMA1_LANE1_SRIO_DEGRADED (JECS_PMA1_LANE1_BASE + 4*0xE2) //Attributes : RW +#define JECS_PMA1_LANE1_SRIO_RETRAIN (JECS_PMA1_LANE1_BASE + 4*0xE3) //Attributes : RW +#define JECS_PMA1_LANE1_SRIO_SHORT_RUN (JECS_PMA1_LANE1_BASE + 4*0xE4) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_INIT_C0 (JECS_PMA1_LANE1_BASE + 4*0xE5) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_INIT_CN1 (JECS_PMA1_LANE1_BASE + 4*0xE6) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_INIT_CP1 (JECS_PMA1_LANE1_BASE + 4*0xE7) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_RULE_CTRL_1 (JECS_PMA1_LANE1_BASE + 4*0xE8) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_RULE_CTRL_2 (JECS_PMA1_LANE1_BASE + 4*0xE9) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_RULE_CTRL_3 (JECS_PMA1_LANE1_BASE + 4*0xEA) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_RULE_CTRL_4 (JECS_PMA1_LANE1_BASE + 4*0xEB) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_ALGORITHM_CTRL (JECS_PMA1_LANE1_BASE + 4*0xEC) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_TX_TRAIN_CTRL (JECS_PMA1_LANE1_BASE + 4*0xED) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_ADJ_INTERVAL (JECS_PMA1_LANE1_BASE + 4*0xEE) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_RX_REQ_CTRL (JECS_PMA1_LANE1_BASE + 4*0xEF) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_RX_TRAIN_CTRL (JECS_PMA1_LANE1_BASE + 4*0xF0) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_RX_RESET_CYCLE (JECS_PMA1_LANE1_BASE + 4*0xF1) //Attributes : RW +#define JECS_PMA1_LANE1_RPCS_KTR_STATUS (JECS_PMA1_LANE1_BASE + 4*0xF2) //Attributes : RO +#define JECS_PMA1_LANE1_EQ_FSM (JECS_PMA1_LANE1_BASE + 4*0xF3) //Attributes : RO +#define JECS_PMA1_LANE1_ETH_RX_LOS (JECS_PMA1_LANE1_BASE + 4*0xF4) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_PRESET_C0 (JECS_PMA1_LANE1_BASE + 4*0xF5) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_PRESET_CN1 (JECS_PMA1_LANE1_BASE + 4*0xF6) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_PRESET_CP1 (JECS_PMA1_LANE1_BASE + 4*0xF7) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_SUCC_MASK (JECS_PMA1_LANE1_BASE + 4*0xF8) //Attributes : RW +#define JECS_PMA1_LANE1_PMA_COM_SCRATCH (JECS_PMA1_LANE1_BASE + 4*0xff) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY0 (JECS_PMA1_LANE1_BASE + 4*0x100) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY1 (JECS_PMA1_LANE1_BASE + 4*0x101) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY2 (JECS_PMA1_LANE1_BASE + 4*0x102) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY3 (JECS_PMA1_LANE1_BASE + 4*0x103) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY4 (JECS_PMA1_LANE1_BASE + 4*0x104) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY5 (JECS_PMA1_LANE1_BASE + 4*0x105) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY6 (JECS_PMA1_LANE1_BASE + 4*0x106) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY7 (JECS_PMA1_LANE1_BASE + 4*0x107) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE1_EQ_TX_FSM_HISTORY_CTRL (JECS_PMA1_LANE1_BASE + 4*0x108) //Attributes : RW +#define JECS_PMA1_LANE1_EQ_RX_FSM_HISTORY0 (JECS_PMA1_LANE1_BASE + 4*0x109) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE1_EQ_RX_FSM_HISTORY1 (JECS_PMA1_LANE1_BASE + 4*0x10A) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_EQ_RX_FSM_HISTORY2 (JECS_PMA1_LANE1_BASE + 4*0x10B) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_EQ_RX_FSM_HISTORY3 (JECS_PMA1_LANE1_BASE + 4*0x10C) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE1_EQ_RX_FSM_HISTORY_CTRL (JECS_PMA1_LANE1_BASE + 4*0x10D) //Attributes : RW +#define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY0 (JECS_PMA1_LANE1_BASE + 4*0x110) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY1 (JECS_PMA1_LANE1_BASE + 4*0x111) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY2 (JECS_PMA1_LANE1_BASE + 4*0x112) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY3 (JECS_PMA1_LANE1_BASE + 4*0x113) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY4 (JECS_PMA1_LANE1_BASE + 4*0x114) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY5 (JECS_PMA1_LANE1_BASE + 4*0x115) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY6 (JECS_PMA1_LANE1_BASE + 4*0x116) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY7 (JECS_PMA1_LANE1_BASE + 4*0x117) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE1_TX_EQ_MAIN_HISTORY_CTRL (JECS_PMA1_LANE1_BASE + 4*0x118) //Attributes : RW +#define JECS_PMA1_LANE1_RX_TXMAIN_DIR_HISTORY0 (JECS_PMA1_LANE1_BASE + 4*0x119) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE1_RX_TXMAIN_DIR_HISTORY1 (JECS_PMA1_LANE1_BASE + 4*0x11A) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_RX_TXMAIN_DIR_HISTORY2 (JECS_PMA1_LANE1_BASE + 4*0x11B) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_RX_TXMAIN_DIR_HISTORY3 (JECS_PMA1_LANE1_BASE + 4*0x11C) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE1_RX_TXMAIN_DIR_HISTORY_CTRL (JECS_PMA1_LANE1_BASE + 4*0x11D) //Attributes : RW +#define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY0 (JECS_PMA1_LANE1_BASE + 4*0x120) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY1 (JECS_PMA1_LANE1_BASE + 4*0x121) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY2 (JECS_PMA1_LANE1_BASE + 4*0x122) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY3 (JECS_PMA1_LANE1_BASE + 4*0x123) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY4 (JECS_PMA1_LANE1_BASE + 4*0x124) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY5 (JECS_PMA1_LANE1_BASE + 4*0x125) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY6 (JECS_PMA1_LANE1_BASE + 4*0x126) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY7 (JECS_PMA1_LANE1_BASE + 4*0x127) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE1_TX_EQ_POST_HISTORY_CTRL (JECS_PMA1_LANE1_BASE + 4*0x128) //Attributes : RW +#define JECS_PMA1_LANE1_RX_TXPOST_DIR_HISTORY0 (JECS_PMA1_LANE1_BASE + 4*0x129) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE1_RX_TXPOST_DIR_HISTORY1 (JECS_PMA1_LANE1_BASE + 4*0x12A) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_RX_TXPOST_DIR_HISTORY2 (JECS_PMA1_LANE1_BASE + 4*0x12B) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_RX_TXPOST_DIR_HISTORY3 (JECS_PMA1_LANE1_BASE + 4*0x12C) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE1_RX_TXPOST_DIR_HISTORY_CTRL (JECS_PMA1_LANE1_BASE + 4*0x12D) //Attributes : RW +#define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY0 (JECS_PMA1_LANE1_BASE + 4*0x130) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY1 (JECS_PMA1_LANE1_BASE + 4*0x131) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY2 (JECS_PMA1_LANE1_BASE + 4*0x132) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY3 (JECS_PMA1_LANE1_BASE + 4*0x133) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY4 (JECS_PMA1_LANE1_BASE + 4*0x134) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY5 (JECS_PMA1_LANE1_BASE + 4*0x135) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY6 (JECS_PMA1_LANE1_BASE + 4*0x136) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY7 (JECS_PMA1_LANE1_BASE + 4*0x137) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE1_TX_EQ_PRE_HISTORY_CTRL (JECS_PMA1_LANE1_BASE + 4*0x138) //Attributes : RW +#define JECS_PMA1_LANE1_RX_TXPRE_DIR_HISTORY0 (JECS_PMA1_LANE1_BASE + 4*0x139) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE1_RX_TXPRE_DIR_HISTORY1 (JECS_PMA1_LANE1_BASE + 4*0x13A) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_RX_TXPRE_DIR_HISTORY2 (JECS_PMA1_LANE1_BASE + 4*0x13B) //Attributes : RO_EXT +#define JECS_PMA1_LANE1_RX_TXPRE_DIR_HISTORY3 (JECS_PMA1_LANE1_BASE + 4*0x13C) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE1_RX_TXPRE_DIR_HISTORY_CTRL (JECS_PMA1_LANE1_BASE + 4*0x13D) //Attributes : RW + +#define JECS_PMA1_LANE2_PMA_LOOPBACK_CTRL (JECS_PMA1_LANE2_BASE + 4*0x00) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_REQ (JECS_PMA1_LANE2_BASE + 4*0x01) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_REQ_ACK (JECS_PMA1_LANE2_BASE + 4*0x02) //Attributes : RO +#define JECS_PMA1_LANE2_RECEIVER_REQ_PARAM2 (JECS_PMA1_LANE2_BASE + 4*0x03) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_REQ_PARAM3 (JECS_PMA1_LANE2_BASE + 4*0x04) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_REQ_PARAM4 (JECS_PMA1_LANE2_BASE + 4*0x05) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_REQ_PARAM5 (JECS_PMA1_LANE2_BASE + 4*0x06) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_REQ_PARAM6 (JECS_PMA1_LANE2_BASE + 4*0x07) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_REQ_PARAM7 (JECS_PMA1_LANE2_BASE + 4*0x08) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_REQ_PARAM8 (JECS_PMA1_LANE2_BASE + 4*0x09) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_REQ_PARAM9 (JECS_PMA1_LANE2_BASE + 4*0x0A) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_REQ_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x0B) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_ADAPT_REQ (JECS_PMA1_LANE2_BASE + 4*0x10) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_ADAPT_REQ_ACK (JECS_PMA1_LANE2_BASE + 4*0x11) //Attributes : RO +#define JECS_PMA1_LANE2_RECEIVER_ADAPT_DIR (JECS_PMA1_LANE2_BASE + 4*0x12) //Attributes : RO +#define JECS_PMA1_LANE2_RECEIVER_ADAPT_SETTING (JECS_PMA1_LANE2_BASE + 4*0x13) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_ADAPT_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x14) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_DATAPATH_EN (JECS_PMA1_LANE2_BASE + 4*0x20) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_DATAPATH_SETTING1 (JECS_PMA1_LANE2_BASE + 4*0x21) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_DATAPATH_SETTING2 (JECS_PMA1_LANE2_BASE + 4*0x22) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_DATAPATH_SETTING3 (JECS_PMA1_LANE2_BASE + 4*0x23) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_DATAPATH_STATUS1 (JECS_PMA1_LANE2_BASE + 4*0x24) //Attributes : RO +#define JECS_PMA1_LANE2_RECEIVER_DATAPATH_STATUS2 (JECS_PMA1_LANE2_BASE + 4*0x25) //Attributes : RO +#define JECS_PMA1_LANE2_RECEIVER_DATAPATH_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x26) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_RESET (JECS_PMA1_LANE2_BASE + 4*0x30) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_CONTROL (JECS_PMA1_LANE2_BASE + 4*0x31) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_CONTROL_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x32) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_RECAL_CTRL (JECS_PMA1_LANE2_BASE + 4*0x40) //Attributes : RW +#define JECS_PMA1_LANE2_RECEIVER_RECAL_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x41) //Attributes : RW +#define JECS_PMA1_LANE2_TRANSMITTER_REQ (JECS_PMA1_LANE2_BASE + 4*0x50) //Attributes : RW +#define JECS_PMA1_LANE2_TRANSMITTER_REQ_ACK (JECS_PMA1_LANE2_BASE + 4*0x51) //Attributes : RO +#define JECS_PMA1_LANE2_TRANSMITTER_REQ_PARAM1 (JECS_PMA1_LANE2_BASE + 4*0x52) //Attributes : RW +#define JECS_PMA1_LANE2_TRANSMITTER_REQ_PARAM2 (JECS_PMA1_LANE2_BASE + 4*0x53) //Attributes : RW +#define JECS_PMA1_LANE2_TRANSMITTER_REQ_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x55) //Attributes : RW +#define JECS_PMA1_LANE2_TRANSMITTER_DATAPATH_EN (JECS_PMA1_LANE2_BASE + 4*0x60) //Attributes : RW +#define JECS_PMA1_LANE2_TRANSMITTER_DATAPATH_CLKRDY (JECS_PMA1_LANE2_BASE + 4*0x61) //Attributes : RW +#define JECS_PMA1_LANE2_TRANSMITTER_DATAPATH_SETTING (JECS_PMA1_LANE2_BASE + 4*0x62) //Attributes : RW +#define JECS_PMA1_LANE2_TRANSMITTER_DATAPATH_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x63) //Attributes : RW +#define JECS_PMA1_LANE2_TRANSMITTER_CONTROL1 (JECS_PMA1_LANE2_BASE + 4*0x70) //Attributes : RW +#define JECS_PMA1_LANE2_TRANSMITTER_CONTROL2 (JECS_PMA1_LANE2_BASE + 4*0x71) //Attributes : RW +#define JECS_PMA1_LANE2_TRANSMITTER_CONTROL_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x72) //Attributes : RW +#define JECS_PMA1_LANE2_TRANSMITTER_EQ1 (JECS_PMA1_LANE2_BASE + 4*0x80) //Attributes : RW +#define JECS_PMA1_LANE2_TRANSMITTER_EQ2 (JECS_PMA1_LANE2_BASE + 4*0x81) //Attributes : RW +#define JECS_PMA1_LANE2_TRANSMITTER_EQ3 (JECS_PMA1_LANE2_BASE + 4*0x82) //Attributes : RW +#define JECS_PMA1_LANE2_TRANSMITTER_EQ_MUX_CTRL (JECS_PMA1_LANE2_BASE + 4*0x83) //Attributes : RW +#define JECS_PMA1_LANE2_CONTEXT_RESTORE_CTRL1 (JECS_PMA1_LANE2_BASE + 4*0x90) //Attributes : RW +#define JECS_PMA1_LANE2_CONTEXT_RESTORE_CTRL2 (JECS_PMA1_LANE2_BASE + 4*0x91) //Attributes : RW +#define JECS_PMA1_LANE2_CONTEXT_RESTORE_CTRL3 (JECS_PMA1_LANE2_BASE + 4*0x92) //Attributes : RW +#define JECS_PMA1_LANE2_CONTEXT_RESTORE_CTRL4 (JECS_PMA1_LANE2_BASE + 4*0x93) //Attributes : RW +#define JECS_PMA1_LANE2_CONTEXT_RESTORE_MUX (JECS_PMA1_LANE2_BASE + 4*0x94) //Attributes : RW +#define JECS_PMA1_LANE2_LANE_REFCLK_SEL (JECS_PMA1_LANE2_BASE + 4*0xA0) //Attributes : RW +#define JECS_PMA1_LANE2_ETH_CLK_CTRL (JECS_PMA1_LANE2_BASE + 4*0xB0) //Attributes : RW +#define JECS_PMA1_LANE2_ETH_CLK_CTRL_MUX (JECS_PMA1_LANE2_BASE + 4*0xB1) //Attributes : RW +#define JECS_PMA1_LANE2_RX_ADAPT_CTRL (JECS_PMA1_LANE2_BASE + 4*0xC0) //Attributes : RW +#define JECS_PMA1_LANE2_RX_DCC_CTRL (JECS_PMA1_LANE2_BASE + 4*0xC1) //Attributes : RW +#define JECS_PMA1_LANE2_RX_EQ_CTRL1 (JECS_PMA1_LANE2_BASE + 4*0xC2) //Attributes : RW +#define JECS_PMA1_LANE2_RX_EQ_CTRL2 (JECS_PMA1_LANE2_BASE + 4*0xC3) //Attributes : RW +#define JECS_PMA1_LANE2_RX_MARGIN_CTRL (JECS_PMA1_LANE2_BASE + 4*0xC4) //Attributes : RW +#define JECS_PMA1_LANE2_RX_MARGIN_ERROR (JECS_PMA1_LANE2_BASE + 4*0xC5) //Attributes : RO +#define JECS_PMA1_LANE2_RECV_REQUEST_CTRL_MUX (JECS_PMA1_LANE2_BASE + 4*0xC6) //Attributes : RW +#define JECS_PMA1_LANE2_RX_COARSE_ADAPT_CTRL (JECS_PMA1_LANE2_BASE + 4*0xC8) //Attributes : RW +#define JECS_PMA1_LANE2_RX_COARSE_ADAPT_CTRL_MUX (JECS_PMA1_LANE2_BASE + 4*0xC9) //Attributes : RW +#define JECS_PMA1_LANE2_RX_DIV_CLK_CTRL (JECS_PMA1_LANE2_BASE + 4*0xCA) //Attributes : RW +#define JECS_PMA1_LANE2_TX_DIV_CLK_CTRL (JECS_PMA1_LANE2_BASE + 4*0xCB) //Attributes : RW +#define JECS_PMA1_LANE2_MULTI_CLK_CTRL_MUX (JECS_PMA1_LANE2_BASE + 4*0xCC) //Attributes : RW +#define JECS_PMA1_LANE2_TRANS_REQ_CTRL1 (JECS_PMA1_LANE2_BASE + 4*0xD0) //Attributes : RW +#define JECS_PMA1_LANE2_TRANS_REQ_CTRL2 (JECS_PMA1_LANE2_BASE + 4*0xD1) //Attributes : RW +#define JECS_PMA1_LANE2_TRANS_REQ_CTRL3 (JECS_PMA1_LANE2_BASE + 4*0xD2) //Attributes : RW +#define JECS_PMA1_LANE2_TRANS_REQ_CTRL4 (JECS_PMA1_LANE2_BASE + 4*0xD3) //Attributes : RW +#define JECS_PMA1_LANE2_TRANS_REQ_CTRL5 (JECS_PMA1_LANE2_BASE + 4*0xD4) //Attributes : RW +#define JECS_PMA1_LANE2_TRANS_REQ_MUX (JECS_PMA1_LANE2_BASE + 4*0xD5) //Attributes : RW +#define JECS_PMA1_LANE2_TRANS_INTERFACE_CTRL (JECS_PMA1_LANE2_BASE + 4*0xD6) //Attributes : RW +#define JECS_PMA1_LANE2_TRANS_INTERFACE_MUX (JECS_PMA1_LANE2_BASE + 4*0xD7) //Attributes : RW +#define JECS_PMA1_LANE2_TRANS_MASTER_PLL_STATE (JECS_PMA1_LANE2_BASE + 4*0xD8) //Attributes : RW +#define JECS_PMA1_LANE2_TRANS_PLL_STATE (JECS_PMA1_LANE2_BASE + 4*0xD9) //Attributes : RO +#define JECS_PMA1_LANE2_PLL_STATE_MUX (JECS_PMA1_LANE2_BASE + 4*0xDA) //Attributes : RW +#define JECS_PMA1_LANE2_RX_VALID_PHY (JECS_PMA1_LANE2_BASE + 4*0xDF) //Attributes : RO +#define JECS_PMA1_LANE2_RX_VALID_MUX (JECS_PMA1_LANE2_BASE + 4*0xE0) //Attributes : RW +#define JECS_PMA1_LANE2_RX_SRIO_SIGDET_MUX (JECS_PMA1_LANE2_BASE + 4*0xE1) //Attributes : RW +#define JECS_PMA1_LANE2_SRIO_DEGRADED (JECS_PMA1_LANE2_BASE + 4*0xE2) //Attributes : RW +#define JECS_PMA1_LANE2_SRIO_RETRAIN (JECS_PMA1_LANE2_BASE + 4*0xE3) //Attributes : RW +#define JECS_PMA1_LANE2_SRIO_SHORT_RUN (JECS_PMA1_LANE2_BASE + 4*0xE4) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_INIT_C0 (JECS_PMA1_LANE2_BASE + 4*0xE5) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_INIT_CN1 (JECS_PMA1_LANE2_BASE + 4*0xE6) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_INIT_CP1 (JECS_PMA1_LANE2_BASE + 4*0xE7) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_RULE_CTRL_1 (JECS_PMA1_LANE2_BASE + 4*0xE8) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_RULE_CTRL_2 (JECS_PMA1_LANE2_BASE + 4*0xE9) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_RULE_CTRL_3 (JECS_PMA1_LANE2_BASE + 4*0xEA) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_RULE_CTRL_4 (JECS_PMA1_LANE2_BASE + 4*0xEB) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_ALGORITHM_CTRL (JECS_PMA1_LANE2_BASE + 4*0xEC) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_TX_TRAIN_CTRL (JECS_PMA1_LANE2_BASE + 4*0xED) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_ADJ_INTERVAL (JECS_PMA1_LANE2_BASE + 4*0xEE) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_RX_REQ_CTRL (JECS_PMA1_LANE2_BASE + 4*0xEF) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_RX_TRAIN_CTRL (JECS_PMA1_LANE2_BASE + 4*0xF0) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_RX_RESET_CYCLE (JECS_PMA1_LANE2_BASE + 4*0xF1) //Attributes : RW +#define JECS_PMA1_LANE2_RPCS_KTR_STATUS (JECS_PMA1_LANE2_BASE + 4*0xF2) //Attributes : RO +#define JECS_PMA1_LANE2_EQ_FSM (JECS_PMA1_LANE2_BASE + 4*0xF3) //Attributes : RO +#define JECS_PMA1_LANE2_ETH_RX_LOS (JECS_PMA1_LANE2_BASE + 4*0xF4) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_PRESET_C0 (JECS_PMA1_LANE2_BASE + 4*0xF5) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_PRESET_CN1 (JECS_PMA1_LANE2_BASE + 4*0xF6) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_PRESET_CP1 (JECS_PMA1_LANE2_BASE + 4*0xF7) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_SUCC_MASK (JECS_PMA1_LANE2_BASE + 4*0xF8) //Attributes : RW +#define JECS_PMA1_LANE2_PMA_COM_SCRATCH (JECS_PMA1_LANE2_BASE + 4*0xff) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY0 (JECS_PMA1_LANE2_BASE + 4*0x100) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY1 (JECS_PMA1_LANE2_BASE + 4*0x101) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY2 (JECS_PMA1_LANE2_BASE + 4*0x102) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY3 (JECS_PMA1_LANE2_BASE + 4*0x103) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY4 (JECS_PMA1_LANE2_BASE + 4*0x104) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY5 (JECS_PMA1_LANE2_BASE + 4*0x105) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY6 (JECS_PMA1_LANE2_BASE + 4*0x106) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY7 (JECS_PMA1_LANE2_BASE + 4*0x107) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE2_EQ_TX_FSM_HISTORY_CTRL (JECS_PMA1_LANE2_BASE + 4*0x108) //Attributes : RW +#define JECS_PMA1_LANE2_EQ_RX_FSM_HISTORY0 (JECS_PMA1_LANE2_BASE + 4*0x109) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE2_EQ_RX_FSM_HISTORY1 (JECS_PMA1_LANE2_BASE + 4*0x10A) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_EQ_RX_FSM_HISTORY2 (JECS_PMA1_LANE2_BASE + 4*0x10B) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_EQ_RX_FSM_HISTORY3 (JECS_PMA1_LANE2_BASE + 4*0x10C) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE2_EQ_RX_FSM_HISTORY_CTRL (JECS_PMA1_LANE2_BASE + 4*0x10D) //Attributes : RW +#define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY0 (JECS_PMA1_LANE2_BASE + 4*0x110) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY1 (JECS_PMA1_LANE2_BASE + 4*0x111) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY2 (JECS_PMA1_LANE2_BASE + 4*0x112) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY3 (JECS_PMA1_LANE2_BASE + 4*0x113) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY4 (JECS_PMA1_LANE2_BASE + 4*0x114) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY5 (JECS_PMA1_LANE2_BASE + 4*0x115) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY6 (JECS_PMA1_LANE2_BASE + 4*0x116) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY7 (JECS_PMA1_LANE2_BASE + 4*0x117) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE2_TX_EQ_MAIN_HISTORY_CTRL (JECS_PMA1_LANE2_BASE + 4*0x118) //Attributes : RW +#define JECS_PMA1_LANE2_RX_TXMAIN_DIR_HISTORY0 (JECS_PMA1_LANE2_BASE + 4*0x119) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE2_RX_TXMAIN_DIR_HISTORY1 (JECS_PMA1_LANE2_BASE + 4*0x11A) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_RX_TXMAIN_DIR_HISTORY2 (JECS_PMA1_LANE2_BASE + 4*0x11B) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_RX_TXMAIN_DIR_HISTORY3 (JECS_PMA1_LANE2_BASE + 4*0x11C) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE2_RX_TXMAIN_DIR_HISTORY_CTRL (JECS_PMA1_LANE2_BASE + 4*0x11D) //Attributes : RW +#define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY0 (JECS_PMA1_LANE2_BASE + 4*0x120) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY1 (JECS_PMA1_LANE2_BASE + 4*0x121) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY2 (JECS_PMA1_LANE2_BASE + 4*0x122) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY3 (JECS_PMA1_LANE2_BASE + 4*0x123) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY4 (JECS_PMA1_LANE2_BASE + 4*0x124) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY5 (JECS_PMA1_LANE2_BASE + 4*0x125) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY6 (JECS_PMA1_LANE2_BASE + 4*0x126) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY7 (JECS_PMA1_LANE2_BASE + 4*0x127) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE2_TX_EQ_POST_HISTORY_CTRL (JECS_PMA1_LANE2_BASE + 4*0x128) //Attributes : RW +#define JECS_PMA1_LANE2_RX_TXPOST_DIR_HISTORY0 (JECS_PMA1_LANE2_BASE + 4*0x129) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE2_RX_TXPOST_DIR_HISTORY1 (JECS_PMA1_LANE2_BASE + 4*0x12A) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_RX_TXPOST_DIR_HISTORY2 (JECS_PMA1_LANE2_BASE + 4*0x12B) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_RX_TXPOST_DIR_HISTORY3 (JECS_PMA1_LANE2_BASE + 4*0x12C) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE2_RX_TXPOST_DIR_HISTORY_CTRL (JECS_PMA1_LANE2_BASE + 4*0x12D) //Attributes : RW +#define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY0 (JECS_PMA1_LANE2_BASE + 4*0x130) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY1 (JECS_PMA1_LANE2_BASE + 4*0x131) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY2 (JECS_PMA1_LANE2_BASE + 4*0x132) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY3 (JECS_PMA1_LANE2_BASE + 4*0x133) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY4 (JECS_PMA1_LANE2_BASE + 4*0x134) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY5 (JECS_PMA1_LANE2_BASE + 4*0x135) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY6 (JECS_PMA1_LANE2_BASE + 4*0x136) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY7 (JECS_PMA1_LANE2_BASE + 4*0x137) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE2_TX_EQ_PRE_HISTORY_CTRL (JECS_PMA1_LANE2_BASE + 4*0x138) //Attributes : RW +#define JECS_PMA1_LANE2_RX_TXPRE_DIR_HISTORY0 (JECS_PMA1_LANE2_BASE + 4*0x139) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE2_RX_TXPRE_DIR_HISTORY1 (JECS_PMA1_LANE2_BASE + 4*0x13A) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_RX_TXPRE_DIR_HISTORY2 (JECS_PMA1_LANE2_BASE + 4*0x13B) //Attributes : RO_EXT +#define JECS_PMA1_LANE2_RX_TXPRE_DIR_HISTORY3 (JECS_PMA1_LANE2_BASE + 4*0x13C) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE2_RX_TXPRE_DIR_HISTORY_CTRL (JECS_PMA1_LANE2_BASE + 4*0x13D) //Attributes : RW + +#define JECS_PMA1_LANE3_PMA_LOOPBACK_CTRL (JECS_PMA1_LANE3_BASE + 4*0x00) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_REQ (JECS_PMA1_LANE3_BASE + 4*0x01) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_REQ_ACK (JECS_PMA1_LANE3_BASE + 4*0x02) //Attributes : RO +#define JECS_PMA1_LANE3_RECEIVER_REQ_PARAM2 (JECS_PMA1_LANE3_BASE + 4*0x03) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_REQ_PARAM3 (JECS_PMA1_LANE3_BASE + 4*0x04) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_REQ_PARAM4 (JECS_PMA1_LANE3_BASE + 4*0x05) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_REQ_PARAM5 (JECS_PMA1_LANE3_BASE + 4*0x06) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_REQ_PARAM6 (JECS_PMA1_LANE3_BASE + 4*0x07) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_REQ_PARAM7 (JECS_PMA1_LANE3_BASE + 4*0x08) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_REQ_PARAM8 (JECS_PMA1_LANE3_BASE + 4*0x09) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_REQ_PARAM9 (JECS_PMA1_LANE3_BASE + 4*0x0A) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_REQ_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x0B) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_ADAPT_REQ (JECS_PMA1_LANE3_BASE + 4*0x10) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_ADAPT_REQ_ACK (JECS_PMA1_LANE3_BASE + 4*0x11) //Attributes : RO +#define JECS_PMA1_LANE3_RECEIVER_ADAPT_DIR (JECS_PMA1_LANE3_BASE + 4*0x12) //Attributes : RO +#define JECS_PMA1_LANE3_RECEIVER_ADAPT_SETTING (JECS_PMA1_LANE3_BASE + 4*0x13) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_ADAPT_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x14) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_DATAPATH_EN (JECS_PMA1_LANE3_BASE + 4*0x20) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_DATAPATH_SETTING1 (JECS_PMA1_LANE3_BASE + 4*0x21) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_DATAPATH_SETTING2 (JECS_PMA1_LANE3_BASE + 4*0x22) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_DATAPATH_SETTING3 (JECS_PMA1_LANE3_BASE + 4*0x23) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_DATAPATH_STATUS1 (JECS_PMA1_LANE3_BASE + 4*0x24) //Attributes : RO +#define JECS_PMA1_LANE3_RECEIVER_DATAPATH_STATUS2 (JECS_PMA1_LANE3_BASE + 4*0x25) //Attributes : RO +#define JECS_PMA1_LANE3_RECEIVER_DATAPATH_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x26) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_RESET (JECS_PMA1_LANE3_BASE + 4*0x30) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_CONTROL (JECS_PMA1_LANE3_BASE + 4*0x31) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_CONTROL_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x32) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_RECAL_CTRL (JECS_PMA1_LANE3_BASE + 4*0x40) //Attributes : RW +#define JECS_PMA1_LANE3_RECEIVER_RECAL_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x41) //Attributes : RW +#define JECS_PMA1_LANE3_TRANSMITTER_REQ (JECS_PMA1_LANE3_BASE + 4*0x50) //Attributes : RW +#define JECS_PMA1_LANE3_TRANSMITTER_REQ_ACK (JECS_PMA1_LANE3_BASE + 4*0x51) //Attributes : RO +#define JECS_PMA1_LANE3_TRANSMITTER_REQ_PARAM1 (JECS_PMA1_LANE3_BASE + 4*0x52) //Attributes : RW +#define JECS_PMA1_LANE3_TRANSMITTER_REQ_PARAM2 (JECS_PMA1_LANE3_BASE + 4*0x53) //Attributes : RW +#define JECS_PMA1_LANE3_TRANSMITTER_REQ_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x55) //Attributes : RW +#define JECS_PMA1_LANE3_TRANSMITTER_DATAPATH_EN (JECS_PMA1_LANE3_BASE + 4*0x60) //Attributes : RW +#define JECS_PMA1_LANE3_TRANSMITTER_DATAPATH_CLKRDY (JECS_PMA1_LANE3_BASE + 4*0x61) //Attributes : RW +#define JECS_PMA1_LANE3_TRANSMITTER_DATAPATH_SETTING (JECS_PMA1_LANE3_BASE + 4*0x62) //Attributes : RW +#define JECS_PMA1_LANE3_TRANSMITTER_DATAPATH_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x63) //Attributes : RW +#define JECS_PMA1_LANE3_TRANSMITTER_CONTROL1 (JECS_PMA1_LANE3_BASE + 4*0x70) //Attributes : RW +#define JECS_PMA1_LANE3_TRANSMITTER_CONTROL2 (JECS_PMA1_LANE3_BASE + 4*0x71) //Attributes : RW +#define JECS_PMA1_LANE3_TRANSMITTER_CONTROL_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x72) //Attributes : RW +#define JECS_PMA1_LANE3_TRANSMITTER_EQ1 (JECS_PMA1_LANE3_BASE + 4*0x80) //Attributes : RW +#define JECS_PMA1_LANE3_TRANSMITTER_EQ2 (JECS_PMA1_LANE3_BASE + 4*0x81) //Attributes : RW +#define JECS_PMA1_LANE3_TRANSMITTER_EQ3 (JECS_PMA1_LANE3_BASE + 4*0x82) //Attributes : RW +#define JECS_PMA1_LANE3_TRANSMITTER_EQ_MUX_CTRL (JECS_PMA1_LANE3_BASE + 4*0x83) //Attributes : RW +#define JECS_PMA1_LANE3_CONTEXT_RESTORE_CTRL1 (JECS_PMA1_LANE3_BASE + 4*0x90) //Attributes : RW +#define JECS_PMA1_LANE3_CONTEXT_RESTORE_CTRL2 (JECS_PMA1_LANE3_BASE + 4*0x91) //Attributes : RW +#define JECS_PMA1_LANE3_CONTEXT_RESTORE_CTRL3 (JECS_PMA1_LANE3_BASE + 4*0x92) //Attributes : RW +#define JECS_PMA1_LANE3_CONTEXT_RESTORE_CTRL4 (JECS_PMA1_LANE3_BASE + 4*0x93) //Attributes : RW +#define JECS_PMA1_LANE3_CONTEXT_RESTORE_MUX (JECS_PMA1_LANE3_BASE + 4*0x94) //Attributes : RW +#define JECS_PMA1_LANE3_LANE_REFCLK_SEL (JECS_PMA1_LANE3_BASE + 4*0xA0) //Attributes : RW +#define JECS_PMA1_LANE3_ETH_CLK_CTRL (JECS_PMA1_LANE3_BASE + 4*0xB0) //Attributes : RW +#define JECS_PMA1_LANE3_ETH_CLK_CTRL_MUX (JECS_PMA1_LANE3_BASE + 4*0xB1) //Attributes : RW +#define JECS_PMA1_LANE3_RX_ADAPT_CTRL (JECS_PMA1_LANE3_BASE + 4*0xC0) //Attributes : RW +#define JECS_PMA1_LANE3_RX_DCC_CTRL (JECS_PMA1_LANE3_BASE + 4*0xC1) //Attributes : RW +#define JECS_PMA1_LANE3_RX_EQ_CTRL1 (JECS_PMA1_LANE3_BASE + 4*0xC2) //Attributes : RW +#define JECS_PMA1_LANE3_RX_EQ_CTRL2 (JECS_PMA1_LANE3_BASE + 4*0xC3) //Attributes : RW +#define JECS_PMA1_LANE3_RX_MARGIN_CTRL (JECS_PMA1_LANE3_BASE + 4*0xC4) //Attributes : RW +#define JECS_PMA1_LANE3_RX_MARGIN_ERROR (JECS_PMA1_LANE3_BASE + 4*0xC5) //Attributes : RO +#define JECS_PMA1_LANE3_RECV_REQUEST_CTRL_MUX (JECS_PMA1_LANE3_BASE + 4*0xC6) //Attributes : RW +#define JECS_PMA1_LANE3_RX_COARSE_ADAPT_CTRL (JECS_PMA1_LANE3_BASE + 4*0xC8) //Attributes : RW +#define JECS_PMA1_LANE3_RX_COARSE_ADAPT_CTRL_MUX (JECS_PMA1_LANE3_BASE + 4*0xC9) //Attributes : RW +#define JECS_PMA1_LANE3_RX_DIV_CLK_CTRL (JECS_PMA1_LANE3_BASE + 4*0xCA) //Attributes : RW +#define JECS_PMA1_LANE3_TX_DIV_CLK_CTRL (JECS_PMA1_LANE3_BASE + 4*0xCB) //Attributes : RW +#define JECS_PMA1_LANE3_MULTI_CLK_CTRL_MUX (JECS_PMA1_LANE3_BASE + 4*0xCC) //Attributes : RW +#define JECS_PMA1_LANE3_TRANS_REQ_CTRL1 (JECS_PMA1_LANE3_BASE + 4*0xD0) //Attributes : RW +#define JECS_PMA1_LANE3_TRANS_REQ_CTRL2 (JECS_PMA1_LANE3_BASE + 4*0xD1) //Attributes : RW +#define JECS_PMA1_LANE3_TRANS_REQ_CTRL3 (JECS_PMA1_LANE3_BASE + 4*0xD2) //Attributes : RW +#define JECS_PMA1_LANE3_TRANS_REQ_CTRL4 (JECS_PMA1_LANE3_BASE + 4*0xD3) //Attributes : RW +#define JECS_PMA1_LANE3_TRANS_REQ_CTRL5 (JECS_PMA1_LANE3_BASE + 4*0xD4) //Attributes : RW +#define JECS_PMA1_LANE3_TRANS_REQ_MUX (JECS_PMA1_LANE3_BASE + 4*0xD5) //Attributes : RW +#define JECS_PMA1_LANE3_TRANS_INTERFACE_CTRL (JECS_PMA1_LANE3_BASE + 4*0xD6) //Attributes : RW +#define JECS_PMA1_LANE3_TRANS_INTERFACE_MUX (JECS_PMA1_LANE3_BASE + 4*0xD7) //Attributes : RW +#define JECS_PMA1_LANE3_TRANS_MASTER_PLL_STATE (JECS_PMA1_LANE3_BASE + 4*0xD8) //Attributes : RW +#define JECS_PMA1_LANE3_TRANS_PLL_STATE (JECS_PMA1_LANE3_BASE + 4*0xD9) //Attributes : RO +#define JECS_PMA1_LANE3_PLL_STATE_MUX (JECS_PMA1_LANE3_BASE + 4*0xDA) //Attributes : RW +#define JECS_PMA1_LANE3_RX_VALID_PHY (JECS_PMA1_LANE3_BASE + 4*0xDF) //Attributes : RO +#define JECS_PMA1_LANE3_RX_VALID_MUX (JECS_PMA1_LANE3_BASE + 4*0xE0) //Attributes : RW +#define JECS_PMA1_LANE3_RX_SRIO_SIGDET_MUX (JECS_PMA1_LANE3_BASE + 4*0xE1) //Attributes : RW +#define JECS_PMA1_LANE3_SRIO_DEGRADED (JECS_PMA1_LANE3_BASE + 4*0xE2) //Attributes : RW +#define JECS_PMA1_LANE3_SRIO_RETRAIN (JECS_PMA1_LANE3_BASE + 4*0xE3) //Attributes : RW +#define JECS_PMA1_LANE3_SRIO_SHORT_RUN (JECS_PMA1_LANE3_BASE + 4*0xE4) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_INIT_C0 (JECS_PMA1_LANE3_BASE + 4*0xE5) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_INIT_CN1 (JECS_PMA1_LANE3_BASE + 4*0xE6) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_INIT_CP1 (JECS_PMA1_LANE3_BASE + 4*0xE7) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_RULE_CTRL_1 (JECS_PMA1_LANE3_BASE + 4*0xE8) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_RULE_CTRL_2 (JECS_PMA1_LANE3_BASE + 4*0xE9) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_RULE_CTRL_3 (JECS_PMA1_LANE3_BASE + 4*0xEA) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_RULE_CTRL_4 (JECS_PMA1_LANE3_BASE + 4*0xEB) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_ALGORITHM_CTRL (JECS_PMA1_LANE3_BASE + 4*0xEC) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_TX_TRAIN_CTRL (JECS_PMA1_LANE3_BASE + 4*0xED) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_ADJ_INTERVAL (JECS_PMA1_LANE3_BASE + 4*0xEE) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_RX_REQ_CTRL (JECS_PMA1_LANE3_BASE + 4*0xEF) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_RX_TRAIN_CTRL (JECS_PMA1_LANE3_BASE + 4*0xF0) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_RX_RESET_CYCLE (JECS_PMA1_LANE3_BASE + 4*0xF1) //Attributes : RW +#define JECS_PMA1_LANE3_RPCS_KTR_STATUS (JECS_PMA1_LANE3_BASE + 4*0xF2) //Attributes : RO +#define JECS_PMA1_LANE3_EQ_FSM (JECS_PMA1_LANE3_BASE + 4*0xF3) //Attributes : RO +#define JECS_PMA1_LANE3_ETH_RX_LOS (JECS_PMA1_LANE3_BASE + 4*0xF4) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_PRESET_C0 (JECS_PMA1_LANE3_BASE + 4*0xF5) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_PRESET_CN1 (JECS_PMA1_LANE3_BASE + 4*0xF6) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_PRESET_CP1 (JECS_PMA1_LANE3_BASE + 4*0xF7) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_SUCC_MASK (JECS_PMA1_LANE3_BASE + 4*0xF8) //Attributes : RW +#define JECS_PMA1_LANE3_PMA_COM_SCRATCH (JECS_PMA1_LANE3_BASE + 4*0xff) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY0 (JECS_PMA1_LANE3_BASE + 4*0x100) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY1 (JECS_PMA1_LANE3_BASE + 4*0x101) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY2 (JECS_PMA1_LANE3_BASE + 4*0x102) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY3 (JECS_PMA1_LANE3_BASE + 4*0x103) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY4 (JECS_PMA1_LANE3_BASE + 4*0x104) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY5 (JECS_PMA1_LANE3_BASE + 4*0x105) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY6 (JECS_PMA1_LANE3_BASE + 4*0x106) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY7 (JECS_PMA1_LANE3_BASE + 4*0x107) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE3_EQ_TX_FSM_HISTORY_CTRL (JECS_PMA1_LANE3_BASE + 4*0x108) //Attributes : RW +#define JECS_PMA1_LANE3_EQ_RX_FSM_HISTORY0 (JECS_PMA1_LANE3_BASE + 4*0x109) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE3_EQ_RX_FSM_HISTORY1 (JECS_PMA1_LANE3_BASE + 4*0x10A) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_EQ_RX_FSM_HISTORY2 (JECS_PMA1_LANE3_BASE + 4*0x10B) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_EQ_RX_FSM_HISTORY3 (JECS_PMA1_LANE3_BASE + 4*0x10C) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE3_EQ_RX_FSM_HISTORY_CTRL (JECS_PMA1_LANE3_BASE + 4*0x10D) //Attributes : RW +#define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY0 (JECS_PMA1_LANE3_BASE + 4*0x110) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY1 (JECS_PMA1_LANE3_BASE + 4*0x111) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY2 (JECS_PMA1_LANE3_BASE + 4*0x112) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY3 (JECS_PMA1_LANE3_BASE + 4*0x113) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY4 (JECS_PMA1_LANE3_BASE + 4*0x114) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY5 (JECS_PMA1_LANE3_BASE + 4*0x115) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY6 (JECS_PMA1_LANE3_BASE + 4*0x116) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY7 (JECS_PMA1_LANE3_BASE + 4*0x117) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE3_TX_EQ_MAIN_HISTORY_CTRL (JECS_PMA1_LANE3_BASE + 4*0x118) //Attributes : RW +#define JECS_PMA1_LANE3_RX_TXMAIN_DIR_HISTORY0 (JECS_PMA1_LANE3_BASE + 4*0x119) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE3_RX_TXMAIN_DIR_HISTORY1 (JECS_PMA1_LANE3_BASE + 4*0x11A) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_RX_TXMAIN_DIR_HISTORY2 (JECS_PMA1_LANE3_BASE + 4*0x11B) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_RX_TXMAIN_DIR_HISTORY3 (JECS_PMA1_LANE3_BASE + 4*0x11C) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE3_RX_TXMAIN_DIR_HISTORY_CTRL (JECS_PMA1_LANE3_BASE + 4*0x11D) //Attributes : RW +#define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY0 (JECS_PMA1_LANE3_BASE + 4*0x120) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY1 (JECS_PMA1_LANE3_BASE + 4*0x121) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY2 (JECS_PMA1_LANE3_BASE + 4*0x122) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY3 (JECS_PMA1_LANE3_BASE + 4*0x123) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY4 (JECS_PMA1_LANE3_BASE + 4*0x124) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY5 (JECS_PMA1_LANE3_BASE + 4*0x125) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY6 (JECS_PMA1_LANE3_BASE + 4*0x126) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY7 (JECS_PMA1_LANE3_BASE + 4*0x127) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE3_TX_EQ_POST_HISTORY_CTRL (JECS_PMA1_LANE3_BASE + 4*0x128) //Attributes : RW +#define JECS_PMA1_LANE3_RX_TXPOST_DIR_HISTORY0 (JECS_PMA1_LANE3_BASE + 4*0x129) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE3_RX_TXPOST_DIR_HISTORY1 (JECS_PMA1_LANE3_BASE + 4*0x12A) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_RX_TXPOST_DIR_HISTORY2 (JECS_PMA1_LANE3_BASE + 4*0x12B) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_RX_TXPOST_DIR_HISTORY3 (JECS_PMA1_LANE3_BASE + 4*0x12C) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE3_RX_TXPOST_DIR_HISTORY_CTRL (JECS_PMA1_LANE3_BASE + 4*0x12D) //Attributes : RW +#define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY0 (JECS_PMA1_LANE3_BASE + 4*0x130) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY1 (JECS_PMA1_LANE3_BASE + 4*0x131) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY2 (JECS_PMA1_LANE3_BASE + 4*0x132) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY3 (JECS_PMA1_LANE3_BASE + 4*0x133) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY4 (JECS_PMA1_LANE3_BASE + 4*0x134) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY5 (JECS_PMA1_LANE3_BASE + 4*0x135) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY6 (JECS_PMA1_LANE3_BASE + 4*0x136) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY7 (JECS_PMA1_LANE3_BASE + 4*0x137) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE3_TX_EQ_PRE_HISTORY_CTRL (JECS_PMA1_LANE3_BASE + 4*0x138) //Attributes : RW +#define JECS_PMA1_LANE3_RX_TXPRE_DIR_HISTORY0 (JECS_PMA1_LANE3_BASE + 4*0x139) //Attributes : RO_EXT_L +#define JECS_PMA1_LANE3_RX_TXPRE_DIR_HISTORY1 (JECS_PMA1_LANE3_BASE + 4*0x13A) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_RX_TXPRE_DIR_HISTORY2 (JECS_PMA1_LANE3_BASE + 4*0x13B) //Attributes : RO_EXT +#define JECS_PMA1_LANE3_RX_TXPRE_DIR_HISTORY3 (JECS_PMA1_LANE3_BASE + 4*0x13C) //Attributes : RO_EXT_H +#define JECS_PMA1_LANE3_RX_TXPRE_DIR_HISTORY_CTRL (JECS_PMA1_LANE3_BASE + 4*0x13D) //Attributes : RW + +#define JECS_PMA1_BROADCAST_PMA_LOOPBACK_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x00) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_REQ (JECS_PMA1_BROADCAST_BASE + 4*0x01) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_REQ_ACK (JECS_PMA1_BROADCAST_BASE + 4*0x02) //Attributes : RO +#define JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM2 (JECS_PMA1_BROADCAST_BASE + 4*0x03) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM3 (JECS_PMA1_BROADCAST_BASE + 4*0x04) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM4 (JECS_PMA1_BROADCAST_BASE + 4*0x05) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM5 (JECS_PMA1_BROADCAST_BASE + 4*0x06) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM6 (JECS_PMA1_BROADCAST_BASE + 4*0x07) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM7 (JECS_PMA1_BROADCAST_BASE + 4*0x08) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM8 (JECS_PMA1_BROADCAST_BASE + 4*0x09) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM9 (JECS_PMA1_BROADCAST_BASE + 4*0x0A) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_REQ_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x0B) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_ADAPT_REQ (JECS_PMA1_BROADCAST_BASE + 4*0x10) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_ADAPT_REQ_ACK (JECS_PMA1_BROADCAST_BASE + 4*0x11) //Attributes : RO +#define JECS_PMA1_BROADCAST_RECEIVER_ADAPT_DIR (JECS_PMA1_BROADCAST_BASE + 4*0x12) //Attributes : RO +#define JECS_PMA1_BROADCAST_RECEIVER_ADAPT_SETTING (JECS_PMA1_BROADCAST_BASE + 4*0x13) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_ADAPT_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x14) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_EN (JECS_PMA1_BROADCAST_BASE + 4*0x20) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING1 (JECS_PMA1_BROADCAST_BASE + 4*0x21) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING2 (JECS_PMA1_BROADCAST_BASE + 4*0x22) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING3 (JECS_PMA1_BROADCAST_BASE + 4*0x23) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_STATUS1 (JECS_PMA1_BROADCAST_BASE + 4*0x24) //Attributes : RO +#define JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_STATUS2 (JECS_PMA1_BROADCAST_BASE + 4*0x25) //Attributes : RO +#define JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x26) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_RESET (JECS_PMA1_BROADCAST_BASE + 4*0x30) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_CONTROL (JECS_PMA1_BROADCAST_BASE + 4*0x31) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_CONTROL_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x32) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_RECAL_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x40) //Attributes : RW +#define JECS_PMA1_BROADCAST_RECEIVER_RECAL_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x41) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANSMITTER_REQ (JECS_PMA1_BROADCAST_BASE + 4*0x50) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANSMITTER_REQ_ACK (JECS_PMA1_BROADCAST_BASE + 4*0x51) //Attributes : RO +#define JECS_PMA1_BROADCAST_TRANSMITTER_REQ_PARAM1 (JECS_PMA1_BROADCAST_BASE + 4*0x52) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANSMITTER_REQ_PARAM2 (JECS_PMA1_BROADCAST_BASE + 4*0x53) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANSMITTER_REQ_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x55) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_EN (JECS_PMA1_BROADCAST_BASE + 4*0x60) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_CLKRDY (JECS_PMA1_BROADCAST_BASE + 4*0x61) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_SETTING (JECS_PMA1_BROADCAST_BASE + 4*0x62) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x63) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANSMITTER_CONTROL1 (JECS_PMA1_BROADCAST_BASE + 4*0x70) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANSMITTER_CONTROL2 (JECS_PMA1_BROADCAST_BASE + 4*0x71) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANSMITTER_CONTROL_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x72) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANSMITTER_EQ1 (JECS_PMA1_BROADCAST_BASE + 4*0x80) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANSMITTER_EQ2 (JECS_PMA1_BROADCAST_BASE + 4*0x81) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANSMITTER_EQ3 (JECS_PMA1_BROADCAST_BASE + 4*0x82) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANSMITTER_EQ_MUX_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x83) //Attributes : RW +#define JECS_PMA1_BROADCAST_CONTEXT_RESTORE_CTRL1 (JECS_PMA1_BROADCAST_BASE + 4*0x90) //Attributes : RW +#define JECS_PMA1_BROADCAST_CONTEXT_RESTORE_CTRL2 (JECS_PMA1_BROADCAST_BASE + 4*0x91) //Attributes : RW +#define JECS_PMA1_BROADCAST_CONTEXT_RESTORE_CTRL3 (JECS_PMA1_BROADCAST_BASE + 4*0x92) //Attributes : RW +#define JECS_PMA1_BROADCAST_CONTEXT_RESTORE_CTRL4 (JECS_PMA1_BROADCAST_BASE + 4*0x93) //Attributes : RW +#define JECS_PMA1_BROADCAST_CONTEXT_RESTORE_MUX (JECS_PMA1_BROADCAST_BASE + 4*0x94) //Attributes : RW +#define JECS_PMA1_BROADCAST_LANE_REFCLK_SEL (JECS_PMA1_BROADCAST_BASE + 4*0xA0) //Attributes : RW +#define JECS_PMA1_BROADCAST_ETH_CLK_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xB0) //Attributes : RW +#define JECS_PMA1_BROADCAST_ETH_CLK_CTRL_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xB1) //Attributes : RW +#define JECS_PMA1_BROADCAST_RX_ADAPT_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xC0) //Attributes : RW +#define JECS_PMA1_BROADCAST_RX_DCC_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xC1) //Attributes : RW +#define JECS_PMA1_BROADCAST_RX_EQ_CTRL1 (JECS_PMA1_BROADCAST_BASE + 4*0xC2) //Attributes : RW +#define JECS_PMA1_BROADCAST_RX_EQ_CTRL2 (JECS_PMA1_BROADCAST_BASE + 4*0xC3) //Attributes : RW +#define JECS_PMA1_BROADCAST_RX_MARGIN_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xC4) //Attributes : RW +#define JECS_PMA1_BROADCAST_RX_MARGIN_ERROR (JECS_PMA1_BROADCAST_BASE + 4*0xC5) //Attributes : RO +#define JECS_PMA1_BROADCAST_RECV_REQUEST_CTRL_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xC6) //Attributes : RW +#define JECS_PMA1_BROADCAST_RX_COARSE_ADAPT_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xC8) //Attributes : RW +#define JECS_PMA1_BROADCAST_RX_COARSE_ADAPT_CTRL_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xC9) //Attributes : RW +#define JECS_PMA1_BROADCAST_RX_DIV_CLK_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xCA) //Attributes : RW +#define JECS_PMA1_BROADCAST_TX_DIV_CLK_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xCB) //Attributes : RW +#define JECS_PMA1_BROADCAST_MULTI_CLK_CTRL_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xCC) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANS_REQ_CTRL1 (JECS_PMA1_BROADCAST_BASE + 4*0xD0) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANS_REQ_CTRL2 (JECS_PMA1_BROADCAST_BASE + 4*0xD1) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANS_REQ_CTRL3 (JECS_PMA1_BROADCAST_BASE + 4*0xD2) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANS_REQ_CTRL4 (JECS_PMA1_BROADCAST_BASE + 4*0xD3) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANS_REQ_CTRL5 (JECS_PMA1_BROADCAST_BASE + 4*0xD4) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANS_REQ_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xD5) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANS_INTERFACE_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xD6) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANS_INTERFACE_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xD7) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANS_MASTER_PLL_STATE (JECS_PMA1_BROADCAST_BASE + 4*0xD8) //Attributes : RW +#define JECS_PMA1_BROADCAST_TRANS_PLL_STATE (JECS_PMA1_BROADCAST_BASE + 4*0xD9) //Attributes : RO +#define JECS_PMA1_BROADCAST_PLL_STATE_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xDA) //Attributes : RW +#define JECS_PMA1_BROADCAST_RX_VALID_PHY (JECS_PMA1_BROADCAST_BASE + 4*0xDF) //Attributes : RO +#define JECS_PMA1_BROADCAST_RX_VALID_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xE0) //Attributes : RW +#define JECS_PMA1_BROADCAST_RX_SRIO_SIGDET_MUX (JECS_PMA1_BROADCAST_BASE + 4*0xE1) //Attributes : RW +#define JECS_PMA1_BROADCAST_SRIO_DEGRADED (JECS_PMA1_BROADCAST_BASE + 4*0xE2) //Attributes : RW +#define JECS_PMA1_BROADCAST_SRIO_RETRAIN (JECS_PMA1_BROADCAST_BASE + 4*0xE3) //Attributes : RW +#define JECS_PMA1_BROADCAST_SRIO_SHORT_RUN (JECS_PMA1_BROADCAST_BASE + 4*0xE4) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_INIT_C0 (JECS_PMA1_BROADCAST_BASE + 4*0xE5) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_INIT_CN1 (JECS_PMA1_BROADCAST_BASE + 4*0xE6) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_INIT_CP1 (JECS_PMA1_BROADCAST_BASE + 4*0xE7) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_RULE_CTRL_1 (JECS_PMA1_BROADCAST_BASE + 4*0xE8) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_RULE_CTRL_2 (JECS_PMA1_BROADCAST_BASE + 4*0xE9) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_RULE_CTRL_3 (JECS_PMA1_BROADCAST_BASE + 4*0xEA) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_RULE_CTRL_4 (JECS_PMA1_BROADCAST_BASE + 4*0xEB) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_ALGORITHM_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xEC) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_TX_TRAIN_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xED) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_ADJ_INTERVAL (JECS_PMA1_BROADCAST_BASE + 4*0xEE) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_RX_REQ_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xEF) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_RX_TRAIN_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0xF0) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_RX_RESET_CYCLE (JECS_PMA1_BROADCAST_BASE + 4*0xF1) //Attributes : RW +#define JECS_PMA1_BROADCAST_RPCS_KTR_STATUS (JECS_PMA1_BROADCAST_BASE + 4*0xF2) //Attributes : RO +#define JECS_PMA1_BROADCAST_EQ_FSM (JECS_PMA1_BROADCAST_BASE + 4*0xF3) //Attributes : RO +#define JECS_PMA1_BROADCAST_ETH_RX_LOS (JECS_PMA1_BROADCAST_BASE + 4*0xF4) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_PRESET_C0 (JECS_PMA1_BROADCAST_BASE + 4*0xF5) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_PRESET_CN1 (JECS_PMA1_BROADCAST_BASE + 4*0xF6) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_PRESET_CP1 (JECS_PMA1_BROADCAST_BASE + 4*0xF7) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_SUCC_MASK (JECS_PMA1_BROADCAST_BASE + 4*0xF8) //Attributes : RW +#define JECS_PMA1_BROADCAST_PMA_COM_SCRATCH (JECS_PMA1_BROADCAST_BASE + 4*0xff) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY0 (JECS_PMA1_BROADCAST_BASE + 4*0x100) //Attributes : RO_EXT_L +#define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY1 (JECS_PMA1_BROADCAST_BASE + 4*0x101) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY2 (JECS_PMA1_BROADCAST_BASE + 4*0x102) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY3 (JECS_PMA1_BROADCAST_BASE + 4*0x103) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY4 (JECS_PMA1_BROADCAST_BASE + 4*0x104) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY5 (JECS_PMA1_BROADCAST_BASE + 4*0x105) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY6 (JECS_PMA1_BROADCAST_BASE + 4*0x106) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY7 (JECS_PMA1_BROADCAST_BASE + 4*0x107) //Attributes : RO_EXT_H +#define JECS_PMA1_BROADCAST_EQ_TX_FSM_HISTORY_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x108) //Attributes : RW +#define JECS_PMA1_BROADCAST_EQ_RX_FSM_HISTORY0 (JECS_PMA1_BROADCAST_BASE + 4*0x109) //Attributes : RO_EXT_L +#define JECS_PMA1_BROADCAST_EQ_RX_FSM_HISTORY1 (JECS_PMA1_BROADCAST_BASE + 4*0x10A) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_EQ_RX_FSM_HISTORY2 (JECS_PMA1_BROADCAST_BASE + 4*0x10B) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_EQ_RX_FSM_HISTORY3 (JECS_PMA1_BROADCAST_BASE + 4*0x10C) //Attributes : RO_EXT_H +#define JECS_PMA1_BROADCAST_EQ_RX_FSM_HISTORY_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x10D) //Attributes : RW +#define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY0 (JECS_PMA1_BROADCAST_BASE + 4*0x110) //Attributes : RO_EXT_L +#define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY1 (JECS_PMA1_BROADCAST_BASE + 4*0x111) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY2 (JECS_PMA1_BROADCAST_BASE + 4*0x112) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY3 (JECS_PMA1_BROADCAST_BASE + 4*0x113) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY4 (JECS_PMA1_BROADCAST_BASE + 4*0x114) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY5 (JECS_PMA1_BROADCAST_BASE + 4*0x115) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY6 (JECS_PMA1_BROADCAST_BASE + 4*0x116) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY7 (JECS_PMA1_BROADCAST_BASE + 4*0x117) //Attributes : RO_EXT_H +#define JECS_PMA1_BROADCAST_TX_EQ_MAIN_HISTORY_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x118) //Attributes : RW +#define JECS_PMA1_BROADCAST_RX_TXMAIN_DIR_HISTORY0 (JECS_PMA1_BROADCAST_BASE + 4*0x119) //Attributes : RO_EXT_L +#define JECS_PMA1_BROADCAST_RX_TXMAIN_DIR_HISTORY1 (JECS_PMA1_BROADCAST_BASE + 4*0x11A) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_RX_TXMAIN_DIR_HISTORY2 (JECS_PMA1_BROADCAST_BASE + 4*0x11B) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_RX_TXMAIN_DIR_HISTORY3 (JECS_PMA1_BROADCAST_BASE + 4*0x11C) //Attributes : RO_EXT_H +#define JECS_PMA1_BROADCAST_RX_TXMAIN_DIR_HISTORY_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x11D) //Attributes : RW +#define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY0 (JECS_PMA1_BROADCAST_BASE + 4*0x120) //Attributes : RO_EXT_L +#define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY1 (JECS_PMA1_BROADCAST_BASE + 4*0x121) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY2 (JECS_PMA1_BROADCAST_BASE + 4*0x122) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY3 (JECS_PMA1_BROADCAST_BASE + 4*0x123) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY4 (JECS_PMA1_BROADCAST_BASE + 4*0x124) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY5 (JECS_PMA1_BROADCAST_BASE + 4*0x125) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY6 (JECS_PMA1_BROADCAST_BASE + 4*0x126) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY7 (JECS_PMA1_BROADCAST_BASE + 4*0x127) //Attributes : RO_EXT_H +#define JECS_PMA1_BROADCAST_TX_EQ_POST_HISTORY_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x128) //Attributes : RW +#define JECS_PMA1_BROADCAST_RX_TXPOST_DIR_HISTORY0 (JECS_PMA1_BROADCAST_BASE + 4*0x129) //Attributes : RO_EXT_L +#define JECS_PMA1_BROADCAST_RX_TXPOST_DIR_HISTORY1 (JECS_PMA1_BROADCAST_BASE + 4*0x12A) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_RX_TXPOST_DIR_HISTORY2 (JECS_PMA1_BROADCAST_BASE + 4*0x12B) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_RX_TXPOST_DIR_HISTORY3 (JECS_PMA1_BROADCAST_BASE + 4*0x12C) //Attributes : RO_EXT_H +#define JECS_PMA1_BROADCAST_RX_TXPOST_DIR_HISTORY_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x12D) //Attributes : RW +#define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY0 (JECS_PMA1_BROADCAST_BASE + 4*0x130) //Attributes : RO_EXT_L +#define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY1 (JECS_PMA1_BROADCAST_BASE + 4*0x131) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY2 (JECS_PMA1_BROADCAST_BASE + 4*0x132) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY3 (JECS_PMA1_BROADCAST_BASE + 4*0x133) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY4 (JECS_PMA1_BROADCAST_BASE + 4*0x134) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY5 (JECS_PMA1_BROADCAST_BASE + 4*0x135) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY6 (JECS_PMA1_BROADCAST_BASE + 4*0x136) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY7 (JECS_PMA1_BROADCAST_BASE + 4*0x137) //Attributes : RO_EXT_H +#define JECS_PMA1_BROADCAST_TX_EQ_PRE_HISTORY_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x138) //Attributes : RW +#define JECS_PMA1_BROADCAST_RX_TXPRE_DIR_HISTORY0 (JECS_PMA1_BROADCAST_BASE + 4*0x139) //Attributes : RO_EXT_L +#define JECS_PMA1_BROADCAST_RX_TXPRE_DIR_HISTORY1 (JECS_PMA1_BROADCAST_BASE + 4*0x13A) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_RX_TXPRE_DIR_HISTORY2 (JECS_PMA1_BROADCAST_BASE + 4*0x13B) //Attributes : RO_EXT +#define JECS_PMA1_BROADCAST_RX_TXPRE_DIR_HISTORY3 (JECS_PMA1_BROADCAST_BASE + 4*0x13C) //Attributes : RO_EXT_H +#define JECS_PMA1_BROADCAST_RX_TXPRE_DIR_HISTORY_CTRL (JECS_PMA1_BROADCAST_BASE + 4*0x13D) //Attributes : RW + +//The PMA COMMON Register +#define JECS_PMA1_MPLLA_PARAM1 (JECS_PMA1_COMMON_BASE + 4*0x00) //Attributes : RW +#define JECS_PMA1_MPLLA_PARAM2 (JECS_PMA1_COMMON_BASE + 4*0x01) //Attributes : RW +#define JECS_PMA1_MPLLA_PARAM3 (JECS_PMA1_COMMON_BASE + 4*0x02) //Attributes : RW +#define JECS_PMA1_MPLLA_PARAM4 (JECS_PMA1_COMMON_BASE + 4*0x03) //Attributes : RW +#define JECS_PMA1_MPLLA_PARAM5 (JECS_PMA1_COMMON_BASE + 4*0x04) //Attributes : RW +#define JECS_PMA1_MPLLA_PARAM6 (JECS_PMA1_COMMON_BASE + 4*0x05) //Attributes : RW +#define JECS_PMA1_MPLLA_FORCE_EN (JECS_PMA1_COMMON_BASE + 4*0x06) //Attributes : RW +#define JECS_PMA1_MPLLA_FORCE_ACK (JECS_PMA1_COMMON_BASE + 4*0x07) //Attributes : RO +#define JECS_PMA1_MPLLB_PARAM1 (JECS_PMA1_COMMON_BASE + 4*0x08) //Attributes : RW +#define JECS_PMA1_MPLLB_PARAM2 (JECS_PMA1_COMMON_BASE + 4*0x09) //Attributes : RW +#define JECS_PMA1_MPLLB_PARAM3 (JECS_PMA1_COMMON_BASE + 4*0x0A) //Attributes : RW +#define JECS_PMA1_MPLLB_PARAM4 (JECS_PMA1_COMMON_BASE + 4*0x0B) //Attributes : RW +#define JECS_PMA1_MPLLB_PARAM5 (JECS_PMA1_COMMON_BASE + 4*0x0C) //Attributes : RW +#define JECS_PMA1_MPLLB_PARAM6 (JECS_PMA1_COMMON_BASE + 4*0x0D) //Attributes : RW +#define JECS_PMA1_MPLLB_FORCE_EN (JECS_PMA1_COMMON_BASE + 4*0x0E) //Attributes : RW +#define JECS_PMA1_MPLLB_FORCE_ACK (JECS_PMA1_COMMON_BASE + 4*0x0F) //Attributes : RO +#define JECS_PMA1_SUP_MISC (JECS_PMA1_COMMON_BASE + 4*0x16) //Attributes : RW +#define JECS_PMA1_MPLLA_FRAC_CTRL1 (JECS_PMA1_COMMON_BASE + 4*0x17) //Attributes : RW +#define JECS_PMA1_MPLLA_FRAC_CTRL2 (JECS_PMA1_COMMON_BASE + 4*0x18) //Attributes : RW +#define JECS_PMA1_MPLLA_FRAC_CTRL3 (JECS_PMA1_COMMON_BASE + 4*0x19) //Attributes : RW +#define JECS_PMA1_MPLLA_FRAC_CTRL4 (JECS_PMA1_COMMON_BASE + 4*0x1A) //Attributes : RW +#define JECS_PMA1_MPLLA_SSC_CTRL1 (JECS_PMA1_COMMON_BASE + 4*0x1B) //Attributes : RW +#define JECS_PMA1_MPLLA_SSC_CTRL2 (JECS_PMA1_COMMON_BASE + 4*0x1C) //Attributes : RW_EXT_L +#define JECS_PMA1_MPLLA_SSC_CTRL3 (JECS_PMA1_COMMON_BASE + 4*0x1D) //Attributes : RW_EXT_H +#define JECS_PMA1_MPLLA_SSC_CTRL4 (JECS_PMA1_COMMON_BASE + 4*0x1E) //Attributes : RW +#define JECS_PMA1_MPLLA_SSC_CTRL5 (JECS_PMA1_COMMON_BASE + 4*0x1F) //Attributes : RW_EXT_L +#define JECS_PMA1_MPLLA_SSC_CTRL6 (JECS_PMA1_COMMON_BASE + 4*0x20) //Attributes : RW_EXT_H +#define JECS_PMA1_MPLLB_FRAC_CTRL1 (JECS_PMA1_COMMON_BASE + 4*0x21) //Attributes : RW +#define JECS_PMA1_MPLLB_FRAC_CTRL2 (JECS_PMA1_COMMON_BASE + 4*0x22) //Attributes : RW +#define JECS_PMA1_MPLLB_FRAC_CTRL3 (JECS_PMA1_COMMON_BASE + 4*0x23) //Attributes : RW +#define JECS_PMA1_MPLLB_FRAC_CTRL4 (JECS_PMA1_COMMON_BASE + 4*0x24) //Attributes : RW +#define JECS_PMA1_MPLLB_SSC_CTRL1 (JECS_PMA1_COMMON_BASE + 4*0x25) //Attributes : RW +#define JECS_PMA1_MPLLB_SSC_CTRL2 (JECS_PMA1_COMMON_BASE + 4*0x26) //Attributes : RW_EXT_L +#define JECS_PMA1_MPLLB_SSC_CTRL3 (JECS_PMA1_COMMON_BASE + 4*0x27) //Attributes : RW_EXT_H +#define JECS_PMA1_MPLLB_SSC_CTRL4 (JECS_PMA1_COMMON_BASE + 4*0x28) //Attributes : RW +#define JECS_PMA1_MPLLB_SSC_CTRL5 (JECS_PMA1_COMMON_BASE + 4*0x29) //Attributes : RW_EXT_L +#define JECS_PMA1_MPLLB_SSC_CTRL6 (JECS_PMA1_COMMON_BASE + 4*0x2A) //Attributes : RW_EXT_H +#define JECS_PMA1_MPLLA_RECAL_CTRL (JECS_PMA1_COMMON_BASE + 4*0x2B) //Attributes : RW +#define JECS_PMA1_MPLLB_RECAL_CTRL (JECS_PMA1_COMMON_BASE + 4*0x2C) //Attributes : RW +#define JECS_PMA1_MPLL_CTRL_MUX (JECS_PMA1_COMMON_BASE + 4*0x2D) //Attributes : RW +#define JECS_PMA1_POWER_SUPPLY_SEL (JECS_PMA1_COMMON_BASE + 4*0x30) //Attributes : RW +#define JECS_PMA1_PHY_RESET (JECS_PMA1_COMMON_BASE + 4*0x31) //Attributes : RW +#define JECS_PMA1_REF_CLK_CTRL (JECS_PMA1_COMMON_BASE + 4*0x40) //Attributes : RW +#define JECS_PMA1_REFA_CLK_CTRL1 (JECS_PMA1_COMMON_BASE + 4*0x41) //Attributes : RW +#define JECS_PMA1_REFA_CLK_CTRL2 (JECS_PMA1_COMMON_BASE + 4*0x42) //Attributes : RW +#define JECS_PMA1_REFA_CLK_STATUS (JECS_PMA1_COMMON_BASE + 4*0x43) //Attributes : RO +#define JECS_PMA1_REFB_CLK_CTRL1 (JECS_PMA1_COMMON_BASE + 4*0x44) //Attributes : RW +#define JECS_PMA1_REFB_CLK_CTRL2 (JECS_PMA1_COMMON_BASE + 4*0x45) //Attributes : RW +#define JECS_PMA1_REFB_CLK_STATUS (JECS_PMA1_COMMON_BASE + 4*0x46) //Attributes : RO +#define JECS_PMA1_REF_CLK_MUX (JECS_PMA1_COMMON_BASE + 4*0x47) //Attributes : RW +#define JECS_PMA1_RES_ACK_IN (JECS_PMA1_COMMON_BASE + 4*0x50) //Attributes : RW +#define JECS_PMA1_RES_ACK_OUT (JECS_PMA1_COMMON_BASE + 4*0x51) //Attributes : RO +#define JECS_PMA1_RES_REQ_IN (JECS_PMA1_COMMON_BASE + 4*0x52) //Attributes : RW +#define JECS_PMA1_RES_REQ_OUT (JECS_PMA1_COMMON_BASE + 4*0x53) //Attributes : RO +#define JECS_PMA1_RTUNE_REQ (JECS_PMA1_COMMON_BASE + 4*0x54) //Attributes : RW +#define JECS_PMA1_RTUNE_ACK (JECS_PMA1_COMMON_BASE + 4*0x55) //Attributes : RO +#define JECS_PMA1_RTUNE_CTRL1 (JECS_PMA1_COMMON_BASE + 4*0x56) //Attributes : RW +#define JECS_PMA1_RTUNE_CTRL2 (JECS_PMA1_COMMON_BASE + 4*0x57) //Attributes : RW +#define JECS_PMA1_RTUNE_CTRL3 (JECS_PMA1_COMMON_BASE + 4*0x58) //Attributes : RW +#define JECS_PMA1_RX_BIAS_CURRENT_CTRL (JECS_PMA1_COMMON_BASE + 4*0x59) //Attributes : RW +#define JECS_PMA1_CR_PARA_SEL (JECS_PMA1_COMMON_BASE + 4*0x90) //Attributes : RW +#define JECS_PMA1_POWER_GATING_SIGNAL1 (JECS_PMA1_COMMON_BASE + 4*0x60) //Attributes : RW +#define JECS_PMA1_POWER_GATING_SIGNAL2 (JECS_PMA1_COMMON_BASE + 4*0x61) //Attributes : RO +#define JECS_PMA1_POWER_GATING_SIGNAL3 (JECS_PMA1_COMMON_BASE + 4*0x62) //Attributes : RW +#define JECS_PMA1_SRAM_CTRL (JECS_PMA1_COMMON_BASE + 4*0x68) //Attributes : RW +#define JECS_PMA1_SRAM_STATUS (JECS_PMA1_COMMON_BASE + 4*0x69) //Attributes : RO +#define JECS_PMA1_SRIO_RST_REQ (JECS_PMA1_COMMON_BASE + 4*0x6A) //Attributes : RO +#define JECS_PMA1_SRIO_GEN3_EN (JECS_PMA1_COMMON_BASE + 4*0x6C) //Attributes : RW +#define JECS_PMA1_SRIO_RATE_OUT (JECS_PMA1_COMMON_BASE + 4*0x6D) //Attributes : RW +#define JECS_PMA1_CPRI_RST_REQ (JECS_PMA1_COMMON_BASE + 4*0x70) //Attributes : RW +#define JECS_PMA1_CPRI_RX_LOS (JECS_PMA1_COMMON_BASE + 4*0x71) //Attributes : RW +#define JECS_PMA1_CPRI_SIGNAL_OK (JECS_PMA1_COMMON_BASE + 4*0x72) //Attributes : RW +#define JECS_PMA1_CPRI_ENERGY_DET (JECS_PMA1_COMMON_BASE + 4*0x73) //Attributes : RW +#define JECS_PMA1_CPRI_SIGDET (JECS_PMA1_COMMON_BASE + 4*0x74) //Attributes : RW +#define JECS_PMA1_CPRI_PCS_STATUS (JECS_PMA1_COMMON_BASE + 4*0x75) //Attributes : RO +#define JECS_PMA1_CPRI_PCS_STATUS_CTRL (JECS_PMA1_COMMON_BASE + 4*0x76) //Attributes : RW +#define JECS_PMA1_ETH_ENERGY_DET (JECS_PMA1_COMMON_BASE + 4*0x80) //Attributes : RW +#define JECS_PMA1_ETH_SPEED_CTRL (JECS_PMA1_COMMON_BASE + 4*0x81) //Attributes : RO +#define JECS_PMA1_TX_CLK_SEL (JECS_PMA1_COMMON_BASE + 4*0xF0) //Attributes : RW +#define JECS_PMA1_RPCS_TX_CLK_SEL (JECS_PMA1_COMMON_BASE + 4*0xF1) //Attributes : RW +#define JECS_PMA1_RPCS_RX_CLK_SEL (JECS_PMA1_COMMON_BASE + 4*0xF2) //Attributes : RW +#define JECS_PMA1_PMA_COM_SCRATCH (JECS_PMA1_COMMON_BASE + 4*0xff) //Attributes : RW + +//The PMA PCS Register +#define JECS_PMA1_PCS_SOFT_RESET (JECS_PMA1_PCS_BASE + 4*0x00) //Attributes : RW +#define JECS_PMA1_PCS_LOOPBACK_CTRL (JECS_PMA1_PCS_BASE + 4*0x04) //Attributes : RW +#define JECS_PMA1_PCS_PRBS_UDP_SEND (JECS_PMA1_PCS_BASE + 4*0x05) //Attributes : RW +#define JECS_PMA1_PCS_PRBS_SEND_ERRINS (JECS_PMA1_PCS_BASE + 4*0x06) //Attributes : RW +#define JECS_PMA1_PCS_TXUDP_0 (JECS_PMA1_PCS_BASE + 4*0x07) //Attributes : RW_EXT_L +#define JECS_PMA1_PCS_TXUDP_1 (JECS_PMA1_PCS_BASE + 4*0x08) //Attributes : RW_EXT +#define JECS_PMA1_PCS_TXUDP_2 (JECS_PMA1_PCS_BASE + 4*0x09) //Attributes : RW_EXT +#define JECS_PMA1_PCS_TXUDP_3 (JECS_PMA1_PCS_BASE + 4*0x0A) //Attributes : RW_EXT +#define JECS_PMA1_PCS_TXUDP_4 (JECS_PMA1_PCS_BASE + 4*0x0B) //Attributes : RW_EXT_H +#define JECS_PMA1_PCS_PRBS_UDP_CHK (JECS_PMA1_PCS_BASE + 4*0x10) //Attributes : RW +#define JECS_PMA1_PCS_RXUDP_0 (JECS_PMA1_PCS_BASE + 4*0x11) //Attributes : RW_EXT_L +#define JECS_PMA1_PCS_RXUDP_1 (JECS_PMA1_PCS_BASE + 4*0x12) //Attributes : RW_EXT +#define JECS_PMA1_PCS_RXUDP_2 (JECS_PMA1_PCS_BASE + 4*0x13) //Attributes : RW_EXT +#define JECS_PMA1_PCS_RXUDP_3 (JECS_PMA1_PCS_BASE + 4*0x14) //Attributes : RW_EXT +#define JECS_PMA1_PCS_RXUDP_4 (JECS_PMA1_PCS_BASE + 4*0x15) //Attributes : RW_EXT_H +#define JECS_PMA1_PCS_RXPRBS_ERRCNT_L0 (JECS_PMA1_PCS_BASE + 4*0x16) //Attributes : RO +#define JECS_PMA1_PCS_RXPRBS_ERRCNT_L1 (JECS_PMA1_PCS_BASE + 4*0x17) //Attributes : RO +#define JECS_PMA1_PCS_RXPRBS_ERRCNT_L2 (JECS_PMA1_PCS_BASE + 4*0x18) //Attributes : RO +#define JECS_PMA1_PCS_RXPRBS_ERRCNT_L3 (JECS_PMA1_PCS_BASE + 4*0x19) //Attributes : RO +#define JECS_PMA1_PCS_NELP_FIFO_STATUS (JECS_PMA1_PCS_BASE + 4*0x20) //Attributes : RO +#define JECS_PMA1_PCS_FELP_FIFO_STATUS (JECS_PMA1_PCS_BASE + 4*0x21) //Attributes : RO +#define JECS_PMA1_PCS_BIT_REV_CTRL (JECS_PMA1_PCS_BASE + 4*0x22) //Attributes : RW +#define JECS_PMA1_PCS_SOFT_PON_RST (JECS_PMA1_PCS_BASE + 4*0xfe) //Attributes : RW +#define JECS_PMA1_PCS_PCS_SCRATCH (JECS_PMA1_PCS_BASE + 4*0xff) //Attributes : RW + +//------------------------PET SUBSYSTEM -------------------------// +//The PMA Lane Config Base Addr +#define PET_PMA3_LANE0_BASE PET_PMA3_CFG + 0x10000*4 +#define PET_PMA3_LANE1_BASE PET_PMA3_CFG + 0x10800*4 +#define PET_PMA3_LANE2_BASE PET_PMA3_CFG + 0x11000*4 +#define PET_PMA3_LANE3_BASE PET_PMA3_CFG + 0x11800*4 +#define PET_PMA3_BROADCAST_BASE PET_PMA3_CFG + 0x12000*4 +//The PMA COMMON Base Addr +#define PET_PMA3_COMMON_BASE PET_PMA3_CFG + 0x14000*4 + +//The PMA PCS Addr +#define PET_PMA3_PCS_BASE PET_PMA3_CFG + 0x18000*4 + + +//The PMA Lane Config Register +#define PET_PMA3_LANE0_PMA_LOOPBACK_CTRL (PET_PMA3_LANE0_BASE + 4*0x00) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_REQ (PET_PMA3_LANE0_BASE + 4*0x01) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_REQ_ACK (PET_PMA3_LANE0_BASE + 4*0x02) //Attributes : RO +#define PET_PMA3_LANE0_RECEIVER_REQ_PARAM2 (PET_PMA3_LANE0_BASE + 4*0x03) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_REQ_PARAM3 (PET_PMA3_LANE0_BASE + 4*0x04) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_REQ_PARAM4 (PET_PMA3_LANE0_BASE + 4*0x05) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_REQ_PARAM5 (PET_PMA3_LANE0_BASE + 4*0x06) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_REQ_PARAM6 (PET_PMA3_LANE0_BASE + 4*0x07) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_REQ_PARAM7 (PET_PMA3_LANE0_BASE + 4*0x08) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_REQ_PARAM8 (PET_PMA3_LANE0_BASE + 4*0x09) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_REQ_PARAM9 (PET_PMA3_LANE0_BASE + 4*0x0A) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_REQ_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x0B) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_ADAPT_REQ (PET_PMA3_LANE0_BASE + 4*0x10) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_ADAPT_REQ_ACK (PET_PMA3_LANE0_BASE + 4*0x11) //Attributes : RO +#define PET_PMA3_LANE0_RECEIVER_ADAPT_DIR (PET_PMA3_LANE0_BASE + 4*0x12) //Attributes : RO +#define PET_PMA3_LANE0_RECEIVER_ADAPT_SETTING (PET_PMA3_LANE0_BASE + 4*0x13) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_ADAPT_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x14) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_DATAPATH_EN (PET_PMA3_LANE0_BASE + 4*0x20) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_DATAPATH_SETTING1 (PET_PMA3_LANE0_BASE + 4*0x21) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_DATAPATH_SETTING2 (PET_PMA3_LANE0_BASE + 4*0x22) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_DATAPATH_SETTING3 (PET_PMA3_LANE0_BASE + 4*0x23) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_DATAPATH_STATUS1 (PET_PMA3_LANE0_BASE + 4*0x24) //Attributes : RO +#define PET_PMA3_LANE0_RECEIVER_DATAPATH_STATUS2 (PET_PMA3_LANE0_BASE + 4*0x25) //Attributes : RO +#define PET_PMA3_LANE0_RECEIVER_DATAPATH_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x26) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_RESET (PET_PMA3_LANE0_BASE + 4*0x30) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_CONTROL (PET_PMA3_LANE0_BASE + 4*0x31) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_CONTROL_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x32) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_RECAL_CTRL (PET_PMA3_LANE0_BASE + 4*0x40) //Attributes : RW +#define PET_PMA3_LANE0_RECEIVER_RECAL_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x41) //Attributes : RW +#define PET_PMA3_LANE0_TRANSMITTER_REQ (PET_PMA3_LANE0_BASE + 4*0x50) //Attributes : RW +#define PET_PMA3_LANE0_TRANSMITTER_REQ_ACK (PET_PMA3_LANE0_BASE + 4*0x51) //Attributes : RO +#define PET_PMA3_LANE0_TRANSMITTER_REQ_PARAM1 (PET_PMA3_LANE0_BASE + 4*0x52) //Attributes : RW +#define PET_PMA3_LANE0_TRANSMITTER_REQ_PARAM2 (PET_PMA3_LANE0_BASE + 4*0x53) //Attributes : RW +#define PET_PMA3_LANE0_TRANSMITTER_REQ_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x55) //Attributes : RW +#define PET_PMA3_LANE0_TRANSMITTER_DATAPATH_EN (PET_PMA3_LANE0_BASE + 4*0x60) //Attributes : RW +#define PET_PMA3_LANE0_TRANSMITTER_DATAPATH_CLKRDY (PET_PMA3_LANE0_BASE + 4*0x61) //Attributes : RW +#define PET_PMA3_LANE0_TRANSMITTER_DATAPATH_SETTING (PET_PMA3_LANE0_BASE + 4*0x62) //Attributes : RW +#define PET_PMA3_LANE0_TRANSMITTER_DATAPATH_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x63) //Attributes : RW +#define PET_PMA3_LANE0_TRANSMITTER_CONTROL1 (PET_PMA3_LANE0_BASE + 4*0x70) //Attributes : RW +#define PET_PMA3_LANE0_TRANSMITTER_CONTROL2 (PET_PMA3_LANE0_BASE + 4*0x71) //Attributes : RW +#define PET_PMA3_LANE0_TRANSMITTER_CONTROL_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x72) //Attributes : RW +#define PET_PMA3_LANE0_TRANSMITTER_EQ1 (PET_PMA3_LANE0_BASE + 4*0x80) //Attributes : RW +#define PET_PMA3_LANE0_TRANSMITTER_EQ2 (PET_PMA3_LANE0_BASE + 4*0x81) //Attributes : RW +#define PET_PMA3_LANE0_TRANSMITTER_EQ3 (PET_PMA3_LANE0_BASE + 4*0x82) //Attributes : RW +#define PET_PMA3_LANE0_TRANSMITTER_EQ_MUX_CTRL (PET_PMA3_LANE0_BASE + 4*0x83) //Attributes : RW +#define PET_PMA3_LANE0_CONTEXT_RESTORE_CTRL1 (PET_PMA3_LANE0_BASE + 4*0x90) //Attributes : RW +#define PET_PMA3_LANE0_CONTEXT_RESTORE_CTRL2 (PET_PMA3_LANE0_BASE + 4*0x91) //Attributes : RW +#define PET_PMA3_LANE0_CONTEXT_RESTORE_CTRL3 (PET_PMA3_LANE0_BASE + 4*0x92) //Attributes : RW +#define PET_PMA3_LANE0_CONTEXT_RESTORE_CTRL4 (PET_PMA3_LANE0_BASE + 4*0x93) //Attributes : RW +#define PET_PMA3_LANE0_CONTEXT_RESTORE_MUX (PET_PMA3_LANE0_BASE + 4*0x94) //Attributes : RW +#define PET_PMA3_LANE0_LANE_REFCLK_SEL (PET_PMA3_LANE0_BASE + 4*0xA0) //Attributes : RW +#define PET_PMA3_LANE0_ETH_CLK_CTRL (PET_PMA3_LANE0_BASE + 4*0xB0) //Attributes : RW +#define PET_PMA3_LANE0_ETH_CLK_CTRL_MUX (PET_PMA3_LANE0_BASE + 4*0xB1) //Attributes : RW +#define PET_PMA3_LANE0_RX_ADAPT_CTRL (PET_PMA3_LANE0_BASE + 4*0xC0) //Attributes : RW +#define PET_PMA3_LANE0_RX_DCC_CTRL (PET_PMA3_LANE0_BASE + 4*0xC1) //Attributes : RW +#define PET_PMA3_LANE0_RX_EQ_CTRL1 (PET_PMA3_LANE0_BASE + 4*0xC2) //Attributes : RW +#define PET_PMA3_LANE0_RX_EQ_CTRL2 (PET_PMA3_LANE0_BASE + 4*0xC3) //Attributes : RW +#define PET_PMA3_LANE0_RX_MARGIN_CTRL (PET_PMA3_LANE0_BASE + 4*0xC4) //Attributes : RW +#define PET_PMA3_LANE0_RX_MARGIN_ERROR (PET_PMA3_LANE0_BASE + 4*0xC5) //Attributes : RO +#define PET_PMA3_LANE0_RECV_REQUEST_CTRL_MUX (PET_PMA3_LANE0_BASE + 4*0xC6) //Attributes : RW +#define PET_PMA3_LANE0_RX_COARSE_ADAPT_CTRL (PET_PMA3_LANE0_BASE + 4*0xC8) //Attributes : RW +#define PET_PMA3_LANE0_RX_COARSE_ADAPT_CTRL_MUX (PET_PMA3_LANE0_BASE + 4*0xC9) //Attributes : RW +#define PET_PMA3_LANE0_RX_DIV_CLK_CTRL (PET_PMA3_LANE0_BASE + 4*0xCA) //Attributes : RW +#define PET_PMA3_LANE0_TX_DIV_CLK_CTRL (PET_PMA3_LANE0_BASE + 4*0xCB) //Attributes : RW +#define PET_PMA3_LANE0_MULTI_CLK_CTRL_MUX (PET_PMA3_LANE0_BASE + 4*0xCC) //Attributes : RW +#define PET_PMA3_LANE0_TRANS_REQ_CTRL1 (PET_PMA3_LANE0_BASE + 4*0xD0) //Attributes : RW +#define PET_PMA3_LANE0_TRANS_REQ_CTRL2 (PET_PMA3_LANE0_BASE + 4*0xD1) //Attributes : RW +#define PET_PMA3_LANE0_TRANS_REQ_CTRL3 (PET_PMA3_LANE0_BASE + 4*0xD2) //Attributes : RW +#define PET_PMA3_LANE0_TRANS_REQ_CTRL4 (PET_PMA3_LANE0_BASE + 4*0xD3) //Attributes : RW +#define PET_PMA3_LANE0_TRANS_REQ_CTRL5 (PET_PMA3_LANE0_BASE + 4*0xD4) //Attributes : RW +#define PET_PMA3_LANE0_TRANS_REQ_MUX (PET_PMA3_LANE0_BASE + 4*0xD5) //Attributes : RW +#define PET_PMA3_LANE0_TRANS_INTERFACE_CTRL (PET_PMA3_LANE0_BASE + 4*0xD6) //Attributes : RW +#define PET_PMA3_LANE0_TRANS_INTERFACE_MUX (PET_PMA3_LANE0_BASE + 4*0xD7) //Attributes : RW +#define PET_PMA3_LANE0_TRANS_MASTER_PLL_STATE (PET_PMA3_LANE0_BASE + 4*0xD8) //Attributes : RW +#define PET_PMA3_LANE0_TRANS_PLL_STATE (PET_PMA3_LANE0_BASE + 4*0xD9) //Attributes : RO +#define PET_PMA3_LANE0_PLL_STATE_MUX (PET_PMA3_LANE0_BASE + 4*0xDA) //Attributes : RW +#define PET_PMA3_LANE0_RX_VALID_PHY (PET_PMA3_LANE0_BASE + 4*0xDF) //Attributes : RO +#define PET_PMA3_LANE0_RX_VALID_MUX (PET_PMA3_LANE0_BASE + 4*0xE0) //Attributes : RW +#define PET_PMA3_LANE0_RX_SRIO_SIGDET_MUX (PET_PMA3_LANE0_BASE + 4*0xE1) //Attributes : RW +#define PET_PMA3_LANE0_SRIO_DEGRADED (PET_PMA3_LANE0_BASE + 4*0xE2) //Attributes : RW +#define PET_PMA3_LANE0_SRIO_RETRAIN (PET_PMA3_LANE0_BASE + 4*0xE3) //Attributes : RW +#define PET_PMA3_LANE0_SRIO_SHORT_RUN (PET_PMA3_LANE0_BASE + 4*0xE4) //Attributes : RW +#define PET_PMA3_LANE0_EQ_INIT_C0 (PET_PMA3_LANE0_BASE + 4*0xE5) //Attributes : RW +#define PET_PMA3_LANE0_EQ_INIT_CN1 (PET_PMA3_LANE0_BASE + 4*0xE6) //Attributes : RW +#define PET_PMA3_LANE0_EQ_INIT_CP1 (PET_PMA3_LANE0_BASE + 4*0xE7) //Attributes : RW +#define PET_PMA3_LANE0_EQ_RULE_CTRL_1 (PET_PMA3_LANE0_BASE + 4*0xE8) //Attributes : RW +#define PET_PMA3_LANE0_EQ_RULE_CTRL_2 (PET_PMA3_LANE0_BASE + 4*0xE9) //Attributes : RW +#define PET_PMA3_LANE0_EQ_RULE_CTRL_3 (PET_PMA3_LANE0_BASE + 4*0xEA) //Attributes : RW +#define PET_PMA3_LANE0_EQ_RULE_CTRL_4 (PET_PMA3_LANE0_BASE + 4*0xEB) //Attributes : RW +#define PET_PMA3_LANE0_EQ_ALGORITHM_CTRL (PET_PMA3_LANE0_BASE + 4*0xEC) //Attributes : RW +#define PET_PMA3_LANE0_EQ_TX_TRAIN_CTRL (PET_PMA3_LANE0_BASE + 4*0xED) //Attributes : RW +#define PET_PMA3_LANE0_EQ_ADJ_INTERVAL (PET_PMA3_LANE0_BASE + 4*0xEE) //Attributes : RW +#define PET_PMA3_LANE0_EQ_RX_REQ_CTRL (PET_PMA3_LANE0_BASE + 4*0xEF) //Attributes : RW +#define PET_PMA3_LANE0_EQ_RX_TRAIN_CTRL (PET_PMA3_LANE0_BASE + 4*0xF0) //Attributes : RW +#define PET_PMA3_LANE0_EQ_RX_RESET_CYCLE (PET_PMA3_LANE0_BASE + 4*0xF1) //Attributes : RW +#define PET_PMA3_LANE0_RPCS_KTR_STATUS (PET_PMA3_LANE0_BASE + 4*0xF2) //Attributes : RO +#define PET_PMA3_LANE0_EQ_FSM (PET_PMA3_LANE0_BASE + 4*0xF3) //Attributes : RO +#define PET_PMA3_LANE0_ETH_RX_LOS (PET_PMA3_LANE0_BASE + 4*0xF4) //Attributes : RW +#define PET_PMA3_LANE0_EQ_PRESET_C0 (PET_PMA3_LANE0_BASE + 4*0xF5) //Attributes : RW +#define PET_PMA3_LANE0_EQ_PRESET_CN1 (PET_PMA3_LANE0_BASE + 4*0xF6) //Attributes : RW +#define PET_PMA3_LANE0_EQ_PRESET_CP1 (PET_PMA3_LANE0_BASE + 4*0xF7) //Attributes : RW +#define PET_PMA3_LANE0_EQ_SUCC_MASK (PET_PMA3_LANE0_BASE + 4*0xF8) //Attributes : RW +#define PET_PMA3_LANE0_PMA_COM_SCRATCH (PET_PMA3_LANE0_BASE + 4*0xff) //Attributes : RW +#define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY0 (PET_PMA3_LANE0_BASE + 4*0x100) //Attributes : RO_EXT_L +#define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY1 (PET_PMA3_LANE0_BASE + 4*0x101) //Attributes : RO_EXT +#define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY2 (PET_PMA3_LANE0_BASE + 4*0x102) //Attributes : RO_EXT +#define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY3 (PET_PMA3_LANE0_BASE + 4*0x103) //Attributes : RO_EXT +#define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY4 (PET_PMA3_LANE0_BASE + 4*0x104) //Attributes : RO_EXT +#define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY5 (PET_PMA3_LANE0_BASE + 4*0x105) //Attributes : RO_EXT +#define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY6 (PET_PMA3_LANE0_BASE + 4*0x106) //Attributes : RO_EXT +#define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY7 (PET_PMA3_LANE0_BASE + 4*0x107) //Attributes : RO_EXT_H +#define PET_PMA3_LANE0_EQ_TX_FSM_HISTORY_CTRL (PET_PMA3_LANE0_BASE + 4*0x108) //Attributes : RW +#define PET_PMA3_LANE0_EQ_RX_FSM_HISTORY0 (PET_PMA3_LANE0_BASE + 4*0x109) //Attributes : RO_EXT_L +#define PET_PMA3_LANE0_EQ_RX_FSM_HISTORY1 (PET_PMA3_LANE0_BASE + 4*0x10A) //Attributes : RO_EXT +#define PET_PMA3_LANE0_EQ_RX_FSM_HISTORY2 (PET_PMA3_LANE0_BASE + 4*0x10B) //Attributes : RO_EXT +#define PET_PMA3_LANE0_EQ_RX_FSM_HISTORY3 (PET_PMA3_LANE0_BASE + 4*0x10C) //Attributes : RO_EXT_H +#define PET_PMA3_LANE0_EQ_RX_FSM_HISTORY_CTRL (PET_PMA3_LANE0_BASE + 4*0x10D) //Attributes : RW +#define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY0 (PET_PMA3_LANE0_BASE + 4*0x110) //Attributes : RO_EXT_L +#define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY1 (PET_PMA3_LANE0_BASE + 4*0x111) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY2 (PET_PMA3_LANE0_BASE + 4*0x112) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY3 (PET_PMA3_LANE0_BASE + 4*0x113) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY4 (PET_PMA3_LANE0_BASE + 4*0x114) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY5 (PET_PMA3_LANE0_BASE + 4*0x115) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY6 (PET_PMA3_LANE0_BASE + 4*0x116) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY7 (PET_PMA3_LANE0_BASE + 4*0x117) //Attributes : RO_EXT_H +#define PET_PMA3_LANE0_TX_EQ_MAIN_HISTORY_CTRL (PET_PMA3_LANE0_BASE + 4*0x118) //Attributes : RW +#define PET_PMA3_LANE0_RX_TXMAIN_DIR_HISTORY0 (PET_PMA3_LANE0_BASE + 4*0x119) //Attributes : RO_EXT_L +#define PET_PMA3_LANE0_RX_TXMAIN_DIR_HISTORY1 (PET_PMA3_LANE0_BASE + 4*0x11A) //Attributes : RO_EXT +#define PET_PMA3_LANE0_RX_TXMAIN_DIR_HISTORY2 (PET_PMA3_LANE0_BASE + 4*0x11B) //Attributes : RO_EXT +#define PET_PMA3_LANE0_RX_TXMAIN_DIR_HISTORY3 (PET_PMA3_LANE0_BASE + 4*0x11C) //Attributes : RO_EXT_H +#define PET_PMA3_LANE0_RX_TXMAIN_DIR_HISTORY_CTRL (PET_PMA3_LANE0_BASE + 4*0x11D) //Attributes : RW +#define PET_PMA3_LANE0_TX_EQ_POST_HISTORY0 (PET_PMA3_LANE0_BASE + 4*0x120) //Attributes : RO_EXT_L +#define PET_PMA3_LANE0_TX_EQ_POST_HISTORY1 (PET_PMA3_LANE0_BASE + 4*0x121) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_POST_HISTORY2 (PET_PMA3_LANE0_BASE + 4*0x122) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_POST_HISTORY3 (PET_PMA3_LANE0_BASE + 4*0x123) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_POST_HISTORY4 (PET_PMA3_LANE0_BASE + 4*0x124) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_POST_HISTORY5 (PET_PMA3_LANE0_BASE + 4*0x125) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_POST_HISTORY6 (PET_PMA3_LANE0_BASE + 4*0x126) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_POST_HISTORY7 (PET_PMA3_LANE0_BASE + 4*0x127) //Attributes : RO_EXT_H +#define PET_PMA3_LANE0_TX_EQ_POST_HISTORY_CTRL (PET_PMA3_LANE0_BASE + 4*0x128) //Attributes : RW +#define PET_PMA3_LANE0_RX_TXPOST_DIR_HISTORY0 (PET_PMA3_LANE0_BASE + 4*0x129) //Attributes : RO_EXT_L +#define PET_PMA3_LANE0_RX_TXPOST_DIR_HISTORY1 (PET_PMA3_LANE0_BASE + 4*0x12A) //Attributes : RO_EXT +#define PET_PMA3_LANE0_RX_TXPOST_DIR_HISTORY2 (PET_PMA3_LANE0_BASE + 4*0x12B) //Attributes : RO_EXT +#define PET_PMA3_LANE0_RX_TXPOST_DIR_HISTORY3 (PET_PMA3_LANE0_BASE + 4*0x12C) //Attributes : RO_EXT_H +#define PET_PMA3_LANE0_RX_TXPOST_DIR_HISTORY_CTRL (PET_PMA3_LANE0_BASE + 4*0x12D) //Attributes : RW +#define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY0 (PET_PMA3_LANE0_BASE + 4*0x130) //Attributes : RO_EXT_L +#define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY1 (PET_PMA3_LANE0_BASE + 4*0x131) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY2 (PET_PMA3_LANE0_BASE + 4*0x132) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY3 (PET_PMA3_LANE0_BASE + 4*0x133) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY4 (PET_PMA3_LANE0_BASE + 4*0x134) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY5 (PET_PMA3_LANE0_BASE + 4*0x135) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY6 (PET_PMA3_LANE0_BASE + 4*0x136) //Attributes : RO_EXT +#define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY7 (PET_PMA3_LANE0_BASE + 4*0x137) //Attributes : RO_EXT_H +#define PET_PMA3_LANE0_TX_EQ_PRE_HISTORY_CTRL (PET_PMA3_LANE0_BASE + 4*0x138) //Attributes : RW +#define PET_PMA3_LANE0_RX_TXPRE_DIR_HISTORY0 (PET_PMA3_LANE0_BASE + 4*0x139) //Attributes : RO_EXT_L +#define PET_PMA3_LANE0_RX_TXPRE_DIR_HISTORY1 (PET_PMA3_LANE0_BASE + 4*0x13A) //Attributes : RO_EXT +#define PET_PMA3_LANE0_RX_TXPRE_DIR_HISTORY2 (PET_PMA3_LANE0_BASE + 4*0x13B) //Attributes : RO_EXT +#define PET_PMA3_LANE0_RX_TXPRE_DIR_HISTORY3 (PET_PMA3_LANE0_BASE + 4*0x13C) //Attributes : RO_EXT_H +#define PET_PMA3_LANE0_RX_TXPRE_DIR_HISTORY_CTRL (PET_PMA3_LANE0_BASE + 4*0x13D) //Attributes : RW + +#define PET_PMA3_LANE1_PMA_LOOPBACK_CTRL (PET_PMA3_LANE1_BASE + 4*0x00) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_REQ (PET_PMA3_LANE1_BASE + 4*0x01) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_REQ_ACK (PET_PMA3_LANE1_BASE + 4*0x02) //Attributes : RO +#define PET_PMA3_LANE1_RECEIVER_REQ_PARAM2 (PET_PMA3_LANE1_BASE + 4*0x03) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_REQ_PARAM3 (PET_PMA3_LANE1_BASE + 4*0x04) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_REQ_PARAM4 (PET_PMA3_LANE1_BASE + 4*0x05) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_REQ_PARAM5 (PET_PMA3_LANE1_BASE + 4*0x06) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_REQ_PARAM6 (PET_PMA3_LANE1_BASE + 4*0x07) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_REQ_PARAM7 (PET_PMA3_LANE1_BASE + 4*0x08) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_REQ_PARAM8 (PET_PMA3_LANE1_BASE + 4*0x09) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_REQ_PARAM9 (PET_PMA3_LANE1_BASE + 4*0x0A) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_REQ_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x0B) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_ADAPT_REQ (PET_PMA3_LANE1_BASE + 4*0x10) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_ADAPT_REQ_ACK (PET_PMA3_LANE1_BASE + 4*0x11) //Attributes : RO +#define PET_PMA3_LANE1_RECEIVER_ADAPT_DIR (PET_PMA3_LANE1_BASE + 4*0x12) //Attributes : RO +#define PET_PMA3_LANE1_RECEIVER_ADAPT_SETTING (PET_PMA3_LANE1_BASE + 4*0x13) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_ADAPT_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x14) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_DATAPATH_EN (PET_PMA3_LANE1_BASE + 4*0x20) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_DATAPATH_SETTING1 (PET_PMA3_LANE1_BASE + 4*0x21) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_DATAPATH_SETTING2 (PET_PMA3_LANE1_BASE + 4*0x22) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_DATAPATH_SETTING3 (PET_PMA3_LANE1_BASE + 4*0x23) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_DATAPATH_STATUS1 (PET_PMA3_LANE1_BASE + 4*0x24) //Attributes : RO +#define PET_PMA3_LANE1_RECEIVER_DATAPATH_STATUS2 (PET_PMA3_LANE1_BASE + 4*0x25) //Attributes : RO +#define PET_PMA3_LANE1_RECEIVER_DATAPATH_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x26) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_RESET (PET_PMA3_LANE1_BASE + 4*0x30) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_CONTROL (PET_PMA3_LANE1_BASE + 4*0x31) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_CONTROL_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x32) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_RECAL_CTRL (PET_PMA3_LANE1_BASE + 4*0x40) //Attributes : RW +#define PET_PMA3_LANE1_RECEIVER_RECAL_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x41) //Attributes : RW +#define PET_PMA3_LANE1_TRANSMITTER_REQ (PET_PMA3_LANE1_BASE + 4*0x50) //Attributes : RW +#define PET_PMA3_LANE1_TRANSMITTER_REQ_ACK (PET_PMA3_LANE1_BASE + 4*0x51) //Attributes : RO +#define PET_PMA3_LANE1_TRANSMITTER_REQ_PARAM1 (PET_PMA3_LANE1_BASE + 4*0x52) //Attributes : RW +#define PET_PMA3_LANE1_TRANSMITTER_REQ_PARAM2 (PET_PMA3_LANE1_BASE + 4*0x53) //Attributes : RW +#define PET_PMA3_LANE1_TRANSMITTER_REQ_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x55) //Attributes : RW +#define PET_PMA3_LANE1_TRANSMITTER_DATAPATH_EN (PET_PMA3_LANE1_BASE + 4*0x60) //Attributes : RW +#define PET_PMA3_LANE1_TRANSMITTER_DATAPATH_CLKRDY (PET_PMA3_LANE1_BASE + 4*0x61) //Attributes : RW +#define PET_PMA3_LANE1_TRANSMITTER_DATAPATH_SETTING (PET_PMA3_LANE1_BASE + 4*0x62) //Attributes : RW +#define PET_PMA3_LANE1_TRANSMITTER_DATAPATH_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x63) //Attributes : RW +#define PET_PMA3_LANE1_TRANSMITTER_CONTROL1 (PET_PMA3_LANE1_BASE + 4*0x70) //Attributes : RW +#define PET_PMA3_LANE1_TRANSMITTER_CONTROL2 (PET_PMA3_LANE1_BASE + 4*0x71) //Attributes : RW +#define PET_PMA3_LANE1_TRANSMITTER_CONTROL_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x72) //Attributes : RW +#define PET_PMA3_LANE1_TRANSMITTER_EQ1 (PET_PMA3_LANE1_BASE + 4*0x80) //Attributes : RW +#define PET_PMA3_LANE1_TRANSMITTER_EQ2 (PET_PMA3_LANE1_BASE + 4*0x81) //Attributes : RW +#define PET_PMA3_LANE1_TRANSMITTER_EQ3 (PET_PMA3_LANE1_BASE + 4*0x82) //Attributes : RW +#define PET_PMA3_LANE1_TRANSMITTER_EQ_MUX_CTRL (PET_PMA3_LANE1_BASE + 4*0x83) //Attributes : RW +#define PET_PMA3_LANE1_CONTEXT_RESTORE_CTRL1 (PET_PMA3_LANE1_BASE + 4*0x90) //Attributes : RW +#define PET_PMA3_LANE1_CONTEXT_RESTORE_CTRL2 (PET_PMA3_LANE1_BASE + 4*0x91) //Attributes : RW +#define PET_PMA3_LANE1_CONTEXT_RESTORE_CTRL3 (PET_PMA3_LANE1_BASE + 4*0x92) //Attributes : RW +#define PET_PMA3_LANE1_CONTEXT_RESTORE_CTRL4 (PET_PMA3_LANE1_BASE + 4*0x93) //Attributes : RW +#define PET_PMA3_LANE1_CONTEXT_RESTORE_MUX (PET_PMA3_LANE1_BASE + 4*0x94) //Attributes : RW +#define PET_PMA3_LANE1_LANE_REFCLK_SEL (PET_PMA3_LANE1_BASE + 4*0xA0) //Attributes : RW +#define PET_PMA3_LANE1_ETH_CLK_CTRL (PET_PMA3_LANE1_BASE + 4*0xB0) //Attributes : RW +#define PET_PMA3_LANE1_ETH_CLK_CTRL_MUX (PET_PMA3_LANE1_BASE + 4*0xB1) //Attributes : RW +#define PET_PMA3_LANE1_RX_ADAPT_CTRL (PET_PMA3_LANE1_BASE + 4*0xC0) //Attributes : RW +#define PET_PMA3_LANE1_RX_DCC_CTRL (PET_PMA3_LANE1_BASE + 4*0xC1) //Attributes : RW +#define PET_PMA3_LANE1_RX_EQ_CTRL1 (PET_PMA3_LANE1_BASE + 4*0xC2) //Attributes : RW +#define PET_PMA3_LANE1_RX_EQ_CTRL2 (PET_PMA3_LANE1_BASE + 4*0xC3) //Attributes : RW +#define PET_PMA3_LANE1_RX_MARGIN_CTRL (PET_PMA3_LANE1_BASE + 4*0xC4) //Attributes : RW +#define PET_PMA3_LANE1_RX_MARGIN_ERROR (PET_PMA3_LANE1_BASE + 4*0xC5) //Attributes : RO +#define PET_PMA3_LANE1_RECV_REQUEST_CTRL_MUX (PET_PMA3_LANE1_BASE + 4*0xC6) //Attributes : RW +#define PET_PMA3_LANE1_RX_COARSE_ADAPT_CTRL (PET_PMA3_LANE1_BASE + 4*0xC8) //Attributes : RW +#define PET_PMA3_LANE1_RX_COARSE_ADAPT_CTRL_MUX (PET_PMA3_LANE1_BASE + 4*0xC9) //Attributes : RW +#define PET_PMA3_LANE1_RX_DIV_CLK_CTRL (PET_PMA3_LANE1_BASE + 4*0xCA) //Attributes : RW +#define PET_PMA3_LANE1_TX_DIV_CLK_CTRL (PET_PMA3_LANE1_BASE + 4*0xCB) //Attributes : RW +#define PET_PMA3_LANE1_MULTI_CLK_CTRL_MUX (PET_PMA3_LANE1_BASE + 4*0xCC) //Attributes : RW +#define PET_PMA3_LANE1_TRANS_REQ_CTRL1 (PET_PMA3_LANE1_BASE + 4*0xD0) //Attributes : RW +#define PET_PMA3_LANE1_TRANS_REQ_CTRL2 (PET_PMA3_LANE1_BASE + 4*0xD1) //Attributes : RW +#define PET_PMA3_LANE1_TRANS_REQ_CTRL3 (PET_PMA3_LANE1_BASE + 4*0xD2) //Attributes : RW +#define PET_PMA3_LANE1_TRANS_REQ_CTRL4 (PET_PMA3_LANE1_BASE + 4*0xD3) //Attributes : RW +#define PET_PMA3_LANE1_TRANS_REQ_CTRL5 (PET_PMA3_LANE1_BASE + 4*0xD4) //Attributes : RW +#define PET_PMA3_LANE1_TRANS_REQ_MUX (PET_PMA3_LANE1_BASE + 4*0xD5) //Attributes : RW +#define PET_PMA3_LANE1_TRANS_INTERFACE_CTRL (PET_PMA3_LANE1_BASE + 4*0xD6) //Attributes : RW +#define PET_PMA3_LANE1_TRANS_INTERFACE_MUX (PET_PMA3_LANE1_BASE + 4*0xD7) //Attributes : RW +#define PET_PMA3_LANE1_TRANS_MASTER_PLL_STATE (PET_PMA3_LANE1_BASE + 4*0xD8) //Attributes : RW +#define PET_PMA3_LANE1_TRANS_PLL_STATE (PET_PMA3_LANE1_BASE + 4*0xD9) //Attributes : RO +#define PET_PMA3_LANE1_PLL_STATE_MUX (PET_PMA3_LANE1_BASE + 4*0xDA) //Attributes : RW +#define PET_PMA3_LANE1_RX_VALID_PHY (PET_PMA3_LANE1_BASE + 4*0xDF) //Attributes : RO +#define PET_PMA3_LANE1_RX_VALID_MUX (PET_PMA3_LANE1_BASE + 4*0xE0) //Attributes : RW +#define PET_PMA3_LANE1_RX_SRIO_SIGDET_MUX (PET_PMA3_LANE1_BASE + 4*0xE1) //Attributes : RW +#define PET_PMA3_LANE1_SRIO_DEGRADED (PET_PMA3_LANE1_BASE + 4*0xE2) //Attributes : RW +#define PET_PMA3_LANE1_SRIO_RETRAIN (PET_PMA3_LANE1_BASE + 4*0xE3) //Attributes : RW +#define PET_PMA3_LANE1_SRIO_SHORT_RUN (PET_PMA3_LANE1_BASE + 4*0xE4) //Attributes : RW +#define PET_PMA3_LANE1_EQ_INIT_C0 (PET_PMA3_LANE1_BASE + 4*0xE5) //Attributes : RW +#define PET_PMA3_LANE1_EQ_INIT_CN1 (PET_PMA3_LANE1_BASE + 4*0xE6) //Attributes : RW +#define PET_PMA3_LANE1_EQ_INIT_CP1 (PET_PMA3_LANE1_BASE + 4*0xE7) //Attributes : RW +#define PET_PMA3_LANE1_EQ_RULE_CTRL_1 (PET_PMA3_LANE1_BASE + 4*0xE8) //Attributes : RW +#define PET_PMA3_LANE1_EQ_RULE_CTRL_2 (PET_PMA3_LANE1_BASE + 4*0xE9) //Attributes : RW +#define PET_PMA3_LANE1_EQ_RULE_CTRL_3 (PET_PMA3_LANE1_BASE + 4*0xEA) //Attributes : RW +#define PET_PMA3_LANE1_EQ_RULE_CTRL_4 (PET_PMA3_LANE1_BASE + 4*0xEB) //Attributes : RW +#define PET_PMA3_LANE1_EQ_ALGORITHM_CTRL (PET_PMA3_LANE1_BASE + 4*0xEC) //Attributes : RW +#define PET_PMA3_LANE1_EQ_TX_TRAIN_CTRL (PET_PMA3_LANE1_BASE + 4*0xED) //Attributes : RW +#define PET_PMA3_LANE1_EQ_ADJ_INTERVAL (PET_PMA3_LANE1_BASE + 4*0xEE) //Attributes : RW +#define PET_PMA3_LANE1_EQ_RX_REQ_CTRL (PET_PMA3_LANE1_BASE + 4*0xEF) //Attributes : RW +#define PET_PMA3_LANE1_EQ_RX_TRAIN_CTRL (PET_PMA3_LANE1_BASE + 4*0xF0) //Attributes : RW +#define PET_PMA3_LANE1_EQ_RX_RESET_CYCLE (PET_PMA3_LANE1_BASE + 4*0xF1) //Attributes : RW +#define PET_PMA3_LANE1_RPCS_KTR_STATUS (PET_PMA3_LANE1_BASE + 4*0xF2) //Attributes : RO +#define PET_PMA3_LANE1_EQ_FSM (PET_PMA3_LANE1_BASE + 4*0xF3) //Attributes : RO +#define PET_PMA3_LANE1_ETH_RX_LOS (PET_PMA3_LANE1_BASE + 4*0xF4) //Attributes : RW +#define PET_PMA3_LANE1_EQ_PRESET_C0 (PET_PMA3_LANE1_BASE + 4*0xF5) //Attributes : RW +#define PET_PMA3_LANE1_EQ_PRESET_CN1 (PET_PMA3_LANE1_BASE + 4*0xF6) //Attributes : RW +#define PET_PMA3_LANE1_EQ_PRESET_CP1 (PET_PMA3_LANE1_BASE + 4*0xF7) //Attributes : RW +#define PET_PMA3_LANE1_EQ_SUCC_MASK (PET_PMA3_LANE1_BASE + 4*0xF8) //Attributes : RW +#define PET_PMA3_LANE1_PMA_COM_SCRATCH (PET_PMA3_LANE1_BASE + 4*0xff) //Attributes : RW +#define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY0 (PET_PMA3_LANE1_BASE + 4*0x100) //Attributes : RO_EXT_L +#define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY1 (PET_PMA3_LANE1_BASE + 4*0x101) //Attributes : RO_EXT +#define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY2 (PET_PMA3_LANE1_BASE + 4*0x102) //Attributes : RO_EXT +#define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY3 (PET_PMA3_LANE1_BASE + 4*0x103) //Attributes : RO_EXT +#define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY4 (PET_PMA3_LANE1_BASE + 4*0x104) //Attributes : RO_EXT +#define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY5 (PET_PMA3_LANE1_BASE + 4*0x105) //Attributes : RO_EXT +#define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY6 (PET_PMA3_LANE1_BASE + 4*0x106) //Attributes : RO_EXT +#define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY7 (PET_PMA3_LANE1_BASE + 4*0x107) //Attributes : RO_EXT_H +#define PET_PMA3_LANE1_EQ_TX_FSM_HISTORY_CTRL (PET_PMA3_LANE1_BASE + 4*0x108) //Attributes : RW +#define PET_PMA3_LANE1_EQ_RX_FSM_HISTORY0 (PET_PMA3_LANE1_BASE + 4*0x109) //Attributes : RO_EXT_L +#define PET_PMA3_LANE1_EQ_RX_FSM_HISTORY1 (PET_PMA3_LANE1_BASE + 4*0x10A) //Attributes : RO_EXT +#define PET_PMA3_LANE1_EQ_RX_FSM_HISTORY2 (PET_PMA3_LANE1_BASE + 4*0x10B) //Attributes : RO_EXT +#define PET_PMA3_LANE1_EQ_RX_FSM_HISTORY3 (PET_PMA3_LANE1_BASE + 4*0x10C) //Attributes : RO_EXT_H +#define PET_PMA3_LANE1_EQ_RX_FSM_HISTORY_CTRL (PET_PMA3_LANE1_BASE + 4*0x10D) //Attributes : RW +#define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY0 (PET_PMA3_LANE1_BASE + 4*0x110) //Attributes : RO_EXT_L +#define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY1 (PET_PMA3_LANE1_BASE + 4*0x111) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY2 (PET_PMA3_LANE1_BASE + 4*0x112) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY3 (PET_PMA3_LANE1_BASE + 4*0x113) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY4 (PET_PMA3_LANE1_BASE + 4*0x114) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY5 (PET_PMA3_LANE1_BASE + 4*0x115) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY6 (PET_PMA3_LANE1_BASE + 4*0x116) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY7 (PET_PMA3_LANE1_BASE + 4*0x117) //Attributes : RO_EXT_H +#define PET_PMA3_LANE1_TX_EQ_MAIN_HISTORY_CTRL (PET_PMA3_LANE1_BASE + 4*0x118) //Attributes : RW +#define PET_PMA3_LANE1_RX_TXMAIN_DIR_HISTORY0 (PET_PMA3_LANE1_BASE + 4*0x119) //Attributes : RO_EXT_L +#define PET_PMA3_LANE1_RX_TXMAIN_DIR_HISTORY1 (PET_PMA3_LANE1_BASE + 4*0x11A) //Attributes : RO_EXT +#define PET_PMA3_LANE1_RX_TXMAIN_DIR_HISTORY2 (PET_PMA3_LANE1_BASE + 4*0x11B) //Attributes : RO_EXT +#define PET_PMA3_LANE1_RX_TXMAIN_DIR_HISTORY3 (PET_PMA3_LANE1_BASE + 4*0x11C) //Attributes : RO_EXT_H +#define PET_PMA3_LANE1_RX_TXMAIN_DIR_HISTORY_CTRL (PET_PMA3_LANE1_BASE + 4*0x11D) //Attributes : RW +#define PET_PMA3_LANE1_TX_EQ_POST_HISTORY0 (PET_PMA3_LANE1_BASE + 4*0x120) //Attributes : RO_EXT_L +#define PET_PMA3_LANE1_TX_EQ_POST_HISTORY1 (PET_PMA3_LANE1_BASE + 4*0x121) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_POST_HISTORY2 (PET_PMA3_LANE1_BASE + 4*0x122) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_POST_HISTORY3 (PET_PMA3_LANE1_BASE + 4*0x123) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_POST_HISTORY4 (PET_PMA3_LANE1_BASE + 4*0x124) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_POST_HISTORY5 (PET_PMA3_LANE1_BASE + 4*0x125) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_POST_HISTORY6 (PET_PMA3_LANE1_BASE + 4*0x126) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_POST_HISTORY7 (PET_PMA3_LANE1_BASE + 4*0x127) //Attributes : RO_EXT_H +#define PET_PMA3_LANE1_TX_EQ_POST_HISTORY_CTRL (PET_PMA3_LANE1_BASE + 4*0x128) //Attributes : RW +#define PET_PMA3_LANE1_RX_TXPOST_DIR_HISTORY0 (PET_PMA3_LANE1_BASE + 4*0x129) //Attributes : RO_EXT_L +#define PET_PMA3_LANE1_RX_TXPOST_DIR_HISTORY1 (PET_PMA3_LANE1_BASE + 4*0x12A) //Attributes : RO_EXT +#define PET_PMA3_LANE1_RX_TXPOST_DIR_HISTORY2 (PET_PMA3_LANE1_BASE + 4*0x12B) //Attributes : RO_EXT +#define PET_PMA3_LANE1_RX_TXPOST_DIR_HISTORY3 (PET_PMA3_LANE1_BASE + 4*0x12C) //Attributes : RO_EXT_H +#define PET_PMA3_LANE1_RX_TXPOST_DIR_HISTORY_CTRL (PET_PMA3_LANE1_BASE + 4*0x12D) //Attributes : RW +#define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY0 (PET_PMA3_LANE1_BASE + 4*0x130) //Attributes : RO_EXT_L +#define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY1 (PET_PMA3_LANE1_BASE + 4*0x131) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY2 (PET_PMA3_LANE1_BASE + 4*0x132) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY3 (PET_PMA3_LANE1_BASE + 4*0x133) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY4 (PET_PMA3_LANE1_BASE + 4*0x134) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY5 (PET_PMA3_LANE1_BASE + 4*0x135) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY6 (PET_PMA3_LANE1_BASE + 4*0x136) //Attributes : RO_EXT +#define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY7 (PET_PMA3_LANE1_BASE + 4*0x137) //Attributes : RO_EXT_H +#define PET_PMA3_LANE1_TX_EQ_PRE_HISTORY_CTRL (PET_PMA3_LANE1_BASE + 4*0x138) //Attributes : RW +#define PET_PMA3_LANE1_RX_TXPRE_DIR_HISTORY0 (PET_PMA3_LANE1_BASE + 4*0x139) //Attributes : RO_EXT_L +#define PET_PMA3_LANE1_RX_TXPRE_DIR_HISTORY1 (PET_PMA3_LANE1_BASE + 4*0x13A) //Attributes : RO_EXT +#define PET_PMA3_LANE1_RX_TXPRE_DIR_HISTORY2 (PET_PMA3_LANE1_BASE + 4*0x13B) //Attributes : RO_EXT +#define PET_PMA3_LANE1_RX_TXPRE_DIR_HISTORY3 (PET_PMA3_LANE1_BASE + 4*0x13C) //Attributes : RO_EXT_H +#define PET_PMA3_LANE1_RX_TXPRE_DIR_HISTORY_CTRL (PET_PMA3_LANE1_BASE + 4*0x13D) //Attributes : RW + +#define PET_PMA3_LANE2_PMA_LOOPBACK_CTRL (PET_PMA3_LANE2_BASE + 4*0x00) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_REQ (PET_PMA3_LANE2_BASE + 4*0x01) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_REQ_ACK (PET_PMA3_LANE2_BASE + 4*0x02) //Attributes : RO +#define PET_PMA3_LANE2_RECEIVER_REQ_PARAM2 (PET_PMA3_LANE2_BASE + 4*0x03) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_REQ_PARAM3 (PET_PMA3_LANE2_BASE + 4*0x04) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_REQ_PARAM4 (PET_PMA3_LANE2_BASE + 4*0x05) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_REQ_PARAM5 (PET_PMA3_LANE2_BASE + 4*0x06) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_REQ_PARAM6 (PET_PMA3_LANE2_BASE + 4*0x07) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_REQ_PARAM7 (PET_PMA3_LANE2_BASE + 4*0x08) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_REQ_PARAM8 (PET_PMA3_LANE2_BASE + 4*0x09) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_REQ_PARAM9 (PET_PMA3_LANE2_BASE + 4*0x0A) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_REQ_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x0B) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_ADAPT_REQ (PET_PMA3_LANE2_BASE + 4*0x10) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_ADAPT_REQ_ACK (PET_PMA3_LANE2_BASE + 4*0x11) //Attributes : RO +#define PET_PMA3_LANE2_RECEIVER_ADAPT_DIR (PET_PMA3_LANE2_BASE + 4*0x12) //Attributes : RO +#define PET_PMA3_LANE2_RECEIVER_ADAPT_SETTING (PET_PMA3_LANE2_BASE + 4*0x13) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_ADAPT_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x14) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_DATAPATH_EN (PET_PMA3_LANE2_BASE + 4*0x20) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_DATAPATH_SETTING1 (PET_PMA3_LANE2_BASE + 4*0x21) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_DATAPATH_SETTING2 (PET_PMA3_LANE2_BASE + 4*0x22) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_DATAPATH_SETTING3 (PET_PMA3_LANE2_BASE + 4*0x23) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_DATAPATH_STATUS1 (PET_PMA3_LANE2_BASE + 4*0x24) //Attributes : RO +#define PET_PMA3_LANE2_RECEIVER_DATAPATH_STATUS2 (PET_PMA3_LANE2_BASE + 4*0x25) //Attributes : RO +#define PET_PMA3_LANE2_RECEIVER_DATAPATH_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x26) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_RESET (PET_PMA3_LANE2_BASE + 4*0x30) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_CONTROL (PET_PMA3_LANE2_BASE + 4*0x31) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_CONTROL_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x32) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_RECAL_CTRL (PET_PMA3_LANE2_BASE + 4*0x40) //Attributes : RW +#define PET_PMA3_LANE2_RECEIVER_RECAL_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x41) //Attributes : RW +#define PET_PMA3_LANE2_TRANSMITTER_REQ (PET_PMA3_LANE2_BASE + 4*0x50) //Attributes : RW +#define PET_PMA3_LANE2_TRANSMITTER_REQ_ACK (PET_PMA3_LANE2_BASE + 4*0x51) //Attributes : RO +#define PET_PMA3_LANE2_TRANSMITTER_REQ_PARAM1 (PET_PMA3_LANE2_BASE + 4*0x52) //Attributes : RW +#define PET_PMA3_LANE2_TRANSMITTER_REQ_PARAM2 (PET_PMA3_LANE2_BASE + 4*0x53) //Attributes : RW +#define PET_PMA3_LANE2_TRANSMITTER_REQ_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x55) //Attributes : RW +#define PET_PMA3_LANE2_TRANSMITTER_DATAPATH_EN (PET_PMA3_LANE2_BASE + 4*0x60) //Attributes : RW +#define PET_PMA3_LANE2_TRANSMITTER_DATAPATH_CLKRDY (PET_PMA3_LANE2_BASE + 4*0x61) //Attributes : RW +#define PET_PMA3_LANE2_TRANSMITTER_DATAPATH_SETTING (PET_PMA3_LANE2_BASE + 4*0x62) //Attributes : RW +#define PET_PMA3_LANE2_TRANSMITTER_DATAPATH_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x63) //Attributes : RW +#define PET_PMA3_LANE2_TRANSMITTER_CONTROL1 (PET_PMA3_LANE2_BASE + 4*0x70) //Attributes : RW +#define PET_PMA3_LANE2_TRANSMITTER_CONTROL2 (PET_PMA3_LANE2_BASE + 4*0x71) //Attributes : RW +#define PET_PMA3_LANE2_TRANSMITTER_CONTROL_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x72) //Attributes : RW +#define PET_PMA3_LANE2_TRANSMITTER_EQ1 (PET_PMA3_LANE2_BASE + 4*0x80) //Attributes : RW +#define PET_PMA3_LANE2_TRANSMITTER_EQ2 (PET_PMA3_LANE2_BASE + 4*0x81) //Attributes : RW +#define PET_PMA3_LANE2_TRANSMITTER_EQ3 (PET_PMA3_LANE2_BASE + 4*0x82) //Attributes : RW +#define PET_PMA3_LANE2_TRANSMITTER_EQ_MUX_CTRL (PET_PMA3_LANE2_BASE + 4*0x83) //Attributes : RW +#define PET_PMA3_LANE2_CONTEXT_RESTORE_CTRL1 (PET_PMA3_LANE2_BASE + 4*0x90) //Attributes : RW +#define PET_PMA3_LANE2_CONTEXT_RESTORE_CTRL2 (PET_PMA3_LANE2_BASE + 4*0x91) //Attributes : RW +#define PET_PMA3_LANE2_CONTEXT_RESTORE_CTRL3 (PET_PMA3_LANE2_BASE + 4*0x92) //Attributes : RW +#define PET_PMA3_LANE2_CONTEXT_RESTORE_CTRL4 (PET_PMA3_LANE2_BASE + 4*0x93) //Attributes : RW +#define PET_PMA3_LANE2_CONTEXT_RESTORE_MUX (PET_PMA3_LANE2_BASE + 4*0x94) //Attributes : RW +#define PET_PMA3_LANE2_LANE_REFCLK_SEL (PET_PMA3_LANE2_BASE + 4*0xA0) //Attributes : RW +#define PET_PMA3_LANE2_ETH_CLK_CTRL (PET_PMA3_LANE2_BASE + 4*0xB0) //Attributes : RW +#define PET_PMA3_LANE2_ETH_CLK_CTRL_MUX (PET_PMA3_LANE2_BASE + 4*0xB1) //Attributes : RW +#define PET_PMA3_LANE2_RX_ADAPT_CTRL (PET_PMA3_LANE2_BASE + 4*0xC0) //Attributes : RW +#define PET_PMA3_LANE2_RX_DCC_CTRL (PET_PMA3_LANE2_BASE + 4*0xC1) //Attributes : RW +#define PET_PMA3_LANE2_RX_EQ_CTRL1 (PET_PMA3_LANE2_BASE + 4*0xC2) //Attributes : RW +#define PET_PMA3_LANE2_RX_EQ_CTRL2 (PET_PMA3_LANE2_BASE + 4*0xC3) //Attributes : RW +#define PET_PMA3_LANE2_RX_MARGIN_CTRL (PET_PMA3_LANE2_BASE + 4*0xC4) //Attributes : RW +#define PET_PMA3_LANE2_RX_MARGIN_ERROR (PET_PMA3_LANE2_BASE + 4*0xC5) //Attributes : RO +#define PET_PMA3_LANE2_RECV_REQUEST_CTRL_MUX (PET_PMA3_LANE2_BASE + 4*0xC6) //Attributes : RW +#define PET_PMA3_LANE2_RX_COARSE_ADAPT_CTRL (PET_PMA3_LANE2_BASE + 4*0xC8) //Attributes : RW +#define PET_PMA3_LANE2_RX_COARSE_ADAPT_CTRL_MUX (PET_PMA3_LANE2_BASE + 4*0xC9) //Attributes : RW +#define PET_PMA3_LANE2_RX_DIV_CLK_CTRL (PET_PMA3_LANE2_BASE + 4*0xCA) //Attributes : RW +#define PET_PMA3_LANE2_TX_DIV_CLK_CTRL (PET_PMA3_LANE2_BASE + 4*0xCB) //Attributes : RW +#define PET_PMA3_LANE2_MULTI_CLK_CTRL_MUX (PET_PMA3_LANE2_BASE + 4*0xCC) //Attributes : RW +#define PET_PMA3_LANE2_TRANS_REQ_CTRL1 (PET_PMA3_LANE2_BASE + 4*0xD0) //Attributes : RW +#define PET_PMA3_LANE2_TRANS_REQ_CTRL2 (PET_PMA3_LANE2_BASE + 4*0xD1) //Attributes : RW +#define PET_PMA3_LANE2_TRANS_REQ_CTRL3 (PET_PMA3_LANE2_BASE + 4*0xD2) //Attributes : RW +#define PET_PMA3_LANE2_TRANS_REQ_CTRL4 (PET_PMA3_LANE2_BASE + 4*0xD3) //Attributes : RW +#define PET_PMA3_LANE2_TRANS_REQ_CTRL5 (PET_PMA3_LANE2_BASE + 4*0xD4) //Attributes : RW +#define PET_PMA3_LANE2_TRANS_REQ_MUX (PET_PMA3_LANE2_BASE + 4*0xD5) //Attributes : RW +#define PET_PMA3_LANE2_TRANS_INTERFACE_CTRL (PET_PMA3_LANE2_BASE + 4*0xD6) //Attributes : RW +#define PET_PMA3_LANE2_TRANS_INTERFACE_MUX (PET_PMA3_LANE2_BASE + 4*0xD7) //Attributes : RW +#define PET_PMA3_LANE2_TRANS_MASTER_PLL_STATE (PET_PMA3_LANE2_BASE + 4*0xD8) //Attributes : RW +#define PET_PMA3_LANE2_TRANS_PLL_STATE (PET_PMA3_LANE2_BASE + 4*0xD9) //Attributes : RO +#define PET_PMA3_LANE2_PLL_STATE_MUX (PET_PMA3_LANE2_BASE + 4*0xDA) //Attributes : RW +#define PET_PMA3_LANE2_RX_VALID_PHY (PET_PMA3_LANE2_BASE + 4*0xDF) //Attributes : RO +#define PET_PMA3_LANE2_RX_VALID_MUX (PET_PMA3_LANE2_BASE + 4*0xE0) //Attributes : RW +#define PET_PMA3_LANE2_RX_SRIO_SIGDET_MUX (PET_PMA3_LANE2_BASE + 4*0xE1) //Attributes : RW +#define PET_PMA3_LANE2_SRIO_DEGRADED (PET_PMA3_LANE2_BASE + 4*0xE2) //Attributes : RW +#define PET_PMA3_LANE2_SRIO_RETRAIN (PET_PMA3_LANE2_BASE + 4*0xE3) //Attributes : RW +#define PET_PMA3_LANE2_SRIO_SHORT_RUN (PET_PMA3_LANE2_BASE + 4*0xE4) //Attributes : RW +#define PET_PMA3_LANE2_EQ_INIT_C0 (PET_PMA3_LANE2_BASE + 4*0xE5) //Attributes : RW +#define PET_PMA3_LANE2_EQ_INIT_CN1 (PET_PMA3_LANE2_BASE + 4*0xE6) //Attributes : RW +#define PET_PMA3_LANE2_EQ_INIT_CP1 (PET_PMA3_LANE2_BASE + 4*0xE7) //Attributes : RW +#define PET_PMA3_LANE2_EQ_RULE_CTRL_1 (PET_PMA3_LANE2_BASE + 4*0xE8) //Attributes : RW +#define PET_PMA3_LANE2_EQ_RULE_CTRL_2 (PET_PMA3_LANE2_BASE + 4*0xE9) //Attributes : RW +#define PET_PMA3_LANE2_EQ_RULE_CTRL_3 (PET_PMA3_LANE2_BASE + 4*0xEA) //Attributes : RW +#define PET_PMA3_LANE2_EQ_RULE_CTRL_4 (PET_PMA3_LANE2_BASE + 4*0xEB) //Attributes : RW +#define PET_PMA3_LANE2_EQ_ALGORITHM_CTRL (PET_PMA3_LANE2_BASE + 4*0xEC) //Attributes : RW +#define PET_PMA3_LANE2_EQ_TX_TRAIN_CTRL (PET_PMA3_LANE2_BASE + 4*0xED) //Attributes : RW +#define PET_PMA3_LANE2_EQ_ADJ_INTERVAL (PET_PMA3_LANE2_BASE + 4*0xEE) //Attributes : RW +#define PET_PMA3_LANE2_EQ_RX_REQ_CTRL (PET_PMA3_LANE2_BASE + 4*0xEF) //Attributes : RW +#define PET_PMA3_LANE2_EQ_RX_TRAIN_CTRL (PET_PMA3_LANE2_BASE + 4*0xF0) //Attributes : RW +#define PET_PMA3_LANE2_EQ_RX_RESET_CYCLE (PET_PMA3_LANE2_BASE + 4*0xF1) //Attributes : RW +#define PET_PMA3_LANE2_RPCS_KTR_STATUS (PET_PMA3_LANE2_BASE + 4*0xF2) //Attributes : RO +#define PET_PMA3_LANE2_EQ_FSM (PET_PMA3_LANE2_BASE + 4*0xF3) //Attributes : RO +#define PET_PMA3_LANE2_ETH_RX_LOS (PET_PMA3_LANE2_BASE + 4*0xF4) //Attributes : RW +#define PET_PMA3_LANE2_EQ_PRESET_C0 (PET_PMA3_LANE2_BASE + 4*0xF5) //Attributes : RW +#define PET_PMA3_LANE2_EQ_PRESET_CN1 (PET_PMA3_LANE2_BASE + 4*0xF6) //Attributes : RW +#define PET_PMA3_LANE2_EQ_PRESET_CP1 (PET_PMA3_LANE2_BASE + 4*0xF7) //Attributes : RW +#define PET_PMA3_LANE2_EQ_SUCC_MASK (PET_PMA3_LANE2_BASE + 4*0xF8) //Attributes : RW +#define PET_PMA3_LANE2_PMA_COM_SCRATCH (PET_PMA3_LANE2_BASE + 4*0xff) //Attributes : RW +#define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY0 (PET_PMA3_LANE2_BASE + 4*0x100) //Attributes : RO_EXT_L +#define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY1 (PET_PMA3_LANE2_BASE + 4*0x101) //Attributes : RO_EXT +#define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY2 (PET_PMA3_LANE2_BASE + 4*0x102) //Attributes : RO_EXT +#define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY3 (PET_PMA3_LANE2_BASE + 4*0x103) //Attributes : RO_EXT +#define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY4 (PET_PMA3_LANE2_BASE + 4*0x104) //Attributes : RO_EXT +#define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY5 (PET_PMA3_LANE2_BASE + 4*0x105) //Attributes : RO_EXT +#define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY6 (PET_PMA3_LANE2_BASE + 4*0x106) //Attributes : RO_EXT +#define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY7 (PET_PMA3_LANE2_BASE + 4*0x107) //Attributes : RO_EXT_H +#define PET_PMA3_LANE2_EQ_TX_FSM_HISTORY_CTRL (PET_PMA3_LANE2_BASE + 4*0x108) //Attributes : RW +#define PET_PMA3_LANE2_EQ_RX_FSM_HISTORY0 (PET_PMA3_LANE2_BASE + 4*0x109) //Attributes : RO_EXT_L +#define PET_PMA3_LANE2_EQ_RX_FSM_HISTORY1 (PET_PMA3_LANE2_BASE + 4*0x10A) //Attributes : RO_EXT +#define PET_PMA3_LANE2_EQ_RX_FSM_HISTORY2 (PET_PMA3_LANE2_BASE + 4*0x10B) //Attributes : RO_EXT +#define PET_PMA3_LANE2_EQ_RX_FSM_HISTORY3 (PET_PMA3_LANE2_BASE + 4*0x10C) //Attributes : RO_EXT_H +#define PET_PMA3_LANE2_EQ_RX_FSM_HISTORY_CTRL (PET_PMA3_LANE2_BASE + 4*0x10D) //Attributes : RW +#define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY0 (PET_PMA3_LANE2_BASE + 4*0x110) //Attributes : RO_EXT_L +#define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY1 (PET_PMA3_LANE2_BASE + 4*0x111) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY2 (PET_PMA3_LANE2_BASE + 4*0x112) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY3 (PET_PMA3_LANE2_BASE + 4*0x113) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY4 (PET_PMA3_LANE2_BASE + 4*0x114) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY5 (PET_PMA3_LANE2_BASE + 4*0x115) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY6 (PET_PMA3_LANE2_BASE + 4*0x116) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY7 (PET_PMA3_LANE2_BASE + 4*0x117) //Attributes : RO_EXT_H +#define PET_PMA3_LANE2_TX_EQ_MAIN_HISTORY_CTRL (PET_PMA3_LANE2_BASE + 4*0x118) //Attributes : RW +#define PET_PMA3_LANE2_RX_TXMAIN_DIR_HISTORY0 (PET_PMA3_LANE2_BASE + 4*0x119) //Attributes : RO_EXT_L +#define PET_PMA3_LANE2_RX_TXMAIN_DIR_HISTORY1 (PET_PMA3_LANE2_BASE + 4*0x11A) //Attributes : RO_EXT +#define PET_PMA3_LANE2_RX_TXMAIN_DIR_HISTORY2 (PET_PMA3_LANE2_BASE + 4*0x11B) //Attributes : RO_EXT +#define PET_PMA3_LANE2_RX_TXMAIN_DIR_HISTORY3 (PET_PMA3_LANE2_BASE + 4*0x11C) //Attributes : RO_EXT_H +#define PET_PMA3_LANE2_RX_TXMAIN_DIR_HISTORY_CTRL (PET_PMA3_LANE2_BASE + 4*0x11D) //Attributes : RW +#define PET_PMA3_LANE2_TX_EQ_POST_HISTORY0 (PET_PMA3_LANE2_BASE + 4*0x120) //Attributes : RO_EXT_L +#define PET_PMA3_LANE2_TX_EQ_POST_HISTORY1 (PET_PMA3_LANE2_BASE + 4*0x121) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_POST_HISTORY2 (PET_PMA3_LANE2_BASE + 4*0x122) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_POST_HISTORY3 (PET_PMA3_LANE2_BASE + 4*0x123) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_POST_HISTORY4 (PET_PMA3_LANE2_BASE + 4*0x124) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_POST_HISTORY5 (PET_PMA3_LANE2_BASE + 4*0x125) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_POST_HISTORY6 (PET_PMA3_LANE2_BASE + 4*0x126) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_POST_HISTORY7 (PET_PMA3_LANE2_BASE + 4*0x127) //Attributes : RO_EXT_H +#define PET_PMA3_LANE2_TX_EQ_POST_HISTORY_CTRL (PET_PMA3_LANE2_BASE + 4*0x128) //Attributes : RW +#define PET_PMA3_LANE2_RX_TXPOST_DIR_HISTORY0 (PET_PMA3_LANE2_BASE + 4*0x129) //Attributes : RO_EXT_L +#define PET_PMA3_LANE2_RX_TXPOST_DIR_HISTORY1 (PET_PMA3_LANE2_BASE + 4*0x12A) //Attributes : RO_EXT +#define PET_PMA3_LANE2_RX_TXPOST_DIR_HISTORY2 (PET_PMA3_LANE2_BASE + 4*0x12B) //Attributes : RO_EXT +#define PET_PMA3_LANE2_RX_TXPOST_DIR_HISTORY3 (PET_PMA3_LANE2_BASE + 4*0x12C) //Attributes : RO_EXT_H +#define PET_PMA3_LANE2_RX_TXPOST_DIR_HISTORY_CTRL (PET_PMA3_LANE2_BASE + 4*0x12D) //Attributes : RW +#define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY0 (PET_PMA3_LANE2_BASE + 4*0x130) //Attributes : RO_EXT_L +#define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY1 (PET_PMA3_LANE2_BASE + 4*0x131) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY2 (PET_PMA3_LANE2_BASE + 4*0x132) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY3 (PET_PMA3_LANE2_BASE + 4*0x133) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY4 (PET_PMA3_LANE2_BASE + 4*0x134) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY5 (PET_PMA3_LANE2_BASE + 4*0x135) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY6 (PET_PMA3_LANE2_BASE + 4*0x136) //Attributes : RO_EXT +#define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY7 (PET_PMA3_LANE2_BASE + 4*0x137) //Attributes : RO_EXT_H +#define PET_PMA3_LANE2_TX_EQ_PRE_HISTORY_CTRL (PET_PMA3_LANE2_BASE + 4*0x138) //Attributes : RW +#define PET_PMA3_LANE2_RX_TXPRE_DIR_HISTORY0 (PET_PMA3_LANE2_BASE + 4*0x139) //Attributes : RO_EXT_L +#define PET_PMA3_LANE2_RX_TXPRE_DIR_HISTORY1 (PET_PMA3_LANE2_BASE + 4*0x13A) //Attributes : RO_EXT +#define PET_PMA3_LANE2_RX_TXPRE_DIR_HISTORY2 (PET_PMA3_LANE2_BASE + 4*0x13B) //Attributes : RO_EXT +#define PET_PMA3_LANE2_RX_TXPRE_DIR_HISTORY3 (PET_PMA3_LANE2_BASE + 4*0x13C) //Attributes : RO_EXT_H +#define PET_PMA3_LANE2_RX_TXPRE_DIR_HISTORY_CTRL (PET_PMA3_LANE2_BASE + 4*0x13D) //Attributes : RW + +#define PET_PMA3_LANE3_PMA_LOOPBACK_CTRL (PET_PMA3_LANE3_BASE + 4*0x00) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_REQ (PET_PMA3_LANE3_BASE + 4*0x01) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_REQ_ACK (PET_PMA3_LANE3_BASE + 4*0x02) //Attributes : RO +#define PET_PMA3_LANE3_RECEIVER_REQ_PARAM2 (PET_PMA3_LANE3_BASE + 4*0x03) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_REQ_PARAM3 (PET_PMA3_LANE3_BASE + 4*0x04) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_REQ_PARAM4 (PET_PMA3_LANE3_BASE + 4*0x05) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_REQ_PARAM5 (PET_PMA3_LANE3_BASE + 4*0x06) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_REQ_PARAM6 (PET_PMA3_LANE3_BASE + 4*0x07) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_REQ_PARAM7 (PET_PMA3_LANE3_BASE + 4*0x08) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_REQ_PARAM8 (PET_PMA3_LANE3_BASE + 4*0x09) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_REQ_PARAM9 (PET_PMA3_LANE3_BASE + 4*0x0A) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_REQ_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x0B) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_ADAPT_REQ (PET_PMA3_LANE3_BASE + 4*0x10) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_ADAPT_REQ_ACK (PET_PMA3_LANE3_BASE + 4*0x11) //Attributes : RO +#define PET_PMA3_LANE3_RECEIVER_ADAPT_DIR (PET_PMA3_LANE3_BASE + 4*0x12) //Attributes : RO +#define PET_PMA3_LANE3_RECEIVER_ADAPT_SETTING (PET_PMA3_LANE3_BASE + 4*0x13) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_ADAPT_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x14) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_DATAPATH_EN (PET_PMA3_LANE3_BASE + 4*0x20) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_DATAPATH_SETTING1 (PET_PMA3_LANE3_BASE + 4*0x21) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_DATAPATH_SETTING2 (PET_PMA3_LANE3_BASE + 4*0x22) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_DATAPATH_SETTING3 (PET_PMA3_LANE3_BASE + 4*0x23) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_DATAPATH_STATUS1 (PET_PMA3_LANE3_BASE + 4*0x24) //Attributes : RO +#define PET_PMA3_LANE3_RECEIVER_DATAPATH_STATUS2 (PET_PMA3_LANE3_BASE + 4*0x25) //Attributes : RO +#define PET_PMA3_LANE3_RECEIVER_DATAPATH_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x26) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_RESET (PET_PMA3_LANE3_BASE + 4*0x30) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_CONTROL (PET_PMA3_LANE3_BASE + 4*0x31) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_CONTROL_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x32) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_RECAL_CTRL (PET_PMA3_LANE3_BASE + 4*0x40) //Attributes : RW +#define PET_PMA3_LANE3_RECEIVER_RECAL_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x41) //Attributes : RW +#define PET_PMA3_LANE3_TRANSMITTER_REQ (PET_PMA3_LANE3_BASE + 4*0x50) //Attributes : RW +#define PET_PMA3_LANE3_TRANSMITTER_REQ_ACK (PET_PMA3_LANE3_BASE + 4*0x51) //Attributes : RO +#define PET_PMA3_LANE3_TRANSMITTER_REQ_PARAM1 (PET_PMA3_LANE3_BASE + 4*0x52) //Attributes : RW +#define PET_PMA3_LANE3_TRANSMITTER_REQ_PARAM2 (PET_PMA3_LANE3_BASE + 4*0x53) //Attributes : RW +#define PET_PMA3_LANE3_TRANSMITTER_REQ_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x55) //Attributes : RW +#define PET_PMA3_LANE3_TRANSMITTER_DATAPATH_EN (PET_PMA3_LANE3_BASE + 4*0x60) //Attributes : RW +#define PET_PMA3_LANE3_TRANSMITTER_DATAPATH_CLKRDY (PET_PMA3_LANE3_BASE + 4*0x61) //Attributes : RW +#define PET_PMA3_LANE3_TRANSMITTER_DATAPATH_SETTING (PET_PMA3_LANE3_BASE + 4*0x62) //Attributes : RW +#define PET_PMA3_LANE3_TRANSMITTER_DATAPATH_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x63) //Attributes : RW +#define PET_PMA3_LANE3_TRANSMITTER_CONTROL1 (PET_PMA3_LANE3_BASE + 4*0x70) //Attributes : RW +#define PET_PMA3_LANE3_TRANSMITTER_CONTROL2 (PET_PMA3_LANE3_BASE + 4*0x71) //Attributes : RW +#define PET_PMA3_LANE3_TRANSMITTER_CONTROL_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x72) //Attributes : RW +#define PET_PMA3_LANE3_TRANSMITTER_EQ1 (PET_PMA3_LANE3_BASE + 4*0x80) //Attributes : RW +#define PET_PMA3_LANE3_TRANSMITTER_EQ2 (PET_PMA3_LANE3_BASE + 4*0x81) //Attributes : RW +#define PET_PMA3_LANE3_TRANSMITTER_EQ3 (PET_PMA3_LANE3_BASE + 4*0x82) //Attributes : RW +#define PET_PMA3_LANE3_TRANSMITTER_EQ_MUX_CTRL (PET_PMA3_LANE3_BASE + 4*0x83) //Attributes : RW +#define PET_PMA3_LANE3_CONTEXT_RESTORE_CTRL1 (PET_PMA3_LANE3_BASE + 4*0x90) //Attributes : RW +#define PET_PMA3_LANE3_CONTEXT_RESTORE_CTRL2 (PET_PMA3_LANE3_BASE + 4*0x91) //Attributes : RW +#define PET_PMA3_LANE3_CONTEXT_RESTORE_CTRL3 (PET_PMA3_LANE3_BASE + 4*0x92) //Attributes : RW +#define PET_PMA3_LANE3_CONTEXT_RESTORE_CTRL4 (PET_PMA3_LANE3_BASE + 4*0x93) //Attributes : RW +#define PET_PMA3_LANE3_CONTEXT_RESTORE_MUX (PET_PMA3_LANE3_BASE + 4*0x94) //Attributes : RW +#define PET_PMA3_LANE3_LANE_REFCLK_SEL (PET_PMA3_LANE3_BASE + 4*0xA0) //Attributes : RW +#define PET_PMA3_LANE3_ETH_CLK_CTRL (PET_PMA3_LANE3_BASE + 4*0xB0) //Attributes : RW +#define PET_PMA3_LANE3_ETH_CLK_CTRL_MUX (PET_PMA3_LANE3_BASE + 4*0xB1) //Attributes : RW +#define PET_PMA3_LANE3_RX_ADAPT_CTRL (PET_PMA3_LANE3_BASE + 4*0xC0) //Attributes : RW +#define PET_PMA3_LANE3_RX_DCC_CTRL (PET_PMA3_LANE3_BASE + 4*0xC1) //Attributes : RW +#define PET_PMA3_LANE3_RX_EQ_CTRL1 (PET_PMA3_LANE3_BASE + 4*0xC2) //Attributes : RW +#define PET_PMA3_LANE3_RX_EQ_CTRL2 (PET_PMA3_LANE3_BASE + 4*0xC3) //Attributes : RW +#define PET_PMA3_LANE3_RX_MARGIN_CTRL (PET_PMA3_LANE3_BASE + 4*0xC4) //Attributes : RW +#define PET_PMA3_LANE3_RX_MARGIN_ERROR (PET_PMA3_LANE3_BASE + 4*0xC5) //Attributes : RO +#define PET_PMA3_LANE3_RECV_REQUEST_CTRL_MUX (PET_PMA3_LANE3_BASE + 4*0xC6) //Attributes : RW +#define PET_PMA3_LANE3_RX_COARSE_ADAPT_CTRL (PET_PMA3_LANE3_BASE + 4*0xC8) //Attributes : RW +#define PET_PMA3_LANE3_RX_COARSE_ADAPT_CTRL_MUX (PET_PMA3_LANE3_BASE + 4*0xC9) //Attributes : RW +#define PET_PMA3_LANE3_RX_DIV_CLK_CTRL (PET_PMA3_LANE3_BASE + 4*0xCA) //Attributes : RW +#define PET_PMA3_LANE3_TX_DIV_CLK_CTRL (PET_PMA3_LANE3_BASE + 4*0xCB) //Attributes : RW +#define PET_PMA3_LANE3_MULTI_CLK_CTRL_MUX (PET_PMA3_LANE3_BASE + 4*0xCC) //Attributes : RW +#define PET_PMA3_LANE3_TRANS_REQ_CTRL1 (PET_PMA3_LANE3_BASE + 4*0xD0) //Attributes : RW +#define PET_PMA3_LANE3_TRANS_REQ_CTRL2 (PET_PMA3_LANE3_BASE + 4*0xD1) //Attributes : RW +#define PET_PMA3_LANE3_TRANS_REQ_CTRL3 (PET_PMA3_LANE3_BASE + 4*0xD2) //Attributes : RW +#define PET_PMA3_LANE3_TRANS_REQ_CTRL4 (PET_PMA3_LANE3_BASE + 4*0xD3) //Attributes : RW +#define PET_PMA3_LANE3_TRANS_REQ_CTRL5 (PET_PMA3_LANE3_BASE + 4*0xD4) //Attributes : RW +#define PET_PMA3_LANE3_TRANS_REQ_MUX (PET_PMA3_LANE3_BASE + 4*0xD5) //Attributes : RW +#define PET_PMA3_LANE3_TRANS_INTERFACE_CTRL (PET_PMA3_LANE3_BASE + 4*0xD6) //Attributes : RW +#define PET_PMA3_LANE3_TRANS_INTERFACE_MUX (PET_PMA3_LANE3_BASE + 4*0xD7) //Attributes : RW +#define PET_PMA3_LANE3_TRANS_MASTER_PLL_STATE (PET_PMA3_LANE3_BASE + 4*0xD8) //Attributes : RW +#define PET_PMA3_LANE3_TRANS_PLL_STATE (PET_PMA3_LANE3_BASE + 4*0xD9) //Attributes : RO +#define PET_PMA3_LANE3_PLL_STATE_MUX (PET_PMA3_LANE3_BASE + 4*0xDA) //Attributes : RW +#define PET_PMA3_LANE3_RX_VALID_PHY (PET_PMA3_LANE3_BASE + 4*0xDF) //Attributes : RO +#define PET_PMA3_LANE3_RX_VALID_MUX (PET_PMA3_LANE3_BASE + 4*0xE0) //Attributes : RW +#define PET_PMA3_LANE3_RX_SRIO_SIGDET_MUX (PET_PMA3_LANE3_BASE + 4*0xE1) //Attributes : RW +#define PET_PMA3_LANE3_SRIO_DEGRADED (PET_PMA3_LANE3_BASE + 4*0xE2) //Attributes : RW +#define PET_PMA3_LANE3_SRIO_RETRAIN (PET_PMA3_LANE3_BASE + 4*0xE3) //Attributes : RW +#define PET_PMA3_LANE3_SRIO_SHORT_RUN (PET_PMA3_LANE3_BASE + 4*0xE4) //Attributes : RW +#define PET_PMA3_LANE3_EQ_INIT_C0 (PET_PMA3_LANE3_BASE + 4*0xE5) //Attributes : RW +#define PET_PMA3_LANE3_EQ_INIT_CN1 (PET_PMA3_LANE3_BASE + 4*0xE6) //Attributes : RW +#define PET_PMA3_LANE3_EQ_INIT_CP1 (PET_PMA3_LANE3_BASE + 4*0xE7) //Attributes : RW +#define PET_PMA3_LANE3_EQ_RULE_CTRL_1 (PET_PMA3_LANE3_BASE + 4*0xE8) //Attributes : RW +#define PET_PMA3_LANE3_EQ_RULE_CTRL_2 (PET_PMA3_LANE3_BASE + 4*0xE9) //Attributes : RW +#define PET_PMA3_LANE3_EQ_RULE_CTRL_3 (PET_PMA3_LANE3_BASE + 4*0xEA) //Attributes : RW +#define PET_PMA3_LANE3_EQ_RULE_CTRL_4 (PET_PMA3_LANE3_BASE + 4*0xEB) //Attributes : RW +#define PET_PMA3_LANE3_EQ_ALGORITHM_CTRL (PET_PMA3_LANE3_BASE + 4*0xEC) //Attributes : RW +#define PET_PMA3_LANE3_EQ_TX_TRAIN_CTRL (PET_PMA3_LANE3_BASE + 4*0xED) //Attributes : RW +#define PET_PMA3_LANE3_EQ_ADJ_INTERVAL (PET_PMA3_LANE3_BASE + 4*0xEE) //Attributes : RW +#define PET_PMA3_LANE3_EQ_RX_REQ_CTRL (PET_PMA3_LANE3_BASE + 4*0xEF) //Attributes : RW +#define PET_PMA3_LANE3_EQ_RX_TRAIN_CTRL (PET_PMA3_LANE3_BASE + 4*0xF0) //Attributes : RW +#define PET_PMA3_LANE3_EQ_RX_RESET_CYCLE (PET_PMA3_LANE3_BASE + 4*0xF1) //Attributes : RW +#define PET_PMA3_LANE3_RPCS_KTR_STATUS (PET_PMA3_LANE3_BASE + 4*0xF2) //Attributes : RO +#define PET_PMA3_LANE3_EQ_FSM (PET_PMA3_LANE3_BASE + 4*0xF3) //Attributes : RO +#define PET_PMA3_LANE3_ETH_RX_LOS (PET_PMA3_LANE3_BASE + 4*0xF4) //Attributes : RW +#define PET_PMA3_LANE3_EQ_PRESET_C0 (PET_PMA3_LANE3_BASE + 4*0xF5) //Attributes : RW +#define PET_PMA3_LANE3_EQ_PRESET_CN1 (PET_PMA3_LANE3_BASE + 4*0xF6) //Attributes : RW +#define PET_PMA3_LANE3_EQ_PRESET_CP1 (PET_PMA3_LANE3_BASE + 4*0xF7) //Attributes : RW +#define PET_PMA3_LANE3_EQ_SUCC_MASK (PET_PMA3_LANE3_BASE + 4*0xF8) //Attributes : RW +#define PET_PMA3_LANE3_PMA_COM_SCRATCH (PET_PMA3_LANE3_BASE + 4*0xff) //Attributes : RW +#define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY0 (PET_PMA3_LANE3_BASE + 4*0x100) //Attributes : RO_EXT_L +#define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY1 (PET_PMA3_LANE3_BASE + 4*0x101) //Attributes : RO_EXT +#define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY2 (PET_PMA3_LANE3_BASE + 4*0x102) //Attributes : RO_EXT +#define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY3 (PET_PMA3_LANE3_BASE + 4*0x103) //Attributes : RO_EXT +#define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY4 (PET_PMA3_LANE3_BASE + 4*0x104) //Attributes : RO_EXT +#define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY5 (PET_PMA3_LANE3_BASE + 4*0x105) //Attributes : RO_EXT +#define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY6 (PET_PMA3_LANE3_BASE + 4*0x106) //Attributes : RO_EXT +#define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY7 (PET_PMA3_LANE3_BASE + 4*0x107) //Attributes : RO_EXT_H +#define PET_PMA3_LANE3_EQ_TX_FSM_HISTORY_CTRL (PET_PMA3_LANE3_BASE + 4*0x108) //Attributes : RW +#define PET_PMA3_LANE3_EQ_RX_FSM_HISTORY0 (PET_PMA3_LANE3_BASE + 4*0x109) //Attributes : RO_EXT_L +#define PET_PMA3_LANE3_EQ_RX_FSM_HISTORY1 (PET_PMA3_LANE3_BASE + 4*0x10A) //Attributes : RO_EXT +#define PET_PMA3_LANE3_EQ_RX_FSM_HISTORY2 (PET_PMA3_LANE3_BASE + 4*0x10B) //Attributes : RO_EXT +#define PET_PMA3_LANE3_EQ_RX_FSM_HISTORY3 (PET_PMA3_LANE3_BASE + 4*0x10C) //Attributes : RO_EXT_H +#define PET_PMA3_LANE3_EQ_RX_FSM_HISTORY_CTRL (PET_PMA3_LANE3_BASE + 4*0x10D) //Attributes : RW +#define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY0 (PET_PMA3_LANE3_BASE + 4*0x110) //Attributes : RO_EXT_L +#define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY1 (PET_PMA3_LANE3_BASE + 4*0x111) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY2 (PET_PMA3_LANE3_BASE + 4*0x112) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY3 (PET_PMA3_LANE3_BASE + 4*0x113) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY4 (PET_PMA3_LANE3_BASE + 4*0x114) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY5 (PET_PMA3_LANE3_BASE + 4*0x115) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY6 (PET_PMA3_LANE3_BASE + 4*0x116) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY7 (PET_PMA3_LANE3_BASE + 4*0x117) //Attributes : RO_EXT_H +#define PET_PMA3_LANE3_TX_EQ_MAIN_HISTORY_CTRL (PET_PMA3_LANE3_BASE + 4*0x118) //Attributes : RW +#define PET_PMA3_LANE3_RX_TXMAIN_DIR_HISTORY0 (PET_PMA3_LANE3_BASE + 4*0x119) //Attributes : RO_EXT_L +#define PET_PMA3_LANE3_RX_TXMAIN_DIR_HISTORY1 (PET_PMA3_LANE3_BASE + 4*0x11A) //Attributes : RO_EXT +#define PET_PMA3_LANE3_RX_TXMAIN_DIR_HISTORY2 (PET_PMA3_LANE3_BASE + 4*0x11B) //Attributes : RO_EXT +#define PET_PMA3_LANE3_RX_TXMAIN_DIR_HISTORY3 (PET_PMA3_LANE3_BASE + 4*0x11C) //Attributes : RO_EXT_H +#define PET_PMA3_LANE3_RX_TXMAIN_DIR_HISTORY_CTRL (PET_PMA3_LANE3_BASE + 4*0x11D) //Attributes : RW +#define PET_PMA3_LANE3_TX_EQ_POST_HISTORY0 (PET_PMA3_LANE3_BASE + 4*0x120) //Attributes : RO_EXT_L +#define PET_PMA3_LANE3_TX_EQ_POST_HISTORY1 (PET_PMA3_LANE3_BASE + 4*0x121) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_POST_HISTORY2 (PET_PMA3_LANE3_BASE + 4*0x122) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_POST_HISTORY3 (PET_PMA3_LANE3_BASE + 4*0x123) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_POST_HISTORY4 (PET_PMA3_LANE3_BASE + 4*0x124) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_POST_HISTORY5 (PET_PMA3_LANE3_BASE + 4*0x125) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_POST_HISTORY6 (PET_PMA3_LANE3_BASE + 4*0x126) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_POST_HISTORY7 (PET_PMA3_LANE3_BASE + 4*0x127) //Attributes : RO_EXT_H +#define PET_PMA3_LANE3_TX_EQ_POST_HISTORY_CTRL (PET_PMA3_LANE3_BASE + 4*0x128) //Attributes : RW +#define PET_PMA3_LANE3_RX_TXPOST_DIR_HISTORY0 (PET_PMA3_LANE3_BASE + 4*0x129) //Attributes : RO_EXT_L +#define PET_PMA3_LANE3_RX_TXPOST_DIR_HISTORY1 (PET_PMA3_LANE3_BASE + 4*0x12A) //Attributes : RO_EXT +#define PET_PMA3_LANE3_RX_TXPOST_DIR_HISTORY2 (PET_PMA3_LANE3_BASE + 4*0x12B) //Attributes : RO_EXT +#define PET_PMA3_LANE3_RX_TXPOST_DIR_HISTORY3 (PET_PMA3_LANE3_BASE + 4*0x12C) //Attributes : RO_EXT_H +#define PET_PMA3_LANE3_RX_TXPOST_DIR_HISTORY_CTRL (PET_PMA3_LANE3_BASE + 4*0x12D) //Attributes : RW +#define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY0 (PET_PMA3_LANE3_BASE + 4*0x130) //Attributes : RO_EXT_L +#define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY1 (PET_PMA3_LANE3_BASE + 4*0x131) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY2 (PET_PMA3_LANE3_BASE + 4*0x132) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY3 (PET_PMA3_LANE3_BASE + 4*0x133) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY4 (PET_PMA3_LANE3_BASE + 4*0x134) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY5 (PET_PMA3_LANE3_BASE + 4*0x135) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY6 (PET_PMA3_LANE3_BASE + 4*0x136) //Attributes : RO_EXT +#define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY7 (PET_PMA3_LANE3_BASE + 4*0x137) //Attributes : RO_EXT_H +#define PET_PMA3_LANE3_TX_EQ_PRE_HISTORY_CTRL (PET_PMA3_LANE3_BASE + 4*0x138) //Attributes : RW +#define PET_PMA3_LANE3_RX_TXPRE_DIR_HISTORY0 (PET_PMA3_LANE3_BASE + 4*0x139) //Attributes : RO_EXT_L +#define PET_PMA3_LANE3_RX_TXPRE_DIR_HISTORY1 (PET_PMA3_LANE3_BASE + 4*0x13A) //Attributes : RO_EXT +#define PET_PMA3_LANE3_RX_TXPRE_DIR_HISTORY2 (PET_PMA3_LANE3_BASE + 4*0x13B) //Attributes : RO_EXT +#define PET_PMA3_LANE3_RX_TXPRE_DIR_HISTORY3 (PET_PMA3_LANE3_BASE + 4*0x13C) //Attributes : RO_EXT_H +#define PET_PMA3_LANE3_RX_TXPRE_DIR_HISTORY_CTRL (PET_PMA3_LANE3_BASE + 4*0x13D) //Attributes : RW + +#define PET_PMA3_BROADCAST_PMA_LOOPBACK_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x00) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_REQ (PET_PMA3_BROADCAST_BASE + 4*0x01) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_REQ_ACK (PET_PMA3_BROADCAST_BASE + 4*0x02) //Attributes : RO +#define PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM2 (PET_PMA3_BROADCAST_BASE + 4*0x03) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM3 (PET_PMA3_BROADCAST_BASE + 4*0x04) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM4 (PET_PMA3_BROADCAST_BASE + 4*0x05) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM5 (PET_PMA3_BROADCAST_BASE + 4*0x06) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM6 (PET_PMA3_BROADCAST_BASE + 4*0x07) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM7 (PET_PMA3_BROADCAST_BASE + 4*0x08) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM8 (PET_PMA3_BROADCAST_BASE + 4*0x09) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM9 (PET_PMA3_BROADCAST_BASE + 4*0x0A) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_REQ_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x0B) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_ADAPT_REQ (PET_PMA3_BROADCAST_BASE + 4*0x10) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_ADAPT_REQ_ACK (PET_PMA3_BROADCAST_BASE + 4*0x11) //Attributes : RO +#define PET_PMA3_BROADCAST_RECEIVER_ADAPT_DIR (PET_PMA3_BROADCAST_BASE + 4*0x12) //Attributes : RO +#define PET_PMA3_BROADCAST_RECEIVER_ADAPT_SETTING (PET_PMA3_BROADCAST_BASE + 4*0x13) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_ADAPT_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x14) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_DATAPATH_EN (PET_PMA3_BROADCAST_BASE + 4*0x20) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_DATAPATH_SETTING1 (PET_PMA3_BROADCAST_BASE + 4*0x21) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_DATAPATH_SETTING2 (PET_PMA3_BROADCAST_BASE + 4*0x22) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_DATAPATH_SETTING3 (PET_PMA3_BROADCAST_BASE + 4*0x23) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_DATAPATH_STATUS1 (PET_PMA3_BROADCAST_BASE + 4*0x24) //Attributes : RO +#define PET_PMA3_BROADCAST_RECEIVER_DATAPATH_STATUS2 (PET_PMA3_BROADCAST_BASE + 4*0x25) //Attributes : RO +#define PET_PMA3_BROADCAST_RECEIVER_DATAPATH_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x26) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_RESET (PET_PMA3_BROADCAST_BASE + 4*0x30) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_CONTROL (PET_PMA3_BROADCAST_BASE + 4*0x31) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_CONTROL_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x32) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_RECAL_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x40) //Attributes : RW +#define PET_PMA3_BROADCAST_RECEIVER_RECAL_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x41) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANSMITTER_REQ (PET_PMA3_BROADCAST_BASE + 4*0x50) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANSMITTER_REQ_ACK (PET_PMA3_BROADCAST_BASE + 4*0x51) //Attributes : RO +#define PET_PMA3_BROADCAST_TRANSMITTER_REQ_PARAM1 (PET_PMA3_BROADCAST_BASE + 4*0x52) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANSMITTER_REQ_PARAM2 (PET_PMA3_BROADCAST_BASE + 4*0x53) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANSMITTER_REQ_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x55) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANSMITTER_DATAPATH_EN (PET_PMA3_BROADCAST_BASE + 4*0x60) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANSMITTER_DATAPATH_CLKRDY (PET_PMA3_BROADCAST_BASE + 4*0x61) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANSMITTER_DATAPATH_SETTING (PET_PMA3_BROADCAST_BASE + 4*0x62) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANSMITTER_DATAPATH_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x63) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANSMITTER_CONTROL1 (PET_PMA3_BROADCAST_BASE + 4*0x70) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANSMITTER_CONTROL2 (PET_PMA3_BROADCAST_BASE + 4*0x71) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANSMITTER_CONTROL_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x72) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANSMITTER_EQ1 (PET_PMA3_BROADCAST_BASE + 4*0x80) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANSMITTER_EQ2 (PET_PMA3_BROADCAST_BASE + 4*0x81) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANSMITTER_EQ3 (PET_PMA3_BROADCAST_BASE + 4*0x82) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANSMITTER_EQ_MUX_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x83) //Attributes : RW +#define PET_PMA3_BROADCAST_CONTEXT_RESTORE_CTRL1 (PET_PMA3_BROADCAST_BASE + 4*0x90) //Attributes : RW +#define PET_PMA3_BROADCAST_CONTEXT_RESTORE_CTRL2 (PET_PMA3_BROADCAST_BASE + 4*0x91) //Attributes : RW +#define PET_PMA3_BROADCAST_CONTEXT_RESTORE_CTRL3 (PET_PMA3_BROADCAST_BASE + 4*0x92) //Attributes : RW +#define PET_PMA3_BROADCAST_CONTEXT_RESTORE_CTRL4 (PET_PMA3_BROADCAST_BASE + 4*0x93) //Attributes : RW +#define PET_PMA3_BROADCAST_CONTEXT_RESTORE_MUX (PET_PMA3_BROADCAST_BASE + 4*0x94) //Attributes : RW +#define PET_PMA3_BROADCAST_LANE_REFCLK_SEL (PET_PMA3_BROADCAST_BASE + 4*0xA0) //Attributes : RW +#define PET_PMA3_BROADCAST_ETH_CLK_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xB0) //Attributes : RW +#define PET_PMA3_BROADCAST_ETH_CLK_CTRL_MUX (PET_PMA3_BROADCAST_BASE + 4*0xB1) //Attributes : RW +#define PET_PMA3_BROADCAST_RX_ADAPT_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xC0) //Attributes : RW +#define PET_PMA3_BROADCAST_RX_DCC_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xC1) //Attributes : RW +#define PET_PMA3_BROADCAST_RX_EQ_CTRL1 (PET_PMA3_BROADCAST_BASE + 4*0xC2) //Attributes : RW +#define PET_PMA3_BROADCAST_RX_EQ_CTRL2 (PET_PMA3_BROADCAST_BASE + 4*0xC3) //Attributes : RW +#define PET_PMA3_BROADCAST_RX_MARGIN_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xC4) //Attributes : RW +#define PET_PMA3_BROADCAST_RX_MARGIN_ERROR (PET_PMA3_BROADCAST_BASE + 4*0xC5) //Attributes : RO +#define PET_PMA3_BROADCAST_RECV_REQUEST_CTRL_MUX (PET_PMA3_BROADCAST_BASE + 4*0xC6) //Attributes : RW +#define PET_PMA3_BROADCAST_RX_COARSE_ADAPT_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xC8) //Attributes : RW +#define PET_PMA3_BROADCAST_RX_COARSE_ADAPT_CTRL_MUX (PET_PMA3_BROADCAST_BASE + 4*0xC9) //Attributes : RW +#define PET_PMA3_BROADCAST_RX_DIV_CLK_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xCA) //Attributes : RW +#define PET_PMA3_BROADCAST_TX_DIV_CLK_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xCB) //Attributes : RW +#define PET_PMA3_BROADCAST_MULTI_CLK_CTRL_MUX (PET_PMA3_BROADCAST_BASE + 4*0xCC) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANS_REQ_CTRL1 (PET_PMA3_BROADCAST_BASE + 4*0xD0) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANS_REQ_CTRL2 (PET_PMA3_BROADCAST_BASE + 4*0xD1) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANS_REQ_CTRL3 (PET_PMA3_BROADCAST_BASE + 4*0xD2) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANS_REQ_CTRL4 (PET_PMA3_BROADCAST_BASE + 4*0xD3) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANS_REQ_CTRL5 (PET_PMA3_BROADCAST_BASE + 4*0xD4) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANS_REQ_MUX (PET_PMA3_BROADCAST_BASE + 4*0xD5) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANS_INTERFACE_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xD6) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANS_INTERFACE_MUX (PET_PMA3_BROADCAST_BASE + 4*0xD7) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANS_MASTER_PLL_STATE (PET_PMA3_BROADCAST_BASE + 4*0xD8) //Attributes : RW +#define PET_PMA3_BROADCAST_TRANS_PLL_STATE (PET_PMA3_BROADCAST_BASE + 4*0xD9) //Attributes : RO +#define PET_PMA3_BROADCAST_PLL_STATE_MUX (PET_PMA3_BROADCAST_BASE + 4*0xDA) //Attributes : RW +#define PET_PMA3_BROADCAST_RX_VALID_PHY (PET_PMA3_BROADCAST_BASE + 4*0xDF) //Attributes : RO +#define PET_PMA3_BROADCAST_RX_VALID_MUX (PET_PMA3_BROADCAST_BASE + 4*0xE0) //Attributes : RW +#define PET_PMA3_BROADCAST_RX_SRIO_SIGDET_MUX (PET_PMA3_BROADCAST_BASE + 4*0xE1) //Attributes : RW +#define PET_PMA3_BROADCAST_SRIO_DEGRADED (PET_PMA3_BROADCAST_BASE + 4*0xE2) //Attributes : RW +#define PET_PMA3_BROADCAST_SRIO_RETRAIN (PET_PMA3_BROADCAST_BASE + 4*0xE3) //Attributes : RW +#define PET_PMA3_BROADCAST_SRIO_SHORT_RUN (PET_PMA3_BROADCAST_BASE + 4*0xE4) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_INIT_C0 (PET_PMA3_BROADCAST_BASE + 4*0xE5) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_INIT_CN1 (PET_PMA3_BROADCAST_BASE + 4*0xE6) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_INIT_CP1 (PET_PMA3_BROADCAST_BASE + 4*0xE7) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_RULE_CTRL_1 (PET_PMA3_BROADCAST_BASE + 4*0xE8) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_RULE_CTRL_2 (PET_PMA3_BROADCAST_BASE + 4*0xE9) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_RULE_CTRL_3 (PET_PMA3_BROADCAST_BASE + 4*0xEA) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_RULE_CTRL_4 (PET_PMA3_BROADCAST_BASE + 4*0xEB) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_ALGORITHM_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xEC) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_TX_TRAIN_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xED) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_ADJ_INTERVAL (PET_PMA3_BROADCAST_BASE + 4*0xEE) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_RX_REQ_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xEF) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_RX_TRAIN_CTRL (PET_PMA3_BROADCAST_BASE + 4*0xF0) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_RX_RESET_CYCLE (PET_PMA3_BROADCAST_BASE + 4*0xF1) //Attributes : RW +#define PET_PMA3_BROADCAST_RPCS_KTR_STATUS (PET_PMA3_BROADCAST_BASE + 4*0xF2) //Attributes : RO +#define PET_PMA3_BROADCAST_EQ_FSM (PET_PMA3_BROADCAST_BASE + 4*0xF3) //Attributes : RO +#define PET_PMA3_BROADCAST_ETH_RX_LOS (PET_PMA3_BROADCAST_BASE + 4*0xF4) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_PRESET_C0 (PET_PMA3_BROADCAST_BASE + 4*0xF5) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_PRESET_CN1 (PET_PMA3_BROADCAST_BASE + 4*0xF6) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_PRESET_CP1 (PET_PMA3_BROADCAST_BASE + 4*0xF7) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_SUCC_MASK (PET_PMA3_BROADCAST_BASE + 4*0xF8) //Attributes : RW +#define PET_PMA3_BROADCAST_PMA_COM_SCRATCH (PET_PMA3_BROADCAST_BASE + 4*0xff) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY0 (PET_PMA3_BROADCAST_BASE + 4*0x100) //Attributes : RO_EXT_L +#define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY1 (PET_PMA3_BROADCAST_BASE + 4*0x101) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY2 (PET_PMA3_BROADCAST_BASE + 4*0x102) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY3 (PET_PMA3_BROADCAST_BASE + 4*0x103) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY4 (PET_PMA3_BROADCAST_BASE + 4*0x104) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY5 (PET_PMA3_BROADCAST_BASE + 4*0x105) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY6 (PET_PMA3_BROADCAST_BASE + 4*0x106) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY7 (PET_PMA3_BROADCAST_BASE + 4*0x107) //Attributes : RO_EXT_H +#define PET_PMA3_BROADCAST_EQ_TX_FSM_HISTORY_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x108) //Attributes : RW +#define PET_PMA3_BROADCAST_EQ_RX_FSM_HISTORY0 (PET_PMA3_BROADCAST_BASE + 4*0x109) //Attributes : RO_EXT_L +#define PET_PMA3_BROADCAST_EQ_RX_FSM_HISTORY1 (PET_PMA3_BROADCAST_BASE + 4*0x10A) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_EQ_RX_FSM_HISTORY2 (PET_PMA3_BROADCAST_BASE + 4*0x10B) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_EQ_RX_FSM_HISTORY3 (PET_PMA3_BROADCAST_BASE + 4*0x10C) //Attributes : RO_EXT_H +#define PET_PMA3_BROADCAST_EQ_RX_FSM_HISTORY_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x10D) //Attributes : RW +#define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY0 (PET_PMA3_BROADCAST_BASE + 4*0x110) //Attributes : RO_EXT_L +#define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY1 (PET_PMA3_BROADCAST_BASE + 4*0x111) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY2 (PET_PMA3_BROADCAST_BASE + 4*0x112) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY3 (PET_PMA3_BROADCAST_BASE + 4*0x113) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY4 (PET_PMA3_BROADCAST_BASE + 4*0x114) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY5 (PET_PMA3_BROADCAST_BASE + 4*0x115) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY6 (PET_PMA3_BROADCAST_BASE + 4*0x116) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY7 (PET_PMA3_BROADCAST_BASE + 4*0x117) //Attributes : RO_EXT_H +#define PET_PMA3_BROADCAST_TX_EQ_MAIN_HISTORY_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x118) //Attributes : RW +#define PET_PMA3_BROADCAST_RX_TXMAIN_DIR_HISTORY0 (PET_PMA3_BROADCAST_BASE + 4*0x119) //Attributes : RO_EXT_L +#define PET_PMA3_BROADCAST_RX_TXMAIN_DIR_HISTORY1 (PET_PMA3_BROADCAST_BASE + 4*0x11A) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_RX_TXMAIN_DIR_HISTORY2 (PET_PMA3_BROADCAST_BASE + 4*0x11B) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_RX_TXMAIN_DIR_HISTORY3 (PET_PMA3_BROADCAST_BASE + 4*0x11C) //Attributes : RO_EXT_H +#define PET_PMA3_BROADCAST_RX_TXMAIN_DIR_HISTORY_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x11D) //Attributes : RW +#define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY0 (PET_PMA3_BROADCAST_BASE + 4*0x120) //Attributes : RO_EXT_L +#define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY1 (PET_PMA3_BROADCAST_BASE + 4*0x121) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY2 (PET_PMA3_BROADCAST_BASE + 4*0x122) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY3 (PET_PMA3_BROADCAST_BASE + 4*0x123) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY4 (PET_PMA3_BROADCAST_BASE + 4*0x124) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY5 (PET_PMA3_BROADCAST_BASE + 4*0x125) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY6 (PET_PMA3_BROADCAST_BASE + 4*0x126) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY7 (PET_PMA3_BROADCAST_BASE + 4*0x127) //Attributes : RO_EXT_H +#define PET_PMA3_BROADCAST_TX_EQ_POST_HISTORY_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x128) //Attributes : RW +#define PET_PMA3_BROADCAST_RX_TXPOST_DIR_HISTORY0 (PET_PMA3_BROADCAST_BASE + 4*0x129) //Attributes : RO_EXT_L +#define PET_PMA3_BROADCAST_RX_TXPOST_DIR_HISTORY1 (PET_PMA3_BROADCAST_BASE + 4*0x12A) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_RX_TXPOST_DIR_HISTORY2 (PET_PMA3_BROADCAST_BASE + 4*0x12B) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_RX_TXPOST_DIR_HISTORY3 (PET_PMA3_BROADCAST_BASE + 4*0x12C) //Attributes : RO_EXT_H +#define PET_PMA3_BROADCAST_RX_TXPOST_DIR_HISTORY_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x12D) //Attributes : RW +#define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY0 (PET_PMA3_BROADCAST_BASE + 4*0x130) //Attributes : RO_EXT_L +#define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY1 (PET_PMA3_BROADCAST_BASE + 4*0x131) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY2 (PET_PMA3_BROADCAST_BASE + 4*0x132) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY3 (PET_PMA3_BROADCAST_BASE + 4*0x133) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY4 (PET_PMA3_BROADCAST_BASE + 4*0x134) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY5 (PET_PMA3_BROADCAST_BASE + 4*0x135) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY6 (PET_PMA3_BROADCAST_BASE + 4*0x136) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY7 (PET_PMA3_BROADCAST_BASE + 4*0x137) //Attributes : RO_EXT_H +#define PET_PMA3_BROADCAST_TX_EQ_PRE_HISTORY_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x138) //Attributes : RW +#define PET_PMA3_BROADCAST_RX_TXPRE_DIR_HISTORY0 (PET_PMA3_BROADCAST_BASE + 4*0x139) //Attributes : RO_EXT_L +#define PET_PMA3_BROADCAST_RX_TXPRE_DIR_HISTORY1 (PET_PMA3_BROADCAST_BASE + 4*0x13A) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_RX_TXPRE_DIR_HISTORY2 (PET_PMA3_BROADCAST_BASE + 4*0x13B) //Attributes : RO_EXT +#define PET_PMA3_BROADCAST_RX_TXPRE_DIR_HISTORY3 (PET_PMA3_BROADCAST_BASE + 4*0x13C) //Attributes : RO_EXT_H +#define PET_PMA3_BROADCAST_RX_TXPRE_DIR_HISTORY_CTRL (PET_PMA3_BROADCAST_BASE + 4*0x13D) //Attributes : RW + +//The PMA COMMON Register +#define PET_PMA3_MPLLA_PARAM1 (PET_PMA3_COMMON_BASE + 4*0x00) //Attributes : RW +#define PET_PMA3_MPLLA_PARAM2 (PET_PMA3_COMMON_BASE + 4*0x01) //Attributes : RW +#define PET_PMA3_MPLLA_PARAM3 (PET_PMA3_COMMON_BASE + 4*0x02) //Attributes : RW +#define PET_PMA3_MPLLA_PARAM4 (PET_PMA3_COMMON_BASE + 4*0x03) //Attributes : RW +#define PET_PMA3_MPLLA_PARAM5 (PET_PMA3_COMMON_BASE + 4*0x04) //Attributes : RW +#define PET_PMA3_MPLLA_PARAM6 (PET_PMA3_COMMON_BASE + 4*0x05) //Attributes : RW +#define PET_PMA3_MPLLA_FORCE_EN (PET_PMA3_COMMON_BASE + 4*0x06) //Attributes : RW +#define PET_PMA3_MPLLA_FORCE_ACK (PET_PMA3_COMMON_BASE + 4*0x07) //Attributes : RO +#define PET_PMA3_MPLLB_PARAM1 (PET_PMA3_COMMON_BASE + 4*0x08) //Attributes : RW +#define PET_PMA3_MPLLB_PARAM2 (PET_PMA3_COMMON_BASE + 4*0x09) //Attributes : RW +#define PET_PMA3_MPLLB_PARAM3 (PET_PMA3_COMMON_BASE + 4*0x0A) //Attributes : RW +#define PET_PMA3_MPLLB_PARAM4 (PET_PMA3_COMMON_BASE + 4*0x0B) //Attributes : RW +#define PET_PMA3_MPLLB_PARAM5 (PET_PMA3_COMMON_BASE + 4*0x0C) //Attributes : RW +#define PET_PMA3_MPLLB_PARAM6 (PET_PMA3_COMMON_BASE + 4*0x0D) //Attributes : RW +#define PET_PMA3_MPLLB_FORCE_EN (PET_PMA3_COMMON_BASE + 4*0x0E) //Attributes : RW +#define PET_PMA3_MPLLB_FORCE_ACK (PET_PMA3_COMMON_BASE + 4*0x0F) //Attributes : RO +#define PET_PMA3_SUP_MISC (PET_PMA3_COMMON_BASE + 4*0x16) //Attributes : RW +#define PET_PMA3_MPLLA_FRAC_CTRL1 (PET_PMA3_COMMON_BASE + 4*0x17) //Attributes : RW +#define PET_PMA3_MPLLA_FRAC_CTRL2 (PET_PMA3_COMMON_BASE + 4*0x18) //Attributes : RW +#define PET_PMA3_MPLLA_FRAC_CTRL3 (PET_PMA3_COMMON_BASE + 4*0x19) //Attributes : RW +#define PET_PMA3_MPLLA_FRAC_CTRL4 (PET_PMA3_COMMON_BASE + 4*0x1A) //Attributes : RW +#define PET_PMA3_MPLLA_SSC_CTRL1 (PET_PMA3_COMMON_BASE + 4*0x1B) //Attributes : RW +#define PET_PMA3_MPLLA_SSC_CTRL2 (PET_PMA3_COMMON_BASE + 4*0x1C) //Attributes : RW_EXT_L +#define PET_PMA3_MPLLA_SSC_CTRL3 (PET_PMA3_COMMON_BASE + 4*0x1D) //Attributes : RW_EXT_H +#define PET_PMA3_MPLLA_SSC_CTRL4 (PET_PMA3_COMMON_BASE + 4*0x1E) //Attributes : RW +#define PET_PMA3_MPLLA_SSC_CTRL5 (PET_PMA3_COMMON_BASE + 4*0x1F) //Attributes : RW_EXT_L +#define PET_PMA3_MPLLA_SSC_CTRL6 (PET_PMA3_COMMON_BASE + 4*0x20) //Attributes : RW_EXT_H +#define PET_PMA3_MPLLB_FRAC_CTRL1 (PET_PMA3_COMMON_BASE + 4*0x21) //Attributes : RW +#define PET_PMA3_MPLLB_FRAC_CTRL2 (PET_PMA3_COMMON_BASE + 4*0x22) //Attributes : RW +#define PET_PMA3_MPLLB_FRAC_CTRL3 (PET_PMA3_COMMON_BASE + 4*0x23) //Attributes : RW +#define PET_PMA3_MPLLB_FRAC_CTRL4 (PET_PMA3_COMMON_BASE + 4*0x24) //Attributes : RW +#define PET_PMA3_MPLLB_SSC_CTRL1 (PET_PMA3_COMMON_BASE + 4*0x25) //Attributes : RW +#define PET_PMA3_MPLLB_SSC_CTRL2 (PET_PMA3_COMMON_BASE + 4*0x26) //Attributes : RW_EXT_L +#define PET_PMA3_MPLLB_SSC_CTRL3 (PET_PMA3_COMMON_BASE + 4*0x27) //Attributes : RW_EXT_H +#define PET_PMA3_MPLLB_SSC_CTRL4 (PET_PMA3_COMMON_BASE + 4*0x28) //Attributes : RW +#define PET_PMA3_MPLLB_SSC_CTRL5 (PET_PMA3_COMMON_BASE + 4*0x29) //Attributes : RW_EXT_L +#define PET_PMA3_MPLLB_SSC_CTRL6 (PET_PMA3_COMMON_BASE + 4*0x2A) //Attributes : RW_EXT_H +#define PET_PMA3_MPLLA_RECAL_CTRL (PET_PMA3_COMMON_BASE + 4*0x2B) //Attributes : RW +#define PET_PMA3_MPLLB_RECAL_CTRL (PET_PMA3_COMMON_BASE + 4*0x2C) //Attributes : RW +#define PET_PMA3_MPLL_CTRL_MUX (PET_PMA3_COMMON_BASE + 4*0x2D) //Attributes : RW +#define PET_PMA3_POWER_SUPPLY_SEL (PET_PMA3_COMMON_BASE + 4*0x30) //Attributes : RW +#define PET_PMA3_PHY_RESET (PET_PMA3_COMMON_BASE + 4*0x31) //Attributes : RW +#define PET_PMA3_REF_CLK_CTRL (PET_PMA3_COMMON_BASE + 4*0x40) //Attributes : RW +#define PET_PMA3_REFA_CLK_CTRL1 (PET_PMA3_COMMON_BASE + 4*0x41) //Attributes : RW +#define PET_PMA3_REFA_CLK_CTRL2 (PET_PMA3_COMMON_BASE + 4*0x42) //Attributes : RW +#define PET_PMA3_REFA_CLK_STATUS (PET_PMA3_COMMON_BASE + 4*0x43) //Attributes : RO +#define PET_PMA3_REFB_CLK_CTRL1 (PET_PMA3_COMMON_BASE + 4*0x44) //Attributes : RW +#define PET_PMA3_REFB_CLK_CTRL2 (PET_PMA3_COMMON_BASE + 4*0x45) //Attributes : RW +#define PET_PMA3_REFB_CLK_STATUS (PET_PMA3_COMMON_BASE + 4*0x46) //Attributes : RO +#define PET_PMA3_REF_CLK_MUX (PET_PMA3_COMMON_BASE + 4*0x47) //Attributes : RW +#define PET_PMA3_RES_ACK_IN (PET_PMA3_COMMON_BASE + 4*0x50) //Attributes : RW +#define PET_PMA3_RES_ACK_OUT (PET_PMA3_COMMON_BASE + 4*0x51) //Attributes : RO +#define PET_PMA3_RES_REQ_IN (PET_PMA3_COMMON_BASE + 4*0x52) //Attributes : RW +#define PET_PMA3_RES_REQ_OUT (PET_PMA3_COMMON_BASE + 4*0x53) //Attributes : RO +#define PET_PMA3_RTUNE_REQ (PET_PMA3_COMMON_BASE + 4*0x54) //Attributes : RW +#define PET_PMA3_RTUNE_ACK (PET_PMA3_COMMON_BASE + 4*0x55) //Attributes : RO +#define PET_PMA3_RTUNE_CTRL1 (PET_PMA3_COMMON_BASE + 4*0x56) //Attributes : RW +#define PET_PMA3_RTUNE_CTRL2 (PET_PMA3_COMMON_BASE + 4*0x57) //Attributes : RW +#define PET_PMA3_RTUNE_CTRL3 (PET_PMA3_COMMON_BASE + 4*0x58) //Attributes : RW +#define PET_PMA3_RX_BIAS_CURRENT_CTRL (PET_PMA3_COMMON_BASE + 4*0x59) //Attributes : RW +#define PET_PMA3_CR_PARA_SEL (PET_PMA3_COMMON_BASE + 4*0x90) //Attributes : RW +#define PET_PMA3_POWER_GATING_SIGNAL1 (PET_PMA3_COMMON_BASE + 4*0x60) //Attributes : RW +#define PET_PMA3_POWER_GATING_SIGNAL2 (PET_PMA3_COMMON_BASE + 4*0x61) //Attributes : RO +#define PET_PMA3_POWER_GATING_SIGNAL3 (PET_PMA3_COMMON_BASE + 4*0x62) //Attributes : RW +#define PET_PMA3_SRAM_CTRL (PET_PMA3_COMMON_BASE + 4*0x68) //Attributes : RW +#define PET_PMA3_SRAM_STATUS (PET_PMA3_COMMON_BASE + 4*0x69) //Attributes : RO +#define PET_PMA3_SRIO_RST_REQ (PET_PMA3_COMMON_BASE + 4*0x6A) //Attributes : RO +#define PET_PMA3_SRIO_GEN3_EN (PET_PMA3_COMMON_BASE + 4*0x6C) //Attributes : RW +#define PET_PMA3_SRIO_RATE_OUT (PET_PMA3_COMMON_BASE + 4*0x6D) //Attributes : RW +#define PET_PMA3_CPRI_RST_REQ (PET_PMA3_COMMON_BASE + 4*0x70) //Attributes : RW +#define PET_PMA3_CPRI_RX_LOS (PET_PMA3_COMMON_BASE + 4*0x71) //Attributes : RW +#define PET_PMA3_CPRI_SIGNAL_OK (PET_PMA3_COMMON_BASE + 4*0x72) //Attributes : RW +#define PET_PMA3_CPRI_ENERGY_DET (PET_PMA3_COMMON_BASE + 4*0x73) //Attributes : RW +#define PET_PMA3_CPRI_SIGDET (PET_PMA3_COMMON_BASE + 4*0x74) //Attributes : RW +#define PET_PMA3_CPRI_PCS_STATUS (PET_PMA3_COMMON_BASE + 4*0x75) //Attributes : RO +#define PET_PMA3_CPRI_PCS_STATUS_CTRL (PET_PMA3_COMMON_BASE + 4*0x76) //Attributes : RW +#define PET_PMA3_ETH_ENERGY_DET (PET_PMA3_COMMON_BASE + 4*0x80) //Attributes : RW +#define PET_PMA3_ETH_SPEED_CTRL (PET_PMA3_COMMON_BASE + 4*0x81) //Attributes : RO +#define PET_PMA3_TX_CLK_SEL (PET_PMA3_COMMON_BASE + 4*0xF0) //Attributes : RW +#define PET_PMA3_RPCS_TX_CLK_SEL (PET_PMA3_COMMON_BASE + 4*0xF1) //Attributes : RW +#define PET_PMA3_RPCS_RX_CLK_SEL (PET_PMA3_COMMON_BASE + 4*0xF2) //Attributes : RW +#define PET_PMA3_PMA_COM_SCRATCH (PET_PMA3_COMMON_BASE + 4*0xff) //Attributes : RW + +//The PMA PCS Register +#define PET_PMA3_PCS_SOFT_RESET (PET_PMA3_PCS_BASE + 4*0x00) //Attributes : RW +#define PET_PMA3_PCS_LOOPBACK_CTRL (PET_PMA3_PCS_BASE + 4*0x04) //Attributes : RW +#define PET_PMA3_PCS_PRBS_UDP_SEND (PET_PMA3_PCS_BASE + 4*0x05) //Attributes : RW +#define PET_PMA3_PCS_PRBS_SEND_ERRINS (PET_PMA3_PCS_BASE + 4*0x06) //Attributes : RW +#define PET_PMA3_PCS_TXUDP_0 (PET_PMA3_PCS_BASE + 4*0x07) //Attributes : RW_EXT_L +#define PET_PMA3_PCS_TXUDP_1 (PET_PMA3_PCS_BASE + 4*0x08) //Attributes : RW_EXT +#define PET_PMA3_PCS_TXUDP_2 (PET_PMA3_PCS_BASE + 4*0x09) //Attributes : RW_EXT +#define PET_PMA3_PCS_TXUDP_3 (PET_PMA3_PCS_BASE + 4*0x0A) //Attributes : RW_EXT +#define PET_PMA3_PCS_TXUDP_4 (PET_PMA3_PCS_BASE + 4*0x0B) //Attributes : RW_EXT_H +#define PET_PMA3_PCS_PRBS_UDP_CHK (PET_PMA3_PCS_BASE + 4*0x10) //Attributes : RW +#define PET_PMA3_PCS_RXUDP_0 (PET_PMA3_PCS_BASE + 4*0x11) //Attributes : RW_EXT_L +#define PET_PMA3_PCS_RXUDP_1 (PET_PMA3_PCS_BASE + 4*0x12) //Attributes : RW_EXT +#define PET_PMA3_PCS_RXUDP_2 (PET_PMA3_PCS_BASE + 4*0x13) //Attributes : RW_EXT +#define PET_PMA3_PCS_RXUDP_3 (PET_PMA3_PCS_BASE + 4*0x14) //Attributes : RW_EXT +#define PET_PMA3_PCS_RXUDP_4 (PET_PMA3_PCS_BASE + 4*0x15) //Attributes : RW_EXT_H +#define PET_PMA3_PCS_RXPRBS_ERRCNT_L0 (PET_PMA3_PCS_BASE + 4*0x16) //Attributes : RO +#define PET_PMA3_PCS_RXPRBS_ERRCNT_L1 (PET_PMA3_PCS_BASE + 4*0x17) //Attributes : RO +#define PET_PMA3_PCS_RXPRBS_ERRCNT_L2 (PET_PMA3_PCS_BASE + 4*0x18) //Attributes : RO +#define PET_PMA3_PCS_RXPRBS_ERRCNT_L3 (PET_PMA3_PCS_BASE + 4*0x19) //Attributes : RO +#define PET_PMA3_PCS_NELP_FIFO_STATUS (PET_PMA3_PCS_BASE + 4*0x20) //Attributes : RO +#define PET_PMA3_PCS_FELP_FIFO_STATUS (PET_PMA3_PCS_BASE + 4*0x21) //Attributes : RO +#define PET_PMA3_PCS_BIT_REV_CTRL (PET_PMA3_PCS_BASE + 4*0x22) //Attributes : RW +#define PET_PMA3_PCS_SOFT_PON_RST (PET_PMA3_PCS_BASE + 4*0xfe) //Attributes : RW +#define PET_PMA3_PCS_PCS_SCRATCH (PET_PMA3_PCS_BASE + 4*0xff) //Attributes : RW + +#endif diff --git a/driver/rfic/ucp/base/inc/ucp_reg_io.h b/driver/rfic/ucp/base/inc/ucp_reg_io.h new file mode 100644 index 0000000..57f9172 --- /dev/null +++ b/driver/rfic/ucp/base/inc/ucp_reg_io.h @@ -0,0 +1,39 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_reg_io.h +// Author : boheng.lin@smartlogictech.com +// Date First Issued : 2022-09-08 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#ifndef __UCP_REG_IO__ +#define __UCP_REG_IO__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern int ucp_reg_init (void); +extern void ucp_reg32_or_write(uint64_t reg, uint32_t mask); +extern void ucp_reg32_and_write(uint64_t reg, uint32_t mask); +extern uint32_t ucp_reg32_and_read(uint64_t reg, uint32_t mask); +extern void ucp_reg16_write(uint64_t reg, uint16_t data); +extern uint16_t ucp_reg16_read(uint64_t reg); +extern void ucp_reg32_write(uint64_t reg, uint32_t data); +extern uint32_t ucp_reg32_read(uint64_t reg); + +extern void ucp_reg_test(void); + +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/driver/rfic/ucp/base/inc/ucp_rfc.h b/driver/rfic/ucp/base/inc/ucp_rfc.h new file mode 100644 index 0000000..dfb6d66 --- /dev/null +++ b/driver/rfic/ucp/base/inc/ucp_rfc.h @@ -0,0 +1,240 @@ +#ifndef __UCP_RFC_H__ +#define __UCP_RFC_H__ + + +#define RF_BASE_ADDR 0x04da0000 +/*----------------------------------------------------- + RF0_REG +-------------------------------------------------------*/ +#define RF_MODE_REG ( RF_BASE_ADDR + 0x00*4 ) +#define IO_CTRL_REG ( RF_BASE_ADDR + 0x01*4 ) +#define CG_CTRL_REG ( RF_BASE_ADDR + 0x02*4 ) +#define ADC_STATUS_REG ( RF_BASE_ADDR + 0x04*4 ) +#define ADC_CTRL_REG ( RF_BASE_ADDR + 0x05*4 ) +#define ADC_DFMT_REG ( RF_BASE_ADDR + 0x06*4 ) +#define ADC_EOF_REG ( RF_BASE_ADDR + 0x07*4 ) +#define DP_PN_CG_REG ( RF_BASE_ADDR + 0x08*4 ) +#define DAC_CTRL_REG ( RF_BASE_ADDR + 0x09*4 ) +#define DAC_DIV_REG ( RF_BASE_ADDR + 0x0A*4 ) +#define DAC_PAT1_REG ( RF_BASE_ADDR + 0x0B*4 ) +#define DAC_PAT2_REG ( RF_BASE_ADDR + 0x0C*4 ) +#define DAC_EOF_REG ( RF_BASE_ADDR + 0x0D*4 ) +#define DP_BIAS_REG ( RF_BASE_ADDR + 0x10*4 ) +#define DP_RTERM0_REG ( RF_BASE_ADDR + 0x11*4 ) +#define DP_RTERM1_REG ( RF_BASE_ADDR + 0x12*4 ) +#define CK_RTERM_REG ( RF_BASE_ADDR + 0x13*4 ) +#define LVDS_EN_REG ( RF_BASE_ADDR + 0x14*4 ) +#define LVDS_CM_REG ( RF_BASE_ADDR + 0x15*4 ) +#define LVDS_TXDRV_REG ( RF_BASE_ADDR + 0x16*4 ) +#define CMOS_IE_REG ( RF_BASE_ADDR + 0x17*4 ) +#define CMOS_OE_REG ( RF_BASE_ADDR + 0x18*4 ) +#define CMOS_PULL_REG ( RF_BASE_ADDR + 0x19*4 ) +#define CMOS_SMT_REG ( RF_BASE_ADDR + 0x1A*4 ) +#define CK_TUNING_REG ( RF_BASE_ADDR + 0x1B*4 ) +#define FRM_TUNING_REG ( RF_BASE_ADDR + 0x1C*4 ) +#define CMOS_TUNING0_REG ( RF_BASE_ADDR + 0x1D*4 ) +#define CMOS_TUNING1_REG ( RF_BASE_ADDR + 0x1E*4 ) +#define CMOS_TUNING2_REG ( RF_BASE_ADDR + 0x1F*4 ) +#define CMOS_TUNING3_REG ( RF_BASE_ADDR + 0x20*4 ) +#define CMOS_TUNING4_REG ( RF_BASE_ADDR + 0x21*4 ) +#define CMOS_TUNING5_REG ( RF_BASE_ADDR + 0x22*4 ) +#define LVDS_TUNING0_REG ( RF_BASE_ADDR + 0x23*4 ) +#define LVDS_TUNING1_REG ( RF_BASE_ADDR + 0x24*4 ) +#define LVDS_PMUX0_REG ( RF_BASE_ADDR + 0x25*4 ) +#define LVDS_PMUX1_REG ( RF_BASE_ADDR + 0x26*4 ) + +/*----------------------------------------------------- + RF common reg +-------------------------------------------------------*/ +#define PIN_CTRL_REG ( RF_BASE_ADDR + 0x5B*4 ) +#define TMR_CTRL_REG ( RF_BASE_ADDR + 0x60*4 ) +#define RF_INTC_REG ( RF_BASE_ADDR + 0x61*4 ) +#define TMR_SCR_REQ_REG ( RF_BASE_ADDR + 0x62*4 ) +/*----------------------------------------------------- + timer0 reg +-------------------------------------------------------*/ +#define TMR_TEVENT_REG ( RF_BASE_ADDR + 0x80*4 ) +#define TMR_TSCR_TRG_REG ( RF_BASE_ADDR + 0x81*4 ) +#define TMR_TWREQ_REG ( RF_BASE_ADDR + 0x82*4 ) +#define TMR_TINTE0_REG ( RF_BASE_ADDR + 0x83*4 ) +#define TMR_TINTF0_REG ( RF_BASE_ADDR + 0x84*4 ) +#define TMR_TINTE1_REG ( RF_BASE_ADDR + 0x85*4 ) +#define TMR_TINTF1_REG ( RF_BASE_ADDR + 0x86*4 ) +#define TMR_TINTE2_REG ( RF_BASE_ADDR + 0x87*4 ) +#define TMR_TINTF2_REG ( RF_BASE_ADDR + 0x88*4 ) +#define TMR_CEVENT_REG ( RF_BASE_ADDR + 0x89*4 ) +#define TMR_CMSK_REG ( RF_BASE_ADDR + 0x8A*4 ) +#define TMR_CINTE0_REG ( RF_BASE_ADDR + 0x8B*4 ) +#define TMR_CINTF0_REG ( RF_BASE_ADDR + 0x8C*4 ) +#define TMR_CINTE1_REG ( RF_BASE_ADDR + 0x8D*4 ) +#define TMR_CINTF1_REG ( RF_BASE_ADDR + 0x8E*4 ) +#define TMR_CINTE2_REG ( RF_BASE_ADDR + 0x8F*4 ) +#define TMR_CINTF2_REG ( RF_BASE_ADDR + 0x90*4 ) +#define TMR_OVFL_REG ( RF_BASE_ADDR + 0x91*4 ) +#define TMR_OVFH_REG ( RF_BASE_ADDR + 0x92*4 ) +#define TMR_RXDP_EN0L_REG ( RF_BASE_ADDR + 0x93*4 ) +#define TMR_RXDP_EN0H_REG ( RF_BASE_ADDR + 0x94*4 ) +#define TMR_RXDP_EN1L_REG ( RF_BASE_ADDR + 0x95*4 ) +#define TMR_RXDP_EN1H_REG ( RF_BASE_ADDR + 0x96*4 ) +#define TMR_TXDP_EN0L_REG ( RF_BASE_ADDR + 0x97*4 ) +#define TMR_TXDP_EN0H_REG ( RF_BASE_ADDR + 0x98*4 ) +#define TMR_TXDP_EN1L_REG ( RF_BASE_ADDR + 0x99*4 ) +#define TMR_TXDP_EN1H_REG ( RF_BASE_ADDR + 0x9A*4 ) +#define TMR_RXEOFL_REG ( RF_BASE_ADDR + 0x9B*4 ) +#define TMR_RXEOFH_REG ( RF_BASE_ADDR + 0x9C*4 ) +#define TMR_TXEOFL_REG ( RF_BASE_ADDR + 0x9D*4 ) +#define TMR_TXEOFH_REG ( RF_BASE_ADDR + 0x9E*4 ) +#define TMR_EN_CTRL0L_REG ( RF_BASE_ADDR + 0x9F*4 ) +#define TMR_EN_CTRL0H_REG ( RF_BASE_ADDR + 0xA0*4 ) +#define TMR_EN_CTRL1L_REG ( RF_BASE_ADDR + 0xA1*4 ) +#define TMR_EN_CTRL1H_REG ( RF_BASE_ADDR + 0xA2*4 ) +#define TMR_EN_CTRL2L_REG ( RF_BASE_ADDR + 0xA3*4 ) +#define TMR_EN_CTRL2H_REG ( RF_BASE_ADDR + 0xA4*4 ) +#define TMR_EN_CTRL3L_REG ( RF_BASE_ADDR + 0xA5*4 ) +#define TMR_EN_CTRL3H_REG ( RF_BASE_ADDR + 0xA6*4 ) +#define TMR_TXRX_CTRL0L_REG ( RF_BASE_ADDR + 0xA7*4 ) +#define TMR_TXRX_CTRL0H_REG ( RF_BASE_ADDR + 0xA8*4 ) +#define TMR_TXRX_CTRL1L_REG ( RF_BASE_ADDR + 0xA9*4 ) +#define TMR_TXRX_CTRL1H_REG ( RF_BASE_ADDR + 0xAA*4 ) +#define TMR_SCRATH0L_REG ( RF_BASE_ADDR + 0xAB*4 ) +#define TMR_SCRATH0H_REG ( RF_BASE_ADDR + 0xAC*4 ) +#define TMR_SCRATH1L_REG ( RF_BASE_ADDR + 0xAD*4 ) +#define TMR_SCRATH1H_REG ( RF_BASE_ADDR + 0xAE*4 ) +#define TMR_1PPSL_REG ( RF_BASE_ADDR + 0xAF*4 ) +#define TMR_1PPSH_REG ( RF_BASE_ADDR + 0xB0*4 ) + +/*----------------------------------------------------- + timer array +-------------------------------------------------------*/ +#define TMR0_ARRAY_BASE RF_BASE_ADDR+0x400 + +#define TMR_TNL_REG0 ( TMR0_ARRAY_BASE + 0x00*4 ) +#define TMR_TNH_REG0 ( TMR0_ARRAY_BASE + 0x01*4 ) +#define TMR_TNL_REG1 ( TMR0_ARRAY_BASE + 0x02*4 ) +#define TMR_TNH_REG1 ( TMR0_ARRAY_BASE + 0x03*4 ) +#define TMR_TNL_REG2 ( TMR0_ARRAY_BASE + 0x04*4 ) +#define TMR_TNH_REG2 ( TMR0_ARRAY_BASE + 0x05*4 ) +#define TMR_TNL_REG3 ( TMR0_ARRAY_BASE + 0x06*4 ) +#define TMR_TNH_REG3 ( TMR0_ARRAY_BASE + 0x07*4 ) +#define TMR_TNL_REG4 ( TMR0_ARRAY_BASE + 0x08*4 ) +#define TMR_TNH_REG4 ( TMR0_ARRAY_BASE + 0x09*4 ) +#define TMR_TNL_REG5 ( TMR0_ARRAY_BASE + 0x0A*4 ) +#define TMR_TNH_REG5 ( TMR0_ARRAY_BASE + 0x0B*4 ) +#define TMR_TNL_REG6 ( TMR0_ARRAY_BASE + 0x0C*4 ) +#define TMR_TNH_REG6 ( TMR0_ARRAY_BASE + 0x0D*4 ) +#define TMR_TNL_REG7 ( TMR0_ARRAY_BASE + 0x0E*4 ) +#define TMR_TNH_REG7 ( TMR0_ARRAY_BASE + 0x0F*4 ) +#define TMR_TNL_REG8 ( TMR0_ARRAY_BASE + 0x10*4 ) +#define TMR_TNH_REG8 ( TMR0_ARRAY_BASE + 0x11*4 ) +#define TMR_TNL_REG9 ( TMR0_ARRAY_BASE + 0x12*4 ) +#define TMR_TNH_REG9 ( TMR0_ARRAY_BASE + 0x13*4 ) +#define TMR_TNL_REG10 ( TMR0_ARRAY_BASE + 0x14*4 ) +#define TMR_TNH_REG10 ( TMR0_ARRAY_BASE + 0x15*4 ) +#define TMR_TNL_REG11 ( TMR0_ARRAY_BASE + 0x16*4 ) +#define TMR_TNH_REG11 ( TMR0_ARRAY_BASE + 0x17*4 ) +#define TMR_TNL_REG12 ( TMR0_ARRAY_BASE + 0x18*4 ) +#define TMR_TNH_REG12 ( TMR0_ARRAY_BASE + 0x19*4 ) +#define TMR_TNL_REG13 ( TMR0_ARRAY_BASE + 0x1A*4 ) +#define TMR_TNH_REG13 ( TMR0_ARRAY_BASE + 0x1B*4 ) +#define TMR_TNL_REG14 ( TMR0_ARRAY_BASE + 0x1C*4 ) +#define TMR_TNH_REG14 ( TMR0_ARRAY_BASE + 0x1D*4 ) +#define TMR_TNL_REG15 ( TMR0_ARRAY_BASE + 0x1E*4 ) +#define TMR_TNH_REG15 ( TMR0_ARRAY_BASE + 0x1F*4 ) +#define TMR_TNL_REG16 ( TMR0_ARRAY_BASE + 0x20*4 ) +#define TMR_TNH_REG16 ( TMR0_ARRAY_BASE + 0x21*4 ) +#define TMR_TNL_REG17 ( TMR0_ARRAY_BASE + 0x22*4 ) +#define TMR_TNH_REG17 ( TMR0_ARRAY_BASE + 0x23*4 ) +#define TMR_TNL_REG18 ( TMR0_ARRAY_BASE + 0x24*4 ) +#define TMR_TNH_REG18 ( TMR0_ARRAY_BASE + 0x25*4 ) +#define TMR_TNL_REG19 ( TMR0_ARRAY_BASE + 0x26*4 ) +#define TMR_TNH_REG19 ( TMR0_ARRAY_BASE + 0x27*4 ) +#define TMR_TNL_REG20 ( TMR0_ARRAY_BASE + 0x28*4 ) +#define TMR_TNH_REG20 ( TMR0_ARRAY_BASE + 0x29*4 ) +#define TMR_TNL_REG21 ( TMR0_ARRAY_BASE + 0x2A*4 ) +#define TMR_TNH_REG21 ( TMR0_ARRAY_BASE + 0x2B*4 ) +#define TMR_TNL_REG22 ( TMR0_ARRAY_BASE + 0x2C*4 ) +#define TMR_TNH_REG22 ( TMR0_ARRAY_BASE + 0x2D*4 ) +#define TMR_TNL_REG23 ( TMR0_ARRAY_BASE + 0x2E*4 ) +#define TMR_TNH_REG23 ( TMR0_ARRAY_BASE + 0x2F*4 ) +#define TMR_TNL_REG24 ( TMR0_ARRAY_BASE + 0x30*4 ) +#define TMR_TNH_REG24 ( TMR0_ARRAY_BASE + 0x31*4 ) +#define TMR_TNL_REG25 ( TMR0_ARRAY_BASE + 0x32*4 ) +#define TMR_TNH_REG25 ( TMR0_ARRAY_BASE + 0x33*4 ) +#define TMR_TNL_REG26 ( TMR0_ARRAY_BASE + 0x34*4 ) +#define TMR_TNH_REG26 ( TMR0_ARRAY_BASE + 0x35*4 ) +#define TMR_TNL_REG27 ( TMR0_ARRAY_BASE + 0x36*4 ) +#define TMR_TNH_REG27 ( TMR0_ARRAY_BASE + 0x37*4 ) +#define TMR_TNL_REG28 ( TMR0_ARRAY_BASE + 0x38*4 ) +#define TMR_TNH_REG28 ( TMR0_ARRAY_BASE + 0x39*4 ) +#define TMR_TNL_REG29 ( TMR0_ARRAY_BASE + 0x3A*4 ) +#define TMR_TNH_REG29 ( TMR0_ARRAY_BASE + 0x3B*4 ) +#define TMR_TNL_REG30 ( TMR0_ARRAY_BASE + 0x3C*4 ) +#define TMR_TNH_REG30 ( TMR0_ARRAY_BASE + 0x3D*4 ) +#define TMR_TNL_REG31 ( TMR0_ARRAY_BASE + 0x3E*4 ) +#define TMR_TNH_REG31 ( TMR0_ARRAY_BASE + 0x3F*4 ) + +#define GPIO_PIN_BASE RF_BASE_ADDR+0x800 + +#define GPIO_PMUX0_REG ( GPIO_PIN_BASE + 0x00*4 ) +#define GPIO_CTRL0_REG ( GPIO_PIN_BASE + 0x01*4 ) + +/*----------------------------------------------------- + RF_REG MASK +-------------------------------------------------------*/ +/////RF_REG_mask///// +#define RF_MODE_REG_MASK 0x800003FF +#define IO_CTRL_REG_MASK 0x00000003 +#define ADC_STATUS_REG_MASK 0x00000F0F +#define ADC_CTRL_REG_MASK 0x3300010F +#define ADC_DFMT_REG_MASK 0x00000FFF +#define DAC_STATUS_REG_MASK 0xFF000000 +#define ADC_EOF_REG_MASK 0xC0000000 +#define DAC_CTRL_REG_MASK 0x0000030B +#define DAC_DIV_REG_MASK 0x0000FFFF +#define DAC_PAT1_REG_MASK 0xFFFFFFFF +#define DAC_PAT2_REG_MASK 0xFFFFFFFF +#define DAC_EOF_REG_MASK 0xC0000000 +#define DP_BIAS_REG_MASK 0xFFFFFFFF +#define DP_RTERM0_REG_MASK 0x3F777777 +#define DP_RTERM1_REG_MASK 0x3F777777 +#define CK_RTERM_REG_MASK 0x0000FFFF +#define LVDS_EN_REG_MASK 0x00FF00FF +//#define DEBUG_LVDS_REG_MASK 0x003F003F +#define LVDS_CM_REG_MASK 0xFFFFFFFF +#define LVDS_TXDRV_REG_MASK 0xFFFFFFFF +#define CMOS_IE_REG_MASK 0xCFFF0FFF +#define CMOS_OE_REG_MASK 0xCFFF0FFF +#define CMOS_PULL_REG_MASK 0xF03F003F +#define CMOS_SMT_REG_MASK 0xF03F003F +#define CK_TUNING_REG_MASK 0x00000F0F +#define FRM_TUNING_REG_MASK 0x000000FF +#define CMOS_TUNING0_REG_MASK 0xFFFFFFFF +#define CMOS_TUNING1_REG_MASK 0xFFFFFFFF +#define CMOS_TUNING2_REG_MASK 0xFFFFFFFF +#define CMOS_TUNING3_REG_MASK 0xFFFFFFFF +#define CMOS_TUNING4_REG_MASK 0xFFFFFFFF +#define CMOS_TUNING5_REG_MASK 0xFFFFFFFF +#define LVDS_TUNING0_REG_MASK 0x00FFFFFF +#define LVDS_TUNING1_REG_MASK 0x00FFFFFF +#define LVDS_PMUX0_REG_MASK 0xFFFFFFFF +#define LVDS_PMUX1_REG_MASK 0xFFFFFFFF + +#define PIN_CTRL_REG_MASK 0xC0007F7F //!!!0xC0003F3F +#define SYNC_GEN_REG_MASK 0x00000001 +#define SYNC_CTRL_REG_MASK 0x0000000F +#define TMR_CTRL_REG_MASK 0x8000C303 +#define RF_INTC_REG_MASK 0x00030000 +#define TMR_SCR_REQ_REG_MASK 0x00000000 + +/////timer_reg_mask +#define TMR_MASK 0x00000000 +#define TMR_UNMASK 0xFFFFFFFF +#define TMR_TSCR_TRG_MASK 0xFF000000 +#define TMR_CEVENT_MASK 0x0000007F +#define TMR_CMSK_MASK 0x00003333 +#define TMR_CINTE_MASK 0x0000007F +#define TMR_OVFH_MASK 0x3FFFFFFF + +#endif + + diff --git a/driver/rfic/ucp/base/inc/ucp_sfr_c.h b/driver/rfic/ucp/base/inc/ucp_sfr_c.h new file mode 100644 index 0000000..9fb7ed8 --- /dev/null +++ b/driver/rfic/ucp/base/inc/ucp_sfr_c.h @@ -0,0 +1,741 @@ +//******************** (C) COPYRIGHT 2019 SmartLogic******************************* +// FileName : ucp_sfr_c.h +// Author : lijian, jian.li@smartlogictech.com +// Date First Issued : 2019-03-29 04:08:48 PM +// Last Modified : 2022-07-07 09:28:02 PM +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** +#ifndef __UCP_SFR_C_H__ +#define __UCP_SFR_C_H__ +#include +#include "ucp_param.h" +#define DDRC_BASE 0x04570000 +#define DDRSYS_BASE 0x04578000 +#define DDRPHY_BASE 0x0d800000 +//pin mux +#define PIN_MUX_BASE_ADDR 0x04458000 + +#define PAD1_CTRL_REG (PIN_MUX_BASE_ADDR + 0x01*4) +#define PAD2_CTRL_REG (PIN_MUX_BASE_ADDR + 0x02*4) +#define PAD3_CTRL_REG (PIN_MUX_BASE_ADDR + 0x03*4) +#define PAD4_CTRL_REG (PIN_MUX_BASE_ADDR + 0x04*4) +#define PAD5_CTRL_REG (PIN_MUX_BASE_ADDR + 0x05*4) +#define PAD6_CTRL_REG (PIN_MUX_BASE_ADDR + 0x06*4) +#define PAD7_CTRL_REG (PIN_MUX_BASE_ADDR + 0x07*4) +#define PAD8_CTRL_REG (PIN_MUX_BASE_ADDR + 0x08*4) +#define PAD9_CTRL_REG (PIN_MUX_BASE_ADDR + 0x09*4) +#define PAD10_CTRL_REG (PIN_MUX_BASE_ADDR + 0x0a*4) +#define PAD11_CTRL_REG (PIN_MUX_BASE_ADDR + 0x0b*4) +#define PAD12_CTRL_REG (PIN_MUX_BASE_ADDR + 0x0c*4) +#define PAD13_CTRL_REG (PIN_MUX_BASE_ADDR + 0x0d*4) +#define PAD14_CTRL_REG (PIN_MUX_BASE_ADDR + 0x0e*4) +#define PAD15_CTRL_REG (PIN_MUX_BASE_ADDR + 0x0f*4) +#define PAD16_CTRL_REG (PIN_MUX_BASE_ADDR + 0x10*4) +#define PAD17_CTRL_REG (PIN_MUX_BASE_ADDR + 0x11*4) +#define PA0_CTRL_REG (PIN_MUX_BASE_ADDR + 0x12*4) +#define PA1_CTRL_REG (PIN_MUX_BASE_ADDR + 0x13*4) +#define PA2_CTRL_REG (PIN_MUX_BASE_ADDR + 0x14*4) +#define PA3_CTRL_REG (PIN_MUX_BASE_ADDR + 0x15*4) +#define PA4_CTRL_REG (PIN_MUX_BASE_ADDR + 0x16*4) +#define PA5_CTRL_REG (PIN_MUX_BASE_ADDR + 0x17*4) +#define PA6_CTRL_REG (PIN_MUX_BASE_ADDR + 0x18*4) +#define PA7_CTRL_REG (PIN_MUX_BASE_ADDR + 0x19*4) +#define PA8_CTRL_REG (PIN_MUX_BASE_ADDR + 0x1a*4) +#define PA9_CTRL_REG (PIN_MUX_BASE_ADDR + 0x1b*4) +#define PA10_CTRL_REG (PIN_MUX_BASE_ADDR + 0x1c*4) +#define PA11_CTRL_REG (PIN_MUX_BASE_ADDR + 0x1d*4) +#define PA12_CTRL_REG (PIN_MUX_BASE_ADDR + 0x1e*4) +#define PA13_CTRL_REG (PIN_MUX_BASE_ADDR + 0x1f*4) +#define PA14_CTRL_REG (PIN_MUX_BASE_ADDR + 0x20*4) +#define PB0_CTRL_REG (PIN_MUX_BASE_ADDR + 0x21*4) +#define PB1_CTRL_REG (PIN_MUX_BASE_ADDR + 0x22*4) +#define PB2_CTRL_REG (PIN_MUX_BASE_ADDR + 0x23*4) +#define PB3_CTRL_REG (PIN_MUX_BASE_ADDR + 0x24*4) +#define PB4_CTRL_REG (PIN_MUX_BASE_ADDR + 0x25*4) +#define PB5_CTRL_REG (PIN_MUX_BASE_ADDR + 0x26*4) +#define PB6_CTRL_REG (PIN_MUX_BASE_ADDR + 0x27*4) +#define PB7_CTRL_REG (PIN_MUX_BASE_ADDR + 0x28*4) +#define PB8_CTRL_REG (PIN_MUX_BASE_ADDR + 0x29*4) +#define PB9_CTRL_REG (PIN_MUX_BASE_ADDR + 0x2a*4) +#define PB10_CTRL_REG (PIN_MUX_BASE_ADDR + 0x2b*4) +#define PB11_CTRL_REG (PIN_MUX_BASE_ADDR + 0x2c*4) +#define PB12_CTRL_REG (PIN_MUX_BASE_ADDR + 0x2d*4) +#define PB13_CTRL_REG (PIN_MUX_BASE_ADDR + 0x2e*4) +#define PB14_CTRL_REG (PIN_MUX_BASE_ADDR + 0x2f*4) +#define PC0_CTRL_REG (PIN_MUX_BASE_ADDR + 0x30*4) +#define PC1_CTRL_REG (PIN_MUX_BASE_ADDR + 0x31*4) +#define PC2_CTRL_REG (PIN_MUX_BASE_ADDR + 0x32*4) +#define PC3_CTRL_REG (PIN_MUX_BASE_ADDR + 0x33*4) +#define PC4_CTRL_REG (PIN_MUX_BASE_ADDR + 0x34*4) +#define PC5_CTRL_REG (PIN_MUX_BASE_ADDR + 0x35*4) +#define PC6_CTRL_REG (PIN_MUX_BASE_ADDR + 0x36*4) +#define PC7_CTRL_REG (PIN_MUX_BASE_ADDR + 0x37*4) +#define PC8_CTRL_REG (PIN_MUX_BASE_ADDR + 0x38*4) +#define PC9_CTRL_REG (PIN_MUX_BASE_ADDR + 0x39*4) +#define PC10_CTRL_REG (PIN_MUX_BASE_ADDR + 0x3a*4) +#define PC11_CTRL_REG (PIN_MUX_BASE_ADDR + 0x3b*4) +#define PC12_CTRL_REG (PIN_MUX_BASE_ADDR + 0x3c*4) +#define PC13_CTRL_REG (PIN_MUX_BASE_ADDR + 0x3d*4) +#define PC14_CTRL_REG (PIN_MUX_BASE_ADDR + 0x3e*4) +#define PD0_CTRL_REG (PIN_MUX_BASE_ADDR + 0x3f*4) +#define PD1_CTRL_REG (PIN_MUX_BASE_ADDR + 0x40*4) +#define PD2_CTRL_REG (PIN_MUX_BASE_ADDR + 0x41*4) +#define PD3_CTRL_REG (PIN_MUX_BASE_ADDR + 0x42*4) +#define PD4_CTRL_REG (PIN_MUX_BASE_ADDR + 0x43*4) +#define PD5_CTRL_REG (PIN_MUX_BASE_ADDR + 0x44*4) +#define PD6_CTRL_REG (PIN_MUX_BASE_ADDR + 0x45*4) +#define PD7_CTRL_REG (PIN_MUX_BASE_ADDR + 0x46*4) +#define PD8_CTRL_REG (PIN_MUX_BASE_ADDR + 0x47*4) +#define PD9_CTRL_REG (PIN_MUX_BASE_ADDR + 0x48*4) +#define PD10_CTRL_REG (PIN_MUX_BASE_ADDR + 0x49*4) +#define PD11_CTRL_REG (PIN_MUX_BASE_ADDR + 0x4a*4) +#define PD12_CTRL_REG (PIN_MUX_BASE_ADDR + 0x4b*4) +#define PD13_CTRL_REG (PIN_MUX_BASE_ADDR + 0x4c*4) +#define PD14_CTRL_REG (PIN_MUX_BASE_ADDR + 0x4d*4) +#define PD15_CTRL_REG (PIN_MUX_BASE_ADDR + 0x4e*4) +#define PD16_CTRL_REG (PIN_MUX_BASE_ADDR + 0x4f*4) +#define PD17_CTRL_REG (PIN_MUX_BASE_ADDR + 0x50*4) +#define PD18_CTRL_REG (PIN_MUX_BASE_ADDR + 0x51*4) +#define PD19_CTRL_REG (PIN_MUX_BASE_ADDR + 0x52*4) +#define PD20_CTRL_REG (PIN_MUX_BASE_ADDR + 0x53*4) +#define PD21_CTRL_REG (PIN_MUX_BASE_ADDR + 0x54*4) +#define PE0_CTRL_REG (PIN_MUX_BASE_ADDR + 0x55*4) +#define PE1_CTRL_REG (PIN_MUX_BASE_ADDR + 0x56*4) +#define PE2_CTRL_REG (PIN_MUX_BASE_ADDR + 0x57*4) +#define PE3_CTRL_REG (PIN_MUX_BASE_ADDR + 0x58*4) +#define PE4_CTRL_REG (PIN_MUX_BASE_ADDR + 0x59*4) +#define PE5_CTRL_REG (PIN_MUX_BASE_ADDR + 0x5a*4) +#define PE6_CTRL_REG (PIN_MUX_BASE_ADDR + 0x5b*4) +#define PE7_CTRL_REG (PIN_MUX_BASE_ADDR + 0x5c*4) +#define PE8_CTRL_REG (PIN_MUX_BASE_ADDR + 0x5d*4) +#define PE9_CTRL_REG (PIN_MUX_BASE_ADDR + 0x5e*4) +#define PA_PMUX_REG (PIN_MUX_BASE_ADDR + 0x5f*4) +#define PB_PMUX_REG (PIN_MUX_BASE_ADDR + 0x60*4) +#define PC_PMUX_REG (PIN_MUX_BASE_ADDR + 0x61*4) +#define PD_PMUX0_REG (PIN_MUX_BASE_ADDR + 0x62*4) +#define PD_PMUX1_REG (PIN_MUX_BASE_ADDR + 0x63*4) +#define PE_PMUX_REG (PIN_MUX_BASE_ADDR + 0x64*4) +#define PE10_CTRL_REG (PIN_MUX_BASE_ADDR + 0x65*4) +#define PE11_CTRL_REG (PIN_MUX_BASE_ADDR + 0x66*4) + +#define PB15_CTRL_REG (PIN_MUX_BASE_ADDR + 0x69*4) +#define PB16_CTRL_REG (PIN_MUX_BASE_ADDR + 0x6a*4) +#define PB_PMUX1_REG (PIN_MUX_BASE_ADDR + 0x68*4) + + +//CRG +#define CRG_BASE_ADDR 0x04550000 +#define PLL0_CTL_REG0 (CRG_BASE_ADDR + 0x0000) +#define PLL0_CTL_REG1 (CRG_BASE_ADDR + 0x0004) +#define PLL0_CTL_REG2 (CRG_BASE_ADDR + 0x0008) +#define PLL0_CTL_REG3 (CRG_BASE_ADDR + 0x000C) +#define PLL0_CTL_REG4 (CRG_BASE_ADDR + 0x0010) +#define PLL1_CTL_REG0 (CRG_BASE_ADDR + 0x0014) +#define PLL1_CTL_REG1 (CRG_BASE_ADDR + 0x0018) +#define PLL1_CTL_REG2 (CRG_BASE_ADDR + 0x001C) +#define PLL1_CTL_REG3 (CRG_BASE_ADDR + 0x0020) +#define PLL1_CTL_REG4 (CRG_BASE_ADDR + 0x0024) +#define PLL2_CTL_REG0 (CRG_BASE_ADDR + 0x0028) +#define PLL2_CTL_REG1 (CRG_BASE_ADDR + 0x002C) +#define PLL2_CTL_REG2 (CRG_BASE_ADDR + 0x0030) +#define PLL2_CTL_REG3 (CRG_BASE_ADDR + 0x0034) +#define PLL2_CTL_REG4 (CRG_BASE_ADDR + 0x0038) +#define PLL3_CTL_REG0 (CRG_BASE_ADDR + 0x003C) +#define PLL3_CTL_REG1 (CRG_BASE_ADDR + 0x0040) +#define PLL3_CTL_REG2 (CRG_BASE_ADDR + 0x0044) +#define PLL3_CTL_REG3 (CRG_BASE_ADDR + 0x0048) +#define PLL3_CTL_REG4 (CRG_BASE_ADDR + 0x004C) +#define PLL4_CTL_REG0 (CRG_BASE_ADDR + 0x0050) +#define PLL4_CTL_REG1 (CRG_BASE_ADDR + 0x0054) +#define PLL4_CTL_REG2 (CRG_BASE_ADDR + 0x0058) +#define PLL4_CTL_REG3 (CRG_BASE_ADDR + 0x005C) +#define PLL4_CTL_REG4 (CRG_BASE_ADDR + 0x0060) +#define PLL5_CTL_REG0 (CRG_BASE_ADDR + 0x0064) +#define PLL5_CTL_REG1 (CRG_BASE_ADDR + 0x0068) +#define PLL5_CTL_REG2 (CRG_BASE_ADDR + 0x006C) +#define PLL5_CTL_REG3 (CRG_BASE_ADDR + 0x0070) +#define PLL5_CTL_REG4 (CRG_BASE_ADDR + 0x0074) +#define CLK_CTL_REG0 (CRG_BASE_ADDR + 0x00C4) +#define CLK_CTL_REG1 (CRG_BASE_ADDR + 0x00C8) +#define PLL0_TESTCLK_CFG_REG (CRG_BASE_ADDR + 0x00CC) +#define PLL1_TESTCLK_CFG_REG (CRG_BASE_ADDR + 0x00D0) +#define PLL2_TESTCLK_CFG_REG (CRG_BASE_ADDR + 0x00D4) +#define PLL3_TESTCLK_CFG_REG (CRG_BASE_ADDR + 0x00D8) +#define PLL4_TESTCLK_CFG_REG (CRG_BASE_ADDR + 0x00DC) +#define PLL5_TESTCLK_CFG_REG (CRG_BASE_ADDR + 0x00E0) +#define APC0_CLK_CFG_REG (CRG_BASE_ADDR + 0x00F8) +#define APC1_CLK_CFG_REG (CRG_BASE_ADDR + 0x00FC) +#define APC2_CLK_CFG_REG (CRG_BASE_ADDR + 0x0100) +#define APC3_CLK_CFG_REG (CRG_BASE_ADDR + 0x0104) +#define APC0_SYSCNT_CLK_CFG_REG (CRG_BASE_ADDR + 0x0108) +#define APC1_SYSCNT_CLK_CFG_REG (CRG_BASE_ADDR + 0x010C) +#define APC2_SYSCNT_CLK_CFG_REG (CRG_BASE_ADDR + 0x0110) +#define APC3_SYSCNT_CLK_CFG_REG (CRG_BASE_ADDR + 0x0114) +#define SRIO0_CLK_CFG_REG (CRG_BASE_ADDR + 0x0120) +#define SRIO1_CLK_CFG_REG (CRG_BASE_ADDR + 0x0124) +#define SRIO2_CLK_CFG_REG (CRG_BASE_ADDR + 0x0128) +#define MAIN_HI_CLK_CFG_REG (CRG_BASE_ADDR + 0x0134) +#define JS_HI_CLK_CFG_REG (CRG_BASE_ADDR + 0x0138) +#define ES_HI_CLK_CFG_REG (CRG_BASE_ADDR + 0x013C) +#define PET_HI_CLK_CFG_REG (CRG_BASE_ADDR + 0x0140) +#define MAIN_LO_CLK_CFG_REG (CRG_BASE_ADDR + 0x0144) +#define JS_LO_CLK_CFG_REG (CRG_BASE_ADDR + 0x0148) +#define ES_LO_CLK_CFG_REG (CRG_BASE_ADDR + 0x014C) +#define PET_LO_CLK_CFG_REG (CRG_BASE_ADDR + 0x0150) +#define MAINH_CLK_CFG_REG (CRG_BASE_ADDR + 0x0154) +#define JSH_CLK_CFG_REG (CRG_BASE_ADDR + 0x0158) +#define ESH_CLK_CFG_REG (CRG_BASE_ADDR + 0x015C) +#define PETH_CLK_CFG_REG (CRG_BASE_ADDR + 0x0160) +#define MAINP_CLK_CFG_REG (CRG_BASE_ADDR + 0x0164) +#define JSP_CLK_CFG_REG (CRG_BASE_ADDR + 0x0168) +#define ESP_CLK_CFG_REG (CRG_BASE_ADDR + 0x016C) +#define PETP_CLK_CFG_REG (CRG_BASE_ADDR + 0x0170) +#define DMAS0_CLK_CFG_REG (CRG_BASE_ADDR + 0x0174) +#define DMAS1_CLK_CFG_REG (CRG_BASE_ADDR + 0x0178) +#define SSI0_CLK_CFG_REG (CRG_BASE_ADDR + 0x017C) +#define SSI1_CLK_CFG_REG (CRG_BASE_ADDR + 0x0180) +#define SSI2_CLK_CFG_REG (CRG_BASE_ADDR + 0x0184) +#define SSI3_CLK_CFG_REG (CRG_BASE_ADDR + 0x0188) +#define IIC0_CLK_CFG_REG (CRG_BASE_ADDR + 0x018C) +#define IIC1_CLK_CFG_REG (CRG_BASE_ADDR + 0x0190) +#define TIMER00_CLK_CFG_REG (CRG_BASE_ADDR + 0x0194) +#define TIMER01_CLK_CFG_REG (CRG_BASE_ADDR + 0x0198) +#define TIMER02_CLK_CFG_REG (CRG_BASE_ADDR + 0x019C) +#define TIMER03_CLK_CFG_REG (CRG_BASE_ADDR + 0x01A0) +#define TIMER04_CLK_CFG_REG (CRG_BASE_ADDR + 0x01A4) +#define TIMER05_CLK_CFG_REG (CRG_BASE_ADDR + 0x01A8) +#define TIMER06_CLK_CFG_REG (CRG_BASE_ADDR + 0x01AC) +#define TIMER07_CLK_CFG_REG (CRG_BASE_ADDR + 0x01B0) +#define TIMER10_CLK_CFG_REG (CRG_BASE_ADDR + 0x01B4) +#define TIMER11_CLK_CFG_REG (CRG_BASE_ADDR + 0x01B8) +#define TIMER12_CLK_CFG_REG (CRG_BASE_ADDR + 0x01BC) +#define TIMER13_CLK_CFG_REG (CRG_BASE_ADDR + 0x01C0) +#define TIMER14_CLK_CFG_REG (CRG_BASE_ADDR + 0x01C4) +#define TIMER15_CLK_CFG_REG (CRG_BASE_ADDR + 0x01C8) +#define TIMER16_CLK_CFG_REG (CRG_BASE_ADDR + 0x01CC) +#define TIMER17_CLK_CFG_REG (CRG_BASE_ADDR + 0x01D0) +#define TIMER20_CLK_CFG_REG (CRG_BASE_ADDR + 0x01D4) +#define TIMER21_CLK_CFG_REG (CRG_BASE_ADDR + 0x01D8) +#define TIMER22_CLK_CFG_REG (CRG_BASE_ADDR + 0x01DC) +#define TIMER23_CLK_CFG_REG (CRG_BASE_ADDR + 0x01E0) +#define TIMER24_CLK_CFG_REG (CRG_BASE_ADDR + 0x01E4) +#define TIMER25_CLK_CFG_REG (CRG_BASE_ADDR + 0x01E8) +#define TIMER26_CLK_CFG_REG (CRG_BASE_ADDR + 0x01EC) +#define TIMER27_CLK_CFG_REG (CRG_BASE_ADDR + 0x01F0) +#define UART0_FRAC_DIV_CLK_CFG_REG (CRG_BASE_ADDR + 0x01F4) +#define UART1_FRAC_DIV_CLK_CFG_REG (CRG_BASE_ADDR + 0x01F8) +#define UART2_FRAC_DIV_CLK_CFG_REG (CRG_BASE_ADDR + 0x01FC) +#define UART3_FRAC_DIV_CLK_CFG_REG (CRG_BASE_ADDR + 0x0200) +#define UART0_CLK_CFG_REG (CRG_BASE_ADDR + 0x0204) +#define UART1_CLK_CFG_REG (CRG_BASE_ADDR + 0x0208) +#define UART2_CLK_CFG_REG (CRG_BASE_ADDR + 0x020C) +#define UART3_CLK_CFG_REG (CRG_BASE_ADDR + 0x0210) +#define GMAC0_PRE_TX_CFG_REG (CRG_BASE_ADDR + 0x0214) +#define GMAC1_PRE_TX_CFG_REG (CRG_BASE_ADDR + 0x0218) +#define GMAC0_TX_CFG_REG (CRG_BASE_ADDR + 0x021C) +#define GMAC1_TX_CFG_REG (CRG_BASE_ADDR + 0x0220) +#define GMAC0_TUNING_CFG_REG (CRG_BASE_ADDR + 0x0224) +#define GMAC1_TUNING_CFG_REG (CRG_BASE_ADDR + 0x0228) +#define GMAC0_PTP_CFG_REG (CRG_BASE_ADDR + 0x022C) +#define GMAC1_PTP_CFG_REG (CRG_BASE_ADDR + 0x0230) +#define TMAC_PTP_CFG_REG (CRG_BASE_ADDR + 0x0234) +#define RTC_CLK_CFG_REG (CRG_BASE_ADDR + 0x0238) +#define GPIO_PRE_DB_CLK_CFG_REG (CRG_BASE_ADDR + 0x023C) +#define GPIO_DB_CLK_CFG_REG (CRG_BASE_ADDR + 0x0240) +#define RFC_CLK_CFG_REG (CRG_BASE_ADDR + 0x0244) +//#define JESD_CLK_CFG_REG (CRG_BASE_ADDR + 0x0248) +#define PCIE_AUX_CLK_CFG_REG (CRG_BASE_ADDR + 0x024C) +#define M3_TPIU_CLK_CFG_REG (CRG_BASE_ADDR + 0x0250) +#define M3_DAP_CLK_CFG_REG (CRG_BASE_ADDR + 0x0254) +#define M3_AHB_CLK_CFG_REG (CRG_BASE_ADDR + 0x0258) +#define PLL_STATUS_REG (CRG_BASE_ADDR + 0x0264) +#define PLL_LOCK_MASK (CRG_BASE_ADDR + 0x0268) +#define WDT_RST_CRG_REG (CRG_BASE_ADDR + 0x026C) +#define SDIO_RST_CFG_REG (CRG_BASE_ADDR + 0x0270) +#define APC0_RST_CFG_REG (CRG_BASE_ADDR + 0x0274) +#define APC1_RST_CFG_REG (CRG_BASE_ADDR + 0x0278) +#define APC2_RST_CFG_REG (CRG_BASE_ADDR + 0x027C) +#define APC3_RST_CFG_REG (CRG_BASE_ADDR + 0x0280) +#define APC0_SYSCNT_RST_CFG_REG (CRG_BASE_ADDR + 0x0284) +#define APC1_SYSCNT_RST_CFG_REG (CRG_BASE_ADDR + 0x0288) +#define APC2_SYSCNT_RST_CFG_REG (CRG_BASE_ADDR + 0x028C) +#define APC3_SYSCNT_RST_CFG_REG (CRG_BASE_ADDR + 0x0290) +#define SRIO0_RST_CFG_REG (CRG_BASE_ADDR + 0x0294) +#define SRIO1_RST_CFG_REG (CRG_BASE_ADDR + 0x0298) +#define SRIO2_RST_CFG_REG (CRG_BASE_ADDR + 0x029C) +#define MAIN_HI_RST_CFG_REG (CRG_BASE_ADDR + 0x02A0) +#define JS_HI_RST_CFG_REG (CRG_BASE_ADDR + 0x02A4) +#define ES_HI_RST_CFG_REG (CRG_BASE_ADDR + 0x02A8) +#define PET_HI_RST_CFG_REG (CRG_BASE_ADDR + 0x02AC) +#define MAIN_LO_RST_CFG_REG (CRG_BASE_ADDR + 0x02B0) +#define JS_LO_RST_CFG_REG (CRG_BASE_ADDR + 0x02B4) +#define ES_LO_RST_CFG_REG (CRG_BASE_ADDR + 0x02B8) +#define PET_LO_RST_CFG_REG (CRG_BASE_ADDR + 0x02BC) +#define MAINH_RST_CFG_REG (CRG_BASE_ADDR + 0x02C0) +#define JSH_RST_CFG_REG (CRG_BASE_ADDR + 0x02C4) +#define ESH_RST_CFG_REG (CRG_BASE_ADDR + 0x02C8) +#define PETH_RST_CFG_REG (CRG_BASE_ADDR + 0x02CC) +#define MAINP_RST_CFG_REG (CRG_BASE_ADDR + 0x02D0) +#define JSP_RST_CFG_REG (CRG_BASE_ADDR + 0x02D4) +#define ESP_RST_CFG_REG (CRG_BASE_ADDR + 0x02D8) +#define PETP_RST_CFG_REG (CRG_BASE_ADDR + 0x02DC) +#define DMAS0_RST_CFG_REG (CRG_BASE_ADDR + 0x02E0) +#define DMAS1_RST_CFG_REG (CRG_BASE_ADDR + 0x02E4) +#define SSI0_RST_CFG_REG (CRG_BASE_ADDR + 0x02E8) +#define SSI1_RST_CFG_REG (CRG_BASE_ADDR + 0x02EC) +#define SSI2_RST_CFG_REG (CRG_BASE_ADDR + 0x02F0) +#define SSI3_RST_CFG_REG (CRG_BASE_ADDR + 0x02F4) +#define IIC0_RST_CFG_REG (CRG_BASE_ADDR + 0x02F8) +#define IIC1_RST_CFG_REG (CRG_BASE_ADDR + 0x02FC) +#define TIMER00_RST_CFG_REG (CRG_BASE_ADDR + 0x0300) +#define TIMER01_RST_CFG_REG (CRG_BASE_ADDR + 0x0304) +#define TIMER02_RST_CFG_REG (CRG_BASE_ADDR + 0x0308) +#define TIMER03_RST_CFG_REG (CRG_BASE_ADDR + 0x030C) +#define TIMER04_RST_CFG_REG (CRG_BASE_ADDR + 0x0310) +#define TIMER05_RST_CFG_REG (CRG_BASE_ADDR + 0x0314) +#define TIMER06_RST_CFG_REG (CRG_BASE_ADDR + 0x0318) +#define TIMER07_RST_CFG_REG (CRG_BASE_ADDR + 0x031C) +#define TIMER10_RST_CFG_REG (CRG_BASE_ADDR + 0x0320) +#define TIMER11_RST_CFG_REG (CRG_BASE_ADDR + 0x0324) +#define TIMER12_RST_CFG_REG (CRG_BASE_ADDR + 0x0328) +#define TIMER13_RST_CFG_REG (CRG_BASE_ADDR + 0x032C) +#define TIMER14_RST_CFG_REG (CRG_BASE_ADDR + 0x0330) +#define TIMER15_RST_CFG_REG (CRG_BASE_ADDR + 0x0334) +#define TIMER16_RST_CFG_REG (CRG_BASE_ADDR + 0x0338) +#define TIMER17_RST_CFG_REG (CRG_BASE_ADDR + 0x033C) +#define TIMER20_RST_CFG_REG (CRG_BASE_ADDR + 0x0340) +#define TIMER21_RST_CFG_REG (CRG_BASE_ADDR + 0x0344) +#define TIMER22_RST_CFG_REG (CRG_BASE_ADDR + 0x0348) +#define TIMER23_RST_CFG_REG (CRG_BASE_ADDR + 0x034C) +#define TIMER24_RST_CFG_REG (CRG_BASE_ADDR + 0x0350) +#define TIMER25_RST_CFG_REG (CRG_BASE_ADDR + 0x0354) +#define TIMER26_RST_CFG_REG (CRG_BASE_ADDR + 0x0358) +#define TIMER27_RST_CFG_REG (CRG_BASE_ADDR + 0x035C) +#define UART0_RST_CFG_REG (CRG_BASE_ADDR + 0x0360) +#define UART1_RST_CFG_REG (CRG_BASE_ADDR + 0x0364) +#define UART2_RST_CFG_REG (CRG_BASE_ADDR + 0x0368) +#define UART3_RST_CFG_REG (CRG_BASE_ADDR + 0x036C) +#define GPIO_RST_CFG_REG (CRG_BASE_ADDR + 0x0370) +#define RTC_RST_CFG_REG (CRG_BASE_ADDR + 0x0374) +#define GMAC0_TX_RST_CFG_REG (CRG_BASE_ADDR + 0x0378) +#define GMAC1_TX_RST_CFG_REG (CRG_BASE_ADDR + 0x037C) +#define TMAC_PTP_RST_CFG_REG (CRG_BASE_ADDR + 0x0380) +#define RFC_RST_CFG_REG (CRG_BASE_ADDR + 0x0384) +#define JS_PMA_RST_CFG_REG (CRG_BASE_ADDR + 0x0388) +#define ES_PMA_RST_CFG_REG (CRG_BASE_ADDR + 0x038C) +#define PET_PMA_RST_CFG_REG (CRG_BASE_ADDR + 0x0390) +#define JS_PMA_CLK_CFG_REG (CRG_BASE_ADDR + 0x0394) +#define ES_PMA_CLK_CFG_REG (CRG_BASE_ADDR + 0x0398) +#define PET_PMA_CLK_CFG_REG (CRG_BASE_ADDR + 0x039C) +#define JESD_SYSREF_CLK_CFG_REG (CRG_BASE_ADDR + 0x03A0) +#define M3_TPIU_RST_CFG_REG (CRG_BASE_ADDR + 0x03A4) +#define M3_DAP_RST_CFG_REG (CRG_BASE_ADDR + 0x03A8) +#define M3_PORN_RST_CFG_REG (CRG_BASE_ADDR + 0x03AC) +#define M3_RST_CFG_REG (CRG_BASE_ADDR + 0x03B0) +#define M3_AHB_RST_CFG_REG (CRG_BASE_ADDR + 0x03B4) +#define USBPHY_RST_CFG_REG (CRG_BASE_ADDR + 0x03B8) +#define SYSC_RST_MASK (CRG_BASE_ADDR + 0x03BC) +#define SMMU_CLK_CFG_REG (CRG_BASE_ADDR + 0x03C0) +#define SMMU_RST_CFG_REG (CRG_BASE_ADDR + 0x03C4) +#define EFUSE_CLK_CFG_REG (CRG_BASE_ADDR + 0x03C8) +#define EFUSE_RST_CFG_REG (CRG_BASE_ADDR + 0x03CC) +#define SPACC_CLK_CFG_REG (CRG_BASE_ADDR + 0x03D0) +#define SPACC_RST_CFG_REG (CRG_BASE_ADDR + 0x03D4) +#define PLL0_DYNAMIC_CFG_REG (CRG_BASE_ADDR + 0x03D8) +#define PLL1_DYNAMIC_CFG_REG (CRG_BASE_ADDR + 0x03DC) +#define PLL2_DYNAMIC_CFG_REG (CRG_BASE_ADDR + 0x03E0) +#define PLL3_DYNAMIC_CFG_REG (CRG_BASE_ADDR + 0x03E4) +#define PLL4_DYNAMIC_CFG_REG (CRG_BASE_ADDR + 0x03E8) +#define PLL5_DYNAMIC_CFG_REG (CRG_BASE_ADDR + 0x03EC) +#define PLL01_FBDIV_DY_REG (CRG_BASE_ADDR + 0x03F0) +#define PLL23_FBDIV_DY_REG (CRG_BASE_ADDR + 0x03F4) +#define PLL45_FBDIV_DY_REG (CRG_BASE_ADDR + 0x03F8) +#define PLL0_FRAC_DY_REG (CRG_BASE_ADDR + 0x03FC) +#define PLL1_FRAC_DY_REG (CRG_BASE_ADDR + 0x0400) +#define PLL2_FRAC_DY_REG (CRG_BASE_ADDR + 0x0404) +#define PLL3_FRAC_DY_REG (CRG_BASE_ADDR + 0x0408) +#define PLL4_FRAC_DY_REG (CRG_BASE_ADDR + 0x040C) +#define PLL5_FRAC_DY_REG (CRG_BASE_ADDR + 0x0410) +#define PLL_FIFO_FULL_ST_REG (CRG_BASE_ADDR + 0x0414) +#define PLL_FIFO_EMPTY_ST_REG (CRG_BASE_ADDR + 0x0418) +#define PLL0_FIFO_DY_CFG_REG (CRG_BASE_ADDR + 0x041C) +#define PLL1_FIFO_DY_CFG_REG (CRG_BASE_ADDR + 0x0420) +#define PLL2_FIFO_DY_CFG_REG (CRG_BASE_ADDR + 0x0424) +#define PLL3_FIFO_DY_CFG_REG (CRG_BASE_ADDR + 0x0428) +#define PLL4_FIFO_DY_CFG_REG (CRG_BASE_ADDR + 0x042C) +#define PLL5_FIFO_DY_CFG_REG (CRG_BASE_ADDR + 0x0430) +#define EIP_CLK_CFG_REG (CRG_BASE_ADDR + 0x0434) +#define EIP_RST_CFG_REG (CRG_BASE_ADDR + 0x0438) +#define PMA_SUB_RST_CFG_REG (CRG_BASE_ADDR + 0x0444) + +#define DEBUG_SCAN_CLK_CFG_REG (CRG_BASE_ADDR + 0x0448) +#define DEBUG_SCAN_RST_CFG_REG (CRG_BASE_ADDR + 0x044C) +//SYSCTRL +#define SYSCFG_BASE_ADDR 0x04560000 +#define APC_CTRL_REG (SYSCFG_BASE_ADDR + 0x00*4) +#define QOS_CTRL1_REG (SYSCFG_BASE_ADDR + 0x01*4) +#define QOS_CTRL2_REG (SYSCFG_BASE_ADDR + 0x02*4) +#define APCS1_AWUSER_REG (SYSCFG_BASE_ADDR + 0x03*4) +#define APCS1_WUSER_REG (SYSCFG_BASE_ADDR + 0x04*4) +#define APCS1_ARUSER_REG (SYSCFG_BASE_ADDR + 0x05*4) +#define APCS2_AWUSER_REG (SYSCFG_BASE_ADDR + 0x06*4) +#define APCS2_WUSER_REG (SYSCFG_BASE_ADDR + 0x07*4) +#define APCS2_ARUSER_REG (SYSCFG_BASE_ADDR + 0x08*4) +#define APCS3_AWUSER_REG (SYSCFG_BASE_ADDR + 0x09*4) +#define APCS3_WUSER_REG (SYSCFG_BASE_ADDR + 0x0a*4) +#define APCS3_ARUSER_REG (SYSCFG_BASE_ADDR + 0x0b*4) +#define APCS0_AWUSER_REG (SYSCFG_BASE_ADDR + 0x0c*4) +#define APCS0_WUSER_REG (SYSCFG_BASE_ADDR + 0x0d*4) +#define APCS0_ARUSER_REG (SYSCFG_BASE_ADDR + 0x0e*4) +#define GMAC0_AWUSER_REG (SYSCFG_BASE_ADDR + 0x0f*4) +#define GMAC0_WUSER_REG (SYSCFG_BASE_ADDR + 0x10*4) +#define GMAC0_ARUSER_REG (SYSCFG_BASE_ADDR + 0x11*4) +#define GMAC1_AWUSER_REG (SYSCFG_BASE_ADDR + 0x12*4) +#define GMAC1_WUSER_REG (SYSCFG_BASE_ADDR + 0x13*4) +#define GMAC1_ARUSER_REG (SYSCFG_BASE_ADDR + 0x14*4) +#define APRFM_AWUSER_REG (SYSCFG_BASE_ADDR + 0x15*4) +#define APRFM_ARUSER_REG (SYSCFG_BASE_ADDR + 0x16*4) +#define PET_MAIN_AWUSER_REG (SYSCFG_BASE_ADDR + 0x17*4) +#define PET_MAIN_WUSER_REG (SYSCFG_BASE_ADDR + 0x18*4) +#define PET_MAIN_ARUSER_REG (SYSCFG_BASE_ADDR + 0x19*4) +#define TESTMODE_SYS_REG (SYSCFG_BASE_ADDR + 0x1a*4) +#define BOOT_I2C_GPIO_REG (SYSCFG_BASE_ADDR + 0x1b*4) +#define PET_MAIN_RUSER_REG (SYSCFG_BASE_ADDR + 0x1c*4) +#define PET_MAIN_BUSER_REG (SYSCFG_BASE_ADDR + 0x1d*4) +#define CCI_QOS_ACCEPT_REG (SYSCFG_BASE_ADDR + 0x1e*4) +#define DMAS_SDMMC_REGCTRL (SYSCFG_BASE_ADDR + 0x1f*4) +#define CCI_EVNTBUS6_REG (SYSCFG_BASE_ADDR + 0x20*4) +#define CCI_EVNTBUS7_REG (SYSCFG_BASE_ADDR + 0x21*4) +#define SMMU_SHARE_CTRL (SYSCFG_BASE_ADDR + 0x22*4) +#define A72_EVENT_SEL (SYSCFG_BASE_ADDR + 0x25*4) +#define A72_CTRL0_STATUS_REG (SYSCFG_BASE_ADDR + 0x26*4) +#define A72_CTRL1_STATUS_REG (SYSCFG_BASE_ADDR + 0x27*4) +#define QOS_CTRL3_REG (SYSCFG_BASE_ADDR + 0x28*4) +#define CCI_ADDRMAP_REG (SYSCFG_BASE_ADDR + 0x29*4) +#define CCI_ARVMIDEXTS_REG (SYSCFG_BASE_ADDR + 0x2a*4) +#define CCI_ARUSERS3_REG (SYSCFG_BASE_ADDR + 0x2b*4) +#define CCI_AWUSERS3_REG (SYSCFG_BASE_ADDR + 0x2c*4) +#define CCI_WUSERS3_REG (SYSCFG_BASE_ADDR + 0x2d*4) +#define CCI_CTRL_REG (SYSCFG_BASE_ADDR + 0x2e*4) +#define CCI_EVNTBUS0_REG (SYSCFG_BASE_ADDR + 0x2f*4) +#define CCI_EVNTBUS1_REG (SYSCFG_BASE_ADDR + 0x30*4) +#define CCI_EVNTBUS2_REG (SYSCFG_BASE_ADDR + 0x31*4) +#define CCI_EVNTBUS3_REG (SYSCFG_BASE_ADDR + 0x32*4) +#define CCI_EVNTBUS4_REG (SYSCFG_BASE_ADDR + 0x33*4) +#define CCI_EVNTBUS5_REG (SYSCFG_BASE_ADDR + 0x34*4) +#define CCI_OVERGLOW_MASK_REG (SYSCFG_BASE_ADDR + 0x35*4) +#define EVENT_ZERO_REG (SYSCFG_BASE_ADDR + 0x36*4) +#define RSB_CFG_RTC_UART_TIMER_REG (SYSCFG_BASE_ADDR + 0x37*4) +#define SDIO_HADDR_GMAC1_GMAC0_REG (SYSCFG_BASE_ADDR + 0x38*4) +#define HAUSER_M3_M3_SUB_S_REG (SYSCFG_BASE_ADDR + 0x39*4) +#define APRFM_USER0_REG (SYSCFG_BASE_ADDR + 0x3a*4) +#define APRFM_USER1_REG (SYSCFG_BASE_ADDR + 0x3b*4) +#define APRFM_USER2_REG (SYSCFG_BASE_ADDR + 0x3c*4) +#define APRFM_USER3_REG (SYSCFG_BASE_ADDR + 0x3d*4) +#define APRFM_USER4_REG (SYSCFG_BASE_ADDR + 0x3e*4) +#define APRFM_USER5_REG (SYSCFG_BASE_ADDR + 0x3f*4) +#define SMMU_WDT_REG (SYSCFG_BASE_ADDR + 0x40*4) +#define APC_QOS_REG (SYSCFG_BASE_ADDR + 0x41*4) +#define RFCQOS_SM_APCSEL_REG (SYSCFG_BASE_ADDR + 0x42*4) +#define PLL_TESTCLK_SEL_REG (SYSCFG_BASE_ADDR + 0x43*4) +#define DFTCTRL_SYS_REG (SYSCFG_BASE_ADDR + 0x44*4) +#define M4_WUSER_REG (SYSCFG_BASE_ADDR + 0x45*4) +#define SYSC_CTC0_REG (SYSCFG_BASE_ADDR + 0x46*4) +#define SYSC_CTC1_REG (SYSCFG_BASE_ADDR + 0x47*4) +#define SYSC_CTC2_REG (SYSCFG_BASE_ADDR + 0x48*4) +#define SYSC_CTC3_REG (SYSCFG_BASE_ADDR + 0x49*4) +#define SYSC_CTC4_REG (SYSCFG_BASE_ADDR + 0x4A*4) +#define SYSC_CTC5_REG (SYSCFG_BASE_ADDR + 0x4B*4) +#define SYSC_CTC6_REG (SYSCFG_BASE_ADDR + 0x4C*4) +#define SYSC_CTC7_REG (SYSCFG_BASE_ADDR + 0x4D*4) +#define SYSC_CTC8_REG (SYSCFG_BASE_ADDR + 0x4E*4) +#define SYSC_CTC9_REG (SYSCFG_BASE_ADDR + 0x4F*4) +#define SYSC_CTC10_REG (SYSCFG_BASE_ADDR + 0x50*4) +#define SYSC_CTC11_REG (SYSCFG_BASE_ADDR + 0x51*4) +#define SYSC_CTC12_REG (SYSCFG_BASE_ADDR + 0x52*4) +#define SYSC_CTC13_REG (SYSCFG_BASE_ADDR + 0x53*4) +#define SYSC_CTC14_REG (SYSCFG_BASE_ADDR + 0x54*4) +#define SYSC_CTC15_REG (SYSCFG_BASE_ADDR + 0x55*4) +#define SYSC_CTC16_REG (SYSCFG_BASE_ADDR + 0x56*4) +#define SYSC_CTC17_REG (SYSCFG_BASE_ADDR + 0x57*4) +#define SYSC_CTC18_REG (SYSCFG_BASE_ADDR + 0x58*4) +#define SYSC_CTC19_REG (SYSCFG_BASE_ADDR + 0x59*4) +#define SYSC_CTC20_REG (SYSCFG_BASE_ADDR + 0x5A*4) +#define SYSC_CTC21_REG (SYSCFG_BASE_ADDR + 0x5B*4) +#define SYSC_CTC22_REG (SYSCFG_BASE_ADDR + 0x5C*4) +#define SYSC_CTC23_REG (SYSCFG_BASE_ADDR + 0x5D*4) +#define SYSC_CTC24_REG (SYSCFG_BASE_ADDR + 0x5E*4) +#define SYSC_CTC25_REG (SYSCFG_BASE_ADDR + 0x5F*4) +#define SYSC_CTC26_REG (SYSCFG_BASE_ADDR + 0x60*4) +#define SYSC_CTC27_REG (SYSCFG_BASE_ADDR + 0x61*4) +#define SYSC_CTC28_REG (SYSCFG_BASE_ADDR + 0x62*4) +#define SYSC_CTC29_REG (SYSCFG_BASE_ADDR + 0x63*4) +#define SYSC_CTC30_REG (SYSCFG_BASE_ADDR + 0x64*4) +#define SYSC_CTC31_REG (SYSCFG_BASE_ADDR + 0x65*4) +#define SYSC_CTC32_REG (SYSCFG_BASE_ADDR + 0x66*4) +#define SYSC_CTC33_REG (SYSCFG_BASE_ADDR + 0x67*4) +#define SYSC_CTC34_REG (SYSCFG_BASE_ADDR + 0x68*4) +#define SYSC_CTC35_REG (SYSCFG_BASE_ADDR + 0x69*4) +#define SYSC_CTC36_REG (SYSCFG_BASE_ADDR + 0x6A*4) +#define SYSC_CTC37_REG (SYSCFG_BASE_ADDR + 0x6B*4) +#define SYSC_CTC38_REG (SYSCFG_BASE_ADDR + 0x6C*4) +#define SYSC_CTC39_REG (SYSCFG_BASE_ADDR + 0x6D*4) +#define SYSC_CTC40_REG (SYSCFG_BASE_ADDR + 0x6E*4) +#define SYSC_CTC41_REG (SYSCFG_BASE_ADDR + 0x6F*4) +#define SYSC_CTC42_REG (SYSCFG_BASE_ADDR + 0x70*4) +#define SYSC_CTC43_REG (SYSCFG_BASE_ADDR + 0x71*4) +#define SYSC_CTC44_REG (SYSCFG_BASE_ADDR + 0x72*4) +#define SYSC_CTC45_REG (SYSCFG_BASE_ADDR + 0x73*4) +#define SYSC_CTC46_REG (SYSCFG_BASE_ADDR + 0x74*4) +#define SYSC_CTC47_REG (SYSCFG_BASE_ADDR + 0x75*4) +#define SYSC_CTC48_REG (SYSCFG_BASE_ADDR + 0x76*4) +#define SYSC_CTC49_REG (SYSCFG_BASE_ADDR + 0x77*4) +#define SYSC_CTC50_REG (SYSCFG_BASE_ADDR + 0x78*4) +#define SYSC_CTC51_REG (SYSCFG_BASE_ADDR + 0x79*4) +#define SYSC_CTC52_REG (SYSCFG_BASE_ADDR + 0x7A*4) +#define SYSC_CTC53_REG (SYSCFG_BASE_ADDR + 0x7B*4) +#define SYSC_CTC54_REG (SYSCFG_BASE_ADDR + 0x7C*4) +#define SYSC_CTC55_REG (SYSCFG_BASE_ADDR + 0x7D*4) +#define SYSC_CTC56_REG (SYSCFG_BASE_ADDR + 0x7E*4) +#define SYSC_CTC57_REG (SYSCFG_BASE_ADDR + 0x7F*4) +#define SYSC_CTC58_REG (SYSCFG_BASE_ADDR + 0x80*4) +#define SYSC_CTC59_REG (SYSCFG_BASE_ADDR + 0x81*4) +#define SYSC_CTC60_REG (SYSCFG_BASE_ADDR + 0x82*4) +#define SYSC_CTC61_REG (SYSCFG_BASE_ADDR + 0x83*4) +#define SYSC_CTC62_REG (SYSCFG_BASE_ADDR + 0x84*4) +#define SYSC_CTC63_REG (SYSCFG_BASE_ADDR + 0x85*4) +#define SYSC_CTC64_REG (SYSCFG_BASE_ADDR + 0x86*4) +#define SYSC_CTC65_REG (SYSCFG_BASE_ADDR + 0x87*4) +#define SYSC_CTC66_REG (SYSCFG_BASE_ADDR + 0x88*4) +#define SYSC_CTC67_REG (SYSCFG_BASE_ADDR + 0x89*4) +#define SYSC_CTC68_REG (SYSCFG_BASE_ADDR + 0x8A*4) +#define SYSC_CTC69_REG (SYSCFG_BASE_ADDR + 0x8B*4) +#define SYSC_CTC70_REG (SYSCFG_BASE_ADDR + 0x8C*4) +#define SYSC_CTC71_REG (SYSCFG_BASE_ADDR + 0x8D*4) +#define M3ARUSER_REG (SYSCFG_BASE_ADDR + 0x8E*4) +#define M3AWUSER_REG (SYSCFG_BASE_ADDR + 0x8F*4) +#define ARUSER_M1_CSU_REG (SYSCFG_BASE_ADDR + 0x90*4) +#define AWUSER_M1_CSU_REG (SYSCFG_BASE_ADDR + 0x91*4) +#define WUSER_M1_CSU_REG (SYSCFG_BASE_ADDR + 0x92*4) +#define CCI_ARUSER_S4_REG (SYSCFG_BASE_ADDR + 0x93*4) +#define CCI_AWUSER_S4_REG (SYSCFG_BASE_ADDR + 0x94*4) +#define CCI_WUSER_S4_REG (SYSCFG_BASE_ADDR + 0x95*4) +#define SYSC_CP_R0_REG (SYSCFG_BASE_ADDR + 0x96*4) +#define SYSC_CP_R1_REG (SYSCFG_BASE_ADDR + 0x97*4) +#define SYSC_CP_R2_REG (SYSCFG_BASE_ADDR + 0x98*4) +#define SYSC_CP_R3_REG (SYSCFG_BASE_ADDR + 0x99*4) +#define SYSC_CP_R4_REG (SYSCFG_BASE_ADDR + 0x9A*4) +#define SYSC_CP_R5_REG (SYSCFG_BASE_ADDR + 0x9B*4) +#define SYSC_CP_R6_REG (SYSCFG_BASE_ADDR + 0x9C*4) +#define SYSC_CP_R7_REG (SYSCFG_BASE_ADDR + 0x9D*4) +#define SYSC_CP_R8_REG (SYSCFG_BASE_ADDR + 0x9E*4) +#define SYSC_CP_R9_REG (SYSCFG_BASE_ADDR + 0x9F*4) +#define SYSC_CP_R10_REG (SYSCFG_BASE_ADDR + 0xA0*4) +#define SYSC_CP_R11_REG (SYSCFG_BASE_ADDR + 0xA1*4) +#define SYSC_CP_R12_REG (SYSCFG_BASE_ADDR + 0xA2*4) +#define SYSC_CP_R13_REG (SYSCFG_BASE_ADDR + 0xA3*4) +#define SYSC_CP_R14_REG (SYSCFG_BASE_ADDR + 0xA4*4) +#define SYSC_CP_R15_REG (SYSCFG_BASE_ADDR + 0xA5*4) +#define SYSC_CP_R16_REG (SYSCFG_BASE_ADDR + 0xA6*4) +#define SYSC_CP_R17_REG (SYSCFG_BASE_ADDR + 0xA7*4) +#define SYSC_CP_R18_REG (SYSCFG_BASE_ADDR + 0xA8*4) +#define EFUSE_CTRL_REG (SYSCFG_BASE_ADDR + 0XA9*4) +#define CCI_NSAIDS_REG0 (SYSCFG_BASE_ADDR + 0xAa*4) +#define CCI_NSAIDS_REG1 (SYSCFG_BASE_ADDR + 0xAb*4) +#define CCI_NSAIDM_REG1 (SYSCFG_BASE_ADDR + 0xAc*4) +#define APSPACC_ADDR_CTRL (SYSCFG_BASE_ADDR + 0xAD*4) +#define CPSPACC_ADDR_CTRL (SYSCFG_BASE_ADDR + 0xAE*4) +#define CCI_NSAIDS_REG2 (SYSCFG_BASE_ADDR + 0xAF*4) +#define SYSCTRL_REG0 (SYSCFG_BASE_ADDR + 176*4) +#define SYSCTRL_REG1 (SYSCFG_BASE_ADDR + 177*4) +#define SYSCTRL_REG2 (SYSCFG_BASE_ADDR + 178*4) +#define SYSCTRL_REG3 (SYSCFG_BASE_ADDR + 179*4) +#define APC0_INT_MASK0 (SYSCFG_BASE_ADDR + 180*4) +#define APC0_INT_MASK1 (SYSCFG_BASE_ADDR + 181*4) +#define APC0_INT_MASK2 (SYSCFG_BASE_ADDR + 182*4) +#define APC0_INT_MASK3 (SYSCFG_BASE_ADDR + 183*4) +#define APC0_INT_MASK4 (SYSCFG_BASE_ADDR + 184*4) +#define APC0_INT_MASK5 (SYSCFG_BASE_ADDR + 185*4) +#define APC0_INT_MASK6 (SYSCFG_BASE_ADDR + 186*4) +#define APC0_INT_MASK7 (SYSCFG_BASE_ADDR + 187*4) +#define APC0_INT_MASK8 (SYSCFG_BASE_ADDR + 188*4) +#define APC0_INT_MASK9 (SYSCFG_BASE_ADDR + 189*4) +#define APC0_INT_MASK10 (SYSCFG_BASE_ADDR + 190*4) +#define APC0_INT_MASK11 (SYSCFG_BASE_ADDR + 191*4) +#define APC0_INT_MASK12 (SYSCFG_BASE_ADDR + 192*4) +#define APC0_INT_MASK13 (SYSCFG_BASE_ADDR + 193*4) +#define APC0_INT_MASK14 (SYSCFG_BASE_ADDR + 194*4) +#define APC0_INT_MASK15 (SYSCFG_BASE_ADDR + 195*4) +#define APC1_INT_MASK0 (SYSCFG_BASE_ADDR + 196*4) +#define APC1_INT_MASK1 (SYSCFG_BASE_ADDR + 197*4) +#define APC1_INT_MASK2 (SYSCFG_BASE_ADDR + 198*4) +#define APC1_INT_MASK3 (SYSCFG_BASE_ADDR + 199*4) +#define APC1_INT_MASK4 (SYSCFG_BASE_ADDR + 200*4) +#define APC1_INT_MASK5 (SYSCFG_BASE_ADDR + 201*4) +#define APC1_INT_MASK6 (SYSCFG_BASE_ADDR + 202*4) +#define APC1_INT_MASK7 (SYSCFG_BASE_ADDR + 203*4) +#define APC1_INT_MASK8 (SYSCFG_BASE_ADDR + 204*4) +#define APC1_INT_MASK9 (SYSCFG_BASE_ADDR + 205*4) +#define APC1_INT_MASK10 (SYSCFG_BASE_ADDR + 206*4) +#define APC1_INT_MASK11 (SYSCFG_BASE_ADDR + 207*4) +#define APC1_INT_MASK12 (SYSCFG_BASE_ADDR + 208*4) +#define APC1_INT_MASK13 (SYSCFG_BASE_ADDR + 209*4) +#define APC1_INT_MASK14 (SYSCFG_BASE_ADDR + 210*4) +#define APC1_INT_MASK15 (SYSCFG_BASE_ADDR + 211*4) +#define APC2_INT_MASK0 (SYSCFG_BASE_ADDR + 212*4) +#define APC2_INT_MASK1 (SYSCFG_BASE_ADDR + 213*4) +#define APC2_INT_MASK2 (SYSCFG_BASE_ADDR + 214*4) +#define APC2_INT_MASK3 (SYSCFG_BASE_ADDR + 215*4) +#define APC2_INT_MASK4 (SYSCFG_BASE_ADDR + 216*4) +#define APC2_INT_MASK5 (SYSCFG_BASE_ADDR + 217*4) +#define APC2_INT_MASK6 (SYSCFG_BASE_ADDR + 218*4) +#define APC2_INT_MASK7 (SYSCFG_BASE_ADDR + 219*4) +#define APC2_INT_MASK8 (SYSCFG_BASE_ADDR + 220*4) +#define APC2_INT_MASK9 (SYSCFG_BASE_ADDR + 221*4) +#define APC2_INT_MASK10 (SYSCFG_BASE_ADDR + 222*4) +#define APC2_INT_MASK11 (SYSCFG_BASE_ADDR + 223*4) +#define APC2_INT_MASK12 (SYSCFG_BASE_ADDR + 224*4) +#define APC2_INT_MASK13 (SYSCFG_BASE_ADDR + 225*4) +#define APC2_INT_MASK14 (SYSCFG_BASE_ADDR + 226*4) +#define APC2_INT_MASK15 (SYSCFG_BASE_ADDR + 227*4) +#define APC3_INT_MASK0 (SYSCFG_BASE_ADDR + 228*4) +#define APC3_INT_MASK1 (SYSCFG_BASE_ADDR + 229*4) +#define APC3_INT_MASK2 (SYSCFG_BASE_ADDR + 230*4) +#define APC3_INT_MASK3 (SYSCFG_BASE_ADDR + 231*4) +#define APC3_INT_MASK4 (SYSCFG_BASE_ADDR + 232*4) +#define APC3_INT_MASK5 (SYSCFG_BASE_ADDR + 233*4) +#define APC3_INT_MASK6 (SYSCFG_BASE_ADDR + 234*4) +#define APC3_INT_MASK7 (SYSCFG_BASE_ADDR + 235*4) +#define APC3_INT_MASK8 (SYSCFG_BASE_ADDR + 236*4) +#define APC3_INT_MASK9 (SYSCFG_BASE_ADDR + 237*4) +#define APC3_INT_MASK10 (SYSCFG_BASE_ADDR + 238*4) +#define APC3_INT_MASK11 (SYSCFG_BASE_ADDR + 239*4) +#define APC3_INT_MASK12 (SYSCFG_BASE_ADDR + 240*4) +#define APC3_INT_MASK13 (SYSCFG_BASE_ADDR + 241*4) +#define APC3_INT_MASK14 (SYSCFG_BASE_ADDR + 242*4) +#define APC3_INT_MASK15 (SYSCFG_BASE_ADDR + 243*4) +#define EIP0_AWUSER (SYSCFG_BASE_ADDR + 300*4) +#define EIP0_WUSER (SYSCFG_BASE_ADDR + 301*4) +#define EIP0_ARUSER (SYSCFG_BASE_ADDR + 302*4) +#define EIP1_AWUSER (SYSCFG_BASE_ADDR + 303*4) +#define EIP1_WUSER (SYSCFG_BASE_ADDR + 304*4) +#define EIP1_ARUSER (SYSCFG_BASE_ADDR + 305*4) +#define EIP0_QOS (SYSCFG_BASE_ADDR + 306*4) +#define EIP1_QOS (SYSCFG_BASE_ADDR + 307*4) +#define SYSCTRL_REG4 (SYSCFG_BASE_ADDR + 308*4) +#define SYSCTRL_REG5 (SYSCFG_BASE_ADDR + 309*4) +#define SYSCTRL_REG6 (SYSCFG_BASE_ADDR + 310*4) +#define SYSCTRL_REG7 (SYSCFG_BASE_ADDR + 311*4) + +#define APC0_INT_STATUS0 (SYSCFG_BASE_ADDR + 312*4) +#define APC0_INT_STATUS1 (SYSCFG_BASE_ADDR + 313*4) +#define APC0_INT_STATUS2 (SYSCFG_BASE_ADDR + 314*4) +#define APC0_INT_STATUS3 (SYSCFG_BASE_ADDR + 315*4) +#define APC0_INT_STATUS4 (SYSCFG_BASE_ADDR + 316*4) +#define APC0_INT_STATUS5 (SYSCFG_BASE_ADDR + 317*4) +#define APC0_INT_STATUS6 (SYSCFG_BASE_ADDR + 318*4) +#define APC0_INT_STATUS7 (SYSCFG_BASE_ADDR + 319*4) +#define APC0_INT_STATUS8 (SYSCFG_BASE_ADDR + 320*4) +#define APC0_INT_STATUS9 (SYSCFG_BASE_ADDR + 321*4) +#define APC0_INT_STATUS10 (SYSCFG_BASE_ADDR + 322*4) +#define APC0_INT_STATUS11 (SYSCFG_BASE_ADDR + 323*4) +#define APC0_INT_STATUS12 (SYSCFG_BASE_ADDR + 324*4) +#define APC0_INT_STATUS13 (SYSCFG_BASE_ADDR + 325*4) +#define APC0_INT_STATUS14 (SYSCFG_BASE_ADDR + 326*4) +#define APC0_INT_STATUS15 (SYSCFG_BASE_ADDR + 327*4) +#define APC1_INT_STATUS0 (SYSCFG_BASE_ADDR + 328*4) +#define APC1_INT_STATUS1 (SYSCFG_BASE_ADDR + 329*4) +#define APC1_INT_STATUS2 (SYSCFG_BASE_ADDR + 330*4) +#define APC1_INT_STATUS3 (SYSCFG_BASE_ADDR + 331*4) +#define APC1_INT_STATUS4 (SYSCFG_BASE_ADDR + 332*4) +#define APC1_INT_STATUS5 (SYSCFG_BASE_ADDR + 333*4) +#define APC1_INT_STATUS6 (SYSCFG_BASE_ADDR + 334*4) +#define APC1_INT_STATUS7 (SYSCFG_BASE_ADDR + 335*4) +#define APC1_INT_STATUS8 (SYSCFG_BASE_ADDR + 336*4) +#define APC1_INT_STATUS9 (SYSCFG_BASE_ADDR + 337*4) +#define APC1_INT_STATUS10 (SYSCFG_BASE_ADDR + 338*4) +#define APC1_INT_STATUS11 (SYSCFG_BASE_ADDR + 339*4) +#define APC1_INT_STATUS12 (SYSCFG_BASE_ADDR + 340*4) +#define APC1_INT_STATUS13 (SYSCFG_BASE_ADDR + 341*4) +#define APC1_INT_STATUS14 (SYSCFG_BASE_ADDR + 342*4) +#define APC1_INT_STATUS15 (SYSCFG_BASE_ADDR + 343*4) +#define APC2_INT_STATUS0 (SYSCFG_BASE_ADDR + 344*4) +#define APC2_INT_STATUS1 (SYSCFG_BASE_ADDR + 345*4) +#define APC2_INT_STATUS2 (SYSCFG_BASE_ADDR + 346*4) +#define APC2_INT_STATUS3 (SYSCFG_BASE_ADDR + 347*4) +#define APC2_INT_STATUS4 (SYSCFG_BASE_ADDR + 348*4) +#define APC2_INT_STATUS5 (SYSCFG_BASE_ADDR + 349*4) +#define APC2_INT_STATUS6 (SYSCFG_BASE_ADDR + 350*4) +#define APC2_INT_STATUS7 (SYSCFG_BASE_ADDR + 351*4) +#define APC2_INT_STATUS8 (SYSCFG_BASE_ADDR + 352*4) +#define APC2_INT_STATUS9 (SYSCFG_BASE_ADDR + 353*4) +#define APC2_INT_STATUS10 (SYSCFG_BASE_ADDR + 354*4) +#define APC2_INT_STATUS11 (SYSCFG_BASE_ADDR + 355*4) +#define APC2_INT_STATUS12 (SYSCFG_BASE_ADDR + 356*4) +#define APC2_INT_STATUS13 (SYSCFG_BASE_ADDR + 357*4) +#define APC2_INT_STATUS14 (SYSCFG_BASE_ADDR + 358*4) +#define APC2_INT_STATUS15 (SYSCFG_BASE_ADDR + 359*4) +#define APC3_INT_STATUS0 (SYSCFG_BASE_ADDR + 360*4) +#define APC3_INT_STATUS1 (SYSCFG_BASE_ADDR + 361*4) +#define APC3_INT_STATUS2 (SYSCFG_BASE_ADDR + 362*4) +#define APC3_INT_STATUS3 (SYSCFG_BASE_ADDR + 363*4) +#define APC3_INT_STATUS4 (SYSCFG_BASE_ADDR + 364*4) +#define APC3_INT_STATUS5 (SYSCFG_BASE_ADDR + 365*4) +#define APC3_INT_STATUS6 (SYSCFG_BASE_ADDR + 366*4) +#define APC3_INT_STATUS7 (SYSCFG_BASE_ADDR + 367*4) +#define APC3_INT_STATUS8 (SYSCFG_BASE_ADDR + 368*4) +#define APC3_INT_STATUS9 (SYSCFG_BASE_ADDR + 369*4) +#define APC3_INT_STATUS10 (SYSCFG_BASE_ADDR + 370*4) +#define APC3_INT_STATUS11 (SYSCFG_BASE_ADDR + 371*4) +#define APC3_INT_STATUS12 (SYSCFG_BASE_ADDR + 372*4) +#define APC3_INT_STATUS13 (SYSCFG_BASE_ADDR + 373*4) +#define APC3_INT_STATUS14 (SYSCFG_BASE_ADDR + 374*4) +#define APC3_INT_STATUS15 (SYSCFG_BASE_ADDR + 375*4) +#define HSMA_QOS_CTRL (SYSCFG_BASE_ADDR + 376*4) +#define HSMA_QOS0 (SYSCFG_BASE_ADDR + 377*4) +#define HSMA_QOS1 (SYSCFG_BASE_ADDR + 378*4) +#define HSMA_QOS2 (SYSCFG_BASE_ADDR + 379*4) + +//SYSDBG +#define SYSCNT0_BASE_ADDR 0x02110000 +#define CNTCR (SYSCNT0_BASE_ADDR + 0x00*4) +#define CNTSR (SYSCNT0_BASE_ADDR + 0x04*4) +#define CNTCVL (SYSCNT0_BASE_ADDR + 0x08*4) +#define CNTCVU (SYSCNT0_BASE_ADDR + 0x0C*4) +#define CNTFID0 (SYSCNT0_BASE_ADDR + 0x20*4) +#define CNT0CR (SYSCNT0_BASE_ADDR + 0x00*4) +#define CNT0SR (SYSCNT0_BASE_ADDR + 0x04*4) +#define CNT0CVL (SYSCNT0_BASE_ADDR + 0x08*4) +#define CNT0CVU (SYSCNT0_BASE_ADDR + 0x0C*4) +#define CNT0FID0 (SYSCNT0_BASE_ADDR + 0x20*4) + +#define SYSCNT1_BASE_ADDR 0x02110000 +#define CNT1CR (SYSCNT1_BASE_ADDR + 0x00*4) +#define CNT1SR (SYSCNT1_BASE_ADDR + 0x04*4) +#define CNT1CVL (SYSCNT1_BASE_ADDR + 0x08*4) +#define CNT1CVU (SYSCNT1_BASE_ADDR + 0x0C*4) +#define CNT1FID0 (SYSCNT1_BASE_ADDR + 0x20*4) + +#define EIP0_BASE 0X01060000 +#define EIP1_BASE 0X01260000 +#define EIP2_BASE 0X08760000 + +#define C2UVM_FLAG (CPSM_BASE + 0x1FF00 ) +#define UVM2C_FLAG (CPSM_BASE + 0x1FF04 ) +#define SIMULATION_END (CPSM_BASE + 0x1FF08 ) +#define APE_FLAG (CPSM_BASE + 0x1FF0C ) +#define TUBE_C (CPSM_BASE + 0x1FF20 ) +#define RNG_VALUE (CPSM_BASE + 0x1FF10 ) +#define ECC_VALUE (CPSM_BASE + 0x1FF14 ) +#define FAST_DDR (CPSM_BASE + 0x1FF18 ) +#define POST_SIM_FLAG (CPSM_BASE + 0x1FF1C ) + +#define C2UVM_FLAG_RFM (SM5_BASE + 0x0017FF00 + 0x00 ) +#define UVM2C_FLAG_RFM (SM5_BASE + 0x0017FF00 + 0x04 ) +#define SIMULATION_END_RFM (SM5_BASE + 0x0017FF00 + 0x08 ) + +#endif diff --git a/driver/rfic/ucp/base/src/ucp_jesd.c b/driver/rfic/ucp/base/src/ucp_jesd.c new file mode 100644 index 0000000..2528b94 --- /dev/null +++ b/driver/rfic/ucp/base/src/ucp_jesd.c @@ -0,0 +1,2218 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_jesd_core.c +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2022-09-08 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +// 1.js_ctrl(lvds & js_subctrl) -> 2.js_crg -> 3.jesd_subctrl -> +// 4.phyPcsPma -> 5.jesd204B/C -> +// 6.jesd_timer(cp) -> 7.jesd_csu(cp) -> +// 8.pinmux & gpio + +#include "ucp_param.h" +#include "csu.h" +#include +#include +#include +#include +#include +#include +#include "jesd204.h" +#include "ucp_pma.h" +#include "ucp_js_subcrg.h" +#include "ucp_js_ctrl.h" +#include "ucp_reg_io.h" +#include "ucp_api_jesd.h" +#include "ucp_jsonTools.h" +#include "ucp_hardware.h" + +#define JS_204B_RX0_CODING_T 0 +#define JS_204B_RX0_SUBCLASS 1 +#define JS_204B_RX0_CF 0 +#define JS_204B_RX0_CS 0 +#define JS_204B_RX0_F 8 +#define JS_204B_RX0_K 32 +#define JS_204B_RX0_L 1 +#define JS_204B_RX0_N 16 +#define JS_204B_RX0_M 4 +#define JS_204B_RX0_NTOTAL 16 +#define JS_204B_RX0_S 1 +#define JS_204B_RX0_SONI 1 +#define JS_204B_RX0_HD 0 +#define JS_204B_RX0_SCR 1 +#define JS_204B_RX0_E 1 +#define JS_204B_RX0_FEC 0 +#define JS_204B_RX0_CRC3 0 +#define JS_204B_RX0_CRC12 0 + +#define JS_204B_RX1_CODING_T 0 +#define JS_204B_RX1_SUBCLASS 1 +#define JS_204B_RX1_CF 0 +#define JS_204B_RX1_CS 0 +#define JS_204B_RX1_F 8 +#define JS_204B_RX1_K 32 +#define JS_204B_RX1_L 1 +#define JS_204B_RX1_N 16 +#define JS_204B_RX1_M 4 +#define JS_204B_RX1_NTOTAL 16 +#define JS_204B_RX1_S 1 +#define JS_204B_RX1_SONI 1 +#define JS_204B_RX1_HD 0 +#define JS_204B_RX1_SCR 1 +#define JS_204B_RX1_E 1 +#define JS_204B_RX1_FEC 0 +#define JS_204B_RX1_CRC3 0 +#define JS_204B_RX1_CRC12 0 + +#define JS_204B_TX_CODING_T 0 +#define JS_204B_TX_SUBCLASS 1 +#define JS_204B_TX_CF 0 +#define JS_204B_TX_CS 0 +#define JS_204B_TX_F 8 +#define JS_204B_TX_K 32 +#define JS_204B_TX_L 1 +#define JS_204B_TX_N 16 +#define JS_204B_TX_M 4 +#define JS_204B_TX_NTOTAL 16 +#define JS_204B_TX_S 1 +#define JS_204B_TX_SONI 1 +#define JS_204B_TX_HD 0 +#define JS_204B_TX_SCR 1 +#define JS_204B_TX_E 1 +#define JS_204B_TX_FEC 0 +#define JS_204B_TX_CRC3 0 +#define JS_204B_TX_CRC12 0 + +#define UCP_OPT_SKIP 0 +#define UCP_OPT_W 1 +#define UCP_OPT_ANDW 2 +#define UCP_OPT_ORW 3 + +typedef struct tUcpAutoConfigPara { + uint32_t addr; + uint32_t value; + uint32_t opt; + uint32_t step; +} tUcpAutoConfigPara_t; + +enum { + SAMPLE_FACTOR_1_1 = 0, + SAMPLE_FACTOR_1_2 +}; + +#define UCP_PLL_FACT 2 // range: 2/4/8 +#define GetL(byte) (((BIT3 & byte) >> 3) + ((BIT2 & byte) >> 2) + ((BIT1 & byte) >> 1) + (BIT0 & byte)) +#define PrintUcpReg(reg) {printf("register: "); printf("(0x%08X, 0x%08X) // ", reg, ucp_reg32_read(reg)); printf(#reg); printf("\n");} + +static uint64_t frameLaneRate, deframe0LaneRate, deframe1LaneRate; +static uint32_t pllFactor, sampleFactor[4]; +static uint32_t cal_lmfc_lemc_delay(uint32_t coding_type, uint32_t f, uint32_t k, uint32_t e); +static uint32_t cal_ratio(uint32_t mode, uint32_t no_converters, uint32_t no_samples, uint32_t ntotal, uint32_t no_frames, uint32_t no_lanes, uint32_t no_samples_on_if); +extern int pma_fw[16384*2]; + +static tUcpAutoConfigPara_t ucpCrgConfig[44] = { + {0x05F10120, 0x00000000, UCP_OPT_W, 0}, //00 JS_CRG_TMR_EN_SAM_CLK_SEL + {0x05F10000, 0x00802A00, UCP_OPT_W, 0}, //01 JS_CRG_CLK_SEL + {0x05F10004, 0x0000002A, UCP_OPT_W, 0}, //02 JS_CRG_DPLL0_CTRL_0 + {0x05F10008, 0x00000000, UCP_OPT_W, 0}, //03 JS_CRG_DPLL0_CTRL_1 + {0x05F10014, 0x00400000, UCP_OPT_W, 0}, //04 JS_CRG_SAM0_CLK_CTRL + {0x05F10018, 0x00400000, UCP_OPT_W, 0}, //05 JS_CRG_SAM1_CLK_CTRL + {0x05F1001C, 0x00401000, UCP_OPT_W, 0}, //06 JS_CRG_SAM2_CLK_CTRL + {0x05F1002C, 0x00401000, UCP_OPT_W, 0}, //07 JS_CRG_SAM3_CLK_CTRL + {0x05F10020, 0x00400000, UCP_OPT_W, 0}, //08 JS_CRG_CHA0_CLK_CTRL + {0x05F10024, 0x00400000, UCP_OPT_W, 0}, //09 JS_CRG_CHA1_CLK_CTRL + {0x05F10028, 0x00400000, UCP_OPT_W, 0}, //10 JS_CRG_CHA2_CLK_CTRL + {0x05F10090, 0x00400000, UCP_OPT_W, 0}, //11 JS_CRG_CHA3_CLK_CTRL + {0x05F10108, 0x0503F007, UCP_OPT_W, 0}, //12 JS_CRG_SAM_CHA0_RST_CTRL + {0x05F1010C, 0x0503F007, UCP_OPT_W, 0}, //13 JS_CRG_SAM_CHA1_RST_CTRL + {0x05F10110, 0x0503F007, UCP_OPT_W, 0}, //14 JS_CRG_SAM_CHA2_RST_CTRL + {0x05F10114, 0x0503F007, UCP_OPT_W, 0}, //15 JS_CRG_SAM_CHA3_RST_CTRL + {0x05F10118, 0x0503F007, UCP_OPT_W, 0}, //16 JS_CRG_SAM_CHA4_RST_CTRL + {0x05F1011C, 0x0503F007, UCP_OPT_W, 0}, //17 JS_CRG_SAM_CHA5_RST_CTRL + {0x05F10094, 0x0503F007, UCP_OPT_W, 0}, //18 JS_CRG_SAM_CHA6_RST_CTRL + {0x05F10098, 0x0503F007, UCP_OPT_W, 0}, //19 JS_CRG_SAM_CHA7_RST_CTRL + {0x05F10038, 0x0503F007, UCP_OPT_W, 0}, //20 JS_CRG_JESD0_TIME_CTRL + {0x05F1003C, 0x0503F007, UCP_OPT_W, 0}, //21 JS_CRG_JESD1_TIME_CTRL + {0x05F10040, 0x0503F007, UCP_OPT_W, 0}, //22 JS_CRG_JESD2_TIME_CTRL + {0x05F10044, 0x0503F007, UCP_OPT_W, 0}, //23 JS_CRG_JESD3_TIME_CTRL + {0x05F10048, 0x0503F007, UCP_OPT_W, 0}, //24 JS_CRG_JESD4_TIME_CTRL + {0x05F1004C, 0x0503F007, UCP_OPT_W, 0}, //25 JS_CRG_JESD5_TIME_CTRL + {0x05F10050, 0x0503F007, UCP_OPT_W, 0}, //26 JS_CRG_JESD6_TIME_CTRL + {0x05F10054, 0x0503F007, UCP_OPT_W, 0}, //27 JS_CRG_JESD7_TIME_CTRL + {0x05F10070, 0x05F00807, UCP_OPT_W, 0}, //28 JS_CRG_PHY_TX_RSTN_JS_CTRL_0 + {0x05F10074, 0x05F00807, UCP_OPT_W, 0}, //29 JS_CRG_PHY_TX_RSTN_JS_CTRL_1 + {0x05F10078, 0x05F00807, UCP_OPT_W, 0}, //30 JS_CRG_PHY_TX_RSTN_JS_CTRL_2 + {0x05F1007C, 0x05F00807, UCP_OPT_W, 0}, //31 JS_CRG_PHY_TX_RSTN_JS_CTRL_3 + {0x05F10080, 0x05F00807, UCP_OPT_W, 0}, //32 JS_CRG_PHY_RX_RSTN_JS_CTRL_0 + {0x05F10084, 0x05F00807, UCP_OPT_W, 0}, //33 JS_CRG_PHY_RX_RSTN_JS_CTRL_1 + {0x05F10088, 0x05F00807, UCP_OPT_W, 0}, //34 JS_CRG_PHY_RX_RSTN_JS_CTRL_2 + {0x05F1008C, 0x05F00807, UCP_OPT_W, 0}, //35 JS_CRG_PHY_RX_RSTN_JS_CTRL_3 + {0x05F100D8, 0x05F00807, UCP_OPT_W, 0}, //36 JS_CRG_PHY_EQ_RSTN_JS_CTRL_0 + {0x05F100DC, 0x05F00807, UCP_OPT_W, 0}, //37 JS_CRG_PHY_EQ_RSTN_JS_CTRL_1 + {0x05F100E0, 0x05F00807, UCP_OPT_W, 0}, //38 JS_CRG_PHY_EQ_RSTN_JS_CTRL_2 + {0x05F100E4, 0x05F00807, UCP_OPT_W, 0}, //39 JS_CRG_PHY_EQ_RSTN_JS_CTRL_3 + {0x05F100F8, 0x05F00807, UCP_OPT_W, 0}, //40 JS_CRG_PHY_PWR_ON_RST_JS_CTRL + {0x05F10030, 0x00000004, UCP_OPT_SKIP, 0}, //41 JS_CRG_DPLL_PMA_CTRL + {0x05F10120, 0x00000000, UCP_OPT_SKIP, 0}, //42 JS_CRG_TMR_EN_SAM_CLK_SEL + {0x05F10120, 0x00000080, UCP_OPT_W, 1} //43 JS_CRG_TMR_EN_SAM_CLK_SEL +}; + +static tUcpAutoConfigPara_t ucpPmaConfig[80] = +{ + {0x05FC40C4, 0x00000001, UCP_OPT_W, 0}, //00 JS_PMA0_PHY_RESET + {0x05FD4088, 0x00000011, UCP_OPT_W, 0}, //01 JS_PMA0_PCS_BIT_REV_CTRL + {0x05FC41A0, 0x00000101, UCP_OPT_W, 0}, //02 JS_PMA0_SRAM_CTRL + {0x05FC43C0, 0x00000002, UCP_OPT_W, 0}, //03 JS_PMA0_TX_CLK_SEL + {0x05FC4108, 0x00000040, UCP_OPT_W, 0}, //04 JS_PMA0_REFA_CLK_CTRL2 + {0x05FC4100, 0x00001111, UCP_OPT_W, 0}, //05 JS_PMA0_REF_CLK_CTRL + {0x05FC4014, 0x00000000, UCP_OPT_W, 0}, //06 JS_PMA0_MPLLA_PARAM6 + {0x05FC400C, 0x000000B4, UCP_OPT_W, 0}, //07 JS_PMA0_MPLLA_PARAM4 + {0x05FC4010, 0x00000110, UCP_OPT_W, 0}, //08 JS_PMA0_MPLLA_PARAM5 + {0x05FC406C, 0x00000000, UCP_OPT_W, 0}, //09 JS_PMA0_MPLLA_SSC_CTRL1 + {0x05FC4078, 0x00000000, UCP_OPT_W, 0}, //10 JS_PMA0_MPLLA_SSC_CTRL4 + {0x05FC4070, 0x00000000, UCP_OPT_W, 0}, //11 JS_PMA0_MPLLA_SSC_CTRL2 + {0x05FC4074, 0x00000000, UCP_OPT_W, 0}, //12 JS_PMA0_MPLLA_SSC_CTRL3 + {0x05FC407C, 0x00000000, UCP_OPT_W, 0}, //13 JS_PMA0_MPLLA_SSC_CTRL5 + {0x05FC4080, 0x00000000, UCP_OPT_W, 0}, //14 JS_PMA0_MPLLA_SSC_CTRL6 + {0x05FC4060, 0x00000000, UCP_OPT_W, 0}, //15 JS_PMA0_MPLLA_FRAC_CTRL2 + {0x05FC4064, 0x00000000, UCP_OPT_W, 0}, //16 JS_PMA0_MPLLA_FRAC_CTRL3 + {0x05FC405C, 0x00000000, UCP_OPT_W, 0}, //17 JS_PMA0_MPLLA_FRAC_CTRL1 + {0x05FC4068, 0x00000000, UCP_OPT_W, 0}, //18 JS_PMA0_MPLLA_FRAC_CTRL4 + {0x05FC4008, 0x0000004B, UCP_OPT_W, 0}, //19 JS_PMA0_MPLLA_PARAM3 + {0x05FC4004, 0x0000063F, UCP_OPT_W, 0}, //20 JS_PMA0_MPLLA_PARAM2 + {0x05FC4000, 0x0000063F, UCP_OPT_W, 0}, //21 JS_PMA0_MPLLA_PARAM1 + {0x05F50050, 0x000002D0, UCP_OPT_W, 0}, //22 JS_PHY_BS_CTRL + {0x05FC4158, 0x00000000, UCP_OPT_W, 0}, //23 JS_PMA0_RTUNE_CTRL1 + {0x05FC415C, 0x00000000, UCP_OPT_W, 0}, //24 JS_PMA0_RTUNE_CTRL2 + {0x05FC4160, 0x00000000, UCP_OPT_W, 0}, //25 JS_PMA0_RTUNE_CTRL3 + {0x05FC4058, 0x00000003, UCP_OPT_W, 0}, //26 JS_PMA0_SUP_MISC + {0x05FC4164, 0x00000005, UCP_OPT_W, 0}, //27 JS_PMA0_RX_BIAS_CURRENT_CTRL + {0x05FBC280, 0x00000000, UCP_OPT_W, 0}, //28 JS_PMA0_BROADCAST_LANE_REFCLK_SEL + {0x05FBC024, 0x00000550, UCP_OPT_W, 0}, //29 JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM8 + {0x05FBC084, 0x00000012, UCP_OPT_W, 0}, //30 JS_PMA0_BROADCAST_RECEIVER_DATAPATH_SETTING1 + {0x05FBC1C4, 0x00000000, UCP_OPT_W, 0}, //31 JS_PMA0_BROADCAST_TRANSMITTER_CONTROL2 + {0x05FBC340, 0x00000088, UCP_OPT_W, 0}, //32 JS_PMA0_BROADCAST_TRANS_REQ_CTRL1 + {0x05FBC14C, 0x00000052, UCP_OPT_W, 0}, //33 JS_PMA0_BROADCAST_TRANSMITTER_REQ_PARAM2 + {0x05FBC344, 0x00005B5B, UCP_OPT_W, 0}, //34 JS_PMA0_BROADCAST_TRANS_REQ_CTRL2 + {0x05FBC34C, 0x0000C941, UCP_OPT_W, 0}, //35 JS_PMA0_BROADCAST_TRANS_REQ_CTRL4 + {0x05FBC350, 0x00000133, UCP_OPT_W, 0}, //36 JS_PMA0_BROADCAST_TRANS_REQ_CTRL5 + {0x05FBC2C0, 0x00004000, UCP_OPT_W, 0}, //37 JS_PMA0_BROADCAST_ETH_CLK_CTRL + {0x05FBC358, 0x00000000, UCP_OPT_W, 0}, //38 JS_PMA0_BROADCAST_TRANS_INTERFACE_CTRL + {0x05FBC32C, 0x00000000, UCP_OPT_W, 0}, //39 JS_PMA0_BROADCAST_TX_DIV_CLK_CTRL + {0x05FBC248, 0x00000000, UCP_OPT_W, 0}, //40 JS_PMA0_BROADCAST_CONTEXT_RESTORE_CTRL3 + {0x05FBC348, 0x00000410, UCP_OPT_W, 0}, //41 JS_PMA0_BROADCAST_TRANS_REQ_CTRL3 + {0x05FBC188, 0x00000000, UCP_OPT_W, 0}, //42 JS_PMA0_BROADCAST_TRANSMITTER_DATAPATH_SETTING + {0x05FBC010, 0x00000050, UCP_OPT_W, 0}, //43 JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM3 + {0x05FBC014, 0x00000110, UCP_OPT_W, 0}, //44 JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM4 + {0x05FBC30C, 0x00001080, UCP_OPT_W, 0}, //45 JS_PMA0_BROADCAST_RX_EQ_CTRL2 + {0x05FBC308, 0x0000014C, UCP_OPT_W, 0}, //46 JS_PMA0_BROADCAST_RX_EQ_CTRL1 + {0x05FBC018, 0x00000000, UCP_OPT_W, 0}, //47 JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM5 + {0x05FBC00C, 0x00000423, UCP_OPT_W, 0}, //48 JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM2 + {0x05FBC304, 0x000000BB, UCP_OPT_W, 0}, //49 JS_PMA0_BROADCAST_RX_DCC_CTRL + {0x05FBC088, 0x00004200, UCP_OPT_W, 0}, //50 JS_PMA0_BROADCAST_RECEIVER_DATAPATH_SETTING2 + {0x05FBC01C, 0x00000000, UCP_OPT_W, 0}, //51 JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM6 + {0x05FBC0C4, 0x00000121, UCP_OPT_W, 0}, //52 JS_PMA0_BROADCAST_RECEIVER_CONTROL + {0x05FBC028, 0x00000005, UCP_OPT_W, 0}, //53 JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM9 + {0x05FBC328, 0x00000000, UCP_OPT_W, 0}, //54 JS_PMA0_BROADCAST_RX_DIV_CLK_CTRL + {0x05FBC04C, 0x00000141, UCP_OPT_W, 0}, //55 JS_PMA0_BROADCAST_RECEIVER_ADAPT_SETTING + {0x05FBC08C, 0x00000000, UCP_OPT_W, 0}, //56 JS_PMA0_BROADCAST_RECEIVER_DATAPATH_SETTING3 + {0x05FBC300, 0x00000000, UCP_OPT_W, 0}, //57 JS_PMA0_BROADCAST_RX_ADAPT_CTRL + {0x05FBC200, 0x00000018, UCP_OPT_W, 0}, //58 JS_PMA0_BROADCAST_TRANSMITTER_EQ1 + {0x05FBC204, 0x00000000, UCP_OPT_W, 0}, //59 JS_PMA0_BROADCAST_TRANSMITTER_EQ2 + {0x05FBC208, 0x00000000, UCP_OPT_W, 0}, //60 JS_PMA0_BROADCAST_TRANSMITTER_EQ3 + {0x05FC40C4, 0x00000000, UCP_OPT_W, 0}, //61 JS_PMA0_PHY_RESET + {0x05FC4104, 0x00000110, UCP_OPT_W, 0}, //62 JS_PMA0_REFA_CLK_CTRL1 + {0x05FBC1C0, 0x00000000, UCP_OPT_W, 1}, //63 JS_PMA0_BROADCAST_TRANSMITTER_CONTROL1 + {0x05FBC0C0, 0x00000000, UCP_OPT_W, 1}, //64 JS_PMA0_BROADCAST_RECEIVER_RESET + {0x05FBC148, 0x00000200, UCP_OPT_W, 2}, //65 JS_PMA0_BROADCAST_TRANSMITTER_REQ_PARAM1 + {0x05FBC020, 0x00001112, UCP_OPT_W, 2}, //66 JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM7 + {0x05FBC140, 0x00000001, UCP_OPT_W, 2}, //67 JS_PMA0_BROADCAST_TRANSMITTER_REQ + {0x05FBC004, 0x00000001, UCP_OPT_W, 2}, //68 JS_PMA0_BROADCAST_RECEIVER_REQ + {0x05FBC140, 0x00000000, UCP_OPT_W, 3}, //69 JS_PMA0_BROADCAST_TRANSMITTER_REQ + {0x05FBC004, 0x00000000, UCP_OPT_W, 3}, //70 JS_PMA0_BROADCAST_RECEIVER_REQ + {0x05FBC020, 0x00001110, UCP_OPT_W, 4}, //71 JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM7 + {0x05FBC148, 0x00000010, UCP_OPT_W, 4}, //72 JS_PMA0_BROADCAST_TRANSMITTER_REQ_PARAM1 + {0x05FBC184, 0x00000001, UCP_OPT_W, 4}, //73 JS_PMA0_BROADCAST_TRANSMITTER_DATAPATH_CLKRDY + {0x05FBC140, 0x00000001, UCP_OPT_W, 4}, //74 JS_PMA0_BROADCAST_TRANSMITTER_REQ + {0x05FBC004, 0x00000001, UCP_OPT_W, 4}, //75 JS_PMA0_BROADCAST_RECEIVER_REQ + {0x05FBC140, 0x00000000, UCP_OPT_W, 5}, //76 JS_PMA0_BROADCAST_TRANSMITTER_REQ + {0x05FBC004, 0x00000000, UCP_OPT_W, 5}, //77 JS_PMA0_BROADCAST_RECEIVER_REQ + {0x05FBC180, 0x00000001, UCP_OPT_W, 6}, //78 JS_PMA0_BROADCAST_TRANSMITTER_DATAPATH_EN + {0x05FBC080, 0x00000001, UCP_OPT_W, 6} //79 JS_PMA0_BROADCAST_RECEIVER_DATAPATH_EN +}; + +static void js_csu_loc_cfg(uint32_t all); +static void js_csu_glb_cfg(uint64_t addr, uint32_t all, uint32_t id); +static void js_csu_glb_cfg_sep(uint64_t addr, uint32_t all, uint32_t id, uint32_t sep_num, uint32_t sep_margin); + +void ucp4008_jesd_js_ctrl_init (void); +void ucp4008_jesd_crg_init (ucp_jesd_Init_t *setting); +void ucp4008_jesd_subctrl_init (ucp_jesd_Init_t *setting); +void ucp4008_jesd_pma_init (ucp_jesd_Init_t *setting); +void ucp4008_jesd204b_init(ucp_jesd_Init_t *setting); +void ucp4008_jesd204c_init(ucp_jesd_Init_t *setting); +void ucp4008_jesd_timer_init (void); +void ucp4008_jesd204b_bringup (void); + +static void ucp4008_jesd_calLarate (ucp_jesd_Init_t *setting); +static void ucp4008_autoStepConfig (tUcpAutoConfigPara_t *para, uint32_t step, uint32_t size); +static void ucp4008_jesd_crg_print (void); +static void ucp4008_jesd_pma_print (void); + +void ucp_jesd_init(ucp_jesd_Init_t *setting) +{ + ucp4008_jesd_calLarate(setting); + ucp4008_jesd_js_ctrl_init(); + ucp4008_jesd_crg_init(setting); + ucp4008_jesd_subctrl_init(setting); + if (0 == setting->common.enableJesd204C) + { + ucp4008_jesd204b_init(setting); + } + else + { + ucp4008_jesd204c_init(setting); + } + ucp4008_jesd_pma_init(setting); + ucp4008_jesd_timer_init(); + ucp4008_jesd204b_bringup(); + + return; +} + +void ucp4008_jesd_js_ctrl_init (void) +{ + ucp_jesd_TrxGpioCfg_t *pTrxGpioCfg; + + pTrxGpioCfg = UCP_API_JESD_TrxGpioGet(); + + //---------------------- Config JS-CTRL --------------------- + // + // bit[ 8]: o_jesda_rx1_sync + // bit[ 7]: o_jesda_rx0_sync + // bit[ 6]: i_jesda_tx_sync + // bit[ 5]: i_jesd_tx_sysref + // bit[ 4]: i_jesd_rx1_sysref + // bit[ 3]: i_jesd_rx0_sysref + // bit[ 2]: i_jesd_tx_dev_clk + // bit[ 1]: i_jesd_rx1_dev_clk + // bit[ 0]: i_jesd_rx0_dev_clk + ucp_reg32_write(JS_CTRL_LVDS_BIAS_EN, 0x1FF); + ucp_reg32_write(JS_CTRL_LVDS_VBIAS_SEL, 0x1FF); + ucp_reg32_write(JS_CTRL_LVDS_PULLDN, 0x000); + ucp_reg32_write(JS_CTRL_LVDS_SCHMITT_EN, 0x000); + ucp_reg32_write(JS_CTRL_LVDS_RTERM_EN, 0x07F); + ucp_reg32_write(JS_CTRL_LVDS_RTERM_VAL_0, 0xDB6DB); + ucp_reg32_write(JS_CTRL_LVDS_RTERM_VAL_1, 0x000); + ucp_reg32_write(JS_CTRL_LVDS_RTERM_VAL_2, 0x000); + ucp_reg32_write(JS_CTRL_LVDS_RTERM_VAL_3, 0x000); + if (pTrxGpioCfg->version > 1) + { + printf("%s-coupled: ", pTrxGpioCfg->lvdsCoupling); + if ('D' == pTrxGpioCfg->lvdsCoupling[0]) + { + ucp_reg32_write(JS_CTRL_LVDS_RXCM_EN, 0x000); // dc-coupled disable cm + printf("lvds CM disable\n"); + } + else if ('A' == pTrxGpioCfg->lvdsCoupling[0]) + { + ucp_reg32_write(JS_CTRL_LVDS_RXCM_EN, 0x07F); // ac-coupled enable cm + printf("lvds CM enable\n"); + } + else + { + ucp_reg32_write(JS_CTRL_LVDS_RXCM_EN, 0x07F); // unknown-coupled enable cm + printf("** unknown-coupled, lvds CM enable\n"); + } + } + else + { + ucp_reg32_write(JS_CTRL_LVDS_RXCM_EN, 0x07F); // enable cm + } + ucp_reg32_write(JS_CTRL_LVDS_RXEN, 0x07F); + ucp_reg32_write(JS_CTRL_LVDS_TXDRV_0, 0x50000000); + ucp_reg32_write(JS_CTRL_LVDS_TXDRV_1, 0x005); + ucp_reg32_write(JS_CTRL_LVDS_TXDRV_2, 0x000); + ucp_reg32_write(JS_CTRL_LVDS_TXDRV_3, 0x000); + ucp_reg32_write(JS_CTRL_LVDS_TXEN, 0x180); + ucp_reg32_write(JS_CTRL_LVDS_TX_CM, 0x180); + + // PCS Protocol Sel + // phy_protocol_sel_sub0 <= pwdata_s10_js_subctrl[0]; //0: JESD, 1:SRIO + // phy_protocol_sel_sub1 <= pwdata_s10_js_subctrl[1]; + // phy_out_test_clk_sel <= pwdata_s10_js_subctrl[2]; + // phy_srds_tx_clk_sel_sub0 <= pwdata_s10_js_subctrl[5:3]; + // phy_tx_clk_mode_sub0 <= pwdata_s10_js_subctrl[6]; + // phy_srds_tx_clk_sel_sub1 <= pwdata_s10_js_subctrl[9:7]; + // phy_tx_clk_mode_sub1 <= pwdata_s10_js_subctrl[10]; + ucp_reg32_write(JS_CTRL_PHY_MISC_SEL_0, ucp_reg32_read(JS_CTRL_PHY_MISC_SEL_0) & 0xFFFFFBBC); + + // coding of jesd_mode_sel + // 000:jesd204b TX + jesd204b RX + // 001:jesd204b TX + jesd204b RX + jesd204b ORX + // 010:jesd204c TX + jesd204c RX + // 011:jesd204c TX + jesd204c RX + jesd204c ORX + // 100:jesd204b TX + jesd204c TX + jesd204b RX + jesd204c RX + // jesd-csu data of RX0/RX1/TX0/TX1 + // RX0: RX_204B_L(M=8,N=16,jesdcsu_through_from_204b_rx1) / ORX_204C(M=2,N=24,jesdcsu_through_from_204c_rx0) + // RX1: RX_204B_H(M=8,N=16,jesdcsu_through_from_204b_rx1) / ORX_204B(M=2,N=24,jesdcsu_through_from_204b_rx0) / RX_204C(M=8,N=24,jesdcsu_through_from_204c_rx1) + // TX0: TX_204B_L(M=8,N=16,jesdcsu_through_to_204b_tx0) + // TX1: TX_204B_H(M=8,N=16,jesdcsu_through_to_204b_tx0) / TX_204C(M=8,N=16,jesdcsu_through_to_204c_tx1) + ucp_reg32_write(JS_CTRL_JESD204_MODE_SEL, 0x0); + ucp_reg32_write(JS_SERDES_CLK_EN, 0x1FFF); + + // printf("\033[0;42;31m"); + printf("js_ctrl ok\n"); +} + + + void ucp4008_jesd_crg_init (ucp_jesd_Init_t *setting) + { + uint32_t size; + tUcpAutoConfigPara_t *pConfig; + ucp_jesd_TrxGpioCfg_t *pTrxGpioCfg; + + size = 44; + pConfig = ucpCrgConfig; + pTrxGpioCfg = UCP_API_JESD_TrxGpioGet(); + + // PLL_CLK = refdiv*2^refdiv + // refdiv bit1:bit0, postdiv bit6:bit4 + switch (pllFactor) + { + case 2: // deviceClk*2 + pConfig[2].value = 0x0000002A; + break; + + case 4: // deviceClk*4 + pConfig[2].value = 0x00000026; + break; + + case 8: // deviceClk*8 + pConfig[2].value = 0x00000022; + break; + + default: + printf("Invalid pll divFactor: %d. pllFactor \n", pllFactor); + exit(1); + break; + } + + // SAM_div CHA_div bit16:bit22 为 (N+1) 分频 + if (setting->deframer[0].enable) + { + if (1 == sampleFactor[0]) { + pConfig[4].value = 0x00400000; + } else if (2 == sampleFactor[0]) { + pConfig[4].value = 0x00401000; + } else if (4 == sampleFactor[0]) { + pConfig[4].value = 0x00403000; + } else if (8 == sampleFactor[0]) { + pConfig[4].value = 0x00407000; + } else { + printf("Invalid deframer[0] sampleFactor: %d\n", sampleFactor[0]); + exit(1); + } + } + + if (setting->deframer[1].enable) + { + if (1 == sampleFactor[1]) { + pConfig[5].value = 0x00400000; + } else if (2 == sampleFactor[1]) { + pConfig[5].value = 0x00401000; + } else if (4 == sampleFactor[1]) { + pConfig[5].value = 0x00403000; + } else if (8 == sampleFactor[1]) { + pConfig[5].value = 0x00407000; + } else { + printf("Invalid deframer[1] sampleFactor: %d\n", sampleFactor[1]); + exit(1); + } + } + + if (setting->framer.enable) + { + if (1 == sampleFactor[2]) { + pConfig[6].value = 0x00400000; + pConfig[7].value = 0x00400000; + } else if (2 == sampleFactor[2]) { + pConfig[6].value = 0x00401000; + pConfig[7].value = 0x00401000; + } else if (4 == sampleFactor[2]) { + pConfig[6].value = 0x00403000; + pConfig[7].value = 0x00403000; + } else if (8 == sampleFactor[2]) { + pConfig[6].value = 0x00407000; + pConfig[7].value = 0x00407000; + } else { + printf("Invalid framer sampleFactor: %d\n", sampleFactor[2]); + exit(1); + } + } + + + switch (pTrxGpioCfg->devClkSrc) + { + case 1: // src as rx1 devClk + pConfig[1].value = 0x00806A00; + printf("DevClkSrc: Rx1\n"); + break; + case 2: // src as tx devClk + pConfig[1].value = 0x0080AA00; + printf("DevClkSrc: Tx\n"); + break; + default: // src as rx0 devClk + pConfig[1].value = 0x00802A00; + printf("DevClkSrc: Rx0\n"); + break; + } + + ucp4008_autoStepConfig(pConfig, 0, size); + printf("DevClkReg: 0x%04X\n", ucp_reg32_read(0x05F10000)); + + while((ucp_reg32_read(JS_CRG_DPLL_PMA_CTRL) & BIT2) != 0x4); + + ucp4008_autoStepConfig(pConfig, 1, size); + + printf("js_crg ok\n"); +} + +void ucp4008_jesd_subctrl_init (ucp_jesd_Init_t *setting) +{ + uint32_t reg; + ucp_jesd_TrxGpioCfg_t* pTrxGpioCfg; + + //--------------------- Config jesd_subctrl ---------------------- + // sl_MUX2D2 u_sysref_mux0(.S0(sysref_sel[0]),.B(jesd_rx1_sysref ),.A(jesd_rx0_sysref ),.Y(sysref_mux_out[0])); //0:A,1:B + // sl_MUX2D2 u_sysref_mux1(.S0(sysref_sel[1]),.B(sysref_mux_out[0]),.A(jesd_tx_sysref ),.Y(sysref_mux_out[1])); //0:A,1:B + // sl_MUX2D2 u_sysref_mux2(.S0(sysref_sel[2]),.B(sysref_mux_out[1]),.A(jesd_int_sysref ),.Y(sysref_mux_out[2])); //0:A,1:B + // sl_MUX2D2 u_sysref_mux3(.S0(sysref_sel[3]),.B(sysref_mux_out[2]),.A(sysref_pulse_char_rx0_sub0 ),.Y(sysref_mux_out[3])); //0:A,1:B + // sl_MUX2D2 u_sysref_mux4(.S0(sysref_sel[4]),.B(sysref_mux_out[3]),.A(sysref_pulse_char_rx1_sub0 ),.Y(sysref_mux_out[4])); //0:A,1:B + // sl_MUX2D2 u_sysref_mux5(.S0(sysref_sel[5]),.B(sysref_mux_out[4]),.A(sysref_pulse_char_tx_sub0 ),.Y(sysref_mux_out[5])); //0:A,1:B + // sl_MUX2D2 u_sysref_mux6(.S0(sysref_sel[6]),.B(sysref_mux_out[5]),.A(sysref_pulse_char_rx0_sub1 ),.Y(sysref_mux_out[6])); //0:A,1:B + // sl_MUX2D2 u_sysref_mux7(.S0(sysref_sel[7]),.B(sysref_mux_out[6]),.A(sysref_pulse_char_rx1_sub1 ),.Y(sysref_mux_out[7])); //0:A,1:B + // sl_MUX2D2 u_sysref_mux8(.S0(sysref_sel[8]),.B(sysref_mux_out[7]),.A(sysref_pulse_char_tx_sub1 ),.Y(sysref_out )); //0:A,1:B + //#JS_204B_RX0_SUBCTRL_SYSREF_RX_SEL = 0x1FE ; // rx0_sysref + //#JS_204B_RX1_SUBCTRL_SYSREF_RX_SEL = 0x1FF ; // rx1_sysref + //#JS_204B_TX_SUBCTRL_SYSREF_TX_SEL = 0x1FC ; // tx_sysref + pTrxGpioCfg = UCP_API_JESD_TrxGpioGet(); + switch (pTrxGpioCfg->devClkSrc) + { + case 1: // src as rx1 devClk + reg = 0x1FF; + printf("RefClkSrc: Rx1 "); + break; + case 2: // src as tx devClk + reg = 0x1FC; + printf("RefClkSrc: Tx "); + break; + default: // src as rx0 devClk + reg = 0x1FE; + printf("RefClkSrc: Rx0 "); + break; + } + printf("%04X\n", reg); + ucp_reg32_write(JS_204B_RX0_SUBCTRL_SYSREF_RX_SEL, reg); + ucp_reg32_write(JS_204B_RX1_SUBCTRL_SYSREF_RX_SEL, reg); + ucp_reg32_write(JS_204B_TX_SUBCTRL_SYSREF_TX_SEL, reg); + + // sl_MUX2D2 u_sync_b_mux0(.S0(sync_b_o_sel[0]),.B(sync_b_o_rx1_sub0 ),.A(sync_b_o_rx0_sub0 ),.Y(sync_b_o_mux_out[0])); //0:A,1:B + // sl_MUX2D2 u_sync_b_mux1(.S0(sync_b_o_sel[1]),.B(sync_b_o_rx1_sub1 ),.A(sync_b_o_rx0_sub1 ),.Y(sync_b_o_mux_out[1])); //0:A,1:B + // sl_MUX2D2 u_sync_b_mux2(.S0(sync_b_o_sel[2]),.B(sync_b_o_mux_out[1]),.A(sync_b_o_mux_out[0]),.Y(sync_b_o_mux_out[2])); //0:A,1:B + // sl_MUX2D2 u_sync_b_mux3(.S0(sync_b_o_sel[3]),.B(sync_b_o_masked_int),.A(sync_b_o_mux_out[2]),.Y(sync_b_out )); //0:A,1:B + //#JS_204B_RX0_SUBCTRL_SYNC_B_SEL = 0x0 ; // sync_b_o_rx0_sub0 + //#JS_204B_RX1_SUBCTRL_SYNC_B_SEL = 0x1 ; // sync_b_o_rx1_sub0 + ucp_reg32_write(JS_204B_RX0_SUBCTRL_SYNC_B_SEL, 0x01); + ucp_reg32_write(JS_204B_RX1_SUBCTRL_SYNC_B_SEL, 0x01); + + // sl_MUX2D2 u_sync_b_mux0(.S0(sync_b_i_sel[8] ),.B(sync_b_i_sub0[1] ),.A(sync_b_i_sub0[0] ),.Y(sync_b_mux_out[0])); //0:A,1:B + // sl_MUX2D2 u_sync_b_mux1(.S0(sync_b_i_sel[9] ),.B(sync_b_mux_out[0] ),.A(sync_b_i_sub0[2] ),.Y(sync_b_mux_out[1])); //0:A,1:B + // sl_MUX2D2 u_sync_b_mux2(.S0(sync_b_i_sel[10]),.B(sync_b_mux_out[1] ),.A(sync_b_i_sub0[3] ),.Y(sync_b_mux_out[2])); //0:A,1:B + // sl_MUX2D2 u_sync_b_mux3(.S0(sync_b_i_sel[11]),.B(synci_sub0_masked_int),.A(sync_b_mux_out[2]),.Y(sync_b_mux_out[3])); //0:A,1:B + // sl_MUX2D2 u_sync_b_mux4(.S0(sync_b_i_sel[12]),.B(sync_b_i_sub1[1] ),.A(sync_b_i_sub1[0] ),.Y(sync_b_mux_out[4])); //0:A,1:B + // sl_MUX2D2 u_sync_b_mux5(.S0(sync_b_i_sel[13]),.B(sync_b_mux_out[4] ),.A(sync_b_i_sub1[2] ),.Y(sync_b_mux_out[5])); //0:A,1:B + // sl_MUX2D2 u_sync_b_mux6(.S0(sync_b_i_sel[14]),.B(sync_b_mux_out[5] ),.A(sync_b_i_sub1[3] ),.Y(sync_b_mux_out[6])); //0:A,1:B + // sl_MUX2D2 u_sync_b_mux7(.S0(sync_b_i_sel[15]),.B(synci_sub1_masked_int),.A(sync_b_mux_out[6]),.Y(sync_b_mux_out[7])); //0:A,1:B + // sl_MUX2D2 u_sync_b_mux8(.S0(sync_b_i_sel[16]),.B(sync_b_mux_out[7] ),.A(sync_b_mux_out[3]),.Y(sync_b_out) ); //0:A,1:B + //#JS_204B_TX_SUBCTRL_SYNC_B_SEL = 0x6<<8 ; // jesda_tx_sync0 + ucp_reg32_write(JS_204B_TX_SUBCTRL_SYNC_B_SEL, (0x6<<8)); + + // 000: JESD204B TX + RX + // 001: JESD204B TX + RX + ORX + // 010: JESD204C TX + RX + // 011: JESD204C TX + RX + ORX + ucp_reg32_write(JS_CTRL_JESD204_MODE_SEL, 0x01); + + printf("jesd subctrl ok\n"); +} + +void ucp4008_jesd_pma_init (ucp_jesd_Init_t *setting) +{ + uint64_t i; + uint32_t size; + tUcpAutoConfigPara_t *pConfig; + + size = 80; + + pConfig = ucpPmaConfig; + + if (4915200000 == frameLaneRate) { + pConfig[3].value = 0x00000002; + pConfig[33].value = 0x00000052; + pConfig[37].value = 0x00004000; + } else if (9830400000 == frameLaneRate) { + pConfig[3].value = 0x00000001; + pConfig[33].value = 0x00000051; + pConfig[37].value = 0x00006000; + } else if (8110080000 == frameLaneRate) { + pConfig[3].value = 0x00000001; + pConfig[33].value = 0x00000051; + pConfig[37].value = 0x00006000; + }else { + exit(1); + } + + if (4915200000 == deframe0LaneRate) { + pConfig[43].value = 0x00000061; + pConfig[44].value = 0x0000010C; + pConfig[46].value = 0x00000514; + pConfig[55].value = 0x00000101; + pConfig[66].value = 0x00001122; + pConfig[71].value = 0x00001120; + } else if (9830400000 == deframe0LaneRate) { + pConfig[43].value = 0x00000050; + pConfig[44].value = 0x00000110; + pConfig[46].value = 0x0000014C; + pConfig[55].value = 0x00000141; + pConfig[66].value = 0x00001112; + pConfig[71].value = 0x00001110; + } else if (8110080000 == deframe0LaneRate) { + pConfig[43].value = 0x00000050; + pConfig[44].value = 0x00000110; + pConfig[46].value = 0x0000014C; + pConfig[55].value = 0x00000141; + pConfig[66].value = 0x00001112; + pConfig[71].value = 0x00001110; + } else { + exit(1); + } + +// step 1 ------------------------------------------------------------------------------ + ucp4008_autoStepConfig(pConfig, 0, size); + + // Wait sram_init_done + // c_rd_data[0] = r_ro1_sram_init_done; + while((ucp_reg32_read(JS_PMA0_SRAM_STATUS) & BIT0) != BIT0); + printf("pma step1 ok\n"); + + for(i=0;i<16384;i++){ + ucp_reg32_write((JS_PMA0_CFG + 0xc000*4 + i*4), pma_fw[i]); + } + ucp_reg32_or_write((JS_PMA0_CFG + 0x101*4), BIT1); + for(i=0;i<16384;i++){ + ucp_reg32_write((JS_PMA0_CFG + 0xc000*4 + i*4), pma_fw[i + 16384]); + } + // sram_ext_ld_done + // r_rw1_sram_bootload_bypass <= c_wr_data[ 0]; + // r_rw1_sram_bypass <= c_wr_data[ 4]; + // r_rw1_sram_ecc_en <= c_wr_data[ 8]; + // r_rw1_sram_ext_ld_done <= c_wr_data[12]; + ucp_reg32_or_write(JS_PMA0_SRAM_CTRL, BIT12); // sram bypass + printf("sram_init_done\n"); + +// step 2 ------------------------------------------------------------------------------ + ucp4008_autoStepConfig(pConfig, 1, size); + + // Wait Ack Done + while((ucp_reg32_read(JS_PMA0_LANE0_TRANSMITTER_REQ_ACK) & BIT0) || (ucp_reg32_read(JS_PMA0_LANE0_RECEIVER_REQ_ACK) & BIT0)); + while((ucp_reg32_read(JS_PMA0_LANE1_TRANSMITTER_REQ_ACK) & BIT0) || (ucp_reg32_read(JS_PMA0_LANE1_RECEIVER_REQ_ACK) & BIT0)); + while((ucp_reg32_read(JS_PMA0_LANE2_TRANSMITTER_REQ_ACK) & BIT0) || (ucp_reg32_read(JS_PMA0_LANE2_RECEIVER_REQ_ACK) & BIT0)); + while((ucp_reg32_read(JS_PMA0_LANE3_TRANSMITTER_REQ_ACK) & BIT0) || (ucp_reg32_read(JS_PMA0_LANE3_RECEIVER_REQ_ACK) & BIT0)); + printf("pma step2 ok\n"); + +// step 3 ------------------------------------------------------------------------------ + ucp4008_autoStepConfig(pConfig, 2, size); + + // Wait ACK and Disable Req + while(!((ucp_reg32_read(JS_PMA0_LANE0_TRANSMITTER_REQ_ACK) & BIT0) || (ucp_reg32_read(JS_PMA0_LANE0_RECEIVER_REQ_ACK) & BIT0))); + while(!((ucp_reg32_read(JS_PMA0_LANE1_TRANSMITTER_REQ_ACK) & BIT0) || (ucp_reg32_read(JS_PMA0_LANE1_RECEIVER_REQ_ACK) & BIT0))); + while(!((ucp_reg32_read(JS_PMA0_LANE2_TRANSMITTER_REQ_ACK) & BIT0) || (ucp_reg32_read(JS_PMA0_LANE2_RECEIVER_REQ_ACK) & BIT0))); + while(!((ucp_reg32_read(JS_PMA0_LANE3_TRANSMITTER_REQ_ACK) & BIT0) || (ucp_reg32_read(JS_PMA0_LANE3_RECEIVER_REQ_ACK) & BIT0))); + printf("pma step3 ok\n"); + +// step 4 ------------------------------------------------------------------------------ + ucp4008_autoStepConfig(pConfig, 3, size); + + // Wait Ack Done + while((ucp_reg32_read(JS_PMA0_LANE0_TRANSMITTER_REQ_ACK) & BIT0) || (ucp_reg32_read(JS_PMA0_LANE0_RECEIVER_REQ_ACK) & BIT0)); + while((ucp_reg32_read(JS_PMA0_LANE1_TRANSMITTER_REQ_ACK) & BIT0) || (ucp_reg32_read(JS_PMA0_LANE1_RECEIVER_REQ_ACK) & BIT0)); + while((ucp_reg32_read(JS_PMA0_LANE2_TRANSMITTER_REQ_ACK) & BIT0) || (ucp_reg32_read(JS_PMA0_LANE2_RECEIVER_REQ_ACK) & BIT0)); + while((ucp_reg32_read(JS_PMA0_LANE3_TRANSMITTER_REQ_ACK) & BIT0) || (ucp_reg32_read(JS_PMA0_LANE3_RECEIVER_REQ_ACK) & BIT0)); + printf("pma step4 ok\n"); + +// step 5 ------------------------------------------------------------------------------ + ucp4008_autoStepConfig(pConfig, 4, size); + + //Wait ACK and Disable Req + while(!((ucp_reg32_read(JS_PMA0_LANE0_TRANSMITTER_REQ_ACK) & BIT0) && (ucp_reg32_read(JS_PMA0_LANE0_RECEIVER_REQ_ACK) & BIT0))); + while(!((ucp_reg32_read(JS_PMA0_LANE1_TRANSMITTER_REQ_ACK) & BIT0) && (ucp_reg32_read(JS_PMA0_LANE1_RECEIVER_REQ_ACK) & BIT0))); + while(!((ucp_reg32_read(JS_PMA0_LANE2_TRANSMITTER_REQ_ACK) & BIT0) && (ucp_reg32_read(JS_PMA0_LANE2_RECEIVER_REQ_ACK) & BIT0))); + while(!((ucp_reg32_read(JS_PMA0_LANE3_TRANSMITTER_REQ_ACK) & BIT0) && (ucp_reg32_read(JS_PMA0_LANE3_RECEIVER_REQ_ACK) & BIT0))); + printf("pma step5 ok\n"); + +// step 6 ------------------------------------------------------------------------------ + ucp4008_autoStepConfig(pConfig, 5, size); + + // Wait Ack Done + while((ucp_reg32_read(JS_PMA0_LANE0_TRANSMITTER_REQ_ACK) & BIT0) || (ucp_reg32_read(JS_PMA0_LANE0_RECEIVER_REQ_ACK) & BIT0)); + while((ucp_reg32_read(JS_PMA0_LANE1_TRANSMITTER_REQ_ACK) & BIT0) || (ucp_reg32_read(JS_PMA0_LANE1_RECEIVER_REQ_ACK) & BIT0)); + while((ucp_reg32_read(JS_PMA0_LANE2_TRANSMITTER_REQ_ACK) & BIT0) || (ucp_reg32_read(JS_PMA0_LANE2_RECEIVER_REQ_ACK) & BIT0)); + while((ucp_reg32_read(JS_PMA0_LANE3_TRANSMITTER_REQ_ACK) & BIT0) || (ucp_reg32_read(JS_PMA0_LANE3_RECEIVER_REQ_ACK) & BIT0)); + printf("pma step6 ok\n"); + +// step 7 ------------------------------------------------------------------------------ + ucp4008_autoStepConfig(pConfig, 6, size); + + // JS PMA TX VALID + while(ucp_reg32_read(JS_PMA0_LANE0_TRANS_PLL_STATE) == 0); + + while(ucp_reg32_read(JS_PMA0_LANE0_RX_VALID_PHY) == 0); + while(ucp_reg32_read(JS_PMA0_LANE1_RX_VALID_PHY) == 0); + while(ucp_reg32_read(JS_PMA0_LANE2_RX_VALID_PHY) == 0); + while(ucp_reg32_read(JS_PMA0_LANE3_RX_VALID_PHY) == 0); + printf("pma step7 ok\n"); + + printf("pma ok\n"); +} + +void ucp4008_jesd204b_init (ucp_jesd_Init_t *setting) +{ + uint32_t tx_ratio ; + uint32_t rx0_ratio ; + uint32_t rx1_ratio ; + + uint32_t tx_lmfc_lemc_delay ; + uint32_t rx0_lmfc_lemc_delay ; + uint32_t rx1_lmfc_lemc_delay ; + + uint32_t jesd204L; + + //-------------------- Config comcore IP --------------------- + // Config jesd_sub0 comcore ip rx0 + if (setting->deframer[1].enable) + { + jesd204L = GetL(setting->deframer[1].deserializerLanesEnabled); + + rx0_ratio = cal_ratio(JS_204B_RX0_CODING_T, setting->deframer[1].jesd204M, JS_204B_RX0_S, setting->deframer[1].jesd204Np, setting->deframer[1].jesd204F, jesd204L, JS_204B_RX0_SONI); + rx0_lmfc_lemc_delay = cal_lmfc_lemc_delay(JS_204B_RX0_CODING_T, setting->deframer[1].jesd204F, setting->deframer[1].jesd204K, JS_204B_RX0_E); + + //#JS_COMC_204B_RX0_BANK_ID = 1 ; + ucp_reg32_write(JS_COMC_204B_RX0_BANK_ID, 1); + //#JS_COMC_204B_RX0_DID = 1 ; + ucp_reg32_write(JS_COMC_204B_RX0_DID, 1); + //#JS_COMC_204B_RX0_SUBCLASS = JS_204B_RX0_SUBCLASS ; + ucp_reg32_write(JS_COMC_204B_RX0_SUBCLASS, JS_204B_RX0_SUBCLASS); + //#JS_COMC_204B_RX0_CF = JS_204B_RX0_CF + (JS_204B_RX0_M<<18) ; + ucp_reg32_write(JS_COMC_204B_RX0_CF, JS_204B_RX0_CF + (JS_204B_RX0_M<<18)); + //#JS_COMC_204B_RX0_CS = JS_204B_RX0_CS ; + ucp_reg32_write(JS_COMC_204B_RX0_CS, JS_204B_RX0_CS); + //#JS_COMC_204B_RX0_F = JS_204B_RX0_F -1 ; + ucp_reg32_write(JS_COMC_204B_RX0_F, setting->deframer[1].jesd204F - 1); + //#JS_COMC_204B_RX0_K = JS_204B_RX0_K -1 ; + ucp_reg32_write(JS_COMC_204B_RX0_K, setting->deframer[1].jesd204K - 1); + //#JS_COMC_204B_RX0_L = JS_204B_RX0_L -1 ; + ucp_reg32_write(JS_COMC_204B_RX0_L, jesd204L - 1); + //#JS_COMC_204B_RX0_N = JS_204B_RX0_N -1 ; + ucp_reg32_write(JS_COMC_204B_RX0_N, JS_204B_RX0_N - 1); + //#JS_COMC_204B_RX0_M = JS_204B_RX0_M -1 ; + ucp_reg32_write(JS_COMC_204B_RX0_M, setting->deframer[1].jesd204M - 1); + //#JS_COMC_204B_RX0_NTOTAL = JS_204B_RX0_NTOTAL -1 ; + ucp_reg32_write(JS_COMC_204B_RX0_NTOTAL, setting->deframer[1].jesd204Np - 1); + //#JS_COMC_204B_RX0_S = JS_204B_RX0_S -1 ; + ucp_reg32_write(JS_COMC_204B_RX0_S, JS_204B_RX0_S - 1); + //#JS_COMC_204B_RX0_HD = JS_204B_RX0_HD ; + ucp_reg32_write(JS_COMC_204B_RX0_HD, JS_204B_RX0_HD); + //#JS_COMC_204B_RX0_SCR = JS_204B_RX0_SCR ; + ucp_reg32_write(JS_COMC_204B_RX0_SCR, JS_204B_RX0_SCR); + //#JS_COMC_204B_RX0_E = JS_204B_RX0_E -1 ; + ucp_reg32_write(JS_COMC_204B_RX0_E, setting->deframer[1].jesd204E - 1); + //#JS_COMC_204B_RX0_S_ON_IF_REG = (JS_204B_RX0_SONI-1) + (((JS_204B_RX0_S*(JS_204B_RX0_CODING_T ? 8:4))/JS_204B_RX0_SONI)<<5) ; + ucp_reg32_write(JS_COMC_204B_RX0_S_ON_IF_REG, (JS_204B_RX0_SONI - 1) + (((JS_204B_RX0_S * (JS_204B_RX0_CODING_T ? 8 : 4)) / JS_204B_RX0_SONI) << 5)); + //#JS_COMC_204B_RX0_CLK_RATIO = rx0_ratio ; + ucp_reg32_write(JS_COMC_204B_RX0_CLK_RATIO, rx0_ratio); + //#JS_COMC_204B_RX0_LMFC_LEMC_DELAY = rx0_lmfc_lemc_delay ; + ucp_reg32_write(JS_COMC_204B_RX0_LMFC_LEMC_DELAY, rx0_lmfc_lemc_delay); + //#JS_COMC_204B_RX0_ILAS_DETAILS = 0x3000000+JS_204B_RX0_F*JS_204B_RX0_K ; + ucp_reg32_write(JS_COMC_204B_RX0_ILAS_DETAILS, 0x3000000 + setting->deframer[1].jesd204F * setting->deframer[1].jesd204K); + //#JS_COMC_204B_RX0_FEC_EN = JS_204B_RX0_FEC ; + ucp_reg32_write(JS_COMC_204B_RX0_FEC_EN, JS_204B_RX0_FEC); + //#JS_COMC_204B_RX0_CRC3_EN = JS_204B_RX0_CRC3 ; + ucp_reg32_write(JS_COMC_204B_RX0_CRC3_EN, JS_204B_RX0_CRC3); + //#JS_COMC_204B_RX0_CRC12_EN = JS_204B_RX0_CRC12 ; + ucp_reg32_write(JS_COMC_204B_RX0_CRC12_EN, JS_204B_RX0_CRC12); + } + + // Config jesd_sub0 comcore ip rx1 + if (setting->deframer[0].enable) + { + jesd204L = GetL(setting->deframer[0].deserializerLanesEnabled); + + rx1_ratio = cal_ratio(JS_204B_RX1_CODING_T, setting->deframer[0].jesd204M, JS_204B_RX1_S, setting->deframer[0].jesd204Np, setting->deframer[0].jesd204F, jesd204L, JS_204B_RX1_SONI); + rx1_lmfc_lemc_delay = cal_lmfc_lemc_delay(JS_204B_RX1_CODING_T, setting->deframer[0].jesd204F, setting->deframer[0].jesd204K, JS_204B_RX1_E); + + //#JS_COMC_204B_RX1_BANK_ID = 1 ; + ucp_reg32_write(JS_COMC_204B_RX1_BANK_ID, 1); + //#JS_COMC_204B_RX1_DID = 1 ; + ucp_reg32_write(JS_COMC_204B_RX1_DID, 1); + //#JS_COMC_204B_RX1_SUBCLASS = JS_204B_RX1_SUBCLASS ; + ucp_reg32_write(JS_COMC_204B_RX1_SUBCLASS, JS_204B_RX1_SUBCLASS); + //#JS_COMC_204B_RX1_CF = JS_204B_RX1_CF + (JS_204B_RX1_M<<18) ; + ucp_reg32_write(JS_COMC_204B_RX1_CF, JS_204B_RX1_CF + (JS_204B_RX1_M << 18)); + //#JS_COMC_204B_RX1_CS = JS_204B_RX1_CS ; + ucp_reg32_write(JS_COMC_204B_RX1_CS, JS_204B_RX1_CS); + //#JS_COMC_204B_RX1_F = JS_204B_RX1_F -1 ; + ucp_reg32_write(JS_COMC_204B_RX1_F, setting->deframer[0].jesd204F - 1); + //#JS_COMC_204B_RX1_K = JS_204B_RX1_K -1 ; + ucp_reg32_write(JS_COMC_204B_RX1_K, setting->deframer[0].jesd204K - 1); + //#JS_COMC_204B_RX1_L = JS_204B_RX1_L -1 ; + ucp_reg32_write(JS_COMC_204B_RX1_L, jesd204L - 1); + //#JS_COMC_204B_RX1_N = JS_204B_RX1_N -1 ; + ucp_reg32_write(JS_COMC_204B_RX1_N, JS_204B_RX1_N - 1); + //#JS_COMC_204B_RX1_M = JS_204B_RX1_M -1 ; + ucp_reg32_write(JS_COMC_204B_RX1_M, setting->deframer[0].jesd204M - 1); + //#JS_COMC_204B_RX1_NTOTAL = JS_204B_RX1_NTOTAL -1 ; + ucp_reg32_write(JS_COMC_204B_RX1_NTOTAL, setting->deframer[0].jesd204Np - 1); + //#JS_COMC_204B_RX1_S = JS_204B_RX1_S -1 ; + ucp_reg32_write(JS_COMC_204B_RX1_S, JS_204B_RX1_S - 1); + //#JS_COMC_204B_RX1_HD = JS_204B_RX1_HD ; + ucp_reg32_write(JS_COMC_204B_RX1_HD, JS_204B_RX1_HD); + //#JS_COMC_204B_RX1_SCR = JS_204B_RX1_SCR ; + ucp_reg32_write(JS_COMC_204B_RX1_SCR, JS_204B_RX1_SCR); + //#JS_COMC_204B_RX1_E = JS_204B_RX1_E -1 ; + ucp_reg32_write(JS_COMC_204B_RX1_E, setting->deframer[0].jesd204E - 1); + //#JS_COMC_204B_RX1_S_ON_IF_REG = (JS_204B_RX1_SONI-1) + (((JS_204B_RX1_S*(JS_204B_RX1_CODING_T ? 8:4))/JS_204B_RX1_SONI)<<5) ; + ucp_reg32_write(JS_COMC_204B_RX1_S_ON_IF_REG, (JS_204B_RX1_SONI - 1) + (((JS_204B_RX1_S * (JS_204B_RX1_CODING_T ? 8 : 4)) / JS_204B_RX1_SONI) << 5)); + //#JS_COMC_204B_RX1_CLK_RATIO = rx1_ratio ; + ucp_reg32_write(JS_COMC_204B_RX1_CLK_RATIO, rx1_ratio); + //#JS_COMC_204B_RX1_LMFC_LEMC_DELAY = rx1_lmfc_lemc_delay ; + ucp_reg32_write(JS_COMC_204B_RX1_LMFC_LEMC_DELAY, rx1_lmfc_lemc_delay); + //#JS_COMC_204B_RX1_ILAS_DETAILS = 0x3000000+JS_204B_RX1_F*JS_204B_RX1_K ; + ucp_reg32_write(JS_COMC_204B_RX1_ILAS_DETAILS, 0x03000000 + setting->deframer[0].jesd204F * setting->deframer[0].jesd204K); + //#JS_COMC_204B_RX1_FEC_EN = JS_204B_RX1_FEC ; + ucp_reg32_write(JS_COMC_204B_RX1_FEC_EN, JS_204B_RX1_FEC); + //#JS_COMC_204B_RX1_CRC3_EN = JS_204B_RX1_CRC3 ; + ucp_reg32_write(JS_COMC_204B_RX1_CRC3_EN, JS_204B_RX1_CRC3); + //#JS_COMC_204B_RX1_CRC12_EN = JS_204B_RX1_CRC12 ; + ucp_reg32_write(JS_COMC_204B_RX1_CRC12_EN, JS_204B_RX1_CRC12); + } + + // Config jesd_sub0 comcore ip tx + if (setting->framer.enable) + { + jesd204L = GetL(setting->framer.serializerLanesEnabled); + + tx_ratio = cal_ratio(JS_204B_TX_CODING_T, setting->framer.jesd204M, JS_204B_TX_S, setting->framer.jesd204Np, setting->framer.jesd204F, jesd204L, JS_204B_TX_SONI); + tx_lmfc_lemc_delay = cal_lmfc_lemc_delay(JS_204B_TX_CODING_T, setting->framer.jesd204F, setting->framer.jesd204K, JS_204B_TX_E); + + //#JS_COMC_204B_TX_BANK_ID = 1 ; + ucp_reg32_write(JS_COMC_204B_TX_BANK_ID, 1); + //#JS_COMC_204B_TX_DID = 1 ; + ucp_reg32_write(JS_COMC_204B_TX_DID, 1); + //#JS_COMC_204B_TX_SUBCLASS = JS_204B_TX_SUBCLASS ; + ucp_reg32_write(JS_COMC_204B_TX_SUBCLASS, JS_204B_TX_SUBCLASS); + //#JS_COMC_204B_TX_CF = JS_204B_TX_CF + (JS_204B_TX_M<<18) ; + ucp_reg32_write(JS_COMC_204B_TX_CF, JS_204B_TX_CF + (JS_204B_TX_M << 18)); + //#JS_COMC_204B_TX_CS = JS_204B_TX_CS ; + ucp_reg32_write(JS_COMC_204B_TX_CS, JS_204B_TX_CS); + //#JS_COMC_204B_TX_F = JS_204B_TX_F -1 ; + ucp_reg32_write(JS_COMC_204B_TX_F, setting->framer.jesd204F - 1); + //#JS_COMC_204B_TX_K = JS_204B_TX_K -1 ; + ucp_reg32_write(JS_COMC_204B_TX_K, setting->framer.jesd204K - 1); + //#JS_COMC_204B_TX_L = JS_204B_TX_L -1 ; + ucp_reg32_write(JS_COMC_204B_TX_L, jesd204L - 1); + //#JS_COMC_204B_TX_N = JS_204B_TX_N -1 ; + ucp_reg32_write(JS_COMC_204B_TX_N, JS_204B_TX_N - 1); + //#JS_COMC_204B_TX_M = JS_204B_TX_M -1 ; + ucp_reg32_write(JS_COMC_204B_TX_M, setting->framer.jesd204M - 1); + //#JS_COMC_204B_TX_NTOTAL = JS_204B_TX_NTOTAL -1 ; + ucp_reg32_write(JS_COMC_204B_TX_NTOTAL, setting->framer.jesd204Np - 1); + //#JS_COMC_204B_TX_S = JS_204B_TX_S -1 ; + ucp_reg32_write(JS_COMC_204B_TX_S, JS_204B_TX_S - 1); + //#JS_COMC_204B_TX_HD = JS_204B_TX_HD ; + ucp_reg32_write(JS_COMC_204B_TX_HD, JS_204B_TX_HD); + //#JS_COMC_204B_TX_SCR = JS_204B_TX_SCR ; + ucp_reg32_write(JS_COMC_204B_TX_SCR, JS_204B_TX_SCR); + //#JS_COMC_204B_TX_E = JS_204B_TX_E -1 ; + ucp_reg32_write(JS_COMC_204B_TX_E, setting->framer.jesd204E - 1); + //#JS_COMC_204B_TX_S_ON_IF_REG = (JS_204B_TX_SONI-1) + (((JS_204B_TX_S*(JS_204B_TX_CODING_T ? 8:4))/JS_204B_TX_SONI)<<5) ; + ucp_reg32_write(JS_COMC_204B_TX_S_ON_IF_REG, (JS_204B_TX_SONI - 1) + (((JS_204B_TX_S * (JS_204B_TX_CODING_T ? 8 : 4)) / JS_204B_TX_SONI) << 5)); + //#JS_COMC_204B_TX_CLK_RATIO = tx_ratio ; + ucp_reg32_write(JS_COMC_204B_TX_CLK_RATIO, tx_ratio); + //#JS_COMC_204B_TX_TL_LATENCY = 58 ; + ucp_reg32_write(JS_COMC_204B_TX_TL_LATENCY, 58); + //#JS_COMC_204B_TX_LMFC_LEMC_DELAY = tx_lmfc_lemc_delay ; + ucp_reg32_write(JS_COMC_204B_TX_LMFC_LEMC_DELAY, tx_lmfc_lemc_delay); + //#JS_COMC_204B_TX_ILAS_DETAILS = 0x3000000+JS_204B_TX_F*JS_204B_TX_K ; + ucp_reg32_write(JS_COMC_204B_TX_ILAS_DETAILS, 0x03000000 + setting->framer.jesd204F * setting->framer.jesd204K); + //#JS_COMC_204B_TX_SAMPLE_REQ = 0x0101 ; + ucp_reg32_write(JS_COMC_204B_TX_SAMPLE_REQ, 0x0101); + //#JS_COMC_204B_TX_FEC_EN = JS_204B_TX_FEC ; + ucp_reg32_write(JS_COMC_204B_TX_FEC_EN, JS_204B_TX_FEC); + //#JS_COMC_204B_TX_CRC3_EN = JS_204B_TX_CRC3 ; + ucp_reg32_write(JS_COMC_204B_TX_CRC3_EN, JS_204B_TX_CRC3); + //#JS_COMC_204B_TX_CRC12_EN = JS_204B_TX_CRC12 ; + ucp_reg32_write(JS_COMC_204B_TX_CRC12_EN, JS_204B_TX_CRC12); + } + + printf("jesd204B ok\n"); + +} + +void ucp4008_jesd204c_init (ucp_jesd_Init_t *setting) +{ + uint32_t tx_ratio ; + uint32_t rx0_ratio ; + uint32_t rx1_ratio ; + + uint32_t tx_lmfc_lemc_delay ; + uint32_t rx0_lmfc_lemc_delay ; + uint32_t rx1_lmfc_lemc_delay ; + + uint32_t jesd204L; + + //-------------------- Config comcore IP --------------------- + // Config jesd_sub0 comcore ip rx0 + if (setting->deframer[0].enable) + { + jesd204L = GetL(setting->deframer[0].deserializerLanesEnabled); + + // JS_204B_RX0_CODING_T + rx0_ratio = cal_ratio(1, setting->deframer[0].jesd204M, JS_204B_RX0_S, setting->deframer[0].jesd204Np, setting->deframer[0].jesd204F, jesd204L, JS_204B_RX0_SONI); + //JS_204B_RX0_CODING_T + rx0_lmfc_lemc_delay = cal_lmfc_lemc_delay(1, setting->deframer[0].jesd204F, setting->deframer[0].jesd204K, JS_204B_RX0_E); + + //#JS_COMC_204C_RX0_BANK_ID = 1 ; + ucp_reg32_write(JS_COMC_204C_RX0_BANK_ID, 1); + //#JS_COMC_204C_RX0_DID = 1 ; + ucp_reg32_write(JS_COMC_204C_RX0_DID, 1); + //#JS_COMC_204C_RX0_SUBCLASS = JS_204B_RX0_SUBCLASS ; + ucp_reg32_write(JS_COMC_204C_RX0_SUBCLASS, JS_204B_RX0_SUBCLASS); + //#JS_COMC_204C_RX0_CF = JS_204B_RX0_CF + (JS_204B_RX0_M<<18) ; + ucp_reg32_write(JS_COMC_204C_RX0_CF, JS_204B_RX0_CF + (JS_204B_RX0_M<<18)); + //#JS_COMC_204C_RX0_CS = JS_204B_RX0_CS ; + ucp_reg32_write(JS_COMC_204C_RX0_CS, JS_204B_RX0_CS); + //#JS_COMC_204C_RX0_F = JS_204B_RX0_F -1 ; + ucp_reg32_write(JS_COMC_204C_RX0_F, setting->deframer[0].jesd204F - 1); + //#JS_COMC_204C_RX0_K = JS_204B_RX0_K -1 ; + ucp_reg32_write(JS_COMC_204C_RX0_K, setting->deframer[0].jesd204K - 1); + //#JS_COMC_204C_RX0_L = JS_204B_RX0_L -1 ; + ucp_reg32_write(JS_COMC_204C_RX0_L, jesd204L - 1); + //#JS_COMC_204C_RX0_N = JS_204B_RX0_N -1 ; + ucp_reg32_write(JS_COMC_204C_RX0_N, JS_204B_RX0_N - 1); + //#JS_COMC_204C_RX0_M = JS_204B_RX0_M -1 ; + ucp_reg32_write(JS_COMC_204C_RX0_M, setting->deframer[0].jesd204M - 1); + //#JS_COMC_204C_RX0_NTOTAL = JS_204B_RX0_NTOTAL -1 ; + ucp_reg32_write(JS_COMC_204C_RX0_NTOTAL, setting->deframer[0].jesd204Np - 1); + //#JS_COMC_204C_RX0_S = JS_204B_RX0_S -1 ; + ucp_reg32_write(JS_COMC_204C_RX0_S, JS_204B_RX0_S - 1); + //#JS_COMC_204C_RX0_HD = JS_204B_RX0_HD ; + ucp_reg32_write(JS_COMC_204C_RX0_HD, JS_204B_RX0_HD); + //#JS_COMC_204C_RX0_SCR = JS_204B_RX0_SCR ; + ucp_reg32_write(JS_COMC_204C_RX0_SCR, JS_204B_RX0_SCR); + //#JS_COMC_204C_RX0_E = JS_204B_RX0_E -1 ; + ucp_reg32_write(JS_COMC_204C_RX0_E, setting->deframer[0].jesd204E - 1); + //#JS_COMC_204C_RX0_S_ON_IF_REG = (JS_204B_RX0_SONI-1) + (((JS_204B_RX0_S*(JS_204B_RX0_CODING_T ? 8:4))/JS_204B_RX0_SONI)<<5) ; + ucp_reg32_write(JS_COMC_204C_RX0_S_ON_IF_REG, (JS_204B_RX0_SONI - 1) + (((JS_204B_RX0_S * (JS_204B_RX0_CODING_T ? 8 : 4)) / JS_204B_RX0_SONI) << 5)); + //#JS_COMC_204C_RX0_CLK_RATIO = rx0_ratio ; + ucp_reg32_write(JS_COMC_204C_RX0_CLK_RATIO, rx0_ratio); + //#JS_COMC_204C_RX0_LMFC_LEMC_DELAY = rx0_lmfc_lemc_delay ; + ucp_reg32_write(JS_COMC_204C_RX0_LMFC_LEMC_DELAY, rx0_lmfc_lemc_delay); + //#JS_COMC_204C_RX0_ILAS_DETAILS = 0x3000000+JS_204B_RX0_F*JS_204B_RX0_K ; + ucp_reg32_write(JS_COMC_204C_RX0_ILAS_DETAILS, 0x3000000 + setting->deframer[0].jesd204F * setting->deframer[0].jesd204K); + //#JS_COMC_204C_RX0_FEC_EN = JS_204B_RX0_FEC ; + ucp_reg32_write(JS_COMC_204C_RX0_FEC_EN, JS_204B_RX0_FEC); + //#JS_COMC_204C_RX0_CRC3_EN = JS_204B_RX0_CRC3 ; + ucp_reg32_write(JS_COMC_204C_RX0_CRC3_EN, JS_204B_RX0_CRC3); + //#JS_COMC_204C_RX0_CRC12_EN = JS_204B_RX0_CRC12 ; + ucp_reg32_write(JS_COMC_204C_RX0_CRC12_EN, JS_204B_RX0_CRC12); + } + + // Config jesd_sub0 comcore ip rx1 + if (setting->deframer[1].enable) + { + jesd204L = GetL(setting->deframer[1].deserializerLanesEnabled); + + rx1_ratio = cal_ratio(1, setting->deframer[1].jesd204M, JS_204B_RX1_S, setting->deframer[1].jesd204Np, setting->deframer[1].jesd204F, jesd204L, JS_204B_RX1_SONI); + rx1_lmfc_lemc_delay = cal_lmfc_lemc_delay(1, setting->deframer[1].jesd204F, setting->deframer[1].jesd204K, JS_204B_RX1_E); + + //#JS_COMC_204C_RX1_BANK_ID = 1 ; + ucp_reg32_write(JS_COMC_204C_RX1_BANK_ID, 1); + //#JS_COMC_204C_RX1_DID = 1 ; + ucp_reg32_write(JS_COMC_204C_RX1_DID, 1); + //#JS_COMC_204C_RX1_SUBCLASS = JS_204B_RX1_SUBCLASS ; + ucp_reg32_write(JS_COMC_204C_RX1_SUBCLASS, JS_204B_RX1_SUBCLASS); + //#JS_COMC_204C_RX1_CF = JS_204B_RX1_CF + (JS_204B_RX1_M<<18) ; + ucp_reg32_write(JS_COMC_204C_RX1_CF, JS_204B_RX1_CF + (JS_204B_RX1_M << 18)); + //#JS_COMC_204C_RX1_CS = JS_204B_RX1_CS ; + ucp_reg32_write(JS_COMC_204C_RX1_CS, JS_204B_RX1_CS); + //#JS_COMC_204C_RX1_F = JS_204B_RX1_F -1 ; + ucp_reg32_write(JS_COMC_204C_RX1_F, setting->deframer[1].jesd204F - 1); + //#JS_COMC_204C_RX1_K = JS_204B_RX1_K -1 ; + ucp_reg32_write(JS_COMC_204C_RX1_K, setting->deframer[1].jesd204K - 1); + //#JS_COMC_204C_RX1_L = JS_204B_RX1_L -1 ; + ucp_reg32_write(JS_COMC_204C_RX1_L, jesd204L - 1); + //#JS_COMC_204C_RX1_N = JS_204B_RX1_N -1 ; + ucp_reg32_write(JS_COMC_204C_RX1_N, JS_204B_RX1_N - 1); + //#JS_COMC_204C_RX1_M = JS_204B_RX1_M -1 ; + ucp_reg32_write(JS_COMC_204C_RX1_M, setting->deframer[1].jesd204M - 1); + //#JS_COMC_204C_RX1_NTOTAL = JS_204B_RX1_NTOTAL -1 ; + ucp_reg32_write(JS_COMC_204C_RX1_NTOTAL, setting->deframer[1].jesd204Np - 1); + //#JS_COMC_204C_RX1_S = JS_204B_RX1_S -1 ; + ucp_reg32_write(JS_COMC_204C_RX1_S, JS_204B_RX1_S - 1); + //#JS_COMC_204C_RX1_HD = JS_204B_RX1_HD ; + ucp_reg32_write(JS_COMC_204C_RX1_HD, JS_204B_RX1_HD); + //#JS_COMC_204C_RX1_SCR = JS_204B_RX1_SCR ; + ucp_reg32_write(JS_COMC_204C_RX1_SCR, JS_204B_RX1_SCR); + //#JS_COMC_204C_RX1_E = JS_204B_RX1_E -1 ; + ucp_reg32_write(JS_COMC_204C_RX1_E, setting->deframer[1].jesd204E - 1); + //#JS_COMC_204C_RX1_S_ON_IF_REG = (JS_204B_RX1_SONI-1) + (((JS_204B_RX1_S*(JS_204B_RX1_CODING_T ? 8:4))/JS_204B_RX1_SONI)<<5) ; + ucp_reg32_write(JS_COMC_204C_RX1_S_ON_IF_REG, (JS_204B_RX1_SONI - 1) + (((JS_204B_RX1_S * (JS_204B_RX1_CODING_T ? 8 : 4)) / JS_204B_RX1_SONI) << 5)); + //#JS_COMC_204C_RX1_CLK_RATIO = rx1_ratio ; + ucp_reg32_write(JS_COMC_204C_RX1_CLK_RATIO, rx1_ratio); + //#JS_COMC_204C_RX1_LMFC_LEMC_DELAY = rx1_lmfc_lemc_delay ; + ucp_reg32_write(JS_COMC_204C_RX1_LMFC_LEMC_DELAY, rx1_lmfc_lemc_delay); + //#JS_COMC_204C_RX1_ILAS_DETAILS = 0x3000000+JS_204B_RX1_F*JS_204B_RX1_K ; + ucp_reg32_write(JS_COMC_204C_RX1_ILAS_DETAILS, 0x03000000 + setting->deframer[1].jesd204F * setting->deframer[1].jesd204K); + //#JS_COMC_204C_RX1_FEC_EN = JS_204B_RX1_FEC ; + ucp_reg32_write(JS_COMC_204C_RX1_FEC_EN, JS_204B_RX1_FEC); + //#JS_COMC_204C_RX1_CRC3_EN = JS_204B_RX1_CRC3 ; + ucp_reg32_write(JS_COMC_204C_RX1_CRC3_EN, JS_204B_RX1_CRC3); + //#JS_COMC_204C_RX1_CRC12_EN = JS_204B_RX1_CRC12 ; + ucp_reg32_write(JS_COMC_204C_RX1_CRC12_EN, JS_204B_RX1_CRC12); + } + + // Config jesd_sub0 comcore ip tx + if (setting->framer.enable) + { + jesd204L = GetL(setting->framer.serializerLanesEnabled); + + tx_ratio = cal_ratio(1, setting->framer.jesd204M, JS_204B_TX_S, setting->framer.jesd204Np, setting->framer.jesd204F, jesd204L, JS_204B_TX_SONI); + tx_lmfc_lemc_delay = cal_lmfc_lemc_delay(1, setting->framer.jesd204F, setting->framer.jesd204K, JS_204B_TX_E); + + //#JS_COMC_204C_TX_BANK_ID = 1 ; + ucp_reg32_write(JS_COMC_204C_TX_BANK_ID, 1); + //#JS_COMC_204C_TX_DID = 1 ; + ucp_reg32_write(JS_COMC_204C_TX_DID, 1); + //#JS_COMC_204C_TX_SUBCLASS = JS_204B_TX_SUBCLASS ; + ucp_reg32_write(JS_COMC_204C_TX_SUBCLASS, JS_204B_TX_SUBCLASS); + //#JS_COMC_204C_TX_CF = JS_204B_TX_CF + (JS_204B_TX_M<<18) ; + ucp_reg32_write(JS_COMC_204C_TX_CF, JS_204B_TX_CF + (JS_204B_TX_M << 18)); + //#JS_COMC_204C_TX_CS = JS_204B_TX_CS ; + ucp_reg32_write(JS_COMC_204C_TX_CS, JS_204B_TX_CS); + //#JS_COMC_204C_TX_F = JS_204B_TX_F -1 ; + ucp_reg32_write(JS_COMC_204C_TX_F, setting->framer.jesd204F - 1); + //#JS_COMC_204C_TX_K = JS_204B_TX_K -1 ; + ucp_reg32_write(JS_COMC_204C_TX_K, setting->framer.jesd204K - 1); + //#JS_COMC_204C_TX_L = JS_204B_TX_L -1 ; + ucp_reg32_write(JS_COMC_204C_TX_L, jesd204L - 1); + //#JS_COMC_204C_TX_N = JS_204B_TX_N -1 ; + ucp_reg32_write(JS_COMC_204C_TX_N, JS_204B_TX_N - 1); + //#JS_COMC_204C_TX_M = JS_204B_TX_M -1 ; + ucp_reg32_write(JS_COMC_204C_TX_M, setting->framer.jesd204M - 1); + //#JS_COMC_204C_TX_NTOTAL = JS_204B_TX_NTOTAL -1 ; + ucp_reg32_write(JS_COMC_204C_TX_NTOTAL, setting->framer.jesd204Np - 1); + //#JS_COMC_204C_TX_S = JS_204B_TX_S -1 ; + ucp_reg32_write(JS_COMC_204C_TX_S, JS_204B_TX_S - 1); + //#JS_COMC_204C_TX_HD = JS_204B_TX_HD ; + ucp_reg32_write(JS_COMC_204C_TX_HD, JS_204B_TX_HD); + //#JS_COMC_204C_TX_SCR = JS_204B_TX_SCR ; + ucp_reg32_write(JS_COMC_204C_TX_SCR, JS_204B_TX_SCR); + //#JS_COMC_204C_TX_E = JS_204B_TX_E -1 ; + ucp_reg32_write(JS_COMC_204C_TX_E, setting->framer.jesd204E - 1); + //#JS_COMC_204C_TX_S_ON_IF_REG = (JS_204B_TX_SONI-1) + (((JS_204B_TX_S*(JS_204B_TX_CODING_T ? 8:4))/JS_204B_TX_SONI)<<5) ; + ucp_reg32_write(JS_COMC_204C_TX_S_ON_IF_REG, (JS_204B_TX_SONI - 1) + (((JS_204B_TX_S * (JS_204B_TX_CODING_T ? 8 : 4)) / JS_204B_TX_SONI) << 5)); + //#JS_COMC_204C_TX_CLK_RATIO = tx_ratio ; + ucp_reg32_write(JS_COMC_204C_TX_CLK_RATIO, tx_ratio); + //#JS_COMC_204C_TX_TL_LATENCY = 58 ; + ucp_reg32_write(JS_COMC_204C_TX_TL_LATENCY, 58); + //#JS_COMC_204C_TX_LMFC_LEMC_DELAY = tx_lmfc_lemc_delay ; + ucp_reg32_write(JS_COMC_204C_TX_LMFC_LEMC_DELAY, tx_lmfc_lemc_delay); + //#JS_COMC_204C_TX_ILAS_DETAILS = 0x3000000+JS_204B_TX_F*JS_204B_TX_K ; + ucp_reg32_write(JS_COMC_204C_TX_ILAS_DETAILS, 0x03000000 + setting->framer.jesd204F * setting->framer.jesd204K); + //#JS_COMC_204C_TX_SAMPLE_REQ = 0x0101 ; + ucp_reg32_write(JS_COMC_204C_TX_SAMPLE_REQ, 0x0101); + //#JS_COMC_204C_TX_FEC_EN = JS_204B_TX_FEC ; + ucp_reg32_write(JS_COMC_204C_TX_FEC_EN, JS_204B_TX_FEC); + //#JS_COMC_204C_TX_CRC3_EN = JS_204B_TX_CRC3 ; + ucp_reg32_write(JS_COMC_204C_TX_CRC3_EN, JS_204B_TX_CRC3); + //#JS_COMC_204C_TX_CRC12_EN = JS_204B_TX_CRC12 ; + ucp_reg32_write(JS_COMC_204C_TX_CRC12_EN, JS_204B_TX_CRC12); + } + + printf("jesd204C ok\n"); + +} + + +void ucp4008_jesd_timer_init (void) +{ + //------------------------- Timer-204 -------------------------- + // RX0_TMR -- ORX_204C + RX_204B + // RX1_TMR -- ORX_204B + RX_204C + // TX0_TMR -- TX_204B + // TX1_TMR -- TX_204C + // ctrl_oe <= wdata_i[0]; // RX_EN, TX_EN, ... + // ctrl_sel <= wdata_i[1]; // 0->reg, 1->tmr + // rx_scrath_en <= wdata_i[2]; + // tx_scrath_en <= wdata_i[3]; + //#JS_RX0_PIN_CTRL_REG = 0xD; + //#JS_RX1_PIN_CTRL_REG = 0xD; + //#JS_TX0_PIN_CTRL_REG = 0xD; + ucp_reg32_write(JS_RX0_PIN_CTRL_REG, 0x0D); + ucp_reg32_write(JS_RX1_PIN_CTRL_REG, 0x0D); + ucp_reg32_write(JS_TX0_PIN_CTRL_REG, 0x0D); + + // io_rxen0_reg <= wdata_i[0]; + // io_txen0_reg <= wdata_i[1]; + // io_rxen1_reg <= wdata_i[2]; + // io_txen1_reg <= wdata_i[3]; + // io_rxen2csu_reg <= wdata_i[4]; + // io_txen2csu_reg <= wdata_i[5]; + //#JS_RX0_IO_CTRL_REG = 0x10; + //#JS_RX1_IO_CTRL_REG = 0x10; + //#JS_TX0_IO_CTRL_REG = 0x20; + ucp_reg32_write(JS_RX0_IO_CTRL_REG, 0x10); + ucp_reg32_write(JS_RX1_IO_CTRL_REG, 0x10); + ucp_reg32_write(JS_TX0_IO_CTRL_REG, 0x10); + + return; +} + +void ucp4008_jesd204b_bringup (void) +{ + ucp_reg32_write(JS_COMC_204B_RX0_ENABLEMODULE, 0x1); + ucp_reg32_write(JS_COMC_204B_RX1_ENABLEMODULE, 0x1); + ucp_reg32_write(JS_COMC_204B_TX_ENABLEMODULE, 0x1); + printf("enable jesd\n"); + +} + +static uint8_t ucp4008_jesd_calSamClkDiv (uint8_t is204C, uint8_t f) +{ + double factD, divPara; + + divPara = (is204C) ? 8.0 : 4.0; + factD = divPara/f; + + if (((factD > 0.0) && (factD < 1.0)) || (fabs(factD - 1.0) < DBL_EPSILON)) + { + return 1; + } + + if (((factD > 1.0) && (factD < 2.0)) || (fabs(factD - 2.0) < DBL_EPSILON)) + { + return 2; + } + + if (((factD > 2.0) && (factD < 4.0)) || (fabs(factD - 4.0) < DBL_EPSILON)) + { + return 4; + } + + if (((factD > 4.0) && (factD < 8.0)) || (fabs(factD - 8.0) < DBL_EPSILON)) + { + return 8; + } + + printf("error: invalid samClk divFact\n"); + exit(1); + return 0; +} + +static void ucp4008_jesd_calLarate (ucp_jesd_Init_t *setting) +{ + uint8_t jesd204L, samClkFactor, chaClkFactor, samClkDiv; + uint32_t pllClk, samClk, chaClk; + + ucp_reg32_write(UCP_JESDPARA_RX0, 0); + ucp_reg32_write(UCP_CLKPARA0_RX0, 0); + ucp_reg32_write(UCP_CLKPARA1_RX0, 0); + ucp_reg32_write(UCP_JESDPARA_RX1, 0); + ucp_reg32_write(UCP_CLKPARA0_RX1, 0); + ucp_reg32_write(UCP_CLKPARA1_RX1, 0); + ucp_reg32_write(UCP_JESDPARA_TX0, 0); + ucp_reg32_write(UCP_CLKPARA0_TX0, 0); + ucp_reg32_write(UCP_CLKPARA1_TX0, 0); + ucp_reg32_write(UCP_JESDPARA_TX1, 0); + ucp_reg32_write(UCP_CLKPARA0_TX1, 0); + ucp_reg32_write(UCP_CLKPARA1_TX1, 0); + + sampleFactor[0] = SAMPLE_FACTOR_1_1; + sampleFactor[1] = SAMPLE_FACTOR_1_1; + sampleFactor[2] = SAMPLE_FACTOR_1_1; + sampleFactor[3] = SAMPLE_FACTOR_1_1; + + pllFactor = UCP_PLL_FACT; // range: 2/4/8 + pllClk = pllFactor*setting->common.devClock_kHz*1e3; + printf("deviceClk: %.4fMhz\n", setting->common.devClock_kHz*1e-3); + printf("pllClk: %.4fMhz\n", pllClk*1e-6); + if (0 == setting->common.enableJesd204C) // is JESD204B + { + jesd204L = GetL(setting->framer.serializerLanesEnabled); + if (jesd204L > 0) + { + frameLaneRate = setting->framer.sampleClock_kHz*1e3*setting->framer.jesd204M*setting->framer.jesd204Np*JS_204B_TX_S*10/8/jesd204L; + chaClk = frameLaneRate/40; // chaClk + chaClkFactor = chaClk/setting->framer.sampleClock_kHz/1000; + samClkDiv = ucp4008_jesd_calSamClkDiv(setting->common.enableJesd204C ,setting->framer.jesd204F); + samClk = chaClk*samClkDiv; // samClk + samClkFactor = samClk/setting->framer.sampleClock_kHz/1000; + sampleFactor[2] = pllClk/samClk; + + ucp_reg32_write(UCP_JESDPARA_TX0, (jesd204L | (setting->framer.jesd204M << 8) | (setting->framer.jesd204Np << 16))); + ucp_reg32_write(UCP_CLKPARA0_TX0, setting->framer.sampleClock_kHz*1e3); + ucp_reg32_write(UCP_CLKPARA1_TX0, (chaClkFactor << 8) | samClkFactor); + printf("jesd frameLaneRate: %.8fGhz\n", frameLaneRate*1.0/1e9); + printf("jesd frameLane: %d %04X\n", jesd204L, setting->framer.serializerLanesEnabled); + printf("sampleClk: %.4fMhz SAM: %.4fMhz(Ssf: %d) CHA: %.4fMhz(Csf: %d) PSf: %d\n", + setting->framer.sampleClock_kHz*0.001, + samClk*0.000001, samClkFactor, + chaClk*0.000001, chaClkFactor, + sampleFactor[2]); + } + + jesd204L = GetL(setting->deframer[0].deserializerLanesEnabled); + if (jesd204L > 0) + { + deframe0LaneRate = setting->deframer[0].sampleClock_kHz*1e3*setting->deframer[0].jesd204M*setting->deframer[0].jesd204Np*JS_204B_RX0_S*10/8/jesd204L; + chaClk = deframe0LaneRate/40; // chaClk + chaClkFactor = chaClk/setting->deframer[0].sampleClock_kHz/1000; + samClkDiv = ucp4008_jesd_calSamClkDiv(setting->common.enableJesd204C ,setting->deframer[0].jesd204F); + samClk = chaClk*samClkDiv; // samClk + samClkFactor = samClk/setting->deframer[0].sampleClock_kHz/1000; + sampleFactor[0] = pllClk/samClk; + + ucp_reg32_write(UCP_JESDPARA_RX0, (jesd204L | (setting->deframer[0].jesd204M << 8) | (setting->deframer[0].jesd204Np << 16))); + ucp_reg32_write(UCP_CLKPARA0_RX0, setting->deframer[0].sampleClock_kHz*1e3); + ucp_reg32_write(UCP_CLKPARA1_RX0, (chaClkFactor << 8) | samClkFactor); + ucp_reg32_write(UCP_JESDPARA_RX1, (jesd204L | (setting->deframer[0].jesd204M << 8) | (setting->deframer[0].jesd204Np << 16))); + ucp_reg32_write(UCP_CLKPARA0_RX1, setting->deframer[0].sampleClock_kHz*1e3); + ucp_reg32_write(UCP_CLKPARA1_RX1, (chaClkFactor << 8) | samClkFactor); + printf("jesd deframe0LaneRate: %.8fGhz\n", deframe0LaneRate*1.0/1e9); + printf("jesd deframeLane: %d %04X\n", jesd204L, setting->deframer[0].deserializerLanesEnabled); + printf("sampleClk: %.4fMhz SAM: %.4fMhz(Ssf: %d) CHA: %.4fMhz(Csf: %d) PSf: %d\n", + setting->deframer[0].sampleClock_kHz*0.001, + samClk*0.000001, samClkFactor, + chaClk*0.000001, chaClkFactor, + sampleFactor[0]); + } + + jesd204L = GetL(setting->deframer[1].deserializerLanesEnabled); + if (jesd204L > 0) + { + deframe1LaneRate = setting->deframer[1].sampleClock_kHz*1e3*setting->deframer[1].jesd204M*setting->deframer[1].jesd204Np*JS_204B_RX1_S*10/8/jesd204L; + chaClk = deframe1LaneRate/40; // chaClk + chaClkFactor = chaClk/setting->deframer[1].sampleClock_kHz/1000; + samClkDiv = ucp4008_jesd_calSamClkDiv(setting->common.enableJesd204C ,setting->deframer[1].jesd204F); + samClk = chaClk*samClkDiv; // samClk + samClkFactor = samClk/setting->deframer[1].sampleClock_kHz/1000; + sampleFactor[1] = pllClk/samClk; + + ucp_reg32_write(UCP_JESDPARA_RX1, (jesd204L | (setting->deframer[1].jesd204M << 8) | (setting->deframer[1].jesd204Np << 16))); + ucp_reg32_write(UCP_CLKPARA0_RX1, setting->deframer[1].sampleClock_kHz*1e3); + ucp_reg32_write(UCP_CLKPARA1_RX1, (chaClkFactor << 8) | samClkFactor); + printf("jesd deframe1LaneRate: %.8fGhz\n", deframe1LaneRate*1.0/1e9); + printf("jesd deframeLane: %d %04X\n", jesd204L, setting->deframer[1].deserializerLanesEnabled); + printf("sampleClk: %.4fMhz SAM: %.4fMhz(Ssf: %d) CHA: %.4fMhz(Csf: %d) PSf: %d\n", + setting->deframer[1].sampleClock_kHz*0.001, + samClk*0.000001, samClkFactor, + chaClk*0.000001, chaClkFactor, + sampleFactor[1]); + } + } + else // is JESD204C + { + jesd204L = GetL(setting->framer.serializerLanesEnabled); + if (jesd204L > 0) + { + frameLaneRate = setting->framer.sampleClock_kHz*1e3*setting->framer.jesd204M*setting->framer.jesd204Np*JS_204B_TX_S*66/64/jesd204L; + chaClk = frameLaneRate/66; // chaClk + chaClkFactor = chaClk/setting->framer.sampleClock_kHz/1000; + samClkDiv = ucp4008_jesd_calSamClkDiv(setting->common.enableJesd204C ,setting->framer.jesd204F); + samClk = chaClk*samClkDiv; // samClk + samClkFactor = samClk/setting->framer.sampleClock_kHz/1000; + sampleFactor[2] = pllClk/samClk; + + ucp_reg32_write(UCP_JESDPARA_TX0, (jesd204L | (setting->framer.jesd204M << 8) | (setting->framer.jesd204Np << 16))); + ucp_reg32_write(UCP_CLKPARA0_TX0, setting->framer.sampleClock_kHz*1e3); + ucp_reg32_write(UCP_CLKPARA1_TX0, (chaClkFactor << 8) | samClkFactor); + printf("jesd frameLaneRate: %.8fGhz\n", frameLaneRate*1.0/1e9); + printf("jesd frameLane: %d %04X\n", jesd204L, setting->framer.serializerLanesEnabled); + printf("sampleClk: %.4fMhz SAM: %.4fMhz(Ssf: %d) CHA: %.4fMhz(Csf: %d) PSf: %d\n", + setting->framer.sampleClock_kHz*0.001, + samClk*0.000001, samClkFactor, + chaClk*0.000001, chaClkFactor, + sampleFactor[2]); + } + + jesd204L = GetL(setting->deframer[0].deserializerLanesEnabled); + if (jesd204L > 0) + { + deframe0LaneRate = setting->deframer[0].sampleClock_kHz*1e3*setting->deframer[0].jesd204M*setting->deframer[0].jesd204Np*JS_204B_RX0_S*66/64/jesd204L; + chaClk = deframe0LaneRate/66; // chaClk + chaClkFactor = chaClk/setting->deframer[0].sampleClock_kHz/1000; + samClkDiv = ucp4008_jesd_calSamClkDiv(setting->common.enableJesd204C ,setting->deframer[0].jesd204F); + samClk = chaClk*samClkDiv; // samClk + samClkFactor = samClk/setting->deframer[0].sampleClock_kHz/1000; + sampleFactor[0] = pllClk/samClk; + + ucp_reg32_write(UCP_JESDPARA_RX0, (jesd204L | (setting->deframer[0].jesd204M << 8) | (setting->deframer[0].jesd204Np << 16))); + ucp_reg32_write(UCP_CLKPARA0_RX0, setting->deframer[0].sampleClock_kHz*1e3); + ucp_reg32_write(UCP_CLKPARA1_RX0, (chaClkFactor << 8) | samClkFactor); + ucp_reg32_write(UCP_JESDPARA_RX1, (jesd204L | (setting->deframer[0].jesd204M << 8) | (setting->deframer[0].jesd204Np << 16))); + ucp_reg32_write(UCP_CLKPARA0_RX1, setting->deframer[0].sampleClock_kHz*1e3); + ucp_reg32_write(UCP_CLKPARA1_RX1, (chaClkFactor << 8) | samClkFactor); + printf("jesd deframe0LaneRate: %.8fGhz\n", deframe0LaneRate*1.0/1e9); + printf("jesd deframeLane: %d %04X\n", jesd204L, setting->deframer[0].deserializerLanesEnabled); + printf("sampleClk: %.4fMhz SAM: %.4fMhz(Ssf: %d) CHA: %.4fMhz(Csf: %d) PSf: %d\n", + setting->deframer[0].sampleClock_kHz*0.001, + samClk*0.000001, samClkFactor, + chaClk*0.000001, chaClkFactor, + sampleFactor[1]); + } + + jesd204L = GetL(setting->deframer[1].deserializerLanesEnabled); + if (jesd204L > 0) + { + deframe1LaneRate = setting->deframer[1].sampleClock_kHz*1e3*setting->deframer[1].jesd204M*setting->deframer[1].jesd204Np*JS_204B_RX1_S*66/64/jesd204L; + chaClk = deframe1LaneRate/66; // chaClk + chaClkFactor = chaClk/setting->deframer[1].sampleClock_kHz/1000; + samClkDiv = ucp4008_jesd_calSamClkDiv(setting->common.enableJesd204C ,setting->deframer[1].jesd204F); + samClk = chaClk*samClkDiv; // samClk + samClkFactor = samClk/setting->deframer[1].sampleClock_kHz/1000; + sampleFactor[1] = pllClk/samClk; + + ucp_reg32_write(UCP_JESDPARA_RX1, (jesd204L | (setting->deframer[1].jesd204M << 8) | (setting->deframer[1].jesd204Np << 16))); + ucp_reg32_write(UCP_CLKPARA0_RX1, setting->deframer[1].sampleClock_kHz*1e3); + ucp_reg32_write(UCP_CLKPARA1_RX1, (chaClkFactor << 8) | samClkFactor); + printf("jesd deframe1LaneRate: %.8fGhz\n", deframe1LaneRate*1.0/1e9); + printf("jesd deframeLane: %d %04X\n", jesd204L, setting->deframer[1].deserializerLanesEnabled); + printf("sampleClk: %.4fMhz SAM: %.4fMhz(Ssf: %d) CHA: %.4fMhz(Csf: %d) PSf: %d\n", + setting->deframer[1].sampleClock_kHz*0.001, + samClk*0.000001, samClkFactor, + chaClk*0.000001, chaClkFactor, + sampleFactor[0]); + } + } + + return; +} + +static void ucp4008_autoStepConfig (tUcpAutoConfigPara_t *para, uint32_t step, uint32_t size) +{ + uint32_t i; + + for (i = 0; i < size; i++) + { + if (para[i].step != step) + { + continue; + } + + switch (para[i].opt) + { + case UCP_OPT_SKIP: + break; + + case UCP_OPT_W: + ucp_reg32_write(para[i].addr, para[i].value); + break; + + case UCP_OPT_ANDW: + ucp_reg32_and_write(para[i].addr, para[i].value); + break; + + case UCP_OPT_ORW: + ucp_reg32_or_write(para[i].addr, para[i].value); + break; + + default: + break; + + } + } + + return; +} + +static void ucp4008_jesd_crg_print (void) +{ + PrintUcpReg(JS_CRG_TMR_EN_SAM_CLK_SEL); + PrintUcpReg(JS_CRG_CLK_SEL); + PrintUcpReg(JS_CRG_DPLL0_CTRL_0); // + PrintUcpReg(JS_CRG_DPLL0_CTRL_1); // + PrintUcpReg(JS_CRG_SAM0_CLK_CTRL); + PrintUcpReg(JS_CRG_SAM1_CLK_CTRL); + PrintUcpReg(JS_CRG_SAM2_CLK_CTRL); + PrintUcpReg(JS_CRG_SAM3_CLK_CTRL); + PrintUcpReg(JS_CRG_CHA0_CLK_CTRL); + PrintUcpReg(JS_CRG_CHA1_CLK_CTRL); + PrintUcpReg(JS_CRG_CHA2_CLK_CTRL); + PrintUcpReg(JS_CRG_CHA3_CLK_CTRL); + PrintUcpReg(JS_CRG_SAM_CHA0_RST_CTRL); + PrintUcpReg(JS_CRG_SAM_CHA1_RST_CTRL); + PrintUcpReg(JS_CRG_SAM_CHA2_RST_CTRL); + PrintUcpReg(JS_CRG_SAM_CHA3_RST_CTRL); + PrintUcpReg(JS_CRG_SAM_CHA4_RST_CTRL); + PrintUcpReg(JS_CRG_SAM_CHA5_RST_CTRL); + PrintUcpReg(JS_CRG_SAM_CHA6_RST_CTRL); + PrintUcpReg(JS_CRG_SAM_CHA7_RST_CTRL); + PrintUcpReg(JS_CRG_JESD0_TIME_CTRL); + PrintUcpReg(JS_CRG_JESD1_TIME_CTRL); + PrintUcpReg(JS_CRG_JESD2_TIME_CTRL); + PrintUcpReg(JS_CRG_JESD3_TIME_CTRL); + PrintUcpReg(JS_CRG_JESD4_TIME_CTRL); + PrintUcpReg(JS_CRG_JESD5_TIME_CTRL); + PrintUcpReg(JS_CRG_JESD6_TIME_CTRL); + PrintUcpReg(JS_CRG_JESD7_TIME_CTRL); + PrintUcpReg(JS_CRG_PHY_TX_RSTN_JS_CTRL_0); + PrintUcpReg(JS_CRG_PHY_TX_RSTN_JS_CTRL_1); + PrintUcpReg(JS_CRG_PHY_TX_RSTN_JS_CTRL_2); + PrintUcpReg(JS_CRG_PHY_TX_RSTN_JS_CTRL_3); + PrintUcpReg(JS_CRG_PHY_RX_RSTN_JS_CTRL_0); + PrintUcpReg(JS_CRG_PHY_RX_RSTN_JS_CTRL_1); + PrintUcpReg(JS_CRG_PHY_RX_RSTN_JS_CTRL_2); + PrintUcpReg(JS_CRG_PHY_RX_RSTN_JS_CTRL_3); + PrintUcpReg(JS_CRG_PHY_EQ_RSTN_JS_CTRL_0); + PrintUcpReg(JS_CRG_PHY_EQ_RSTN_JS_CTRL_1); + PrintUcpReg(JS_CRG_PHY_EQ_RSTN_JS_CTRL_2); + PrintUcpReg(JS_CRG_PHY_EQ_RSTN_JS_CTRL_3); + PrintUcpReg(JS_CRG_PHY_PWR_ON_RST_JS_CTRL); + PrintUcpReg(JS_CRG_DPLL_PMA_CTRL); // + PrintUcpReg(JS_CRG_DPLL_PMA_CTRL); // read + PrintUcpReg(JS_CRG_TMR_EN_SAM_CLK_SEL); // + + return; +} + +static void ucp4008_jesd_pma_print (void) +{ + // step 1 + PrintUcpReg(JS_PMA0_PHY_RESET); + PrintUcpReg(JS_PMA0_PCS_BIT_REV_CTRL); + PrintUcpReg(JS_PMA0_SRAM_CTRL); + PrintUcpReg(JS_PMA0_TX_CLK_SEL); + PrintUcpReg(JS_PMA0_REFA_CLK_CTRL2); + PrintUcpReg(JS_PMA0_REF_CLK_CTRL); + PrintUcpReg(JS_PMA0_MPLLA_PARAM6); + PrintUcpReg(JS_PMA0_MPLLA_PARAM4); + PrintUcpReg(JS_PMA0_MPLLA_PARAM5); + PrintUcpReg(JS_PMA0_MPLLA_SSC_CTRL1); + PrintUcpReg(JS_PMA0_MPLLA_SSC_CTRL4); + PrintUcpReg(JS_PMA0_MPLLA_SSC_CTRL2); + PrintUcpReg(JS_PMA0_MPLLA_SSC_CTRL3); + PrintUcpReg(JS_PMA0_MPLLA_SSC_CTRL5); + PrintUcpReg(JS_PMA0_MPLLA_SSC_CTRL6); + PrintUcpReg(JS_PMA0_MPLLA_FRAC_CTRL2); + PrintUcpReg(JS_PMA0_MPLLA_FRAC_CTRL3); + PrintUcpReg(JS_PMA0_MPLLA_FRAC_CTRL1); + PrintUcpReg(JS_PMA0_MPLLA_FRAC_CTRL4); + PrintUcpReg(JS_PMA0_MPLLA_PARAM3); + PrintUcpReg(JS_PMA0_MPLLA_PARAM2); + PrintUcpReg(JS_PMA0_MPLLA_PARAM1); + PrintUcpReg(JS_PHY_BS_CTRL); + PrintUcpReg(JS_PMA0_RTUNE_CTRL1); + PrintUcpReg(JS_PMA0_RTUNE_CTRL2); + PrintUcpReg(JS_PMA0_RTUNE_CTRL3); + PrintUcpReg(JS_PMA0_SUP_MISC); + PrintUcpReg(JS_PMA0_RX_BIAS_CURRENT_CTRL); + PrintUcpReg(JS_PMA0_BROADCAST_LANE_REFCLK_SEL); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM8); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_DATAPATH_SETTING1); + PrintUcpReg(JS_PMA0_BROADCAST_TRANSMITTER_CONTROL2); + PrintUcpReg(JS_PMA0_BROADCAST_TRANS_REQ_CTRL1); + PrintUcpReg(JS_PMA0_BROADCAST_TRANSMITTER_REQ_PARAM2); + PrintUcpReg(JS_PMA0_BROADCAST_TRANS_REQ_CTRL2); + PrintUcpReg(JS_PMA0_BROADCAST_TRANS_REQ_CTRL4); + PrintUcpReg(JS_PMA0_BROADCAST_TRANS_REQ_CTRL5); + PrintUcpReg(JS_PMA0_BROADCAST_ETH_CLK_CTRL); + PrintUcpReg(JS_PMA0_BROADCAST_TRANS_INTERFACE_CTRL); + PrintUcpReg(JS_PMA0_BROADCAST_TX_DIV_CLK_CTRL); + PrintUcpReg(JS_PMA0_BROADCAST_CONTEXT_RESTORE_CTRL3); + PrintUcpReg(JS_PMA0_BROADCAST_TRANS_REQ_CTRL3); + PrintUcpReg(JS_PMA0_BROADCAST_TRANSMITTER_DATAPATH_SETTING); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM3); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM4); + PrintUcpReg(JS_PMA0_BROADCAST_RX_EQ_CTRL2); + PrintUcpReg(JS_PMA0_BROADCAST_RX_EQ_CTRL1); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM5); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM2); + PrintUcpReg(JS_PMA0_BROADCAST_RX_DCC_CTRL); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_DATAPATH_SETTING2); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM6); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_CONTROL); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM9); + PrintUcpReg(JS_PMA0_BROADCAST_RX_DIV_CLK_CTRL); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_ADAPT_SETTING); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_DATAPATH_SETTING3); + PrintUcpReg(JS_PMA0_BROADCAST_RX_ADAPT_CTRL); + PrintUcpReg(JS_PMA0_BROADCAST_TRANSMITTER_EQ1); + PrintUcpReg(JS_PMA0_BROADCAST_TRANSMITTER_EQ2); + PrintUcpReg(JS_PMA0_BROADCAST_TRANSMITTER_EQ3); + PrintUcpReg(JS_PMA0_PHY_RESET); + PrintUcpReg(JS_PMA0_REFA_CLK_CTRL1); + + // step 2 + PrintUcpReg(JS_PMA0_BROADCAST_TRANSMITTER_CONTROL1); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_RESET); + + // step 3 + PrintUcpReg(JS_PMA0_BROADCAST_TRANSMITTER_REQ_PARAM1); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM7); + PrintUcpReg(JS_PMA0_BROADCAST_TRANSMITTER_REQ); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_REQ); + + // step 4 + PrintUcpReg(JS_PMA0_BROADCAST_TRANSMITTER_REQ); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_REQ); + + // step 5 + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_REQ_PARAM7); + PrintUcpReg(JS_PMA0_BROADCAST_TRANSMITTER_REQ_PARAM1); + PrintUcpReg(JS_PMA0_BROADCAST_TRANSMITTER_DATAPATH_CLKRDY); + PrintUcpReg(JS_PMA0_BROADCAST_TRANSMITTER_REQ); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_REQ); + + // step 6 + PrintUcpReg(JS_PMA0_BROADCAST_TRANSMITTER_REQ); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_REQ); + + // step 7 + PrintUcpReg(JS_PMA0_BROADCAST_TRANSMITTER_DATAPATH_EN); + PrintUcpReg(JS_PMA0_BROADCAST_RECEIVER_DATAPATH_EN); + +} +// ----------------------------------- CSU ----------------------------------- +extern uint32_t nr_fm20000000_1slot_all[]; +extern uint32_t nr_fm20000000_1slot_pre7[]; +extern uint32_t nr_fm20000000_1slot_post7[]; +void ucp_csu_config_test(void) +{ + // 0.5us + // 0.5us oneAnt: 61,440*2bytes_I*2bytes_Q = 245,760 bytes/oneAnt + // 0.5us 4Ants: 61,440*2bytes_I*2bytes_Q*4ants = 245760*4 bytes = 983,040bytes + // 1s oneAnt: 245,760/0.0005 = 491,520,000 bytes + // 1s 4Ants: 491,520,000*4 = 1,966,080,000 bytes + #define TONELEN 61440 + #define N15DBFS_FIX_AMP 6515 + double alfa; + int16_t iData, qData; + uint32_t i; + uint64_t addrRxMem, addrTxMem; + + //------------------------- Timer-204 -------------------------- + // RX0_TMR -- ORX_204C + RX_204B + // RX1_TMR -- ORX_204B + RX_204C + // TX0_TMR -- TX_204B + // TX1_TMR -- TX_204C + // ctrl_oe <= wdata_i[0]; // RX_EN, TX_EN, ... + // ctrl_sel <= wdata_i[1]; // 0->reg, 1->tmr + // rx_scrath_en <= wdata_i[2]; + // tx_scrath_en <= wdata_i[3]; + //#JS_RX0_PIN_CTRL_REG = 0xD; + //#JS_RX1_PIN_CTRL_REG = 0xD; + //#JS_TX0_PIN_CTRL_REG = 0xD; + ucp_reg32_write(JS_RX0_PIN_CTRL_REG, 0x0D); + ucp_reg32_write(JS_RX1_PIN_CTRL_REG, 0x0D); + ucp_reg32_write(JS_TX0_PIN_CTRL_REG, 0x0D); + + // io_rxen0_reg <= wdata_i[0]; + // io_txen0_reg <= wdata_i[1]; + // io_rxen1_reg <= wdata_i[2]; + // io_txen1_reg <= wdata_i[3]; + // io_rxen2csu_reg <= wdata_i[4]; + // io_txen2csu_reg <= wdata_i[5]; + //#JS_RX0_IO_CTRL_REG = 0x10; + //#JS_RX1_IO_CTRL_REG = 0x10; + //#JS_TX0_IO_CTRL_REG = 0x20; + ucp_reg32_write(JS_RX0_IO_CTRL_REG, 0x10); + ucp_reg32_write(JS_RX1_IO_CTRL_REG, 0x10); + ucp_reg32_write(JS_TX0_IO_CTRL_REG, 0x20); + + //-------------------------- CSU-DMA --------------------------- + addrRxMem = 0x6BC44800; + addrTxMem = 0x60F00000; + + #if 0 + js_csu_loc_cfg(0x4000); + js_csu_glb_cfg(addrRxMem + 0*TONELEN*4*4, TONELEN*4*4, 1); + printf("CsuMem Rx 1: %X\n", addrRxMem + 0*TONELEN*4*4); + js_csu_glb_cfg(addrRxMem + 1*TONELEN*4*4, TONELEN*4*4, 2); + printf("CsuMem Rx 2: %X\n", addrRxMem + 1*TONELEN*4*4); + js_csu_glb_cfg(addrRxMem + 2*TONELEN*4*4, TONELEN*4*4, 3); + printf("CsuMem Rx 3: %X\n", addrRxMem + 2*TONELEN*4*4); + + js_csu_glb_cfg(addrTxMem + 0*TONELEN*4*4, TONELEN*4*4, 4); + printf("CsuMem Tx 1: %X\n", addrTxMem + 0*TONELEN*4*4); + js_csu_glb_cfg(addrTxMem + 1*TONELEN*4*4, TONELEN*4*4, 5); + printf("CsuMem Tx 2: %X\n", addrTxMem + 1*TONELEN*4*4); + js_csu_glb_cfg(addrTxMem + 2*TONELEN*4*4, TONELEN*4*4, 6); + printf("CsuMem Tx 3: %X\n", addrTxMem + 2*TONELEN*4*4); + #else + js_csu_loc_cfg(0xF0000); + + js_csu_glb_cfg_sep(addrRxMem + 0*0xF0000, 0xF0000, 1, 4, 0); + printf("CsuMem Rx 1: %#lX\n", addrRxMem + 0*0xF0000); + js_csu_glb_cfg_sep(addrRxMem + 1*0xF0000, 0xF0000, 2, 4, 0); + printf("CsuMem Rx 2: %#lX\n", addrRxMem + 1*0xF0000); + js_csu_glb_cfg_sep(addrRxMem + 2*0xF0000, 0xF0000, 3, 4, 0); + printf("CsuMem Rx 3: %#lX\n", addrRxMem + 2*0xF0000); + + js_csu_glb_cfg_sep(addrTxMem + 0*0xF0000, 0xF0000, 4, 4, 0); + printf("CsuMem Tx 1: %#lX\n", addrTxMem + 0*0xF0000); + js_csu_glb_cfg_sep(addrTxMem + 1*0xF0000, 0xF0000, 5, 4, 0); + printf("CsuMem Tx 2: %#lX\n", addrTxMem + 1*0xF0000); + js_csu_glb_cfg_sep(addrTxMem + 2*0xF0000, 0xF0000, 6, 4, 0); + printf("CsuMem Tx 3: %#lX\n", addrTxMem + 2*0xF0000); + #endif + + + + // [ 1: 0] -> CS + // [ 6: 4] -> Margin + // [15: 8] -> Num, (16+2*Num)=2*N + // [23:16] -> N*M + // [25:24] -> SepNum + // [27:26] -> M/2-1 + //# JS_CSU_JESDRX0SET = ((JS_204B_RX1_M/2-1)<<26)+((JS_204B_RX1_NTOTAL*JS_204B_RX1_M)<<16)+((JS_204B_RX1_N-8)<<8)+JS_204B_RX1_CS; + //# JS_CSU_JESDRX1SET = ((JS_204B_RX0_M/2-1)<<26)+((JS_204B_RX0_NTOTAL*JS_204B_RX0_M)<<16)+((JS_204B_RX0_N-8)<<8)+JS_204B_RX0_CS; + //# JS_CSU_JESDTXSET = ((JS_204B_TX_M /2-1)<<26)+((JS_204B_TX_NTOTAL *JS_204B_TX_M )<<16)+((JS_204B_TX_N -8)<<8)+JS_204B_TX_CS ; + ucp_reg32_write(JS_CSU_JESDRX0SET, ((JS_204B_RX1_M / 2 - 1) << 26) + (3 << 24) + ((JS_204B_RX1_NTOTAL * JS_204B_RX1_M/4) << 16) + ((JS_204B_RX1_N - 8) << 8 ) + JS_204B_RX1_CS); + // ucp_reg32_write(JS_CSU_JESDRX1SET, ((JS_204B_RX0_M / 2 -1) << 26) + (3 << 24) + ((JS_204B_RX0_NTOTAL * JS_204B_RX0_M/4) << 16)+((JS_204B_RX0_N - 8) << 8) + JS_204B_RX0_CS); + ucp_reg32_write(JS_CSU_JESDTXSET, ((JS_204B_TX_M / 2 -1) << 26) + (3 << 24) + ((JS_204B_TX_NTOTAL * JS_204B_TX_M/4) << 16)+((JS_204B_TX_N - 8) << 8) + JS_204B_TX_CS); + + // almostfull=0x10, + // sendthred=0x4 + //# JS_CSU_ALMOSTFULLSENDTHRED = 0x00040400; + //# JS_CSU_ALMOSTFULLSENDTHRED = 0x80048400; + //# JS_CSU_FINDDMATAG = 0x60 ; // st wait wr resp + ucp_reg32_write(JS_CSU_ALMOSTFULLSENDTHRED, 0x00040100); + ucp_reg32_write(JS_CSU_ALMOSTFULLSENDTHRED, 0x80048100); + ucp_reg32_write(JS_CSU_FINDDMATAG, 0x60); + + for(i = 0; i < 0x78200/4; i++) + { + alfa = -2 * M_PI * i / 122.88; + iData = (int16_t)(N15DBFS_FIX_AMP * cos(alfa)); + qData = (int16_t)(N15DBFS_FIX_AMP * sin(alfa)); + //iqData <<= 16; + //iqData += (int16_t)(N15DBFS_FIX_AMP * sin(alfa)); + +#if 1 + ucp_reg16_write(addrTxMem + 0*0xF0000 + i*4 + 0x0, iData); + ucp_reg16_write(addrTxMem + 0*0xF0000 + i*4 + 0x2, qData); + + ucp_reg16_write(addrTxMem + 1*0xF0000 + i*4 + 0x0, iData); + ucp_reg16_write(addrTxMem + 1*0xF0000 + i*4 + 0x2, qData); + + ucp_reg16_write(addrTxMem + 2*0xF0000 + i*4 + 0x0, iData); + ucp_reg16_write(addrTxMem + 2*0xF0000 + i*4 + 0x2, qData); +#else + ucp_reg32_write(addrTxMem + 0*0xF0000 + i*4, nr_fm20000000_1slot_all[i]); + ucp_reg32_write(addrTxMem + 1*0xF0000 + i*4, nr_fm20000000_1slot_all[i]); + ucp_reg32_write(addrTxMem + 2*0xF0000 + i*4, nr_fm20000000_1slot_all[i]); +#endif + } + +#if 0 + for(i = 0; i < 0x78200/4; i++) + { + ucp_reg32_write(addrTxMem + 0*0xF0000 + i*4, nr_fm20000000_1slot_pre7[i]); + } + for(i = 0; i < 0x77e00/4; i++) + { + ucp_reg32_write(addrTxMem + 1*0xF0000 + i*4, nr_fm20000000_1slot_post7[i]); + } +#endif + +#if 0 + //----------------------- Start Sequence ------------------------ + // + // [45:40] -> ecpri par + // [39:32] -> ecpri user + // [31:31] -> stall + // [30:30] -> AllNum Sel + // [29:28] -> ZNum or YNum send end + // [27:27] -> ZNum or AllNum + // [26:24] -> ecpri end + // [23:23] -> flush + // [22:18] -> DMA Tag + // [17:13] -> dest DMA config buffer id + // [12: 8] -> soure DMA config buffer id + // [ 7: 7] -> continue the last DMA + // [ 6: 6] -> continue the next DMA + // [ 5: 5] -> cachable, used to read DDR, cci (axi1 port) + // [ 4: 4] -> enable 3D + // [ 3: 2] -> W , 00: Normal 01 ; 01: One Dimo List without num ; 10: One Dimo List with num ; 11 : Two Dimo List ; + // [ 1: 0] -> R , 00: Normal 01 ; 01: One Dimo List without num ; 10: One Dimo List with num ; 11 : Two Dimo List ; + //# JS_CSU_CMDFIFO0 = (1<<30)+(0x0<<18)+(2<<13)+(0<<8)+(0<<5)+(1<<4)+0; // rx0 --> SM1 _ + //# JS_CSU_CMDFIFO2 = (1<<30)+(0x1<<18)+(3<<13)+(0<<8)+(1<<5)+(1<<4)+0; // rx1 --> SM2 / + //# JS_CSU_CMDFIFO1 = (0<<30)+(0x2<<18)+(0<<13)+(1<<8)+(0<<5)+(1<<4)+0; // tx <-- SM0 / + ucp_reg32_write(JS_CSU_CMDFIFO0, (1<<30)+(0x0<<18)+(2<<13)+(0<<8)+(0<<5)+(1<<4)+0); + ucp_reg32_write(JS_CSU_CMDFIFO2, (1<<30)+(0x1<<18)+(3<<13)+(0<<8)+(1<<5)+(1<<4)+0); + ucp_reg32_write(JS_CSU_CMDFIFO1, (0<<30)+(0x2<<18)+(0<<13)+(1<<8)+(0<<5)+(1<<4)+0); + // > diff glb _ + //# JS_CSU_CMDFIFO0 = (1<<30)+(0x3<<18)+(5<<13)+(0<<8)+(0<<5)+(1<<4)+0; // rx0 --> SM4 / diff tag id | + //# JS_CSU_CMDFIFO2 = (1<<30)+(0x4<<18)+(6<<13)+(0<<8)+(1<<5)+(1<<4)+0; // rx1 --> SM5 / | + //# JS_CSU_CMDFIFO1 = (0<<30)+(0x5<<18)+(0<<13)+(4<<8)+(0<<5)+(1<<4)+0; // tx <-- SM3 _/ | | + ucp_reg32_write(JS_CSU_CMDFIFO0, (1<<30)+(0x3<<18)+(5<<13)+(0<<8)+(0<<5)+(1<<4)+0); + ucp_reg32_write(JS_CSU_CMDFIFO2, (1<<30)+(0x4<<18)+(6<<13)+(0<<8)+(1<<5)+(1<<4)+0); + ucp_reg32_write(JS_CSU_CMDFIFO1, (0<<30)+(0x5<<18)+(0<<13)+(4<<8)+(0<<5)+(1<<4)+0); + // | same glb | + //JS_CSU_CMDFIFO0 = (1<<30)+(0x6<<18)+(2<<13)+(0<<8)+(0<<5)+(1<<4)+0; // rx0 --> SM1 _ |same tag id > repeat 2 times + //JS_CSU_CMDFIFO2 = (1<<30)+(0x7<<18)+(3<<13)+(0<<8)+(1<<5)+(1<<4)+0; // rx1 --> SM2 / | | + //JS_CSU_CMDFIFO1 = (0<<30)+(0x8<<18)+(0<<13)+(1<<8)+(0<<5)+(1<<4)+0; // tx <-- SM0 / V | + // // > diff glb | + //JS_CSU_CMDFIFO0 = (1<<30)+(0x9<<18)+(5<<13)+(0<<8)+(0<<5)+(1<<4)+0; // rx0 --> SM4 / diff tag id _| + //JS_CSU_CMDFIFO2 = (1<<30)+(0xa<<18)+(6<<13)+(0<<8)+(1<<5)+(1<<4)+0; // rx1 --> SM5 / + //JS_CSU_CMDFIFO1 = (0<<30)+(0xb<<18)+(0<<13)+(4<<8)+(0<<5)+(1<<4)+0; // tx <-- SM3 _/ + + //JS_CSU_TAGMASK0 = 0x1<<0; + //JS_CSU_TAGMASK2 = 0x1<<1; + //JS_CSU_TAGMASK1 = 0x1<<2; + //JS_CSU_INTMASK = (BIT12|BIT13|BIT14); + + printf("CMDFIFO1_NUM 3: %X\n", ucp_reg32_read(JS_CSU_CMDFIFO1_NUM)); + printf("CSU_DMASTATUS: %X\n", ucp_reg32_read(JS_CSU_DMASTATUS)); + //----------------------- Wait DMA finish ------------------------ + //# while(!(JS_CSU_DMASTATUS&BIT0)); + while(!(ucp_reg32_read(JS_CSU_DMASTATUS) & BIT0)); + printf("DMA 1th tag0(jesd-rx0) has finished.\n"); + + //# while(!(JS_CSU_DMASTATUS&BIT1)); + //while(!(ucp_reg32_read(JS_CSU_DMASTATUS) & BIT1)); + //printf("DMA 1th tag1(jesd-rx1) has finished.\n"); + + //# while(!(JS_CSU_DMASTATUS&BIT2)); + while(!(ucp_reg32_read(JS_CSU_DMASTATUS) & BIT2)); + printf("DMA 1th tag2(jesd-tx ) has finished.\n"); + + //# while(!(JS_CSU_DMASTATUS&BIT3)); + while(!(ucp_reg32_read(JS_CSU_DMASTATUS) & BIT3)); + printf("DMA 1th tag3(jesd-rx0) has finished.\n"); + + //# while(!(JS_CSU_DMASTATUS&BIT4)); + //while(!(ucp_reg32_read(JS_CSU_DMASTATUS) & BIT4)); + //printf("DMA 1th tag4(jesd-rx1) has finished.\n"); + + //# while(!(JS_CSU_DMASTATUS&BIT5)); + while(!(ucp_reg32_read(JS_CSU_DMASTATUS) & BIT5)); + printf("DMA 1th tag5(jesd-tx ) has finished.\n"); + + //---------------------------- End ----------------------------- +#endif + + return; +} + +// [45:40] -> ecpri par +// [39:32] -> ecpri user +// [31:31] -> stall +// [30:30] -> AllNum Sel: 0 src 1 des +// [29:28] -> ZNum or YNum send end +// [27:27] -> ZNum or AllNum +// [26:24] -> ecpri end +// [23:23] -> flush +// [22:18] -> DMA Tag +// [17:13] -> dest DMA config buffer id +// [12: 8] -> soure DMA config buffer id +// [ 7: 7] -> continue the last DMA +// [ 6: 6] -> continue the next DMA +// [ 5: 5] -> cachable, used to read DDR, cci (axi1 port) +// [ 4: 4] -> enable 3D +// [ 3: 2] -> W , 00: Normal 01 ; 01: One Dimo List without num ; 10: One Dimo List with num ; 11 : Two Dimo List ; +// [ 1: 0] -> R , 00: Normal 01 ; 01: One Dimo List without num ; 10: One Dimo List with num ; 11 : Two Dimo List ; +void js_csu_ioctrl_tx (void) +{ + ucp_reg32_write(JS_CSU_CMDFIFO1, (0<<30)+(0x3<<18)+(0<<13)+(4<<8)+(0<<5)+(1<<4)+0); + while(!(ucp_reg32_read(JS_CSU_DMASTATUS) & BIT3)) {}; + + ucp_reg32_write(JS_CSU_CMDFIFO1, (0<<30)+(0x4<<18)+(0<<13)+(5<<8)+(0<<5)+(1<<4)+0); + while(!(ucp_reg32_read(JS_CSU_DMASTATUS) & BIT4)) {}; + +#if 0 + ucp_reg32_write(JS_CSU_CMDFIFO1, (0<<30)+(0x5<<18)+(0<<13)+(6<<8)+(1<<5)+(1<<4)+0); + while(!(ucp_reg32_read(JS_CSU_DMASTATUS) & BIT5)); +#endif +} + +void js_csu_ioctrl_rx (void) +{ + ucp_reg32_write(JS_CSU_CMDFIFO0, (1<<30)+(0x0<<18)+(1<<13)+(0<<8)+(0<<5)+(1<<4)+0); + while(!(ucp_reg32_read(JS_CSU_DMASTATUS) & BIT0)); + + ucp_reg32_write(JS_CSU_CMDFIFO0, (1<<30)+(0x1<<18)+(2<<13)+(0<<8)+(0<<5)+(1<<4)+0); + while(!(ucp_reg32_read(JS_CSU_DMASTATUS) & BIT1)); + + ucp_reg32_write(JS_CSU_CMDFIFO0, (1<<30)+(0x2<<18)+(3<<13)+(0<<8)+(0<<5)+(1<<4)+0); + while(!(ucp_reg32_read(JS_CSU_DMASTATUS) & BIT2)); +} + + +static void js_csu_loc_cfg(uint32_t all) +{ + ucp_reg32_write(JS_CSU_DMAADDRL0 , 0x0); + ucp_reg32_write(JS_CSU_DMAADDRH0 , 0x0); + ucp_reg32_write(JS_CSU_DMAYSTEPL0 , 0x20); + ucp_reg32_write(JS_CSU_DMAYSTEPH0 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL0 , 0x20); + ucp_reg32_write(JS_CSU_DMAZSTEPH0 , 0x0); + ucp_reg32_write(JS_CSU_DMAYNUMXNUM0 , (1<<16)+0x20); + ucp_reg32_write(JS_CSU_DMASIZEGRANALLNUM0 , (0x0<<28)+(0x8<<24)+all); +} + +static void js_csu_glb_cfg(uint64_t addr, uint32_t all, uint32_t id) +{ + if(id == 0x1){ + ucp_reg32_write(JS_CSU_DMAADDRL1 , addr&0xffffffff); + ucp_reg32_write(JS_CSU_DMAADDRH1 , addr>>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL1 , 0x80); + ucp_reg32_write(JS_CSU_DMAYSTEPH1 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL1 , all/0x80*0x80); + ucp_reg32_write(JS_CSU_DMAZSTEPH1 , 0x0); + ucp_reg32_write(JS_CSU_DMAYNUMXNUM1 , ((all/0x80)<<16)+0x80); + ucp_reg32_write(JS_CSU_DMASIZEGRANALLNUM1 , (0x7<<28)+(0xd<<24)+all); + }else if(id == 0x2){ + ucp_reg32_write(JS_CSU_DMAADDRL2 , addr&0xffffffff); + ucp_reg32_write(JS_CSU_DMAADDRH2 , addr>>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL2 , 0x80); + ucp_reg32_write(JS_CSU_DMAYSTEPH2 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL2 , all/0x80*0x80); + ucp_reg32_write(JS_CSU_DMAZSTEPH2 , 0x0); + ucp_reg32_write(JS_CSU_DMAYNUMXNUM2 , ((all/0x80)<<16)+0x80); + ucp_reg32_write(JS_CSU_DMASIZEGRANALLNUM2 , (0x7<<28)+(0xd<<24)+all); + }else if(id == 0x3){ + ucp_reg32_write(JS_CSU_DMAADDRL3 , addr&0xffffffff); + ucp_reg32_write(JS_CSU_DMAADDRH3 , addr>>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL3 , 0x80); + ucp_reg32_write(JS_CSU_DMAYSTEPH3 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL3 , all/0x80*0x80); + ucp_reg32_write(JS_CSU_DMAZSTEPH3 , 0x0); + ucp_reg32_write(JS_CSU_DMAYNUMXNUM3 , ((all/0x80)<<16)+0x80); + ucp_reg32_write(JS_CSU_DMASIZEGRANALLNUM3 , (0x7<<28)+(0xd<<24)+all); + }else if(id == 0x4){ + ucp_reg32_write(JS_CSU_DMAADDRL4 , addr&0xffffffff); + ucp_reg32_write(JS_CSU_DMAADDRH4 , addr>>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL4 , 0x80); + ucp_reg32_write(JS_CSU_DMAYSTEPH4 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL4 , all/0x80*0x80); + ucp_reg32_write(JS_CSU_DMAZSTEPH4 , 0x0); + ucp_reg32_write(JS_CSU_DMAYNUMXNUM4 , ((all/0x80)<<16)+0x80); + ucp_reg32_write(JS_CSU_DMASIZEGRANALLNUM4 , (0x7<<28)+(0xd<<24)+all); + }else if(id == 0x5){ + ucp_reg32_write(JS_CSU_DMAADDRL5 , addr&0xffffffff); + ucp_reg32_write(JS_CSU_DMAADDRH5 , addr>>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL5 , 0x80); + ucp_reg32_write(JS_CSU_DMAYSTEPH5 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL5 , all/0x80*0x80); + ucp_reg32_write(JS_CSU_DMAZSTEPH5 , 0x0); + ucp_reg32_write(JS_CSU_DMAYNUMXNUM5 , ((all/0x80)<<16)+0x80); + ucp_reg32_write(JS_CSU_DMASIZEGRANALLNUM5 , (0x7<<28)+(0xd<<24)+all); + }else if(id == 0x6){ + ucp_reg32_write(JS_CSU_DMAADDRL6 , addr&0xffffffff); + ucp_reg32_write(JS_CSU_DMAADDRH6 , addr>>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL6 , 0x80); + ucp_reg32_write(JS_CSU_DMAYSTEPH6 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL6 , all/0x80*0x80); + ucp_reg32_write(JS_CSU_DMAZSTEPH6 , 0x0); + ucp_reg32_write(JS_CSU_DMAYNUMXNUM6 , ((all/0x80)<<16)+0x80); + ucp_reg32_write(JS_CSU_DMASIZEGRANALLNUM6 , (0x7<<28)+(0xd<<24)+all); + }else if(id == 0x7){ + ucp_reg32_write(JS_CSU_DMAADDRL7 , addr&0xffffffff); + ucp_reg32_write(JS_CSU_DMAADDRH7 , addr>>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL7 , 0x80); + ucp_reg32_write(JS_CSU_DMAYSTEPH7 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL7 , all/0x80*0x80); + ucp_reg32_write(JS_CSU_DMAZSTEPH7 , 0x0); + ucp_reg32_write(JS_CSU_DMAYNUMXNUM7 , ((all/0x80)<<16)+0x80); + ucp_reg32_write(JS_CSU_DMASIZEGRANALLNUM7 , (0x7<<28)+(0xd<<24)+all); + }else if(id == 0x8){ + ucp_reg32_write(JS_CSU_DMAADDRL8 , addr&0xffffffff); + ucp_reg32_write(JS_CSU_DMAADDRH8 , addr>>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL8 , 0x80); + ucp_reg32_write(JS_CSU_DMAYSTEPH8 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL8 , all/0x80*0x80); + ucp_reg32_write(JS_CSU_DMAZSTEPH8 , 0x0); + ucp_reg32_write(JS_CSU_DMAYNUMXNUM8 , ((all/0x80)<<16)+0x80); + ucp_reg32_write(JS_CSU_DMASIZEGRANALLNUM8 , (0x7<<28)+(0xd<<24)+all); + }else if(id == 0x9){ + ucp_reg32_write(JS_CSU_DMAADDRL9 , addr&0xffffffff); + ucp_reg32_write(JS_CSU_DMAADDRH9 , addr>>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL9 , 0x80); + ucp_reg32_write(JS_CSU_DMAYSTEPH9 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL9 , all/0x80*0x80); + ucp_reg32_write(JS_CSU_DMAZSTEPH9 , 0x0); + ucp_reg32_write(JS_CSU_DMAYNUMXNUM9 , ((all/0x80)<<16)+0x80); + ucp_reg32_write(JS_CSU_DMASIZEGRANALLNUM9 , (0x7<<28)+(0xd<<24)+all); + }else if(id == 0xa){ + ucp_reg32_write(JS_CSU_DMAADDRL10 , addr&0xffffffff); + ucp_reg32_write(JS_CSU_DMAADDRH10 , addr>>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL10 , 0x80); + ucp_reg32_write(JS_CSU_DMAYSTEPH10 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL10 , all/0x80*0x80); + ucp_reg32_write(JS_CSU_DMAZSTEPH10 , 0x0); + ucp_reg32_write(JS_CSU_DMAYNUMXNUM10 , ((all/0x80)<<16)+0x80); + ucp_reg32_write(JS_CSU_DMASIZEGRANALLNUM10 , (0x7<<28)+(0xd<<24)+all); + }else if(id == 0xb){ + ucp_reg32_write(JS_CSU_DMAADDRL11 , addr&0xffffffff); + ucp_reg32_write(JS_CSU_DMAADDRH11 , addr>>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL11 , 0x80); + ucp_reg32_write(JS_CSU_DMAYSTEPH11 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL11 , all/0x80*0x80); + ucp_reg32_write(JS_CSU_DMAZSTEPH11 , 0x0); + ucp_reg32_write(JS_CSU_DMAYNUMXNUM11 , ((all/0x80)<<16)+0x80); + ucp_reg32_write(JS_CSU_DMASIZEGRANALLNUM11 , (0x7<<28)+(0xd<<24)+all); + }else if(id == 0xc){ + ucp_reg32_write(JS_CSU_DMAADDRL12 , addr&0xffffffff); + ucp_reg32_write(JS_CSU_DMAADDRH12 , addr>>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL12 , 0x80); + ucp_reg32_write(JS_CSU_DMAYSTEPH12 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL12 , all/0x80*0x80); + ucp_reg32_write(JS_CSU_DMAZSTEPH12 , 0x0); + ucp_reg32_write(JS_CSU_DMAYNUMXNUM12 , ((all/0x80)<<16)+0x80); + ucp_reg32_write(JS_CSU_DMASIZEGRANALLNUM12 , (0x7<<28)+(0xd<<24)+all); + }else if(id == 0xd){ + ucp_reg32_write(JS_CSU_DMAADDRL13 , addr&0xffffffff); + ucp_reg32_write(JS_CSU_DMAADDRH13 , addr>>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL13 , 0x80); + ucp_reg32_write(JS_CSU_DMAYSTEPH13 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL13 , all/0x80*0x80); + ucp_reg32_write(JS_CSU_DMAZSTEPH13 , 0x0); + ucp_reg32_write(JS_CSU_DMAYNUMXNUM13 , ((all/0x80)<<16)+0x80); + ucp_reg32_write(JS_CSU_DMASIZEGRANALLNUM13 , (0x7<<28)+(0xd<<24)+all); + }else if(id == 0xd){ + ucp_reg32_write(JS_CSU_DMAADDRL14 , addr&0xffffffff); + ucp_reg32_write(JS_CSU_DMAADDRH14 , addr>>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL14 , 0x80); + ucp_reg32_write(JS_CSU_DMAYSTEPH14 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL14 , all/0x80*0x80); + ucp_reg32_write(JS_CSU_DMAZSTEPH14 , 0x0); + ucp_reg32_write(JS_CSU_DMAYNUMXNUM14 , ((all/0x80)<<16)+0x80); + ucp_reg32_write(JS_CSU_DMASIZEGRANALLNUM14 , (0x7<<28)+(0xd<<24)+all); + }else if(id == 0xf){ + ucp_reg32_write(JS_CSU_DMAADDRL15 , addr&0xffffffff); + ucp_reg32_write(JS_CSU_DMAADDRH15 , addr>>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL15 , 0x80); + ucp_reg32_write(JS_CSU_DMAYSTEPH15 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL15 , all/0x80*0x80); + ucp_reg32_write(JS_CSU_DMAZSTEPH15 , 0x0); + ucp_reg32_write(JS_CSU_DMAYNUMXNUM15 , ((all/0x80)<<16)+0x80); + ucp_reg32_write(JS_CSU_DMASIZEGRANALLNUM15 , (0x7<<28)+(0xd<<24)+all); + }else{ + printf("The id is invalid!"); + } +} + +static void js_csu_glb_cfg_sep(uint64_t addr, uint32_t all, uint32_t id, uint32_t sep_num, uint32_t sep_margin) +{ + if(id == 0x1){ + ucp_reg32_write(JS_CSU_DMAADDRL1 , addr&0xffffffff); + ucp_reg32_write(JS_CSU_DMAADDRH1 , addr>>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL1 , all/sep_num); + ucp_reg32_write(JS_CSU_DMAYSTEPH1 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL1 , 32*(1<>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL2 , all/sep_num); + ucp_reg32_write(JS_CSU_DMAYSTEPH2 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL2 , 32*(1<>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL3 , all/sep_num); + ucp_reg32_write(JS_CSU_DMAYSTEPH3 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL3 , 32*(1<>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL4 , all/sep_num); + ucp_reg32_write(JS_CSU_DMAYSTEPH4 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL4 , 32*(1<>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL5 , all/sep_num); + ucp_reg32_write(JS_CSU_DMAYSTEPH5 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL5 , 32*(1<>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL6 , all/sep_num); + ucp_reg32_write(JS_CSU_DMAYSTEPH6 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL6 , 32*(1<>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL7 , all/sep_num); + ucp_reg32_write(JS_CSU_DMAYSTEPH7 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL7 , 32*(1<>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL8 , all/sep_num); + ucp_reg32_write(JS_CSU_DMAYSTEPH8 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL8 , 32*(1<>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL9 , all/sep_num); + ucp_reg32_write(JS_CSU_DMAYSTEPH9 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL9 , 32*(1<>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL10 , all/sep_num); + ucp_reg32_write(JS_CSU_DMAYSTEPH10 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL10 , 32*(1<>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL11 , all/sep_num); + ucp_reg32_write(JS_CSU_DMAYSTEPH11 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL11 , 32*(1<>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL12 , all/sep_num); + ucp_reg32_write(JS_CSU_DMAYSTEPH12 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL12 , 32*(1<>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL13 , all/sep_num); + ucp_reg32_write(JS_CSU_DMAYSTEPH13 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL13 , 32*(1<>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL14 , all/sep_num); + ucp_reg32_write(JS_CSU_DMAYSTEPH14 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL14 , 32*(1<>32); + ucp_reg32_write(JS_CSU_DMAYSTEPL15 , all/sep_num); + ucp_reg32_write(JS_CSU_DMAYSTEPH15 , 0x0); + ucp_reg32_write(JS_CSU_DMAZSTEPL15 , 32*(1<1 && bit_division<=2){ + return 1; + } else if(bit_division>2 && bit_division<=4){ + return 2; + } else if(bit_division>4 && bit_division<=8){ + return 3; + } + + return 4; +} + +static uint32_t cal_lmfc_lemc_delay(uint32_t coding_type, + uint32_t f, + uint32_t k, + uint32_t e) +{ + if(coding_type){ // LEMC + return 32*e; + } else { // LMFC + return f*k/4; + } +} + +void ucp_jesd_pcsReset(void) +{ + ucp_reg32_write(JS_PMA0_PCS_SOFT_RESET, 0x8FFF); + usleep(1000); + ucp_reg32_write(JS_PMA0_PCS_SOFT_RESET, 0x0); + usleep(10); +} + +void ucp_cofigPrbsSend(uint8_t prbsIndex) +{ + + ucp_reg32_write(JS_PMA0_PCS_BIT_REV_CTRL, 0x001); + if (0 == prbsIndex) + { + ucp_reg32_write(JS_PMA0_PCS_PRBS_UDP_SEND, 0xf0); // daya debug PRBS31 SEND + printf("ucpSend_PRBS31\n"); + } + else + { + ucp_reg32_write(JS_PMA0_PCS_PRBS_UDP_SEND, 0xf); // daya debug PRBS9 SEND + printf("ucpSend_PRBS9\n"); + } +} + +void ucp_insertPrbsErr (void) +{ + ucp_reg32_write(JS_PMA0_PCS_PRBS_SEND_ERRINS, 0xf); +} + +void ucp_cofigPrbsCheck(uint8_t prbsIndex) +{ + ucp_reg32_write(JS_PMA0_PCS_BIT_REV_CTRL, 0x001); + if (0 == prbsIndex) + { + ucp_reg32_write(JS_PMA0_PCS_PRBS_UDP_CHK, 0xf0); // daya debug PRBS31 check + printf("ucpCheck_PRBS31\n"); + } + else + { + ucp_reg32_write(JS_PMA0_PCS_PRBS_UDP_CHK, 0xf); // daya debug PRBS9 check + printf("ucpCheck_PRBS9\n"); + } +} + +void ucp_cofigPrbsFarEndLoopBack (void) +{ + ucp_reg32_write(JS_PMA0_PCS_LOOPBACK_CTRL, 0x10); + printf("ucpFarEndLoopback\n"); +} + +void ucp_cofigPrbsNearEndLoopBack (void) +{ + ucp_reg32_write(JS_PMA0_PCS_LOOPBACK_CTRL, 0x1); + printf("ucpNearEndLoopback\n"); +} + +void ucp_resetPrbsCheckCount (void) +{ + ucp_reg32_write(JS_PMA0_PCS_LOOPBACK_CTRL, 0x1); + printf("ucpNearEndLoopback\n"); +} + +void ucp_prbsCheckCount (void) +{ + printf("ucpPrbs: %d %d %d %d\n", + ucp_reg32_read (JS_PMA0_PCS_RXPRBS_ERRCNT_L0), + ucp_reg32_read (JS_PMA0_PCS_RXPRBS_ERRCNT_L1), + ucp_reg32_read (JS_PMA0_PCS_RXPRBS_ERRCNT_L2), + ucp_reg32_read (JS_PMA0_PCS_RXPRBS_ERRCNT_L3)); + +} + +uint32_t ucp_linkTestCount1(void) // for K code +{ + return ucp_reg32_read(JS_COMC_204B_RX1_LINKTEST_1_RECEIVECOUNTER); +} + +void ucp_jesd204_interrupt(uint8_t en) +{ + if (en) + { + ucp_reg32_write(JS_COMC_204B_RX1_CORE_INTERRUPT_MASK, 0); + } + else + { + ucp_reg32_write(JS_COMC_204B_RX1_CORE_INTERRUPT_MASK, 0xFFFFFFFF); + } +} + +void ucp_configRxFeature(void) +{ + // ucp_reg32_write(JS_COMC_204C_RX0_FEATURE_DISABLE, 0x9F); +} + +void wno_unused_myheadername(void) +{ + /* don't need to actually call the functions to avoid the warnings */ + (void)&js_csu_glb_cfg; + (void)&ucp4008_jesd_pma_print; + (void)&ucp4008_jesd_crg_print; + return; + } + diff --git a/driver/rfic/ucp/base/src/ucp_jesd.o b/driver/rfic/ucp/base/src/ucp_jesd.o new file mode 100644 index 0000000..629980e Binary files /dev/null and b/driver/rfic/ucp/base/src/ucp_jesd.o differ diff --git a/driver/rfic/ucp/base/src/ucp_jesd_gpio.c b/driver/rfic/ucp/base/src/ucp_jesd_gpio.c new file mode 100644 index 0000000..a2e7908 --- /dev/null +++ b/driver/rfic/ucp/base/src/ucp_jesd_gpio.c @@ -0,0 +1,641 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_jesd_gpio.c +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2022-09-08 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#include +#include +#include +#include +#include "ucp_jesd_gpio.h" +#include "ucp_reg_io.h" +#include "dw_apb_gpio.h" +#include "ucp_rfc.h" +#include "ucp_sfr_c.h" +#include "ucp_param.h" +#include "ucp_api_jesd.h" +#include "ucp_jsonTools.h" +#include "ucp_hardware.h" + +#define GPIO_INVERSE_ENABLELEVEL(a) (a ? ((UCP_JESD_TRX_GPIO_VALID_LOW == a) ? UCP_JESD_TRX_GPIO_VALID_HIGH : UCP_JESD_TRX_GPIO_VALID_LOW) : a) +#define GPIO_RF_ON_PIN_LEVEL(a) ((UCP_JESD_TRX_GPIO_VALID_HIGH == a) ? 1 : 0) +#define GPIO_RF_OFF_PIN_LEVEL(a) ((UCP_JESD_TRX_GPIO_VALID_HIGH == a) ? 0 : 1) + +// ------------------------------------------------------- +// | hardware GPIO pin | software GPIO pin | +// | GPIO0A0-GPIO0A31 | 480~511 | +// | GPIO0B0-GPIO0B31 | 448~479 | +// | GPIO1A0-GPIO1A14 | 433~447 | +// | GPIO1B0-GPIO1B31 | 401~432 | +// ------------------------------------------------------- +const tUcpGpioRegTable_t infRegPort0AP_A[] = { +/*480 AP_GPIO0A0 */ {PA_PMUX_REG, (BIT0 | BIT1), (BIT0 | BIT1), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT0}, +/*481 AP_GPIO0A1 */ {PA_PMUX_REG, (BIT2 | BIT3), (BIT2 | BIT3), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT1}, +/*482 AP_GPIO0A2 */ {PA_PMUX_REG, (BIT4 | BIT5), (BIT4 | BIT5), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT2}, +/*483 AP_GPIO0A3 */ {PA_PMUX_REG, (BIT6 | BIT7), (BIT6 | BIT7), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT3}, +/*484 AP_GPIO0A4 */ {PA_PMUX_REG, (BIT8 | BIT9), (BIT8 | BIT9), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT4}, +/*485 AP_GPIO0A5 */ {PA_PMUX_REG, (BIT10| BIT11), (BIT10| BIT11), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT5}, +/*486 AP_GPIO0A6 */ {PA_PMUX_REG, (BIT12| BIT13), (BIT12| BIT13), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT6}, +/*487 AP_GPIO0A7 */ {PA_PMUX_REG, (BIT14| BIT15), (BIT14| BIT15), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT7}, +/*488 AP_GPIO0A8 */ {PA_PMUX_REG, (BIT16| BIT17), (BIT16| BIT17), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT8}, +/*489 AP_GPIO0A9 */ {PA_PMUX_REG, (BIT18| BIT19), (BIT18| BIT19), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT9}, +/*490 AP_GPIO0A10 */ {PA_PMUX_REG, (BIT20| BIT21), (BIT20| BIT21), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT10}, +/*491 AP_GPIO0A11 */ {PA_PMUX_REG, (BIT22| BIT23), (BIT22| BIT23), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT11}, +/*492 AP_GPIO0A12 */ {PA_PMUX_REG, (BIT24| BIT25), (BIT24| BIT25), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT12}, +/*493 AP_GPIO0A13 */ {PA_PMUX_REG, (BIT26| BIT27), (BIT26| BIT27), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT13}, +/*494 AP_GPIO0A14 */ {PA_PMUX_REG, (BIT28| BIT29), (BIT28| BIT29), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT14}, +/*495 AP_GPIO0A15 */ {PD_PMUX0_REG, (BIT0 | BIT1), (BIT0 | BIT1), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT15}, +/*496 AP_GPIO0A16 */ {PD_PMUX0_REG, (BIT2 | BIT3), (BIT2 | BIT3), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT16}, +/*497 AP_GPIO0A17 */ {PD_PMUX0_REG, (BIT4 | BIT5), (BIT4 | BIT5), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT17}, +/*498 AP_GPIO0A18 */ {PD_PMUX0_REG, (BIT6 | BIT7), (BIT6 | BIT7), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT18}, +/*499 AP_GPIO0A19 */ {PD_PMUX0_REG, (BIT8 | BIT9), (BIT8 | BIT9), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT19}, +/*500 AP_GPIO0A20 */ {PD_PMUX0_REG, (BIT10| BIT11), (BIT10| BIT11), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT20}, +/*501 AP_GPIO0A21 */ {PD_PMUX0_REG, (BIT12| BIT13), (BIT12| BIT13), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT21}, +/*502 AP_GPIO0A22 */ {PD_PMUX0_REG, (BIT14| BIT15), (BIT14| BIT15), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT22}, +/*503 AP_GPIO0A23 */ {PD_PMUX0_REG, (BIT16| BIT17), (BIT16| BIT17), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT23}, +/*504 AP_GPIO0A24 */ {PB_PMUX_REG, (BIT18| BIT19), (BIT18| BIT19), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT24}, +/*505 AP_GPIO0A25 */ {PB_PMUX_REG, (BIT20| BIT21), (BIT20| BIT21), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT25}, +/*506 AP_GPIO0A26 */ {PB_PMUX_REG, (BIT22| BIT23), (BIT22| BIT23), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT26}, +/*507 AP_GPIO0A27 */ {PB_PMUX_REG, (BIT24| BIT25), (BIT24| BIT25), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT27}, +/*508 AP_GPIO0A28 */ {PB_PMUX_REG, (BIT26| BIT27), (BIT26| BIT27), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT28}, +/*509 AP_GPIO0A29 */ {PB_PMUX_REG, (BIT28| BIT29), (BIT28| BIT29), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT29}, +/*510 AP_GPIO0A30 */ {PC_PMUX_REG, (BIT0 | BIT1), (BIT0 | BIT1), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT30}, +/*511 AP_GPIO0A31 */ {PC_PMUX_REG, (BIT2 | BIT3), (BIT2 | BIT3), GPIO0_SWPORTA_DDR, GPIO0_SWPORTA_DR, BIT31} +}; + +const tUcpGpioRegTable_t infRegPort0AP_B[] = { +/*448 AP_GPIO0B0 */ {PC_PMUX_REG, (BIT4 | BIT5), (BIT4 | BIT5), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT0}, +/*449 AP_GPIO0B1 */ {PC_PMUX_REG, (BIT6 | BIT7), (BIT6 | BIT7), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT1}, +/*450 AP_GPIO0B2 */ {PA_PMUX_REG, (BIT8 | BIT9), (BIT8 | BIT9), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT2}, +/*451 AP_GPIO0B3 */ {PC_PMUX_REG, (BIT10| BIT11), (BIT10| BIT11), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT3}, +/*452 AP_GPIO0B4 */ {PC_PMUX_REG, (BIT12| BIT13), (BIT12| BIT13), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT4}, +/*453 AP_GPIO0B5 */ {PC_PMUX_REG, (BIT14| BIT15), (BIT14| BIT15), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT5}, +/*454 AP_GPIO0B6 */ {PC_PMUX_REG, (BIT16| BIT17), (BIT16| BIT17), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT6}, +/*455 AP_GPIO0B7 */ {PC_PMUX_REG, (BIT18| BIT19), (BIT18| BIT19), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT7}, +/*456 AP_GPIO0B8 */ {PC_PMUX_REG, (BIT20| BIT21), (BIT20| BIT21), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT8}, +/*457 AP_GPIO0B9 */ {PC_PMUX_REG, (BIT22| BIT23), (BIT22| BIT23), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT9}, +/*458 AP_GPIO0B10 */ {PC_PMUX_REG, (BIT24| BIT25), (BIT24| BIT25), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT10}, +/*459 AP_GPIO0B11 */ {PC_PMUX_REG, (BIT26| BIT27), (BIT26| BIT27), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT11}, +/*460 AP_GPIO0B12 */ {PC_PMUX_REG, (BIT28| BIT29), (BIT28| BIT29), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT12}, +/*461 AP_GPIO0B13 */ {PD_PMUX0_REG, ( BIT0), (BIT0 | BIT1), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT13}, +/*462 AP_GPIO0B14 */ {PD_PMUX0_REG, ( BIT2), (BIT2 | BIT3), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT14}, +/*463 AP_GPIO0B15 */ {PD_PMUX0_REG, ( 0x00), (BIT4 | BIT5), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT15}, +/*464 AP_GPIO0B16 */ {PD_PMUX0_REG, ( 0x00), (BIT6 | BIT7), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT16}, +/*465 AP_GPIO0B17 */ {PD_PMUX0_REG, ( 0x00), (BIT8 | BIT9), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT17}, +/*466 AP_GPIO0B18 */ {PD_PMUX0_REG, ( 0x00), (BIT10| BIT11), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT18}, +/*467 AP_GPIO0B19 */ {PD_PMUX0_REG, ( 0x00), (BIT12| BIT13), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT19}, +/*468 AP_GPIO0B20 */ {PD_PMUX0_REG, ( 0x00), (BIT14| BIT15), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT20}, +/*469 AP_GPIO0B21 */ {PD_PMUX0_REG, ( 0x00), (BIT16| BIT17), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT21}, +/*470 AP_GPIO0B22 */ {PD_PMUX0_REG, ( 0x00), (BIT18| BIT19), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT22}, +/*471 AP_GPIO0B23 */ {PD_PMUX0_REG, (BIT20| BIT21), (BIT20| BIT21), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT23}, +/*472 AP_GPIO0B24 */ {PD_PMUX0_REG, (BIT22| BIT23), (BIT22| BIT23), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT24}, +/*473 AP_GPIO0B25 */ {PD_PMUX0_REG, (BIT24| BIT25), (BIT24| BIT25), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT25}, +/*474 AP_GPIO0B26 */ {PD_PMUX0_REG, (BIT26| BIT27), (BIT26| BIT27), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT26}, +/*475 AP_GPIO0B27 */ {PD_PMUX0_REG, (BIT28| BIT29), (BIT28| BIT29), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT27}, +/*476 AP_GPIO0B28 */ {PD_PMUX0_REG, (BIT30| BIT31), (BIT30| BIT31), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT28}, +/*477 AP_GPIO0B29 */ {PD_PMUX1_REG, (BIT0 | BIT1), (BIT0 | BIT1), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT29}, +/*478 AP_GPIO0B30 */ {PD_PMUX1_REG, (BIT2 | BIT3), (BIT2 | BIT3), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT30}, +/*479 AP_GPIO0B31 */ {PD_PMUX1_REG, (BIT4 | BIT5), (BIT4 | BIT5), GPIO0_SWPORTB_DDR, GPIO0_SWPORTB_DR, BIT31} +}; + +const tUcpGpioRegTable_t infRegPort1CP_A[] = { +/*433 CP_GPIO1A0 */ {PD_PMUX1_REG, (BIT6 | BIT7), (BIT6 | BIT7), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT0}, +/*434 CP_GPIO1A1 */ {PD_PMUX1_REG, (BIT8 | BIT9), (BIT8 | BIT9), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT1}, +/*435 CP_GPIO1A2 */ {PD_PMUX1_REG, (BIT10| BIT11), (BIT10| BIT11), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT2}, +/*436 CP_GPIO1A3 */ {PE_PMUX_REG, (BIT0 | BIT1), (BIT0 | BIT1), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT3}, +/*437 CP_GPIO1A4 */ {PE_PMUX_REG, (BIT2 | BIT3), (BIT2 | BIT3), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT4}, +/*438 CP_GPIO1A5 */ {PE_PMUX_REG, (BIT4 | BIT5), (BIT4 | BIT5), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT5}, +/*439 CP_GPIO1A6 */ {PE_PMUX_REG, (BIT6 | BIT7), (BIT6 | BIT7), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT6}, +/*440 CP_GPIO1A7 */ {PE_PMUX_REG, (BIT8 | BIT9), (BIT8 | BIT9), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT7}, +/*441 CP_GPIO1A8 */ {PE_PMUX_REG, (BIT10| BIT11), (BIT10| BIT11), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT8}, +/*442 CP_GPIO1A9 */ {PE_PMUX_REG, (BIT12| BIT13), (BIT12| BIT13), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT9}, +/*443 CP_GPIO1A10 */ {PE_PMUX_REG, (BIT14| BIT15), (BIT14| BIT15), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT10}, +/*444 CP_GPIO1A11 */ {PE_PMUX_REG, (BIT16| BIT17), (BIT16| BIT17), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT11}, +/*445 CP_GPIO1A12 */ {PE_PMUX_REG, (BIT18| BIT19), (BIT18| BIT19), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT12}, +/*446 CP_GPIO1A13 */ {PE_PMUX_REG, (BIT20| BIT21), (BIT20| BIT21), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT13}, +/*447 CP_GPIO1A14 */ {PE_PMUX_REG, (BIT22| BIT23), (BIT22| BIT23), GPIO1_SWPORTA_DDR, GPIO1_SWPORTA_DR, BIT14}, +}; + +const tUcpGpioRegTable_t infRegPort1CP_B[] = { +/*401 CP_GPIO1B0 */ {LVDS_PMUX0_REG, (BIT0 | BIT1), (BIT0 | BIT1), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT0}, +/*402 CP_GPIO1B1 */ {LVDS_PMUX0_REG, (BIT2 | BIT3), (BIT2 | BIT3), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT1}, +/*403 CP_GPIO1B2 */ {LVDS_PMUX0_REG, (BIT4 | BIT5), (BIT4 | BIT5), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT2}, +/*404 CP_GPIO1B3 */ {LVDS_PMUX0_REG, (BIT6 | BIT7), (BIT6 | BIT7), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT3}, +/*405 CP_GPIO1B4 */ {LVDS_PMUX0_REG, (BIT8 | BIT9), (BIT8 | BIT9), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT4}, +/*406 CP_GPIO1B5 */ {LVDS_PMUX0_REG, (BIT10| BIT11), (BIT10| BIT11), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT5}, +/*407 CP_GPIO1B6 */ {LVDS_PMUX0_REG, (BIT12| BIT13), (BIT12| BIT13), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT6}, +/*408 CP_GPIO1B7 */ {LVDS_PMUX0_REG, (BIT14| BIT15), (BIT14| BIT15), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT7}, +/*409 CP_GPIO1B8 */ {LVDS_PMUX0_REG, (BIT16| BIT17), (BIT16| BIT17), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT8}, +/*410 CP_GPIO1B9 */ {LVDS_PMUX0_REG, (BIT18| BIT19), (BIT18| BIT19), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT9}, +/*411 CP_GPIO1B10 */ {LVDS_PMUX0_REG, (BIT20| BIT21), (BIT20| BIT21), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT10}, +/*412 CP_GPIO1B11 */ {LVDS_PMUX0_REG, (BIT22| BIT23), (BIT22| BIT23), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT11}, +/*413 CP_GPIO1B12 */ {LVDS_PMUX0_REG, (BIT24| BIT25), (BIT24| BIT25), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT12}, +/*414 CP_GPIO1B13 */ {LVDS_PMUX0_REG, (BIT26| BIT27), (BIT26| BIT27), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT13}, +/*415 CP_GPIO1B14 */ {LVDS_PMUX0_REG, (BIT28| BIT29), (BIT28| BIT29), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT14}, +/*416 CP_GPIO1B15 */ {LVDS_PMUX0_REG, (BIT30| BIT31), (BIT30| BIT31), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT15}, +/*417 CP_GPIO1B16 */ {LVDS_PMUX1_REG, (BIT0 | BIT1), (BIT0 | BIT1), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT16}, +/*418 CP_GPIO1B17 */ {LVDS_PMUX1_REG, (BIT2 | BIT3), (BIT2 | BIT3), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT17}, +/*419 CP_GPIO1B18 */ {LVDS_PMUX1_REG, (BIT4 | BIT5), (BIT4 | BIT5), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT18}, +/*420 CP_GPIO1B19 */ {LVDS_PMUX1_REG, (BIT6 | BIT7), (BIT6 | BIT7), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT19}, +/*421 CP_GPIO1B20 */ {LVDS_PMUX1_REG, (BIT8 | BIT9), (BIT8 | BIT9), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT20}, +/*422 CP_GPIO1B21 */ {LVDS_PMUX1_REG, (BIT10| BIT11), (BIT10| BIT11), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT21}, +/*423 CP_GPIO1B22 */ {LVDS_PMUX1_REG, (BIT12| BIT13), (BIT12| BIT13), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT22}, +/*424 CP_GPIO1B23 */ {LVDS_PMUX1_REG, (BIT14| BIT15), (BIT14| BIT15), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT23}, +/*425 CP_GPIO1B24 */ {LVDS_PMUX1_REG, (BIT16| BIT17), (BIT16| BIT17), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT24}, +/*426 CP_GPIO1B25 */ {LVDS_PMUX1_REG, (BIT18| BIT19), (BIT18| BIT19), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT25}, +/*427 CP_GPIO1B26 */ {LVDS_PMUX1_REG, (BIT20| BIT21), (BIT20| BIT21), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT26}, +/*428 CP_GPIO1B27 */ {LVDS_PMUX1_REG, (BIT22| BIT23), (BIT22| BIT23), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT27}, +/*429 CP_GPIO1B28 */ {LVDS_PMUX1_REG, (BIT24| BIT25), (BIT24| BIT25), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT28}, +/*430 CP_GPIO1B29 */ {LVDS_PMUX1_REG, (BIT26| BIT27), (BIT26| BIT27), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT29}, +/*431 CP_GPIO1B30 */ {LVDS_PMUX1_REG, (BIT28| BIT29), (BIT28| BIT29), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT30}, +/*432 CP_GPIO1B31 */ {LVDS_PMUX1_REG, (BIT30| BIT31), (BIT30| BIT31), GPIO1_SWPORTB_DDR, GPIO1_SWPORTB_DR, BIT31} +}; + +const tUcpGpioRegTable_t *pUcpGpioTable[] = {infRegPort0AP_A, infRegPort0AP_B, infRegPort1CP_A, infRegPort1CP_B}; +tGpioInfRegTable infRegTable[GPIO_INDEX_MAX]; +enum { + TR_IND_TX_TRX, TR_IND_TX_RF, TR_IND_TX_SW, + TR_IND_RX_TRX, TR_IND_RX_RF, TR_IND_RX_SW, + TR_IND_ORX_TRX, TR_IND_ORX_RF, TR_IND_ORX_SW, + TR_IND_TRIG +}; +static uint32_t trAnd[10][4], trXor[10][4]; + +static void ucp_jesd_gpioCfgInf2CSU (ucp_jesd_gpio_t *gpio, uint32_t bit2csuAddr) +{ + uint32_t bit, enValue; + + bit = 0; + enValue = 0; + + // port 0~3: AP_GPIO0A、AP_GPIO0B、CP_GPIO0A、CP_GPIO0B + if (gpio->enableLevel) + { + bit |= (1 << gpio->pin); + if (UCP_JESD_TRX_GPIO_VALID_HIGH == gpio->enableLevel) + { + enValue |= (1 << gpio->pin); + } + + ucp_reg32_or_write(bit2csuAddr + gpio->port*4, bit); + ucp_reg32_or_write(bit2csuAddr + gpio->port*4 + 16, enValue); + } + + return; +} + +static void ucp_jesd_tr_on (uint8_t trIndex) +{ + if (trAnd[trIndex][0]) + { + ucp_reg32_or_write(GPIO0_SWPORTA_DR, trAnd[trIndex][0]); + } + + if (trAnd[trIndex][1]) + { + ucp_reg32_or_write(GPIO0_SWPORTB_DR, trAnd[trIndex][1]); + } + + if (trAnd[trIndex][2]) + { + ucp_reg32_or_write(GPIO1_SWPORTA_DR, trAnd[trIndex][2]); + } + + if (trAnd[trIndex][3]) + { + ucp_reg32_or_write(GPIO1_SWPORTB_DR, trAnd[trIndex][3]); + } + + if (trXor[trIndex][0]) + { + ucp_reg32_and_write(GPIO0_SWPORTA_DR, trXor[trIndex][0]); + } + + if (trXor[trIndex][1]) + { + ucp_reg32_and_write(GPIO0_SWPORTB_DR, trXor[trIndex][1]); + } + + if (trXor[trIndex][2]) + { + ucp_reg32_and_write(GPIO1_SWPORTA_DR, trXor[trIndex][2]); + } + + if (trXor[trIndex][3]) + { + ucp_reg32_and_write(GPIO1_SWPORTB_DR, trXor[trIndex][3]); + } +} + +static void ucp_jesd_tr_off (uint8_t trIndex) +{ + if (trAnd[trIndex][0]) + { + ucp_reg32_and_write(GPIO0_SWPORTA_DR, trAnd[trIndex][0]); + } + + if (trAnd[trIndex][1]) + { + ucp_reg32_and_write(GPIO0_SWPORTB_DR, trAnd[trIndex][1]); + } + + if (trAnd[trIndex][2]) + { + ucp_reg32_and_write(GPIO1_SWPORTA_DR, trAnd[trIndex][2]); + } + + if (trAnd[trIndex][3]) + { + ucp_reg32_and_write(GPIO1_SWPORTB_DR, trAnd[trIndex][3]); + } + + if (trXor[trIndex][0]) + { + ucp_reg32_or_write(GPIO0_SWPORTA_DR, trXor[trIndex][0]); + } + + if (trXor[trIndex][1]) + { + ucp_reg32_or_write(GPIO0_SWPORTB_DR, trXor[trIndex][1]); + } + + if (trXor[trIndex][2]) + { + ucp_reg32_or_write(GPIO1_SWPORTA_DR, trXor[trIndex][2]); + } + + if (trXor[trIndex][3]) + { + ucp_reg32_or_write(GPIO1_SWPORTB_DR, trXor[trIndex][3]); + } +} + +ucp_jesd_TrxGpioCfg_t ucp_jesd_gpioInit (const char *trxGpioConfigFile, uint16_t enLog) +{ + ucp_jesd_TrxGpioCfg_t trxGpioCfg; + uint32_t i, config[36]; + + ucp_reg32_write(GPIO_VERSION2UCP_ADDR, 0); + ucp_reg32_write(GPIO_ULDELAY2UCP_ADDR, 0); + ucp_reg32_write(GPIO_DLDELAY2UCP_ADDR, 0); + + for (i = 0;i < 80;i++) + { + ucp_reg32_write(GPIO_TRIGBIT2UCP_ADDR + 4*i, 0); + } + + memset(infRegTable, 0, sizeof(infRegTable)); + memset(trAnd, 0, sizeof(trAnd)); + memset(trXor, 0, sizeof(trXor)); + + trxGpioCfg = ucp_GetGpioConfig(trxGpioConfigFile); + if (enLog) + { + ucp_printGpioConfigStruct(trxGpioCfg); + } + + ucp_reg32_write(GPIO_PRE_DB_CLK_CFG_REG, 0x527000); + ucp_reg32_write(GPIO_DB_CLK_CFG_REG, 0x527000); + ucp_reg32_write(RFC_CLK_CFG_REG, 0x521000); + //------------------------- CONFIG RF tx/rx/orx GPIO ------------------------- + for (i = 0;i < trxGpioCfg.maxCh;i++) + { + config[0 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].tx.trx.enableLevel); + config[1 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].tx.rf.enableLevel); + config[2 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].tx.sw.enableLevel); + + config[3 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].rx.trx.enableLevel); + config[4 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].rx.rf.enableLevel); + config[5 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].rx.sw.enableLevel); + + config[6 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].orx.trx.enableLevel); + config[7 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].orx.rf.enableLevel); + config[8 + i*9] = GPIO_INVERSE_ENABLELEVEL(trxGpioCfg.ch[i].orx.sw.enableLevel); + } + + for (i = 0;i < trxGpioCfg.maxCh;i++) + { + ucp_jesd_gpioConfig(GPIO_INDEX_TRX_TX1 + i, GPIO_DIR_OUT, config[0 + i*9],UCP_GPIO(trxGpioCfg.ch[i].tx.trx.port, trxGpioCfg.ch[i].tx.trx.pin)); + ucp_jesd_gpioConfig(GPIO_INDEX_RF_TX1 + i, GPIO_DIR_OUT, config[1 + i*9],UCP_GPIO(trxGpioCfg.ch[i].tx.rf.port, trxGpioCfg.ch[i].tx.rf.pin)); + ucp_jesd_gpioConfig(GPIO_INDEX_SW_TX1 + i, GPIO_DIR_OUT, config[2 + i*9],UCP_GPIO(trxGpioCfg.ch[i].tx.sw.port, trxGpioCfg.ch[i].tx.sw.pin)); + + ucp_jesd_gpioConfig(GPIO_INDEX_TRX_RX1 + i, GPIO_DIR_OUT, config[3 + i*9],UCP_GPIO(trxGpioCfg.ch[i].rx.trx.port, trxGpioCfg.ch[i].rx.trx.pin)); + ucp_jesd_gpioConfig(GPIO_INDEX_RF_RX1 + i, GPIO_DIR_OUT, config[4 + i*9],UCP_GPIO(trxGpioCfg.ch[i].rx.rf.port, trxGpioCfg.ch[i].rx.rf.pin)); + ucp_jesd_gpioConfig(GPIO_INDEX_SW_RX1 + i, GPIO_DIR_OUT, config[5 + i*9],UCP_GPIO(trxGpioCfg.ch[i].rx.sw.port, trxGpioCfg.ch[i].rx.sw.pin)); + + ucp_jesd_gpioConfig(GPIO_INDEX_TRX_ORX1 + i, GPIO_DIR_OUT, config[6 + i*9],UCP_GPIO(trxGpioCfg.ch[i].orx.trx.port, trxGpioCfg.ch[i].orx.trx.pin)); + ucp_jesd_gpioConfig(GPIO_INDEX_RF_ORX1 + i, GPIO_DIR_OUT, config[7 + i*9],UCP_GPIO(trxGpioCfg.ch[i].orx.rf.port, trxGpioCfg.ch[i].orx.rf.pin)); + ucp_jesd_gpioConfig(GPIO_INDEX_SW_ORX1 + i, GPIO_DIR_OUT, config[8 + i*9],UCP_GPIO(trxGpioCfg.ch[i].orx.sw.port, trxGpioCfg.ch[i].orx.sw.pin)); + } + + ucp_jesd_gpioConfig(GPIO_INDEX_TRIGER,GPIO_DIR_OUT,trxGpioCfg.triger.enableLevel,UCP_GPIO(trxGpioCfg.triger.port,trxGpioCfg.triger.pin)); + + //------------------------- CONFIG share memry ------------------------- + ucp_reg32_write(GPIO_VERSION2UCP_ADDR, trxGpioCfg.version); + ucp_reg32_write(GPIO_ULDELAY2UCP_ADDR, trxGpioCfg.uldelay); + ucp_reg32_write(GPIO_DLDELAY2UCP_ADDR, trxGpioCfg.dldelay); + + for (i = 0;i < trxGpioCfg.maxCh;i++) + { + ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].tx.trx, GPIO_TXTRXBIT2UCP_ADDR); + ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].tx.rf, GPIO_TXRFBIT2UCP_ADDR); + ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].tx.sw, GPIO_TXSWBIT2UCP_ADDR); + + ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].rx.trx, GPIO_RXTRXBIT2UCP_ADDR); + ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].rx.rf, GPIO_RXRFBIT2UCP_ADDR); + ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].rx.sw, GPIO_RXSWBIT2UCP_ADDR); + + ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].orx.trx, GPIO_ORXTRXBIT2UCP_ADDR); + ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].orx.rf, GPIO_ORXRFBIT2UCP_ADDR); + ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.ch[i].orx.sw, GPIO_ORXSWBIT2UCP_ADDR); + } + + ucp_jesd_gpioCfgInf2CSU(&trxGpioCfg.triger, GPIO_TRIGBIT2UCP_ADDR); + + for (i = 0;i < 4;i++) + { + trAnd[TR_IND_TX_TRX][i] = ucp_reg32_read(GPIO_TXTRXBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_TXTRXBIT2UCP_ADDR + 16 + 4*i); + trXor[TR_IND_TX_TRX][i] = ucp_reg32_read(GPIO_TXTRXBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_TXTRXBIT2UCP_ADDR + 16 + 4*i); + trAnd[TR_IND_TX_RF][i] = ucp_reg32_read(GPIO_TXRFBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_TXRFBIT2UCP_ADDR + 16 + 4*i); + trXor[TR_IND_TX_RF][i] = ucp_reg32_read(GPIO_TXRFBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_TXRFBIT2UCP_ADDR + 16 + 4*i); + trAnd[TR_IND_TX_SW][i] = ucp_reg32_read(GPIO_TXSWBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_TXSWBIT2UCP_ADDR + 16 + 4*i); + trXor[TR_IND_TX_SW][i] = ucp_reg32_read(GPIO_TXSWBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_TXSWBIT2UCP_ADDR + 16 + 4*i); + + trAnd[TR_IND_RX_TRX][i] = ucp_reg32_read(GPIO_RXTRXBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_RXTRXBIT2UCP_ADDR + 16 + 4*i); + trXor[TR_IND_RX_TRX][i] = ucp_reg32_read(GPIO_RXTRXBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_RXTRXBIT2UCP_ADDR + 16 + 4*i); + trAnd[TR_IND_RX_RF][i] = ucp_reg32_read(GPIO_RXRFBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_RXRFBIT2UCP_ADDR + 16 + 4*i); + trXor[TR_IND_RX_RF][i] = ucp_reg32_read(GPIO_RXRFBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_RXRFBIT2UCP_ADDR + 16 + 4*i); + trAnd[TR_IND_RX_SW][i] = ucp_reg32_read(GPIO_RXSWBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_RXSWBIT2UCP_ADDR + 16 + 4*i); + trXor[TR_IND_RX_SW][i] = ucp_reg32_read(GPIO_RXSWBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_RXSWBIT2UCP_ADDR + 16 + 4*i); + + trAnd[TR_IND_ORX_TRX][i] = ucp_reg32_read(GPIO_ORXTRXBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_ORXTRXBIT2UCP_ADDR + 16 + 4*i); + trXor[TR_IND_ORX_TRX][i] = ucp_reg32_read(GPIO_ORXTRXBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_ORXTRXBIT2UCP_ADDR + 16 + 4*i); + trAnd[TR_IND_ORX_RF][i] = ucp_reg32_read(GPIO_ORXRFBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_ORXRFBIT2UCP_ADDR + 16 + 4*i); + trXor[TR_IND_ORX_RF][i] = ucp_reg32_read(GPIO_ORXRFBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_ORXRFBIT2UCP_ADDR + 16 + 4*i); + trAnd[TR_IND_ORX_SW][i] = ucp_reg32_read(GPIO_ORXSWBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_ORXSWBIT2UCP_ADDR + 16 + 4*i); + trXor[TR_IND_ORX_SW][i] = ucp_reg32_read(GPIO_ORXSWBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_ORXSWBIT2UCP_ADDR + 16 + 4*i); + + trAnd[TR_IND_TRIG][i] = ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 4*i)&ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 16 + 4*i); + trXor[TR_IND_TRIG][i] = ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 4*i)^ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 16 + 4*i); + } + + if (enLog) + { + printf("VERSION: %d\n", ucp_reg32_read(GPIO_VERSION2UCP_ADDR)); + printf("ULDELAY: %d\n", ucp_reg32_read(GPIO_ULDELAY2UCP_ADDR)); + printf("DLDELAY: %d\n\n", ucp_reg32_read(GPIO_DLDELAY2UCP_ADDR)); + + for (i = 0;i < 10;i++) + { + printf("ADDR: %08X, BIT: %08X %08X %08X %08X\n", GPIO_TRIGBIT2UCP_ADDR + i*32, + ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 0*4 + i*32), + ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 1*4 + i*32), + ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 2*4 + i*32), + ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 3*4 + i*32)); + printf("ADDR: %08X, VAILID: %08X %08X %08X %08X\n\n", GPIO_TRIGBIT2UCP_ADDR + 4*4 + i*32, + ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 4*4 + i*32), + ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 5*4 + i*32), + ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 6*4 + i*32), + ucp_reg32_read(GPIO_TRIGBIT2UCP_ADDR + 7*4 + i*32)); + } + + printf("Trig: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n", + trAnd[TR_IND_TRIG][0], trAnd[TR_IND_TRIG][1], trAnd[TR_IND_TRIG][2], trAnd[TR_IND_TRIG][3], + trXor[TR_IND_TRIG][0], trXor[TR_IND_TRIG][1], trXor[TR_IND_TRIG][2], trXor[TR_IND_TRIG][3]); + printf("TxTrx: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n", + trAnd[TR_IND_TX_TRX][0], trAnd[TR_IND_TX_TRX][1], trAnd[TR_IND_TX_TRX][2], trAnd[TR_IND_TX_TRX][3], + trXor[TR_IND_TX_TRX][0], trXor[TR_IND_TX_TRX][1], trXor[TR_IND_TX_TRX][2], trXor[TR_IND_TX_TRX][3]); + printf("TxRf: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n", + trAnd[TR_IND_TX_RF][0], trAnd[TR_IND_TX_RF][1], trAnd[TR_IND_TX_RF][2], trAnd[TR_IND_TX_RF][3], + trXor[TR_IND_TX_RF][0], trXor[TR_IND_TX_RF][1], trXor[TR_IND_TX_RF][2], trXor[TR_IND_TX_RF][3]); + printf("TxSw: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n", + trAnd[TR_IND_TX_SW][0], trAnd[TR_IND_TX_SW][1], trAnd[TR_IND_TX_SW][2], trAnd[TR_IND_TX_SW][3], + trXor[TR_IND_TX_SW][0], trXor[TR_IND_TX_SW][1], trXor[TR_IND_TX_SW][2], trXor[TR_IND_TX_SW][3]); + + printf("RxTrx: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n", + trAnd[TR_IND_RX_TRX][0], trAnd[TR_IND_RX_TRX][1], trAnd[TR_IND_RX_TRX][2], trAnd[TR_IND_RX_TRX][3], + trXor[TR_IND_RX_TRX][0], trXor[TR_IND_RX_TRX][1], trXor[TR_IND_RX_TRX][2], trXor[TR_IND_RX_TRX][3]); + printf("RxRf: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n", + trAnd[TR_IND_RX_RF][0], trAnd[TR_IND_RX_RF][1], trAnd[TR_IND_RX_RF][2], trAnd[TR_IND_RX_RF][3], + trXor[TR_IND_RX_RF][0], trXor[TR_IND_RX_RF][1], trXor[TR_IND_RX_RF][2], trXor[TR_IND_RX_RF][3]); + printf("RxSw: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n", + trAnd[TR_IND_RX_SW][0], trAnd[TR_IND_RX_SW][1], trAnd[TR_IND_RX_SW][2], trAnd[TR_IND_RX_SW][3], + trXor[TR_IND_RX_SW][0], trXor[TR_IND_RX_SW][1], trXor[TR_IND_RX_SW][2], trXor[TR_IND_RX_SW][3]); + + printf("OrxTrx: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n", + trAnd[TR_IND_ORX_TRX][0], trAnd[TR_IND_ORX_TRX][1], trAnd[TR_IND_ORX_TRX][2], trAnd[TR_IND_ORX_TRX][3], + trXor[TR_IND_ORX_TRX][0], trXor[TR_IND_ORX_TRX][1], trXor[TR_IND_ORX_TRX][2], trXor[TR_IND_ORX_TRX][3]); + printf("OrxRf: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n", + trAnd[TR_IND_ORX_RF][0], trAnd[TR_IND_ORX_RF][1], trAnd[TR_IND_ORX_RF][2], trAnd[TR_IND_ORX_RF][3], + trXor[TR_IND_ORX_RF][0], trXor[TR_IND_ORX_RF][1], trXor[TR_IND_ORX_RF][2], trXor[TR_IND_ORX_RF][3]); + + printf("OrxSw: %08X_%08X_%08X_%08X, %08X_%08X_%08X_%08X\n\n", + trAnd[TR_IND_ORX_SW][0], trAnd[TR_IND_ORX_SW][1], trAnd[TR_IND_ORX_SW][2], trAnd[TR_IND_ORX_SW][3], + trXor[TR_IND_ORX_SW][0], trXor[TR_IND_ORX_SW][1], trXor[TR_IND_ORX_SW][2], trXor[TR_IND_ORX_SW][3]); + } +//------------------------- CONFIG RF tx/rx/orx GPIO END ------------------------- + + return trxGpioCfg; +} + +int ucp_jesd_gpioConfig (const int pinIdex, uint8_t dir, uint8_t enable, tUcpGpioRegTable_t *gpio) +{ + if (pinIdex < GPIO_INDEX_MAX) + { + infRegTable[pinIdex].index = pinIdex; + infRegTable[pinIdex].enable = enable; + infRegTable[pinIdex].dir = dir; + infRegTable[pinIdex].value = 0; + infRegTable[pinIdex].gpio = gpio; + + if (infRegTable[pinIdex].enable) + { + infRegTable[pinIdex].value = (UCP_JESD_TRX_GPIO_VALID_HIGH == infRegTable[pinIdex].enable) ? 1 : 0; + + ucp_reg32_and_write(infRegTable[pinIdex].gpio->pinMuxReg, infRegTable[pinIdex].gpio->muxMask); + ucp_reg32_or_write(infRegTable[pinIdex].gpio->pinMuxReg, infRegTable[pinIdex].gpio->muxValue); + + ucp_jesd_gpioSetDir(infRegTable[pinIdex].index, infRegTable[pinIdex].dir); + if (GPIO_DIR_OUT == infRegTable[pinIdex].dir) + { + ucp_jesd_gpioSet(infRegTable[pinIdex].index, infRegTable[pinIdex].value); + } + } + + return true; + } + else + { + printf("err: index %d out range @%s %d\n", pinIdex, __FILE__, __LINE__); + return false; + } +} + +int ucp_jesd_gpioSetDir(const int pinIdex, eGpioDir dir) +{ + if (pinIdex < GPIO_INDEX_MAX) + { + if (infRegTable[pinIdex].enable) + { + if (GPIO_DIR_IN == dir ) + { + ucp_reg32_and_write(infRegTable[pinIdex].gpio->dirReg, infRegTable[pinIdex].gpio->bitMask); + } + else if (GPIO_DIR_OUT == dir ) + { + ucp_reg32_or_write(infRegTable[pinIdex].gpio->dirReg, infRegTable[pinIdex].gpio->bitMask); + } + + return true; + } + else + { + return false; + } + } + else + { + printf("err: index %d out range @%s %d\n", pinIdex, __FILE__, __LINE__); + return false; + } +} + +eGpioDir ucp_jesd_gpioGetDir(const int pinIdex) +{ + uint32_t dir; + + if ((pinIdex < GPIO_INDEX_MAX) && infRegTable[pinIdex].enable) + { + dir = ucp_reg32_and_read(infRegTable[pinIdex].gpio->dirReg, infRegTable[pinIdex].gpio->bitMask); + return (dir ? GPIO_DIR_IN : GPIO_DIR_OUT); + } + else + { + printf("err: index %d out range @%s %d\n", pinIdex, __FILE__, __LINE__); + return -1; + } + +} + +int ucp_jesd_gpioSet(const int pinIdex, int value) +{ + if (pinIdex < GPIO_INDEX_MAX) + { + if (infRegTable[pinIdex].enable) + { + if (0 == value) + { + ucp_reg32_and_write(infRegTable[pinIdex].gpio->valueReg, infRegTable[pinIdex].gpio->bitMask); + } + else + { + ucp_reg32_or_write(infRegTable[pinIdex].gpio->valueReg, infRegTable[pinIdex].gpio->bitMask); + } + + return true; + } + else + { + return false; + } + } + else + { + printf("err: index %d out range @%s %d\n", pinIdex, __FILE__, __LINE__); + return false; + } +} + +int ucp_jesd_gpioGet(const int pinIdex) +{ + uint32_t dir; + + if ((pinIdex < GPIO_INDEX_MAX) && infRegTable[pinIdex].enable) + { + dir = ucp_reg32_and_read(infRegTable[pinIdex].gpio->valueReg, infRegTable[pinIdex].gpio->bitMask); + return (dir ? 1 : 0); + } + else + { + printf("err: index %d out range @%s %d\n", pinIdex, __FILE__, __LINE__); + return -1; + } +} + +void ucp_jesd_gpio_tx (void) +{ + ucp_jesd_tr_off(TR_IND_RX_RF); + ucp_jesd_tr_off(TR_IND_RX_TRX); + ucp_jesd_tr_off(TR_IND_RX_SW); + + ucp_jesd_tr_on(TR_IND_TX_SW); + ucp_jesd_tr_on(TR_IND_TX_RF); + ucp_jesd_tr_on(TR_IND_TX_TRX); +} + +void ucp_jesd_gpio_rx (void) +{ + ucp_jesd_tr_off(TR_IND_TX_TRX); + ucp_jesd_tr_off(TR_IND_TX_RF); + ucp_jesd_tr_off(TR_IND_TX_SW); + + ucp_jesd_tr_on(TR_IND_RX_SW); + ucp_jesd_tr_on(TR_IND_RX_RF); + ucp_jesd_tr_on(TR_IND_RX_TRX); +} + +void ucp_jesd_gpio_on (void) +{ + ucp_jesd_tr_on(TR_IND_RX_SW); + ucp_jesd_tr_on(TR_IND_RX_RF); + ucp_jesd_tr_on(TR_IND_RX_TRX); + + ucp_jesd_tr_on(TR_IND_TX_TRX); + ucp_jesd_tr_on(TR_IND_TX_RF); + ucp_jesd_tr_on(TR_IND_TX_SW); +} + +void ucp_jesd_gpio_off (void) +{ + ucp_jesd_tr_off(TR_IND_TX_TRX); + ucp_jesd_tr_off(TR_IND_TX_RF); + ucp_jesd_tr_off(TR_IND_TX_SW); + + ucp_jesd_tr_off(TR_IND_RX_SW); + ucp_jesd_tr_off(TR_IND_RX_RF); + ucp_jesd_tr_off(TR_IND_RX_TRX); +} + +void ucp_jesd_gpio_orxOn (void) +{ + ucp_jesd_tr_on(TR_IND_ORX_SW); + ucp_jesd_tr_on(TR_IND_ORX_RF); + ucp_jesd_tr_on(TR_IND_ORX_TRX); +} + +void ucp_jesd_gpio_orxOff (void) +{ + ucp_jesd_tr_off(TR_IND_ORX_TRX); + ucp_jesd_tr_off(TR_IND_ORX_RF); + ucp_jesd_tr_off(TR_IND_ORX_SW); +} + +void ucp_jesd_gpio_trigOn (void) +{ + ucp_jesd_tr_on(TR_IND_TRIG); +} + +void ucp_jesd_gpio_trigOff (void) +{ + ucp_jesd_tr_off(TR_IND_TRIG); +} + + + diff --git a/driver/rfic/ucp/base/src/ucp_jesd_gpio.o b/driver/rfic/ucp/base/src/ucp_jesd_gpio.o new file mode 100644 index 0000000..fee0c76 Binary files /dev/null and b/driver/rfic/ucp/base/src/ucp_jesd_gpio.o differ diff --git a/driver/rfic/ucp/base/src/ucp_jsonTools.c b/driver/rfic/ucp/base/src/ucp_jsonTools.c new file mode 100644 index 0000000..d1dd46c --- /dev/null +++ b/driver/rfic/ucp/base/src/ucp_jsonTools.c @@ -0,0 +1,511 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_jsonTools.c +// Author : Boheng Lin bhlin919@126.com +// Date First Issued : 2023-08-15 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#include +#include +#include "xzJSON.h" +#include +#include "ucp_jsonTools.h" + +#define RFIC_CFG_FILE_PATH "/lib/firmware/resources/ucp_rfic_cfg.json" +#define RFIC_CAL_FILE_PATH "/lib/firmware/resources/ucp_rfic_calpara.json" + +typedef struct ucp_rfic_cfg +{ + uint64_t txLo; + uint64_t rxLo; + uint64_t auxLo; + uint16_t initAtt; + uint16_t initGain; + + uint64_t sampleRate; + uint64_t bw; + uint16_t antNumb; + uint16_t enFdd; + uint16_t enOrx; + uint16_t en204C; + uint16_t enUcpLog; + + int16_t calOrxGainIndex; + int16_t calChAttPara[4]; + + uint16_t padding; +} ucp_rfic_cfg_t; + + +typedef struct ucp_rfic_calPara +{ + int16_t calOrxGainIndex; + int16_t calChAttPara[4]; +} ucp_rfic_calPara_t; + +static void printfJson(xzJSON *json) { + if (NULL == json) { + return; + } + char *cjson = xzJSON_Print(json); + printf("json:%s\n", cjson); + free(cjson); +} + +void ucp_printGpioConfigStruct (ucp_jesd_TrxGpioCfg_t gpioConfig) +{ + printf("-----------------------------------------\n"); + printf("board = %s\n", gpioConfig.board); + printf("version = %d\n", gpioConfig.version); + printf("maxCh = %d\n", gpioConfig.maxCh); + printf("devClkSrc = %d\n", gpioConfig.devClkSrc); + printf("uldelay = %d\n", gpioConfig.uldelay); + printf("dldelay = %d\n", gpioConfig.dldelay); + if (gpioConfig.version > 1) + { + printf("lvdsCoupling = %s\n\n", gpioConfig.lvdsCoupling); + } + + printf("triger port: %02d\n", gpioConfig.triger.port); + printf("triger pin: %02d\n", gpioConfig.triger.pin); + printf("triger enableLevel: %02d\n", gpioConfig.triger.enableLevel); + + printf("\nPORT/PIN/EN CH0 CH1 CH2 CH3 \n"); + printf("tx trx: %02d %02d %02d | %02d %02d %02d | %02d %02d %02d | %02d %02d %02d\n", + gpioConfig.ch[0].tx.trx.port, gpioConfig.ch[0].tx.trx.pin, gpioConfig.ch[0].tx.trx.enableLevel, + gpioConfig.ch[1].tx.trx.port, gpioConfig.ch[1].tx.trx.pin, gpioConfig.ch[1].tx.trx.enableLevel, + gpioConfig.ch[2].tx.trx.port, gpioConfig.ch[2].tx.trx.pin, gpioConfig.ch[2].tx.trx.enableLevel, + gpioConfig.ch[3].tx.trx.port, gpioConfig.ch[3].tx.trx.pin, gpioConfig.ch[3].tx.trx.enableLevel); + printf("tx rf: %02d %02d %02d | %02d %02d %02d | %02d %02d %02d | %02d %02d %02d\n", + gpioConfig.ch[0].tx.rf.port, gpioConfig.ch[0].tx.rf.pin, gpioConfig.ch[0].tx.rf.enableLevel, + gpioConfig.ch[1].tx.rf.port, gpioConfig.ch[1].tx.rf.pin, gpioConfig.ch[1].tx.rf.enableLevel, + gpioConfig.ch[2].tx.rf.port, gpioConfig.ch[2].tx.rf.pin, gpioConfig.ch[2].tx.rf.enableLevel, + gpioConfig.ch[3].tx.rf.port, gpioConfig.ch[3].tx.rf.pin, gpioConfig.ch[3].tx.rf.enableLevel); + printf("tx sw: %02d %02d %02d | %02d %02d %02d | %02d %02d %02d | %02d %02d %02d\n\n", + gpioConfig.ch[0].tx.sw.port, gpioConfig.ch[0].tx.sw.pin, gpioConfig.ch[0].tx.sw.enableLevel, + gpioConfig.ch[1].tx.sw.port, gpioConfig.ch[1].tx.sw.pin, gpioConfig.ch[1].tx.sw.enableLevel, + gpioConfig.ch[2].tx.sw.port, gpioConfig.ch[2].tx.sw.pin, gpioConfig.ch[2].tx.sw.enableLevel, + gpioConfig.ch[3].tx.sw.port, gpioConfig.ch[3].tx.sw.pin, gpioConfig.ch[3].tx.sw.enableLevel); + + printf("rx trx: %02d %02d %02d | %02d %02d %02d | %02d %02d %02d | %02d %02d %02d\n", + gpioConfig.ch[0].rx.trx.port, gpioConfig.ch[0].rx.trx.pin, gpioConfig.ch[0].rx.trx.enableLevel, + gpioConfig.ch[1].rx.trx.port, gpioConfig.ch[1].rx.trx.pin, gpioConfig.ch[1].rx.trx.enableLevel, + gpioConfig.ch[2].rx.trx.port, gpioConfig.ch[2].rx.trx.pin, gpioConfig.ch[2].rx.trx.enableLevel, + gpioConfig.ch[3].rx.trx.port, gpioConfig.ch[3].rx.trx.pin, gpioConfig.ch[3].rx.trx.enableLevel); + printf("rx rf: %02d %02d %02d | %02d %02d %02d | %02d %02d %02d | %02d %02d %02d\n", + gpioConfig.ch[0].rx.rf.port, gpioConfig.ch[0].rx.rf.pin, gpioConfig.ch[0].rx.rf.enableLevel, + gpioConfig.ch[1].rx.rf.port, gpioConfig.ch[1].rx.rf.pin, gpioConfig.ch[1].rx.rf.enableLevel, + gpioConfig.ch[2].rx.rf.port, gpioConfig.ch[2].rx.rf.pin, gpioConfig.ch[2].rx.rf.enableLevel, + gpioConfig.ch[3].rx.rf.port, gpioConfig.ch[3].rx.rf.pin, gpioConfig.ch[3].rx.rf.enableLevel); + printf("rx sw: %02d %02d %02d | %02d %02d %02d | %02d %02d %02d | %02d %02d %02d\n\n", + gpioConfig.ch[0].rx.sw.port, gpioConfig.ch[0].rx.sw.pin, gpioConfig.ch[0].rx.sw.enableLevel, + gpioConfig.ch[1].rx.sw.port, gpioConfig.ch[1].rx.sw.pin, gpioConfig.ch[1].rx.sw.enableLevel, + gpioConfig.ch[2].rx.sw.port, gpioConfig.ch[2].rx.sw.pin, gpioConfig.ch[2].rx.sw.enableLevel, + gpioConfig.ch[3].rx.sw.port, gpioConfig.ch[3].rx.sw.pin, gpioConfig.ch[3].rx.sw.enableLevel); + + printf("orx trx: %02d %02d %02d | %02d %02d %02d | %02d %02d %02d | %02d %02d %02d\n", + gpioConfig.ch[0].orx.trx.port, gpioConfig.ch[0].orx.trx.pin, gpioConfig.ch[0].orx.trx.enableLevel, + gpioConfig.ch[1].orx.trx.port, gpioConfig.ch[1].orx.trx.pin, gpioConfig.ch[1].orx.trx.enableLevel, + gpioConfig.ch[2].orx.trx.port, gpioConfig.ch[2].orx.trx.pin, gpioConfig.ch[2].orx.trx.enableLevel, + gpioConfig.ch[3].orx.trx.port, gpioConfig.ch[3].orx.trx.pin, gpioConfig.ch[3].orx.trx.enableLevel); + printf("orx rf: %02d %02d %02d | %02d %02d %02d | %02d %02d %02d | %02d %02d %02d\n", + gpioConfig.ch[0].orx.rf.port, gpioConfig.ch[0].orx.rf.pin, gpioConfig.ch[0].orx.rf.enableLevel, + gpioConfig.ch[1].orx.rf.port, gpioConfig.ch[1].orx.rf.pin, gpioConfig.ch[1].orx.rf.enableLevel, + gpioConfig.ch[2].orx.rf.port, gpioConfig.ch[2].orx.rf.pin, gpioConfig.ch[2].orx.rf.enableLevel, + gpioConfig.ch[3].orx.rf.port, gpioConfig.ch[3].orx.rf.pin, gpioConfig.ch[3].orx.rf.enableLevel); + printf("orx sw: %02d %02d %02d | %02d %02d %02d | %02d %02d %02d | %02d %02d %02d\n", + gpioConfig.ch[0].orx.sw.port, gpioConfig.ch[0].orx.sw.pin, gpioConfig.ch[0].orx.sw.enableLevel, + gpioConfig.ch[1].orx.sw.port, gpioConfig.ch[1].orx.sw.pin, gpioConfig.ch[1].orx.sw.enableLevel, + gpioConfig.ch[2].orx.sw.port, gpioConfig.ch[2].orx.sw.pin, gpioConfig.ch[2].orx.sw.enableLevel, + gpioConfig.ch[3].orx.sw.port, gpioConfig.ch[3].orx.sw.pin, gpioConfig.ch[3].orx.sw.enableLevel); + + printf("-----------------------------------------\n"); + + return; +} + +void freeJson(xzJSON *json) { + if (json != NULL) { + xzJSON_Delete(json); + } +} + +void ucp_jsonSave (const char *fileName, xzJSON *json) +{ + char *cjson = xzJSON_Print(json); + FILE *fpw = NULL; + + fpw = fopen(fileName, "w+"); + if (NULL != fpw) { + fwrite(cjson, strlen(cjson),1,fpw); + fclose(fpw); + } + if (cjson != NULL) { + free(cjson); + } +} + +xzJSON* ucp_jsonLoad (const char *fileName) +{ + FILE *fpr = NULL; + xzJSON *json; + long len; + + fpr = fopen(fileName, "r"); + if (NULL == fpr) + { + return ((xzJSON*)NULL); + } + + fseek(fpr, 0, SEEK_END); + + len = ftell(fpr); + fseek(fpr, 0, SEEK_SET); + char *data = (char*)malloc(len + 1); + fread(data, 1, len, fpr); + if (fpr != NULL) + { + fclose(fpr); + } + + json = xzJSON_Parse(data); + + return json; +} + +void ucp_GenGpioConfig (const char *fileName) +{ + ucp_jesd_TrxGpioCfg_t gpioConfig; + xzJSON *root = xzJSON_CreateObject(); + xzJSON *item; + xzJSON *config; + uint32_t i; + + memset(&gpioConfig, 0, sizeof(gpioConfig)); + + item = xzJSON_GetObjectItem(root, "common"); + + gpioConfig.version = 1; + strcpy(gpioConfig.board, "EVMT"); + gpioConfig.maxCh = MAX_UCP_JESD_TRX_CH; + gpioConfig.devClkSrc = 2; + + for (i = 0;i < gpioConfig.maxCh;i++) + { + gpioConfig.ch[i].tx.trx.port = 0; + gpioConfig.ch[i].tx.trx.pin = 0; + gpioConfig.ch[i].tx.trx.enableLevel = UCP_JESD_TRX_GPIO_DISABLE; + gpioConfig.ch[i].tx.rf.port = 0; + gpioConfig.ch[i].tx.rf.pin = 0; + gpioConfig.ch[i].tx.rf.enableLevel = UCP_JESD_TRX_GPIO_DISABLE; + gpioConfig.ch[i].tx.sw.port = 0; + gpioConfig.ch[i].tx.sw.pin = 0; + gpioConfig.ch[i].tx.sw.enableLevel = UCP_JESD_TRX_GPIO_DISABLE; + + gpioConfig.ch[i].rx.trx.port = 0; + gpioConfig.ch[i].rx.trx.pin = 0; + gpioConfig.ch[i].rx.trx.enableLevel = UCP_JESD_TRX_GPIO_DISABLE; + gpioConfig.ch[i].rx.rf.port = 0; + gpioConfig.ch[i].rx.rf.pin = 0; + gpioConfig.ch[i].rx.rf.enableLevel = UCP_JESD_TRX_GPIO_DISABLE; + gpioConfig.ch[i].rx.sw.port = 0; + gpioConfig.ch[i].rx.sw.pin = 0; + gpioConfig.ch[i].rx.sw.enableLevel = UCP_JESD_TRX_GPIO_DISABLE; + + gpioConfig.ch[i].orx.trx.port = 0; + gpioConfig.ch[i].orx.trx.pin = 0; + gpioConfig.ch[i].orx.trx.enableLevel = UCP_JESD_TRX_GPIO_DISABLE; + gpioConfig.ch[i].orx.rf.port = 0; + gpioConfig.ch[i].orx.rf.pin = 0; + gpioConfig.ch[i].orx.rf.enableLevel = UCP_JESD_TRX_GPIO_DISABLE; + gpioConfig.ch[i].orx.sw.port = 0; + gpioConfig.ch[i].orx.sw.pin = 0; + gpioConfig.ch[i].orx.sw.enableLevel = UCP_JESD_TRX_GPIO_DISABLE; + } + + gpioConfig.triger.port = 0; + gpioConfig.triger.pin = 0; + gpioConfig.triger.enableLevel = UCP_JESD_TRX_GPIO_DISABLE; + + item = xzJSON_AddObjectToObject(root, "common"); + xzJSON_AddStringToObject(item, "board", gpioConfig.board); + xzJSON_AddNumberToObject(item, "version", gpioConfig.version); + xzJSON_AddNumberToObject(item, "maxCh", gpioConfig.maxCh); + xzJSON_AddNumberToObject(item, "devClkSrc", gpioConfig.devClkSrc); + xzJSON_AddNumberToObject(item, "uldelay", 0); + xzJSON_AddNumberToObject(item, "dldelay", 0); + xzJSON_AddStringToObject(item, "lvdsCoupling", gpioConfig.lvdsCoupling); + + item = xzJSON_CreateArray(); + for (i = 0;i < gpioConfig.maxCh;i++) + { + config = xzJSON_CreateObject(); + xzJSON_AddNumberToObject(config, "tx_trx_port", gpioConfig.ch[i].tx.trx.port); + xzJSON_AddNumberToObject(config, "tx_trx_pin", gpioConfig.ch[i].tx.trx.pin); + xzJSON_AddNumberToObject(config, "tx_trx_enableLevel", gpioConfig.ch[i].tx.trx.enableLevel); + xzJSON_AddNumberToObject(config, "tx_rf_port", gpioConfig.ch[i].tx.rf.port); + xzJSON_AddNumberToObject(config, "tx_rf_pin", gpioConfig.ch[i].tx.rf.pin); + xzJSON_AddNumberToObject(config, "tx_rf_enableLevel", gpioConfig.ch[i].tx.rf.enableLevel); + xzJSON_AddNumberToObject(config, "tx_sw_port", gpioConfig.ch[i].tx.sw.port); + xzJSON_AddNumberToObject(config, "tx_sw_pin", gpioConfig.ch[i].tx.sw.pin); + xzJSON_AddNumberToObject(config, "tx_sw_enableLevel", gpioConfig.ch[i].tx.sw.enableLevel); + + xzJSON_AddNumberToObject(config, "rx_trx_port", gpioConfig.ch[i].rx.trx.port); + xzJSON_AddNumberToObject(config, "rx_trx_pin", gpioConfig.ch[i].rx.trx.pin); + xzJSON_AddNumberToObject(config, "rx_trx_enableLevel", gpioConfig.ch[i].rx.trx.enableLevel); + xzJSON_AddNumberToObject(config, "rx_rf_port", gpioConfig.ch[i].rx.rf.port); + xzJSON_AddNumberToObject(config, "rx_rf_pin", gpioConfig.ch[i].rx.rf.pin); + xzJSON_AddNumberToObject(config, "rx_rf_enableLevel", gpioConfig.ch[i].rx.rf.enableLevel); + xzJSON_AddNumberToObject(config, "rx_sw_port", gpioConfig.ch[i].rx.sw.port); + xzJSON_AddNumberToObject(config, "rx_sw_pin", gpioConfig.ch[i].rx.sw.pin); + xzJSON_AddNumberToObject(config, "rx_sw_enableLevel", gpioConfig.ch[i].rx.sw.enableLevel); + + xzJSON_AddNumberToObject(config, "orx_trx_port", gpioConfig.ch[i].orx.trx.port); + xzJSON_AddNumberToObject(config, "orx_trx_pin", gpioConfig.ch[i].orx.trx.pin); + xzJSON_AddNumberToObject(config, "orx_trx_enableLevel", gpioConfig.ch[i].orx.trx.enableLevel); + xzJSON_AddNumberToObject(config, "orx_rf_port", gpioConfig.ch[i].orx.rf.port); + xzJSON_AddNumberToObject(config, "orx_rf_pin", gpioConfig.ch[i].orx.rf.pin); + xzJSON_AddNumberToObject(config, "orx_rf_enableLevel", gpioConfig.ch[i].orx.rf.enableLevel); + xzJSON_AddNumberToObject(config, "orx_sw_port", gpioConfig.ch[i].orx.sw.port); + xzJSON_AddNumberToObject(config, "orx_sw_pin", gpioConfig.ch[i].orx.sw.pin); + xzJSON_AddNumberToObject(config, "orx_sw_enableLevel", gpioConfig.ch[i].orx.sw.enableLevel); + + xzJSON_AddItemToArray(item, config); + } + + config = xzJSON_CreateObject(); + xzJSON_AddNumberToObject(config, "triger_port", gpioConfig.triger.port); + xzJSON_AddNumberToObject(config, "triger_pin", gpioConfig.triger.pin); + xzJSON_AddNumberToObject(config, "triger_enableLevel", gpioConfig.triger.enableLevel); + xzJSON_AddItemToArray(item, config); + + xzJSON_AddItemReferenceToObject(root, "config", item); + printfJson(root); + ucp_jsonSave(fileName, root); + + //xzJSON_Delete(root); + //xzJSON_Delete(item); + //xzJSON_Delete(config); +} + +ucp_jesd_TrxGpioCfg_t ucp_GetGpioConfig (const char *fileName) +{ + ucp_jesd_TrxGpioCfg_t gpioConfig; + xzJSON *root, *item, *array, *config; + uint32_t i; + + root = ucp_jsonLoad(fileName); + if (((xzJSON*)NULL) == root) + { + printf("Error: Can't find gpio's config File!\n"); + exit(1); + } + + memset(&gpioConfig, 0, sizeof(gpioConfig)); + + item = xzJSON_GetObjectItem(root, "common"); + config = xzJSON_GetObjectItem(item, "board"); + strcpy(gpioConfig.board, config->valuestring); + config = xzJSON_GetObjectItem(item, "version"); + gpioConfig.version = config->valueint; + config = xzJSON_GetObjectItem(item, "maxCh"); + gpioConfig.maxCh = config->valueint; + config = xzJSON_GetObjectItem(item, "devClkSrc"); + gpioConfig.devClkSrc = config->valueint; + config = xzJSON_GetObjectItem(item, "uldelay"); + gpioConfig.uldelay = config->valueint; + config = xzJSON_GetObjectItem(item, "dldelay"); + gpioConfig.dldelay = config->valueint; + if (gpioConfig.version > 1) + { + config = xzJSON_GetObjectItem(item, "lvdsCoupling"); + strcpy(gpioConfig.lvdsCoupling, config->valuestring); + } + else + { + printf("Note: A new version of ucp_trx_gpioCfg.json is available, please update!\n"); + } + + item = xzJSON_GetObjectItem(root, "config"); + for (i = 0;i < gpioConfig.maxCh;i++) + { + array = xzJSON_GetArrayItem(item, i); + + config = xzJSON_GetObjectItem(array, "tx_trx_port"); + gpioConfig.ch[i].tx.trx.port = config->valueint; + config = xzJSON_GetObjectItem(array, "tx_trx_pin"); + gpioConfig.ch[i].tx.trx.pin = config->valueint; + config = xzJSON_GetObjectItem(array, "tx_trx_enableLevel"); + gpioConfig.ch[i].tx.trx.enableLevel = config->valueint; + config = xzJSON_GetObjectItem(array, "tx_rf_port"); + gpioConfig.ch[i].tx.rf.port = config->valueint; + config = xzJSON_GetObjectItem(array, "tx_rf_pin"); + gpioConfig.ch[i].tx.rf.pin = config->valueint; + config = xzJSON_GetObjectItem(array, "tx_rf_enableLevel"); + gpioConfig.ch[i].tx.rf.enableLevel = config->valueint; + config = xzJSON_GetObjectItem(array, "tx_sw_port"); + gpioConfig.ch[i].tx.sw.port = config->valueint; + config = xzJSON_GetObjectItem(array, "tx_sw_pin"); + gpioConfig.ch[i].tx.sw.pin = config->valueint; + config = xzJSON_GetObjectItem(array, "tx_sw_enableLevel"); + gpioConfig.ch[i].tx.sw.enableLevel = config->valueint; + + config = xzJSON_GetObjectItem(array, "rx_trx_port"); + gpioConfig.ch[i].rx.trx.port = config->valueint; + config = xzJSON_GetObjectItem(array, "rx_trx_pin"); + gpioConfig.ch[i].rx.trx.pin = config->valueint; + config = xzJSON_GetObjectItem(array, "rx_trx_enableLevel"); + gpioConfig.ch[i].rx.trx.enableLevel = config->valueint; + config = xzJSON_GetObjectItem(array, "rx_rf_port"); + gpioConfig.ch[i].rx.rf.port = config->valueint; + config = xzJSON_GetObjectItem(array, "rx_rf_pin"); + gpioConfig.ch[i].rx.rf.pin = config->valueint; + config = xzJSON_GetObjectItem(array, "rx_rf_enableLevel"); + gpioConfig.ch[i].rx.rf.enableLevel = config->valueint; + config = xzJSON_GetObjectItem(array, "rx_sw_port"); + gpioConfig.ch[i].rx.sw.port = config->valueint; + config = xzJSON_GetObjectItem(array, "rx_sw_pin"); + gpioConfig.ch[i].rx.sw.pin = config->valueint; + config = xzJSON_GetObjectItem(array, "rx_sw_enableLevel"); + gpioConfig.ch[i].rx.sw.enableLevel = config->valueint; + + config = xzJSON_GetObjectItem(array, "orx_trx_port"); + gpioConfig.ch[i].orx.trx.port = config->valueint; + config = xzJSON_GetObjectItem(array, "orx_trx_pin"); + gpioConfig.ch[i].orx.trx.pin = config->valueint; + config = xzJSON_GetObjectItem(array, "orx_trx_enableLevel"); + gpioConfig.ch[i].orx.trx.enableLevel = config->valueint; + config = xzJSON_GetObjectItem(array, "orx_rf_port"); + gpioConfig.ch[i].orx.rf.port = config->valueint; + config = xzJSON_GetObjectItem(array, "orx_rf_pin"); + gpioConfig.ch[i].orx.rf.pin = config->valueint; + config = xzJSON_GetObjectItem(array, "orx_rf_enableLevel"); + gpioConfig.ch[i].orx.rf.enableLevel = config->valueint; + config = xzJSON_GetObjectItem(array, "orx_sw_port"); + gpioConfig.ch[i].orx.sw.port = config->valueint; + config = xzJSON_GetObjectItem(array, "orx_sw_pin"); + gpioConfig.ch[i].orx.sw.pin = config->valueint; + config = xzJSON_GetObjectItem(array, "orx_sw_enableLevel"); + gpioConfig.ch[i].orx.sw.enableLevel = config->valueint; + } + + array = xzJSON_GetArrayItem(item, 4); + config = xzJSON_GetObjectItem(array, "triger_port"); + gpioConfig.triger.port = config->valueint; + config = xzJSON_GetObjectItem(array, "triger_pin"); + gpioConfig.triger.pin = config->valueint; + config = xzJSON_GetObjectItem(array, "triger_enableLevel"); + gpioConfig.triger.enableLevel = config->valueint; + + return gpioConfig; +} + +ucp_rfic_cfg_t ucp_GetRficCfgInfo(void) +{ + ucp_rfic_cfg_t st_rfic_cfg; + xzJSON *root = NULL; + xzJSON *item = NULL; + xzJSON *config = NULL; + + root = ucp_jsonLoad(RFIC_CFG_FILE_PATH); + if (((xzJSON*)NULL) == root) + { + printf("rfic_get_cfg_info: load file error!\r\n"); + exit(1); + } + + item = xzJSON_GetObjectItem(root, "common"); + config = xzJSON_GetObjectItem(item, "txLo"); + st_rfic_cfg.txLo = config->valuedouble; + config = xzJSON_GetObjectItem(item, "rxLo"); + st_rfic_cfg.rxLo = config->valuedouble; + config = xzJSON_GetObjectItem(item, "auxLo"); + st_rfic_cfg.auxLo = config->valuedouble; + config = xzJSON_GetObjectItem(item, "initAtt"); + st_rfic_cfg.initAtt = config->valueint; + config = xzJSON_GetObjectItem(item, "initGain"); + st_rfic_cfg.initGain = config->valueint; + + item = xzJSON_GetObjectItem(root, "para"); + config = xzJSON_GetObjectItem(item, "sampleRate"); + st_rfic_cfg.sampleRate = config->valueint; + config = xzJSON_GetObjectItem(item, "bw"); + st_rfic_cfg.bw = config->valuedouble; + config = xzJSON_GetObjectItem(item, "antNumb"); + st_rfic_cfg.antNumb = config->valuedouble; + config = xzJSON_GetObjectItem(item, "enFdd"); + st_rfic_cfg.enFdd = config->valuedouble; + config = xzJSON_GetObjectItem(item, "enOrx"); + st_rfic_cfg.enOrx = config->valuedouble; + config = xzJSON_GetObjectItem(item, "en204C"); + st_rfic_cfg.en204C = config->valuedouble; + config = xzJSON_GetObjectItem(item, "enUcpLog"); + st_rfic_cfg.enUcpLog = config->valuedouble; + + config = xzJSON_GetObjectItem(item, "calOrxGainIndex"); + st_rfic_cfg.calOrxGainIndex = config->valueint; + + item = xzJSON_GetObjectItem(item, "calChAttPara"); + config = xzJSON_GetObjectItem(item, "ch1"); + st_rfic_cfg.calChAttPara[0] = config->valueint; + config = xzJSON_GetObjectItem(item, "ch2"); + st_rfic_cfg.calChAttPara[1] = config->valueint; + config = xzJSON_GetObjectItem(item, "ch3"); + st_rfic_cfg.calChAttPara[2] = config->valueint; + config = xzJSON_GetObjectItem(item, "ch4"); + st_rfic_cfg.calChAttPara[3] = config->valueint; + + xzJSON_Delete(root); + + return st_rfic_cfg; +} + +ucp_rfic_calPara_t ucp_GetRficCalParaInfo(void) +{ + ucp_rfic_calPara_t st_rfic_para; + xzJSON *root = NULL; + xzJSON *item = NULL; + xzJSON *config = NULL; + + root = ucp_jsonLoad(RFIC_CAL_FILE_PATH); + if (((xzJSON*)NULL) == root) + { + printf("rfic_get_cfg_info: load file error!\r\n"); + exit(1); + } + + config = xzJSON_GetObjectItem(root, "calOrxGainIndex"); + st_rfic_para.calOrxGainIndex = config->valueint; + + item = xzJSON_GetObjectItem(root, "calChAttPara"); + config = xzJSON_GetObjectItem(item, "ch1"); + st_rfic_para.calChAttPara[0] = config->valueint; + config = xzJSON_GetObjectItem(item, "ch2"); + st_rfic_para.calChAttPara[1] = config->valueint; + config = xzJSON_GetObjectItem(item, "ch3"); + st_rfic_para.calChAttPara[2] = config->valueint; + config = xzJSON_GetObjectItem(item, "ch4"); + st_rfic_para.calChAttPara[3] = config->valueint; + + xzJSON_Delete(root); + + return st_rfic_para; +} + +#if 0 +int main(int argc, char *argv[]) +{ + ucp_jesd_TrxGpioCfg_t gpioConfig; + + ucp_GenGpioConfig("./ucp_trx_gpioCfg.json"); + gpioConfig = ucp_GetGpioConfig("./ucp_trx_gpioCfg_evb.json"); + ucp_printGpioConfigStruct(gpioConfig); + + return 0; +} +#endif diff --git a/driver/rfic/ucp/base/src/ucp_jsonTools.o b/driver/rfic/ucp/base/src/ucp_jsonTools.o new file mode 100644 index 0000000..dffd4fc Binary files /dev/null and b/driver/rfic/ucp/base/src/ucp_jsonTools.o differ diff --git a/driver/rfic/ucp/base/src/ucp_reg_io.c b/driver/rfic/ucp/base/src/ucp_reg_io.c new file mode 100644 index 0000000..262df81 --- /dev/null +++ b/driver/rfic/ucp/base/src/ucp_reg_io.c @@ -0,0 +1,206 @@ +//******************** (C) COPYRIGHT 2022 SmartLogic******************************* +// FileName : ucp_reg_io.c +// Author : boheng.lin@smartlogictech.com +// Date First Issued : 2022-09-08 02:37:50 PM +// Last Modified : +// Description : +// ------------------------------------------------------------ +// Modification History: +// Version Date Author Modification Description +// +//********************************************************************************** + +#include + +#include +#include +#include +#include +#include +#include + +#define ARGV_CMD_POS 1 +#define ARGV_ADDR_POS 2 +#define ARGV_DATA_POS 3 +#define ARGV_RBYTE_POS 3 +#define ARGV_WBYTE_POS 4 + +#define IOCTL_MMAPREG _IO('k',0x20) + +static int regfd = 0; + +typedef union c2u32_t +{ + char c[4]; + uint32_t u; +} tC2u32; + +typedef union c2u16_t +{ + char c[2]; + uint16_t u; +} tC2u16; + +int ucp_reg_init (void) +{ + if (0 != regfd) + { + close(regfd); + } + + regfd = open("/dev/ioreg", O_RDWR); + if (regfd < 0) + { + printf("open(/dev/ioreg) failed."); + return 0; + } + + return regfd; +} + +void ucp_reg32_or_write(uint64_t reg, uint32_t mask) +{ + tC2u32 val; + + if((reg%4) != 0) + { + printf("Addr Err.\r\n"); + return; + } + + // printf("orW: %08X %08X\n", (uint32_t)reg, mask); + val.u = 0; + ioctl(regfd, IOCTL_MMAPREG, ®); + read(regfd,(char*)val.c, 4); + val.u |= mask; + ioctl(regfd, IOCTL_MMAPREG, ®); + write(regfd, val.c, 4); + + return; +} + +void ucp_reg32_and_write(uint64_t reg, uint32_t mask) +{ + tC2u32 val; + + if((reg%4) != 0) + { + printf("Addr Err.\r\n"); + return; + } + + // printf("andW: %08X %08X\n", (uint32_t)reg, mask); + val.u = 0; + mask = ~mask; + ioctl(regfd, IOCTL_MMAPREG, ®); + read(regfd,(char*)val.c, 4); + val.u &= mask; + ioctl(regfd, IOCTL_MMAPREG, ®); + write(regfd, val.c, 4); + + return; +} + +uint32_t ucp_reg32_and_read(uint64_t reg, uint32_t mask) +{ + tC2u32 val; + + if((reg%4) != 0) + { + printf("Addr Err.\r\n"); + return 0; + } + + val.u = 0; + ioctl(regfd, IOCTL_MMAPREG, ®); + read(regfd,(char*)val.c, 4); + val.u &= mask; + + return val.u; + +} + +void ucp_reg16_write(uint64_t reg, uint16_t data) +{ + tC2u16 val; + + if((reg%2) != 0) + { + printf("Addr Err.\r\n"); + return; + } + + val.u = data; + ioctl(regfd, IOCTL_MMAPREG, ®); + write(regfd, val.c, 2); + + return; +} + +uint16_t ucp_reg16_read(uint64_t reg) +{ + tC2u16 val; + + if((reg%2) != 0) + { + printf("Addr Err.\r\n"); + return 0; + } + + val.u = 0; + ioctl(regfd, IOCTL_MMAPREG, ®); + read(regfd,(char*)val.c, 2); + + return val.u; +} + +void ucp_reg32_write(uint64_t reg, uint32_t data) +{ + tC2u32 val; + + if((reg%4) != 0) + { + printf("Addr Err.\r\n"); + return; + } + + val.u = data; + ioctl(regfd, IOCTL_MMAPREG, ®); + write(regfd, val.c, 4); + + return; +} + +uint32_t ucp_reg32_read(uint64_t reg) +{ + tC2u32 val; + + if((reg%4) != 0) + { + printf("Addr Err. @%s\r\n", __func__); + return 0; + } + + val.u = 0; + ioctl(regfd, IOCTL_MMAPREG, ®); + read(regfd,(char*)val.c, 4); + + return val.u; +} + +void ucp_reg_test(void) +{ + ucp_reg_init(); + + printf("reg 0 = 0x%X\n", ucp_reg32_read(0x4458000+0x17c)); + ucp_reg32_write(0x4458000+0x17c, 0x15c03001); + printf("reg 1 = 0x%X\n", ucp_reg32_read(0x4458000+0x17c)); + ucp_reg32_or_write(0x4458000+0x17c, 0x01); + printf("reg 2 = 0x%X\n", ucp_reg32_read(0x4458000+0x17c)); + ucp_reg32_and_write(0x4458000+0x17c, 0x10); + printf("reg 3 = 0x%X\n", ucp_reg32_read(0x4458000+0x17c)); + printf("reg 4 = 0x%X\n", ucp_reg32_and_read(0x4458000+0x17c, 0x01)); + printf("reg 5 = 0x%X\n", ucp_reg32_and_read(0x4458000+0x17c, 0x10)); +} + + diff --git a/driver/rfic/ucp/base/src/ucp_reg_io.o b/driver/rfic/ucp/base/src/ucp_reg_io.o new file mode 100644 index 0000000..718a5e9 Binary files /dev/null and b/driver/rfic/ucp/base/src/ucp_reg_io.o differ diff --git a/driver/rfic/ucp/base/src/wafer.c b/driver/rfic/ucp/base/src/wafer.c new file mode 100644 index 0000000..1123f20 --- /dev/null +++ b/driver/rfic/ucp/base/src/wafer.c @@ -0,0 +1,32770 @@ +int pma_fw[16384*2] ={ + 0x081D, + 0xFFFF, + 0xD362, + 0xD34B, + 0xD37D, + 0x1CC0, + 0xA2C4, + 0xD2F1, + 0x02A6, + 0xD009, + 0xD34C, + 0xD62D, + 0xD4CD, + 0xD35D, + 0xD35E, + 0x0C1E, + 0x080F, + 0x4000, + 0xD22B, + 0x080F, + 0x1000, + 0xD243, + 0x080F, + 0x4000, + 0xD240, + 0x080F, + 0x8000, + 0xD240, + 0x1CC1, + 0xA021, + 0x1CC3, + 0xA0AA, + 0x8138, + 0x0C6F, + 0x0417, + 0x0003, + 0x0C6F, + 0x04B6, + 0x0002, + 0x0C4F, + 0xD408, + 0x0C4E, + 0x1C9D, + 0xA02D, + 0x8031, + 0x0406, + 0x0003, + 0x0C4F, + 0xD49D, + 0xD365, + 0xD364, + 0x080F, + 0x0100, + 0xD36A, + 0x0315, + 0x0358, + 0xD49C, + 0xDD31, + 0xD52C, + 0x0C4F, + 0xD40A, + 0x080F, + 0x8000, + 0xD355, + 0x080F, + 0x2000, + 0xD355, + 0xD367, + 0xD372, + 0xD370, + 0xD371, + 0x080E, + 0x4000, + 0x1C0F, + 0xA13B, + 0xDCC7, + 0xDC9B, + 0xDCCB, + 0xDCCC, + 0xD41A, + 0xDCE9, + 0xDCE7, + 0xDCE5, + 0xDCE3, + 0xDCEB, + 0xDCED, + 0x080F, + 0x0020, + 0xD375, + 0x0E0F, + 0xD376, + 0x080F, + 0x0200, + 0xD376, + 0x080F, + 0x4000, + 0xD376, + 0x0E0F, + 0xD375, + 0x0D0E, + 0x1E2C, + 0x0C2F, + 0x2E67, + 0x080F, + 0x0400, + 0xD405, + 0x0C4F, + 0xDA87, + 0x0D0F, + 0xDA87, + 0x0E0F, + 0xD287, + 0x080F, + 0x4000, + 0xD364, + 0x080F, + 0x0030, + 0xD220, + 0x0C4F, + 0xD42B, + 0x0E0F, + 0xD40C, + 0x1D05, + 0xA07F, + 0xD61F, + 0xD61D, + 0x808F, + 0x31AC, + 0x0C6D, + 0x558D, + 0xA086, + 0xD61F, + 0xD61D, + 0x808F, + 0x5C2D, + 0xA08B, + 0xD6C4, + 0xD6C2, + 0x808F, + 0x5C2D, + 0xA08F, + 0xD62A, + 0xD628, + 0x0C2E, + 0x1F08, + 0x080F, + 0x0100, + 0x2E44, + 0x0C2E, + 0x1F09, + 0x080F, + 0x0200, + 0x2E44, + 0x0C2E, + 0x1F0A, + 0x080F, + 0x0400, + 0x2E44, + 0x0C2F, + 0xD708, + 0x0C2F, + 0xD709, + 0x0C2F, + 0xD70A, + 0xD36C, + 0xD36A, + 0x0DEF, + 0x04B6, + 0x0002, + 0x80AE, + 0xD49B, + 0x080F, + 0x0F00, + 0xD644, + 0x04CD, + 0x0020, + 0x0368, + 0x1E38, + 0x0368, + 0x0E38, + 0xD49C, + 0x0C2F, + 0xD708, + 0x0C2F, + 0xD709, + 0x0C2F, + 0xD70A, + 0xDD31, + 0x1E97, + 0xA0BF, + 0x80C2, + 0x1C5E, + 0xA0C2, + 0x80DE, + 0x0C4F, + 0xD287, + 0x0D0F, + 0xD287, + 0x0FEF, + 0x040C, + 0x0010, + 0x1C9B, + 0xA0CC, + 0x80D4, + 0xD406, + 0x0C4F, + 0xDC08, + 0x1C5D, + 0xA0D2, + 0x80CF, + 0x1CB7, + 0xA0D2, + 0x0C6F, + 0xD4B6, + 0x0C4F, + 0xD408, + 0x0C4F, + 0xDC9D, + 0x0806, + 0x00E1, + 0x0C39, + 0x8D9A, + 0x0816, + 0x00E1, + 0x8E40, + 0x0C4F, + 0xD49D, + 0x1CDF, + 0xA0E6, + 0x80EC, + 0x0C1B, + 0x0C3C, + 0x0806, + 0x00EC, + 0x0C3F, + 0x8ABA, + 0xDCE0, + 0x1D10, + 0x2D12, + 0xD406, + 0xDD16, + 0xDCC9, + 0x1CB7, + 0xA0F2, + 0x1C68, + 0xA103, + 0x080E, + 0x8000, + 0x1CA3, + 0xA0FB, + 0x8103, + 0x080E, + 0x00E0, + 0x1CA3, + 0xA100, + 0x8103, + 0x7402, + 0x5C2D, + 0x80FE, + 0x080E, + 0x0100, + 0x1E44, + 0x0C2F, + 0x2F08, + 0x080E, + 0x0200, + 0x1E44, + 0x0C2F, + 0x2F09, + 0x080E, + 0x0400, + 0x1E44, + 0x0C2F, + 0x2F0A, + 0x080E, + 0x1000, + 0x1E44, + 0x0C8F, + 0x2F08, + 0x080E, + 0x2000, + 0x1E44, + 0x0C8F, + 0x2F09, + 0x080E, + 0x4000, + 0x1E44, + 0x0C8F, + 0x2F0A, + 0x080E, + 0x8000, + 0x1E50, + 0xA12D, + 0x1A9D, + 0x1A9D, + 0x2E40, + 0x080E, + 0x4000, + 0x1E50, + 0xA138, + 0x8138, + 0x0640, + 0x2000, + 0x080E, + 0x4000, + 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b/driver/rfic/ucp/cJSON/inc/xzJSON.h @@ -0,0 +1,300 @@ +/* + Copyright (c) 2009-2017 Dave Gamble and xzJSON contributors + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + THE SOFTWARE. +*/ + +#ifndef xzJSON__h +#define xzJSON__h + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !defined(__WINDOWS__) && (defined(WIN32) || defined(WIN64) || defined(_MSC_VER) || defined(_WIN32)) +#define __WINDOWS__ +#endif + +#ifdef __WINDOWS__ + +/* When compiling for windows, we specify a specific calling convention to avoid issues where we are being called from a project with a different default calling convention. For windows you have 3 define options: + +CJSON_HIDE_SYMBOLS - Define this in the case where you don't want to ever dllexport symbols +CJSON_EXPORT_SYMBOLS - Define this on library build when you want to dllexport symbols (default) +CJSON_IMPORT_SYMBOLS - Define this if you want to dllimport symbol + +For *nix builds that support visibility attribute, you can define similar behavior by + +setting default visibility to hidden by adding +-fvisibility=hidden (for gcc) +or +-xldscope=hidden (for sun cc) +to CFLAGS + +then using the CJSON_API_VISIBILITY flag to "export" the same symbols the way CJSON_EXPORT_SYMBOLS does + +*/ + +#define CJSON_CDECL __cdecl +#define CJSON_STDCALL __stdcall + +/* export symbols by default, this is necessary for copy pasting the C and header file */ +#if !defined(CJSON_HIDE_SYMBOLS) && !defined(CJSON_IMPORT_SYMBOLS) && !defined(CJSON_EXPORT_SYMBOLS) +#define CJSON_EXPORT_SYMBOLS +#endif + +#if defined(CJSON_HIDE_SYMBOLS) +#define XZJSON_PUBLIC(type) type CJSON_STDCALL +#elif defined(CJSON_EXPORT_SYMBOLS) +#define XZJSON_PUBLIC(type) __declspec(dllexport) type CJSON_STDCALL +#elif defined(CJSON_IMPORT_SYMBOLS) +#define XZJSON_PUBLIC(type) __declspec(dllimport) type CJSON_STDCALL +#endif +#else /* !__WINDOWS__ */ +#define CJSON_CDECL +#define CJSON_STDCALL + +#if (defined(__GNUC__) || defined(__SUNPRO_CC) || defined (__SUNPRO_C)) && defined(CJSON_API_VISIBILITY) +#define XZJSON_PUBLIC(type) __attribute__((visibility("default"))) type +#else +#define XZJSON_PUBLIC(type) type +#endif +#endif + +/* project version */ +#define CJSON_VERSION_MAJOR 1 +#define CJSON_VERSION_MINOR 7 +#define CJSON_VERSION_PATCH 16 + +#include + +/* xzJSON Types: */ +#define xzJSON_Invalid (0) +#define xzJSON_False (1 << 0) +#define xzJSON_True (1 << 1) +#define xzJSON_NULL (1 << 2) +#define xzJSON_Number (1 << 3) +#define xzJSON_String (1 << 4) +#define xzJSON_Array (1 << 5) +#define xzJSON_Object (1 << 6) +#define xzJSON_Raw (1 << 7) /* raw json */ + +#define xzJSON_IsReference 256 +#define xzJSON_StringIsConst 512 + +/* The xzJSON structure: */ +typedef struct xzJSON +{ + /* next/prev allow you to walk array/object chains. Alternatively, use GetArraySize/GetArrayItem/GetObjectItem */ + struct xzJSON *next; + struct xzJSON *prev; + /* An array or object item will have a child pointer pointing to a chain of the items in the array/object. */ + struct xzJSON *child; + + /* The type of the item, as above. */ + int type; + + /* The item's string, if type==xzJSON_String and type == xzJSON_Raw */ + char *valuestring; + /* writing to valueint is DEPRECATED, use xzJSON_SetNumberValue instead */ + int valueint; + /* The item's number, if type==xzJSON_Number */ + double valuedouble; + + /* The item's name string, if this item is the child of, or is in the list of subitems of an object. */ + char *string; +} xzJSON; + +typedef struct xzJSON_Hooks +{ + /* malloc/free are CDECL on Windows regardless of the default calling convention of the compiler, so ensure the hooks allow passing those functions directly. */ + void *(CJSON_CDECL *malloc_fn)(size_t sz); + void (CJSON_CDECL *free_fn)(void *ptr); +} xzJSON_Hooks; + +typedef int xzJSON_bool; + +/* Limits how deeply nested arrays/objects can be before xzJSON rejects to parse them. + * This is to prevent stack overflows. */ +#ifndef CJSON_NESTING_LIMIT +#define CJSON_NESTING_LIMIT 1000 +#endif + +/* returns the version of xzJSON as a string */ +XZJSON_PUBLIC(const char*) xzJSON_Version(void); + +/* Supply malloc, realloc and free functions to xzJSON */ +XZJSON_PUBLIC(void) xzJSON_InitHooks(xzJSON_Hooks* hooks); + +/* Memory Management: the caller is always responsible to free the results from all variants of xzJSON_Parse (with xzJSON_Delete) and xzJSON_Print (with stdlib free, xzJSON_Hooks.free_fn, or xzJSON_free as appropriate). The exception is xzJSON_PrintPreallocated, where the caller has full responsibility of the buffer. */ +/* Supply a block of JSON, and this returns a xzJSON object you can interrogate. */ +XZJSON_PUBLIC(xzJSON *) xzJSON_Parse(const char *value); +XZJSON_PUBLIC(xzJSON *) xzJSON_ParseWithLength(const char *value, size_t buffer_length); +/* ParseWithOpts allows you to require (and check) that the JSON is null terminated, and to retrieve the pointer to the final byte parsed. */ +/* If you supply a ptr in return_parse_end and parsing fails, then return_parse_end will contain a pointer to the error so will match xzJSON_GetErrorPtr(). */ +XZJSON_PUBLIC(xzJSON *) xzJSON_ParseWithOpts(const char *value, const char **return_parse_end, xzJSON_bool require_null_terminated); +XZJSON_PUBLIC(xzJSON *) xzJSON_ParseWithLengthOpts(const char *value, size_t buffer_length, const char **return_parse_end, xzJSON_bool require_null_terminated); + +/* Render a xzJSON entity to text for transfer/storage. */ +XZJSON_PUBLIC(char *) xzJSON_Print(const xzJSON *item); +/* Render a xzJSON entity to text for transfer/storage without any formatting. */ +XZJSON_PUBLIC(char *) xzJSON_PrintUnformatted(const xzJSON *item); +/* Render a xzJSON entity to text using a buffered strategy. prebuffer is a guess at the final size. guessing well reduces reallocation. fmt=0 gives unformatted, =1 gives formatted */ +XZJSON_PUBLIC(char *) xzJSON_PrintBuffered(const xzJSON *item, int prebuffer, xzJSON_bool fmt); +/* Render a xzJSON entity to text using a buffer already allocated in memory with given length. Returns 1 on success and 0 on failure. */ +/* NOTE: xzJSON is not always 100% accurate in estimating how much memory it will use, so to be safe allocate 5 bytes more than you actually need */ +XZJSON_PUBLIC(xzJSON_bool) xzJSON_PrintPreallocated(xzJSON *item, char *buffer, const int length, const xzJSON_bool format); +/* Delete a xzJSON entity and all subentities. */ +XZJSON_PUBLIC(void) xzJSON_Delete(xzJSON *item); + +/* Returns the number of items in an array (or object). */ +XZJSON_PUBLIC(int) xzJSON_GetArraySize(const xzJSON *array); +/* Retrieve item number "index" from array "array". Returns NULL if unsuccessful. */ +XZJSON_PUBLIC(xzJSON *) xzJSON_GetArrayItem(const xzJSON *array, int index); +/* Get item "string" from object. Case insensitive. */ +XZJSON_PUBLIC(xzJSON *) xzJSON_GetObjectItem(const xzJSON * const object, const char * const string); +XZJSON_PUBLIC(xzJSON *) xzJSON_GetObjectItemCaseSensitive(const xzJSON * const object, const char * const string); +XZJSON_PUBLIC(xzJSON_bool) xzJSON_HasObjectItem(const xzJSON *object, const char *string); +/* For analysing failed parses. This returns a pointer to the parse error. You'll probably need to look a few chars back to make sense of it. Defined when xzJSON_Parse() returns 0. 0 when xzJSON_Parse() succeeds. */ +XZJSON_PUBLIC(const char *) xzJSON_GetErrorPtr(void); + +/* Check item type and return its value */ +XZJSON_PUBLIC(char *) xzJSON_GetStringValue(const xzJSON * const item); +XZJSON_PUBLIC(double) xzJSON_GetNumberValue(const xzJSON * const item); + +/* These functions check the type of an item */ +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsInvalid(const xzJSON * const item); +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsFalse(const xzJSON * const item); +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsTrue(const xzJSON * const item); +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsBool(const xzJSON * const item); +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsNull(const xzJSON * const item); +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsNumber(const xzJSON * const item); +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsString(const xzJSON * const item); +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsArray(const xzJSON * const item); +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsObject(const xzJSON * const item); +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsRaw(const xzJSON * const item); + +/* These calls create a xzJSON item of the appropriate type. */ +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateNull(void); +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateTrue(void); +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateFalse(void); +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateBool(xzJSON_bool boolean); +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateNumber(double num); +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateString(const char *string); +/* raw json */ +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateRaw(const char *raw); +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateArray(void); +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateObject(void); + +/* Create a string where valuestring references a string so + * it will not be freed by xzJSON_Delete */ +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateStringReference(const char *string); +/* Create an object/array that only references it's elements so + * they will not be freed by xzJSON_Delete */ +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateObjectReference(const xzJSON *child); +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateArrayReference(const xzJSON *child); + +/* These utilities create an Array of count items. + * The parameter count cannot be greater than the number of elements in the number array, otherwise array access will be out of bounds.*/ +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateIntArray(const int *numbers, int count); +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateFloatArray(const float *numbers, int count); +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateDoubleArray(const double *numbers, int count); +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateStringArray(const char *const *strings, int count); + +/* Append item to the specified array/object. */ +XZJSON_PUBLIC(xzJSON_bool) xzJSON_AddItemToArray(xzJSON *array, xzJSON *item); +XZJSON_PUBLIC(xzJSON_bool) xzJSON_AddItemToObject(xzJSON *object, const char *string, xzJSON *item); +/* Use this when string is definitely const (i.e. a literal, or as good as), and will definitely survive the xzJSON object. + * WARNING: When this function was used, make sure to always check that (item->type & xzJSON_StringIsConst) is zero before + * writing to `item->string` */ +XZJSON_PUBLIC(xzJSON_bool) xzJSON_AddItemToObjectCS(xzJSON *object, const char *string, xzJSON *item); +/* Append reference to item to the specified array/object. Use this when you want to add an existing xzJSON to a new xzJSON, but don't want to corrupt your existing xzJSON. */ +XZJSON_PUBLIC(xzJSON_bool) xzJSON_AddItemReferenceToArray(xzJSON *array, xzJSON *item); +XZJSON_PUBLIC(xzJSON_bool) xzJSON_AddItemReferenceToObject(xzJSON *object, const char *string, xzJSON *item); + +/* Remove/Detach items from Arrays/Objects. */ +XZJSON_PUBLIC(xzJSON *) xzJSON_DetachItemViaPointer(xzJSON *parent, xzJSON * const item); +XZJSON_PUBLIC(xzJSON *) xzJSON_DetachItemFromArray(xzJSON *array, int which); +XZJSON_PUBLIC(void) xzJSON_DeleteItemFromArray(xzJSON *array, int which); +XZJSON_PUBLIC(xzJSON *) xzJSON_DetachItemFromObject(xzJSON *object, const char *string); +XZJSON_PUBLIC(xzJSON *) xzJSON_DetachItemFromObjectCaseSensitive(xzJSON *object, const char *string); +XZJSON_PUBLIC(void) xzJSON_DeleteItemFromObject(xzJSON *object, const char *string); +XZJSON_PUBLIC(void) xzJSON_DeleteItemFromObjectCaseSensitive(xzJSON *object, const char *string); + +/* Update array items. */ +XZJSON_PUBLIC(xzJSON_bool) xzJSON_InsertItemInArray(xzJSON *array, int which, xzJSON *newitem); /* Shifts pre-existing items to the right. */ +XZJSON_PUBLIC(xzJSON_bool) xzJSON_ReplaceItemViaPointer(xzJSON * const parent, xzJSON * const item, xzJSON * replacement); +XZJSON_PUBLIC(xzJSON_bool) xzJSON_ReplaceItemInArray(xzJSON *array, int which, xzJSON *newitem); +XZJSON_PUBLIC(xzJSON_bool) xzJSON_ReplaceItemInObject(xzJSON *object,const char *string,xzJSON *newitem); +XZJSON_PUBLIC(xzJSON_bool) xzJSON_ReplaceItemInObjectCaseSensitive(xzJSON *object,const char *string,xzJSON *newitem); + +/* Duplicate a xzJSON item */ +XZJSON_PUBLIC(xzJSON *) xzJSON_Duplicate(const xzJSON *item, xzJSON_bool recurse); +/* Duplicate will create a new, identical xzJSON item to the one you pass, in new memory that will + * need to be released. With recurse!=0, it will duplicate any children connected to the item. + * The item->next and ->prev pointers are always zero on return from Duplicate. */ +/* Recursively compare two xzJSON items for equality. If either a or b is NULL or invalid, they will be considered unequal. + * case_sensitive determines if object keys are treated case sensitive (1) or case insensitive (0) */ +XZJSON_PUBLIC(xzJSON_bool) xzJSON_Compare(const xzJSON * const a, const xzJSON * const b, const xzJSON_bool case_sensitive); + +/* Minify a strings, remove blank characters(such as ' ', '\t', '\r', '\n') from strings. + * The input pointer json cannot point to a read-only address area, such as a string constant, + * but should point to a readable and writable address area. */ +XZJSON_PUBLIC(void) xzJSON_Minify(char *json); + +/* Helper functions for creating and adding items to an object at the same time. + * They return the added item or NULL on failure. */ +XZJSON_PUBLIC(xzJSON*) xzJSON_AddNullToObject(xzJSON * const object, const char * const name); +XZJSON_PUBLIC(xzJSON*) xzJSON_AddTrueToObject(xzJSON * const object, const char * const name); +XZJSON_PUBLIC(xzJSON*) xzJSON_AddFalseToObject(xzJSON * const object, const char * const name); +XZJSON_PUBLIC(xzJSON*) xzJSON_AddBoolToObject(xzJSON * const object, const char * const name, const xzJSON_bool boolean); +XZJSON_PUBLIC(xzJSON*) xzJSON_AddNumberToObject(xzJSON * const object, const char * const name, const double number); +XZJSON_PUBLIC(xzJSON*) xzJSON_AddStringToObject(xzJSON * const object, const char * const name, const char * const string); +XZJSON_PUBLIC(xzJSON*) xzJSON_AddRawToObject(xzJSON * const object, const char * const name, const char * const raw); +XZJSON_PUBLIC(xzJSON*) xzJSON_AddObjectToObject(xzJSON * const object, const char * const name); +XZJSON_PUBLIC(xzJSON*) xzJSON_AddArrayToObject(xzJSON * const object, const char * const name); + +/* When assigning an integer value, it needs to be propagated to valuedouble too. */ +#define xzJSON_SetIntValue(object, number) ((object) ? (object)->valueint = (object)->valuedouble = (number) : (number)) +/* helper for the xzJSON_SetNumberValue macro */ +XZJSON_PUBLIC(double) xzJSON_SetNumberHelper(xzJSON *object, double number); +#define xzJSON_SetNumberValue(object, number) ((object != NULL) ? xzJSON_SetNumberHelper(object, (double)number) : (number)) +/* Change the valuestring of a xzJSON_String object, only takes effect when type of object is xzJSON_String */ +XZJSON_PUBLIC(char*) xzJSON_SetValuestring(xzJSON *object, const char *valuestring); + +/* If the object is not a boolean type this does nothing and returns xzJSON_Invalid else it returns the new type*/ +#define xzJSON_SetBoolValue(object, boolValue) ( \ + (object != NULL && ((object)->type & (xzJSON_False|xzJSON_True))) ? \ + (object)->type=((object)->type &(~(xzJSON_False|xzJSON_True)))|((boolValue)?xzJSON_True:xzJSON_False) : \ + xzJSON_Invalid\ +) + +/* Macro for iterating over an array or object */ +#define xzJSON_ArrayForEach(element, array) for(element = (array != NULL) ? (array)->child : NULL; element != NULL; element = element->next) + +/* malloc/free objects using the malloc/free functions that have been set with xzJSON_InitHooks */ +XZJSON_PUBLIC(void *) xzJSON_malloc(size_t size); +XZJSON_PUBLIC(void) xzJSON_free(void *object); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/ucp/cJSON/inc/xzJSON_Utils.h b/driver/rfic/ucp/cJSON/inc/xzJSON_Utils.h new file mode 100644 index 0000000..b7b4a15 --- /dev/null +++ b/driver/rfic/ucp/cJSON/inc/xzJSON_Utils.h @@ -0,0 +1,88 @@ +/* + Copyright (c) 2009-2017 Dave Gamble and xzJSON contributors + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + THE SOFTWARE. +*/ + +#ifndef xzJSON_Utils__h +#define xzJSON_Utils__h + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "xzJSON.h" + +/* Implement RFC6901 (https://tools.ietf.org/html/rfc6901) JSON Pointer spec. */ +XZJSON_PUBLIC(xzJSON *) xzJSONUtils_GetPointer(xzJSON * const object, const char *pointer); +XZJSON_PUBLIC(xzJSON *) xzJSONUtils_GetPointerCaseSensitive(xzJSON * const object, const char *pointer); + +/* Implement RFC6902 (https://tools.ietf.org/html/rfc6902) JSON Patch spec. */ +/* NOTE: This modifies objects in 'from' and 'to' by sorting the elements by their key */ +XZJSON_PUBLIC(xzJSON *) xzJSONUtils_GeneratePatches(xzJSON * const from, xzJSON * const to); +XZJSON_PUBLIC(xzJSON *) xzJSONUtils_GeneratePatchesCaseSensitive(xzJSON * const from, xzJSON * const to); +/* Utility for generating patch array entries. */ +XZJSON_PUBLIC(void) xzJSONUtils_AddPatchToArray(xzJSON * const array, const char * const operation, const char * const path, const xzJSON * const value); +/* Returns 0 for success. */ +XZJSON_PUBLIC(int) xzJSONUtils_ApplyPatches(xzJSON * const object, const xzJSON * const patches); +XZJSON_PUBLIC(int) xzJSONUtils_ApplyPatchesCaseSensitive(xzJSON * const object, const xzJSON * const patches); + +/* +// Note that ApplyPatches is NOT atomic on failure. To implement an atomic ApplyPatches, use: +//int xzJSONUtils_AtomicApplyPatches(xzJSON **object, xzJSON *patches) +//{ +// xzJSON *modme = xzJSON_Duplicate(*object, 1); +// int error = xzJSONUtils_ApplyPatches(modme, patches); +// if (!error) +// { +// xzJSON_Delete(*object); +// *object = modme; +// } +// else +// { +// xzJSON_Delete(modme); +// } +// +// return error; +//} +// Code not added to library since this strategy is a LOT slower. +*/ + +/* Implement RFC7386 (https://tools.ietf.org/html/rfc7396) JSON Merge Patch spec. */ +/* target will be modified by patch. return value is new ptr for target. */ +XZJSON_PUBLIC(xzJSON *) xzJSONUtils_MergePatch(xzJSON *target, const xzJSON * const patch); +XZJSON_PUBLIC(xzJSON *) xzJSONUtils_MergePatchCaseSensitive(xzJSON *target, const xzJSON * const patch); +/* generates a patch to move from -> to */ +/* NOTE: This modifies objects in 'from' and 'to' by sorting the elements by their key */ +XZJSON_PUBLIC(xzJSON *) xzJSONUtils_GenerateMergePatch(xzJSON * const from, xzJSON * const to); +XZJSON_PUBLIC(xzJSON *) xzJSONUtils_GenerateMergePatchCaseSensitive(xzJSON * const from, xzJSON * const to); + +/* Given a root object and a target object, construct a pointer from one to the other. */ +XZJSON_PUBLIC(char *) xzJSONUtils_FindPointerFromObjectTo(const xzJSON * const object, const xzJSON * const target); + +/* Sorts the members of the object into alphabetical order. */ +XZJSON_PUBLIC(void) xzJSONUtils_SortObject(xzJSON * const object); +XZJSON_PUBLIC(void) xzJSONUtils_SortObjectCaseSensitive(xzJSON * const object); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/rfic/ucp/cJSON/src/xzJSON.c b/driver/rfic/ucp/cJSON/src/xzJSON.c new file mode 100644 index 0000000..befcc72 --- /dev/null +++ b/driver/rfic/ucp/cJSON/src/xzJSON.c @@ -0,0 +1,3119 @@ +/* + Copyright (c) 2009-2017 Dave Gamble and xzJSON contributors + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + THE SOFTWARE. +*/ + +/* xzJSON */ +/* JSON parser in C. */ + +/* disable warnings about old C89 functions in MSVC */ +#if !defined(_CRT_SECURE_NO_DEPRECATE) && defined(_MSC_VER) +#define _CRT_SECURE_NO_DEPRECATE +#endif + +#ifdef __GNUC__ +#pragma GCC visibility push(default) +#endif +#if defined(_MSC_VER) +#pragma warning (push) +/* disable warning about single line comments in system headers */ +#pragma warning (disable : 4001) +#endif + +#include +#include +#include +#include +#include +#include +#include + +#ifdef ENABLE_LOCALES +#include +#endif + +#if defined(_MSC_VER) +#pragma warning (pop) +#endif +#ifdef __GNUC__ +#pragma GCC visibility pop +#endif + +#include "xzJSON.h" + +/* define our own boolean type */ +#ifdef true +#undef true +#endif +#define true ((xzJSON_bool)1) + +#ifdef false +#undef false +#endif +#define false ((xzJSON_bool)0) + +/* define isnan and isinf for ANSI C, if in C99 or above, isnan and isinf has been defined in math.h */ +#ifndef isinf +#define isinf(d) (isnan((d - d)) && !isnan(d)) +#endif +#ifndef isnan +#define isnan(d) (d != d) +#endif + +#ifndef NAN +#ifdef _WIN32 +#define NAN sqrt(-1.0) +#else +#define NAN 0.0/0.0 +#endif +#endif + +typedef struct { + const unsigned char *json; + size_t position; +} error; +static error global_error = { NULL, 0 }; + +XZJSON_PUBLIC(const char *) xzJSON_GetErrorPtr(void) +{ + return (const char*) (global_error.json + global_error.position); +} + +XZJSON_PUBLIC(char *) xzJSON_GetStringValue(const xzJSON * const item) +{ + if (!xzJSON_IsString(item)) + { + return NULL; + } + + return item->valuestring; +} + +XZJSON_PUBLIC(double) xzJSON_GetNumberValue(const xzJSON * const item) +{ + if (!xzJSON_IsNumber(item)) + { + return (double) NAN; + } + + return item->valuedouble; +} + +/* This is a safeguard to prevent copy-pasters from using incompatible C and header files */ +#if (CJSON_VERSION_MAJOR != 1) || (CJSON_VERSION_MINOR != 7) || (CJSON_VERSION_PATCH != 16) + #error xzJSON.h and xzJSON.c have different versions. Make sure that both have the same. +#endif + +XZJSON_PUBLIC(const char*) xzJSON_Version(void) +{ + static char version[15]; + sprintf(version, "%i.%i.%i", CJSON_VERSION_MAJOR, CJSON_VERSION_MINOR, CJSON_VERSION_PATCH); + + return version; +} + +/* Case insensitive string comparison, doesn't consider two NULL pointers equal though */ +static int case_insensitive_strcmp(const unsigned char *string1, const unsigned char *string2) +{ + if ((string1 == NULL) || (string2 == NULL)) + { + return 1; + } + + if (string1 == string2) + { + return 0; + } + + for(; tolower(*string1) == tolower(*string2); (void)string1++, string2++) + { + if (*string1 == '\0') + { + return 0; + } + } + + return tolower(*string1) - tolower(*string2); +} + +typedef struct internal_hooks +{ + void *(CJSON_CDECL *allocate)(size_t size); + void (CJSON_CDECL *deallocate)(void *pointer); + void *(CJSON_CDECL *reallocate)(void *pointer, size_t size); +} internal_hooks; + +#if defined(_MSC_VER) +/* work around MSVC error C2322: '...' address of dllimport '...' is not static */ +static void * CJSON_CDECL internal_malloc(size_t size) +{ + return malloc(size); +} +static void CJSON_CDECL internal_free(void *pointer) +{ + free(pointer); +} +static void * CJSON_CDECL internal_realloc(void *pointer, size_t size) +{ + return realloc(pointer, size); +} +#else +#define internal_malloc malloc +#define internal_free free +#define internal_realloc realloc +#endif + +/* strlen of character literals resolved at compile time */ +#define static_strlen(string_literal) (sizeof(string_literal) - sizeof("")) + +static internal_hooks global_hooks = { internal_malloc, internal_free, internal_realloc }; + +static unsigned char* xzJSON_strdup(const unsigned char* string, const internal_hooks * const hooks) +{ + size_t length = 0; + unsigned char *copy = NULL; + + if (string == NULL) + { + return NULL; + } + + length = strlen((const char*)string) + sizeof(""); + copy = (unsigned char*)hooks->allocate(length); + if (copy == NULL) + { + return NULL; + } + memcpy(copy, string, length); + + return copy; +} + +XZJSON_PUBLIC(void) xzJSON_InitHooks(xzJSON_Hooks* hooks) +{ + if (hooks == NULL) + { + /* Reset hooks */ + global_hooks.allocate = malloc; + global_hooks.deallocate = free; + global_hooks.reallocate = realloc; + return; + } + + global_hooks.allocate = malloc; + if (hooks->malloc_fn != NULL) + { + global_hooks.allocate = hooks->malloc_fn; + } + + global_hooks.deallocate = free; + if (hooks->free_fn != NULL) + { + global_hooks.deallocate = hooks->free_fn; + } + + /* use realloc only if both free and malloc are used */ + global_hooks.reallocate = NULL; + if ((global_hooks.allocate == malloc) && (global_hooks.deallocate == free)) + { + global_hooks.reallocate = realloc; + } +} + +/* Internal constructor. */ +static xzJSON *xzJSON_New_Item(const internal_hooks * const hooks) +{ + xzJSON* node = (xzJSON*)hooks->allocate(sizeof(xzJSON)); + if (node) + { + memset(node, '\0', sizeof(xzJSON)); + } + + return node; +} + +/* Delete a xzJSON structure. */ +XZJSON_PUBLIC(void) xzJSON_Delete(xzJSON *item) +{ + xzJSON *next = NULL; + while (item != NULL) + { + next = item->next; + if (!(item->type & xzJSON_IsReference) && (item->child != NULL)) + { + xzJSON_Delete(item->child); + } + if (!(item->type & xzJSON_IsReference) && (item->valuestring != NULL)) + { + global_hooks.deallocate(item->valuestring); + } + if (!(item->type & xzJSON_StringIsConst) && (item->string != NULL)) + { + global_hooks.deallocate(item->string); + } + global_hooks.deallocate(item); + item = next; + } +} + +/* get the decimal point character of the current locale */ +static unsigned char get_decimal_point(void) +{ +#ifdef ENABLE_LOCALES + struct lconv *lconv = localeconv(); + return (unsigned char) lconv->decimal_point[0]; +#else + return '.'; +#endif +} + +typedef struct +{ + const unsigned char *content; + size_t length; + size_t offset; + size_t depth; /* How deeply nested (in arrays/objects) is the input at the current offset. */ + internal_hooks hooks; +} parse_buffer; + +/* check if the given size is left to read in a given parse buffer (starting with 1) */ +#define can_read(buffer, size) ((buffer != NULL) && (((buffer)->offset + size) <= (buffer)->length)) +/* check if the buffer can be accessed at the given index (starting with 0) */ +#define can_access_at_index(buffer, index) ((buffer != NULL) && (((buffer)->offset + index) < (buffer)->length)) +#define cannot_access_at_index(buffer, index) (!can_access_at_index(buffer, index)) +/* get a pointer to the buffer at the position */ +#define buffer_at_offset(buffer) ((buffer)->content + (buffer)->offset) + +/* Parse the input text to generate a number, and populate the result into item. */ +static xzJSON_bool parse_number(xzJSON * const item, parse_buffer * const input_buffer) +{ + double number = 0; + unsigned char *after_end = NULL; + unsigned char number_c_string[64]; + unsigned char decimal_point = get_decimal_point(); + size_t i = 0; + + if ((input_buffer == NULL) || (input_buffer->content == NULL)) + { + return false; + } + + /* copy the number into a temporary buffer and replace '.' with the decimal point + * of the current locale (for strtod) + * This also takes care of '\0' not necessarily being available for marking the end of the input */ + for (i = 0; (i < (sizeof(number_c_string) - 1)) && can_access_at_index(input_buffer, i); i++) + { + switch (buffer_at_offset(input_buffer)[i]) + { + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case '+': + case '-': + case 'e': + case 'E': + number_c_string[i] = buffer_at_offset(input_buffer)[i]; + break; + + case '.': + number_c_string[i] = decimal_point; + break; + + default: + goto loop_end; + } + } +loop_end: + number_c_string[i] = '\0'; + + number = strtod((const char*)number_c_string, (char**)&after_end); + if (number_c_string == after_end) + { + return false; /* parse_error */ + } + + item->valuedouble = number; + + /* use saturation in case of overflow */ + if (number >= INT_MAX) + { + item->valueint = INT_MAX; + } + else if (number <= (double)INT_MIN) + { + item->valueint = INT_MIN; + } + else + { + item->valueint = (int)number; + } + + item->type = xzJSON_Number; + + input_buffer->offset += (size_t)(after_end - number_c_string); + return true; +} + +/* don't ask me, but the original xzJSON_SetNumberValue returns an integer or double */ +XZJSON_PUBLIC(double) xzJSON_SetNumberHelper(xzJSON *object, double number) +{ + if (number >= INT_MAX) + { + object->valueint = INT_MAX; + } + else if (number <= (double)INT_MIN) + { + object->valueint = INT_MIN; + } + else + { + object->valueint = (int)number; + } + + return object->valuedouble = number; +} + +XZJSON_PUBLIC(char*) xzJSON_SetValuestring(xzJSON *object, const char *valuestring) +{ + char *copy = NULL; + /* if object's type is not xzJSON_String or is xzJSON_IsReference, it should not set valuestring */ + if (!(object->type & xzJSON_String) || (object->type & xzJSON_IsReference)) + { + return NULL; + } + if (strlen(valuestring) <= strlen(object->valuestring)) + { + strcpy(object->valuestring, valuestring); + return object->valuestring; + } + copy = (char*) xzJSON_strdup((const unsigned char*)valuestring, &global_hooks); + if (copy == NULL) + { + return NULL; + } + if (object->valuestring != NULL) + { + xzJSON_free(object->valuestring); + } + object->valuestring = copy; + + return copy; +} + +typedef struct +{ + unsigned char *buffer; + size_t length; + size_t offset; + size_t depth; /* current nesting depth (for formatted printing) */ + xzJSON_bool noalloc; + xzJSON_bool format; /* is this print a formatted print */ + internal_hooks hooks; +} printbuffer; + +/* realloc printbuffer if necessary to have at least "needed" bytes more */ +static unsigned char* ensure(printbuffer * const p, size_t needed) +{ + unsigned char *newbuffer = NULL; + size_t newsize = 0; + + if ((p == NULL) || (p->buffer == NULL)) + { + return NULL; + } + + if ((p->length > 0) && (p->offset >= p->length)) + { + /* make sure that offset is valid */ + return NULL; + } + + if (needed > INT_MAX) + { + /* sizes bigger than INT_MAX are currently not supported */ + return NULL; + } + + needed += p->offset + 1; + if (needed <= p->length) + { + return p->buffer + p->offset; + } + + if (p->noalloc) { + return NULL; + } + + /* calculate new buffer size */ + if (needed > (INT_MAX / 2)) + { + /* overflow of int, use INT_MAX if possible */ + if (needed <= INT_MAX) + { + newsize = INT_MAX; + } + else + { + return NULL; + } + } + else + { + newsize = needed * 2; + } + + if (p->hooks.reallocate != NULL) + { + /* reallocate with realloc if available */ + newbuffer = (unsigned char*)p->hooks.reallocate(p->buffer, newsize); + if (newbuffer == NULL) + { + p->hooks.deallocate(p->buffer); + p->length = 0; + p->buffer = NULL; + + return NULL; + } + } + else + { + /* otherwise reallocate manually */ + newbuffer = (unsigned char*)p->hooks.allocate(newsize); + if (!newbuffer) + { + p->hooks.deallocate(p->buffer); + p->length = 0; + p->buffer = NULL; + + return NULL; + } + + memcpy(newbuffer, p->buffer, p->offset + 1); + p->hooks.deallocate(p->buffer); + } + p->length = newsize; + p->buffer = newbuffer; + + return newbuffer + p->offset; +} + +/* calculate the new length of the string in a printbuffer and update the offset */ +static void update_offset(printbuffer * const buffer) +{ + const unsigned char *buffer_pointer = NULL; + if ((buffer == NULL) || (buffer->buffer == NULL)) + { + return; + } + buffer_pointer = buffer->buffer + buffer->offset; + + buffer->offset += strlen((const char*)buffer_pointer); +} + +/* securely comparison of floating-point variables */ +static xzJSON_bool compare_double(double a, double b) +{ + double maxVal = fabs(a) > fabs(b) ? fabs(a) : fabs(b); + return (fabs(a - b) <= maxVal * DBL_EPSILON); +} + +/* Render the number nicely from the given item into a string. */ +static xzJSON_bool print_number(const xzJSON * const item, printbuffer * const output_buffer) +{ + unsigned char *output_pointer = NULL; + double d = item->valuedouble; + int length = 0; + size_t i = 0; + unsigned char number_buffer[26] = {0}; /* temporary buffer to print the number into */ + unsigned char decimal_point = get_decimal_point(); + double test = 0.0; + + if (output_buffer == NULL) + { + return false; + } + + /* This checks for NaN and Infinity */ + if (isnan(d) || isinf(d)) + { + length = sprintf((char*)number_buffer, "null"); + } + else if(d == (double)item->valueint) + { + length = sprintf((char*)number_buffer, "%d", item->valueint); + } + else + { + /* Try 15 decimal places of precision to avoid nonsignificant nonzero digits */ + length = sprintf((char*)number_buffer, "%1.15g", d); + + /* Check whether the original double can be recovered */ + if ((sscanf((char*)number_buffer, "%lg", &test) != 1) || !compare_double((double)test, d)) + { + /* If not, print with 17 decimal places of precision */ + length = sprintf((char*)number_buffer, "%1.17g", d); + } + } + + /* sprintf failed or buffer overrun occurred */ + if ((length < 0) || (length > (int)(sizeof(number_buffer) - 1))) + { + return false; + } + + /* reserve appropriate space in the output */ + output_pointer = ensure(output_buffer, (size_t)length + sizeof("")); + if (output_pointer == NULL) + { + return false; + } + + /* copy the printed number to the output and replace locale + * dependent decimal point with '.' */ + for (i = 0; i < ((size_t)length); i++) + { + if (number_buffer[i] == decimal_point) + { + output_pointer[i] = '.'; + continue; + } + + output_pointer[i] = number_buffer[i]; + } + output_pointer[i] = '\0'; + + output_buffer->offset += (size_t)length; + + return true; +} + +/* parse 4 digit hexadecimal number */ +static unsigned parse_hex4(const unsigned char * const input) +{ + unsigned int h = 0; + size_t i = 0; + + for (i = 0; i < 4; i++) + { + /* parse digit */ + if ((input[i] >= '0') && (input[i] <= '9')) + { + h += (unsigned int) input[i] - '0'; + } + else if ((input[i] >= 'A') && (input[i] <= 'F')) + { + h += (unsigned int) 10 + input[i] - 'A'; + } + else if ((input[i] >= 'a') && (input[i] <= 'f')) + { + h += (unsigned int) 10 + input[i] - 'a'; + } + else /* invalid */ + { + return 0; + } + + if (i < 3) + { + /* shift left to make place for the next nibble */ + h = h << 4; + } + } + + return h; +} + +/* converts a UTF-16 literal to UTF-8 + * A literal can be one or two sequences of the form \uXXXX */ +static unsigned char utf16_literal_to_utf8(const unsigned char * const input_pointer, const unsigned char * const input_end, unsigned char **output_pointer) +{ + long unsigned int codepoint = 0; + unsigned int first_code = 0; + const unsigned char *first_sequence = input_pointer; + unsigned char utf8_length = 0; + unsigned char utf8_position = 0; + unsigned char sequence_length = 0; + unsigned char first_byte_mark = 0; + + if ((input_end - first_sequence) < 6) + { + /* input ends unexpectedly */ + goto fail; + } + + /* get the first utf16 sequence */ + first_code = parse_hex4(first_sequence + 2); + + /* check that the code is valid */ + if (((first_code >= 0xDC00) && (first_code <= 0xDFFF))) + { + goto fail; + } + + /* UTF16 surrogate pair */ + if ((first_code >= 0xD800) && (first_code <= 0xDBFF)) + { + const unsigned char *second_sequence = first_sequence + 6; + unsigned int second_code = 0; + sequence_length = 12; /* \uXXXX\uXXXX */ + + if ((input_end - second_sequence) < 6) + { + /* input ends unexpectedly */ + goto fail; + } + + if ((second_sequence[0] != '\\') || (second_sequence[1] != 'u')) + { + /* missing second half of the surrogate pair */ + goto fail; + } + + /* get the second utf16 sequence */ + second_code = parse_hex4(second_sequence + 2); + /* check that the code is valid */ + if ((second_code < 0xDC00) || (second_code > 0xDFFF)) + { + /* invalid second half of the surrogate pair */ + goto fail; + } + + + /* calculate the unicode codepoint from the surrogate pair */ + codepoint = 0x10000 + (((first_code & 0x3FF) << 10) | (second_code & 0x3FF)); + } + else + { + sequence_length = 6; /* \uXXXX */ + codepoint = first_code; + } + + /* encode as UTF-8 + * takes at maximum 4 bytes to encode: + * 11110xxx 10xxxxxx 10xxxxxx 10xxxxxx */ + if (codepoint < 0x80) + { + /* normal ascii, encoding 0xxxxxxx */ + utf8_length = 1; + } + else if (codepoint < 0x800) + { + /* two bytes, encoding 110xxxxx 10xxxxxx */ + utf8_length = 2; + first_byte_mark = 0xC0; /* 11000000 */ + } + else if (codepoint < 0x10000) + { + /* three bytes, encoding 1110xxxx 10xxxxxx 10xxxxxx */ + utf8_length = 3; + first_byte_mark = 0xE0; /* 11100000 */ + } + else if (codepoint <= 0x10FFFF) + { + /* four bytes, encoding 1110xxxx 10xxxxxx 10xxxxxx 10xxxxxx */ + utf8_length = 4; + first_byte_mark = 0xF0; /* 11110000 */ + } + else + { + /* invalid unicode codepoint */ + goto fail; + } + + /* encode as utf8 */ + for (utf8_position = (unsigned char)(utf8_length - 1); utf8_position > 0; utf8_position--) + { + /* 10xxxxxx */ + (*output_pointer)[utf8_position] = (unsigned char)((codepoint | 0x80) & 0xBF); + codepoint >>= 6; + } + /* encode first byte */ + if (utf8_length > 1) + { + (*output_pointer)[0] = (unsigned char)((codepoint | first_byte_mark) & 0xFF); + } + else + { + (*output_pointer)[0] = (unsigned char)(codepoint & 0x7F); + } + + *output_pointer += utf8_length; + + return sequence_length; + +fail: + return 0; +} + +/* Parse the input text into an unescaped cinput, and populate item. */ +static xzJSON_bool parse_string(xzJSON * const item, parse_buffer * const input_buffer) +{ + const unsigned char *input_pointer = buffer_at_offset(input_buffer) + 1; + const unsigned char *input_end = buffer_at_offset(input_buffer) + 1; + unsigned char *output_pointer = NULL; + unsigned char *output = NULL; + + /* not a string */ + if (buffer_at_offset(input_buffer)[0] != '\"') + { + goto fail; + } + + { + /* calculate approximate size of the output (overestimate) */ + size_t allocation_length = 0; + size_t skipped_bytes = 0; + while (((size_t)(input_end - input_buffer->content) < input_buffer->length) && (*input_end != '\"')) + { + /* is escape sequence */ + if (input_end[0] == '\\') + { + if ((size_t)(input_end + 1 - input_buffer->content) >= input_buffer->length) + { + /* prevent buffer overflow when last input character is a backslash */ + goto fail; + } + skipped_bytes++; + input_end++; + } + input_end++; + } + if (((size_t)(input_end - input_buffer->content) >= input_buffer->length) || (*input_end != '\"')) + { + goto fail; /* string ended unexpectedly */ + } + + /* This is at most how much we need for the output */ + allocation_length = (size_t) (input_end - buffer_at_offset(input_buffer)) - skipped_bytes; + output = (unsigned char*)input_buffer->hooks.allocate(allocation_length + sizeof("")); + if (output == NULL) + { + goto fail; /* allocation failure */ + } + } + + output_pointer = output; + /* loop through the string literal */ + while (input_pointer < input_end) + { + if (*input_pointer != '\\') + { + *output_pointer++ = *input_pointer++; + } + /* escape sequence */ + else + { + unsigned char sequence_length = 2; + if ((input_end - input_pointer) < 1) + { + goto fail; + } + + switch (input_pointer[1]) + { + case 'b': + *output_pointer++ = '\b'; + break; + case 'f': + *output_pointer++ = '\f'; + break; + case 'n': + *output_pointer++ = '\n'; + break; + case 'r': + *output_pointer++ = '\r'; + break; + case 't': + *output_pointer++ = '\t'; + break; + case '\"': + case '\\': + case '/': + *output_pointer++ = input_pointer[1]; + break; + + /* UTF-16 literal */ + case 'u': + sequence_length = utf16_literal_to_utf8(input_pointer, input_end, &output_pointer); + if (sequence_length == 0) + { + /* failed to convert UTF16-literal to UTF-8 */ + goto fail; + } + break; + + default: + goto fail; + } + input_pointer += sequence_length; + } + } + + /* zero terminate the output */ + *output_pointer = '\0'; + + item->type = xzJSON_String; + item->valuestring = (char*)output; + + input_buffer->offset = (size_t) (input_end - input_buffer->content); + input_buffer->offset++; + + return true; + +fail: + if (output != NULL) + { + input_buffer->hooks.deallocate(output); + } + + if (input_pointer != NULL) + { + input_buffer->offset = (size_t)(input_pointer - input_buffer->content); + } + + return false; +} + +/* Render the cstring provided to an escaped version that can be printed. */ +static xzJSON_bool print_string_ptr(const unsigned char * const input, printbuffer * const output_buffer) +{ + const unsigned char *input_pointer = NULL; + unsigned char *output = NULL; + unsigned char *output_pointer = NULL; + size_t output_length = 0; + /* numbers of additional characters needed for escaping */ + size_t escape_characters = 0; + + if (output_buffer == NULL) + { + return false; + } + + /* empty string */ + if (input == NULL) + { + output = ensure(output_buffer, sizeof("\"\"")); + if (output == NULL) + { + return false; + } + strcpy((char*)output, "\"\""); + + return true; + } + + /* set "flag" to 1 if something needs to be escaped */ + for (input_pointer = input; *input_pointer; input_pointer++) + { + switch (*input_pointer) + { + case '\"': + case '\\': + case '\b': + case '\f': + case '\n': + case '\r': + case '\t': + /* one character escape sequence */ + escape_characters++; + break; + default: + if (*input_pointer < 32) + { + /* UTF-16 escape sequence uXXXX */ + escape_characters += 5; + } + break; + } + } + output_length = (size_t)(input_pointer - input) + escape_characters; + + output = ensure(output_buffer, output_length + sizeof("\"\"")); + if (output == NULL) + { + return false; + } + + /* no characters have to be escaped */ + if (escape_characters == 0) + { + output[0] = '\"'; + memcpy(output + 1, input, output_length); + output[output_length + 1] = '\"'; + output[output_length + 2] = '\0'; + + return true; + } + + output[0] = '\"'; + output_pointer = output + 1; + /* copy the string */ + for (input_pointer = input; *input_pointer != '\0'; (void)input_pointer++, output_pointer++) + { + if ((*input_pointer > 31) && (*input_pointer != '\"') && (*input_pointer != '\\')) + { + /* normal character, copy */ + *output_pointer = *input_pointer; + } + else + { + /* character needs to be escaped */ + *output_pointer++ = '\\'; + switch (*input_pointer) + { + case '\\': + *output_pointer = '\\'; + break; + case '\"': + *output_pointer = '\"'; + break; + case '\b': + *output_pointer = 'b'; + break; + case '\f': + *output_pointer = 'f'; + break; + case '\n': + *output_pointer = 'n'; + break; + case '\r': + *output_pointer = 'r'; + break; + case '\t': + *output_pointer = 't'; + break; + default: + /* escape and print as unicode codepoint */ + sprintf((char*)output_pointer, "u%04x", *input_pointer); + output_pointer += 4; + break; + } + } + } + output[output_length + 1] = '\"'; + output[output_length + 2] = '\0'; + + return true; +} + +/* Invoke print_string_ptr (which is useful) on an item. */ +static xzJSON_bool print_string(const xzJSON * const item, printbuffer * const p) +{ + return print_string_ptr((unsigned char*)item->valuestring, p); +} + +/* Predeclare these prototypes. */ +static xzJSON_bool parse_value(xzJSON * const item, parse_buffer * const input_buffer); +static xzJSON_bool print_value(const xzJSON * const item, printbuffer * const output_buffer); +static xzJSON_bool parse_array(xzJSON * const item, parse_buffer * const input_buffer); +static xzJSON_bool print_array(const xzJSON * const item, printbuffer * const output_buffer); +static xzJSON_bool parse_object(xzJSON * const item, parse_buffer * const input_buffer); +static xzJSON_bool print_object(const xzJSON * const item, printbuffer * const output_buffer); + +/* Utility to jump whitespace and cr/lf */ +static parse_buffer *buffer_skip_whitespace(parse_buffer * const buffer) +{ + if ((buffer == NULL) || (buffer->content == NULL)) + { + return NULL; + } + + if (cannot_access_at_index(buffer, 0)) + { + return buffer; + } + + while (can_access_at_index(buffer, 0) && (buffer_at_offset(buffer)[0] <= 32)) + { + buffer->offset++; + } + + if (buffer->offset == buffer->length) + { + buffer->offset--; + } + + return buffer; +} + +/* skip the UTF-8 BOM (byte order mark) if it is at the beginning of a buffer */ +static parse_buffer *skip_utf8_bom(parse_buffer * const buffer) +{ + if ((buffer == NULL) || (buffer->content == NULL) || (buffer->offset != 0)) + { + return NULL; + } + + if (can_access_at_index(buffer, 4) && (strncmp((const char*)buffer_at_offset(buffer), "\xEF\xBB\xBF", 3) == 0)) + { + buffer->offset += 3; + } + + return buffer; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_ParseWithOpts(const char *value, const char **return_parse_end, xzJSON_bool require_null_terminated) +{ + size_t buffer_length; + + if (NULL == value) + { + return NULL; + } + + /* Adding null character size due to require_null_terminated. */ + buffer_length = strlen(value) + sizeof(""); + + return xzJSON_ParseWithLengthOpts(value, buffer_length, return_parse_end, require_null_terminated); +} + +/* Parse an object - create a new root, and populate. */ +XZJSON_PUBLIC(xzJSON *) xzJSON_ParseWithLengthOpts(const char *value, size_t buffer_length, const char **return_parse_end, xzJSON_bool require_null_terminated) +{ + parse_buffer buffer = { 0, 0, 0, 0, { 0, 0, 0 } }; + xzJSON *item = NULL; + + /* reset error position */ + global_error.json = NULL; + global_error.position = 0; + + if (value == NULL || 0 == buffer_length) + { + goto fail; + } + + buffer.content = (const unsigned char*)value; + buffer.length = buffer_length; + buffer.offset = 0; + buffer.hooks = global_hooks; + + item = xzJSON_New_Item(&global_hooks); + if (item == NULL) /* memory fail */ + { + goto fail; + } + + if (!parse_value(item, buffer_skip_whitespace(skip_utf8_bom(&buffer)))) + { + /* parse failure. ep is set. */ + goto fail; + } + + /* if we require null-terminated JSON without appended garbage, skip and then check for a null terminator */ + if (require_null_terminated) + { + buffer_skip_whitespace(&buffer); + if ((buffer.offset >= buffer.length) || buffer_at_offset(&buffer)[0] != '\0') + { + goto fail; + } + } + if (return_parse_end) + { + *return_parse_end = (const char*)buffer_at_offset(&buffer); + } + + return item; + +fail: + if (item != NULL) + { + xzJSON_Delete(item); + } + + if (value != NULL) + { + error local_error; + local_error.json = (const unsigned char*)value; + local_error.position = 0; + + if (buffer.offset < buffer.length) + { + local_error.position = buffer.offset; + } + else if (buffer.length > 0) + { + local_error.position = buffer.length - 1; + } + + if (return_parse_end != NULL) + { + *return_parse_end = (const char*)local_error.json + local_error.position; + } + + global_error = local_error; + } + + return NULL; +} + +/* Default options for xzJSON_Parse */ +XZJSON_PUBLIC(xzJSON *) xzJSON_Parse(const char *value) +{ + return xzJSON_ParseWithOpts(value, 0, 0); +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_ParseWithLength(const char *value, size_t buffer_length) +{ + return xzJSON_ParseWithLengthOpts(value, buffer_length, 0, 0); +} + +#define cjson_min(a, b) (((a) < (b)) ? (a) : (b)) + +static unsigned char *print(const xzJSON * const item, xzJSON_bool format, const internal_hooks * const hooks) +{ + static const size_t default_buffer_size = 256; + printbuffer buffer[1]; + unsigned char *printed = NULL; + + memset(buffer, 0, sizeof(buffer)); + + /* create buffer */ + buffer->buffer = (unsigned char*) hooks->allocate(default_buffer_size); + buffer->length = default_buffer_size; + buffer->format = format; + buffer->hooks = *hooks; + if (buffer->buffer == NULL) + { + goto fail; + } + + /* print the value */ + if (!print_value(item, buffer)) + { + goto fail; + } + update_offset(buffer); + + /* check if reallocate is available */ + if (hooks->reallocate != NULL) + { + printed = (unsigned char*) hooks->reallocate(buffer->buffer, buffer->offset + 1); + if (printed == NULL) { + goto fail; + } + buffer->buffer = NULL; + } + else /* otherwise copy the JSON over to a new buffer */ + { + printed = (unsigned char*) hooks->allocate(buffer->offset + 1); + if (printed == NULL) + { + goto fail; + } + memcpy(printed, buffer->buffer, cjson_min(buffer->length, buffer->offset + 1)); + printed[buffer->offset] = '\0'; /* just to be sure */ + + /* free the buffer */ + hooks->deallocate(buffer->buffer); + } + + return printed; + +fail: + if (buffer->buffer != NULL) + { + hooks->deallocate(buffer->buffer); + } + + if (printed != NULL) + { + hooks->deallocate(printed); + } + + return NULL; +} + +/* Render a xzJSON item/entity/structure to text. */ +XZJSON_PUBLIC(char *) xzJSON_Print(const xzJSON *item) +{ + return (char*)print(item, true, &global_hooks); +} + +XZJSON_PUBLIC(char *) xzJSON_PrintUnformatted(const xzJSON *item) +{ + return (char*)print(item, false, &global_hooks); +} + +XZJSON_PUBLIC(char *) xzJSON_PrintBuffered(const xzJSON *item, int prebuffer, xzJSON_bool fmt) +{ + printbuffer p = { 0, 0, 0, 0, 0, 0, { 0, 0, 0 } }; + + if (prebuffer < 0) + { + return NULL; + } + + p.buffer = (unsigned char*)global_hooks.allocate((size_t)prebuffer); + if (!p.buffer) + { + return NULL; + } + + p.length = (size_t)prebuffer; + p.offset = 0; + p.noalloc = false; + p.format = fmt; + p.hooks = global_hooks; + + if (!print_value(item, &p)) + { + global_hooks.deallocate(p.buffer); + return NULL; + } + + return (char*)p.buffer; +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_PrintPreallocated(xzJSON *item, char *buffer, const int length, const xzJSON_bool format) +{ + printbuffer p = { 0, 0, 0, 0, 0, 0, { 0, 0, 0 } }; + + if ((length < 0) || (buffer == NULL)) + { + return false; + } + + p.buffer = (unsigned char*)buffer; + p.length = (size_t)length; + p.offset = 0; + p.noalloc = true; + p.format = format; + p.hooks = global_hooks; + + return print_value(item, &p); +} + +/* Parser core - when encountering text, process appropriately. */ +static xzJSON_bool parse_value(xzJSON * const item, parse_buffer * const input_buffer) +{ + if ((input_buffer == NULL) || (input_buffer->content == NULL)) + { + return false; /* no input */ + } + + /* parse the different types of values */ + /* null */ + if (can_read(input_buffer, 4) && (strncmp((const char*)buffer_at_offset(input_buffer), "null", 4) == 0)) + { + item->type = xzJSON_NULL; + input_buffer->offset += 4; + return true; + } + /* false */ + if (can_read(input_buffer, 5) && (strncmp((const char*)buffer_at_offset(input_buffer), "false", 5) == 0)) + { + item->type = xzJSON_False; + input_buffer->offset += 5; + return true; + } + /* true */ + if (can_read(input_buffer, 4) && (strncmp((const char*)buffer_at_offset(input_buffer), "true", 4) == 0)) + { + item->type = xzJSON_True; + item->valueint = 1; + input_buffer->offset += 4; + return true; + } + /* string */ + if (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == '\"')) + { + return parse_string(item, input_buffer); + } + /* number */ + if (can_access_at_index(input_buffer, 0) && ((buffer_at_offset(input_buffer)[0] == '-') || ((buffer_at_offset(input_buffer)[0] >= '0') && (buffer_at_offset(input_buffer)[0] <= '9')))) + { + return parse_number(item, input_buffer); + } + /* array */ + if (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == '[')) + { + return parse_array(item, input_buffer); + } + /* object */ + if (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == '{')) + { + return parse_object(item, input_buffer); + } + + return false; +} + +/* Render a value to text. */ +static xzJSON_bool print_value(const xzJSON * const item, printbuffer * const output_buffer) +{ + unsigned char *output = NULL; + + if ((item == NULL) || (output_buffer == NULL)) + { + return false; + } + + switch ((item->type) & 0xFF) + { + case xzJSON_NULL: + output = ensure(output_buffer, 5); + if (output == NULL) + { + return false; + } + strcpy((char*)output, "null"); + return true; + + case xzJSON_False: + output = ensure(output_buffer, 6); + if (output == NULL) + { + return false; + } + strcpy((char*)output, "false"); + return true; + + case xzJSON_True: + output = ensure(output_buffer, 5); + if (output == NULL) + { + return false; + } + strcpy((char*)output, "true"); + return true; + + case xzJSON_Number: + return print_number(item, output_buffer); + + case xzJSON_Raw: + { + size_t raw_length = 0; + if (item->valuestring == NULL) + { + return false; + } + + raw_length = strlen(item->valuestring) + sizeof(""); + output = ensure(output_buffer, raw_length); + if (output == NULL) + { + return false; + } + memcpy(output, item->valuestring, raw_length); + return true; + } + + case xzJSON_String: + return print_string(item, output_buffer); + + case xzJSON_Array: + return print_array(item, output_buffer); + + case xzJSON_Object: + return print_object(item, output_buffer); + + default: + return false; + } +} + +/* Build an array from input text. */ +static xzJSON_bool parse_array(xzJSON * const item, parse_buffer * const input_buffer) +{ + xzJSON *head = NULL; /* head of the linked list */ + xzJSON *current_item = NULL; + + if (input_buffer->depth >= CJSON_NESTING_LIMIT) + { + return false; /* to deeply nested */ + } + input_buffer->depth++; + + if (buffer_at_offset(input_buffer)[0] != '[') + { + /* not an array */ + goto fail; + } + + input_buffer->offset++; + buffer_skip_whitespace(input_buffer); + if (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == ']')) + { + /* empty array */ + goto success; + } + + /* check if we skipped to the end of the buffer */ + if (cannot_access_at_index(input_buffer, 0)) + { + input_buffer->offset--; + goto fail; + } + + /* step back to character in front of the first element */ + input_buffer->offset--; + /* loop through the comma separated array elements */ + do + { + /* allocate next item */ + xzJSON *new_item = xzJSON_New_Item(&(input_buffer->hooks)); + if (new_item == NULL) + { + goto fail; /* allocation failure */ + } + + /* attach next item to list */ + if (head == NULL) + { + /* start the linked list */ + current_item = head = new_item; + } + else + { + /* add to the end and advance */ + current_item->next = new_item; + new_item->prev = current_item; + current_item = new_item; + } + + /* parse next value */ + input_buffer->offset++; + buffer_skip_whitespace(input_buffer); + if (!parse_value(current_item, input_buffer)) + { + goto fail; /* failed to parse value */ + } + buffer_skip_whitespace(input_buffer); + } + while (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == ',')); + + if (cannot_access_at_index(input_buffer, 0) || buffer_at_offset(input_buffer)[0] != ']') + { + goto fail; /* expected end of array */ + } + +success: + input_buffer->depth--; + + if (head != NULL) { + head->prev = current_item; + } + + item->type = xzJSON_Array; + item->child = head; + + input_buffer->offset++; + + return true; + +fail: + if (head != NULL) + { + xzJSON_Delete(head); + } + + return false; +} + +/* Render an array to text */ +static xzJSON_bool print_array(const xzJSON * const item, printbuffer * const output_buffer) +{ + unsigned char *output_pointer = NULL; + size_t length = 0; + xzJSON *current_element = item->child; + + if (output_buffer == NULL) + { + return false; + } + + /* Compose the output array. */ + /* opening square bracket */ + output_pointer = ensure(output_buffer, 1); + if (output_pointer == NULL) + { + return false; + } + + *output_pointer = '['; + output_buffer->offset++; + output_buffer->depth++; + + while (current_element != NULL) + { + if (!print_value(current_element, output_buffer)) + { + return false; + } + update_offset(output_buffer); + if (current_element->next) + { + length = (size_t) (output_buffer->format ? 2 : 1); + output_pointer = ensure(output_buffer, length + 1); + if (output_pointer == NULL) + { + return false; + } + *output_pointer++ = ','; + if(output_buffer->format) + { + *output_pointer++ = ' '; + } + *output_pointer = '\0'; + output_buffer->offset += length; + } + current_element = current_element->next; + } + + output_pointer = ensure(output_buffer, 2); + if (output_pointer == NULL) + { + return false; + } + *output_pointer++ = ']'; + *output_pointer = '\0'; + output_buffer->depth--; + + return true; +} + +/* Build an object from the text. */ +static xzJSON_bool parse_object(xzJSON * const item, parse_buffer * const input_buffer) +{ + xzJSON *head = NULL; /* linked list head */ + xzJSON *current_item = NULL; + + if (input_buffer->depth >= CJSON_NESTING_LIMIT) + { + return false; /* to deeply nested */ + } + input_buffer->depth++; + + if (cannot_access_at_index(input_buffer, 0) || (buffer_at_offset(input_buffer)[0] != '{')) + { + goto fail; /* not an object */ + } + + input_buffer->offset++; + buffer_skip_whitespace(input_buffer); + if (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == '}')) + { + goto success; /* empty object */ + } + + /* check if we skipped to the end of the buffer */ + if (cannot_access_at_index(input_buffer, 0)) + { + input_buffer->offset--; + goto fail; + } + + /* step back to character in front of the first element */ + input_buffer->offset--; + /* loop through the comma separated array elements */ + do + { + /* allocate next item */ + xzJSON *new_item = xzJSON_New_Item(&(input_buffer->hooks)); + if (new_item == NULL) + { + goto fail; /* allocation failure */ + } + + /* attach next item to list */ + if (head == NULL) + { + /* start the linked list */ + current_item = head = new_item; + } + else + { + /* add to the end and advance */ + current_item->next = new_item; + new_item->prev = current_item; + current_item = new_item; + } + + /* parse the name of the child */ + input_buffer->offset++; + buffer_skip_whitespace(input_buffer); + if (!parse_string(current_item, input_buffer)) + { + goto fail; /* failed to parse name */ + } + buffer_skip_whitespace(input_buffer); + + /* swap valuestring and string, because we parsed the name */ + current_item->string = current_item->valuestring; + current_item->valuestring = NULL; + + if (cannot_access_at_index(input_buffer, 0) || (buffer_at_offset(input_buffer)[0] != ':')) + { + goto fail; /* invalid object */ + } + + /* parse the value */ + input_buffer->offset++; + buffer_skip_whitespace(input_buffer); + if (!parse_value(current_item, input_buffer)) + { + goto fail; /* failed to parse value */ + } + buffer_skip_whitespace(input_buffer); + } + while (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == ',')); + + if (cannot_access_at_index(input_buffer, 0) || (buffer_at_offset(input_buffer)[0] != '}')) + { + goto fail; /* expected end of object */ + } + +success: + input_buffer->depth--; + + if (head != NULL) { + head->prev = current_item; + } + + item->type = xzJSON_Object; + item->child = head; + + input_buffer->offset++; + return true; + +fail: + if (head != NULL) + { + xzJSON_Delete(head); + } + + return false; +} + +/* Render an object to text. */ +static xzJSON_bool print_object(const xzJSON * const item, printbuffer * const output_buffer) +{ + unsigned char *output_pointer = NULL; + size_t length = 0; + xzJSON *current_item = item->child; + + if (output_buffer == NULL) + { + return false; + } + + /* Compose the output: */ + length = (size_t) (output_buffer->format ? 2 : 1); /* fmt: {\n */ + output_pointer = ensure(output_buffer, length + 1); + if (output_pointer == NULL) + { + return false; + } + + *output_pointer++ = '{'; + output_buffer->depth++; + if (output_buffer->format) + { + *output_pointer++ = '\n'; + } + output_buffer->offset += length; + + while (current_item) + { + if (output_buffer->format) + { + size_t i; + output_pointer = ensure(output_buffer, output_buffer->depth); + if (output_pointer == NULL) + { + return false; + } + for (i = 0; i < output_buffer->depth; i++) + { + *output_pointer++ = '\t'; + } + output_buffer->offset += output_buffer->depth; + } + + /* print key */ + if (!print_string_ptr((unsigned char*)current_item->string, output_buffer)) + { + return false; + } + update_offset(output_buffer); + + length = (size_t) (output_buffer->format ? 2 : 1); + output_pointer = ensure(output_buffer, length); + if (output_pointer == NULL) + { + return false; + } + *output_pointer++ = ':'; + if (output_buffer->format) + { + *output_pointer++ = '\t'; + } + output_buffer->offset += length; + + /* print value */ + if (!print_value(current_item, output_buffer)) + { + return false; + } + update_offset(output_buffer); + + /* print comma if not last */ + length = ((size_t)(output_buffer->format ? 1 : 0) + (size_t)(current_item->next ? 1 : 0)); + output_pointer = ensure(output_buffer, length + 1); + if (output_pointer == NULL) + { + return false; + } + if (current_item->next) + { + *output_pointer++ = ','; + } + + if (output_buffer->format) + { + *output_pointer++ = '\n'; + } + *output_pointer = '\0'; + output_buffer->offset += length; + + current_item = current_item->next; + } + + output_pointer = ensure(output_buffer, output_buffer->format ? (output_buffer->depth + 1) : 2); + if (output_pointer == NULL) + { + return false; + } + if (output_buffer->format) + { + size_t i; + for (i = 0; i < (output_buffer->depth - 1); i++) + { + *output_pointer++ = '\t'; + } + } + *output_pointer++ = '}'; + *output_pointer = '\0'; + output_buffer->depth--; + + return true; +} + +/* Get Array size/item / object item. */ +XZJSON_PUBLIC(int) xzJSON_GetArraySize(const xzJSON *array) +{ + xzJSON *child = NULL; + size_t size = 0; + + if (array == NULL) + { + return 0; + } + + child = array->child; + + while(child != NULL) + { + size++; + child = child->next; + } + + /* FIXME: Can overflow here. Cannot be fixed without breaking the API */ + + return (int)size; +} + +static xzJSON* get_array_item(const xzJSON *array, size_t index) +{ + xzJSON *current_child = NULL; + + if (array == NULL) + { + return NULL; + } + + current_child = array->child; + while ((current_child != NULL) && (index > 0)) + { + index--; + current_child = current_child->next; + } + + return current_child; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_GetArrayItem(const xzJSON *array, int index) +{ + if (index < 0) + { + return NULL; + } + + return get_array_item(array, (size_t)index); +} + +static xzJSON *get_object_item(const xzJSON * const object, const char * const name, const xzJSON_bool case_sensitive) +{ + xzJSON *current_element = NULL; + + if ((object == NULL) || (name == NULL)) + { + return NULL; + } + + current_element = object->child; + if (case_sensitive) + { + while ((current_element != NULL) && (current_element->string != NULL) && (strcmp(name, current_element->string) != 0)) + { + current_element = current_element->next; + } + } + else + { + while ((current_element != NULL) && (case_insensitive_strcmp((const unsigned char*)name, (const unsigned char*)(current_element->string)) != 0)) + { + current_element = current_element->next; + } + } + + if ((current_element == NULL) || (current_element->string == NULL)) { + return NULL; + } + + return current_element; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_GetObjectItem(const xzJSON * const object, const char * const string) +{ + return get_object_item(object, string, false); +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_GetObjectItemCaseSensitive(const xzJSON * const object, const char * const string) +{ + return get_object_item(object, string, true); +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_HasObjectItem(const xzJSON *object, const char *string) +{ + return xzJSON_GetObjectItem(object, string) ? 1 : 0; +} + +/* Utility for array list handling. */ +static void suffix_object(xzJSON *prev, xzJSON *item) +{ + prev->next = item; + item->prev = prev; +} + +/* Utility for handling references. */ +static xzJSON *create_reference(const xzJSON *item, const internal_hooks * const hooks) +{ + xzJSON *reference = NULL; + if (item == NULL) + { + return NULL; + } + + reference = xzJSON_New_Item(hooks); + if (reference == NULL) + { + return NULL; + } + + memcpy(reference, item, sizeof(xzJSON)); + reference->string = NULL; + reference->type |= xzJSON_IsReference; + reference->next = reference->prev = NULL; + return reference; +} + +static xzJSON_bool add_item_to_array(xzJSON *array, xzJSON *item) +{ + xzJSON *child = NULL; + + if ((item == NULL) || (array == NULL) || (array == item)) + { + return false; + } + + child = array->child; + /* + * To find the last item in array quickly, we use prev in array + */ + if (child == NULL) + { + /* list is empty, start new one */ + array->child = item; + item->prev = item; + item->next = NULL; + } + else + { + /* append to the end */ + if (child->prev) + { + suffix_object(child->prev, item); + array->child->prev = item; + } + } + + return true; +} + +/* Add item to array/object. */ +XZJSON_PUBLIC(xzJSON_bool) xzJSON_AddItemToArray(xzJSON *array, xzJSON *item) +{ + return add_item_to_array(array, item); +} + +#if defined(__clang__) || (defined(__GNUC__) && ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ > 5)))) + #pragma GCC diagnostic push +#endif +#ifdef __GNUC__ +#pragma GCC diagnostic ignored "-Wcast-qual" +#endif +/* helper function to cast away const */ +static void* cast_away_const(const void* string) +{ + return (void*)string; +} +#if defined(__clang__) || (defined(__GNUC__) && ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ > 5)))) + #pragma GCC diagnostic pop +#endif + + +static xzJSON_bool add_item_to_object(xzJSON * const object, const char * const string, xzJSON * const item, const internal_hooks * const hooks, const xzJSON_bool constant_key) +{ + char *new_key = NULL; + int new_type = xzJSON_Invalid; + + if ((object == NULL) || (string == NULL) || (item == NULL) || (object == item)) + { + return false; + } + + if (constant_key) + { + new_key = (char*)cast_away_const(string); + new_type = item->type | xzJSON_StringIsConst; + } + else + { + new_key = (char*)xzJSON_strdup((const unsigned char*)string, hooks); + if (new_key == NULL) + { + return false; + } + + new_type = item->type & ~xzJSON_StringIsConst; + } + + if (!(item->type & xzJSON_StringIsConst) && (item->string != NULL)) + { + hooks->deallocate(item->string); + } + + item->string = new_key; + item->type = new_type; + + return add_item_to_array(object, item); +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_AddItemToObject(xzJSON *object, const char *string, xzJSON *item) +{ + return add_item_to_object(object, string, item, &global_hooks, false); +} + +/* Add an item to an object with constant string as key */ +XZJSON_PUBLIC(xzJSON_bool) xzJSON_AddItemToObjectCS(xzJSON *object, const char *string, xzJSON *item) +{ + return add_item_to_object(object, string, item, &global_hooks, true); +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_AddItemReferenceToArray(xzJSON *array, xzJSON *item) +{ + if (array == NULL) + { + return false; + } + + return add_item_to_array(array, create_reference(item, &global_hooks)); +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_AddItemReferenceToObject(xzJSON *object, const char *string, xzJSON *item) +{ + if ((object == NULL) || (string == NULL)) + { + return false; + } + + return add_item_to_object(object, string, create_reference(item, &global_hooks), &global_hooks, false); +} + +XZJSON_PUBLIC(xzJSON*) xzJSON_AddNullToObject(xzJSON * const object, const char * const name) +{ + xzJSON *null = xzJSON_CreateNull(); + if (add_item_to_object(object, name, null, &global_hooks, false)) + { + return null; + } + + xzJSON_Delete(null); + return NULL; +} + +XZJSON_PUBLIC(xzJSON*) xzJSON_AddTrueToObject(xzJSON * const object, const char * const name) +{ + xzJSON *true_item = xzJSON_CreateTrue(); + if (add_item_to_object(object, name, true_item, &global_hooks, false)) + { + return true_item; + } + + xzJSON_Delete(true_item); + return NULL; +} + +XZJSON_PUBLIC(xzJSON*) xzJSON_AddFalseToObject(xzJSON * const object, const char * const name) +{ + xzJSON *false_item = xzJSON_CreateFalse(); + if (add_item_to_object(object, name, false_item, &global_hooks, false)) + { + return false_item; + } + + xzJSON_Delete(false_item); + return NULL; +} + +XZJSON_PUBLIC(xzJSON*) xzJSON_AddBoolToObject(xzJSON * const object, const char * const name, const xzJSON_bool boolean) +{ + xzJSON *bool_item = xzJSON_CreateBool(boolean); + if (add_item_to_object(object, name, bool_item, &global_hooks, false)) + { + return bool_item; + } + + xzJSON_Delete(bool_item); + return NULL; +} + +XZJSON_PUBLIC(xzJSON*) xzJSON_AddNumberToObject(xzJSON * const object, const char * const name, const double number) +{ + xzJSON *number_item = xzJSON_CreateNumber(number); + if (add_item_to_object(object, name, number_item, &global_hooks, false)) + { + return number_item; + } + + xzJSON_Delete(number_item); + return NULL; +} + +XZJSON_PUBLIC(xzJSON*) xzJSON_AddStringToObject(xzJSON * const object, const char * const name, const char * const string) +{ + xzJSON *string_item = xzJSON_CreateString(string); + if (add_item_to_object(object, name, string_item, &global_hooks, false)) + { + return string_item; + } + + xzJSON_Delete(string_item); + return NULL; +} + +XZJSON_PUBLIC(xzJSON*) xzJSON_AddRawToObject(xzJSON * const object, const char * const name, const char * const raw) +{ + xzJSON *raw_item = xzJSON_CreateRaw(raw); + if (add_item_to_object(object, name, raw_item, &global_hooks, false)) + { + return raw_item; + } + + xzJSON_Delete(raw_item); + return NULL; +} + +XZJSON_PUBLIC(xzJSON*) xzJSON_AddObjectToObject(xzJSON * const object, const char * const name) +{ + xzJSON *object_item = xzJSON_CreateObject(); + if (add_item_to_object(object, name, object_item, &global_hooks, false)) + { + return object_item; + } + + xzJSON_Delete(object_item); + return NULL; +} + +XZJSON_PUBLIC(xzJSON*) xzJSON_AddArrayToObject(xzJSON * const object, const char * const name) +{ + xzJSON *array = xzJSON_CreateArray(); + if (add_item_to_object(object, name, array, &global_hooks, false)) + { + return array; + } + + xzJSON_Delete(array); + return NULL; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_DetachItemViaPointer(xzJSON *parent, xzJSON * const item) +{ + if ((parent == NULL) || (item == NULL)) + { + return NULL; + } + + if (item != parent->child) + { + /* not the first element */ + item->prev->next = item->next; + } + if (item->next != NULL) + { + /* not the last element */ + item->next->prev = item->prev; + } + + if (item == parent->child) + { + /* first element */ + parent->child = item->next; + } + else if (item->next == NULL) + { + /* last element */ + parent->child->prev = item->prev; + } + + /* make sure the detached item doesn't point anywhere anymore */ + item->prev = NULL; + item->next = NULL; + + return item; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_DetachItemFromArray(xzJSON *array, int which) +{ + if (which < 0) + { + return NULL; + } + + return xzJSON_DetachItemViaPointer(array, get_array_item(array, (size_t)which)); +} + +XZJSON_PUBLIC(void) xzJSON_DeleteItemFromArray(xzJSON *array, int which) +{ + xzJSON_Delete(xzJSON_DetachItemFromArray(array, which)); +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_DetachItemFromObject(xzJSON *object, const char *string) +{ + xzJSON *to_detach = xzJSON_GetObjectItem(object, string); + + return xzJSON_DetachItemViaPointer(object, to_detach); +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_DetachItemFromObjectCaseSensitive(xzJSON *object, const char *string) +{ + xzJSON *to_detach = xzJSON_GetObjectItemCaseSensitive(object, string); + + return xzJSON_DetachItemViaPointer(object, to_detach); +} + +XZJSON_PUBLIC(void) xzJSON_DeleteItemFromObject(xzJSON *object, const char *string) +{ + xzJSON_Delete(xzJSON_DetachItemFromObject(object, string)); +} + +XZJSON_PUBLIC(void) xzJSON_DeleteItemFromObjectCaseSensitive(xzJSON *object, const char *string) +{ + xzJSON_Delete(xzJSON_DetachItemFromObjectCaseSensitive(object, string)); +} + +/* Replace array/object items with new ones. */ +XZJSON_PUBLIC(xzJSON_bool) xzJSON_InsertItemInArray(xzJSON *array, int which, xzJSON *newitem) +{ + xzJSON *after_inserted = NULL; + + if (which < 0) + { + return false; + } + + after_inserted = get_array_item(array, (size_t)which); + if (after_inserted == NULL) + { + return add_item_to_array(array, newitem); + } + + newitem->next = after_inserted; + newitem->prev = after_inserted->prev; + after_inserted->prev = newitem; + if (after_inserted == array->child) + { + array->child = newitem; + } + else + { + newitem->prev->next = newitem; + } + return true; +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_ReplaceItemViaPointer(xzJSON * const parent, xzJSON * const item, xzJSON * replacement) +{ + if ((parent == NULL) || (parent->child == NULL) || (replacement == NULL) || (item == NULL)) + { + return false; + } + + if (replacement == item) + { + return true; + } + + replacement->next = item->next; + replacement->prev = item->prev; + + if (replacement->next != NULL) + { + replacement->next->prev = replacement; + } + if (parent->child == item) + { + if (parent->child->prev == parent->child) + { + replacement->prev = replacement; + } + parent->child = replacement; + } + else + { /* + * To find the last item in array quickly, we use prev in array. + * We can't modify the last item's next pointer where this item was the parent's child + */ + if (replacement->prev != NULL) + { + replacement->prev->next = replacement; + } + if (replacement->next == NULL) + { + parent->child->prev = replacement; + } + } + + item->next = NULL; + item->prev = NULL; + xzJSON_Delete(item); + + return true; +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_ReplaceItemInArray(xzJSON *array, int which, xzJSON *newitem) +{ + if (which < 0) + { + return false; + } + + return xzJSON_ReplaceItemViaPointer(array, get_array_item(array, (size_t)which), newitem); +} + +static xzJSON_bool replace_item_in_object(xzJSON *object, const char *string, xzJSON *replacement, xzJSON_bool case_sensitive) +{ + if ((replacement == NULL) || (string == NULL)) + { + return false; + } + + /* replace the name in the replacement */ + if (!(replacement->type & xzJSON_StringIsConst) && (replacement->string != NULL)) + { + xzJSON_free(replacement->string); + } + replacement->string = (char*)xzJSON_strdup((const unsigned char*)string, &global_hooks); + if (replacement->string == NULL) + { + return false; + } + + replacement->type &= ~xzJSON_StringIsConst; + + return xzJSON_ReplaceItemViaPointer(object, get_object_item(object, string, case_sensitive), replacement); +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_ReplaceItemInObject(xzJSON *object, const char *string, xzJSON *newitem) +{ + return replace_item_in_object(object, string, newitem, false); +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_ReplaceItemInObjectCaseSensitive(xzJSON *object, const char *string, xzJSON *newitem) +{ + return replace_item_in_object(object, string, newitem, true); +} + +/* Create basic types: */ +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateNull(void) +{ + xzJSON *item = xzJSON_New_Item(&global_hooks); + if(item) + { + item->type = xzJSON_NULL; + } + + return item; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateTrue(void) +{ + xzJSON *item = xzJSON_New_Item(&global_hooks); + if(item) + { + item->type = xzJSON_True; + } + + return item; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateFalse(void) +{ + xzJSON *item = xzJSON_New_Item(&global_hooks); + if(item) + { + item->type = xzJSON_False; + } + + return item; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateBool(xzJSON_bool boolean) +{ + xzJSON *item = xzJSON_New_Item(&global_hooks); + if(item) + { + item->type = boolean ? xzJSON_True : xzJSON_False; + } + + return item; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateNumber(double num) +{ + xzJSON *item = xzJSON_New_Item(&global_hooks); + if(item) + { + item->type = xzJSON_Number; + item->valuedouble = num; + + /* use saturation in case of overflow */ + if (num >= INT_MAX) + { + item->valueint = INT_MAX; + } + else if (num <= (double)INT_MIN) + { + item->valueint = INT_MIN; + } + else + { + item->valueint = (int)num; + } + } + + return item; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateString(const char *string) +{ + xzJSON *item = xzJSON_New_Item(&global_hooks); + if(item) + { + item->type = xzJSON_String; + item->valuestring = (char*)xzJSON_strdup((const unsigned char*)string, &global_hooks); + if(!item->valuestring) + { + xzJSON_Delete(item); + return NULL; + } + } + + return item; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateStringReference(const char *string) +{ + xzJSON *item = xzJSON_New_Item(&global_hooks); + if (item != NULL) + { + item->type = xzJSON_String | xzJSON_IsReference; + item->valuestring = (char*)cast_away_const(string); + } + + return item; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateObjectReference(const xzJSON *child) +{ + xzJSON *item = xzJSON_New_Item(&global_hooks); + if (item != NULL) { + item->type = xzJSON_Object | xzJSON_IsReference; + item->child = (xzJSON*)cast_away_const(child); + } + + return item; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateArrayReference(const xzJSON *child) { + xzJSON *item = xzJSON_New_Item(&global_hooks); + if (item != NULL) { + item->type = xzJSON_Array | xzJSON_IsReference; + item->child = (xzJSON*)cast_away_const(child); + } + + return item; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateRaw(const char *raw) +{ + xzJSON *item = xzJSON_New_Item(&global_hooks); + if(item) + { + item->type = xzJSON_Raw; + item->valuestring = (char*)xzJSON_strdup((const unsigned char*)raw, &global_hooks); + if(!item->valuestring) + { + xzJSON_Delete(item); + return NULL; + } + } + + return item; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateArray(void) +{ + xzJSON *item = xzJSON_New_Item(&global_hooks); + if(item) + { + item->type=xzJSON_Array; + } + + return item; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateObject(void) +{ + xzJSON *item = xzJSON_New_Item(&global_hooks); + if (item) + { + item->type = xzJSON_Object; + } + + return item; +} + +/* Create Arrays: */ +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateIntArray(const int *numbers, int count) +{ + size_t i = 0; + xzJSON *n = NULL; + xzJSON *p = NULL; + xzJSON *a = NULL; + + if ((count < 0) || (numbers == NULL)) + { + return NULL; + } + + a = xzJSON_CreateArray(); + + for(i = 0; a && (i < (size_t)count); i++) + { + n = xzJSON_CreateNumber(numbers[i]); + if (!n) + { + xzJSON_Delete(a); + return NULL; + } + if(!i) + { + a->child = n; + } + else + { + suffix_object(p, n); + } + p = n; + } + + if (a && a->child) { + a->child->prev = n; + } + + return a; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateFloatArray(const float *numbers, int count) +{ + size_t i = 0; + xzJSON *n = NULL; + xzJSON *p = NULL; + xzJSON *a = NULL; + + if ((count < 0) || (numbers == NULL)) + { + return NULL; + } + + a = xzJSON_CreateArray(); + + for(i = 0; a && (i < (size_t)count); i++) + { + n = xzJSON_CreateNumber((double)numbers[i]); + if(!n) + { + xzJSON_Delete(a); + return NULL; + } + if(!i) + { + a->child = n; + } + else + { + suffix_object(p, n); + } + p = n; + } + + if (a && a->child) { + a->child->prev = n; + } + + return a; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateDoubleArray(const double *numbers, int count) +{ + size_t i = 0; + xzJSON *n = NULL; + xzJSON *p = NULL; + xzJSON *a = NULL; + + if ((count < 0) || (numbers == NULL)) + { + return NULL; + } + + a = xzJSON_CreateArray(); + + for(i = 0; a && (i < (size_t)count); i++) + { + n = xzJSON_CreateNumber(numbers[i]); + if(!n) + { + xzJSON_Delete(a); + return NULL; + } + if(!i) + { + a->child = n; + } + else + { + suffix_object(p, n); + } + p = n; + } + + if (a && a->child) { + a->child->prev = n; + } + + return a; +} + +XZJSON_PUBLIC(xzJSON *) xzJSON_CreateStringArray(const char *const *strings, int count) +{ + size_t i = 0; + xzJSON *n = NULL; + xzJSON *p = NULL; + xzJSON *a = NULL; + + if ((count < 0) || (strings == NULL)) + { + return NULL; + } + + a = xzJSON_CreateArray(); + + for (i = 0; a && (i < (size_t)count); i++) + { + n = xzJSON_CreateString(strings[i]); + if(!n) + { + xzJSON_Delete(a); + return NULL; + } + if(!i) + { + a->child = n; + } + else + { + suffix_object(p,n); + } + p = n; + } + + if (a && a->child) { + a->child->prev = n; + } + + return a; +} + +/* Duplication */ +XZJSON_PUBLIC(xzJSON *) xzJSON_Duplicate(const xzJSON *item, xzJSON_bool recurse) +{ + xzJSON *newitem = NULL; + xzJSON *child = NULL; + xzJSON *next = NULL; + xzJSON *newchild = NULL; + + /* Bail on bad ptr */ + if (!item) + { + goto fail; + } + /* Create new item */ + newitem = xzJSON_New_Item(&global_hooks); + if (!newitem) + { + goto fail; + } + /* Copy over all vars */ + newitem->type = item->type & (~xzJSON_IsReference); + newitem->valueint = item->valueint; + newitem->valuedouble = item->valuedouble; + if (item->valuestring) + { + newitem->valuestring = (char*)xzJSON_strdup((unsigned char*)item->valuestring, &global_hooks); + if (!newitem->valuestring) + { + goto fail; + } + } + if (item->string) + { + newitem->string = (item->type&xzJSON_StringIsConst) ? item->string : (char*)xzJSON_strdup((unsigned char*)item->string, &global_hooks); + if (!newitem->string) + { + goto fail; + } + } + /* If non-recursive, then we're done! */ + if (!recurse) + { + return newitem; + } + /* Walk the ->next chain for the child. */ + child = item->child; + while (child != NULL) + { + newchild = xzJSON_Duplicate(child, true); /* Duplicate (with recurse) each item in the ->next chain */ + if (!newchild) + { + goto fail; + } + if (next != NULL) + { + /* If newitem->child already set, then crosswire ->prev and ->next and move on */ + next->next = newchild; + newchild->prev = next; + next = newchild; + } + else + { + /* Set newitem->child and move to it */ + newitem->child = newchild; + next = newchild; + } + child = child->next; + } + if (newitem && newitem->child) + { + newitem->child->prev = newchild; + } + + return newitem; + +fail: + if (newitem != NULL) + { + xzJSON_Delete(newitem); + } + + return NULL; +} + +static void skip_oneline_comment(char **input) +{ + *input += static_strlen("//"); + + for (; (*input)[0] != '\0'; ++(*input)) + { + if ((*input)[0] == '\n') { + *input += static_strlen("\n"); + return; + } + } +} + +static void skip_multiline_comment(char **input) +{ + *input += static_strlen("/*"); + + for (; (*input)[0] != '\0'; ++(*input)) + { + if (((*input)[0] == '*') && ((*input)[1] == '/')) + { + *input += static_strlen("*/"); + return; + } + } +} + +static void minify_string(char **input, char **output) { + (*output)[0] = (*input)[0]; + *input += static_strlen("\""); + *output += static_strlen("\""); + + + for (; (*input)[0] != '\0'; (void)++(*input), ++(*output)) { + (*output)[0] = (*input)[0]; + + if ((*input)[0] == '\"') { + (*output)[0] = '\"'; + *input += static_strlen("\""); + *output += static_strlen("\""); + return; + } else if (((*input)[0] == '\\') && ((*input)[1] == '\"')) { + (*output)[1] = (*input)[1]; + *input += static_strlen("\""); + *output += static_strlen("\""); + } + } +} + +XZJSON_PUBLIC(void) xzJSON_Minify(char *json) +{ + char *into = json; + + if (json == NULL) + { + return; + } + + while (json[0] != '\0') + { + switch (json[0]) + { + case ' ': + case '\t': + case '\r': + case '\n': + json++; + break; + + case '/': + if (json[1] == '/') + { + skip_oneline_comment(&json); + } + else if (json[1] == '*') + { + skip_multiline_comment(&json); + } else { + json++; + } + break; + + case '\"': + minify_string(&json, (char**)&into); + break; + + default: + into[0] = json[0]; + json++; + into++; + } + } + + /* and null-terminate. */ + *into = '\0'; +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsInvalid(const xzJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xFF) == xzJSON_Invalid; +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsFalse(const xzJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xFF) == xzJSON_False; +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsTrue(const xzJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xff) == xzJSON_True; +} + + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsBool(const xzJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & (xzJSON_True | xzJSON_False)) != 0; +} +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsNull(const xzJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xFF) == xzJSON_NULL; +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsNumber(const xzJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xFF) == xzJSON_Number; +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsString(const xzJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xFF) == xzJSON_String; +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsArray(const xzJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xFF) == xzJSON_Array; +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsObject(const xzJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xFF) == xzJSON_Object; +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_IsRaw(const xzJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xFF) == xzJSON_Raw; +} + +XZJSON_PUBLIC(xzJSON_bool) xzJSON_Compare(const xzJSON * const a, const xzJSON * const b, const xzJSON_bool case_sensitive) +{ + if ((a == NULL) || (b == NULL) || ((a->type & 0xFF) != (b->type & 0xFF))) + { + return false; + } + + /* check if type is valid */ + switch (a->type & 0xFF) + { + case xzJSON_False: + case xzJSON_True: + case xzJSON_NULL: + case xzJSON_Number: + case xzJSON_String: + case xzJSON_Raw: + case xzJSON_Array: + case xzJSON_Object: + break; + + default: + return false; + } + + /* identical objects are equal */ + if (a == b) + { + return true; + } + + switch (a->type & 0xFF) + { + /* in these cases and equal type is enough */ + case xzJSON_False: + case xzJSON_True: + case xzJSON_NULL: + return true; + + case xzJSON_Number: + if (compare_double(a->valuedouble, b->valuedouble)) + { + return true; + } + return false; + + case xzJSON_String: + case xzJSON_Raw: + if ((a->valuestring == NULL) || (b->valuestring == NULL)) + { + return false; + } + if (strcmp(a->valuestring, b->valuestring) == 0) + { + return true; + } + + return false; + + case xzJSON_Array: + { + xzJSON *a_element = a->child; + xzJSON *b_element = b->child; + + for (; (a_element != NULL) && (b_element != NULL);) + { + if (!xzJSON_Compare(a_element, b_element, case_sensitive)) + { + return false; + } + + a_element = a_element->next; + b_element = b_element->next; + } + + /* one of the arrays is longer than the other */ + if (a_element != b_element) { + return false; + } + + return true; + } + + case xzJSON_Object: + { + xzJSON *a_element = NULL; + xzJSON *b_element = NULL; + xzJSON_ArrayForEach(a_element, a) + { + /* TODO This has O(n^2) runtime, which is horrible! */ + b_element = get_object_item(b, a_element->string, case_sensitive); + if (b_element == NULL) + { + return false; + } + + if (!xzJSON_Compare(a_element, b_element, case_sensitive)) + { + return false; + } + } + + /* doing this twice, once on a and b to prevent true comparison if a subset of b + * TODO: Do this the proper way, this is just a fix for now */ + xzJSON_ArrayForEach(b_element, b) + { + a_element = get_object_item(a, b_element->string, case_sensitive); + if (a_element == NULL) + { + return false; + } + + if (!xzJSON_Compare(b_element, a_element, case_sensitive)) + { + return false; + } + } + + return true; + } + + default: + return false; + } +} + +XZJSON_PUBLIC(void *) xzJSON_malloc(size_t size) +{ + return global_hooks.allocate(size); +} + +XZJSON_PUBLIC(void) xzJSON_free(void *object) +{ + global_hooks.deallocate(object); +} diff --git a/driver/rfic/ucp/cJSON/src/xzJSON.o b/driver/rfic/ucp/cJSON/src/xzJSON.o new file mode 100644 index 0000000..6a86656 Binary files /dev/null and b/driver/rfic/ucp/cJSON/src/xzJSON.o differ diff --git a/driver/rfic/ucp/cJSON/src/xzJSON_Utils.c b/driver/rfic/ucp/cJSON/src/xzJSON_Utils.c new file mode 100644 index 0000000..9239813 --- /dev/null +++ b/driver/rfic/ucp/cJSON/src/xzJSON_Utils.c @@ -0,0 +1,1481 @@ +/* + Copyright (c) 2009-2017 Dave Gamble and xzJSON contributors + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + THE SOFTWARE. +*/ + +/* disable warnings about old C89 functions in MSVC */ +#if !defined(_CRT_SECURE_NO_DEPRECATE) && defined(_MSC_VER) +#define _CRT_SECURE_NO_DEPRECATE +#endif + +#ifdef __GNUCC__ +#pragma GCC visibility push(default) +#endif +#if defined(_MSC_VER) +#pragma warning (push) +/* disable warning about single line comments in system headers */ +#pragma warning (disable : 4001) +#endif + +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(_MSC_VER) +#pragma warning (pop) +#endif +#ifdef __GNUCC__ +#pragma GCC visibility pop +#endif + +#include "xzJSON_Utils.h" + +/* define our own boolean type */ +#ifdef true +#undef true +#endif +#define true ((xzJSON_bool)1) + +#ifdef false +#undef false +#endif +#define false ((xzJSON_bool)0) + +static unsigned char* xzJSONUtils_strdup(const unsigned char* const string) +{ + size_t length = 0; + unsigned char *copy = NULL; + + length = strlen((const char*)string) + sizeof(""); + copy = (unsigned char*) xzJSON_malloc(length); + if (copy == NULL) + { + return NULL; + } + memcpy(copy, string, length); + + return copy; +} + +/* string comparison which doesn't consider NULL pointers equal */ +static int compare_strings(const unsigned char *string1, const unsigned char *string2, const xzJSON_bool case_sensitive) +{ + if ((string1 == NULL) || (string2 == NULL)) + { + return 1; + } + + if (string1 == string2) + { + return 0; + } + + if (case_sensitive) + { + return strcmp((const char*)string1, (const char*)string2); + } + + for(; tolower(*string1) == tolower(*string2); (void)string1++, string2++) + { + if (*string1 == '\0') + { + return 0; + } + } + + return tolower(*string1) - tolower(*string2); +} + +/* securely comparison of floating-point variables */ +static xzJSON_bool compare_double(double a, double b) +{ + double maxVal = fabs(a) > fabs(b) ? fabs(a) : fabs(b); + return (fabs(a - b) <= maxVal * DBL_EPSILON); +} + + +/* Compare the next path element of two JSON pointers, two NULL pointers are considered unequal: */ +static xzJSON_bool compare_pointers(const unsigned char *name, const unsigned char *pointer, const xzJSON_bool case_sensitive) +{ + if ((name == NULL) || (pointer == NULL)) + { + return false; + } + + for (; (*name != '\0') && (*pointer != '\0') && (*pointer != '/'); (void)name++, pointer++) /* compare until next '/' */ + { + if (*pointer == '~') + { + /* check for escaped '~' (~0) and '/' (~1) */ + if (((pointer[1] != '0') || (*name != '~')) && ((pointer[1] != '1') || (*name != '/'))) + { + /* invalid escape sequence or wrong character in *name */ + return false; + } + else + { + pointer++; + } + } + else if ((!case_sensitive && (tolower(*name) != tolower(*pointer))) || (case_sensitive && (*name != *pointer))) + { + return false; + } + } + if (((*pointer != 0) && (*pointer != '/')) != (*name != 0)) + { + /* one string has ended, the other not */ + return false;; + } + + return true; +} + +/* calculate the length of a string if encoded as JSON pointer with ~0 and ~1 escape sequences */ +static size_t pointer_encoded_length(const unsigned char *string) +{ + size_t length; + for (length = 0; *string != '\0'; (void)string++, length++) + { + /* character needs to be escaped? */ + if ((*string == '~') || (*string == '/')) + { + length++; + } + } + + return length; +} + +/* copy a string while escaping '~' and '/' with ~0 and ~1 JSON pointer escape codes */ +static void encode_string_as_pointer(unsigned char *destination, const unsigned char *source) +{ + for (; source[0] != '\0'; (void)source++, destination++) + { + if (source[0] == '/') + { + destination[0] = '~'; + destination[1] = '1'; + destination++; + } + else if (source[0] == '~') + { + destination[0] = '~'; + destination[1] = '0'; + destination++; + } + else + { + destination[0] = source[0]; + } + } + + destination[0] = '\0'; +} + +XZJSON_PUBLIC(char *) xzJSONUtils_FindPointerFromObjectTo(const xzJSON * const object, const xzJSON * const target) +{ + size_t child_index = 0; + xzJSON *current_child = 0; + + if ((object == NULL) || (target == NULL)) + { + return NULL; + } + + if (object == target) + { + /* found */ + return (char*)xzJSONUtils_strdup((const unsigned char*)""); + } + + /* recursively search all children of the object or array */ + for (current_child = object->child; current_child != NULL; (void)(current_child = current_child->next), child_index++) + { + unsigned char *target_pointer = (unsigned char*)xzJSONUtils_FindPointerFromObjectTo(current_child, target); + /* found the target? */ + if (target_pointer != NULL) + { + if (xzJSON_IsArray(object)) + { + /* reserve enough memory for a 64 bit integer + '/' and '\0' */ + unsigned char *full_pointer = (unsigned char*)xzJSON_malloc(strlen((char*)target_pointer) + 20 + sizeof("/")); + /* check if conversion to unsigned long is valid + * This should be eliminated at compile time by dead code elimination + * if size_t is an alias of unsigned long, or if it is bigger */ + if (child_index > ULONG_MAX) + { + xzJSON_free(target_pointer); + xzJSON_free(full_pointer); + return NULL; + } + sprintf((char*)full_pointer, "/%lu%s", (unsigned long)child_index, target_pointer); /* / */ + xzJSON_free(target_pointer); + + return (char*)full_pointer; + } + + if (xzJSON_IsObject(object)) + { + unsigned char *full_pointer = (unsigned char*)xzJSON_malloc(strlen((char*)target_pointer) + pointer_encoded_length((unsigned char*)current_child->string) + 2); + full_pointer[0] = '/'; + encode_string_as_pointer(full_pointer + 1, (unsigned char*)current_child->string); + strcat((char*)full_pointer, (char*)target_pointer); + xzJSON_free(target_pointer); + + return (char*)full_pointer; + } + + /* reached leaf of the tree, found nothing */ + xzJSON_free(target_pointer); + return NULL; + } + } + + /* not found */ + return NULL; +} + +/* non broken version of xzJSON_GetArrayItem */ +static xzJSON *get_array_item(const xzJSON *array, size_t item) +{ + xzJSON *child = array ? array->child : NULL; + while ((child != NULL) && (item > 0)) + { + item--; + child = child->next; + } + + return child; +} + +static xzJSON_bool decode_array_index_from_pointer(const unsigned char * const pointer, size_t * const index) +{ + size_t parsed_index = 0; + size_t position = 0; + + if ((pointer[0] == '0') && ((pointer[1] != '\0') && (pointer[1] != '/'))) + { + /* leading zeroes are not permitted */ + return 0; + } + + for (position = 0; (pointer[position] >= '0') && (pointer[0] <= '9'); position++) + { + parsed_index = (10 * parsed_index) + (size_t)(pointer[position] - '0'); + + } + + if ((pointer[position] != '\0') && (pointer[position] != '/')) + { + return 0; + } + + *index = parsed_index; + + return 1; +} + +static xzJSON *get_item_from_pointer(xzJSON * const object, const char * pointer, const xzJSON_bool case_sensitive) +{ + xzJSON *current_element = object; + + if (pointer == NULL) + { + return NULL; + } + + /* follow path of the pointer */ + while ((pointer[0] == '/') && (current_element != NULL)) + { + pointer++; + if (xzJSON_IsArray(current_element)) + { + size_t index = 0; + if (!decode_array_index_from_pointer((const unsigned char*)pointer, &index)) + { + return NULL; + } + + current_element = get_array_item(current_element, index); + } + else if (xzJSON_IsObject(current_element)) + { + current_element = current_element->child; + /* GetObjectItem. */ + while ((current_element != NULL) && !compare_pointers((unsigned char*)current_element->string, (const unsigned char*)pointer, case_sensitive)) + { + current_element = current_element->next; + } + } + else + { + return NULL; + } + + /* skip to the next path token or end of string */ + while ((pointer[0] != '\0') && (pointer[0] != '/')) + { + pointer++; + } + } + + return current_element; +} + +XZJSON_PUBLIC(xzJSON *) xzJSONUtils_GetPointer(xzJSON * const object, const char *pointer) +{ + return get_item_from_pointer(object, pointer, false); +} + +XZJSON_PUBLIC(xzJSON *) xzJSONUtils_GetPointerCaseSensitive(xzJSON * const object, const char *pointer) +{ + return get_item_from_pointer(object, pointer, true); +} + +/* JSON Patch implementation. */ +static void decode_pointer_inplace(unsigned char *string) +{ + unsigned char *decoded_string = string; + + if (string == NULL) { + return; + } + + for (; *string; (void)decoded_string++, string++) + { + if (string[0] == '~') + { + if (string[1] == '0') + { + decoded_string[0] = '~'; + } + else if (string[1] == '1') + { + decoded_string[1] = '/'; + } + else + { + /* invalid escape sequence */ + return; + } + + string++; + } + } + + decoded_string[0] = '\0'; +} + +/* non-broken xzJSON_DetachItemFromArray */ +static xzJSON *detach_item_from_array(xzJSON *array, size_t which) +{ + xzJSON *c = array->child; + while (c && (which > 0)) + { + c = c->next; + which--; + } + if (!c) + { + /* item doesn't exist */ + return NULL; + } + if (c != array->child) + { + /* not the first element */ + c->prev->next = c->next; + } + if (c->next) + { + c->next->prev = c->prev; + } + if (c == array->child) + { + array->child = c->next; + } + else if (c->next == NULL) + { + array->child->prev = c->prev; + } + /* make sure the detached item doesn't point anywhere anymore */ + c->prev = c->next = NULL; + + return c; +} + +/* detach an item at the given path */ +static xzJSON *detach_path(xzJSON *object, const unsigned char *path, const xzJSON_bool case_sensitive) +{ + unsigned char *parent_pointer = NULL; + unsigned char *child_pointer = NULL; + xzJSON *parent = NULL; + xzJSON *detached_item = NULL; + + /* copy path and split it in parent and child */ + parent_pointer = xzJSONUtils_strdup(path); + if (parent_pointer == NULL) { + goto cleanup; + } + + child_pointer = (unsigned char*)strrchr((char*)parent_pointer, '/'); /* last '/' */ + if (child_pointer == NULL) + { + goto cleanup; + } + /* split strings */ + child_pointer[0] = '\0'; + child_pointer++; + + parent = get_item_from_pointer(object, (char*)parent_pointer, case_sensitive); + decode_pointer_inplace(child_pointer); + + if (xzJSON_IsArray(parent)) + { + size_t index = 0; + if (!decode_array_index_from_pointer(child_pointer, &index)) + { + goto cleanup; + } + detached_item = detach_item_from_array(parent, index); + } + else if (xzJSON_IsObject(parent)) + { + detached_item = xzJSON_DetachItemFromObject(parent, (char*)child_pointer); + } + else + { + /* Couldn't find object to remove child from. */ + goto cleanup; + } + +cleanup: + if (parent_pointer != NULL) + { + xzJSON_free(parent_pointer); + } + + return detached_item; +} + +/* sort lists using mergesort */ +static xzJSON *sort_list(xzJSON *list, const xzJSON_bool case_sensitive) +{ + xzJSON *first = list; + xzJSON *second = list; + xzJSON *current_item = list; + xzJSON *result = list; + xzJSON *result_tail = NULL; + + if ((list == NULL) || (list->next == NULL)) + { + /* One entry is sorted already. */ + return result; + } + + while ((current_item != NULL) && (current_item->next != NULL) && (compare_strings((unsigned char*)current_item->string, (unsigned char*)current_item->next->string, case_sensitive) < 0)) + { + /* Test for list sorted. */ + current_item = current_item->next; + } + if ((current_item == NULL) || (current_item->next == NULL)) + { + /* Leave sorted lists unmodified. */ + return result; + } + + /* reset pointer to the beginning */ + current_item = list; + while (current_item != NULL) + { + /* Walk two pointers to find the middle. */ + second = second->next; + current_item = current_item->next; + /* advances current_item two steps at a time */ + if (current_item != NULL) + { + current_item = current_item->next; + } + } + if ((second != NULL) && (second->prev != NULL)) + { + /* Split the lists */ + second->prev->next = NULL; + second->prev = NULL; + } + + /* Recursively sort the sub-lists. */ + first = sort_list(first, case_sensitive); + second = sort_list(second, case_sensitive); + result = NULL; + + /* Merge the sub-lists */ + while ((first != NULL) && (second != NULL)) + { + xzJSON *smaller = NULL; + if (compare_strings((unsigned char*)first->string, (unsigned char*)second->string, case_sensitive) < 0) + { + smaller = first; + } + else + { + smaller = second; + } + + if (result == NULL) + { + /* start merged list with the smaller element */ + result_tail = smaller; + result = smaller; + } + else + { + /* add smaller element to the list */ + result_tail->next = smaller; + smaller->prev = result_tail; + result_tail = smaller; + } + + if (first == smaller) + { + first = first->next; + } + else + { + second = second->next; + } + } + + if (first != NULL) + { + /* Append rest of first list. */ + if (result == NULL) + { + return first; + } + result_tail->next = first; + first->prev = result_tail; + } + if (second != NULL) + { + /* Append rest of second list */ + if (result == NULL) + { + return second; + } + result_tail->next = second; + second->prev = result_tail; + } + + return result; +} + +static void sort_object(xzJSON * const object, const xzJSON_bool case_sensitive) +{ + if (object == NULL) + { + return; + } + object->child = sort_list(object->child, case_sensitive); +} + +static xzJSON_bool compare_json(xzJSON *a, xzJSON *b, const xzJSON_bool case_sensitive) +{ + if ((a == NULL) || (b == NULL) || ((a->type & 0xFF) != (b->type & 0xFF))) + { + /* mismatched type. */ + return false; + } + switch (a->type & 0xFF) + { + case xzJSON_Number: + /* numeric mismatch. */ + if ((a->valueint != b->valueint) || (!compare_double(a->valuedouble, b->valuedouble))) + { + return false; + } + else + { + return true; + } + + case xzJSON_String: + /* string mismatch. */ + if (strcmp(a->valuestring, b->valuestring) != 0) + { + return false; + } + else + { + return true; + } + + case xzJSON_Array: + for ((void)(a = a->child), b = b->child; (a != NULL) && (b != NULL); (void)(a = a->next), b = b->next) + { + xzJSON_bool identical = compare_json(a, b, case_sensitive); + if (!identical) + { + return false; + } + } + + /* array size mismatch? (one of both children is not NULL) */ + if ((a != NULL) || (b != NULL)) + { + return false; + } + else + { + return true; + } + + case xzJSON_Object: + sort_object(a, case_sensitive); + sort_object(b, case_sensitive); + for ((void)(a = a->child), b = b->child; (a != NULL) && (b != NULL); (void)(a = a->next), b = b->next) + { + xzJSON_bool identical = false; + /* compare object keys */ + if (compare_strings((unsigned char*)a->string, (unsigned char*)b->string, case_sensitive)) + { + /* missing member */ + return false; + } + identical = compare_json(a, b, case_sensitive); + if (!identical) + { + return false; + } + } + + /* object length mismatch (one of both children is not null) */ + if ((a != NULL) || (b != NULL)) + { + return false; + } + else + { + return true; + } + + default: + break; + } + + /* null, true or false */ + return true; +} + +/* non broken version of xzJSON_InsertItemInArray */ +static xzJSON_bool insert_item_in_array(xzJSON *array, size_t which, xzJSON *newitem) +{ + xzJSON *child = array->child; + while (child && (which > 0)) + { + child = child->next; + which--; + } + if (which > 0) + { + /* item is after the end of the array */ + return 0; + } + if (child == NULL) + { + xzJSON_AddItemToArray(array, newitem); + return 1; + } + + /* insert into the linked list */ + newitem->next = child; + newitem->prev = child->prev; + child->prev = newitem; + + /* was it at the beginning */ + if (child == array->child) + { + array->child = newitem; + } + else + { + newitem->prev->next = newitem; + } + + return 1; +} + +static xzJSON *get_object_item(const xzJSON * const object, const char* name, const xzJSON_bool case_sensitive) +{ + if (case_sensitive) + { + return xzJSON_GetObjectItemCaseSensitive(object, name); + } + + return xzJSON_GetObjectItem(object, name); +} + +enum patch_operation { INVALID, ADD, REMOVE, REPLACE, MOVE, COPY, TEST }; + +static enum patch_operation decode_patch_operation(const xzJSON * const patch, const xzJSON_bool case_sensitive) +{ + xzJSON *operation = get_object_item(patch, "op", case_sensitive); + if (!xzJSON_IsString(operation)) + { + return INVALID; + } + + if (strcmp(operation->valuestring, "add") == 0) + { + return ADD; + } + + if (strcmp(operation->valuestring, "remove") == 0) + { + return REMOVE; + } + + if (strcmp(operation->valuestring, "replace") == 0) + { + return REPLACE; + } + + if (strcmp(operation->valuestring, "move") == 0) + { + return MOVE; + } + + if (strcmp(operation->valuestring, "copy") == 0) + { + return COPY; + } + + if (strcmp(operation->valuestring, "test") == 0) + { + return TEST; + } + + return INVALID; +} + +/* overwrite and existing item with another one and free resources on the way */ +static void overwrite_item(xzJSON * const root, const xzJSON replacement) +{ + if (root == NULL) + { + return; + } + + if (root->string != NULL) + { + xzJSON_free(root->string); + } + if (root->valuestring != NULL) + { + xzJSON_free(root->valuestring); + } + if (root->child != NULL) + { + xzJSON_Delete(root->child); + } + + memcpy(root, &replacement, sizeof(xzJSON)); +} + +static int apply_patch(xzJSON *object, const xzJSON *patch, const xzJSON_bool case_sensitive) +{ + xzJSON *path = NULL; + xzJSON *value = NULL; + xzJSON *parent = NULL; + enum patch_operation opcode = INVALID; + unsigned char *parent_pointer = NULL; + unsigned char *child_pointer = NULL; + int status = 0; + + path = get_object_item(patch, "path", case_sensitive); + if (!xzJSON_IsString(path)) + { + /* malformed patch. */ + status = 2; + goto cleanup; + } + + opcode = decode_patch_operation(patch, case_sensitive); + if (opcode == INVALID) + { + status = 3; + goto cleanup; + } + else if (opcode == TEST) + { + /* compare value: {...} with the given path */ + status = !compare_json(get_item_from_pointer(object, path->valuestring, case_sensitive), get_object_item(patch, "value", case_sensitive), case_sensitive); + goto cleanup; + } + + /* special case for replacing the root */ + if (path->valuestring[0] == '\0') + { + if (opcode == REMOVE) + { + static const xzJSON invalid = { NULL, NULL, NULL, xzJSON_Invalid, NULL, 0, 0, NULL}; + + overwrite_item(object, invalid); + + status = 0; + goto cleanup; + } + + if ((opcode == REPLACE) || (opcode == ADD)) + { + value = get_object_item(patch, "value", case_sensitive); + if (value == NULL) + { + /* missing "value" for add/replace. */ + status = 7; + goto cleanup; + } + + value = xzJSON_Duplicate(value, 1); + if (value == NULL) + { + /* out of memory for add/replace. */ + status = 8; + goto cleanup; + } + + overwrite_item(object, *value); + + /* delete the duplicated value */ + xzJSON_free(value); + value = NULL; + + /* the string "value" isn't needed */ + if (object->string != NULL) + { + xzJSON_free(object->string); + object->string = NULL; + } + + status = 0; + goto cleanup; + } + } + + if ((opcode == REMOVE) || (opcode == REPLACE)) + { + /* Get rid of old. */ + xzJSON *old_item = detach_path(object, (unsigned char*)path->valuestring, case_sensitive); + if (old_item == NULL) + { + status = 13; + goto cleanup; + } + xzJSON_Delete(old_item); + if (opcode == REMOVE) + { + /* For Remove, this job is done. */ + status = 0; + goto cleanup; + } + } + + /* Copy/Move uses "from". */ + if ((opcode == MOVE) || (opcode == COPY)) + { + xzJSON *from = get_object_item(patch, "from", case_sensitive); + if (from == NULL) + { + /* missing "from" for copy/move. */ + status = 4; + goto cleanup; + } + + if (opcode == MOVE) + { + value = detach_path(object, (unsigned char*)from->valuestring, case_sensitive); + } + if (opcode == COPY) + { + value = get_item_from_pointer(object, from->valuestring, case_sensitive); + } + if (value == NULL) + { + /* missing "from" for copy/move. */ + status = 5; + goto cleanup; + } + if (opcode == COPY) + { + value = xzJSON_Duplicate(value, 1); + } + if (value == NULL) + { + /* out of memory for copy/move. */ + status = 6; + goto cleanup; + } + } + else /* Add/Replace uses "value". */ + { + value = get_object_item(patch, "value", case_sensitive); + if (value == NULL) + { + /* missing "value" for add/replace. */ + status = 7; + goto cleanup; + } + value = xzJSON_Duplicate(value, 1); + if (value == NULL) + { + /* out of memory for add/replace. */ + status = 8; + goto cleanup; + } + } + + /* Now, just add "value" to "path". */ + + /* split pointer in parent and child */ + parent_pointer = xzJSONUtils_strdup((unsigned char*)path->valuestring); + if (parent_pointer) { + child_pointer = (unsigned char*)strrchr((char*)parent_pointer, '/'); + } + if (child_pointer != NULL) + { + child_pointer[0] = '\0'; + child_pointer++; + } + parent = get_item_from_pointer(object, (char*)parent_pointer, case_sensitive); + decode_pointer_inplace(child_pointer); + + /* add, remove, replace, move, copy, test. */ + if ((parent == NULL) || (child_pointer == NULL)) + { + /* Couldn't find object to add to. */ + status = 9; + goto cleanup; + } + else if (xzJSON_IsArray(parent)) + { + if (strcmp((char*)child_pointer, "-") == 0) + { + xzJSON_AddItemToArray(parent, value); + value = NULL; + } + else + { + size_t index = 0; + if (!decode_array_index_from_pointer(child_pointer, &index)) + { + status = 11; + goto cleanup; + } + + if (!insert_item_in_array(parent, index, value)) + { + status = 10; + goto cleanup; + } + value = NULL; + } + } + else if (xzJSON_IsObject(parent)) + { + if (case_sensitive) + { + xzJSON_DeleteItemFromObjectCaseSensitive(parent, (char*)child_pointer); + } + else + { + xzJSON_DeleteItemFromObject(parent, (char*)child_pointer); + } + xzJSON_AddItemToObject(parent, (char*)child_pointer, value); + value = NULL; + } + else /* parent is not an object */ + { + /* Couldn't find object to add to. */ + status = 9; + goto cleanup; + } + +cleanup: + if (value != NULL) + { + xzJSON_Delete(value); + } + if (parent_pointer != NULL) + { + xzJSON_free(parent_pointer); + } + + return status; +} + +XZJSON_PUBLIC(int) xzJSONUtils_ApplyPatches(xzJSON * const object, const xzJSON * const patches) +{ + const xzJSON *current_patch = NULL; + int status = 0; + + if (!xzJSON_IsArray(patches)) + { + /* malformed patches. */ + return 1; + } + + if (patches != NULL) + { + current_patch = patches->child; + } + + while (current_patch != NULL) + { + status = apply_patch(object, current_patch, false); + if (status != 0) + { + return status; + } + current_patch = current_patch->next; + } + + return 0; +} + +XZJSON_PUBLIC(int) xzJSONUtils_ApplyPatchesCaseSensitive(xzJSON * const object, const xzJSON * const patches) +{ + const xzJSON *current_patch = NULL; + int status = 0; + + if (!xzJSON_IsArray(patches)) + { + /* malformed patches. */ + return 1; + } + + if (patches != NULL) + { + current_patch = patches->child; + } + + while (current_patch != NULL) + { + status = apply_patch(object, current_patch, true); + if (status != 0) + { + return status; + } + current_patch = current_patch->next; + } + + return 0; +} + +static void compose_patch(xzJSON * const patches, const unsigned char * const operation, const unsigned char * const path, const unsigned char *suffix, const xzJSON * const value) +{ + xzJSON *patch = NULL; + + if ((patches == NULL) || (operation == NULL) || (path == NULL)) + { + return; + } + + patch = xzJSON_CreateObject(); + if (patch == NULL) + { + return; + } + xzJSON_AddItemToObject(patch, "op", xzJSON_CreateString((const char*)operation)); + + if (suffix == NULL) + { + xzJSON_AddItemToObject(patch, "path", xzJSON_CreateString((const char*)path)); + } + else + { + size_t suffix_length = pointer_encoded_length(suffix); + size_t path_length = strlen((const char*)path); + unsigned char *full_path = (unsigned char*)xzJSON_malloc(path_length + suffix_length + sizeof("/")); + + sprintf((char*)full_path, "%s/", (const char*)path); + encode_string_as_pointer(full_path + path_length + 1, suffix); + + xzJSON_AddItemToObject(patch, "path", xzJSON_CreateString((const char*)full_path)); + xzJSON_free(full_path); + } + + if (value != NULL) + { + xzJSON_AddItemToObject(patch, "value", xzJSON_Duplicate(value, 1)); + } + xzJSON_AddItemToArray(patches, patch); +} + +XZJSON_PUBLIC(void) xzJSONUtils_AddPatchToArray(xzJSON * const array, const char * const operation, const char * const path, const xzJSON * const value) +{ + compose_patch(array, (const unsigned char*)operation, (const unsigned char*)path, NULL, value); +} + +static void create_patches(xzJSON * const patches, const unsigned char * const path, xzJSON * const from, xzJSON * const to, const xzJSON_bool case_sensitive) +{ + if ((from == NULL) || (to == NULL)) + { + return; + } + + if ((from->type & 0xFF) != (to->type & 0xFF)) + { + compose_patch(patches, (const unsigned char*)"replace", path, 0, to); + return; + } + + switch (from->type & 0xFF) + { + case xzJSON_Number: + if ((from->valueint != to->valueint) || !compare_double(from->valuedouble, to->valuedouble)) + { + compose_patch(patches, (const unsigned char*)"replace", path, NULL, to); + } + return; + + case xzJSON_String: + if (strcmp(from->valuestring, to->valuestring) != 0) + { + compose_patch(patches, (const unsigned char*)"replace", path, NULL, to); + } + return; + + case xzJSON_Array: + { + size_t index = 0; + xzJSON *from_child = from->child; + xzJSON *to_child = to->child; + unsigned char *new_path = (unsigned char*)xzJSON_malloc(strlen((const char*)path) + 20 + sizeof("/")); /* Allow space for 64bit int. log10(2^64) = 20 */ + + /* generate patches for all array elements that exist in both "from" and "to" */ + for (index = 0; (from_child != NULL) && (to_child != NULL); (void)(from_child = from_child->next), (void)(to_child = to_child->next), index++) + { + /* check if conversion to unsigned long is valid + * This should be eliminated at compile time by dead code elimination + * if size_t is an alias of unsigned long, or if it is bigger */ + if (index > ULONG_MAX) + { + xzJSON_free(new_path); + return; + } + sprintf((char*)new_path, "%s/%lu", path, (unsigned long)index); /* path of the current array element */ + create_patches(patches, new_path, from_child, to_child, case_sensitive); + } + + /* remove leftover elements from 'from' that are not in 'to' */ + for (; (from_child != NULL); (void)(from_child = from_child->next)) + { + /* check if conversion to unsigned long is valid + * This should be eliminated at compile time by dead code elimination + * if size_t is an alias of unsigned long, or if it is bigger */ + if (index > ULONG_MAX) + { + xzJSON_free(new_path); + return; + } + sprintf((char*)new_path, "%lu", (unsigned long)index); + compose_patch(patches, (const unsigned char*)"remove", path, new_path, NULL); + } + /* add new elements in 'to' that were not in 'from' */ + for (; (to_child != NULL); (void)(to_child = to_child->next), index++) + { + compose_patch(patches, (const unsigned char*)"add", path, (const unsigned char*)"-", to_child); + } + xzJSON_free(new_path); + return; + } + + case xzJSON_Object: + { + xzJSON *from_child = NULL; + xzJSON *to_child = NULL; + sort_object(from, case_sensitive); + sort_object(to, case_sensitive); + + from_child = from->child; + to_child = to->child; + /* for all object values in the object with more of them */ + while ((from_child != NULL) || (to_child != NULL)) + { + int diff; + if (from_child == NULL) + { + diff = 1; + } + else if (to_child == NULL) + { + diff = -1; + } + else + { + diff = compare_strings((unsigned char*)from_child->string, (unsigned char*)to_child->string, case_sensitive); + } + + if (diff == 0) + { + /* both object keys are the same */ + size_t path_length = strlen((const char*)path); + size_t from_child_name_length = pointer_encoded_length((unsigned char*)from_child->string); + unsigned char *new_path = (unsigned char*)xzJSON_malloc(path_length + from_child_name_length + sizeof("/")); + + sprintf((char*)new_path, "%s/", path); + encode_string_as_pointer(new_path + path_length + 1, (unsigned char*)from_child->string); + + /* create a patch for the element */ + create_patches(patches, new_path, from_child, to_child, case_sensitive); + xzJSON_free(new_path); + + from_child = from_child->next; + to_child = to_child->next; + } + else if (diff < 0) + { + /* object element doesn't exist in 'to' --> remove it */ + compose_patch(patches, (const unsigned char*)"remove", path, (unsigned char*)from_child->string, NULL); + + from_child = from_child->next; + } + else + { + /* object element doesn't exist in 'from' --> add it */ + compose_patch(patches, (const unsigned char*)"add", path, (unsigned char*)to_child->string, to_child); + + to_child = to_child->next; + } + } + return; + } + + default: + break; + } +} + +XZJSON_PUBLIC(xzJSON *) xzJSONUtils_GeneratePatches(xzJSON * const from, xzJSON * const to) +{ + xzJSON *patches = NULL; + + if ((from == NULL) || (to == NULL)) + { + return NULL; + } + + patches = xzJSON_CreateArray(); + create_patches(patches, (const unsigned char*)"", from, to, false); + + return patches; +} + +XZJSON_PUBLIC(xzJSON *) xzJSONUtils_GeneratePatchesCaseSensitive(xzJSON * const from, xzJSON * const to) +{ + xzJSON *patches = NULL; + + if ((from == NULL) || (to == NULL)) + { + return NULL; + } + + patches = xzJSON_CreateArray(); + create_patches(patches, (const unsigned char*)"", from, to, true); + + return patches; +} + +XZJSON_PUBLIC(void) xzJSONUtils_SortObject(xzJSON * const object) +{ + sort_object(object, false); +} + +XZJSON_PUBLIC(void) xzJSONUtils_SortObjectCaseSensitive(xzJSON * const object) +{ + sort_object(object, true); +} + +static xzJSON *merge_patch(xzJSON *target, const xzJSON * const patch, const xzJSON_bool case_sensitive) +{ + xzJSON *patch_child = NULL; + + if (!xzJSON_IsObject(patch)) + { + /* scalar value, array or NULL, just duplicate */ + xzJSON_Delete(target); + return xzJSON_Duplicate(patch, 1); + } + + if (!xzJSON_IsObject(target)) + { + xzJSON_Delete(target); + target = xzJSON_CreateObject(); + } + + patch_child = patch->child; + while (patch_child != NULL) + { + if (xzJSON_IsNull(patch_child)) + { + /* NULL is the indicator to remove a value, see RFC7396 */ + if (case_sensitive) + { + xzJSON_DeleteItemFromObjectCaseSensitive(target, patch_child->string); + } + else + { + xzJSON_DeleteItemFromObject(target, patch_child->string); + } + } + else + { + xzJSON *replace_me = NULL; + xzJSON *replacement = NULL; + + if (case_sensitive) + { + replace_me = xzJSON_DetachItemFromObjectCaseSensitive(target, patch_child->string); + } + else + { + replace_me = xzJSON_DetachItemFromObject(target, patch_child->string); + } + + replacement = merge_patch(replace_me, patch_child, case_sensitive); + if (replacement == NULL) + { + xzJSON_Delete(target); + return NULL; + } + + xzJSON_AddItemToObject(target, patch_child->string, replacement); + } + patch_child = patch_child->next; + } + return target; +} + +XZJSON_PUBLIC(xzJSON *) xzJSONUtils_MergePatch(xzJSON *target, const xzJSON * const patch) +{ + return merge_patch(target, patch, false); +} + +XZJSON_PUBLIC(xzJSON *) xzJSONUtils_MergePatchCaseSensitive(xzJSON *target, const xzJSON * const patch) +{ + return merge_patch(target, patch, true); +} + +static xzJSON *generate_merge_patch(xzJSON * const from, xzJSON * const to, const xzJSON_bool case_sensitive) +{ + xzJSON *from_child = NULL; + xzJSON *to_child = NULL; + xzJSON *patch = NULL; + if (to == NULL) + { + /* patch to delete everything */ + return xzJSON_CreateNull(); + } + if (!xzJSON_IsObject(to) || !xzJSON_IsObject(from)) + { + return xzJSON_Duplicate(to, 1); + } + + sort_object(from, case_sensitive); + sort_object(to, case_sensitive); + + from_child = from->child; + to_child = to->child; + patch = xzJSON_CreateObject(); + if (patch == NULL) + { + return NULL; + } + while (from_child || to_child) + { + int diff; + if (from_child != NULL) + { + if (to_child != NULL) + { + diff = strcmp(from_child->string, to_child->string); + } + else + { + diff = -1; + } + } + else + { + diff = 1; + } + + if (diff < 0) + { + /* from has a value that to doesn't have -> remove */ + xzJSON_AddItemToObject(patch, from_child->string, xzJSON_CreateNull()); + + from_child = from_child->next; + } + else if (diff > 0) + { + /* to has a value that from doesn't have -> add to patch */ + xzJSON_AddItemToObject(patch, to_child->string, xzJSON_Duplicate(to_child, 1)); + + to_child = to_child->next; + } + else + { + /* object key exists in both objects */ + if (!compare_json(from_child, to_child, case_sensitive)) + { + /* not identical --> generate a patch */ + xzJSON_AddItemToObject(patch, to_child->string, xzJSONUtils_GenerateMergePatch(from_child, to_child)); + } + + /* next key in the object */ + from_child = from_child->next; + to_child = to_child->next; + } + } + if (patch->child == NULL) + { + /* no patch generated */ + xzJSON_Delete(patch); + return NULL; + } + + return patch; +} + +XZJSON_PUBLIC(xzJSON *) xzJSONUtils_GenerateMergePatch(xzJSON * const from, xzJSON * const to) +{ + return generate_merge_patch(from, to, false); +} + +XZJSON_PUBLIC(xzJSON *) xzJSONUtils_GenerateMergePatchCaseSensitive(xzJSON * const from, xzJSON * const to) +{ + return generate_merge_patch(from, to, true); +} diff --git a/driver/rfic/ucp/cJSON/src/xzJSON_Utils.o b/driver/rfic/ucp/cJSON/src/xzJSON_Utils.o new file mode 100644 index 0000000..20b6ac6 Binary files /dev/null and b/driver/rfic/ucp/cJSON/src/xzJSON_Utils.o differ diff --git a/driver/rfic/ucp/libjesd.a b/driver/rfic/ucp/libjesd.a new file mode 100644 index 0000000..34304f0 Binary files /dev/null and b/driver/rfic/ucp/libjesd.a differ diff --git a/driver/rfic/ucp/makefile b/driver/rfic/ucp/makefile new file mode 100644 index 0000000..422c0bb --- /dev/null +++ b/driver/rfic/ucp/makefile @@ -0,0 +1,24 @@ +LIB_UCP4008_JESD = libjesd.a +CC = aarch64-linux-gnu-gcc + +UCP4008_SRC = ./base/src +ARFLAGS = -rv +CFLAGS = -Wall -I./base/inc -I./cJSON/inc -I../ -I./api/inc -Werror +EXT = c + +SRC = $(wildcard api/src/*.$(EXT)) $(wildcard cJSON/src/*.$(EXT)) $(wildcard $(UCP4008_SRC)/*.$(EXT)) +OBJS = $(SRC:.$(EXT)=.o) + +all: $(LIB_UCP4008_JESD) + +.$(EXT).o: + $(CC) $(CFLAGS) -o $@ -c $< + +$(LIB_UCP4008_JESD): $(OBJS) + ar $(ARFLAGS) $(LIB_UCP4008_JESD) $(OBJS) + +clean: + rm -rf $(UCP4008_SRC)/*.o + rm -rf cJSON/src/*.o + rm -rf api/src/*.o + rm -rf *.a \ No newline at end of file diff --git a/driver/rfic/ucp/test/src/nr_fm20000000_1slot_all.c b/driver/rfic/ucp/test/src/nr_fm20000000_1slot_all.c new file mode 100644 index 0000000..27b05a4 --- /dev/null +++ b/driver/rfic/ucp/test/src/nr_fm20000000_1slot_all.c @@ -0,0 +1,245763 @@ +#include + +uint32_t nr_fm20000000_1slot_all[] = { +0x000016c2, +0x136d0bdc, +0x143ff59a, +0x01ade94d, +0xed80f2be, +0xeb0b08e2, +0xfca91683, +0x117a0e95, +0x158df8af, +0x04fde9cb, +0xefa5f02c, +0xe9f805b6, +0xf96515c8, +0x0f2510fd, +0x1664fbed, +0x0831eac4, +0xf225edf2, +0xe95e026b, +0xf6451493, +0x0c7d1307, +0x16bfff41, +0x0b38ec32, +0xf4f2ec1b, +0xe942ff12, +0xf35b12ed, +0x099014a7, +0x169c029a, +0x0e01ee0f, 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+0xea640724, +0xfad5162a, +0x103a0ff6, +0x1614fa78, +0x06c9ea46, +0xf0feeee3, +0xe99303e4, +0xf7a3152b, +0x0db5122b, +0x16a6fdc5, +0x09e6eb81, +0xf3abecdf, +0xe93f008f, +0xf49f13b6, +0x0ae513fc, +0x16bb011e, +0x0ccded2e, +0xf69beb45, +0xe969fd37, +0xf1da11d4, +0x07d8155e, +0x16530471, +0x0f6cef43, +0xf9c0ea1d, +0xea11f9ee, +0xef630f8f, +0x049f1649, +0x156e07ab, +0x11b6f1b5, +0xfd07e96f, +0xeb31f6c7, +0xed490cf4, +0x014d16b9, +0x14120abb, +0x139ef476, +0x005fe93e, +0xecc5f3d3, +0xeb960a11, +0xfdf416ab, +0x12480d8f, +0x1519f776, +0x03b5e98b, +0xeec4f122, +0xea5506f6, +0xfaa7161f, +0x10181018, +0x161ffaa7, +0x06f6ea55, +0xf122eec4, +0xe98b03b5, +0xf7761519, +0x0d8f1248, +0x16abfdf4, +0x0a11eb96, +0xf3d3ecc5, +0xe93e005f, +0xf476139e, +0x0abb1412, +0x16b9014d, +0x0cf4ed49, +0xf6c7eb31, +0xe96ffd07, +0xf1b511b6, +0x07ab156e, +0x1649049f, +0x0f8fef63, +0xf9eeea11, +0xea1df9c0, +0xef430f6c, +0x04711653, +0x155e07d8, +0x11d4f1da, +0xfd37e969, +0xeb45f69b, +0xed2e0ccd, +0x011e16bb, +0x13fc0ae5, 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+0xef030f25, +0x04131664, +0x153c0831, +0x120ef225, +0xfd95e95e, +0xeb6df645, +0xecf90c7d, +0x00bf16bf, +0x13ce0b38, +0x13e5f4f2, +0x00eee942, +0xed13f35b, +0xeb590990, +0xfd66169c, +0x11f10e01, +0x154df7fc, +0x0442e9a4, +0xef23f0b7, +0xea2b066e, +0xfa1c15fc, +0x0fb2107c, +0x163ffb32, +0x077eea82, +0xf190ee68, +0xe9760328, +0xf6f314e2, +0x0d1b129c, +0x16b6fe83, +0x0a90ebd7, +0xf44dec7a, +0xe93effd0, +0xf3fb1354, +0x0a3c1454, +0x16af01dc, +0x0d68ed9c, +0xf74aeaf9, +0xe984fc7a, +0xf147115b, +0x0724159c, +0x162a052b, +0x0ff6efc6, +0xfa78e9ec, +0xea46f937, +0xeee30f02, +0x03e4166d, +0x152b085d, +0x122bf24b, +0xfdc5e95a, +0xeb81f61a, +0xecdf0c55, +0x008f16c1, +0x13b60b61, +0x13fcf51b, +0x011ee945, +0xed2ef333, +0xeb450965, +0xfd371697, +0x11d40e26, +0x155ef828, +0x0471e9ad, +0xef43f094, +0xea1d0640, +0xf9ee15ef, +0x0f8f109d, +0x1649fb61, +0x07abea92, +0xf1b5ee4a, +0xe96f02f9, +0xf6c714cf, +0x0cf412b7, +0x16b9feb3, +0x0abbebee, +0xf476ec62, +0xe93effa1, +0xf3d3133b, +0x0a11146a, +0x16ab020c, +0x0d8fedb8, +0xf776eae7, +0xe98bfc4b, +0xf122113c, +0x06f615ab, +0x161f0559, +0x1018efe8, +0xfaa7e9e1, +0xea55f90a, +0xeec40ede, +0x03b51675, +0x1519088a, +0x1248f271, +0xfdf4e955, +0xeb96f5ef, +0xecc50c2d, +0x005f16c2, +0x139e0b8a, +0x1412f545, +0x014de947, +0xed49f30c, +0xeb310939, +0xfd071691, +0x11b60e4b, +0x156ef855, +0x049fe9b7, +0xef63f071, +0xea110612, +0xf9c015e3, +0x0f6c10bd, +0x1653fb8f, +0x07d8eaa2, +0xf1daee2c, +0xe96902c9, +0xf69b14bb, +0x0ccd12d2, +0x16bbfee2, +0x0ae5ec04, +0xf49fec4a, +0xe93fff71, +0xf3ab1321, +0x09e6147f, +0x16a6023b, +0x0db5edd5, +0xf7a3ead5, +0xe993fc1c, +0xf0fe111d, +0x06c915ba, +0x16140588, +0x103af00a, +0xfad5e9d6, +0xea64f8dc, +0xeea50eb9, +0x0386167c, +0x150708b6, +0x1264f298, +0xfe24e951, +0xebacf5c4, +0xecac0c05, +0x003016c2, +0x13860bb3, +0x1429f570, +0x017de94a, +0xed64f2e5, +0xeb1e090d, +0xfcd8168a, +0x11980e70, +0x157ef882, +0x04cee9c1, +0xef84f04e, +0xea0405e4, +0xf99215d5, +0x0f4910dd, +0x165cfbbe, +0x0804eab3, +0xf1ffee0f, +0xe964029a, +0xf67014a7, +0x0ca512ed, +0x16beff12, +0x0b0eec1b, +0xf4c8ec32, +0xe941ff41, +0xf3831307, +0x09bb1493, +0x16a2026b, +0x0ddbedf2, +0xf7cfeac4, +0xe99cfbed, +0xf0db10fd, +0x069b15c8, +0x160805b6, +0x105bf02c, +0xfb03e9cb, +0xea73f8af, +0xee860e95, +0x03571683, +0x14f508e2, +0x1280f2be, +0xfe53e94d, +0xebc1f59a, +0xec930bdc}; \ No newline at end of file diff --git a/driver/rfic/ucp/test/src/nr_fm20000000_1slot_post7.c b/driver/rfic/ucp/test/src/nr_fm20000000_1slot_post7.c new file mode 100644 index 0000000..d0e2ea1 --- /dev/null +++ b/driver/rfic/ucp/test/src/nr_fm20000000_1slot_post7.c @@ -0,0 +1,122756 @@ +#include + +uint32_t nr_fm20000000_1slot_post7[] = { +0x15fc05e4, +0x107cf04e, +0xfb32e9c1, +0xea82f882, +0xee680e70, +0x0328168a, +0x14e2090d, +0x129cf2e5, +0xfe83e94a, +0xebd7f570, +0xec7a0bb3, +0xffd016c2, +0x13540c05, +0x1454f5c4, +0x01dce951, +0xed9cf298, +0xeaf908b6, +0xfc7a167c, +0x115b0eb9, +0x159cf8dc, +0x052be9d6, +0xefc6f00a, +0xe9ec0588, +0xf93715ba, +0x0f02111d, +0x166dfc1c, +0x085dead5, +0xf24bedd5, +0xe95a023b, +0xf61a147f, +0x0c551321, +0x16c1ff71, +0x0b61ec4a, +0xf51bec04, +0xe945fee2, +0xf33312d2, +0x096514bb, +0x169702c9, +0x0e26ee2c, +0xf828eaa2, +0xe9adfb8f, +0xf09410bd, +0x064015e3, +0x15ef0612, +0x109df071, +0xfb61e9b7, +0xea92f855, +0xee4a0e4b, +0x02f91691, +0x14cf0939, +0x12b7f30c, +0xfeb3e947, +0xebeef545, +0xec620b8a, +0xffa116c2, +0x133b0c2d, +0x146af5ef, +0x020ce955, +0xedb8f271, +0xeae7088a, +0xfc4b1675, +0x113c0ede, +0x15abf90a, +0x0559e9e1, +0xefe8efe8, +0xe9e10559, +0xf90a15ab, +0x0ede113c, +0x1675fc4b, +0x088aeae7, +0xf271edb8, +0xe955020c, +0xf5ef146a, +0x0c2d133b, +0x16c2ffa1, +0x0b8aec62, +0xf545ebee, +0xe947feb3, +0xf30c12b7, +0x093914cf, +0x169102f9, +0x0e4bee4a, +0xf855ea92, +0xe9b7fb61, +0xf071109d, +0x061215ef, +0x15e30640, +0x10bdf094, +0xfb8fe9ad, +0xeaa2f828, +0xee2c0e26, +0x02c91697, +0x14bb0965, +0x12d2f333, +0xfee2e945, +0xec04f51b, +0xec4a0b61, +0xff7116c1, +0x13210c55, +0x147ff61a, +0x023be95a, +0xedd5f24b, +0xead5085d, +0xfc1c166d, +0x111d0f02, +0x15baf937, +0x0588e9ec, +0xf00aefc6, +0xe9d6052b, +0xf8dc159c, +0x0eb9115b, +0x167cfc7a, +0x08b6eaf9, +0xf298ed9c, +0xe95101dc, +0xf5c41454, +0x0c051354, +0x16c2ffd0, +0x0bb3ec7a, +0xf570ebd7, +0xe94afe83, +0xf2e5129c, +0x090d14e2, +0x168a0328, +0x0e70ee68, +0xf882ea82, +0xe9c1fb32, +0xf04e107c, +0x05e415fc, +0x15d5066e, +0x10ddf0b7, +0xfbbee9a4, +0xeab3f7fc, +0xee0f0e01, +0x029a169c, +0x14a70990, +0x12edf35b, +0xff12e942, +0xec1bf4f2, +0xec320b38, +0xff4116bf, +0x13070c7d, +0x1493f645, +0x026be95e, +0xedf2f225, +0xeac40831, +0xfbed1664, +0x10fd0f25, +0x15c8f965, +0x05b6e9f8, +0xf02cefa5, +0xe9cb04fd, +0xf8af158d, +0x0e95117a, +0x1683fca9, +0x08e2eb0b, +0xf2beed80, +0xe94d01ad, +0xf59a143f, +0x0bdc136d, +0x16c20000, +0x0bdcec93, +0xf59aebc1, +0xe94dfe53, +0xf2be1280, +0x08e214f5, +0x16830357, +0x0e95ee86, +0xf8afea73, +0xe9cbfb03, +0xf02c105b, +0x05b61608, +0x15c8069b, +0x10fdf0db, +0xfbede99c, +0xeac4f7cf, +0xedf20ddb, +0x026b16a2, +0x149309bb, +0x1307f383, +0xff41e941, +0xec32f4c8, +0xec1b0b0e, +0xff1216be, +0x12ed0ca5, +0x14a7f670, +0x029ae964, +0xee0ff1ff, +0xeab30804, +0xfbbe165c, +0x10dd0f49, +0x15d5f992, +0x05e4ea04, +0xf04eef84, +0xe9c104ce, +0xf882157e, +0x0e701198, +0x168afcd8, +0x090deb1e, +0xf2e5ed64, +0xe94a017d, +0xf5701429, +0x0bb31386, +0x16c20030, +0x0c05ecac, +0xf5c4ebac, +0xe951fe24, +0xf2981264, +0x08b61507, +0x167c0386, +0x0eb9eea5, +0xf8dcea64, +0xe9d6fad5, +0xf00a103a, +0x05881614, +0x15ba06c9, +0x111df0fe, +0xfc1ce993, +0xead5f7a3, +0xedd50db5, +0x023b16a6, +0x147f09e6, +0x1321f3ab, +0xff71e93f, +0xec4af49f, +0xec040ae5, +0xfee216bb, +0x12d20ccd, +0x14bbf69b, +0x02c9e969, +0xee2cf1da, +0xeaa207d8, +0xfb8f1653, +0x10bd0f6c, +0x15e3f9c0, +0x0612ea11, +0xf071ef63, +0xe9b7049f, +0xf855156e, +0x0e4b11b6, +0x1691fd07, +0x0939eb31, +0xf30ced49, +0xe947014d, +0xf5451412, +0x0b8a139e, +0x16c2005f, +0x0c2decc5, +0xf5efeb96, +0xe955fdf4, +0xf2711248, +0x088a1519, +0x167503b5, +0x0edeeec4, +0xf90aea55, +0xe9e1faa7, +0xefe81018, +0x0559161f, +0x15ab06f6, +0x113cf122, +0xfc4be98b, +0xeae7f776, +0xedb80d8f, +0x020c16ab, +0x146a0a11, +0x133bf3d3, +0xffa1e93e, +0xec62f476, +0xebee0abb, +0xfeb316b9, +0x12b70cf4, +0x14cff6c7, +0x02f9e96f, +0xee4af1b5, +0xea9207ab, +0xfb611649, +0x109d0f8f, +0x15eff9ee, +0x0640ea1d, +0xf094ef43, +0xe9ad0471, +0xf828155e, +0x0e2611d4, +0x1697fd37, +0x0965eb45, +0xf333ed2e, +0xe945011e, +0xf51b13fc, +0x0b6113b6, +0x16c1008f, +0x0c55ecdf, +0xf61aeb81, +0xe95afdc5, +0xf24b122b, +0x085d152b, +0x166d03e4, +0x0f02eee3, +0xf937ea46, +0xe9ecfa78, +0xefc60ff6, +0x052b162a, +0x159c0724, +0x115bf147, +0xfc7ae984, +0xeaf9f74a, +0xed9c0d68, +0x01dc16af, +0x14540a3c, +0x1354f3fb, +0xffd0e93e, +0xec7af44d, +0xebd70a90, +0xfe8316b6, +0x129c0d1b, +0x14e2f6f3, +0x0328e976, +0xee68f190, +0xea82077e, +0xfb32163f, +0x107c0fb2, +0x15fcfa1c, +0x066eea2b, +0xf0b7ef23, +0xe9a40442, +0xf7fc154d, +0x0e0111f1, +0x169cfd66, +0x0990eb59, +0xf35bed13, +0xe94200ee, +0xf4f213e5, +0x0b3813ce, +0x16bf00bf, +0x0c7decf9, +0xf645eb6d, +0xe95efd95, +0xf225120e, +0x0831153c, +0x16640413, +0x0f25ef03, +0xf965ea38, +0xe9f8fa4a, +0xefa50fd4, +0x04fd1635, +0x158d0751, +0x117af16b, +0xfca9e97d, +0xeb0bf71e, +0xed800d42, +0x01ad16b3, +0x143f0a66, +0x136df424, +0x0000e93e, +0xec93f424, +0xebc10a66, +0xfe5316b3, +0x12800d42, +0x14f5f71e, +0x0357e97d, +0xee86f16b, +0xea730751, +0xfb031635, +0x105b0fd4, +0x1608fa4a, +0x069bea38, +0xf0dbef03, +0xe99c0413, +0xf7cf153c, +0x0ddb120e, +0x16a2fd95, +0x09bbeb6d, +0xf383ecf9, +0xe94100bf, +0xf4c813ce, +0x0b0e13e5, +0x16be00ee, +0x0ca5ed13, +0xf670eb59, +0xe964fd66, +0xf1ff11f1, +0x0804154d, +0x165c0442, +0x0f49ef23, +0xf992ea2b, +0xea04fa1c, +0xef840fb2, +0x04ce163f, +0x157e077e, +0x1198f190, +0xfcd8e976, +0xeb1ef6f3, +0xed640d1b, +0x017d16b6, +0x14290a90, +0x1386f44d, +0x0030e93e, +0xecacf3fb, +0xebac0a3c, +0xfe2416af, +0x12640d68, +0x1507f74a, +0x0386e984, +0xeea5f147, +0xea640724, +0xfad5162a, +0x103a0ff6, +0x1614fa78, +0x06c9ea46, +0xf0feeee3, +0xe99303e4, +0xf7a3152b, +0x0db5122b, +0x16a6fdc5, +0x09e6eb81, +0xf3abecdf, +0xe93f008f, +0xf49f13b6, +0x0ae513fc, +0x16bb011e, +0x0ccded2e, +0xf69beb45, +0xe969fd37, +0xf1da11d4, +0x07d8155e, +0x16530471, +0x0f6cef43, +0xf9c0ea1d, +0xea11f9ee, +0xef630f8f, +0x049f1649, +0x156e07ab, +0x11b6f1b5, +0xfd07e96f, +0xeb31f6c7, +0xed490cf4, +0x014d16b9, +0x14120abb, +0x139ef476, +0x005fe93e, +0xecc5f3d3, +0xeb960a11, +0xfdf416ab, +0x12480d8f, +0x1519f776, +0x03b5e98b, +0xeec4f122, +0xea5506f6, +0xfaa7161f, +0x10181018, +0x161ffaa7, +0x06f6ea55, +0xf122eec4, +0xe98b03b5, +0xf7761519, +0x0d8f1248, +0x16abfdf4, +0x0a11eb96, +0xf3d3ecc5, +0xe93e005f, +0xf476139e, +0x0abb1412, +0x16b9014d, +0x0cf4ed49, +0xf6c7eb31, +0xe96ffd07, +0xf1b511b6, +0x07ab156e, +0x1649049f, +0x0f8fef63, +0xf9eeea11, +0xea1df9c0, +0xef430f6c, +0x04711653, +0x155e07d8, +0x11d4f1da, +0xfd37e969, +0xeb45f69b, +0xed2e0ccd, +0x011e16bb, +0x13fc0ae5, +0x13b6f49f, +0x008fe93f, +0xecdff3ab, +0xeb8109e6, +0xfdc516a6, +0x122b0db5, +0x152bf7a3, +0x03e4e993, +0xeee3f0fe, +0xea4606c9, +0xfa781614, +0x0ff6103a, +0x162afad5, +0x0724ea64, +0xf147eea5, +0xe9840386, +0xf74a1507, +0x0d681264, +0x16affe24, +0x0a3cebac, +0xf3fbecac, +0xe93e0030, +0xf44d1386, +0x0a901429, +0x16b6017d, +0x0d1bed64, +0xf6f3eb1e, +0xe976fcd8, +0xf1901198, +0x077e157e, +0x163f04ce, +0x0fb2ef84, +0xfa1cea04, +0xea2bf992, +0xef230f49, +0x0442165c, +0x154d0804, +0x11f1f1ff, +0xfd66e964, +0xeb59f670, +0xed130ca5, +0x00ee16be, +0x13e50b0e, +0x13cef4c8, +0x00bfe941, +0xecf9f383, +0xeb6d09bb, +0xfd9516a2, +0x120e0ddb, +0x153cf7cf, +0x0413e99c, +0xef03f0db, +0xea38069b, +0xfa4a1608, +0x0fd4105b, +0x1635fb03, +0x0751ea73, +0xf16bee86, +0xe97d0357, +0xf71e14f5, +0x0d421280, +0x16b3fe53, +0x0a66ebc1, +0xf424ec93, +0xe93e0000, +0xf424136d, +0x0a66143f, +0x16b301ad, +0x0d42ed80, +0xf71eeb0b, +0xe97dfca9, +0xf16b117a, +0x0751158d, +0x163504fd, +0x0fd4efa5, +0xfa4ae9f8, +0xea38f965, +0xef030f25, +0x04131664, +0x153c0831, +0x120ef225, +0xfd95e95e, +0xeb6df645, +0xecf90c7d, +0x00bf16bf, +0x13ce0b38, +0x13e5f4f2, +0x00eee942, +0xed13f35b, +0xeb590990, +0xfd66169c, +0x11f10e01, +0x154df7fc, +0x0442e9a4, +0xef23f0b7, +0xea2b066e, +0xfa1c15fc, +0x0fb2107c, +0x163ffb32, +0x077eea82, +0xf190ee68, +0xe9760328, +0xf6f314e2, +0x0d1b129c, +0x16b6fe83, +0x0a90ebd7, +0xf44dec7a, +0xe93effd0, +0xf3fb1354, +0x0a3c1454, +0x16af01dc, +0x0d68ed9c, +0xf74aeaf9, +0xe984fc7a, +0xf147115b, +0x0724159c, +0x162a052b, +0x0ff6efc6, +0xfa78e9ec, +0xea46f937, +0xeee30f02, +0x03e4166d, +0x152b085d, +0x122bf24b, +0xfdc5e95a, +0xeb81f61a, +0xecdf0c55, +0x008f16c1, +0x13b60b61, +0x13fcf51b, +0x011ee945, +0xed2ef333, +0xeb450965, +0xfd371697, +0x11d40e26, +0x155ef828, +0x0471e9ad, +0xef43f094, +0xea1d0640, +0xf9ee15ef, +0x0f8f109d, +0x1649fb61, +0x07abea92, +0xf1b5ee4a, +0xe96f02f9, +0xf6c714cf, +0x0cf412b7, +0x16b9feb3, +0x0abbebee, +0xf476ec62, +0xe93effa1, +0xf3d3133b, +0x0a11146a, +0x16ab020c, +0x0d8fedb8, +0xf776eae7, +0xe98bfc4b, +0xf122113c, +0x06f615ab, +0x161f0559, +0x1018efe8, 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+0xecc5f3d3, +0xeb960a11, +0xfdf416ab, +0x12480d8f, +0x1519f776, +0x03b5e98b, +0xeec4f122, +0xea5506f6, +0xfaa7161f, +0x10181018, +0x161ffaa7, +0x06f6ea55, +0xf122eec4, +0xe98b03b5, +0xf7761519, +0x0d8f1248, +0x16abfdf4, +0x0a11eb96, +0xf3d3ecc5, +0xe93e005f, +0xf476139e, +0x0abb1412, +0x16b9014d, +0x0cf4ed49, +0xf6c7eb31, +0xe96ffd07, +0xf1b511b6, +0x07ab156e, +0x1649049f, +0x0f8fef63, +0xf9eeea11, +0xea1df9c0, +0xef430f6c, +0x04711653, +0x155e07d8, +0x11d4f1da, +0xfd37e969, +0xeb45f69b, +0xed2e0ccd, +0x011e16bb, +0x13fc0ae5, +0x13b6f49f, +0x008fe93f, +0xecdff3ab, +0xeb8109e6, +0xfdc516a6, +0x122b0db5, +0x152bf7a3, +0x03e4e993, +0xeee3f0fe, +0xea4606c9, +0xfa781614, +0x0ff6103a, +0x162afad5, +0x0724ea64, +0xf147eea5, +0xe9840386, +0xf74a1507, +0x0d681264, +0x16affe24, +0x0a3cebac, +0xf3fbecac, +0xe93e0030, +0xf44d1386, +0x0a901429, +0x16b6017d, +0x0d1bed64, +0xf6f3eb1e, +0xe976fcd8, +0xf1901198, +0x077e157e, +0x163f04ce, +0x0fb2ef84, +0xfa1cea04, +0xea2bf992, +0xef230f49, +0x0442165c, +0x154d0804, +0x11f1f1ff, +0xfd66e964, +0xeb59f670, +0xed130ca5, +0x00ee16be, +0x13e50b0e, +0x13cef4c8, +0x00bfe941, +0xecf9f383, +0xeb6d09bb, +0xfd9516a2, +0x120e0ddb, +0x153cf7cf, +0x0413e99c, +0xef03f0db, +0xea38069b, +0xfa4a1608, +0x0fd4105b, +0x1635fb03, +0x0751ea73, +0xf16bee86, +0xe97d0357, +0xf71e14f5, +0x0d421280, +0x16b3fe53, +0x0a66ebc1, +0xf424ec93, +0xe93e0000, +0xf424136d, +0x0a66143f, +0x16b301ad, +0x0d42ed80, +0xf71eeb0b, +0xe97dfca9, +0xf16b117a, +0x0751158d, +0x163504fd, +0x0fd4efa5, +0xfa4ae9f8, +0xea38f965, +0xef030f25, +0x04131664, +0x153c0831, +0x120ef225, +0xfd95e95e, +0xeb6df645, +0xecf90c7d, +0x00bf16bf, +0x13ce0b38, +0x13e5f4f2, +0x00eee942, +0xed13f35b, +0xeb590990, +0xfd66169c, +0x11f10e01, +0x154df7fc, +0x0442e9a4, +0xef23f0b7, +0xea2b066e, +0xfa1c15fc, +0x0fb2107c, +0x163ffb32, +0x077eea82, +0xf190ee68, +0xe9760328, +0xf6f314e2, +0x0d1b129c, +0x16b6fe83, +0x0a90ebd7, +0xf44dec7a, +0xe93effd0, +0xf3fb1354, +0x0a3c1454, +0x16af01dc, +0x0d68ed9c, +0xf74aeaf9, +0xe984fc7a, +0xf147115b, +0x0724159c, +0x162a052b, +0x0ff6efc6, +0xfa78e9ec, +0xea46f937, +0xeee30f02, +0x03e4166d, +0x152b085d, +0x122bf24b, +0xfdc5e95a, +0xeb81f61a, +0xecdf0c55, +0x008f16c1, +0x13b60b61, +0x13fcf51b, +0x011ee945, +0xed2ef333, +0xeb450965, +0xfd371697, +0x11d40e26, +0x155ef828, +0x0471e9ad, +0xef43f094, +0xea1d0640, +0xf9ee15ef, +0x0f8f109d, +0x1649fb61, +0x07abea92, +0xf1b5ee4a, +0xe96f02f9, +0xf6c714cf, +0x0cf412b7, +0x16b9feb3, +0x0abbebee, +0xf476ec62, +0xe93effa1, +0xf3d3133b, +0x0a11146a, +0x16ab020c, +0x0d8fedb8, +0xf776eae7, +0xe98bfc4b, +0xf122113c, +0x06f615ab, +0x161f0559, +0x1018efe8, +0xfaa7e9e1, +0xea55f90a, +0xeec40ede, +0x03b51675, +0x1519088a, +0x1248f271, +0xfdf4e955, +0xeb96f5ef, +0xecc50c2d, +0x005f16c2, +0x139e0b8a, +0x1412f545, +0x014de947, +0xed49f30c, +0xeb310939, +0xfd071691, +0x11b60e4b, +0x156ef855, +0x049fe9b7, +0xef63f071, +0xea110612, +0xf9c015e3, +0x0f6c10bd, +0x1653fb8f, +0x07d8eaa2, +0xf1daee2c, +0xe96902c9, +0xf69b14bb, +0x0ccd12d2, +0x16bbfee2, +0x0ae5ec04, +0xf49fec4a, +0xe93fff71, +0xf3ab1321, +0x09e6147f, +0x16a6023b, +0x0db5edd5, +0xf7a3ead5, +0xe993fc1c, +0xf0fe111d, +0x06c915ba, +0x16140588, +0x103af00a, +0xfad5e9d6, +0xea64f8dc, +0xeea50eb9, +0x0386167c, +0x150708b6, +0x1264f298, +0xfe24e951, +0xebacf5c4, +0xecac0c05, +0x003016c2, +0x13860bb3, +0x1429f570, +0x017de94a, +0xed64f2e5, +0xeb1e090d, +0xfcd8168a, +0x11980e70, +0x157ef882, +0x04cee9c1, +0xef84f04e, +0xea0405e4, +0xf99215d5, +0x0f4910dd, +0x165cfbbe, +0x0804eab3, +0xf1ffee0f, +0xe964029a, +0xf67014a7, +0x0ca512ed, +0x16beff12, +0x0b0eec1b, +0xf4c8ec32, +0xe941ff41, +0xf3831307, +0x09bb1493, +0x16a2026b, +0x0ddbedf2, +0xf7cfeac4, +0xe99cfbed, +0xf0db10fd, +0x069b15c8, +0x160805b6, +0x105bf02c, +0xfb03e9cb, +0xea73f8af, +0xee860e95, +0x03571683, +0x14f508e2, +0x1280f2be, +0xfe53e94d, +0xebc1f59a, +0xec930bdc +}; diff --git a/driver/rfic/ucp/test/src/nr_fm20000000_1slot_pre7.c b/driver/rfic/ucp/test/src/nr_fm20000000_1slot_pre7.c new file mode 100644 index 0000000..eced567 --- /dev/null +++ b/driver/rfic/ucp/test/src/nr_fm20000000_1slot_pre7.c @@ -0,0 +1,123012 @@ +#include + +uint32_t nr_fm20000000_1slot_pre7[] = { +0x000016c2, +0x136d0bdc, +0x143ff59a, +0x01ade94d, +0xed80f2be, +0xeb0b08e2, +0xfca91683, +0x117a0e95, +0x158df8af, +0x04fde9cb, +0xefa5f02c, +0xe9f805b6, +0xf96515c8, +0x0f2510fd, +0x1664fbed, +0x0831eac4, +0xf225edf2, +0xe95e026b, +0xf6451493, +0x0c7d1307, +0x16bfff41, +0x0b38ec32, +0xf4f2ec1b, +0xe942ff12, +0xf35b12ed, +0x099014a7, +0x169c029a, +0x0e01ee0f, +0xf7fceab3, +0xe9a4fbbe, +0xf0b710dd, +0x066e15d5, +0x15fc05e4, +0x107cf04e, +0xfb32e9c1, +0xea82f882, +0xee680e70, +0x0328168a, +0x14e2090d, +0x129cf2e5, +0xfe83e94a, +0xebd7f570, +0xec7a0bb3, +0xffd016c2, +0x13540c05, +0x1454f5c4, +0x01dce951, +0xed9cf298, +0xeaf908b6, +0xfc7a167c, +0x115b0eb9, +0x159cf8dc, +0x052be9d6, +0xefc6f00a, +0xe9ec0588, +0xf93715ba, +0x0f02111d, +0x166dfc1c, +0x085dead5, +0xf24bedd5, +0xe95a023b, +0xf61a147f, +0x0c551321, +0x16c1ff71, +0x0b61ec4a, +0xf51bec04, +0xe945fee2, +0xf33312d2, +0x096514bb, +0x169702c9, +0x0e26ee2c, +0xf828eaa2, +0xe9adfb8f, +0xf09410bd, +0x064015e3, +0x15ef0612, +0x109df071, +0xfb61e9b7, +0xea92f855, +0xee4a0e4b, +0x02f91691, +0x14cf0939, +0x12b7f30c, +0xfeb3e947, +0xebeef545, +0xec620b8a, +0xffa116c2, +0x133b0c2d, +0x146af5ef, +0x020ce955, +0xedb8f271, +0xeae7088a, +0xfc4b1675, +0x113c0ede, +0x15abf90a, +0x0559e9e1, +0xefe8efe8, +0xe9e10559, +0xf90a15ab, +0x0ede113c, +0x1675fc4b, +0x088aeae7, +0xf271edb8, +0xe955020c, +0xf5ef146a, +0x0c2d133b, +0x16c2ffa1, +0x0b8aec62, +0xf545ebee, +0xe947feb3, +0xf30c12b7, +0x093914cf, +0x169102f9, +0x0e4bee4a, +0xf855ea92, +0xe9b7fb61, +0xf071109d, +0x061215ef, +0x15e30640, +0x10bdf094, +0xfb8fe9ad, +0xeaa2f828, +0xee2c0e26, +0x02c91697, +0x14bb0965, +0x12d2f333, +0xfee2e945, +0xec04f51b, +0xec4a0b61, +0xff7116c1, +0x13210c55, +0x147ff61a, +0x023be95a, +0xedd5f24b, +0xead5085d, +0xfc1c166d, +0x111d0f02, +0x15baf937, +0x0588e9ec, +0xf00aefc6, +0xe9d6052b, +0xf8dc159c, +0x0eb9115b, +0x167cfc7a, +0x08b6eaf9, +0xf298ed9c, +0xe95101dc, +0xf5c41454, +0x0c051354, +0x16c2ffd0, +0x0bb3ec7a, +0xf570ebd7, +0xe94afe83, +0xf2e5129c, +0x090d14e2, +0x168a0328, +0x0e70ee68, +0xf882ea82, +0xe9c1fb32, +0xf04e107c, +0x05e415fc, +0x15d5066e, +0x10ddf0b7, +0xfbbee9a4, +0xeab3f7fc, +0xee0f0e01, +0x029a169c, +0x14a70990, +0x12edf35b, +0xff12e942, +0xec1bf4f2, +0xec320b38, +0xff4116bf, +0x13070c7d, +0x1493f645, +0x026be95e, +0xedf2f225, +0xeac40831, +0xfbed1664, +0x10fd0f25, +0x15c8f965, +0x05b6e9f8, +0xf02cefa5, +0xe9cb04fd, +0xf8af158d, +0x0e95117a, +0x1683fca9, +0x08e2eb0b, +0xf2beed80, +0xe94d01ad, +0xf59a143f, +0x0bdc136d, +0x16c20000, +0x0bdcec93, +0xf59aebc1, +0xe94dfe53, +0xf2be1280, +0x08e214f5, +0x16830357, +0x0e95ee86, +0xf8afea73, +0xe9cbfb03, +0xf02c105b, +0x05b61608, +0x15c8069b, +0x10fdf0db, +0xfbede99c, +0xeac4f7cf, +0xedf20ddb, +0x026b16a2, +0x149309bb, +0x1307f383, +0xff41e941, +0xec32f4c8, +0xec1b0b0e, +0xff1216be, +0x12ed0ca5, +0x14a7f670, +0x029ae964, +0xee0ff1ff, +0xeab30804, +0xfbbe165c, +0x10dd0f49, +0x15d5f992, +0x05e4ea04, +0xf04eef84, +0xe9c104ce, +0xf882157e, +0x0e701198, +0x168afcd8, +0x090deb1e, +0xf2e5ed64, +0xe94a017d, +0xf5701429, +0x0bb31386, +0x16c20030, +0x0c05ecac, +0xf5c4ebac, +0xe951fe24, +0xf2981264, +0x08b61507, +0x167c0386, +0x0eb9eea5, +0xf8dcea64, +0xe9d6fad5, +0xf00a103a, +0x05881614, +0x15ba06c9, +0x111df0fe, +0xfc1ce993, +0xead5f7a3, +0xedd50db5, +0x023b16a6, +0x147f09e6, +0x1321f3ab, +0xff71e93f, +0xec4af49f, +0xec040ae5, +0xfee216bb, +0x12d20ccd, +0x14bbf69b, +0x02c9e969, +0xee2cf1da, +0xeaa207d8, +0xfb8f1653, +0x10bd0f6c, +0x15e3f9c0, +0x0612ea11, +0xf071ef63, +0xe9b7049f, +0xf855156e, +0x0e4b11b6, +0x1691fd07, +0x0939eb31, +0xf30ced49, +0xe947014d, +0xf5451412, +0x0b8a139e, +0x16c2005f, +0x0c2decc5, +0xf5efeb96, +0xe955fdf4, +0xf2711248, +0x088a1519, +0x167503b5, +0x0edeeec4, +0xf90aea55, +0xe9e1faa7, +0xefe81018, +0x0559161f, +0x15ab06f6, +0x113cf122, +0xfc4be98b, +0xeae7f776, +0xedb80d8f, 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+0xe941ff41, +0xf3831307, +0x09bb1493, +0x16a2026b, +0x0ddbedf2, +0xf7cfeac4, +0xe99cfbed, +0xf0db10fd, +0x069b15c8, +0x160805b6, +0x105bf02c, +0xfb03e9cb, +0xea73f8af, +0xee860e95, +0x03571683, +0x14f508e2, +0x1280f2be, +0xfe53e94d, +0xebc1f59a, +0xec930bdc, +0x000016c2, +0x136d0bdc, +0x143ff59a, +0x01ade94d, +0xed80f2be, +0xeb0b08e2, +0xfca91683, +0x117a0e95, +0x158df8af, +0x04fde9cb, +0xefa5f02c, +0xe9f805b6, +0xf96515c8, +0x0f2510fd, +0x1664fbed, +0x0831eac4, +0xf225edf2, +0xe95e026b, +0xf6451493, +0x0c7d1307, +0x16bfff41, +0x0b38ec32, +0xf4f2ec1b, +0xe942ff12, +0xf35b12ed, +0x099014a7, +0x169c029a, +0x0e01ee0f, +0xf7fceab3, +0xe9a4fbbe, +0xf0b710dd, +0x066e15d5 +}; \ No newline at end of file diff --git a/driver/tfu/README.md b/driver/tfu/README.md new file mode 100644 index 0000000..cf14de2 --- /dev/null +++ b/driver/tfu/README.md @@ -0,0 +1,92 @@ +# UCP4008_TFU + + + +## Getting started + +To make it easy for you to get started with GitLab, here's a list of recommended next steps. + +Already a pro? Just edit this README.md and make it your own. Want to make it easy? [Use the template at the bottom](#editing-this-readme)! + +## Add your files + +- [ ] [Create](https://docs.gitlab.com/ee/user/project/repository/web_editor.html#create-a-file) or [upload](https://docs.gitlab.com/ee/user/project/repository/web_editor.html#upload-a-file) files +- [ ] [Add files using the command line](https://docs.gitlab.com/ee/gitlab-basics/add-file.html#add-a-file-using-the-command-line) or push an existing Git repository with the following command: + +``` +cd existing_repo +git remote add origin http://gitlab.smartlogictech.com/ucp/driver/ucp4008_tfu.git +git branch -M main +git push -uf origin main +``` + +## Integrate with your tools + +- [ ] [Set up project integrations](http://gitlab.smartlogictech.com/ucp/driver/ucp4008_tfu/-/settings/integrations) + +## Collaborate with your team + +- [ ] [Invite team members and collaborators](https://docs.gitlab.com/ee/user/project/members/) +- [ ] [Create a new merge request](https://docs.gitlab.com/ee/user/project/merge_requests/creating_merge_requests.html) +- [ ] [Automatically close issues from merge requests](https://docs.gitlab.com/ee/user/project/issues/managing_issues.html#closing-issues-automatically) +- [ ] [Enable merge request approvals](https://docs.gitlab.com/ee/user/project/merge_requests/approvals/) +- [ ] [Set auto-merge](https://docs.gitlab.com/ee/user/project/merge_requests/merge_when_pipeline_succeeds.html) + +## Test and Deploy + +Use the built-in continuous integration in GitLab. + +- [ ] [Get started with GitLab CI/CD](https://docs.gitlab.com/ee/ci/quick_start/index.html) +- [ ] [Analyze your code for known vulnerabilities with Static Application Security Testing(SAST)](https://docs.gitlab.com/ee/user/application_security/sast/) +- [ ] [Deploy to Kubernetes, Amazon EC2, or Amazon ECS using Auto Deploy](https://docs.gitlab.com/ee/topics/autodevops/requirements.html) +- [ ] [Use pull-based deployments for improved Kubernetes management](https://docs.gitlab.com/ee/user/clusters/agent/) +- [ ] [Set up protected environments](https://docs.gitlab.com/ee/ci/environments/protected_environments.html) + +*** + +# Editing this README + +When you're ready to make this README your own, just edit this file and use the handy template below (or feel free to structure it however you want - this is just a starting point!). Thank you to [makeareadme.com](https://www.makeareadme.com/) for this template. + +## Suggestions for a good README +Every project is different, so consider which of these sections apply to yours. The sections used in the template are suggestions for most open source projects. Also keep in mind that while a README can be too long and detailed, too long is better than too short. If you think your README is too long, consider utilizing another form of documentation rather than cutting out information. + +## Name +Choose a self-explaining name for your project. + +## Description +Let people know what your project can do specifically. Provide context and add a link to any reference visitors might be unfamiliar with. A list of Features or a Background subsection can also be added here. If there are alternatives to your project, this is a good place to list differentiating factors. + +## Badges +On some READMEs, you may see small images that convey metadata, such as whether or not all the tests are passing for the project. You can use Shields to add some to your README. Many services also have instructions for adding a badge. + +## Visuals +Depending on what you are making, it can be a good idea to include screenshots or even a video (you'll frequently see GIFs rather than actual videos). Tools like ttygif can help, but check out Asciinema for a more sophisticated method. + +## Installation +Within a particular ecosystem, there may be a common way of installing things, such as using Yarn, NuGet, or Homebrew. However, consider the possibility that whoever is reading your README is a novice and would like more guidance. Listing specific steps helps remove ambiguity and gets people to using your project as quickly as possible. If it only runs in a specific context like a particular programming language version or operating system or has dependencies that have to be installed manually, also add a Requirements subsection. + +## Usage +Use examples liberally, and show the expected output if you can. It's helpful to have inline the smallest example of usage that you can demonstrate, while providing links to more sophisticated examples if they are too long to reasonably include in the README. + +## Support +Tell people where they can go to for help. It can be any combination of an issue tracker, a chat room, an email address, etc. + +## Roadmap +If you have ideas for releases in the future, it is a good idea to list them in the README. + +## Contributing +State if you are open to contributions and what your requirements are for accepting them. + +For people who want to make changes to your project, it's helpful to have some documentation on how to get started. Perhaps there is a script that they should run or some environment variables that they need to set. Make these steps explicit. These instructions could also be useful to your future self. + +You can also document commands to lint the code or run tests. These steps help to ensure high code quality and reduce the likelihood that the changes inadvertently break something. Having instructions for running tests is especially helpful if it requires external setup, such as starting a Selenium server for testing in a browser. + +## Authors and acknowledgment +Show your appreciation to those who have contributed to the project. + +## License +For open source projects, say how it is licensed. + +## Project status +If you have run out of energy or time for your project, put a note at the top of the README saying that development has slowed down or stopped completely. Someone may choose to fork your project or volunteer to step in as a maintainer or owner, allowing your project to keep going. You can also make an explicit request for maintainers. diff --git a/driver/tfu/build.sh b/driver/tfu/build.sh new file mode 100644 index 0000000..8290424 --- /dev/null +++ b/driver/tfu/build.sh @@ -0,0 +1,12 @@ +set -e + +# git submodule init +# git submodule update --remote --merge --recursive + +# git clean -dxf +# git fetch +# git checkout DEV +# git pull + +make clean +make all diff --git a/driver/tfu/build/libstc.a b/driver/tfu/build/libstc.a new file mode 100644 index 0000000..57184e1 Binary files /dev/null and b/driver/tfu/build/libstc.a differ diff --git a/driver/tfu/build/obj/main.o b/driver/tfu/build/obj/main.o new file mode 100644 index 0000000..13b4f0d Binary files /dev/null and b/driver/tfu/build/obj/main.o differ diff --git a/driver/tfu/build/obj/stc_drv.o b/driver/tfu/build/obj/stc_drv.o new file mode 100644 index 0000000..fd32392 Binary files /dev/null and b/driver/tfu/build/obj/stc_drv.o differ diff --git a/driver/tfu/build/obj/ublox_drv.o b/driver/tfu/build/obj/ublox_drv.o new file mode 100644 index 0000000..266b2d3 Binary files /dev/null and b/driver/tfu/build/obj/ublox_drv.o differ diff --git a/driver/tfu/build/tfu.out b/driver/tfu/build/tfu.out new file mode 100644 index 0000000..0c2b6b3 Binary files /dev/null and b/driver/tfu/build/tfu.out differ diff --git a/driver/tfu/lc98s/inc/lc98s_drv.h b/driver/tfu/lc98s/inc/lc98s_drv.h new file mode 100644 index 0000000..1208556 --- /dev/null +++ b/driver/tfu/lc98s/inc/lc98s_drv.h @@ -0,0 +1,125 @@ +/*------------------------------------------------------------ +// Copyright (c) 2022 SmartLogic. +// ALL RIGHTS RESERVED +// ----------------------------------------------------------------- +// Filename : stc_drv.c +// Author : weihua.li +// Created On : 2022-11-23 +// Last Modified : +// ----------------------------------------------------------------- +// Description: +// +// +// ----------------------------------------------------------------*/ + +#ifndef __LC98S_DRV_H__ +#define __LC98S_DRV_H__ + +#define NUMCHN 20 +#define GPS_TX_BUF_SIZE 256 +#define GPS_RX_BUF_SIZE 1024 +#define GPS_SEM_NUM 13 +#define HALF_BUFSIZE 511 +#define MY_IPCKEY 0x10005500 + +#define MIN(x,y) ((x)<(y)?(x):(y)) +#define MAX(x,y) ((x)>(y)?(x):(y)) + +#define GPS_SECONDS(tow,wnum) (604800*(wnum) + (tow)) +#define MOD_2N(x,y) ((x) & (y-1)) + + +#define GPS_FIX_OK 0x03 +#define NAV_ALMANACH 0x04 + +/* arg for semctl system calls. */ +union semun { + int val; /* value for SETVAL */ + struct semid_ds *buf; /* buffer for IPC_STAT & IPC_SET */ + unsigned short *array; /* array for GETALL & SETALL */ + struct seminfo *__buf; /* buffer for IPC_INFO */ +}; + +typedef struct +{ + int32_t latitude; /*degree 1e-7*/ + int32_t longitude;/*degree 1e-7*/ + int32_t altitude; /*millimeter*/ + uint8_t gps_fix; + uint8_t fix_flag; + uint32_t time_of_week; + uint8_t valid_flag; + int8_t leap_sec; + uint16_t week_number; + uint8_t num_ch; + int16_t cab_dly; /*cable delay time,uint:ns*/ + uint32_t pulse_width; /*Length of time pulse*/ + int8_t pps_status; /*PPS: >0,postive; =0,no;<0, negative*/ + uint8_t ant_state; + uint8_t sw_version[30]; + uint8_t hw_version[10]; + uint8_t sta_id[NUMCHN]; /*satellite ID*/ + uint8_t cno[NUMCHN]; /*Carrier to Noise Ratio (Signal Strength)*/ + uint8_t tracking_num; + uint8_t visable_num; + uint8_t sig_over_high; + uint8_t lock_state; /*1: gps lock 0: gps unlock*/ + +}drv_gps_msg_s; + +/********************************************************************/ +typedef struct +{ + uint8_t recv_buf[GPS_RX_BUF_SIZE]; + /*union + { + uint32_t whole; + struct + { + uint16_t recv_ptr; //接收指针 + uint16_t deal_ptr; //处理指针 + } + }*/ + uint16_t recv_ptr; /*接收指针*/ + uint16_t deal_ptr; /*处理指针*/ + uint16_t recv_cnt; /*最新接收到的消息长?*/ + uint16_t deal_cnt; /*未处理消息长?*/ + int32_t send_sem; + uint8_t *send_buf_ptr; + uint16_t send_cnt; /*待发送消息长?*/ + uint16_t frame_flag; //帧头 +}gps_uart_s; + +typedef struct +{ + int32_t latitude; //纬度 单位：度/1e-7 + int32_t longitude; //经度 单位：度/1e-7 + int32_t altitude; //高度 单位：毫? +}location_info_s; + +typedef struct +{ + uint8_t lock_flag; /* GPS Fixed ok */ + uint8_t leap_valid; /* leap second valid */ + uint8_t view_sats; /* Satellites in view */ + uint8_t track_sats; /* Satellites under tracking */ + uint8_t survey_in; /*0 not in Survey-in mode*/ + uint8_t alma_complete; /* 0 Calendar not complete */ + uint8_t resv[2]; /* resv*/ + float sig_level[12]; /* signal level of satellites */ +}tracking_info_s; + +int32_t drv_tfu_gps_init(void); +void drv_gps_recv_task(void); +int32_t init_clock_module(void); +int32_t get_receiver_fix_status(); +int32_t get_src_time(time_t* time_ptr); + +#ifdef __cplusplus + #if __cplusplus + } + #endif +#endif + +#endif +/**********************************************************************/ diff --git a/driver/tfu/lc98s/src/lc98s_drv.c b/driver/tfu/lc98s/src/lc98s_drv.c new file mode 100644 index 0000000..8c74382 --- /dev/null +++ b/driver/tfu/lc98s/src/lc98s_drv.c @@ -0,0 +1,634 @@ +/*------------------------------------------------------------ +// Copyright (c) 2022 SmartLogic. +// ALL RIGHTS RESERVED +// ----------------------------------------------------------------- +// Filename : stc_drv.c +// Author : weihua.li +// Created On : 2022-11-23 +// Last Modified : +// ----------------------------------------------------------------- +// Description: +// +// +// ----------------------------------------------------------------*/ +#define _GNU_SOURCE +#include +#include +#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include + +#include "ucp_printf.h" +#include "typedef.h" +#include "../inc/lc98s_drv.h" +#include "nmea.h" + +#define PRINT_NO (0) +#define PRINT_UTC (1<<0) +#define PRINT_MSG (1<<1) +#define PRINT_GGA (1<<2) +#define PRINT_GSA (1<<3) +#define PRINT_GSV (1<<4) +#define PRINT_RMC (1<<5) + +drv_gps_msg_s g_gps_recv_msg; + +uint8_t g_tx_buf[GPS_TX_BUF_SIZE]; +uint8_t g_curRxIndex = 0; +uint8_t g_rx_cnt[2] = {0, 0}; +uint8_t g_rx_buf[2][HALF_BUFSIZE]; +int32_t g_gps_recv_task_id = -1; + + +gps_uart_s g_gps_uart = +{ + .recv_ptr = 0, + .deal_ptr = 0, + .recv_cnt = 0, + .deal_cnt = 0, + .send_cnt = 0, + .send_buf_ptr = (uint8_t*)(g_tx_buf), +}; + +uint8_t g_almanach_flag; /*Almanach flag*/ +int32_t g_ubx_sem[GPS_SEM_NUM]; +uint32_t g_tod_link_alarm = 0; +int32_t g_tfu_sync_sem = -1; //pp1s中断同步信号量 +int32_t g_tfu_to_time_sem = 0; //tracking后释放给OM，计算帧号 +int32_t g_tfu_init_flag = 0; +int32_t drv_uart_fd = -1; +int32_t g_sem_prj_id = 20; + +static struct tGGA gga; +static struct tGSA gsa; +static struct tGSV gsv; +static struct tRMC rmc; +static uint16_t printMask = (PRINT_UTC); + +extern void drv_tfu_phase_adjust(uint8_t count); +extern int32_t drv_semaphore_p(int32_t sem_id); +static int32_t drv_semaphore_timed_p(int32_t sem_id,int32_t timeout_us); +static int32_t drv_semaphore_v(int32_t sem_id); + +extern void nmea_messageConfig (void); +extern void drv_set_odd_flag(uint8_t flag); /*1:odd 2:even*/ + +extern int32_t drv_thread_create(uint8_t* pthread_name, uint8_t thread_prio, uint32_t thread_size, void *callback, void* pArg); + + +int32_t drv_sem_create(int32_t prj_id) +{ + key_t key; + int32_t sem_id; + union semun sem_union; + + //key = ftok(MY_IPCKEY,prj_id); + key = MY_IPCKEY + prj_id; + sem_id = semget((key_t)key, 1, IPC_CREAT); + if(-1 == sem_id) + { + UCP_PRINT_ERROR("semget error sem_id:%d err = %s!\n\r",sem_id,strerror(errno)); + return OSP_ERROR; + } + + sem_union.val = 1; + if(semctl(sem_id, 0, SETVAL, sem_union) == -1) + { + UCP_PRINT_ERROR("semctl error\n\r"); + return OSP_ERROR; + } + + return sem_id; +} + +int32_t drv_sem_create_sync(int32_t prj_id) +{ + key_t key; + int32_t sem_id; + union semun sem_union; + + //key = ftok(MY_IPCKEY,prj_id); + key = MY_IPCKEY + prj_id; + sem_id = semget((key_t)key, 1, IPC_CREAT); + if(-1 == sem_id) + { + UCP_PRINT_ERROR("semget error sem_id:%d err = %s!\n\r",sem_id,strerror(errno)); + return OSP_ERROR; + } + + sem_union.val = 0; + if(semctl(sem_id, 0, SETVAL, sem_union) == -1) + { + UCP_PRINT_ERROR("semctl error\n\r"); + return OSP_ERROR; + } + + return sem_id; +} + +int32_t drv_semaphore_p(int32_t sem_id) +{ + struct sembuf sem_p; + sem_p.sem_num = 0; + sem_p.sem_op = -1; + sem_p.sem_flg = SEM_UNDO; + + if(semop(sem_id, &sem_p, 1) == -1) + { + UCP_PRINT_ERROR("semaphore_p failed err=%s \n\r",strerror(errno)); + return OSP_ERROR; + } + + return OSP_OK; +} + +static int32_t drv_semaphore_timed_p(int32_t sem_id,int32_t timeout_us) +{ + struct sembuf sem_p; + struct timespec time; + int32_t temp = timeout_us; + + if(temp >= 1000000) + { + time.tv_sec = temp/1000/1000; + temp = temp%1000000; + } + else + { + time.tv_sec = 0; + } + + time.tv_nsec = temp*1000; + + sem_p.sem_num = 0; + sem_p.sem_op = -1; + sem_p.sem_flg = SEM_UNDO; + + if(semtimedop(sem_id, &sem_p, 1,&time) == -1) + { + UCP_PRINT_ERROR("semtimedop failed"); + return OSP_ERROR; + } + + return OSP_OK; +} + + +static int32_t drv_semaphore_v(int32_t sem_id) +{ + struct sembuf sem_b; + + sem_b.sem_num = 0; + sem_b.sem_op = 1; + sem_b.sem_flg = SEM_UNDO; + if(semop(sem_id, &sem_b, 1) == -1) + { + UCP_PRINT_ERROR("semaphore_v failed sem_id%d err = %s! \n\r",sem_id, strerror(errno)); + return OSP_ERROR; + } + return OSP_OK; +} + +int32_t set_opt(int32_t fd,int32_t nSpeed, int32_t nBits, int8_t nEvent, int32_t nStop) +{ + struct termios newtio,oldtio; + + if ( tcgetattr( fd,&oldtio) != 0) + { + perror("SetupSerial error"); + UCP_PRINT_ERROR("SetupSerial error\n\r"); + return -1; + } + + bzero( &newtio, sizeof( newtio ) ); + newtio.c_cflag |= CLOCAL | CREAD; + newtio.c_cflag &= ~CSIZE; + + switch( nBits ) + { + case 7: + newtio.c_cflag |= CS7; + break; + case 8: + newtio.c_cflag |= CS8; + break; + } + + switch( nEvent ) + { + case 'O': + newtio.c_cflag |= PARENB; + newtio.c_cflag |= PARODD; + newtio.c_iflag |= (INPCK | ISTRIP); + break; + case 'E': + newtio.c_iflag |= (INPCK | ISTRIP); + newtio.c_cflag |= PARENB; + newtio.c_cflag &= ~PARODD; + break; + case 'N': + newtio.c_cflag &= ~PARENB; + break; + } + + switch( nSpeed ) + { + case 2400: + cfsetispeed(&newtio, B2400); + cfsetospeed(&newtio, B2400); + break; + case 4800: + cfsetispeed(&newtio, B4800); + cfsetospeed(&newtio, B4800); + break; + case 9600: + cfsetispeed(&newtio, B9600); + cfsetospeed(&newtio, B9600); + break; + case 115200: + cfsetispeed(&newtio, B115200); + cfsetospeed(&newtio, B115200); + break; + default: + cfsetispeed(&newtio, B9600); + cfsetospeed(&newtio, B9600); + break; + } + + if( nStop == 1 ) + { + newtio.c_cflag &= ~CSTOPB; + } + else if ( nStop == 2 ) + { + newtio.c_cflag |= CSTOPB; + } + newtio.c_cc[VTIME] = 1; //100ms + newtio.c_cc[VMIN] = 64; //60; + tcflush(fd,TCIFLUSH); + if((tcsetattr(fd,TCSANOW,&newtio))!=0) + { + perror("com set error"); + UCP_PRINT_ERROR("com set error\n\r"); + return -1; + } + UCP_PRINT_DEBUG("set done!\n"); + return 0; +} + +static int32_t drv_tfu_uart_init(void) +{ + if(drv_uart_fd < 0) + { + drv_uart_fd = open( "/dev/ttyS2", O_RDWR); + if (-1 == drv_uart_fd) + { + perror("Can't Open Serial Port"); + UCP_PRINT_ERROR("Can't Open Serial Port\n\r"); + return OSP_ERROR; + } + } + + if(fcntl(drv_uart_fd, F_SETFL, 0)<0) + { + UCP_PRINT_ERROR("fcntl failed!\n"); + } + + if(isatty(STDIN_FILENO) == 0) + { + UCP_PRINT_ERROR("standard input is not a terminal device\n"); + } + + if(set_opt(drv_uart_fd,115200,8,'N',1) < 0) + { + perror("set_opt error"); + UCP_PRINT_ERROR("set_opt error\n\r"); + return OSP_ERROR; + } + return OSP_OK; +} + +static int32_t drv_uart_read(uint8_t *pdata, uint32_t len) +{ + int32_t read_bytes = 0; + + if(NULL == pdata) + { + return OSP_ERROR; + } + + read_bytes = read(drv_uart_fd,pdata,len); + if(read_bytes < 0) + { + // UCP_PRINT_ERROR("uart read error\n\r"); + return OSP_ERROR; + } + + return read_bytes; +} + +static int drv_tfu_uart_send (uint8_t *pdata, uint32_t len) +{ + int32_t write_count = 0; + if((NULL == pdata)|(0 == len)) + { + UCP_PRINT_ERROR("uart send para error"); + return OSP_ERROR; + } + + write_count = write(drv_uart_fd,pdata,len); + + if(write_count < len) + { + UCP_PRINT_ERROR("uart send error write_count=%d,len=%d",write_count,len); + return OSP_ERROR; + } + + return OSP_OK; +} + +int32_t drv_tfu_receiver_init(void) +{ + uint32_t i = 0; + + if(OSP_ERROR == (g_gps_uart.send_sem = drv_sem_create(g_sem_prj_id))) + { + UCP_PRINT_ERROR("TFU: create g_gps_uart.send_sem error!\n"); + return OSP_ERROR; + } + UCP_PRINT_DEBUG("g_gps_uart.send_sem=%d\n\r",g_gps_uart.send_sem); + + g_sem_prj_id++; + for(i = 0; i < GPS_SEM_NUM; ++i) + { + if(OSP_ERROR == (g_ubx_sem[i]= drv_sem_create_sync(g_sem_prj_id++))) + { + UCP_PRINT_ERROR("drv_tfu_init semBCreate error i:%d\n\r",i); + return OSP_ERROR; + } + //g_sem_prj_id++; + } + + g_gps_recv_task_id = drv_thread_create( (uint8_t *)"dgps_recv", 72, 8192, + (void *)drv_gps_recv_task, NULL); + if(OSP_ERROR == g_gps_recv_task_id) + { + UCP_PRINT_ERROR("lc98s: create GPS recv task error!\n"); + return OSP_ERROR; + } + + return OSP_OK; +} + +void drv_gps_recv_task(void) +{ + uint8_t dealRxIndex, dealCnt; + int32_t recv_cnt, i, iCnt; + uint8_t recv_buf[GPS_RX_BUF_SIZE]; + + while(1) + { + recv_cnt = drv_uart_read(recv_buf, GPS_RX_BUF_SIZE); + if (recv_cnt > 0) + { + for (i = 0;i < recv_cnt;i++) + { + if (g_rx_cnt[g_curRxIndex] >= HALF_BUFSIZE) + { + g_rx_cnt[g_curRxIndex] = 0; + } + + if ('$' == recv_buf[i]) + { + dealRxIndex = g_curRxIndex; + dealCnt = g_rx_cnt[g_curRxIndex]; + g_rx_cnt[g_curRxIndex] = 0; + g_curRxIndex ^= 1; + g_rx_buf[dealRxIndex][dealCnt] = 0; + if (printMask & PRINT_MSG) + { + printf("%s", g_rx_buf[dealRxIndex]); + } + switch(NmeaGetType((int8_t*)g_rx_buf[dealRxIndex])) + { + case ENMEA_TYPE_GGA: + NmeaDealStr((int8_t*)g_rx_buf[dealRxIndex], &gga,sizeof(gga)); + if (printMask & PRINT_GGA) + { + printf("#GGA:\r\n"); + printf("Time: %02d:%02d:%.3f\r\n", gga.hour + 8, gga.minute, gga.second); + printf("Lat: %f\r\n", gga.lat); + printf("LatH: %c\r\n", gga.latHemishere); + printf("Lon: %f\r\n", gga.lon); + printf("LonH: %c\r\n", gga.lonHemishere); + printf("Stat: %d\r\n", gga.gpsState); + printf("NumU: %d\r\n", gga.satNumber); + printf("HDOP: %.1f\r\n", gga.hdop); + printf("Alt: %f\r\n", gga.alt); + printf("DifT: %f\r\n", gga.diffTime); + printf("DifI: %d\r\n", gga.diffID); + } + nmea_messageConfig(); + break; + + case ENMEA_TYPE_GSA: + NmeaDealStr((int8_t*)g_rx_buf[dealRxIndex], &gsa, sizeof(gsa)); + if (printMask & PRINT_GSA) + { + printf("#GSA:\r\n"); + printf("Mode: %c\r\n", gsa.mode); + printf("Type: %d\r\n", gsa.type); + printf("SatU: "); + for (iCnt = 0; iCnt < 12; iCnt++) + { + if (gsa.prn[iCnt]) + { + printf("%02d ", gsa.prn[iCnt]); + } + } + printf("\r\n"); + printf("PDOP: %.1f\r\n", gsa.pdop); + printf("HDOP: %.1f\r\n", gsa.hdop); + printf("VDOP: %.1f\r\n", gsa.vdop); + } + break; + + case ENMEA_TYPE_GSV: + NmeaDealStr((int8_t*)g_rx_buf[dealRxIndex], &gsv, sizeof(gsv)); + if (printMask & PRINT_GSV) + { + printf("#GSV:\r\n"); + printf("Total:%02d\r\n", gsv.total); + printf("Numb: %02d\r\n", gsv.numb); + printf("SatV: %02d\r\n", gsv.satInView); + for (iCnt = 0; iCnt < 4; iCnt++) + { + if (gsv.prn[iCnt]) + { + printf("Sat: "); + printf("%02d ", gsv.prn[iCnt]); + printf("%02d ", gsv.elev[iCnt]); + printf("%02d ", gsv.azim[iCnt]); + printf("%02d\r\n", gsv.snr[iCnt]); + } + } + } + break; + + case ENMEA_TYPE_RMC: + NmeaDealStr((int8_t*)g_rx_buf[dealRxIndex], &rmc, sizeof(rmc)); + if (printMask & PRINT_RMC) + { + printf("#RMC:\r\n"); + printf("Time: %2d:%02d:%.3f\r\n", rmc.hour + 8, rmc.minute, rmc.second); + printf("Stat: %c\r\n", rmc.state); + printf("Lat: %f\r\n", rmc.lat); + printf("LatH: %c\r\n", rmc.latHemishere); + printf("Lon: %f\r\n", rmc.lon); + printf("LonH: %c\r\n", rmc.lonHemishere); + printf("Speed: %f\r\n", rmc.speed); + printf("Azim: %f\r\n", rmc.azim); + printf("Date: %2d %02d %02d\r\n", rmc.year,rmc.month, rmc.day); + printf("Mag: %f\r\n", rmc.magnetic); + printf("MAzim: %f\r\n", rmc.magneticAzim); + printf("Mode: %c\r\n", rmc.mode); + } + + if (printMask & PRINT_UTC) + { + time_t utc; + get_src_time(&utc); + printf("fix: %d, utc: %lu\n", get_receiver_fix_status(), utc); + } + break; + + default: + break; + } + } + + g_rx_buf[g_curRxIndex][g_rx_cnt[g_curRxIndex]] = recv_buf[i]; + g_rx_cnt[g_curRxIndex]++; + } + } + } +} + +void nmea_messageConfig (void) +{ + memset(g_tx_buf, 0, sizeof(g_tx_buf)); + strcpy((char*)g_tx_buf, "$PSTMCFGMSGL,0,1,44,0\r\n"); + drv_tfu_uart_send(g_tx_buf, strlen((char*)g_tx_buf)); + + memset(g_tx_buf, 0, sizeof(g_tx_buf)); + strcpy((char*)g_tx_buf, "$PSTMSAVEPAR\r\n"); + drv_tfu_uart_send(g_tx_buf, strlen((char*)g_tx_buf)); + + memset(g_tx_buf, 0, sizeof(g_tx_buf)); + strcpy((char*)g_tx_buf, "$PSTMSRR\r\n"); + drv_tfu_uart_send(g_tx_buf, strlen((char*)g_tx_buf)); +} + +int32_t reset_clock_module(void) +{ + return OSP_OK; +} + +int32_t get_tfu_location_info(location_info_s *locat_ptr) +{ + if(NULL == locat_ptr) + { + UCP_PRINT_ERROR("locat_ptr == NULL\n\r"); + return OSP_ERROR; + } + + return OSP_OK; +} + +int32_t get_clock_tracking_state(tracking_info_s *trk_ptr) +{ + trk_ptr = (tracking_info_s*)0; + return OSP_OK; +} + +int32_t get_receiver_fix_status() +{ + return (3 == gsa.type) ? 1 : 0; //接收机锁定状态 +} + +int32_t get_src_time(time_t* time_ptr) +{ + struct tm t; + time_t tmp_time; + + t.tm_year = rmc.year + 2000 - 1900; + t.tm_mon = rmc.month - 1; + t.tm_mday = rmc.day; + t.tm_hour = rmc.hour; + t.tm_min = rmc.minute; + t.tm_sec = (int32_t)rmc.second; + t.tm_isdst = -1; + + tmp_time = mktime(&t); + *time_ptr = tmp_time; + + return OSP_OK; +} + +int32_t drv_tfu_get_ublox_seconds(time_t* sec_ptr) +{ + return get_src_time(sec_ptr); +} + +int32_t init_clock_module(void) +{ + int32_t result = 0; + + if(1 == g_tfu_init_flag) + { + UCP_PRINT_ERROR("tfu init flag = 1"); + return OSP_ERROR; + } + else + { + result = drv_tfu_uart_init(); + if(OSP_ERROR == result) + { + UCP_PRINT_ERROR("uart init error\n\r"); + return OSP_ERROR; + } + + /*tracking后释放给OM，计算帧号*/ + if(OSP_ERROR == (g_tfu_to_time_sem = drv_sem_create(g_sem_prj_id))) + { + UCP_PRINT_ERROR("g_tfu_to_time_sem create error\n\r"); + return OSP_ERROR; + } + UCP_PRINT_DEBUG("g_tfu_to_time_sem=%d\n\r",g_tfu_to_time_sem); + + g_sem_prj_id++; + if(OSP_ERROR == (g_tfu_sync_sem = drv_sem_create_sync(g_sem_prj_id))) + { + UCP_PRINT_ERROR("g_tfu_sync_sem create error\n\r"); + return OSP_ERROR; + } + g_sem_prj_id++; + UCP_PRINT_DEBUG("g_tfu_sync_sem=%d\n\r",g_tfu_sync_sem); + + g_tfu_init_flag = 1; + return OSP_OK; + } +} + diff --git a/driver/tfu/lc98s/src/nmea.c b/driver/tfu/lc98s/src/nmea.c new file mode 100644 index 0000000..44489ed --- /dev/null +++ b/driver/tfu/lc98s/src/nmea.c @@ -0,0 +1,417 @@ +/** +* @file nmea.c +* @brief This is the nmea file. +* @details +* @author BohengLin +* @date 2014.1.21 +* @version V0.0.1 +* @par Copyright (c): Company +* @par History: +* V0.0.1: BohengLin,2014.1.21,build\n +*/ + +#include +#include +#include +#include + +#include "nmea.h" + +#define TRUE 1 +#define FALSE 0 + +#define MAX_NMEA_BYTES 512 + +static int8_t NmeaCheck(int8_t *inStr) +{ + uint32_t iCnt; + uint8_t sum, check, checkStr[3]; + + iCnt = 1; + sum = 0; + + while (iCnt < MAX_NMEA_BYTES) + { + if (('*' == *(int8_t*)(inStr + iCnt))) + { + break; + } + + sum ^= *(int8_t*)(inStr + iCnt); + iCnt++; + } + + checkStr[0] = *(int8_t*)(inStr + iCnt + 1); + checkStr[1] = *(int8_t*)(inStr + iCnt + 2); + checkStr[2] = '\0'; + + check = (uint8_t)(strtol((const char*)checkStr,NULL,16) & 0xFF); + + return (check == sum) ? TRUE : FALSE; +} + +static uint32_t NmeaGetValue(int8_t *inStr,uint32_t start, + int8_t *outStr,uint32_t outSize) +{ + uint32_t pos, len, iCnt; + int8_t tmp; + + pos = 0; + iCnt = 0; + tmp = 0; + len = (uint32_t)strlen((const char*)inStr); + memset(outStr,0,outSize); + + while ((',' != tmp) && (pos < len)) + { + tmp = *(int8_t*)(inStr + start + pos); + + if (pos < outSize) + { + if (' ' != tmp) + { + *(int8_t*)(outStr + iCnt) = tmp; + iCnt++; + } + } + else + { + return 0; + } + + pos++; + } + + *(int8_t*)(outStr + pos - 1) = '\0'; + + return (start + pos); +} + +static int8_t NmeaDealGGA(struct tGGA *gga,int8_t *str) +{ + uint32_t n; + int8_t buf[125]; + + n = NmeaGetValue(str,7,buf,sizeof(buf)); + gga->hour = (buf[0] - '0')*10 + (buf[1] - '0'); + gga->minute = (buf[2] - '0')*10 + (buf[3] - '0'); + gga->second = atof((const char*)&buf[4]); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gga->lat = atof((const char*)buf); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gga->latHemishere = buf[0]; + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gga->lon = atof((const char*)buf); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gga->lonHemishere = buf[0]; + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gga->gpsState = buf[0] - '0'; + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gga->satNumber = atoi((const char*)buf); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gga->hdop = atof((const char*)buf); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gga->alt = atof((const char*)buf); + + // M + n = NmeaGetValue(str,n,buf,sizeof(buf)); + n = NmeaGetValue(str,n,buf,sizeof(buf)); + // M + n = NmeaGetValue(str,n,buf,sizeof(buf)); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gga->diffTime = atof((const char*)buf); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gga->diffID = atoi((const char*)buf); + + return TRUE; +} + +static int8_t NmeaDealGSA(struct tGSA *gsa,int8_t *str) +{ + uint32_t n, iCnt; + int8_t buf[125]; + + n = NmeaGetValue(str,7,buf,sizeof(buf)); + gsa->mode = buf[0]; + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gsa->type = buf[0] - '0'; + + for (iCnt = 0; iCnt < 12; iCnt++) + { + buf[0] = 0; + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gsa->prn[iCnt] = atoi((const char*)buf); + } + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gsa->pdop = atof((const char*)buf); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gsa->hdop = atof((const char*)buf); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gsa->vdop = atof((const char*)buf); + + return TRUE; +} + +static int8_t NmeaDealGSV(struct tGSV *gsv,int8_t *str) +{ + uint32_t n, iCnt; + int8_t buf[125]; + + n = NmeaGetValue(str,7,buf,sizeof(buf)); + gsv->total = atoi((const char*)buf); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gsv->numb = atoi((const char*)buf); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gsv->satInView = atoi((const char*)buf); + + for (iCnt = 0; iCnt < 4; iCnt++) + { + buf[0] = 0; + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gsv->prn[iCnt] = atoi((const char*)buf); + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gsv->elev[iCnt] = atof((const char*)buf); + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gsv->azim[iCnt] = atof((const char*)buf); + n = NmeaGetValue(str,n,buf,sizeof(buf)); + gsv->snr[iCnt] = (uint8_t)atol((const char*)buf); + } + + return TRUE; +} + +int8_t NmeaDealRMC(struct tRMC *rmc,int8_t *str) +{ + uint32_t n; + int8_t buf[125]; + + n = NmeaGetValue(str,7,buf,sizeof(buf)); + rmc->hour = (buf[0] - '0')*10 + (buf[1] - '0'); + rmc->minute = (buf[2] - '0')*10 + (buf[3] - '0'); + rmc->second = (buf[4] - '0')*10 + (buf[5] - '0'); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + rmc->state = buf[0]; + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + rmc->lat = atof((const char*)buf); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + rmc->latHemishere = buf[0]; + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + rmc->lon = atof((const char*)buf); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + rmc->lonHemishere = buf[0]; + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + rmc->speed = atof((const char*)buf); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + rmc->azim = atof((const char*)buf); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + rmc->day = (buf[0] - '0')*10 + (buf[1] - '0'); + rmc->month = (buf[2] - '0')*10 + (buf[3] - '0'); + rmc->year = (buf[4] - '0')*10 + (buf[5] - '0'); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + rmc->magnetic = atof((const char*)buf); + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + rmc->magneticAzim = buf[0]; + + n = NmeaGetValue(str,n,buf,sizeof(buf)); + rmc->mode = buf[0]; + + return TRUE; +} + +int8_t NmeaGetType(int8_t *inStr) +{ + uint16_t magic1, magic2, magic3; + + magic1 = *(int8_t*)(inStr + 3); + magic2 = *(int8_t*)(inStr + 4); + magic3 = *(int8_t*)(inStr + 5); + + if ('G' == magic1) + { + if ('G' == magic2) + { + return ENMEA_TYPE_GGA; + } + else if ('S' == magic2) + { + if ('A' == magic3) + { + return ENMEA_TYPE_GSA; + } + else if ('V' == magic3) + { + return ENMEA_TYPE_GSV; + } + } + } + else if ('R' == magic1) + { + return ENMEA_TYPE_RMC; + } + + return ENMEA_TYPE_INVALID; +} + +int8_t NmeaDealStr(int8_t *inStr, void *outStr, uint32_t outSize) +{ + uint16_t magic1, magic2, magic3; + + if (FALSE == NmeaCheck(inStr)) + { + printf("Check err\r\n"); + return ENMEA_TYPE_INVALID; + } + + magic1 = *(int8_t*)(inStr + 3); + magic2 = *(int8_t*)(inStr + 4); + magic3 = *(int8_t*)(inStr + 5); + + if ('G' == magic1) + { + if ('G' == magic2) + { + if (outSize >= sizeof(struct tGGA)) + { + NmeaDealGGA(outStr, inStr); + return ENMEA_TYPE_GGA; + } + } + else if ('S' == magic2) + { + if ('A' == magic3) + { + if (outSize >= sizeof(struct tGSA)) + { + NmeaDealGSA(outStr,inStr); + return ENMEA_TYPE_GSA; + } + } + else if ('V' == magic3) + { + if (outSize >= sizeof(struct tGSV)) + { + NmeaDealGSV(outStr, inStr); + return ENMEA_TYPE_GSV; + } + } + } + } + else if ('R' == magic1) + { + if (outSize >= sizeof(struct tRMC)) + { + NmeaDealRMC(outStr, inStr); + return ENMEA_TYPE_RMC; + } + } + + return ENMEA_TYPE_INVALID; +} + +#if PRJ_NMEA_TEST + +void NmeaTest(void) +{ + uint32_t iCnt; + struct tGGA gga; + struct tGSA gsa; + struct tGSV gsv; + struct tRMC rmc; + int8_t ggaDate[] = "$GPGGA,020751.147,3413.4754,N,10852.8330,E,1,05,2.8,309.3,M,-28.4,M,,0000*7B\r\n"; + int8_t gsaDate[] = "$GPGSA,A,3,03,06,08,09,02,,,,,,,,3.0,2.8,1.0*3C\r\n"; + int8_t gsvDate[] = "$GPGSV,2,1,05,06,85,219,48,02,38,223,38,03,49,177,44,08,65,127,46*71\r\n"; + int8_t rmcDate[] = "$GPRMC,020751.147,A,3413.4754,N,10852.8330,E,0.42,67.92,251213,,,A*56\r\n"; + + //NmeaDealGGA(&gga,ggaDate); + NmeaDealStr(ggaDate,&gga,sizeof(gga)); + NmeaDealStr(gsaDate,&gsa,sizeof(gsa)); + NmeaDealStr(gsvDate,&gsv,sizeof(gsv)); + NmeaDealStr(rmcDate,&rmc,sizeof(rmc)); + + NmeaCheck(ggaDate); + + printf("Time: %2d:%02d:%2f\r\n",gga.hour + 8, gga.minute, gga.second); + printf("Lat: %f\r\n",gga.lat); + printf("LatH: %c\r\n",gga.latHemishere); + printf("Lon: %f\r\n",gga.lon); + printf("LonH: %c\r\n",gga.lonHemishere); + printf("Stat: %d\r\n",gga.gpsState); + printf("NumU: %d\r\n",gga.satNumber); + printf("HDOP: %f\r\n",gga.hdop); + printf("Alt: %f\r\n",gga.alt); + printf("DifT: %f\r\n",gga.diffTime); + printf("DifI: %d\r\n",gga.diffID); + + printf("Mode: %c\r\n",gsa.mode); + printf("Type: %d\r\n",gsa.type); + printf("SatU: "); + for (iCnt = 0; iCnt < 12; iCnt++) + { + if (gsa.prn[iCnt]) + { + printf("%02d ",gsa.prn[iCnt]); + } + } + printf("\r\n"); + printf("PDOP: %f\r\n",gsa.pdop); + printf("HDOP: %f\r\n",gsa.hdop); + printf("VDOP: %f\r\n",gsa.vdop); + + printf("Total:%2d\r\n",gsv.total); + printf("Numb: %2d\r\n",gsv.numb); + printf("SatV: %2d\r\n",gsv.satInView); + for (iCnt = 0; iCnt < 4; iCnt++) + { + if (gsv.prn[iCnt]) + { + printf("Sat: "); + printf("%02d ",gsv.prn[iCnt]); + printf("%2f ",gsv.elev[iCnt]); + printf("%2f ",gsv.azim[iCnt]); + printf("%2f\r\n",gsv.snr[iCnt]); + } + } + + printf("Time: %2d:%02d:%02d\r\n",rmc.hour + 8,rmc.minute,rmc.second); + printf("Stat: %c\r\n",rmc.state); + printf("Lat: %f\r\n",rmc.lat); + printf("LatH: %c\r\n",rmc.latHemishere); + printf("Lon: %f\r\n",rmc.lon); + printf("LonH: %c\r\n",rmc.lonHemishere); + printf("Speed: %f\r\n",rmc.speed); + printf("Azim: %f\r\n",rmc.azim); + printf("Date: %2d %02d %02d\r\n",rmc.year,rmc.month,rmc.day); + printf("Mag: %f\r\n",rmc.magnetic); + printf("MAzim: %f\r\n",rmc.magneticAzim); + printf("Mode: %c\r\n",rmc.mode); + + +} + +#endif diff --git a/driver/tfu/lc98s/src/nmea.h b/driver/tfu/lc98s/src/nmea.h new file mode 100644 index 0000000..fc04682 --- /dev/null +++ b/driver/tfu/lc98s/src/nmea.h @@ -0,0 +1,142 @@ +/** +* @file nmea.h +* @brief This is the nmea file. +* @details +* @author BohengLin +* @date 2014.1.21 +* @version V0.0.1 +* @par Copyright (c): Company +* @par History: +* V0.0.1: BohengLin,2014.1.21,build\n +*/ + +#ifndef _NMEA_H_ +#define _NMEA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +enum +{ + ENMEA_TYPE_INVALID = 0, \ + ENMEA_TYPE_GGA = 1, \ + ENMEA_TYPE_GSA, \ + ENMEA_TYPE_GSV, \ + ENMEA_TYPE_RMC +}; + +/** +$GPGGA,<1>,<2>,<3>,<4>,<5>,<6>,<7>,<8>,<9>,M,<10>,M,<11>,<12>*hh +<1> UTC time，hhmmss (hour,minute,second) +<2> latitude ddmm.mmmm (degree,minute) +<3> hemishere of latitude (N or S) +<4> longitude dddmm.mmmm(degree,minute) +<5> hemishere of longitude (E or W) +<6> GPS state (0 = no fixed，1 = no diff，2 = diff，6 = estimate) +<7> number of sat(00~12) +<8> HDOP (0.5~99.9) +<9> altitude height(-9999.9~99999.9) +<10> 地球椭球面相对大地水准面的高度 +<11> time of diff +<12> ID of diff station ( 0000~1023) +*/ +struct tGGA +{ + int8_t hour; + int8_t minute; + double second; + double lat; + double lon; + int8_t latHemishere; + int8_t lonHemishere; + int8_t gpsState; + int8_t satNumber; + double hdop; + double alt; + double diffTime; + uint16_t diffID; +}; + +/** +<1> Mode M = manual A = auto +<2> Type 1 = No fix 2 = 2D 3 = 3D +<3> PRN Sat in use(01~32) +<4> PDOP 0.5~99.9 +<5> HDOP 0.5~99.9 +<6> VDOP 0.5~99.9 +*/ +struct tGSA +{ + int8_t mode; + int8_t type; + int8_t prn[12]; + double pdop; + double hdop; + double vdop; +}; + +/** +<1> total of GSV +<2> Numb of GSV +<3> Sat in view 0~12 +<4> PRN +<5> Elevation 00~90 degree +<6> Azimuth 000~359 degree +<7> SNR 00~99dB +*/ +struct tGSV +{ + int8_t total; + int8_t numb; + uint16_t satInView; + int8_t prn[4]; + uint16_t elev[4]; + uint16_t azim[4]; + int8_t snr[4]; +}; + +/** +<1> UTC time，hhmmss (hour,minute,second) +<2> state A = value V = invalid +<3> latitude ddmm.mmmm (degree,minute) +<4> hemishere of latitude (N or S) +<5> longitude dddmm.mmmm(degree,minute) +<6> hemishere of longitude (E or W) +<7> speed 000.0~999.9 +<8> Azimuth 000~359 degree +<9> UTC date，ddmmyy (day,month,year) +<10> magnetic declination 000.0~180.0 +<11> The direction of magnetic declination, E or W +<12> mode A = self D = diff E = estimate N= invalid +*/ +struct tRMC +{ + int8_t hour; + int8_t minute; + double second; + double lat; + double lon; + int8_t latHemishere; + int8_t lonHemishere; + double speed; + double azim; + int8_t state; + int8_t year; + int8_t month; + int8_t day; + double magnetic; + double magneticAzim; + int8_t mode; +}; + +int8_t NmeaGetType(int8_t *inStr); +int8_t NmeaDealStr(int8_t *inStr,void *outStr,uint32_t outSize); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/driver/tfu/main/src/main.c b/driver/tfu/main/src/main.c new file mode 100644 index 0000000..a44e737 --- /dev/null +++ b/driver/tfu/main/src/main.c @@ -0,0 +1,592 @@ +// +FHDR------------------------------------------------------------ +// Copyright (c) 2022 SmartLogic. +// ALL RIGHTS RESERVED +// ----------------------------------------------------------------- +// Filename : main.c +// Author : xianfeng.du +// Created On : 2022-06-25 +// Last Modified : +// ----------------------------------------------------------------- +// Description: +// +// +// -FHDR------------------------------------------------------------ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ucp_printf.h" +#include "stc_drv_api.h" +#include "stc_drv.h" +#include "ublox_drv.h" + +#define MAX_PARA_NUM 4 + +#define CP_GPIO1_REG_BASE_ADDR (0x04D10000) //CP_GPIO1模块基地址 +#define CP_GPIO1_REG_LEN (0x8000) + +#define LOCK_8A34002 0x01 +#define UNLOCK_8A34002 0x00 + +#define STC_HOLD_OVER_CNT 90 //S +#define STC_DISABLE_CNT 86400 //3600*24 + +#define TOD_LOCK_THRESHOLD 20 //0x1400000000UL //20ns +#define MAX_PP1S_INTERVAL 2700000000UL +#define FRAME_NUM_MASK 1023 +#define SECOND2FRAMENUM 100 + +uint32_t *g_8a34002_lock_ptr = NULL; + +time_t g_sys_time; +int32_t g_hscc_dump_task_id = -1; +int32_t g_stc_sync_task_id = -1; + +static uint64_t get_arm_cycle() +{ + uint64_t cycle; + + asm volatile("mrs %0, pmccntr_el0" : "=r" (cycle)); + + return cycle; +} + +uint32_t get_8a34002_lock_status() +{ + return (*g_8a34002_lock_ptr & BIT30); +} + +int32_t get_sys_time(time_t* time_ptr) +{ + if(NULL == time_ptr) + { + UCP_PRINT_ERROR("tfu: get_sys_time error!"); + return OSP_ERROR; + } + *time_ptr = g_sys_time; + + return OSP_OK; +} + +uint64_t stc_update_sync_state_task() +{ + int32_t ret = 0; + //uint32_t ex_pp1s_irq_cnt = 0; + uint32_t jitter_idx; + time_t sec_count; + static uint32_t sync_flag = 0; + static uint32_t jitter_num = 0; + static uint32_t jitter_mem[4] = {0,0,0,0}; + static uint64_t last_cycle = 0; + uint64_t current_cycle = 0; + uint64_t pp1s_interval = 0; + uint32_t lock_flag = 0; + int32_t phase_diff; + stc_state_s* stc_state_ptr = get_stc_state(); + arm_stc_regs *stc_regs_ptr = get_stc_reg_base(); + /*uint32_t tod_s = 0; + uint64_t tod_t = 0; + uint32_t stc_cnt = 0;*/ + while(1) + { + ret = stc_wait_for_expps(); //pend + if(STC_OK != ret) + { + UCP_PRINT_ERROR("stc wait for 1PPS_IN interrupt error\n"); + continue; + } + + /*tod_s = stc_regs_ptr->tod_reg_tod_lo; + tod_t = ((stc_regs_ptr->tod_reg_tod_mi & 0xffff) << 16) | (tod_s >> 16); + tod_s = stc_regs_ptr->tod_reg_tod_hi; + stc_cnt = read_stc_local_timer(); + UCP_PRINT_DEBUG("tod_t = %ld,stc_cnt = %d",tod_t,stc_cnt);*/ + + g_sys_time++; + //UCP_PRINT_DEBUG("ex_pp1s_irq_cnt = %d,g_sys_time = %ld,sec_count = %ld",ex_pp1s_irq_cnt,g_sys_time,sec_count); + lock_flag = get_8a34002_lock_status();//read status of 8A34002:lock + //stc_adjust_frequency(); + if(lock_flag) //locked + { + phase_diff = stc_adjust_phase(TOD_LOCK_THRESHOLD); + UCP_PRINT_DEBUG("diff_ns = %d,tracking_cnt = %d,holdover_cnt = %d\n",phase_diff,stc_state_ptr->phase.tracking_cnt,stc_state_ptr->phase.holdover_cnt); + + if(EX_SYNCE == stc_state_ptr->hscc_dump_src) + { + stc_adjust_frequency(); + } + } + else //unlock + { + if(CLK_TRACKING == stc_state_ptr->state) + { + if(STC_HOLD_OVER_CNT < ++stc_state_ptr->phase.holdover_cnt) + { + stc_state_ptr->phase.holdover_cnt = STC_HOLD_OVER_CNT; + stc_state_ptr->phase.tracking_cnt = 0; + stc_state_ptr->state = CLK_HOLD_OVER; + UCP_PRINT_DEBUG("change from LOCK to HOLDOVER!!"); + } + } + else if(CLK_HOLD_OVER == stc_state_ptr->state) + { + if(STC_DISABLE_CNT < ++stc_state_ptr->phase.disable_cnt) + { + stc_state_ptr->phase.disable_cnt = STC_DISABLE_CNT; + stc_state_ptr->state = CLK_DISABLE; + UCP_PRINT_DEBUG("change to CLK_DISABLE!!"); + sync_flag = 0; + } + } + } + + current_cycle = get_arm_cycle(); + pp1s_interval = current_cycle - last_cycle; + last_cycle = current_cycle; + + /*maintain time*/ + usleep(200000); + if(GNSS_1PPS_IN == stc_state_ptr->pp1s_src) + { + lock_flag = get_receiver_fix_status(); + ret = get_src_time(&sec_count); + if(OSP_ERROR == ret) + { + //UCP_PRINT_ERROR("stc get gnss second error"); + //return OSP_ERROR; + continue; + } + } + else if(GMAC0_1PPS_IN == stc_state_ptr->pp1s_src) + { + sec_count = get_gmac_src_time(); + } + else if(TMAC_1PPS_IN == stc_state_ptr->pp1s_src) + { + sec_count = get_tmac_src_time(); + } + else + { + //return OSP_ERROR; + continue; + } + /*tod_s = stc_regs_ptr->tod_reg_tod_lo; + tod_s = stc_regs_ptr->tod_reg_tod_mi; + tod_t = stc_regs_ptr->tod_reg_tod_hi; + tod_t <<= 16; + tod_t |= (tod_s >> 16); + UCP_PRINT_DEBUG("g_sys_time = %ld,sec_count = %ld,tod_t = %ld",g_sys_time,sec_count,tod_t);*/ + //UCP_PRINT_LOG("g_sys_time = %ld,sec_count = %ld,cycle = %ld",g_sys_time,sec_count,pp1s_interval); + UCP_PRINT_DEBUG("g_sys_time = %ld,sec_count = %ld",g_sys_time,sec_count); + + if(sync_flag) + { + if(1 == sync_flag) + { + sync_flag = 2; + stc_regs_ptr->tod_reg_config |= BIT4; //set tod_incr_en,TOD second auto add + } + + if(g_sys_time == sec_count) + { + if((CLK_TRACKING == stc_state_ptr->state) && (pp1s_interval < MAX_PP1S_INTERVAL)) + { + set_ape_preset_value(((g_sys_time + 1) * SECOND2FRAMENUM) & FRAME_NUM_MASK); + //stc_adjust_sniffer_phase(sec_count); //test + } + + /*-- clear jitter count --*/ + jitter_num = 0; + UCP_PRINT_LOG("g_sys_time=sec_count,sec_count=%ld,g_sys_time=%ld",sec_count,g_sys_time); + } + else + { + /* --get clock source lock state --*/ + if(lock_flag) /*1:lock 0:unlock*/ + { + /*-- save time jump record -- */ + if(abs(g_sys_time - sec_count) > GPS_TIME_JUMP_20MIN) + { + UCP_PRINT_DEBUG("maintain jump 20 min"); + } + else + { + /*-- if jitter success, adjust g_sys_time --*/ + jitter_idx = jitter_num & 0x3; + jitter_mem[jitter_idx] = sec_count; + UCP_PRINT_DEBUG("jitter_num = %d,sec_count = %ld,g_sys_time = %ld",jitter_num,sec_count,g_sys_time); + if((2 == jitter_idx)/*continues gps second,2 second interval*/ + && (1 == (jitter_mem[2] - jitter_mem[1])) + && (1 == (jitter_mem[1] - jitter_mem[0]))) + { + g_sys_time = sec_count; + UCP_PRINT_DEBUG("g_sys_time(PP2S) calibration!jitter_num=%d",jitter_num); + UCP_PRINT_DEBUG("sec_count1=%ld,g_sys_time1=%ld",sec_count,g_sys_time); + jitter_num = 0; + memset(jitter_mem, 0, sizeof(jitter_mem)); + } + else + { + jitter_num++; + } + } + } + else + { + UCP_PRINT_ERROR("tfu: clk src unlock, can not maintain time.\n"); + } + } + } + else if(0 == sync_flag) + { + if(CLK_TRACKING == stc_state_ptr->state) + { + sync_flag = 1; + stc_state_ptr->pesudo_flag = ZERO_FLAG; + g_sys_time = sec_count; + set_su_reg(g_sys_time + 1); //set tod su reg + set_sync_status_to_ape(1); //set locked flag to ape + UCP_PRINT_DEBUG("stc tracking ok !!!!!! maintain g_sys_time:%ld\n",g_sys_time); + } + } + } + return STC_OK; +} + +uint64_t stc_hscc_dump_task() +{ + //uint32_t hscc_dump_irq_cnt = 0; + int32_t ret = 0; + while(1) + { + ret = stc_wait_for_hscc(); //pend + if(STC_OK != ret) + { + UCP_PRINT_ERROR("stc wait for HSCC_DUMP interrupt error\n"); + //return LOGIC_ERROR1; + continue; + } + + stc_adjust_frequency(); + } + return STC_OK; +} + +#if 0 +uint64_t stc_tod_1pps_task() +{ + uint32_t jitter_idx,tod_1pps_irq_cnt; + int32_t ret = 0; + time_t sec_count; + static uint32_t sync_flag = 0; + static uint32_t jitter_num = 0; + static uint32_t jitter_mem[4] = {0,0,0,0}; + + ret = read(g_stc_fd, &tod_1pps_irq_cnt, STC_TOD_1PPS); //pend + if(STC_OK != ret) + { + UCP_PRINT_ERROR("stc wait for interrupt error\n"); + return LOGIC_ERROR1; + } + + g_sys_time++; + UCP_PRINT_DEBUG("g_sys_time = %#lx,sync_flag = %d,irq = %d",g_sys_time,sync_flag,tod_1pps_irq_cnt); + usleep(150000); + ret = drv_tfu_get_ublox_seconds(&sec_count); + if(OSP_ERROR == ret) + { + UCP_PRINT_ERROR("stc get ublox second error"); + return OSP_ERROR; + } + + if(1 == sync_flag) + { + if(g_sys_time == sec_count) + { + /*-- clear jitter count --*/ + jitter_num = 0; + UCP_PRINT_LOG("g_sys_time=sec_count,sec_count=%ld,g_sys_time=%ld",sec_count,g_sys_time); + } + else + { + /* --get gps lock state --*/ + if(get_receiver_fix_status()) /*1:lock 0:unlock*/ + { + /*-- save time jump record -- */ + if(abs(g_sys_time - sec_count) > GPS_TIME_JUMP_20MIN) + { + UCP_PRINT_DEBUG("maintain jump 20 min"); + } + else + { + /*-- if jitter success, adjust g_sys_time --*/ + jitter_idx = jitter_num & 0x3; + jitter_mem[jitter_idx] = sec_count; + UCP_PRINT_DEBUG("jitter_num = %d,sec_count = %ld,g_sys_time = %ld",jitter_num,sec_count,g_sys_time); + if((2 == jitter_idx)/*continues gps second,2 second interval*/ + && (1 == (jitter_mem[2] - jitter_mem[1])) + && (1 == (jitter_mem[1] - jitter_mem[0]))) + { + g_sys_time = sec_count; + UCP_PRINT_DEBUG("g_sys_time(PP2S) calibration!jitter_num=%d",jitter_num); + UCP_PRINT_DEBUG("sec_count1=%ld,g_sys_time1=%ld",sec_count,g_sys_time); + jitter_num = 0; + memset(jitter_mem, 0, sizeof(jitter_mem)); + } + else + { + jitter_num++; + } + } + } + else + { + UCP_PRINT_ERROR("tfu: clk src unlock, can not maintain time.\n"); + } + } + } + else if(0 == sync_flag) + { + if(CLK_TRACKING == stc_state_ptr->state) + { + sync_flag = 1; + g_sys_time = sec_count; + UCP_PRINT_DEBUG("maintain g_sys_time:%ld",g_sys_time); + } + } + return OSP_OK; +} +#endif + +int32_t drv_thread_create(uint8_t* pthread_name, uint8_t thread_prio, uint32_t thread_size, void *callback, void* pArg) +{ + + pthread_t thread_id; + pthread_attr_t stthread_attr; /*线程属性*/ + struct sched_param stprior_param; + int32_t result = 0; + + result = pthread_attr_init(&stthread_attr); + if (STC_OK != result) + { + UCP_PRINT_ERROR(" pthread_attr_init() fail return = %d, err = %s!\n", result, strerror(errno)); + return LOGIC_ERROR1; + } + + result = pthread_attr_setinheritsched(&stthread_attr, PTHREAD_EXPLICIT_SCHED); + if (STC_OK != result) + { + UCP_PRINT_ERROR("Failed. pthread_attr_setinheritsched() return = %d, err = %s!\n", result, strerror(errno)); + return LOGIC_ERROR2; + } + + + result = pthread_attr_setschedpolicy(&stthread_attr, SCHED_RR); + if (STC_OK != result) + { + UCP_PRINT_ERROR("Failed. pthread_attr_setschedpolicy() return = %d, err = %s!\n", result, strerror(errno)); + return LOGIC_ERROR3; + } + + result = pthread_attr_setscope(&stthread_attr, PTHREAD_SCOPE_SYSTEM); + if (STC_OK != result) + { + UCP_PRINT_ERROR(" Failed. pthread_attr_setscope() return = %d, err = %s!\n", result, strerror(errno)); + return LOGIC_ERROR4; + } + + result = pthread_attr_setdetachstate(&stthread_attr, PTHREAD_CREATE_DETACHED); + if (STC_OK != result) + { + UCP_PRINT_ERROR(" Failed. pthread_attr_setdetachstate() return = %d, err = %s!\n", result, strerror(errno)); + return LOGIC_ERROR5; + } + + + + result = pthread_attr_getschedparam(&stthread_attr, &stprior_param); + if (STC_OK != result) + { + UCP_PRINT_ERROR("Failed. pthread_attr_getschedparam() return = %d, err = %s!\n", result, strerror(errno)); + return LOGIC_ERROR6; + } + + stprior_param.sched_priority = thread_prio; + result = pthread_attr_setschedparam(&stthread_attr, &stprior_param); + if (STC_OK!= result) + { + UCP_PRINT_ERROR("Failed. pthread_attr_setschedparam() return = %d, err = %s!\n", result, strerror(errno)); + return LOGIC_ERROR7; + } + + /*result = pthread_attr_setstacksize(&stthread_attr, thread_size); + if (STC_OK != result) + { + UCP_PRINT_ERROR(" Failed. pthread_attr_setstacksize() return = %d, err = %s!\n", result, strerror(errno)); + return LOGIC_ERROR8; + }*/ + + result = pthread_create(&thread_id, &stthread_attr, callback, pArg); + if (STC_OK != result) + { + UCP_PRINT_ERROR("[GalTaskCreate]: Failed. pthread_create() return = %d, err = %s!\n", result, strerror(errno)); + return LOGIC_ERROR9; + } + + result = pthread_attr_destroy(&stthread_attr); + if (STC_OK != result) + { + UCP_PRINT_ERROR(" Failed. pthread_attr_destroy() return = %d, err = %s!\n", result, strerror(errno)); + return LOGIC_ERROR10; + } + + return thread_id; +} + + +int32_t main(int32_t argc, char* argvp[]) +{ + void *gpio_regs_ptr = NULL; // + int32_t g_main_mem_fd = -1; + + UCP_PRINT_DEBUG("Hello world from A72."); + + cpu_set_t mask; + CPU_ZERO(&mask); + CPU_SET(0,&mask); + sched_setaffinity(0,sizeof(cpu_set_t),&mask); + + int32_t args[MAX_PARA_NUM] = {0,0,0,0}; + uint32_t count = argc - 1; + if(count > MAX_PARA_NUM) { + UCP_PRINT_ERROR("parameter number[%d] error",count); + return -1; + } + + for (uint32_t i = 0; i < count; i++) { + args[i] = (int32_t)strtoul(argvp[i+1],NULL,0); + } + + + g_main_mem_fd = open("/dev/mem", O_RDWR|O_SYNC); + if(g_main_mem_fd < 0) + { + UCP_PRINT_ERROR("open /dev/mem error"); + return LOGIC_ERROR1; + } + + if(0 == args[0]) //gnss 配置接收机 + { + + UCP_PRINT_DEBUG("entered gps testmode."); + if(0 != init_clock_module()) + { + UCP_PRINT_ERROR("Init clock_module error!!"); + return -2; + } + + if(0 != drv_tfu_receiver_init()) + { + UCP_PRINT_ERROR("Init ublox error!!"); + //return -2; + } + } + + if(0 != init_stc()) + { + UCP_PRINT_ERROR("Init stc error!!"); + return -3; + } + +#ifdef EVMYFT + gpio_regs_ptr = get_ap_gpio_reg_base(); + *(uint32_t *)(gpio_regs_ptr + AP_GPIO_REG_LEN + 0x18c) |= (BIT2 | BIT3); //ap_gpiob30 in +#else + uint32_t *rf_lvds_pmux1_reg_ptr = NULL; //8a34002 cp_gpiob30 + + if(rf_lvds_pmux1_reg_ptr == NULL) + { + rf_lvds_pmux1_reg_ptr = (uint32_t *)mmap(NULL,0x1000, PROT_READ|PROT_WRITE, MAP_SHARED, + g_main_mem_fd, 0x04da0000); + if(-1 == (int64_t)rf_lvds_pmux1_reg_ptr) + { + UCP_PRINT_ERROR("mmap lvds gpiob30(8a34002 lock status) pinmux error!! return = %ld\n",(uint64_t)rf_lvds_pmux1_reg_ptr); + return LOGIC_ERROR5; + } + else + { + *(rf_lvds_pmux1_reg_ptr + 0x26) |= (BIT28 | BIT29); //0x04da0098 cp_gpiob30 pad 8a34002 lock + munmap((void*)rf_lvds_pmux1_reg_ptr,0x1000); + } + } + + if(gpio_regs_ptr == NULL) //cp_gpiob30 0x04D10000 + { + gpio_regs_ptr = mmap(NULL, CP_GPIO1_REG_LEN, PROT_READ|PROT_WRITE, MAP_SHARED, + g_main_mem_fd, CP_GPIO1_REG_BASE_ADDR); + if(-1 == (int64_t)gpio_regs_ptr) + { + UCP_PRINT_ERROR("mmap cp_gpio1 error!! return = %ld\n",(uint64_t)gpio_regs_ptr); + return LOGIC_ERROR4; + } + } +#endif + + g_8a34002_lock_ptr = (uint32_t *)(gpio_regs_ptr + 0x54); + + g_stc_sync_task_id = drv_thread_create( (uint8_t *)"stcsynctask", 71, 8192, + (void *)stc_update_sync_state_task, NULL); + if(OSP_ERROR == g_stc_sync_task_id) + { + UCP_PRINT_ERROR("tfu: create stcsynctask error!\n"); + return LOGIC_ERROR5; + } + + g_hscc_dump_task_id = drv_thread_create( (uint8_t *)"hsccdumptask", 68, 4096, + (void *)stc_hscc_dump_task, NULL); + if(OSP_ERROR == g_hscc_dump_task_id) + { + UCP_PRINT_ERROR("stc: create hsccdumptask error!\n"); + return LOGIC_ERROR6; + } + + if(0 == args[0]) //gnss + { + set_xpps_out_source(TOD_1PPS_OUT,1); + select_xpps_in_source(GNSS_1PPS_IN); + } + else if(1 == args[0]) //GMAC 1588 + { + UCP_PRINT_DEBUG("entered GMAC 1588 testmode."); + select_xpps_in_source(GMAC0_1PPS_IN); + } + else if(2 == args[0]) //TMAC 1588 + { + UCP_PRINT_DEBUG("entered TMAC 1588 testmode."); + select_xpps_in_source(TMAC_1PPS_IN); + } + + enable_stc_irq(STC_EX_1PPS_IN); + + while (1) + { + usleep(100); + } + + close(g_main_mem_fd); + + return 0; +} + diff --git a/driver/tfu/makefile b/driver/tfu/makefile new file mode 100644 index 0000000..7718842 --- /dev/null +++ b/driver/tfu/makefile @@ -0,0 +1,167 @@ +#======================================================================================================== +# stc makefile +#FileName: makefile +#Author: xianfeng.du +#Data： 2022-08-10 +#Description: top makefile +#======================================================================================================== +VERSION = 1.00 + +OPTION ?= +ifeq ($(OPTION),GCC) + CROSS_CC ?= +else +# TOOLS ?= /opt/gcc-linaro-7.5.0-2019.12-x86_64_aarch64-linux-gnu/bin +# CROSS_CC ?= $(TOOLS)/aarch64-linux-gnu- + CROSS_CC ?= aarch64-linux-gnu- +endif + +AR = ar +CC = $(CROSS_CC)gcc +#$(info "CC=" $(CC)) + +git_id ?= $(shell git log -1 --format="%H") +commit_ts ?= $(shell git log -1 --format="%ct") +commit_time ?= $(shell date -d@$(commit_ts) +"%Y-%m-%d-%H:%M:%S") +#git_cmit ?= $(shell date +"%Y-%m-%d::%H:%M:%S") + +$(info "commit_ts=" $(commit_ts)) +$(info "commit_time=" $(commit_time)) + +DEFINES ?= TFU_VER=\"commit_id:$(git_id),commit_time:$(commit_time)\" +ifeq ($(adj_freq),yes) +DEFINES += SL_ADJ_FREQ +endif +board ?= EVMYFT +#ifeq ($(board),evb) +#DEFINES += EVB +#else +#DEFINES += EVMYFT +#endif +DEFINES += $(board) + + +#optimization level -O2 +C_OPT_FLAGS ?= -O2 + +CC_FLAGS ?= $(C_OPT_FLAGS) -Wall -g +CC_FLAGS += -Werror -Wno-unused-function +CC_FLAGS += $(foreach d,$(DEFINES),-D$(d)) +CC_FLAGS += -fPIC + +SRC_DIRS ?= ./main/src +LIB_SRC_DIRS ?= ./stc/src +ifeq ($(gps),lc98s) +SRC_DIRS += ./lc98s/src +else +SRC_DIRS += ./ublox/src +endif + +INCLUDE_DIRS ?= ./main/inc +INCLUDE_DIRS += ./stc/inc +INCLUDE_DIRS += ./ublox/inc + +LD_FLAGS ?= -lgcc -lc +LD_FLAGS += -lm -ldl -Wl,-rpath=./ +LD_FLAGS += -lpthread +LD_FLAGS += -lstc +LD_FLAGS += -rdynamic -funwind-tables -ffunction-sections + +$(info "DEFINES=" $(DEFINES)) +#$(info "lib src =" $(LIB_SRC_DIRS)) + +#Flatten files and remove the duplicate by sort +ABS_SRC_DIRS := $(foreach d,$(SRC_DIRS),$(abspath $(d))) +#$(info "abs src =" $(ABS_SRC_DIRS)) +ABS_LIB_SRC_DIRS := $(foreach d,$(LIB_SRC_DIRS),$(abspath $(d))) +#$(info "abs lib =" $(ABS_LIB_SRC_DIRS)) + +SRC_FILES := $(foreach d,$(ABS_SRC_DIRS),$(wildcard $(d)/*.c)) +#$(info "src files =" $(SRC_FILES)) +LIB_SRC_FILES := $(foreach d,$(ABS_LIB_SRC_DIRS),$(wildcard $(d)/*.c)) +#$(info "lib files =" $(LIB_SRC_FILES)) +#main.c +MAIN_DIR := ./main/src +MAIN_FILE := ./main/src/main.c + +# Allow certain files to be excluded from the build +#EXCL_SRCS ?= $(MAIN_FILE) + +# Filter source files (allow files to be excluded) +FINAL_SRCS_FILES += $(foreach f,$(SRC_FILES),$(if $(findstring $(abspath $(f)),$(abspath $(EXCL_SRCS))),,$(f))) +#$(info "FINAL_SRCS_FILES=" $(FINAL_SRCS_FILES)) + +# ============================================================================== +# Variables: Output Files +# ============================================================================== +BUILD_DIR := ./build +LIB_DIRS ?= $(BUILD_DIR) +OBJ_MAIN_DIR := $(BUILD_DIR)/main +OBJ_DIR := $(BUILD_DIR)/obj +#BIN_DIR := $(BUILD_DIR)/bin +#LIB_DIR := $(BUILD_DIR)/lib +#ELF_FILE := $(BIN_DIR)/test.elf +BIN_FILE := $(BUILD_DIR)/tfu.out +LIB_FILE := $(BUILD_DIR)/libstc.a + +OBJ_FILES += $(foreach f,$(FINAL_SRCS_FILES),$(OBJ_DIR)/$(patsubst %.c,%.o,$(notdir $(f)))) +#$(info "obj files =" $(OBJ_FILES)) +LIB_OBJ_FILES += $(foreach f,$(LIB_SRC_FILES),$(OBJ_DIR)/$(patsubst %.c,%.o,$(notdir $(f)))) +#$(info "lib obj files =" $(LIB_OBJ_FILES)) +OBJ_MAIN_FILES += $(foreach f,$(MAIN_FILE),$(OBJ_MAIN_DIR)/$(patsubst %.c,%.o,$(notdir $(f)))) + + + +# ============================================================================== +# Rules: Compilation +# ============================================================================== +define DO_BUILD_OBJ +$(2)/%.o: $(1)/%.c | $(2) + @echo "# Compiling $$< -> $$@" + $(CC) $(CC_FLAGS) -o $$@ -c $$< $(patsubst %,-I %,$(INCLUDE_DIRS)) +#OBJ_TGTS += $(foreach f,$(wildcard $(1)/*.c),$(OBJ_DIR)/$(notdir $(basename $(1)))/$(patsubst %.c,%.o,$(notdir $(f)))) +endef + +define DO_BUILD_DIR +$(1): + @echo "# Creating directory $$@" + mkdir -p $$@ +endef + +define DO_BUILD + $(eval $(call DO_BUILD_DIR,$(1))) + $(foreach d,$(sort $(2)),$(eval $(call DO_BUILD_OBJ,$(d),$(1)))) +endef + +$(eval $(call DO_BUILD,$(OBJ_DIR),$(ABS_SRC_DIRS))) +$(eval $(call DO_BUILD,$(OBJ_DIR),$(ABS_LIB_SRC_DIRS))) +$(eval $(call DO_BUILD,$(OBJ_MAIN_DIR), $(abspath $(MAIN_DIR)))) + +#$(BIN_FILE):$(OBJ_FILES) $(OBJ_MAIN_FILES) +$(BIN_FILE):$(OBJ_FILES) +# @echo "# Creating bin directory $(BIN_DIR)" +# mkdir -p $(BIN_DIR) + + @echo "# Linking objects to form $@" + $(CC) -o $@ $^ $(LD_FLAGS) $(patsubst %,-L %,$(LIB_DIRS)) +# $(CC) -o $@ $^ $(LD_FLAGS) -T$(LINK_FILE) + +$(LIB_FILE):$(LIB_OBJ_FILES) +# @echo "# Creating lib directory $(LIB_DIR)" +# mkdir -p $(LIB_DIR) + # $(info "lib obj =" $(LIB_OBJ_FILES)) + @echo "# Linking objects to form $@" + $(AR) -rcs $@ $^ +# $(CC) -shared -o $@ $^ $(LD_FLAGS) + +# ============================================================================== +# Rules: Targets +# ============================================================================== +.DEFAULT_GOAL := all +.PHONY: build lib clean +all: lib build +build: $(BIN_FILE) +lib: $(LIB_FILE) +clean: + @echo "deleted all files" + rm -rf $(BUILD_DIR) diff --git a/driver/tfu/stc/inc/stc_drv.h b/driver/tfu/stc/inc/stc_drv.h new file mode 100644 index 0000000..ef85619 --- /dev/null +++ b/driver/tfu/stc/inc/stc_drv.h @@ -0,0 +1,326 @@ +/*============================================================================== +* Copyright (c) 2011~2012, CPIT. All Rights Reserved. +* +* MODULE: STC模块驱动 +* +* FILENAME: stc.h +* +* DESCRIPTION: Source Code of STC Driver +* +* Current Version: 1.0 +* +* HISTORY: +* Date CR No Person Description +* ---------- ------------ ------ ------------- +* 2022-05-21 Li Weihua Initial version. +==============================================================================*/ +#ifndef __STC_DRV_H__ +#define __STC_DRV_H__ + +#include "typedef.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +#if 0 +#pragma align(1) /* set tight packing */ +#pragma pack(1) +#endif +/*============================================================================== + Includes and Public Data Declarations +==============================================================================*/ + +/* 包含系统文件以及定义公用数据文件 */ + + +/*============================================================================== + Include Files +==============================================================================*/ + +/* 包含本地文件 */ +/*============================================================================== + Constant / Define Declarations +==============================================================================*/ + + +/* 常量定义，并对所定义的常量进行说明 */ +/*============================================================================== + Global Constant Data Declarations +==============================================================================*/ + +/*============================================================================== + Macro Definitions +==============================================================================*/ +/* 宏定义，并对其进行简要说明 */ +#define STC_REG_BASE_ADDR (0x08568000) //STC模块基地址 +#define STC_REG_LEN (0x08000) +#define STC_LTBG_REG_OFFSET 0x1005 + +#define ECS_SUBCTRL_REG_BASE_ADDR (0x08460000) //ECS_SUBCTRL模块基地址 +#define ECS_SUBCTRL_REG_LEN (0x10000) + +#define ECS_CRG_REG_BASE_ADDR (0x08430000) //ECS_CRG模块基地址 +#define ECS_CRG_REG_LEN (0x10000) + +#define AP_GPIO_PINMUX_REG_BASE_ADDR (0x04450000) //AP_GPIO基地址:0x04450000,AP_GPIO_PINMUX模块基地址0x04458000 +#define AP_GPIO_REG_LEN (0x8000) +#define AP_GPIO_PINMUX_REG_LEN (0x10000) + +#define GMAC0_REG_BASE_ADDR (0x01a40000) //GMAC0模块基地址 +#define GMAC0_TOD_REG (0xB08) +#define GMAC0_REG_LEN (0x10000) + + +#define TMAC_REG_BASE_ADDR (0x09090000) //TMAC模块基地址 +#define TMAC0_TOD_REG (0xD08) +#define TMAC_REG_LEN (0x100000) + +#define STC_DEV_NAME "/dev/stc_dev" +#define STC_MODULE_MAGIC 'g' +#define STC_INT_CFG _IOWR(STC_MODULE_MAGIC, 0x01, uint32_t) + +#define SECOND2NS 1000000000.000001 +#define DEFAULT_RT_VALUE 0x3B9ACA0000000000UL +#define DEFAULT_RT_HALF 0x1DCD650000000000UL +#define KERNEL2USER_DELAY 9320 //9320ns +#define STC_LOCK_CNT 15 +#define SNIFFER_LOCK_THRESHOLD 20 //0x1400000000UL //20ns + + + +#define SFN_BASE_ADDR 0x0A4f2220UL //0x0A4D7220UL +#define SNIFFER_BASE_ADDR 0x0A4f2140UL +#define SHARE_MEM_BASE_ADDR 0x009D00000UL +#define SHARE_MEM_LEN 0x000800000UL + +#define BIT0 (0x00000001) +#define BIT1 (0x00000002) +#define BIT2 (0x00000004) +#define BIT3 (0x00000008) +#define BIT4 (0x00000010) +#define BIT5 (0x00000020) +#define BIT6 (0x00000040) +#define BIT7 (0x00000080) +#define BIT8 (0x00000100) +#define BIT9 (0x00000200) +#define BIT10 (0x00000400) +#define BIT11 (0x00000800) +#define BIT12 (0x00001000) +#define BIT13 (0x00002000) +#define BIT14 (0x00004000) +#define BIT15 (0x00008000) +#define BIT16 (0x00010000) +#define BIT17 (0x00020000) +#define BIT18 (0x00040000) +#define BIT19 (0x00080000) +#define BIT20 (0x00100000) +#define BIT21 (0x00200000) +#define BIT22 (0x00400000) +#define BIT23 (0x00800000) +#define BIT24 (0x01000000) +#define BIT25 (0x02000000) +#define BIT26 (0x04000000) +#define BIT27 (0x08000000) +#define BIT28 (0x10000000) +#define BIT29 (0x20000000) +#define BIT30 (0x40000000) +#define BIT31 (0x80000000) + +typedef volatile uint32_t vuint32_t; +typedef volatile uint8_t vuint8_t; + + +/*============================================================================== + Type Declarations +==============================================================================*/ + +/* 类型定义，struct、enum等，对每种类型定义作简要说明，如果是重要数据结构，要详细 + 说明 */ + +/*STC 寄存器*/ +typedef struct +{ + vuint32_t tod_reg_config; /*0*/ + vuint32_t tod_reg_int_status; /*4*/ + vuint32_t tod_reg_irq_en; /*0x8*/ + vuint32_t tod_clr; /*0xc*/ + vuint8_t reserve0[0x30]; /*0x10-0x40*/ + vuint32_t tod_reg_nf; /*0x40*/ + vuint32_t tod_reg_hscc; /*0x44*/ + vuint32_t tod_reg_nsf_init_lo; /*0x48*/ + vuint32_t tod_reg_nsf_init_hi; /*0x4c*/ + vuint32_t tod_reg_ft_lo; /*0x50*/ + vuint32_t tod_reg_ft_hi; /*0x54*/ + vuint32_t tod_reg_rt_lo; /*0x58*/ + vuint32_t tod_reg_rt_hi; /*0x5c*/ + vuint32_t tod_reg_su_lo; /*0x60*/ //TOD second lo + vuint32_t tod_reg_su_hi; /*0x64*/ //TOD second hi + vuint32_t tod_reg_nsf_1pps_lo; /*0x68*/ + vuint32_t tod_reg_nsf_1pps_hi; /*0x6c*/ + vuint32_t tod_reg_tod_lo; /*0x70*/ + vuint32_t tod_reg_tod_mi; /*0x74*/ + vuint32_t tod_reg_tod_hi; /*0x78*/ + vuint32_t reserve1; /*0x7c*/ + vuint32_t ltbg0_reg_r; /*0x80*/ + vuint32_t ltbg0_reg_n; /*0x84*/ + vuint32_t ltbg0_reg_n1; /*0x88*/ + vuint8_t reserve2[116]; /*0x8c-100*/ + vuint32_t ctw_reg_timer0_0; /*0x100*/ + vuint32_t ctw_reg_timer0_1; /*0x104*/ + vuint32_t ctw_reg_timer0_2; /*0x108*/ + vuint32_t ctw_reg_timer0_3; /*0x10c*/ + vuint32_t ctw_reg_timer1_0; /*0x110*/ + vuint32_t ctw_reg_timer1_1; /*0x114*/ + vuint32_t ctw_reg_timer1_2; /*0x118*/ + vuint32_t ctw_reg_timer1_3; /*0x11c*/ + vuint32_t ctw_reg_irq0_0; /*0x120*/ + vuint32_t ctw_reg_irq0_1; /*0x124*/ + vuint32_t ctw_reg_irq0_2; /*0x128*/ + vuint32_t ctw_reg_irq0_3; /*0x12c*/ + vuint32_t ctw_reg_irq1_0; /*0x130*/ + vuint32_t ctw_reg_irq1_1; /*0x134*/ + vuint32_t ctw_reg_irq1_2; /*0x138*/ + vuint32_t ctw_reg_irq1_3; /*0x13c*/ + vuint32_t ctw_reg_status; /*0x140*/ +}arm_stc_regs; + +#if 0 +/*输出到PAD的1PPS信号: jecs_subctrl_reg33:gnss_pps_out*/ +typedef enum +{ + GMAC0_1PPS_OUT = 0, /* gmac0 */ + GMAC1_1PPS_OUT, /* gmac1 */ + RESERVED0_1PPS_OUT, /* Reserved*/ + CPRI_GMAC_1PPS_OUT = 3, /* cpri gmac */ + TMAC_1PPS_OUT, /* tmac */ + STC_1PPS_OUT, /* stc产生的1pps */ + TOD_1PPS_OUT, /* stc产生的1pps */ + RESERVED_1PPS_OUT /* Reserved*/ +} pp1s_output_e; +#endif + +typedef enum +{ + ZERO_FLAG = 0, /*0标志*/ + TRUE_FLAG /*1 标志*/ +}clk_flag_e; + +typedef enum +{ + CLK_DISABLE = 0, /* clock unuseable status */ + CLK_WARM_UP = 1, /* warm up status */ + CLK_TRACKING, /* tracking status */ + CLK_HOLD_OVER /* hold over status */ +}clk_sync_state_e; + +/*前传接口类型*/ +typedef enum +{ + UCP4008_JESD = 0, /* JESD */ + UCP4008_CPRI, /* CPRI */ + UCP4008_ECPRI, /* eCPRI */ + RESERVED_FH /* Reserved*/ +} front_hual_e; + + + +/*恢复时钟类型*/ +typedef enum +{ + SYNC_ETH_CLK = 25000000, /* 外部同步以太网时钟输入 25M*N*/ + CLK_GE_CDR = 125000000, /* 千兆以太网RX时钟，外部输入125MHz */ + CLK_CPRI_CDR = 122880000, /* 内部CPRI SERDES恢复时钟输出122.88MHZ*/ + CLK_ECPRI_CDR = 156250000, /* 内部eCPRI SERDES恢复时钟输出156.25MHz */ + CLK_TMAC_CDR = 156250000 /* 内部TMAC SERDES(PT SERDES)恢复时钟156.25MHz */ +} recovery_clk_e; + +typedef struct +{ + double integral; //累计偏差(积分) + double magic_num; //输出系数 PCLK的周期 + double p_ratio; //比例系数 + double i_ratio; //积分系数 + uint8_t status; //是否同步 0:未同步，1同步 + uint8_t tracking_cnt; + uint16_t holdover_cnt; + uint32_t disable_cnt; +}pi_struct_s; + +/*typedef struct +{ + pi_struct_s + +}adjust_struct_s;*/ + + + +typedef struct +{ + pp1s_soure_e pp1s_src; //1pps源 + //front_hual_e fh_interface; //前传接口类型 + hscc_dump_soure_e hscc_dump_src; + //recovery_clk_e recovery_clk; + uint32_t synce_flag; //是否有synce时钟 1：有，0：没有 + uint32_t synce_clk; //synce时钟频率Hz + uint32_t cal_period; //频率校准的频率（每秒校准次数）,单位：Hz + uint32_t p_clk; //P_CLK_STC的频率值 + uint64_t default_ft; //默认的ft值 + double p_clk_period; //P_CLK_STC的周期值 + pi_struct_s freq; //频率校准 + pi_struct_s phase; //相位校准 + clk_sync_state_e state; + uint32_t pesudo_flag; +}stc_state_s; + + +typedef struct +{ + uint32_t common_alarm; + uint32_t hold_over_time; + clk_sync_state_e status; +}clock_module_status_s; + +/*错误返回码*/ +#define STC_OK (0) /* 函数调用返回成功 */ +#define PARAMETER1_ERROR (-1) +#define PARAMETER2_ERROR (-2) +#define PARAMETER3_ERROR (-3) +#define PARAMETER4_ERROR (-4) +#define PARAMETER5_ERROR (-5) +#define LOGIC_ERROR1 (-6) +#define LOGIC_ERROR2 (-7) +#define LOGIC_ERROR3 (-8) +#define LOGIC_ERROR4 (-9) +#define LOGIC_ERROR5 (-10) +#define LOGIC_ERROR6 (-11) +#define LOGIC_ERROR7 (-12) +#define LOGIC_ERROR8 (-13) +#define LOGIC_ERROR9 (-14) +#define LOGIC_ERROR10 (-15) +#define LOGIC_ERROR11 (-16) +#define LOGIC_ERROR12 (-17) +#define LOGIC_ERROR13 (-18) + +/*============================================================================== + Function Prototypes +==============================================================================*/ +int32_t set_clk_mode(clk_flag_e pseudo_flag); +int32_t get_clock_module_status(volatile clock_module_status_s* clk_module_status_ptr); +stc_state_s* get_stc_state(); +arm_stc_regs * get_stc_reg_base(); +void set_su_reg(uint64_t value); +void * get_ap_gpio_reg_base(); + +#if 0 +#pragma align() /* restore default packing */ +#pragma pack() +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __STC_DRV_H__ */ + diff --git a/driver/tfu/stc/inc/stc_drv_api.h b/driver/tfu/stc/inc/stc_drv_api.h new file mode 100644 index 0000000..89fa966 --- /dev/null +++ b/driver/tfu/stc/inc/stc_drv_api.h @@ -0,0 +1,163 @@ +/*============================================================================== +* Copyright (c) 2011~2012, CPIT. All Rights Reserved. +* +* MODULE: STC模块驱动 +* +* FILENAME: stc.h +* +* DESCRIPTION: Source Code of STC Driver +* +* Current Version: 1.0 +* +* HISTORY: +* Date CR No Person Description +* ---------- ------------ ------ ------------- +* 2022-05-21 Li Weihua Initial version. +==============================================================================*/ +#ifndef __STC_DRV_API_H__ +#define __STC_DRV_API_H__ + +#include "typedef.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if 0 +#pragma align(1) /* set tight packing */ +#pragma pack(1) +#endif +/*============================================================================== + Includes and Public Data Declarations +==============================================================================*/ + +/* 包含系统文件以及定义公用数据文件 */ + + +/*============================================================================== + Include Files +==============================================================================*/ + +/* 包含本地文件 */ +/*============================================================================== + Constant / Define Declarations +==============================================================================*/ + + +/* 常量定义，并对所定义的常量进行说明 */ +/*============================================================================== + Global Constant Data Declarations +==============================================================================*/ + +/*============================================================================== + Macro Definitions +==============================================================================*/ +/* 宏定义，并对其进行简要说明 */ + +/*============================================================================== + Function Prototypes +==============================================================================*/ + +/*STC中断类型*/ +typedef enum +{ + STC_INT_RESERVED = 0, /* Reserved*/ + STC_TOD_1PPS, /* stc内部产生的1pps中断 */ + STC_EX_1PPS_IN, /* 外部1pps中断 */ + STC_HSCC_DUMP = 4 /* HSCC_DUMP中断 */ +} stc_int_type_e; + + +/*输入1PPS中断源*/ +typedef enum +{ + GMAC0_1PPS_IN = 0, /* gmac0 */ + GMAC1_1PPS_IN, /* gmac1 */ + RESERVED0_1PPS_IN, /* Reserved*/ + CPRI_GMAC_1PPS_IN = 3, /* cpri gmac */ + TMAC_1PPS_IN, /* tmac */ + GNSS_1PPS_IN, /* 接收机 */ + //GMAC_1PPS + RESERVED_1PPS_IN /* Reserved*/ +} pp1s_soure_e; + +/*输出1PPS源*/ +typedef enum +{ + GMAC0_1PPS_OUT = 0, /* gmac0 */ + GMAC1_1PPS_OUT, /* gmac1 */ + RESERVED0_1PPS_OUT, /* Reserved*/ + CPRI_GMAC_1PPS_OUT = 3, /* cpri gmac */ + TMAC_1PPS_OUT, /* tmac */ + STC_1PPS_OUT, /* stc产生的1pps */ + TOD_1PPS_OUT, /* stc产生的1pps */ + RESERVED_1PPS_OUT /* Reserved*/ +} pp1s_output_e; + +/*synce接口类型*/ +typedef enum +{ + SYNCE_GMAC = 0, /* GMAC */ + SYNCE_TMAC, /* TMAC */ + SYNCE_ECPRI, /* eCPRI */ + RESERVED_SYNCE /* Reserved*/ +}synce_src_e; + + +/*hscc_dump的输入源*/ +typedef enum +{ + TOD_1PPS = 0, /* stc内部产生的1pps */ + EX_1PPS_IN, /* 外部1pps */ + EX_SYNCE, /* 恢复时钟/synce时钟分频产生的1pps */ + HSCC_RESERVED /* Reserved*/ +} hscc_dump_soure_e; + +int32_t init_stc(); +int32_t enable_stc_irq(stc_int_type_e irq_type); +int32_t disable_stc_irq(stc_int_type_e irq_type); +int32_t select_xpps_in_source(pp1s_soure_e src); +int32_t set_xpps_out_source(pp1s_output_e src,uint32_t enable); +double stc_adjust_frequency(); +int32_t stc_adjust_phase(uint32_t phase_diff); +int32_t stc_adjust_sniffer_phase(int32_t phase_diff,uint32_t flag); +int32_t set_ape_preset_value(uint32_t cal_bfn); +int32_t stc_wait_for_hscc(); +int32_t stc_wait_for_expps(); +uint32_t get_gmac_src_time(); +uint32_t get_tmac_src_time(); +uint32_t read_stc_local_timer(); + +/****************************************************************** +* Input(s): +* sync_status: STC同步状态 1：同步，0：失步 +* Output(s): +* +* Returns: +* 0：成功 +* 非0：失败 +********************************************************************/ +int32_t set_sync_status_to_ape(uint32_t sync_status); + +/*配置STC内部 synce时钟源*/ +int32_t config_synce(uint32_t synce_flag, synce_src_e interface, uint32_t clk); + +/*synce时设置频率校准周期*/ +int32_t set_fsync_frequncy(uint32_t frequncy); + +/*选择hscc_dump中断的输入*/ +int32_t select_hscc_dump_source(hscc_dump_soure_e src_type); + +uint32_t read_stc_local_timer(); + +#if 0 +#pragma align() /* restore default packing */ +#pragma pack() +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __STC_DRV_API_H__ */ + diff --git a/driver/tfu/stc/inc/typedef.h b/driver/tfu/stc/inc/typedef.h new file mode 100644 index 0000000..b15fd61 --- /dev/null +++ b/driver/tfu/stc/inc/typedef.h @@ -0,0 +1,36 @@ +// +FHDR------------------------------------------------------------ +// Copyright (c) 2022 SmartLogic. +// ALL RIGHTS RESERVED +// ----------------------------------------------------------------- +// Filename : typedef.h +// Author : xianfeng.du +// Created On : 2022-06-25 +// Last Modified : +// ----------------------------------------------------------------- +// Description: +// +// +// -FHDR------------------------------------------------------------ + +#ifndef __TYPEDEF_H__ +#define __TYPEDEF_H__ + +typedef unsigned char uint8_t; +typedef signed char int8_t; +typedef short int int16_t; +typedef unsigned short int uint16_t; +typedef int int32_t; +typedef unsigned int uint32_t; +typedef long int int64_t; +typedef unsigned long int uint64_t; + +#define OSP_OK (0) /* 正常返回 */ +#define OSP_ERROR (-1) /* 错误返回 */ +//#define OSP_PAR_ILL (-2) /* 入参错误 */ +//#define OSP_FILE_ERROR (-3) /* 文件错误 */ +//#define OSP_PAR_REP (-4) /* 入参重复 */ +//#define OSP_QUE_FULL (-5) /* 软队列满 */ +//#define OSP_QUE_EMPT (-6) /* 软队列空 */ +//#define OSP_MEM_FULL (-7) /* 内存申请失败 */ + +#endif diff --git a/driver/tfu/stc/inc/ucp_printf.h b/driver/tfu/stc/inc/ucp_printf.h new file mode 100644 index 0000000..d68f1a3 --- /dev/null +++ b/driver/tfu/stc/inc/ucp_printf.h @@ -0,0 +1,78 @@ +// +FHDR------------------------------------------------------------ +// Copyright (c) 2022 SmartLogic. +// ALL RIGHTS RESERVED +// ----------------------------------------------------------------- +// Filename : ucp_printf.h +// Author : xianfeng.du +// Created On : 2022-06-25 +// Last Modified : +// ----------------------------------------------------------------- +// Description: +// +// +// -FHDR------------------------------------------------------------ + + +#ifndef __UCP_RINTF_H__ +#define __UCP_RINTF_H__ + +#include +//#include + +#define PRINT_OFF 0x00000000 // close all PRINT +#define PRINT_ERROR 0x00000001 +#define PRINT_WARN 0x00000002 +#define PRINT_LOG 0x00000004 +#define PRINT_DEBUG 0x00000008 +#define PRINT_TICK 0x00000010 +#define PRINT_SHELL 0x00000020 + +//#define UCP_PRINT_LEVEL (PRINT_OFF) +//#define UCP_PRINT_LEVEL (PRINT_ERROR | PRINT_WARN |PRINT_LOG | PRINT_TICK| PRINT_DEBUG|PRINT_SHELL) +#define UCP_PRINT_LEVEL (PRINT_ERROR |PRINT_DEBUG| PRINT_SHELL) +//#define UCP_PRINT_LEVEL (PRINT_ERROR) + +#if (UCP_PRINT_LEVEL & PRINT_ERROR) +//#define UCP_PRINT_ERROR(fmt, args...) printf(__FILE__ ": [ERROR]: %d: %s():" fmt "\n", __LINE__, __func__, ##args) +#define UCP_PRINT_ERROR(fmt, args...) printf("[ERROR]:" fmt "\n", ##args) +#else +#define UCP_PRINT_ERROR(fmt, args...) +#endif + +#if (UCP_PRINT_LEVEL & PRINT_WARN) +//#define UCP_PRINT_WARN(fmt, args...) printf(__FILE__ ": [WARN]: %d: %s():" fmt "\n", __LINE__, __func__, ##args) +#define UCP_PRINT_WARN(fmt, args...) printf("[WARN]:" fmt "\n", ##args) +#else +#define UCP_PRINT_WARN(fmt, args...) +#endif + +#if (UCP_PRINT_LEVEL & PRINT_LOG) +//#define UCP_PRINT_LOG(fmt, args...) printf(__FILE__ ": [LOG]: %d: %s():" fmt "\n", __LINE__, __func__, ##args) +#define UCP_PRINT_LOG(fmt, args...) printf("[LOG]:" fmt "\n", ##args) +#else +#define UCP_PRINT_LOG(fmt, args...) +#endif + +#if (UCP_PRINT_LEVEL & PRINT_DEBUG) +//#define UCP_PRINT_LOG(fmt, args...) printf(__FILE__ ": [LOG]: %d: %s():" fmt "\n", __LINE__, __func__, ##args) +#define UCP_PRINT_DEBUG(fmt, args...) printf("[DEBUG]:" fmt "\n", ##args) +#else +#define UCP_PRINT_DEBUG(fmt, args...) +#endif + +#if (UCP_PRINT_LEVEL & PRINT_TICK) +//#define UCP_PRINT_TICK(fmt, args...) printf(__FILE__ ": [TICK]: %d: %s():" fmt "\n", __LINE__, __func__, ##args) +#define UCP_PRINT_TICK(fmt, args...) printf("[TICK]:" fmt "\n", ##args) +#else +#define UCP_PRINT_TICK(fmt, args...) +#endif + +#if (UCP_PRINT_LEVEL & PRINT_SHELL) +//#define UCP_PRINT_SHELL(fmt, args...) printf(__FILE__ ": [SHELL]: %d: %s():" fmt "\n", __LINE__, __func__, ##args) +#define UCP_PRINT_SHELL(fmt, args...) printf("[SHELL:]" fmt, ##args) +#else +#define UCP_PRINT_SHELL(fmt, args...) +#endif + + +#endif diff --git a/driver/tfu/stc/src/stc_drv.c b/driver/tfu/stc/src/stc_drv.c new file mode 100644 index 0000000..308a4a6 --- /dev/null +++ b/driver/tfu/stc/src/stc_drv.c @@ -0,0 +1,875 @@ +/*------------------------------------------------------------ +// Copyright (c) 2022 SmartLogic. +// ALL RIGHTS RESERVED +// ----------------------------------------------------------------- +// Filename : stc_drv.c +// Author : weihua.li +// Created On : 2022-11-23 +// Last Modified : +// ----------------------------------------------------------------- +// Description: +// +// +// ----------------------------------------------------------------*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "typedef.h" +#include "stc_drv_api.h" +#include "stc_drv.h" +#include "ucp_printf.h" +/*============================================================================== + Constant / Defines +==============================================================================*/ + +/* 常量定义，并对常量定义进行简要说明 */ + +/*============================================================================== + Global variable Definitions +==============================================================================*/ +arm_stc_regs *g_stc_regs_ptr = NULL; //0x08568000 +void *g_ecs_subctrl_regs_ptr = NULL; //0x08460000 +void *g_ecs_crg_regs_ptr = NULL; //0x08430000 +void *g_ap_gpio_pinmux_regs_ptr = NULL; //0x04450000-0x04458000 +uint32_t *g_gmac0_tod_ptr = NULL; //0x01a40000 + 0xb08 +uint32_t *g_tmac_tod_ptr = NULL; //0x09090000 + 0xd08 +uint32_t *g_sfn_ptr = NULL; //0x0A4f2220 +uint32_t *g_sniffer_ptr = NULL; //0x0A4f2140 +int32_t g_drv_mem_fd = -1; + +stc_state_s g_stc_state = +{ + .pp1s_src = GNSS_1PPS_IN, + .hscc_dump_src = HSCC_RESERVED, + .synce_flag = 0, + .cal_period = 1, + .state = CLK_WARM_UP, + .freq = { + .integral = 0, + .p_ratio = 0.5, + .i_ratio = 0.5, + .tracking_cnt = 0, + .holdover_cnt = 0, + .disable_cnt = 0, + + }, + .phase = { + .integral = 0, + .p_ratio = 0.7218, + .i_ratio = 0.2308, + .tracking_cnt = 0, + .holdover_cnt = 0, + .disable_cnt = 0, + + }, +}; //stc状态 + +uint32_t g_init_stc_flag = 0;/*模块初始化标志0:未初始化，1:已初始化*/ +int32_t g_stc_fd = -1; /*STC ko fd*/ + + +/*============================================================================== + Local Object Definitions +==============================================================================*/ + +/* 局部对象定义，并对其进行简要说明 */ + +/*============================================================================== + Static Variable Definitions +==============================================================================*/ + +/* 静态变量定义，并对其进行简要说明 */ + +/*============================================================================== + Forward Declarations +==============================================================================*/ + +/* 前置声明 */ + +/*============================================================================== + Function Definitions +==============================================================================*/ +static int32_t map_stc_reg_space() +{ + //uint32_t *ecs_crg_reg5_ptr = NULL; //stc_cdr_clk_sel + //uint32_t *ecs_crg_reg8_ptr = NULL; //jecs2_div + uint32_t *pb14_ctrl_reg_ptr = NULL; //pb14_ctrl + uint32_t *pb_pmux_reg_ptr = NULL; //pp1s in->gpioa29 + void *tmp_ptr = NULL; + + if(g_drv_mem_fd < 0) + { + g_drv_mem_fd = open("/dev/mem", O_RDWR|O_SYNC); + if(g_drv_mem_fd < 0) + { + UCP_PRINT_ERROR("open /dev/mem error"); + return LOGIC_ERROR1; + } + } + + + tmp_ptr = mmap(NULL, GMAC0_REG_LEN, PROT_READ|PROT_WRITE, MAP_SHARED, + g_drv_mem_fd, GMAC0_REG_BASE_ADDR); + if(-1 == (int64_t)tmp_ptr) + { + UCP_PRINT_ERROR("mmap gmac0 error!! return = %ld\n",(uint64_t)tmp_ptr); + return LOGIC_ERROR4; + } + else + { + g_gmac0_tod_ptr = (uint32_t *)(tmp_ptr + GMAC0_TOD_REG); + } + + tmp_ptr = mmap(NULL, TMAC_REG_LEN, PROT_READ|PROT_WRITE, MAP_SHARED, + g_drv_mem_fd, TMAC_REG_BASE_ADDR); + if(-1 == (int64_t)tmp_ptr) + { + UCP_PRINT_ERROR("mmap tmac error!! return = %ld\n",(uint64_t)tmp_ptr); + return LOGIC_ERROR7; + } + else + { + g_tmac_tod_ptr = (uint32_t *)(tmp_ptr + TMAC0_TOD_REG); + } + + if(g_stc_regs_ptr == NULL) + { + g_stc_regs_ptr = mmap(NULL, STC_REG_LEN, PROT_READ|PROT_WRITE, MAP_SHARED, + g_drv_mem_fd, STC_REG_BASE_ADDR); + if(-1 == (int64_t)g_stc_regs_ptr) + { + UCP_PRINT_ERROR("mmap stc regs error!! return = %ld\n",(uint64_t)g_stc_regs_ptr); + g_stc_regs_ptr = NULL; + return LOGIC_ERROR2; + } + } + + if(g_ecs_subctrl_regs_ptr == NULL) + { + g_ecs_subctrl_regs_ptr = mmap(NULL, ECS_SUBCTRL_REG_LEN, PROT_READ|PROT_WRITE, MAP_SHARED, + g_drv_mem_fd, ECS_SUBCTRL_REG_BASE_ADDR); + if(-1 == (int64_t)g_ecs_subctrl_regs_ptr) + { + UCP_PRINT_ERROR("mmap ecs_subctrl error!! return = %ld\n",(uint64_t)g_ecs_subctrl_regs_ptr); + return LOGIC_ERROR3; + } + } + + if(g_ecs_crg_regs_ptr == NULL) + { + g_ecs_crg_regs_ptr = mmap(NULL, ECS_CRG_REG_LEN, PROT_READ|PROT_WRITE, MAP_SHARED, + g_drv_mem_fd, ECS_CRG_REG_BASE_ADDR); + if(-1 == (int64_t)g_ecs_crg_regs_ptr) + { + UCP_PRINT_ERROR("mmap ecs_crg error!! return = %ld\n",(uint64_t)g_ecs_crg_regs_ptr); + return LOGIC_ERROR4; + } + } + + if(g_ap_gpio_pinmux_regs_ptr == NULL) + { + g_ap_gpio_pinmux_regs_ptr = mmap(NULL, AP_GPIO_PINMUX_REG_LEN, PROT_READ|PROT_WRITE, MAP_SHARED, + g_drv_mem_fd, AP_GPIO_PINMUX_REG_BASE_ADDR); + if(-1 == (int64_t)g_ap_gpio_pinmux_regs_ptr) + { + UCP_PRINT_ERROR("mmap AP_GPIO pinmux error!! return = %ld\n",(uint64_t)g_ap_gpio_pinmux_regs_ptr); + return LOGIC_ERROR3; + } + } + + tmp_ptr = mmap(NULL, SHARE_MEM_LEN, PROT_READ|PROT_WRITE, MAP_SHARED, + g_drv_mem_fd, SHARE_MEM_BASE_ADDR); + if(-1 == (int64_t)tmp_ptr) + { + UCP_PRINT_ERROR("mmap g_sfn_ptr!! return = %ld\n",(uint64_t)tmp_ptr); + return LOGIC_ERROR6; + } + else + { + g_sfn_ptr = (uint32_t *)(tmp_ptr + SFN_BASE_ADDR - SHARE_MEM_BASE_ADDR); + g_sniffer_ptr = (uint32_t *)(tmp_ptr + SNIFFER_BASE_ADDR - SHARE_MEM_BASE_ADDR); + //*(g_sniffer_ptr + 1) = 0; + *g_sfn_ptr = 0xaa; + } + + /*config TMAC/ECPRI synce clk */ + /*ecs_crg_reg5_ptr = (uint32_t *)(g_ecs_crg_regs_ptr + 0x14); //stc_cdr_clk_sel + ecs_crg_reg8_ptr = (uint32_t *)(g_ecs_crg_regs_ptr + 0x20); //jecs2_div + *ecs_crg_reg8_ptr = 0x520000; + *ecs_crg_reg5_ptr |= BIT31; */ + + /*EX_1PPS_IN CFG*/ + pb14_ctrl_reg_ptr = (uint32_t *)(g_ap_gpio_pinmux_regs_ptr + AP_GPIO_REG_LEN + 0xbc); //PB14_CTRL_REG + *pb14_ctrl_reg_ptr |= (BIT6 | BIT7); + pb_pmux_reg_ptr = (uint32_t *)(g_ap_gpio_pinmux_regs_ptr + AP_GPIO_REG_LEN + 0x180); //PB_PMUX_REG + *pb_pmux_reg_ptr = (*pb_pmux_reg_ptr & 0xcfffffff) | BIT29; //sel:GNSS_PPS_IN + + return STC_OK; +} + +/********获取P_CLK时钟值********* +从前传接口驱动中获取***********/ +static uint32_t get_pclk_value() +{ + uint32_t tmp_clk = g_stc_regs_ptr->tod_reg_nf; + + if(0xc0000000 != (tmp_clk & 0xc0000000)) + { + return LOGIC_ERROR1; + } + else + { + g_stc_state.p_clk = g_stc_regs_ptr->tod_reg_nf & 0x3fffffff; //更新状态 + g_stc_state.p_clk_period = 1.000000000001 / g_stc_state.p_clk; + g_stc_state.phase.magic_num = 1.000000000001 / g_stc_state.p_clk; + } + return STC_OK; +} + +int32_t set_ape_preset_value(uint32_t cal_sub_bfn) +{ + static uint32_t valid_flag = 0xa5a5a5a5; + //struct timeval begin; + + *g_sfn_ptr = 0xaa; + *(g_sfn_ptr + 1) = cal_sub_bfn; + *(g_sfn_ptr + 2) = valid_flag; + *g_sfn_ptr = 0x55; + valid_flag = ~valid_flag; + //gettimeofday(&begin, NULL); + //UCP_PRINT_DEBUG("s = %ld,u = %ld, sfn = %d",begin.tv_sec,begin.tv_usec,cal_sub_bfn); + return STC_OK; +} + +int32_t set_sync_status_to_ape(uint32_t sync_status) +{ + *(g_sfn_ptr + 3) = sync_status; //set locked flag to ape + + return STC_OK; +} + +int32_t stc_wait_for_expps() +{ + int32_t ret = -1; + uint32_t ex_pp1s_irq_cnt; + + if(-1 == g_stc_fd) + { + g_stc_fd = open(STC_DEV_NAME,O_RDWR);//O_RDWR + if(-1 == g_stc_fd) + { + printf("open stc-dev device failed\n\r"); + return LOGIC_ERROR1; + } + } + + ret = read(g_stc_fd, &ex_pp1s_irq_cnt, STC_EX_1PPS_IN); //pend + + return ret; + +} + +int32_t stc_wait_for_hscc() +{ + int32_t ret = -1; + uint32_t hscc_dump_irq_cnt = 0; + + if(-1 == g_stc_fd) + { + g_stc_fd = open(STC_DEV_NAME,O_RDWR);//O_RDWR + if(-1 == g_stc_fd) + { + printf("open stc-dev device failed\n\r"); + return LOGIC_ERROR1; + } + } + + ret = read(g_stc_fd, &hscc_dump_irq_cnt, STC_HSCC_DUMP); //pend + + return ret; +} + +int32_t enable_stc_irq(stc_int_type_e irq_type) +{ + if(-1 == g_stc_fd) + { + g_stc_fd = open(STC_DEV_NAME,O_RDWR);//O_RDWR + if(-1 == g_stc_fd) + { + printf("open stc-dev device failed\n\r"); + return LOGIC_ERROR2; + } + } + + if(STC_OK == ioctl(g_stc_fd,STC_INT_CFG,&irq_type)) + { + return STC_OK; + } + else + { + return LOGIC_ERROR1; + } +} + +int32_t disable_stc_irq(stc_int_type_e irq_type) +{ + g_stc_regs_ptr->tod_reg_irq_en &= ~irq_type; + return STC_OK; +} + +/*选择送给A72和stc的外部1PPS源*/ +int32_t select_xpps_in_source(pp1s_soure_e src) +{ + uint32_t stc_sel; //配置jecs_subctrl_reg33:stc_sel,选择xpps_in的输入 + uint32_t *stc_sel_ptr = (uint32_t *)(g_ecs_subctrl_regs_ptr + 0x84); + + if(src > GNSS_1PPS_IN) + { + return PARAMETER1_ERROR; + } + + //配置输入1pps源寄存器 + stc_sel = *stc_sel_ptr; + //stc_sel = 0xfffffc7f; + ///stc_sel |= src << 7; + /*统一使用8a34002输出的1pps，因此固定为GNSS_1PPS_IN*/ + *stc_sel_ptr = (stc_sel & ~(BIT7 | BIT8 | BIT9)) | (GNSS_1PPS_IN << 7); + //*stc_sel_ptr = (stc_sel & ~(BIT7 | BIT8 | BIT9)) | (src << 7); + + g_stc_state.pp1s_src = src; //更新状态 + + return STC_OK; +} + +/*设置输出1PPS源*/ +int32_t set_xpps_out_source(pp1s_output_e src,uint32_t enable) +{ + uint32_t gnss_sel; //配置jecs_subctrl_reg33,选择输出到pad的1pps信号 + uint32_t *gnss_sel_ptr = (uint32_t *)(g_ecs_subctrl_regs_ptr + 0x84); + uint32_t *pc_mux_reg_ptr = (g_ap_gpio_pinmux_regs_ptr + AP_GPIO_REG_LEN + 0x184); //PINMUX:PC_MUX_REG 0x04458184 + uint32_t out_src = src; + + if(src > TOD_1PPS_OUT) + { + return PARAMETER1_ERROR; + } + + if(!g_stc_state.default_ft) + { + UCP_PRINT_ERROR("does not init stc,please init stc first!"); + return LOGIC_ERROR2; + } + + if(1 == enable) //enable pps out + { + g_stc_regs_ptr->tod_reg_config |= BIT3; + } + else //disable pps out + { + g_stc_regs_ptr->tod_reg_config &= ~BIT3; + out_src = STC_1PPS_OUT; + } + + *pc_mux_reg_ptr = (*pc_mux_reg_ptr & 0xcfffffff) | BIT29; //sel:GNSS_PPS_OUT + + //配置输出1pps源寄存器 + gnss_sel = *gnss_sel_ptr; + //gnss_sel &= 0xffffff8f; + //gnss_sel |= src << 4; + *gnss_sel_ptr = (gnss_sel & ~(BIT4 | BIT5 | BIT6)) | (out_src << 4); + + g_stc_regs_ptr->tod_reg_ft_lo = g_stc_state.default_ft & 0xffffffff; + g_stc_regs_ptr->tod_reg_ft_hi = g_stc_state.default_ft >> 32; //恢复默认值 + + UCP_PRINT_DEBUG("pps out = %d(1:enable,0:disable),default_value = %#lx\n",enable,g_stc_state.default_ft); + + return STC_OK; +} + +/*选择hscc_dump中断的输入*/ +int32_t select_hscc_dump_source(hscc_dump_soure_e src_type) +{ + if(src_type > EX_SYNCE) + { + return PARAMETER1_ERROR; + } + + g_stc_regs_ptr->tod_reg_config &= ~(BIT0 | BIT1); + g_stc_regs_ptr->tod_reg_config |= src_type; + + g_stc_state.hscc_dump_src = src_type; + + return STC_OK; +} + +/*设置RT寄存器，高32bit一般为10^9ns（0x3B9ACA00 1s），低32bit为0*/ +void set_rt_reg(uint32_t value) +{ + g_stc_regs_ptr->tod_reg_rt_lo = 0; + g_stc_regs_ptr->tod_reg_rt_hi = value; + + return; +} + +/*设置NSF_INIT寄存器，TOD的低48bit +hi_value：ns值 +lo_value：ns值的小数，高16bit有效，低16bit忽略*/ +void set_nsf_init_reg(uint32_t lo_value, uint32_t hi_value) +{ + g_stc_regs_ptr->tod_reg_nsf_init_lo = lo_value & 0xffff0000; + g_stc_regs_ptr->tod_reg_nsf_init_hi = hi_value; + return; +} + +/*设置SU寄存器,配置TOD秒的初值,有效值为低48bit*/ +void set_su_reg(uint64_t value) +{ + g_stc_regs_ptr->tod_reg_su_lo = value; + g_stc_regs_ptr->tod_reg_su_hi = (value >> 32) & 0xffff; //取value的32-47bit + + g_stc_regs_ptr->tod_reg_config &= ~BIT4; // clear tod_incr_en + + return; +} + +/*设置tod累加步进值FT +FT没有配置之前，stc TOD流程不启动 +在配置FT前，先配置： +1、set_rt_reg +2、set_nsf_init_reg +3、set_su_reg +一旦配置了FT的值，stc TOD流程就启动了*/ +void set_ft_init_value(uint32_t pclk) +{ + //(10^9 * 2^32) = 0x3B9ACA0000000000ULL + uint64_t coff = DEFAULT_RT_VALUE / pclk; + /*double clk_2_ns = SECOND2NS / pclk; //pclk的周期（以ns为单位） + uint32_t hi_of_ft = (uint32_t)clk_2_ns; //取clk_2_ns的整数部分，ns + uint32_t lo_of_ft = (clk_2_ns - hi_of_ft) * coff; //小数部分*2^32*/ + + g_stc_regs_ptr->tod_reg_ft_lo = coff & 0xffffffff; + g_stc_regs_ptr->tod_reg_ft_hi = coff >> 32; + + g_stc_state.default_ft = coff; + + UCP_PRINT_DEBUG("default_ft = %#lx\n",g_stc_state.default_ft); + + return; +} + + +int32_t set_default_ft_value() +{ + if(!g_stc_state.default_ft) + { + UCP_PRINT_ERROR("set default ft error!"); + return LOGIC_ERROR1; + } + + g_stc_regs_ptr->tod_reg_ft_lo = g_stc_state.default_ft & 0xffffffff; + g_stc_regs_ptr->tod_reg_ft_hi = g_stc_state.default_ft >> 32; //恢复默认值 + + UCP_PRINT_DEBUG("default_value = %#lx\n",g_stc_state.default_ft); + + return STC_OK; +} + + +/*设置频率校准*/ +int32_t set_fsync_frequncy(uint32_t frequncy) +{ + g_stc_regs_ptr->tod_reg_nf = g_stc_state.synce_clk / frequncy; + g_stc_state.cal_period = frequncy; //更新状态 + + return STC_OK; +} + + +/*选择STC内部 synce时钟源*/ +int32_t config_synce(uint32_t synce_flag, synce_src_e interface, uint32_t clk) +{ + uint32_t *eth_clk_sel_ptr = (uint32_t *)(g_ecs_subctrl_regs_ptr + 0x84); + uint32_t *ecs_crg_reg61_ptr = (uint32_t *)(g_ecs_crg_regs_ptr + 0xf4); + uint32_t stc_serdes_clk_sel; + + g_stc_state.synce_flag = synce_flag; + if(1 == synce_flag) + { + if(SYNCE_GMAC == interface) //B 选择sfp_eth_clk + { + *eth_clk_sel_ptr |= BIT1; + } + else //A 选择eth_serdes_rx_clk + { + stc_serdes_clk_sel = *ecs_crg_reg61_ptr; + stc_serdes_clk_sel &= ~(BIT2 | BIT3); + if(SYNCE_TMAC == interface) + { + stc_serdes_clk_sel |= BIT2; + *ecs_crg_reg61_ptr = stc_serdes_clk_sel; + } + + *eth_clk_sel_ptr &= ~BIT1; //最终的输出，选择eth_erdes_rx_clk + } + + g_stc_state.synce_clk = clk; + g_stc_regs_ptr->tod_reg_nf = clk / g_stc_state.cal_period; //写入synce分频 + } + + return STC_OK; +} + +/*调整频率，实现频率同步*/ +double stc_adjust_frequency(void) +{ + uint32_t hscc_value = g_stc_regs_ptr->tod_reg_hscc; //读取HSCC寄存器值 + int32_t diff = hscc_value - g_stc_state.p_clk; //计算实际CLK与读取的计数值之间的差值 + double delta; + +#ifdef SL_ADJ_FREQ + g_stc_state.freq.integral += diff; + delta = g_stc_state.freq.p_ratio * diff + g_stc_state.freq.i_ratio * g_stc_state.freq.integral; +#else + delta = diff * g_stc_state.p_clk_period; //频偏百分比 + //UCP_PRINT_DEBUG("hscc_value = %d, pclk = %d,fre_delta = %-16.10f",hscc_value,g_stc_state.p_clk,delta); +#endif + /*根据差值，通过SPI接口调整外部VCXO或OCXO的频率*/ + return delta; +} + +/*调整相位，实现时间同步*/ +int32_t stc_adjust_phase(uint32_t phase_diff) +{ + uint32_t nsf_reg_lo; + int32_t diff_ns,track_ns; //phase diff(ns) + static uint32_t first_sync_flag = 0; + int64_t nsf_value; + int64_t rt_value = DEFAULT_RT_VALUE; + int64_t rt_hf_value = DEFAULT_RT_HALF; + uint64_t ft_new; + int64_t diff; + uint32_t tod_lo,tod_mi,nano_sec; + double delta; + + nsf_reg_lo = g_stc_regs_ptr->tod_reg_nsf_1pps_lo; + ft_new = g_stc_regs_ptr->tod_reg_nsf_1pps_hi; + nsf_value = (ft_new << 32) | nsf_reg_lo; //获取当前nsf寄存器值 + if(nsf_value < rt_hf_value) //STC pp1s 提前，ft过大 + { + diff = nsf_value; + track_ns = diff >> 32; + //track_ns = ft_new; + diff_ns = track_ns; + } + else //STC pp1s 滞后，ft过小 + { + diff = nsf_value - rt_value; + //track_ns = 1000000000 - ft_new; + track_ns = (rt_value - nsf_value) >> 32; + diff_ns = -track_ns; + } + + if(!first_sync_flag) + { + g_stc_regs_ptr->tod_reg_ft_lo = 0; + g_stc_regs_ptr->tod_reg_ft_hi = 0; //先停止计数 + + tod_lo = g_stc_regs_ptr->tod_reg_tod_lo; + tod_mi = g_stc_regs_ptr->tod_reg_tod_mi; + nsf_reg_lo = g_stc_regs_ptr->tod_reg_tod_hi; + nsf_reg_lo = ((tod_mi & 0xffff) << 16) | (tod_lo >> 16); //计算出当前的ns值 + + /*gnss pps起点是0，计算计数初值*/ + if(nsf_reg_lo > ft_new) //计算stc pps与gnss pps相差 + { + nano_sec = nsf_reg_lo - ft_new; + } + else + { + nano_sec = 1000000000 - ft_new + nsf_reg_lo; + } + g_stc_regs_ptr->tod_reg_nsf_init_lo = 0; + g_stc_regs_ptr->tod_reg_nsf_init_hi = nano_sec + 904; + + g_stc_regs_ptr->tod_reg_ft_lo = g_stc_state.default_ft & 0xffffffff; + g_stc_regs_ptr->tod_reg_ft_hi = g_stc_state.default_ft >> 32; //恢复计数 + + first_sync_flag = 1; + UCP_PRINT_DEBUG("dump_1pps = %ld,tod_ns = %d,cal_ns = %d",ft_new,nsf_reg_lo,nano_sec); + return diff_ns; + } + + if(track_ns < phase_diff) + { + g_stc_state.phase.status = 1; + if(++g_stc_state.phase.tracking_cnt > STC_LOCK_CNT) + { + g_stc_state.phase.tracking_cnt = STC_LOCK_CNT; + g_stc_state.phase.holdover_cnt = 0; + g_stc_state.phase.disable_cnt = 0; + g_stc_state.state = CLK_TRACKING; + } + } + else + { + g_stc_state.phase.tracking_cnt = 0; + g_stc_state.phase.status = 0; + } + + g_stc_state.phase.integral += diff; + + /*根据差值，设置Ft寄存器值，使|Rt-nsf|最小*/ + delta = g_stc_state.phase.p_ratio * diff + g_stc_state.phase.i_ratio * g_stc_state.phase.integral; + ft_new = g_stc_state.default_ft - delta * g_stc_state.phase.magic_num; + //UCP_PRINT_DEBUG("delta = %f, ft_new = %#lx",delta,ft_new); + + g_stc_regs_ptr->tod_reg_ft_lo = ft_new & 0xffffffff; + g_stc_regs_ptr->tod_reg_ft_hi = ft_new >> 32; + + //UCP_PRINT_DEBUG("diff_ns = %d,tracking_cnt = %d,holdover_cnt = %d,ft_new = %lx\n",diff_ns,g_stc_state.phase.tracking_cnt,g_stc_state.phase.holdover_cnt,ft_new); + + return diff_ns; +} + +/*phase_diff:相位差，单位 ns*/ +int32_t stc_adjust_sniffer_phase(int32_t phase_diff,uint32_t flag) +{ + uint64_t ft_new; + double delta; + int64_t diff = phase_diff; + uint32_t tod_lo,tod_mi; + uint64_t tod_second; + static uint32_t first_sync_flag = 0; + + if((flag)||(!first_sync_flag)) + { + first_sync_flag = 1; + + g_stc_regs_ptr->tod_reg_ft_lo = 0; //ft + g_stc_regs_ptr->tod_reg_ft_hi = 0; + //g_stc_regs_ptr->tod_reg_config &= 0xef;//clear tod_incr_en + + tod_lo = g_stc_regs_ptr->tod_reg_tod_lo; + tod_mi = g_stc_regs_ptr->tod_reg_tod_mi; + tod_second = g_stc_regs_ptr->tod_reg_tod_hi; + ft_new = ((tod_mi & 0xffff) << 16) | (tod_lo >> 16); + diff = (ft_new + 904) - diff; + tod_second = (tod_second << 16) | (tod_mi >> 16); + if(diff >= 1000000000) + { + diff -= 1000000000; + tod_second += 1; + } + else if(diff < 0) + { + diff += 1000000000; + tod_second -= 1; + } + tod_second += 1; + //g_stc_regs_ptr->tod_reg_su_lo = tod_second; + //g_stc_regs_ptr->tod_reg_su_hi = tod_second >> 32; //set su + + g_stc_regs_ptr->tod_reg_nsf_init_lo = 0; + g_stc_regs_ptr->tod_reg_nsf_init_hi = diff; //set nsf_init + /*g_stc_regs_ptr->tod_reg_int_status = 4; //clear hscc_dump(tod) int */ + g_stc_regs_ptr->tod_reg_ft_lo = g_stc_state.default_ft; // set ft + g_stc_regs_ptr->tod_reg_ft_hi = g_stc_state.default_ft >> 32; + + /*do{ + usleep(1000); + }while(!(g_stc_regs_ptr->tod_reg_int_status & 0x4)); //wait hscc_dump(tod) int + + g_stc_regs_ptr->tod_reg_config |= 0x10; //set tod_incr_en,TOD second auto add */ + UCP_PRINT_DEBUG("phase_diff = %d,tod_ns = %ld,diff = %ld",phase_diff,ft_new,diff); + + return STC_OK; + } + + if((phase_diff < SNIFFER_LOCK_THRESHOLD) && (phase_diff > -SNIFFER_LOCK_THRESHOLD)) + { + g_stc_state.phase.status = 1; + if(++g_stc_state.phase.tracking_cnt > STC_LOCK_CNT) + { + g_stc_state.phase.tracking_cnt = STC_LOCK_CNT; + g_stc_state.phase.holdover_cnt = 0; + g_stc_state.phase.disable_cnt = 0; + g_stc_state.state = CLK_TRACKING; + } + } + else + { + g_stc_state.phase.tracking_cnt = 0; + g_stc_state.phase.status = 0; + } + + diff <<= 32; + g_stc_state.phase.integral += diff; + + /*根据差值，设置Ft寄存器值，使|Rt-nsf|最小*/ + delta = g_stc_state.phase.p_ratio * diff + g_stc_state.phase.i_ratio * g_stc_state.phase.integral; + ft_new = g_stc_state.default_ft - delta * g_stc_state.phase.magic_num; +#ifdef SL_ADJ_FREQ + UCP_PRINT_DEBUG("phase_diff = %d,diff = %ld, ft_new = %#lx",phase_diff,diff,ft_new); +#endif + + g_stc_regs_ptr->tod_reg_ft_lo = ft_new & 0xffffffff; + g_stc_regs_ptr->tod_reg_ft_hi = ft_new >> 32; + + return STC_OK; +} + +uint32_t read_stc_local_timer() +{ + if(g_drv_mem_fd < 0) + { + g_drv_mem_fd = open("/dev/mem", O_RDWR|O_SYNC); + if(g_drv_mem_fd < 0) + { + UCP_PRINT_ERROR("open /dev/mem error"); + return LOGIC_ERROR1; + } + } + + if(g_stc_regs_ptr == NULL) + { + g_stc_regs_ptr = mmap(NULL, STC_REG_LEN, PROT_READ|PROT_WRITE, MAP_SHARED, + g_drv_mem_fd, STC_REG_BASE_ADDR); + if(-1 == (int64_t)g_stc_regs_ptr) + { + UCP_PRINT_ERROR("mmap stc regs error!! return = %ld\n",(uint64_t)g_stc_regs_ptr); + g_stc_regs_ptr = NULL; + return LOGIC_ERROR2; + } + } + + return *((uint32_t*)g_stc_regs_ptr + STC_LTBG_REG_OFFSET); +} + +int32_t set_clk_mode(clk_flag_e pseudo_flag) +{ + g_stc_state.pesudo_flag = pseudo_flag; + return STC_OK; +} + +/*------------------------------------------------------------------------------ +* +* Function Name: init_stc +* +* Input(s): +* +* +* Output(s): +* +* +* Returns: +* STC_OK; +* <0 +* +* Description: +* 实现STC模块初始化，包括中断使能等。由于芯片 +* 级驱动的初始化均采用默认配置，故在板级初始化时，针对特殊应用， +* 需调用芯片级驱动提供的相关配置接口，使芯片工作在稳定状态。 +* +------------------------------------------------------------------------------*/ +int32_t init_stc() +{ + if(1 == g_init_stc_flag) + { + return STC_OK; + } + + UCP_PRINT_DEBUG("stc version: %s",TFU_VER); + + if(STC_OK != map_stc_reg_space()) + { + UCP_PRINT_ERROR("map stc reg error!"); + return LOGIC_ERROR1; + } + + if(-1 == g_stc_fd) + { + g_stc_fd = open(STC_DEV_NAME,O_RDWR);//O_RDWR + if(-1 == g_stc_fd) + { + UCP_PRINT_ERROR("open stc-dev device failed!!!"); + return LOGIC_ERROR3; + } + } + + if(STC_OK != get_pclk_value()) + { + UCP_PRINT_ERROR("get pclk error!"); + return LOGIC_ERROR4; + } + else + { + set_rt_reg(0x3B9ACA00); + set_su_reg(100); + select_hscc_dump_source(EX_1PPS_IN); + select_xpps_in_source(GNSS_1PPS_IN); + set_ft_init_value(g_stc_state.p_clk); + //set_xpps_out_source(TOD_1PPS_OUT); + //select_xpps_in_source(GNSS_1PPS_IN); + //select_xpps_in_source(GMAC0_1PPS_IN); + //enable_stc_irq(STC_EX_1PPS_IN); + } + + g_init_stc_flag = 1; + + return STC_OK; +} + +uint32_t get_gmac_src_time() +{ + return *g_gmac0_tod_ptr; +} + +uint32_t get_tmac_src_time() +{ + return *g_tmac_tod_ptr; +} + +int32_t get_clock_module_status(volatile clock_module_status_s* clk_module_status_ptr) +{ + if(NULL == clk_module_status_ptr) + { + UCP_PRINT_ERROR("clk_module_status_ptr is null!"); + return LOGIC_ERROR1; + } + + clk_module_status_ptr->status = g_stc_state.state; + + if(TRUE_FLAG == g_stc_state.pesudo_flag) + { + clk_module_status_ptr->status = CLK_TRACKING; + } + + return STC_OK; +} + +stc_state_s * get_stc_state() +{ + return &g_stc_state; +} + +arm_stc_regs * get_stc_reg_base() +{ + return g_stc_regs_ptr; +} + +void * get_ap_gpio_reg_base() +{ + return g_ap_gpio_pinmux_regs_ptr; +} + + +/* End of stc_drv.c */ diff --git a/driver/tfu/ublox/inc/ublox_drv.h b/driver/tfu/ublox/inc/ublox_drv.h new file mode 100644 index 0000000..6a12d44 --- /dev/null +++ b/driver/tfu/ublox/inc/ublox_drv.h @@ -0,0 +1,568 @@ +/*------------------------------------------------------------ +// Copyright (c) 2022 SmartLogic. +// ALL RIGHTS RESERVED +// ----------------------------------------------------------------- +// Filename : stc_drv.c +// Author : weihua.li +// Created On : 2022-11-23 +// Last Modified : +// ----------------------------------------------------------------- +// Description: +// +// +// ----------------------------------------------------------------*/ + +#ifndef __UBLOX_DRV_H__ +#define __UBLOX_DRV_H__ + +#define GTM_OK 0 +#define GTM_ERROR -1 +#define GTM_YES 1 +#define GTM_NO 0 +#define GTM_NULL_PTR 0 + +#define GTM_MOD_ADD(augend, addend, modulus) \ + (((augend) + (addend)) % (modulus)) +#define GTM_MOD_SUB(minuend, subtrahend, modulus) \ + (((minuend) >= (subtrahend)) ? ((minuend) - (subtrahend)) : ((minuend) + (modulus) - (subtrahend))) + + +#define REVS16(x) x +#define REVS32(x) x + +#define IRQF_DISABLED 0x00000020 +#if 0 +#define REVS16(x) (uint16_t) ((((x) & 0xFF00)>>8)|(((x) & 0x00FF)<<8)) +#define REVS32(x) (uint32_t) ((((x) & 0xFF000000)>>24)|(((x) & 0x00FF0000)>>8)|\ + (((x) & 0x0000FF00)<<8)|(((x) & 0x000000FF)<<24)) +#endif +#define MIN(x,y) ((x)<(y)?(x):(y)) +#define MAX(x,y) ((x)>(y)?(x):(y)) + +#define GPS_SECONDS(tow,wnum) (604800*(wnum) + (tow)) +#define MOD_2N(x,y) ((x) & (y-1)) + + +#define GPS_FIX_OK 0x03 +#define NAV_ALMANACH 0x04 + +/*ublox sync header*/ +#define SYNC1_UBLOX 0xB5 +#define SYNC2_UBLOX 0x62 +#define UBLOX_SYNC_LEN 0x2 +#define INDEX_OF_PAYLOAD 0x6 //SYNC(2) + CLSID + MSGID + LENGTH(2) +#define UBLOX_CHECK_SUM_LEN 0x2 //2 BYTES +#define UBLOX_HEADER_SUM_LEN 0x8 //SYNC(2) + CLSID + MSGID + LENGTH(2) + CHECKSUM(2) +#define UBLOX_MSG_TOTAL_LEN(payload_len) ((payload_len) + UBLOX_HEADER_SUM_LEN) + +#define POLL_LENGTH 0 + +#define CFG_PRT_LEN 20 +#define PORT_NUMBER 1 + +/*----GPS Time Solution----*/ +#define NAV_TIMEGPS 0x20 +#define TIME_VALID 0x03 /*Time of Week and Week Number valid*/ +#define LEAP_VALID 0x04 /*Valid UTC (Leap Seconds already known)*/ + +/*--sat chn num--*/ +#define NUMCHN 20 +#define TOD_LINK_ALARM_VALUE 0x02 +#define ANT_OPEN_ALARM_VALUE 0x04 +#define ANT_SHORT_ALARM_VALUE 0x03 +#define GPS_ANT_SIGNAL_WEEK_ALARM_VALUE 0x05 +#define GPS_ANT_SIGNAL_STRONG_ALARM_VALUE 0x06 + +/*8bit ,1 stop bit , no portiy*/ +#define PORT_MODE_8N1 (0x3<<6)|(0x4<<9)|(0x0<<12) +#define PORT_BAUDRATE 9600 +#define PORT_PROTOCAL_IN 0x07 /*UBX+NMEA+RTCM2*/ +#define PORT_PROTOCAL_OUT 0x01 /*UBX*/ + +#define CFG_ANT_LEN 4 +#define ANT_FLAGS 0x1F + +#define CABDLY_DELAY_CRC_BYTE1 0xa5 +#define CABDLY_DELAY_CRC_BYTE2 0x5a +#define CABDLY_DELAY 12 //205 1m 4ns +#define CABLE_DELAY_ADDR 0x643800 +#define CABLE_DELAY_SIZE 2048 + +#define CFG_TP_LEN 20 +#define CFG_TP5_LEN 32 +#define TP_IDX0 0 +#define TP_IDX11 1 +#define TP_INTERVAL 1000000 //1s +#define TP_POSITIVE 1 +#define TP_NEGATIVE -1 +#define TP_TIME_GPS 1 +#define TP_TIME_UTC 0 +#define TP_PLUSE_WIDTH 1000 //1ms + +#define CFG_NAV5_LEN 36 +#define NAV5_FIXMODE 2 +#define NAV5_PACC 100 +#define NAV5_TACC 100 + +#define CFG_MSG_LEN 3 + +/*--ublox max message length--*/ +#define UBLOX_MAX_MEG_LENGTH 280 +#define UBLOX_MIN_MEG_LENGTH 10 +#define UBLOX_CABDLY 205 + + +/*class id and msg id*/ +#define ACK 0x05 +#define ACK_ACK 0x01 +#define ACK_NACK 0x00 + +#define NAV 0x01 +#define NAV_AOPSTATUS 0x60 +#define NAV_CLOCK 0x22 +#define NAV_DGPS 0x31 +#define NAV_DOP 0x04 +#define NAV_EKFSTATUS 0x40 +#define NAV_POSECEF 0x01 +#define NAV_POSLLH 0x02 +#define NAV_SBAS 0x32 +#define NAV_SOL 0x06 +#define NAV_STATUS 0x03 +#define NAV_SVINFO 0x30 +#define NAV_TIMEGPS 0x20 +#define NAV_TIMEUTC 0x21 +#define NAV_VELECEF 0x11 +#define NAV_VELNED 0x12 + +#define CFG 0x06 +#define CFG_ANT 0x13 +#define CFG_CFG 0x09 +#define CFG_DAT 0x06 +#define CFG_EKF 0x12 +#define CFG_ESFGWT 0x29 +#define CFG_FXN 0xE +#define CFG_INF 0x2 +#define CFG_ITFM 0x39 +#define CFG_MSG 0x1 +#define CFG_NAV5 0x24 +#define CFG_NAVX5 0x23 +#define CFG_NMEA 0x17 +#define CFG_NVS 0x22 +#define CFG_PM2 0x3B +#define CFG_PM 0x32 +#define CFG_PRT 0x00 +#define CFG_RATE 0x8 +#define CFG_RINV 0x34 +#define CFG_RST 0x4 +#define CFG_RXM 0x11 +#define CFG_SBAS 0x16 +#define CFG_TMODE2 0x3D +#define CFG_TMODE 0x1D +#define CFG_TP5 0x31 +#define CFG_TP 0x7 +#define CFG_USB 0x1B + +#define CFG_RST_LEN 4 +#define RST_NAVBBR_COLD 0xFFFF +#define RST_MODE_HW 0x00 + +#define MON 0x0a +#define MON_HW2 0xb +#define MON_HW 0x9 +#define MON_IO 0x2 +#define MON_MSGPP 0x6 +#define MON_RXBUF 0x7 +#define MON_RXR 0x21 +#define MON_TXBUF 0x8 +#define MON_VER 0x4 + +/*close name mes*/ +#define NMEA 0xf0 +#define RMC 0x04 +#define VTG 0x05 +#define GGA 0x00 +#define GSA 0x02 +#define GSV 0x03 +#define GLL 0x01 +#define ZDA 0x08 + +#define GPS_TIME_JUMP_20MIN 1200 /* 60*20 */ +#define HOLD_OVER_TIME_UNIT 900 /* 15*60 */ + +/*#define FPGA_BASE_ADDR 0x74000000*/ +#define PHASE_DIFF_COUNT_L_REG 0xe +#define PHASE_DIFF_COUNT_H_REG 0xd +#define PHASE_DIFF_FLAG_REG 0xf +#define PP2S_SYNC_EN_REG 0xb + +#define PP2S_CTRL 0xc +#define PHASE_FLAG 0xf /*1:ǰ 0:ͺ*/ +#define SYNC_EN_FLAG 0x01 +#define PP2S_COUNTER_ADV 0x10 /*ǰ*/ +#define PP2S_COUNTER_DELAY 0x11 /*ͺ*/ + +#define PP2S_ADV_PPS_MASK 0x8000 +#define PP2S_PPS_PHD_ABS 0x7FFF + +#define CPU_TIMER_MASK 15 +#define AD9548_M 6 + + +/* should be update when hardware changed */ +#define PH_ERR_NS 8 /*1000/122.88M ~= 8.138*/ +#define PH_SYNC 15 /*122.88/5 ~= 25*/ +#define PH_FSYNC 18 /*122.88/20.48*3 = 18*/ +#define PH_LIMIT_1 120 +#define PH_LIMIT_2 130 + +#define HOLD_OVER_IN 90 /* 3*30 = 90 gpsʧÿ3sһpp1sź*/ +#define HOLD_OVER_1_HOUR 3600 /* 60*60 */ +#define HOLD_OVER_1_DAY 86400/* 3600*24 */ + +#define UBX_SEM_NUM 13 + +#define MY_IPCKEY 0x10005500 + +#define TX_SEMA_NAME "tx_sema" +typedef void (*FUNCPTR)(void *); + +#define UBLOX_TX_BUF_SIZE 256 +#define UBLOX_RX_BUF_SIZE 1024 +#define HALF_BUFSIZE 511 +#define RT_MASK 1023 //(RTBUFSIZE - 1) + +/*-----some get/set types protocols' sem-------*/ +typedef enum +{ + CFG_PRT_SEM, + CFG_MSG_SEM, + CFG_TP_SEM, + CFG_CFG_SEM, + CFG_ANT_SEM, + CFG_NAV5_SEM, + CFG_RST_SEM, + NAV_POSLLH_SEM, + NAV_STATUS_SEM, + NAV_GPSTIME_SEM, + NAV_SVINFO_SEM, + MON_HW_SEM, + MON_VER_SEM +}ubx_sem_e; + +/* arg for semctl system calls. */ +union semun { + int val; /* value for SETVAL */ + struct semid_ds *buf; /* buffer for IPC_STAT & IPC_SET */ + unsigned short *array; /* array for GETALL & SETALL */ + struct seminfo *__buf; /* buffer for IPC_INFO */ +}; + +typedef struct +{ + uint16_t reg_addr; + uint8_t reg_val; +}reg_value_s; + +//typedef unsigned int time_t;/*32bit*/ +typedef void irqreturn_t; +typedef irqreturn_t (*irq_handler_t)(int, void *); +/*Start of repeated block (numCh times) in payload of NAV-SVINFO*/ +typedef struct +{ + uint8_t chn; /*Channel number*/ + uint8_t svid; /*Satellite ID*/ + uint8_t flags; /*Bitmask,bit2,Orbit information is available for this SV (Ephemeris or Almanach)*/ + uint8_t quality; /**/ + uint8_t cno; /*Carrier to Noise Ratio (Signal Strength)*/ + int8_t elev; /*Elevation in integer degrees*/ + int16_t azim; /*Azimuth in integer degrees*/ + int32_t prres; /*Pseudo range residual in centimetres*/ +}__attribute__((packed)) chn_info_s; + + +/*gps消息结构体*/ +typedef struct +{ + uint8_t cls_id; + uint8_t msg_id; + uint16_t length; + + union + { + /*Class NAV 0X01--------------------------------- */ + /*Message NAV-POSLLH 0X02*/ + struct + { + uint32_t i_tow; /*gps millsecond time of week,ms*/ + int32_t lon; /* longitude,deg scaling: 1e-7*/ + int32_t lat; /*latitude,deg scaling: 1e-7*/ + int32_t height; /*Height above Ellipsoid,mm*/ + int32_t hmsl; /*Height above mean sea level,mm*/ + uint32_t hacc; /*Horizontal Accuracy Estimate,mm*/ + uint32_t vacc; /*Vertical Accuracy Estimate,mm*/ + }__attribute__((packed)) nav_pos; + /*message NAV-STATUS 0x03*/ + struct + { + uint32_t i_tow; + uint8_t gps_fix; /*GPSfix Type,0x00 no fix,others */ + uint8_t flags; /*bit0:gpsFixOk,bit1:1 if DGPS used,bit2:1 if Week Number valid,bit3:1 if Time of Week valid*/ + uint8_t diff_stat; + uint8_t res; + uint32_t ttff; /*Time to first fix (millisecond time tag)*/ + uint32_t msss; /*Milliseconds since Startup / Reset*/ + }__attribute__((packed)) nav_status; + /*message NAV-TIMEGPS*/ + struct + { + uint32_t i_tow; + int32_t f_low; /* Fractional Nanoseconds remainder of rounded ms above,*/ + int16_t week; /*GPS week (GPS time)*/ + int8_t leap; /*Leap Seconds (GPS-UTC)*/ + uint8_t valid; /*Validity Flags,bit0=1Valid Time of Week,bit1=1 Valid Week Number,bit2=1 Valid Leap Seconds,*/ + uint32_t vacc; /*Time Accuracy Estimate*/ + }__attribute__((packed)) nav_timegps; + /*message NAV-SVINFO*/ + struct + { + uint32_t i_tow; + uint8_t num_ch; /*Number of channels*/ + uint8_t global_flags; + uint16_t res; + chn_info_s chn_info; + }__attribute__((packed)) nav_svinfo; + + /*--------------------------------------------------------*/ + /*----class ACK---------*/ + /*--message ACK-(NAK 0X00 or ACK 0X01)--*/ + struct + { + uint8_t clsid; /*Class ID of the Not-Acknowledged/Acknowledged Message*/ + uint8_t msgid; /*Message ID of the Not-Acknowledged/Acknowledged Message*/ + }__attribute__((packed)) ack_msg; + /*--------------------------------------------------------*/ + /*----class CFG 0X06---------*/ + /*--message CFG-PRT 0X00 (Get/Set Port Configuration for UART)--*/ + struct + { + uint8_t portid; /*Port Identifier Number (= 1 or 2 for UART ports)*/ + uint8_t res0; + uint16_t res1; + uint32_t mode; /*A bit mask describing the UART mode, bit7-bit6=11(8bit),*/ + uint32_t baudrate; /*Baudrate in bits/second*/ + uint16_t inportmask; /*A mask describing which input protocols are active.bit0=UBX*/ + uint16_t outportmask; /*A mask describing which output protocols are active.*/ + uint16_t flags; + uint16_t pad; + }__attribute__((packed)) config_port; + /*--message CFG-MSG 0X01 --*/ + struct + { + uint8_t cls; + uint8_t msgid; + uint8_t rate; + }__attribute__((packed))config_msg; + + /*--Message CFG-RST 0X04--*/ + struct + { + uint16_t nav_bbr; + uint8_t rst_mode; + uint8_t res; + }__attribute__((packed)) config_rst; +#if 0 + /*--message CFG-TP 0X07(Get/Set TimePulse Parameters)--*/ + struct + { + uint32_t interval; /*Time interval for time pulse*/ + uint32_t length; /*Length of time pulse*/ + int8_t status; /*Time pulse config setting,>0 positive,=0 off,<0 negative*/ + uint8_t time_ref; /*Tlignment to reference time,0=UTC time,1=GPS time*/ + uint8_t flags; /*bit0=1 TP allowed to be asynchronized and available even when time is not valid*/ + uint8_t res; + int16_t cab_dly; /*Antenna Cable Delay*/ + int16_t rf_grp_dly; /*Receiver RF Group Delay*/ + int32_t user_dly; /*User Time Function Delay (positive delay results in earlier pulse)*/ + }__attribute__((packed)) config_tp; +#endif + struct + { + uint8_t tp_idx; + uint8_t version; + uint8_t rsv[2]; /*reserved*/ + int16_t cab_dly; /*Antenna Cable Delay: ns*/ + int16_t rf_dly; /*RF group delay: ns*/ + uint32_t freq_period; /*pulse frequence or period: Hz_us*/ + uint32_t freq_period_locked; /*pulse frequence or period when locked to GNSS: Hz_us*/ + uint32_t pulse_len; /*pulse width or duty: us_%*/ + uint32_t pulse_len_locked; /*pulse width or duty when locked to GNSS: us_%*/ + int32_t user_delay; /*user-configurable time pulse delay: ns*/ + uint32_t active:1; + uint32_t lock_gnss_freq:1; + uint32_t lock_other_set:1; + uint32_t is_freq:1; + uint32_t is_length:1; + uint32_t align2tow:1; + uint32_t polarity:1; + uint32_t grid_utc_gnss:4; + uint32_t sync_mode:3; + uint32_t flag_rsv:18; + }__attribute__((packed)) config_tp5; + /*--message CFG-NAV5 Get/Set Navigation Engine Settings--*/ + struct + { + uint16_t mask; /*Parameters Bitmask.*/ + uint8_t dyn_model; /*Dynamic Platform model:*/ + uint8_t fix_mode; /*Position Fixing Mode.*/ + int32_t fixed_alt; /*Fixed altitude*/ + uint32_t fixed_alt_var; /*Fixed altitude variance for 2D mode.*/ + int8_t min_elev; /*Minimum Elevation for a GNSS satellite to be used in NAV*/ + uint8_t drlimit; /*Maximum time to perform dead reckoning*/ + uint16_t pdop; /*Position DOP Mask to use*/ + uint16_t tdop; /*Time DOP Mask to use*/ + uint16_t pacc; /* Position Accuracy Mask */ + uint16_t tacc; /* Time Accuracy Mask */ + uint8_t static_hold_thresh; /* Static hold threshold */ + uint8_t dgps_time_out; /* DGPS timeout */ + uint32_t res2; /* reserved, set to 0 */ + uint32_t res3; /* reserved, set to 0 */ + uint32_t res4; /* reserved, set to 0 */ + }__attribute__((packed)) config_nav5; + /*--message CFG-CFG 0X09 (Clear, Save and Load configurations)--*/ + struct + { + uint32_t clearmask; + uint32_t savemask; + uint32_t loadmask; + }__attribute__((packed)) config_cfg; + + /*--message CFG-ANT 0X13 (Get/Set Antenna Control Settings)--*/ + struct + { + uint16_t flags; + uint16_t pins;/*READ-ONLY,when get*/ + }__attribute__((packed)) config_ant; + /*---------------------------------------------------------------*/ + /*--class MON 0x0A--*/ + /*--Message MON-HW0x09--*/ + struct + { + uint32_t pinsel; + uint32_t pinbank; + uint32_t pindir; + uint32_t pinvar; + uint16_t noiseperms; + uint16_t agccnt; + uint8_t astatus; + uint8_t apower; + uint8_t flags; + uint8_t res1; + uint32_t usedmask; + uint8_t vp[25]; + uint8_t res2[3]; + uint32_t pinirq; + uint32_t pullh; + uint32_t pulll; + }__attribute__((packed)) monitor_hw; + struct + { + uint8_t sw_version[30]; + uint8_t hw_version[10]; + /* + uint8_t rom_version[30]; + uint8_t extension[30]; + */ + }__attribute__((packed)) monitor_ver; + /*--------------------------------------------------------*/ + }__attribute__((packed))pay_load; +}__attribute__((packed)) ubx_msg_s; + +typedef struct +{ + int32_t latitude; /*degree 1e-7*/ + int32_t longitude;/*degree 1e-7*/ + int32_t altitude; /*millimeter*/ + uint8_t gps_fix; + uint8_t fix_flag; + uint32_t time_of_week; + uint8_t valid_flag; + int8_t leap_sec; + uint16_t week_number; + uint8_t num_ch; + int16_t cab_dly; /*cable delay time,uint:ns*/ + uint32_t pulse_width; /*Length of time pulse*/ + int8_t pps_status; /*PPS: >0,postive; =0,no;<0, negative*/ + uint8_t ant_state; + uint8_t sw_version[30]; + uint8_t hw_version[10]; + uint8_t sta_id[NUMCHN]; /*satellite ID*/ + uint8_t cno[NUMCHN]; /*Carrier to Noise Ratio (Signal Strength)*/ + uint8_t tracking_num; + uint8_t visable_num; + uint8_t sig_over_high; + uint8_t lock_state; /*1: gps lock 0: gps unlock*/ + +}drv_gps_msg_s; + +/********************************************************************/ +typedef struct +{ + uint8_t recv_buf[UBLOX_RX_BUF_SIZE]; + /*union + { + uint32_t whole; + struct + { + uint16_t recv_ptr; //接收指针 + uint16_t deal_ptr; //处理指针 + } + }*/ + uint16_t recv_ptr; /*接收指针*/ + uint16_t deal_ptr; /*处理指针*/ + uint16_t recv_cnt; /*最新接收到的消息长度*/ + uint16_t deal_cnt; /*未处理消息长度*/ + int32_t send_sem; + ubx_msg_s *send_buf_ptr; + uint16_t send_cnt; /*待发送消息长度*/ + uint16_t frame_flag; //帧头 +}ublox_uart_s; + +typedef struct +{ + int32_t latitude; //纬度 单位：度/1e-7 + int32_t longitude; //经度 单位：度/1e-7 + int32_t altitude; //高度 单位：毫米 +}location_info_s; + +typedef struct +{ + uint8_t lock_flag; /* GPS Fixed ok */ + uint8_t leap_valid; /* leap second valid */ + uint8_t view_sats; /* Satellites in view */ + uint8_t track_sats; /* Satellites under tracking */ + uint8_t survey_in; /*0 not in Survey-in mode*/ + uint8_t alma_complete; /* 0 Calendar not complete */ + uint8_t resv[2]; /* resv*/ + float sig_level[12]; /* signal level of satellites */ +}tracking_info_s; + +void drv_gps_recv_task(void); +int32_t drv_uart_read(uint8_t *pdata, uint32_t len); +int32_t init_clock_module(void); +int32_t drv_tfu_receiver_init(void); +int32_t get_receiver_fix_status(); +int32_t get_src_time(time_t* time_ptr); +int32_t drv_tfu_get_ublox_seconds(time_t* sec_ptr); +int32_t get_tfu_location_info(location_info_s *locat_ptr); +int32_t get_clock_tracking_state(tracking_info_s *trk_ptr); +int32_t reset_clock_module(void); + + +#ifdef __cplusplus + #if __cplusplus + } + #endif +#endif + +#endif +/**********************************************************************/ diff --git a/driver/tfu/ublox/src/ublox_drv.c b/driver/tfu/ublox/src/ublox_drv.c new file mode 100644 index 0000000..95cda69 --- /dev/null +++ b/driver/tfu/ublox/src/ublox_drv.c @@ -0,0 +1,1791 @@ +/*------------------------------------------------------------ +// Copyright (c) 2022 SmartLogic. +// ALL RIGHTS RESERVED +// ----------------------------------------------------------------- +// Filename : stc_drv.c +// Author : weihua.li +// Created On : 2022-11-23 +// Last Modified : +// ----------------------------------------------------------------- +// Description: +// +// +// ----------------------------------------------------------------*/ +#define _GNU_SOURCE +#include +#include +#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include +#include "typedef.h" +#include "ucp_printf.h" +#include "ublox_drv.h" + +drv_gps_msg_s g_gps_recv_msg; +int32_t g_gps_recv_task_id = -1; + + +uint8_t g_tx_buf[UBLOX_TX_BUF_SIZE] = {SYNC1_UBLOX,SYNC2_UBLOX}; +ublox_uart_s g_ublox_uart = +{ + .recv_ptr = 0, + .deal_ptr = 0, + .recv_cnt = 0, + .deal_cnt = 0, + .send_cnt = 0, + .send_buf_ptr = (ubx_msg_s*)(g_tx_buf + 2), +}; + +uint8_t g_almanach_flag; /*Almanach flag*/ +int32_t g_ubx_sem[UBX_SEM_NUM]; +uint32_t g_tod_link_alarm = 0; +int32_t g_tfu_sync_sem = -1; //pp1s中断同步信号量 +int32_t g_tfu_to_time_sem = 0; //tracking后释放给OM，计算帧号 +int32_t g_tfu_init_flag = 0; +int32_t drv_uart_fd = -1; +int32_t g_sem_prj_id = 20; + +extern void drv_tfu_phase_adjust(uint8_t count); +extern int32_t drv_semaphore_p(int32_t sem_id); +static int32_t drv_semaphore_timed_p(int32_t sem_id,int32_t timeout_us); +static int32_t drv_semaphore_v(int32_t sem_id); + +extern void drv_set_odd_flag(uint8_t flag);/*1:odd 2:even*/ +int32_t drv_thread_create(uint8_t* pthread_name, uint8_t thread_prio, uint32_t thread_size, void *callback, void* pArg); + +int32_t drv_sem_create(int32_t prj_id) +{ + key_t key; + int32_t sem_id; + union semun sem_union; + + //key = ftok(MY_IPCKEY,prj_id); + key = MY_IPCKEY + prj_id; + sem_id = semget((key_t)key, 1, IPC_CREAT); + if(-1 == sem_id) + { + UCP_PRINT_ERROR("semget error sem_id:%d err = %s!\n\r",sem_id,strerror(errno)); + return OSP_ERROR; + } + + sem_union.val = 1; + if(semctl(sem_id, 0, SETVAL, sem_union) == -1) + { + UCP_PRINT_ERROR("semctl error\n\r"); + return OSP_ERROR; + } + + return sem_id; +} + +int32_t drv_sem_create_sync(int32_t prj_id) +{ + key_t key; + int32_t sem_id; + union semun sem_union; + + //key = ftok(MY_IPCKEY,prj_id); + key = MY_IPCKEY + prj_id; + sem_id = semget((key_t)key, 1, IPC_CREAT); + if(-1 == sem_id) + { + UCP_PRINT_ERROR("semget error sem_id:%d err = %s!\n\r",sem_id,strerror(errno)); + return OSP_ERROR; + } + + sem_union.val = 0; + if(semctl(sem_id, 0, SETVAL, sem_union) == -1) + { + UCP_PRINT_ERROR("semctl error\n\r"); + return OSP_ERROR; + } + + return sem_id; +} + +int32_t drv_semaphore_p(int32_t sem_id) +{ + struct sembuf sem_p; + sem_p.sem_num = 0; + sem_p.sem_op = -1; + sem_p.sem_flg = SEM_UNDO; + + if(semop(sem_id, &sem_p, 1) == -1) + { + UCP_PRINT_ERROR("semaphore_p failed err=%s \n\r",strerror(errno)); + return OSP_ERROR; + } + + return OSP_OK; +} + +static int32_t drv_semaphore_timed_p(int32_t sem_id,int32_t timeout_us) +{ + struct sembuf sem_p; + struct timespec time; + int32_t temp = timeout_us; + + if(temp >= 1000000) + { + time.tv_sec = temp/1000/1000; + temp = temp%1000000; + } + else + { + time.tv_sec = 0; + } + + time.tv_nsec = temp*1000; + + sem_p.sem_num = 0; + sem_p.sem_op = -1; + sem_p.sem_flg = SEM_UNDO; + + if(semtimedop(sem_id, &sem_p, 1,&time) == -1) + { + UCP_PRINT_ERROR("semtimedop failed"); + return OSP_ERROR; + } + + return OSP_OK; +} + + +static int32_t drv_semaphore_v(int32_t sem_id) +{ + struct sembuf sem_b; + + sem_b.sem_num = 0; + sem_b.sem_op = 1; + sem_b.sem_flg = SEM_UNDO; + if(semop(sem_id, &sem_b, 1) == -1) + { + UCP_PRINT_ERROR("semaphore_v failed sem_id%d err = %s! \n\r",sem_id, strerror(errno)); + return OSP_ERROR; + } + return OSP_OK; +} + +int32_t set_opt(int32_t fd,int32_t nSpeed, int32_t nBits, int8_t nEvent, int32_t nStop) +{ + struct termios newtio,oldtio; + + if ( tcgetattr( fd,&oldtio) != 0) + { + perror("SetupSerial error"); + UCP_PRINT_ERROR("SetupSerial error\n\r"); + return -1; + } + + bzero( &newtio, sizeof( newtio ) ); + newtio.c_cflag |= CLOCAL | CREAD; + newtio.c_cflag &= ~CSIZE; + + switch( nBits ) + { + case 7: + newtio.c_cflag |= CS7; + break; + case 8: + newtio.c_cflag |= CS8; + break; + } + + switch( nEvent ) + { + case 'O': + newtio.c_cflag |= PARENB; + newtio.c_cflag |= PARODD; + newtio.c_iflag |= (INPCK | ISTRIP); + break; + case 'E': + newtio.c_iflag |= (INPCK | ISTRIP); + newtio.c_cflag |= PARENB; + newtio.c_cflag &= ~PARODD; + break; + case 'N': + newtio.c_cflag &= ~PARENB; + break; + } + + switch( nSpeed ) + { + case 2400: + cfsetispeed(&newtio, B2400); + cfsetospeed(&newtio, B2400); + break; + case 4800: + cfsetispeed(&newtio, B4800); + cfsetospeed(&newtio, B4800); + break; + case 9600: + cfsetispeed(&newtio, B9600); + cfsetospeed(&newtio, B9600); + break; + case 115200: + cfsetispeed(&newtio, B115200); + cfsetospeed(&newtio, B115200); + break; + default: + cfsetispeed(&newtio, B9600); + cfsetospeed(&newtio, B9600); + break; + } + + if( nStop == 1 ) + { + newtio.c_cflag &= ~CSTOPB; + } + else if ( nStop == 2 ) + { + newtio.c_cflag |= CSTOPB; + } + newtio.c_cc[VTIME] = 1; //100ms + newtio.c_cc[VMIN] = 64; //60; + tcflush(fd,TCIFLUSH); + if((tcsetattr(fd,TCSANOW,&newtio))!=0) + { + perror("com set error"); + UCP_PRINT_ERROR("com set error\n\r"); + return -1; + } + UCP_PRINT_DEBUG("set done!\n"); + return 0; +} + + +static int drv_tfu_uart_send (uint8_t *pdata, uint32_t len) +{ + int32_t write_count = 0; + if((NULL == pdata)|(0 == len)) + { + UCP_PRINT_ERROR("uart send para error"); + return OSP_ERROR; + } + + write_count = write(drv_uart_fd,pdata,len); + + if(write_count < len) + { + UCP_PRINT_ERROR("uart send error write_count=%d,len=%d",write_count,len); + return OSP_ERROR; + } + + return OSP_OK; +} + +static int32_t drv_send_ublox_msg(void) +{ + uint32_t i; + uint8_t ck_a = 0, ck_b = 0; + uint16_t pld_len, pld_end; + int32_t result = 0; + + pld_len = REVS16(g_ublox_uart.send_buf_ptr->length); + + /*calc checksum */ + pld_end = pld_len + INDEX_OF_PAYLOAD; + for(i = 2; i < pld_end; ++i) + { + ck_a += g_tx_buf[i]; + ck_b += ck_a; + } + g_tx_buf[pld_end] = ck_a; + g_tx_buf[pld_end + 1] = ck_b; + + result = drv_tfu_uart_send(g_tx_buf, pld_end + 2); + memset(g_tx_buf + 2, 0, UBLOX_TX_BUF_SIZE - 2); + if(OSP_ERROR == result) + { + UCP_PRINT_ERROR("uart send msg error"); + return OSP_ERROR; + } + return OSP_OK; +} + + +int32_t drv_tfu_get_port_cfg(void) +{ + int32_t result = OSP_ERROR; + + drv_semaphore_p(g_ublox_uart.send_sem);/* get tx sem*/ + g_ublox_uart.send_buf_ptr->cls_id = CFG; + g_ublox_uart.send_buf_ptr->msg_id = CFG_PRT; + g_ublox_uart.send_buf_ptr->length = REVS16(POLL_LENGTH); + result = drv_send_ublox_msg(); + if(OSP_ERROR == result) + { + UCP_PRINT_ERROR("send ublox msg error\n\r"); + //******************************* + drv_semaphore_v(g_ublox_uart.send_sem);/*send tx sem*/ + return OSP_ERROR; + } + drv_semaphore_v(g_ublox_uart.send_sem);/*send tx sem*/ + if(OSP_OK != drv_semaphore_timed_p(g_ubx_sem[CFG_PRT_SEM], 3*1000000)) + { + UCP_PRINT_ERROR("tfu: gps not reply! %s\n", __FUNCTION__); + g_tod_link_alarm = 1; + return OSP_ERROR; + } + else + { + g_tod_link_alarm = 0; + } + + return OSP_OK; +} + + +int32_t drv_tfu_set_port_cfg(void) +{ + int32_t result = 0; + + drv_semaphore_p(g_ublox_uart.send_sem); + g_ublox_uart.send_buf_ptr->cls_id = CFG; + g_ublox_uart.send_buf_ptr->msg_id = CFG_PRT; + g_ublox_uart.send_buf_ptr->length = REVS16(CFG_PRT_LEN); + g_ublox_uart.send_buf_ptr->pay_load.config_port.portid = PORT_NUMBER; + g_ublox_uart.send_buf_ptr->pay_load.config_port.res0 = 0; + g_ublox_uart.send_buf_ptr->pay_load.config_port.res1 = 0; + g_ublox_uart.send_buf_ptr->pay_load.config_port.mode = REVS32(PORT_MODE_8N1); + g_ublox_uart.send_buf_ptr->pay_load.config_port.baudrate = REVS32(PORT_BAUDRATE); + g_ublox_uart.send_buf_ptr->pay_load.config_port.inportmask = REVS16(PORT_PROTOCAL_IN); + g_ublox_uart.send_buf_ptr->pay_load.config_port.outportmask = REVS16(PORT_PROTOCAL_OUT); + g_ublox_uart.send_buf_ptr->pay_load.config_port.flags = 0; + g_ublox_uart.send_buf_ptr->pay_load.config_port.pad = 0; + result = drv_send_ublox_msg(); + if(OSP_ERROR == result) + { + UCP_PRINT_ERROR("send ublox msg error\n\r"); + //******************************* + drv_semaphore_v(g_ublox_uart.send_sem); + return OSP_ERROR; + } + drv_semaphore_v(g_ublox_uart.send_sem); + + if(OSP_OK != drv_semaphore_timed_p(g_ubx_sem[CFG_PRT_SEM], 2*1000000)) + { + UCP_PRINT_ERROR("tfu: no response to %s!\n", __FUNCTION__); + g_tod_link_alarm = 1; + return OSP_ERROR; + } + else + { + g_tod_link_alarm = 0; + } + return OSP_OK; +} + +int32_t drv_tfu_set_ant_cfg(void) +{ + int32_t result = 0; + + /*drv_semaphore_p(g_ublox_uart.send_sem); + + g_ublox_uart.send_buf_ptr->cls_id = CFG; + g_ublox_uart.send_buf_ptr->msg_id = CFG_ANT; + g_ublox_uart.send_buf_ptr->length = POLL_LENGTH; + + result = drv_send_ublox_msg(); + if(OSP_ERROR == result) + { + UCP_PRINT_ERROR("poll ant cfg : send ublox msg error\n\r"); + drv_semaphore_v(g_ublox_uart.send_sem); + return OSP_ERROR; + } + + drv_semaphore_v(g_ublox_uart.send_sem); + + if(OSP_OK != drv_semaphore_timed_p(g_ubx_sem[CFG_ANT_SEM], 2*1000000)) + { + UCP_PRINT_ERROR("poll ant cfg error\n\r"); + g_tod_link_alarm = 1; + return OSP_ERROR; + } + else + { + g_tod_link_alarm = 0; + }*/ + + drv_semaphore_p(g_ublox_uart.send_sem); + + g_ublox_uart.send_buf_ptr->cls_id = CFG; + g_ublox_uart.send_buf_ptr->msg_id = CFG_ANT; + g_ublox_uart.send_buf_ptr->length = REVS16(CFG_ANT_LEN); + g_ublox_uart.send_buf_ptr->pay_load.config_ant.flags = REVS16(ANT_FLAGS); + g_ublox_uart.send_buf_ptr->pay_load.config_ant.pins = REVS16(0xb9f0); + + result = drv_send_ublox_msg(); + drv_semaphore_v(g_ublox_uart.send_sem); + if(OSP_OK != result) + { + UCP_PRINT_ERROR("ant cfg: send ublox msg error"); + return OSP_ERROR; + } + + if(OSP_OK != drv_semaphore_timed_p(g_ubx_sem[CFG_ANT_SEM], 2*1000000)) + { + UCP_PRINT_ERROR("set_ant_cfg error\n\r"); + return OSP_ERROR; + } + else + { + g_tod_link_alarm = 0; + } + + return OSP_OK; +} + + +int32_t drv_tfu_set_tp_cfg(uint32_t tp_width, int8_t pps_polarity,int16_t cab_delay) +{ + int32_t result = 0; + + drv_semaphore_p(g_ublox_uart.send_sem); + + g_ublox_uart.send_buf_ptr->cls_id = CFG; + g_ublox_uart.send_buf_ptr->msg_id = CFG_TP5; + g_ublox_uart.send_buf_ptr->length = REVS16(CFG_TP5_LEN); + g_ublox_uart.send_buf_ptr->pay_load.config_tp5.tp_idx = TP_IDX0; + g_ublox_uart.send_buf_ptr->pay_load.config_tp5.cab_dly = REVS16(cab_delay); + g_ublox_uart.send_buf_ptr->pay_load.config_tp5.rf_dly = REVS16(0); + g_ublox_uart.send_buf_ptr->pay_load.config_tp5.freq_period = REVS16(TP_INTERVAL); + g_ublox_uart.send_buf_ptr->pay_load.config_tp5.freq_period_locked = REVS16(TP_INTERVAL); + g_ublox_uart.send_buf_ptr->pay_load.config_tp5.pulse_len = REVS16(0); //no pulse before ublox locked + g_ublox_uart.send_buf_ptr->pay_load.config_tp5.pulse_len_locked = REVS16(tp_width); + g_ublox_uart.send_buf_ptr->pay_load.config_tp5.user_delay = REVS16(0); + g_ublox_uart.send_buf_ptr->pay_load.config_tp5.active = 1; + g_ublox_uart.send_buf_ptr->pay_load.config_tp5.lock_gnss_freq = 1; + g_ublox_uart.send_buf_ptr->pay_load.config_tp5.lock_other_set = 1; + g_ublox_uart.send_buf_ptr->pay_load.config_tp5.is_freq = 0; //us + g_ublox_uart.send_buf_ptr->pay_load.config_tp5.is_length = 1; //us + g_ublox_uart.send_buf_ptr->pay_load.config_tp5.align2tow = 1; + g_ublox_uart.send_buf_ptr->pay_load.config_tp5.polarity = pps_polarity; + g_ublox_uart.send_buf_ptr->pay_load.config_tp5.grid_utc_gnss = TP_TIME_GPS; + + result = drv_send_ublox_msg(); + if(OSP_ERROR == result) + { + UCP_PRINT_ERROR("set tp cfg: send ublox msg error\n\r"); + drv_semaphore_v(g_ublox_uart.send_sem); + return OSP_ERROR; + } + + drv_semaphore_v(g_ublox_uart.send_sem); + + if(OSP_OK != drv_semaphore_timed_p(g_ubx_sem[CFG_TP_SEM], 2*1000000)) + { + g_tod_link_alarm = 1; + return OSP_ERROR; + } + else + { + g_tod_link_alarm = 0; + } + return OSP_OK; +} + + +int32_t set_cable_time_delay(int16_t delay_time) +{ + int32_t result = 0; + + /*--get g_pulse_width ,and then be writed agian--*/ + drv_semaphore_p(g_ublox_uart.send_sem); + + g_ublox_uart.send_buf_ptr->cls_id = CFG; + g_ublox_uart.send_buf_ptr->msg_id = CFG_TP5; + g_ublox_uart.send_buf_ptr->length = POLL_LENGTH; + + result = drv_send_ublox_msg(); + if(OSP_ERROR == result) + { + UCP_PRINT_ERROR("set cabdelay : send ublox msg error\n\r"); + drv_semaphore_v(g_ublox_uart.send_sem); + return OSP_ERROR; + } + + drv_semaphore_v(g_ublox_uart.send_sem); + + if(OSP_OK != drv_semaphore_timed_p(g_ubx_sem[CFG_TP_SEM], 2*1000000)) + { + return OSP_ERROR; + } + else + { + g_tod_link_alarm = 0; + } + + if(OSP_OK != drv_tfu_set_tp_cfg(TP_PLUSE_WIDTH, TP_POSITIVE, delay_time)) + { + return OSP_ERROR; + } + return OSP_OK; +} + +#if 0 +int32_t get_cable_time_delay(int16_t* delay_time_ptr) +{ + + uint8_t cable_delay[8] = {0}; + uint32_t flash_result = -1; + + if(NULL == delay_time_ptr) + { + UCP_PRINT_ERROR("tfu: %s, delay_time_ptr is NULL.\n", __FUNCTION__); + return OSP_ERROR; + } + + flash_result = drv_flash_read(&cable_delay[0], 8, CABLE_DELAY_ADDR); + if(0 == flash_result) + { + UCP_PRINT_ERROR("read flash error\n\r"); + return OSP_ERROR; + } + + if((CABDLY_DELAY_CRC_BYTE1==cable_delay[0]) && (CABDLY_DELAY_CRC_BYTE2==cable_delay[1])) + { + memcpy(delay_time_ptr, cable_delay+2, 2); + UCP_PRINT_DEBUG("valid cable delay = %d \n",*((int16_t* )(&cable_delay[2]))); + return OSP_OK; + } + else + { + UCP_PRINT_ERROR("invalid cable delay = %x%x \n",cable_delay[0],cable_delay[1]); + return OSP_ERROR; + } +} +#endif + +int32_t drv_tfu_set_nav5_cfg(void) +{ + int32_t result = 0; + + drv_semaphore_p(g_ublox_uart.send_sem); + + g_ublox_uart.send_buf_ptr->cls_id = CFG; + g_ublox_uart.send_buf_ptr->msg_id = CFG_NAV5; + g_ublox_uart.send_buf_ptr->length = REVS16(CFG_NAV5_LEN); + g_ublox_uart.send_buf_ptr->pay_load.config_nav5.fix_mode = NAV5_FIXMODE; + g_ublox_uart.send_buf_ptr->pay_load.config_nav5.pacc = REVS16(NAV5_PACC); + g_ublox_uart.send_buf_ptr->pay_load.config_nav5.tacc = REVS16(NAV5_TACC); + + result = drv_send_ublox_msg(); + if(OSP_ERROR == result) + { + UCP_PRINT_ERROR("set nav5 cfg: send ublox msg error \n\r"); + drv_semaphore_v(g_ublox_uart.send_sem); + return OSP_ERROR; + } + drv_semaphore_v(g_ublox_uart.send_sem); + + if(OSP_OK != drv_semaphore_timed_p(g_ubx_sem[CFG_NAV5_SEM], 3*1000000)) + { + + return OSP_ERROR; + } + else + { + g_tod_link_alarm = 0; + } + return OSP_OK; +} + + +int32_t drv_tfu_set_msg_cfg(uint8_t cls, uint8_t msg, uint8_t rate) +{ + int32_t result = 0; + + drv_semaphore_p(g_ublox_uart.send_sem); + + g_ublox_uart.send_buf_ptr->cls_id = CFG; + g_ublox_uart.send_buf_ptr->msg_id = CFG_MSG; + g_ublox_uart.send_buf_ptr->length = REVS16(CFG_MSG_LEN); + g_ublox_uart.send_buf_ptr->pay_load.config_msg.cls = cls; + g_ublox_uart.send_buf_ptr->pay_load.config_msg.msgid = msg; + g_ublox_uart.send_buf_ptr->pay_load.config_msg.rate = rate; + + result = drv_send_ublox_msg(); + if(OSP_ERROR == result) + { + UCP_PRINT_ERROR("set msg cfg: send ublox msg error\n\r"); + drv_semaphore_v(g_ublox_uart.send_sem); + return OSP_ERROR; + } + + drv_semaphore_v(g_ublox_uart.send_sem); + + if(OSP_OK != drv_semaphore_timed_p(g_ubx_sem[CFG_MSG_SEM], 2*1000000)) + { + return OSP_ERROR; + } + else + { + g_tod_link_alarm = 0; + } + return OSP_OK; +} + + +int32_t drv_tfu_config_ublox(void) +{ + uint8_t i = 0; + /**/ +#if 0 + for(i=0;i<3;i++) + { + if(OSP_OK == drv_tfu_get_port_cfg()) + { + break; + } + else + { + sleep(1);/*s*/ + } + } + if(3 == i) + { + TFU_PRINTF(LTE230_PRINT_ERROR,"ublox: get port cfg error!\n"); + return OSP_ERROR; + } +//TFU_PRINTF(LTE230_PRINT_DEBUG,"get_port_cfg i=%d\n\r",i); +#endif + + tcflush(drv_uart_fd,TCIOFLUSH); + + for(i = 0; i < 3; i++) + { + if(OSP_OK == drv_tfu_set_port_cfg()) + { + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + UCP_PRINT_ERROR("ublox: set port cfg error!\n"); + //return OSP_ERROR; + } + +#if 0 + /*close name gprmc*/ + for(i = 0; i < 3; i++) + { + if(OSP_OK == drv_tfu_set_msg_cfg(NMEA, RMC,0)) + { + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + UCP_PRINT_ERROR("ublox: close name gprmc error!\n"); + g_tod_link_alarm = 1; + //return OSP_ERROR; + } + + /*close GPVTG*/ + for(i = 0; i < 3; i++) + { + if(OSP_OK == drv_tfu_set_msg_cfg(NMEA, VTG,0)) + { + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + UCP_PRINT_ERROR("ublox: close gpvtg error!\n"); + g_tod_link_alarm = 1; + //return OSP_ERROR; + } + + /*close gpgga*/ + for(i = 0; i < 3; i++) + { + if(OSP_OK == drv_tfu_set_msg_cfg(NMEA, GGA,0)) + { + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + UCP_PRINT_ERROR("ublox:close gpgga error!\n"); + g_tod_link_alarm = 1; + //return OSP_ERROR; + } + + /*close gpgsa*/ + for(i = 0; i < 3; i++) + { + if(OSP_OK == drv_tfu_set_msg_cfg(NMEA, GSA,0)) + { + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + UCP_PRINT_ERROR("ublox: close GPGSA error!\n"); + g_tod_link_alarm = 1; + //return OSP_ERROR; + } + + /*close gpgsv*/ + for(i = 0; i < 3; i++) + { + if(OSP_OK == drv_tfu_set_msg_cfg(NMEA, GSV,0)) + { + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + UCP_PRINT_ERROR("ublox: close gpgsv error!\n"); + g_tod_link_alarm = 1; + //return OSP_ERROR; + } + + /*close gpgll*/ + for(i = 0; i < 3; i++) + { + if(OSP_OK == drv_tfu_set_msg_cfg(NMEA,GLL,0)) + { + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + UCP_PRINT_ERROR("ublox: close gpgll error!\n"); + g_tod_link_alarm = 1; + //return OSP_ERROR; + } + + /*close zda*/ + for(i = 0; i < 3; i++) + { + if(OSP_OK == drv_tfu_set_msg_cfg(NMEA, ZDA,0)) + { + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + UCP_PRINT_ERROR("ublox: close gpzda error!\n"); + g_tod_link_alarm = 1; + //return OSP_ERROR; + } +#endif + /*set ant cfg*/ + for(i = 0; i < 3; i++) + { + if(OSP_OK == drv_tfu_set_ant_cfg()) + { + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + UCP_PRINT_ERROR("ublox: set ant cfg error!\n"); + g_tod_link_alarm = 1; + //return OSP_ERROR; + } + + for(i = 0; i < 3; i++) + { + if(OSP_OK == set_cable_time_delay(CABDLY_DELAY)) + { + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + UCP_PRINT_ERROR("set ublox cabdly error!\n"); + g_tod_link_alarm = 1; + //return OSP_ERROR; + } + + for(i = 0; i < 3; i++) + { + if(OSP_OK == drv_tfu_set_nav5_cfg()) + { + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + UCP_PRINT_ERROR("ublox: set nav5 cfg error!\n"); + g_tod_link_alarm = 1; + //return OSP_ERROR; + } + + /*NAV-sys_status,NAV-TIMEGPS*/ + for(i = 0; i < 3; i++) + { + if(OSP_OK == drv_tfu_set_msg_cfg(NAV, NAV_TIMEGPS,1)) + { + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + UCP_PRINT_ERROR("ublox: set msg cfg NAV, NAV TIMEGPS error!\n"); + g_tod_link_alarm = 1; + //return OSP_ERROR; + } + + for(i = 0; i < 3; i++) + { + if(OSP_OK == drv_tfu_set_msg_cfg(NAV, NAV_STATUS,1)) + { + /*clear alarm*/ + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + UCP_PRINT_ERROR("ublox: set msg cfg NAV, NAV STATUS error!\n"); + g_tod_link_alarm = 1; + + /*set alarm*/ + //return OSP_ERROR; + } +#if 0 + for(i=0;i<3;i++) + { + if(OSP_OK == drv_tfu_set_msg_cfg(NAV, NAV_SVINFO,1)) + { + /*clear alarm*/ + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + TFU_PRINTF(LTE230_PRINT_ERROR,"ublox: set msg cfg NAV, NAV SVINFO error!\n"); + g_tod_link_alarm = 1; + /*set alarm*/ + return OSP_ERROR; + } +#endif +#if 0 //20230227 + + for(i = 0; i < 3; i++) + { + if(OSP_OK == drv_tfu_set_msg_cfg(MON, MON_HW,1)) + { + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + UCP_PRINT_ERROR("ublox: set msg cfg MON, MON HW error!\n"); + g_tod_link_alarm = 1; + //return OSP_ERROR; + } +#endif +#if 0 + for(i=0;i<3;i++) + { + if(OSP_OK == drv_tfu_set_msg_cfg(NAV, NAV_POSLLH,3)) + { + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + TFU_PRINTF(LTE230_PRINT_ERROR,"ublox: set msg cfg MON, MON HW error!%\n"); + g_tod_link_alarm = 1; + return OSP_ERROR; + } +#endif +#if 0 + for(i=0;i<3;i++) + { + if(OSP_OK == drv_tfu_set_msg_cfg(NAV, NAV_SVINFO,3)) + { + break; + } + else + { + sleep(1); + } + } + if(3 == i) + { + TFU_PRINTF(LTE230_PRINT_ERROR,"ublox: set msg cfg MON, MON HW error!%\n"); + g_tod_link_alarm = 1; + return OSP_ERROR; + } +#endif + + return OSP_OK; +} + + +int32_t drv_tfu_receiver_init(void) +{ + uint32_t i = 0; + int32_t result = 0; + + if(OSP_ERROR == (g_ublox_uart.send_sem = drv_sem_create(g_sem_prj_id))) + { + UCP_PRINT_ERROR("TFU: create g_ublox_uart.send_sem error!\n"); + return OSP_ERROR; + } + UCP_PRINT_DEBUG("g_ublox_uart.send_sem=%d\n\r",g_ublox_uart.send_sem); + + g_sem_prj_id++; + for(i = 0; i < UBX_SEM_NUM; ++i) + { + if(OSP_ERROR == (g_ubx_sem[i]= drv_sem_create_sync(g_sem_prj_id++))) + { + UCP_PRINT_ERROR("drv_tfu_init semBCreate error i:%d\n\r",i); + return OSP_ERROR; + } + //g_sem_prj_id++; + } + + g_gps_recv_task_id = drv_thread_create( (uint8_t *)"dgps_recv", 72, 8192, + (void *)drv_gps_recv_task, NULL); + if(OSP_ERROR == g_gps_recv_task_id) + { + UCP_PRINT_ERROR("ublox: create GPS recv task error!\n"); + return OSP_ERROR; + } + + result = drv_tfu_config_ublox(); + if(OSP_ERROR == result) + { + UCP_PRINT_ERROR("config ublox error\n\r"); + return OSP_ERROR; + } + + return OSP_OK; +} + +int32_t drv_handle_ublox_msg(ubx_msg_s *rx_msg_ptr) +{ + uint8_t cls = 0, msg = 0; + chn_info_s* chn_info_ptr; + uint32_t i = 0; + cls = rx_msg_ptr->cls_id; + msg = rx_msg_ptr->msg_id; + UCP_PRINT_LOG("gps data cls=%#x msg=%#x msg_length=%d",cls,msg,rx_msg_ptr->length); + switch(cls) + { + case ACK: + { + switch(msg) + { + case ACK_ACK: /*ack*/ + { + switch(rx_msg_ptr->pay_load.ack_msg.msgid) + { + case CFG_PRT: + { + drv_semaphore_v(g_ubx_sem[CFG_PRT_SEM]); + UCP_PRINT_LOG("tfu: give g_ubx_sem[CFG_PRT_SEM]..."); + break; + } + case CFG_MSG: + { + drv_semaphore_v(g_ubx_sem[CFG_MSG_SEM]); + UCP_PRINT_LOG("tfu: give g_ubx_sem[CFG_MSG_SEM]..."); + break; + } + case CFG_TP5: + { + drv_semaphore_v(g_ubx_sem[CFG_TP_SEM]); + UCP_PRINT_LOG("tfu:give g_ubx_sem[CFG_TP_SEM]..."); + break; + } + case CFG_CFG: + { + drv_semaphore_v(g_ubx_sem[CFG_CFG_SEM]); + UCP_PRINT_LOG("tfu: g_ubx_sem[CFG_MSG_SEM]..."); + break; + } + case CFG_ANT: + { + drv_semaphore_v(g_ubx_sem[CFG_ANT_SEM]); + UCP_PRINT_LOG("tfu: g_ubx_sem[CFG_ANT_SEM]..."); + break; + } + case CFG_NAV5: + { + drv_semaphore_v(g_ubx_sem[CFG_NAV5_SEM]); + UCP_PRINT_LOG("tfu: g_ubx_sem[CFG_NAV5_SEM]..."); + break; + } + case CFG_RST: + { + drv_semaphore_v(g_ubx_sem[CFG_RST_SEM]); + UCP_PRINT_LOG("tfu: g_ubx_sem[CFG_RST_SEM]..."); + break; + } + default: + { + UCP_PRINT_ERROR("tfu: unknown msg ack! msgid:%d\n",rx_msg_ptr->pay_load.ack_msg.msgid); + break; + } + }/*switch(g_rx_buf_ptr->pay_load.ack_msg.msgid)*/ + break; + } + case ACK_NACK:/*nack*/ + { + UCP_PRINT_ERROR("ack_nack!!!"); + return OSP_ERROR; + } + default: + { + UCP_PRINT_ERROR("not ack, not nack msgid:%d\n\r",msg); + return OSP_ERROR; + } + }/*switch(msg)*/ + break; + } + case NAV: + { + switch(msg) + { + case NAV_POSLLH: + g_gps_recv_msg.altitude = REVS32(rx_msg_ptr->pay_load.nav_pos.height); + g_gps_recv_msg.latitude = REVS32(rx_msg_ptr->pay_load.nav_pos.lat); + g_gps_recv_msg.longitude = REVS32(rx_msg_ptr->pay_load.nav_pos.lon); + UCP_PRINT_LOG("gps altitude=%d lat=%d lon=%d\n\r",g_gps_recv_msg.altitude,g_gps_recv_msg.latitude,g_gps_recv_msg.longitude); + drv_semaphore_v(g_ubx_sem[NAV_POSLLH_SEM]); + break; + case NAV_STATUS: + g_gps_recv_msg.lock_state = rx_msg_ptr->pay_load.nav_status.flags & 0x1; + g_gps_recv_msg.gps_fix = rx_msg_ptr->pay_load.nav_status.gps_fix; + g_gps_recv_msg.fix_flag = rx_msg_ptr->pay_load.nav_status.flags; + g_gps_recv_msg.time_of_week = REVS32(rx_msg_ptr->pay_load.nav_status.i_tow) / 1000; + UCP_PRINT_LOG("gps lock_state=%d,time_of_week=%d",g_gps_recv_msg.lock_state,g_gps_recv_msg.time_of_week); + break; + case NAV_TIMEGPS: + g_gps_recv_msg.valid_flag = rx_msg_ptr->pay_load.nav_timegps.valid; + if(g_gps_recv_msg.valid_flag & (0x1 << 2)) + { + g_gps_recv_msg.leap_sec = rx_msg_ptr->pay_load.nav_timegps.leap; + } + g_gps_recv_msg.week_number = REVS16(rx_msg_ptr->pay_load.nav_timegps.week); + UCP_PRINT_LOG("week_number=%d",g_gps_recv_msg.week_number); + //drv_semaphore_v(g_ubx_sem[NAV_GPSTIME_SEM]); + break; + + case NAV_SVINFO: + g_gps_recv_msg.num_ch = rx_msg_ptr->pay_load.nav_svinfo.num_ch; + chn_info_ptr = (chn_info_s*)(&rx_msg_ptr->pay_load.nav_svinfo.chn_info); + memset(g_gps_recv_msg.sta_id, 0, sizeof(g_gps_recv_msg.sta_id)); + memset(g_gps_recv_msg.cno, 0, sizeof(g_gps_recv_msg.cno)); + g_gps_recv_msg.tracking_num = 0; + g_gps_recv_msg.visable_num = 0; + g_almanach_flag = 0; + for(i = 0; i < g_gps_recv_msg.num_ch; i++) + { + int32_t j = 0, k = 0; + g_almanach_flag |= (chn_info_ptr+i)->flags; + if((chn_info_ptr+i)->cno > 0) + { + g_gps_recv_msg.visable_num++; + g_gps_recv_msg.sta_id[i] = (chn_info_ptr+i)->svid; + j++; + g_gps_recv_msg.cno[i] = (chn_info_ptr+i)->cno; + if(g_gps_recv_msg.cno[i] > 25) + { + g_gps_recv_msg.tracking_num++; + /*if(g_gps_recv_msg.cno[i] > 50) + { + g_gps_recv_msg.sig_over_high++; + }*/ + } + k++; + } + UCP_PRINT_DEBUG("i=%d chn=%d svid=%d flags=%d",i,(chn_info_ptr+i)->chn,(chn_info_ptr+i)->svid,(chn_info_ptr+i)->flags); + UCP_PRINT_DEBUG("cno=%d elev=%d azim=%d prres=%d\n\r",(chn_info_ptr+i)->cno,(chn_info_ptr+i)->elev,(chn_info_ptr+i)->azim,(chn_info_ptr+i)->prres); + } + UCP_PRINT_DEBUG("tracking_num:%d visable_num:%d\n\r",g_gps_recv_msg.tracking_num,g_gps_recv_msg.visable_num); + UCP_PRINT_DEBUG("tfu lock_flag=%#x num_ch=%d\n\r",g_gps_recv_msg.fix_flag,g_gps_recv_msg.num_ch); + + drv_semaphore_v(g_ubx_sem[NAV_SVINFO_SEM]); + break; + default:break; + } + break; + } + case CFG: + { + switch(msg) + { + case CFG_PRT: + UCP_PRINT_DEBUG("tfu: mode: %x.\n",REVS32(rx_msg_ptr->pay_load.config_port.mode)); + UCP_PRINT_DEBUG("tfu: baudrate: %x.\n",REVS32(rx_msg_ptr->pay_load.config_port.baudrate)); + UCP_PRINT_DEBUG("tfu: inportmask: %x.\n",REVS16(rx_msg_ptr->pay_load.config_port.inportmask)); + UCP_PRINT_DEBUG("tfu: outportmask: %x.\n",REVS16(rx_msg_ptr->pay_load.config_port.outportmask)); + break; + case CFG_MSG: + + break; + case CFG_TP5: + g_gps_recv_msg.cab_dly = REVS16(rx_msg_ptr->pay_load.config_tp5.cab_dly); + g_gps_recv_msg.pulse_width = REVS32(rx_msg_ptr->pay_load.config_tp5.freq_period_locked); + g_gps_recv_msg.pps_status = rx_msg_ptr->pay_load.config_tp5.polarity; + break; + case CFG_ANT: + UCP_PRINT_DEBUG("cfg ant: flags: %x.\n",REVS32(rx_msg_ptr->pay_load.config_ant.flags)); + UCP_PRINT_DEBUG("cfg ant: pins: %x.\n",REVS32(rx_msg_ptr->pay_load.config_ant.pins)); + drv_semaphore_v(g_ubx_sem[CFG_ANT_SEM]); + break; + case CFG_RST: + UCP_PRINT_DEBUG("tfu:CFG.... CFG_RST\n"); + break; + default: + break; + }/*switch(msg) CFG*/ + break; + } + case MON: + { + switch(msg) + { + case MON_HW: + g_gps_recv_msg.ant_state = rx_msg_ptr->pay_load.monitor_hw.astatus; +#if 0 + if (ANT_OPEN_ALARM_VALUE == g_gps_recv_msg.ant_state) + { + /*dingyi*/ + g_monitor_alarms |= (0x01 << 2); /*short*/ + } + if (ANT_SHORT_ALARM_VALUE == g_gps_recv_msg.ant_state) + { + g_monitor_alarms |= (0x01 << 1); /*open*/ + } +#endif + //drv_semaphore_v(g_ubx_sem[MON_HW_SEM]); + break; + + case MON_VER: + memset(g_gps_recv_msg.sw_version, 0, sizeof(g_gps_recv_msg.sw_version)); + memset(g_gps_recv_msg.hw_version, 0, sizeof(g_gps_recv_msg.hw_version)); + memcpy(g_gps_recv_msg.sw_version,rx_msg_ptr->pay_load.monitor_ver.sw_version,sizeof(g_gps_recv_msg.sw_version)); + memcpy(g_gps_recv_msg.hw_version,rx_msg_ptr->pay_load.monitor_ver.hw_version,sizeof(g_gps_recv_msg.hw_version)); + + break; + + default: + UCP_PRINT_DEBUG("tfu: unknown MON msg: %x.\n", msg); + break; + }/*switch(msg) mon*/ + break; + } + default: + { + UCP_PRINT_DEBUG("tfu: unknown cls: %x.\n", cls); + break; + } + } + return OSP_OK; +} + + +int32_t drv_tfu_get_ublox_seconds(time_t* sec_ptr) +{ + struct tm time_base = {0,0,0,6,0,80,0,0,0}; + if(NULL == sec_ptr) + { + UCP_PRINT_ERROR("tfu: get_ublox_seconds error -1.\n"); + return OSP_ERROR; + } + + /*time of week and week number are valid*/ + if(TIME_VALID != (TIME_VALID & g_gps_recv_msg.valid_flag)) + { + //UCP_PRINT_ERROR("tfu: time is invalid! %x.\n", g_gps_recv_msg.valid_flag); + return OSP_ERROR; + } + + /* *sec_ptr = mktime(1980,1,6,0,0,0)+ \ */ + *sec_ptr = mktime(&time_base)+ \ + GPS_SECONDS(g_gps_recv_msg.time_of_week, g_gps_recv_msg.week_number); + return OSP_OK; +} + +void deal_gps_data(void) +{ + int32_t i = 0,len,len_left = 0,check_len = 0; + uint8_t *head_ptr; + ubx_msg_s *rx_msg_ptr; + ublox_uart_s *uart_ptr = &g_ublox_uart; + uint8_t ck_a = 0, ck_b = 0; + + //memset(&uart_ptr->recv_buf[uart_ptr->recv_ptr],0x0,255); + uart_ptr->recv_cnt = drv_uart_read(&uart_ptr->recv_buf[uart_ptr->recv_ptr],HALF_BUFSIZE); + if(uart_ptr->recv_cnt <= 0) + { + UCP_PRINT_ERROR("uart read error"); + return; + } + + //uart_ptr->deal_ptr = 0; + len = uart_ptr->recv_cnt + uart_ptr->deal_cnt; //本次接收+上次遗留的长度 + //uart_ptr->recv_buf[len] = '\0'; + //len_left = len; + + while(uart_ptr->deal_ptr < len) //maybe more than one message + { + if(SYNC1_UBLOX == uart_ptr->recv_buf[uart_ptr->deal_ptr++]) + { + if(SYNC2_UBLOX == uart_ptr->recv_buf[uart_ptr->deal_ptr]) + { + uart_ptr->deal_ptr--; + uart_ptr->frame_flag = 1; //search frame header ok! + head_ptr = &uart_ptr->recv_buf[uart_ptr->deal_ptr + UBLOX_SYNC_LEN]; //class_id + } + else + { + continue; + } + } + else + { + uart_ptr->frame_flag = 0; + continue; + } + + len_left = len - uart_ptr->deal_ptr; + if(len_left >= INDEX_OF_PAYLOAD) + { + rx_msg_ptr = (ubx_msg_s*)head_ptr; + } + else //the last 6 bytes + { + //memcpy(&uart_ptr->recv_buf[0],&uart_ptr->recv_buf[uart_ptr->deal_ptr],len_left); + uart_ptr->deal_cnt = len_left; + uart_ptr->recv_ptr += uart_ptr->recv_cnt; + UCP_PRINT_DEBUG("Len of header is not enougth,len_left = %d,recv_ptr = %d,deal_ptr = %d",len_left,uart_ptr->recv_ptr,uart_ptr->deal_ptr); + if(uart_ptr->recv_ptr > HALF_BUFSIZE) + { + memcpy(&uart_ptr->recv_buf[0],&uart_ptr->recv_buf[uart_ptr->deal_ptr],len_left); + uart_ptr->recv_ptr = len_left; + } + return; + } +#if 0 + if(rx_msg_ptr->length > UBLOX_MAX_MEG_LENGTH) + { + UCP_PRINT_ERROR("msg len error len = %d ",rx_msg_ptr->length); + //*(uint16_t *)head_ptr = 0; clean sync + uart_ptr->deal_ptr += INDEX_OF_PAYLOAD; + continue;//data len error + } +#endif + if(rx_msg_ptr->length + UBLOX_HEADER_SUM_LEN > len_left) //message segment + { + UCP_PRINT_DEBUG("payload_len = %d,total_len = %d,left_len = %d,recv_ptr = %d,deal_ptr = %d,packet_len = %d",\ + rx_msg_ptr->length,len,len_left,uart_ptr->recv_ptr,uart_ptr->deal_ptr,uart_ptr->recv_cnt); + + uart_ptr->deal_cnt = len_left; + uart_ptr->recv_ptr += uart_ptr->recv_cnt; + if(uart_ptr->recv_ptr > HALF_BUFSIZE) + { + memcpy(&uart_ptr->recv_buf[0],&uart_ptr->recv_buf[uart_ptr->deal_ptr],len_left); + uart_ptr->recv_ptr = len_left; + } + //UCP_PRINT_DEBUG("next recv_ptr = %d\n",uart_ptr->recv_ptr); + return;/*data len error*/ + } + + /*check the msg */ + ck_a = 0; + ck_b = 0; + check_len = rx_msg_ptr->length + 4; + for(i = 0; i < check_len; i++) //check sum: (class_id + msg_id + len + payload) + { + ck_a += *head_ptr++; + ck_b += ck_a; + } + + uart_ptr->deal_ptr += UBLOX_MSG_TOTAL_LEN(rx_msg_ptr->length); //header of next message + + if((ck_a == *head_ptr++) && (ck_b == *head_ptr)) + { + if(OSP_OK != drv_handle_ublox_msg(rx_msg_ptr)) + { + UCP_PRINT_ERROR("handle ublox msg error"); + //continue; + } + } + else + { + UCP_PRINT_ERROR("ublox crc error"); + //continue; + } + } + + uart_ptr->deal_ptr = 0; + + if(0 == uart_ptr->frame_flag) + { + // UCP_PRINT_ERROR("cann't find ublox header"); + //uart_ptr->recv_ptr = 0; + if(SYNC1_UBLOX == uart_ptr->recv_buf[len - 1]) + { + uart_ptr->recv_buf[0] = SYNC1_UBLOX; + uart_ptr->deal_cnt = 1; + uart_ptr->recv_ptr = 1; + return; + } + } + + uart_ptr->recv_ptr = 0; + uart_ptr->deal_cnt = 0; + return; +} + +void drv_gps_recv_task(void) +{ + while(1) + { + deal_gps_data(); + } +} + +int32_t drv_tfu_uart_init(void) +{ + if(drv_uart_fd < 0) + { + drv_uart_fd = open( "/dev/ttyS2", O_RDWR); + if (-1 == drv_uart_fd) + { + perror("Can't Open Serial Port"); + UCP_PRINT_ERROR("Can't Open Serial Port\n\r"); + return OSP_ERROR; + } + } + + if(fcntl(drv_uart_fd, F_SETFL, 0)<0) + { + UCP_PRINT_ERROR("fcntl failed!\n"); + } + + if(isatty(STDIN_FILENO) == 0) + { + UCP_PRINT_ERROR("standard input is not a terminal device\n"); + } + + if(set_opt(drv_uart_fd,9600,8,'N',1) < 0) + { + perror("set_opt error"); + UCP_PRINT_ERROR("set_opt error\n\r"); + return OSP_ERROR; + } + return OSP_OK; +} + +int32_t drv_uart_read(uint8_t *pdata, uint32_t len) +{ + int32_t read_bytes = 0; + + if(NULL == pdata) + { + return OSP_ERROR; + } + + read_bytes = read(drv_uart_fd,pdata,len); + if(read_bytes < 0) + { + // UCP_PRINT_ERROR("uart read error\n\r"); + return OSP_ERROR; + } + + return read_bytes; +} + +int32_t get_receiver_fix_status() +{ + return g_gps_recv_msg.lock_state; //接收机锁定状态 +} + +int32_t reset_clock_module(void) +{ + + (void)drv_semaphore_p(g_ublox_uart.send_sem); + + g_ublox_uart.send_buf_ptr->cls_id = CFG; + g_ublox_uart.send_buf_ptr->msg_id = CFG_RST; + g_ublox_uart.send_buf_ptr->length = REVS16(CFG_RST_LEN); + + g_ublox_uart.send_buf_ptr->pay_load.config_rst.nav_bbr = REVS16(RST_NAVBBR_COLD); + g_ublox_uart.send_buf_ptr->pay_load.config_rst.rst_mode = RST_MODE_HW; + + drv_send_ublox_msg(); + drv_semaphore_v(g_ublox_uart.send_sem); + + if(OSP_OK != drv_tfu_config_ublox()) + { + UCP_PRINT_ERROR("tfu: config_ublox error!"); + return OSP_ERROR; + } + return OSP_OK; +} + +int32_t get_src_time(time_t* time_ptr) +{ + time_t tmp_time; + if(NULL == time_ptr) + { + UCP_PRINT_ERROR("tfu: get_src_time *time_prt is null!\n"); + return OSP_ERROR; + } + if(OSP_OK != drv_tfu_get_ublox_seconds(&tmp_time)) + { + UCP_PRINT_ERROR("tfu: get gps time error !\n"); + return OSP_ERROR; + } + *time_ptr = tmp_time; + return OSP_OK; +} + + +int32_t get_leap_time(uint8_t* leap_ptr) +{ + + if(NULL == leap_ptr) + { + UCP_PRINT_ERROR("tfu: get_leap_time *leap_ptr is null!\n"); + return OSP_ERROR; + } + + if(LEAP_VALID != (LEAP_VALID & g_gps_recv_msg.valid_flag)) + { + *leap_ptr = 19; + return OSP_OK; + } + + *leap_ptr = g_gps_recv_msg.leap_sec; + return OSP_OK; +} + + +int32_t get_tfu_location_info(location_info_s *locat_ptr) +{ + if(NULL == locat_ptr) + { + UCP_PRINT_ERROR("locat_ptr == NULL\n\r"); + return OSP_ERROR; + } + (void)drv_semaphore_p(g_ublox_uart.send_sem); + g_ublox_uart.send_buf_ptr->cls_id = NAV; + g_ublox_uart.send_buf_ptr->msg_id = NAV_POSLLH; + g_ublox_uart.send_buf_ptr->length = POLL_LENGTH; + + drv_send_ublox_msg(); + drv_semaphore_v(g_ublox_uart.send_sem); + if(OSP_OK != drv_semaphore_timed_p(g_ubx_sem[NAV_POSLLH_SEM], 2*1000000)) + { + UCP_PRINT_ERROR("tfu: no position info back!\n"); + g_tod_link_alarm = 1; + return OSP_ERROR; + } + else + { + g_tod_link_alarm = 0; + } + + locat_ptr->altitude = g_gps_recv_msg.altitude; + locat_ptr->latitude = g_gps_recv_msg.latitude; + locat_ptr->longitude = g_gps_recv_msg.longitude; + + return OSP_OK; +} + +int32_t get_clock_tracking_state(tracking_info_s *trk_ptr) +{ + uint8_t i; + float* sig_level_ptr; + + if(NULL == trk_ptr) + { + UCP_PRINT_ERROR("trk_ptr == NULL\n\r"); + return OSP_ERROR; + } + + sig_level_ptr = trk_ptr->sig_level; + if(-1 == g_ublox_uart.send_sem) + { + return OSP_ERROR; + } + (void)drv_semaphore_p(g_ublox_uart.send_sem); + g_ublox_uart.send_buf_ptr->cls_id = NAV; + g_ublox_uart.send_buf_ptr->msg_id = NAV_SVINFO; + g_ublox_uart.send_buf_ptr->length = POLL_LENGTH; + + drv_send_ublox_msg(); + drv_semaphore_v(g_ublox_uart.send_sem); + if(OSP_OK != drv_semaphore_timed_p(g_ubx_sem[NAV_SVINFO_SEM], 3*1000000)) + { + UCP_PRINT_ERROR("tfu: no sv info back! \n"); + g_tod_link_alarm = 1; + return OSP_ERROR; + } + else + { + g_tod_link_alarm = 0; + } + if(g_gps_recv_msg.fix_flag & GPS_FIX_OK) + { + trk_ptr->lock_flag = 1; + } + else + { + trk_ptr->lock_flag = 0; + } + + if(g_gps_recv_msg.valid_flag & LEAP_VALID) + { + trk_ptr->leap_valid = 1; + } + else + { + trk_ptr->leap_valid = 0; + } + if(g_almanach_flag & NAV_ALMANACH) + { + trk_ptr->alma_complete = 1; + } + else + { + trk_ptr->alma_complete = 0; + } + trk_ptr->view_sats = g_gps_recv_msg.visable_num; + trk_ptr->track_sats = g_gps_recv_msg.tracking_num; + trk_ptr->survey_in = 0; + + for(i = 0; i < MIN(g_gps_recv_msg.visable_num,12); ++i) + { + *(sig_level_ptr++) = (float)g_gps_recv_msg.cno[i]; + } + //get_ad9548_lock_status(&phase_diff); + //trk_ptr->pahse_diff = (int16_t)phase_diff; + for(i = 0; i < MIN(g_gps_recv_msg.visable_num,12); i++) + { + UCP_PRINT_DEBUG(" %f",trk_ptr->sig_level[i]); + } + + UCP_PRINT_DEBUG("get_clock_tracking_state: lock_flag=%d leap_valid=%d view_sats=%d\n\r",trk_ptr->lock_flag,trk_ptr->leap_valid,trk_ptr->view_sats); + //UCP_PRINT_DEBUG"get_clock_tracking_state: track_sat=%d phase_diff=%d\n\r",trk_ptr->track_sats,trk_ptr->pahse_diff); + + + return OSP_OK; +} + +#if 0 +int32_t get_clock_module_status(clk_modu_state_s* clk_modu_state_ptr) +{ + + if(NULL == clk_modu_state_ptr) + { + UCP_PRINT_ERROR("clk_modu_state_ptr == NULL\n\r"); + return OSP_ERROR; + } + memset((void *)clk_modu_state_ptr, 0, sizeof(clk_modu_state_s)); + + /* ------------get common_alarm -----------------------*/ + if(CLK_DISABLE == g_sync_state ) + { + clk_modu_state_ptr->common_alarm |= COM_CLK_DISABLE_ALARM; + } + + /*-- if phase diff over, set bit2-- */ + if(g_phase_over_flow) + { + clk_modu_state_ptr->common_alarm |= COM_PHASE_DIFF_OVER_ALARM; + } + /*-- if hold over, set bit3 --*/ + if(CLK_HOLD_OVER == g_sync_state) + clk_modu_state_ptr->common_alarm |= COM_HOLD_OVER_STATE_ALARM; + + /*-- if gps/bd tod link alarm, set bit4-- */ + if(g_tod_link_alarm) + { + clk_modu_state_ptr->common_alarm |= COM_TOD_LINK_ALARM; + } + + /* ---------------get clk_gps_alarm --------------------*/ + + /*--set TOD channel alarm, bit2-- */ + if(TOD_LINK_ALARM_VALUE == g_gps_recv_msg.ant_state) + { + clk_modu_state_ptr->clk_gps_alarm |= GPS_LINK_CHAN_FAULT_ALARM; + } + + /* --set antenna short alarm-- */ + if(ANT_OPEN_ALARM_VALUE == g_gps_recv_msg.ant_state) + { + clk_modu_state_ptr->clk_gps_alarm |= GPS_ANT_OPEN_ALARM; + } + + /* --set antenna open alarm-- */ + if(ANT_SHORT_ALARM_VALUE == g_gps_recv_msg.ant_state) + { + clk_modu_state_ptr->clk_gps_alarm |= GPS_ANT_SHORT_ALARM; + } + + /* --set siglever too week alarm-- */ + if(g_gps_recv_msg.tracking_num < 3) + { + clk_modu_state_ptr->clk_gps_alarm |= GPS_ANT_SIGNAL_WEEK_ALARM; + } + /* --set siglever too strong alarm-- */ + if(g_gps_recv_msg.sig_over_high > 0) + { + clk_modu_state_ptr->clk_gps_alarm |= GPS_ANT_SIGNAL_STRONG_ALARM; + } + + /*-------------- get clk_forced_flag ---------------------*/ + clk_modu_state_ptr->clk_forced_flag = g_force_flag; + + /*------------- get clk_pesudo_flag ----------------------*/ + clk_modu_state_ptr->clk_pesudo_flag = g_pesudo_lock; + + /*--------------- get sync state -----------------------*/ + if(g_pesudo_lock) + { + clk_modu_state_ptr->clk_sync = CLK_TRACKING; + clk_modu_state_ptr->common_alarm &= ~COM_CLK_DISABLE_ALARM; + } + else + { + clk_modu_state_ptr->clk_sync = g_sync_state; + } + + if(1 == g_gps_recv_msg.lock_state) + { + clk_modu_state_ptr->clk_gps_locked_flag = TRUE_FLAG; + } + else + { + clk_modu_state_ptr->clk_gps_locked_flag = ZERO_FLAG; + } + + /*------------ get hold_over_time ---------------------*/ + clk_modu_state_ptr->hold_over_time = g_hold_over_time/HOLD_OVER_TIME_UNIT; + + /* ----------------get clk_src ------------------------*/ + clk_modu_state_ptr->clk_src = CLK_SRC_GPS; + + return OSP_OK; +} +#endif +int32_t init_clock_module(void) +{ + int32_t result = 0; + + if(1 == g_tfu_init_flag) + { + UCP_PRINT_ERROR("tfu init flag = 1"); + return OSP_ERROR; + } + else + { + result = drv_tfu_uart_init(); + if(OSP_ERROR == result) + { + UCP_PRINT_ERROR("uart init error\n\r"); + return OSP_ERROR; + } + + /*tracking后释放给OM，计算帧号*/ + if(OSP_ERROR == (g_tfu_to_time_sem = drv_sem_create(g_sem_prj_id))) + { + UCP_PRINT_ERROR("g_tfu_to_time_sem create error\n\r"); + return OSP_ERROR; + } + UCP_PRINT_DEBUG("g_tfu_to_time_sem=%d\n\r",g_tfu_to_time_sem); + + g_sem_prj_id++; + if(OSP_ERROR == (g_tfu_sync_sem = drv_sem_create_sync(g_sem_prj_id))) + { + UCP_PRINT_ERROR("g_tfu_sync_sem create error\n\r"); + return OSP_ERROR; + } + g_sem_prj_id++; + UCP_PRINT_DEBUG("g_tfu_sync_sem=%d\n\r",g_tfu_sync_sem); + + g_tfu_init_flag = 1; + return OSP_OK; + } +} +